drivers/iommu/intel-svm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright © 2015 Intel Corporation.
   4  *
   5  * Authors: David Woodhouse <dwmw2@infradead.org>
   6  */
   7
   8 #include <linux/intel-iommu.h>
   9 #include <linux/mmu_notifier.h>
  10 #include <linux/sched.h>
  11 #include <linux/sched/mm.h>
  12 #include <linux/slab.h>
  13 #include <linux/intel-svm.h>
  14 #include <linux/rculist.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci-ats.h>
  17 #include <linux/dmar.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/mm_types.h>
  20 #include <asm/page.h>
  21
  22 #include "intel-pasid.h"
  23
  24 static irqreturn_t prq_event_thread(int irq, void *d);
  25
  26 #define PRQ_ORDER 0
  27
  28 int intel_svm_enable_prq(struct intel_iommu *iommu)
  29 {
  30         struct page *pages;
  31         int irq, ret;
  32
  33         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
  34         if (!pages) {
  35                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
  36                         iommu->name);
  37                 return -ENOMEM;
  38         }
  39         iommu->prq = page_address(pages);
  40
  41         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
  42         if (irq <= 0) {
  43                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
  44                        iommu->name);
  45                 ret = -EINVAL;
  46         err:
  47                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
  48                 iommu->prq = NULL;
  49                 return ret;
  50         }
  51         iommu->pr_irq = irq;
  52
  53         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
  54
  55         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
  56                                    iommu->prq_name, iommu);
  57         if (ret) {
  58                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
  59                        iommu->name);
  60                 dmar_free_hwirq(irq);
  61                 iommu->pr_irq = 0;
  62                 goto err;
  63         }
  64         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  65         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  66         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
  67
  68         return 0;
  69 }
  70
  71 int intel_svm_finish_prq(struct intel_iommu *iommu)
  72 {
  73         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  74         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  75         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
  76
  77         if (iommu->pr_irq) {
  78                 free_irq(iommu->pr_irq, iommu);
  79                 dmar_free_hwirq(iommu->pr_irq);
  80                 iommu->pr_irq = 0;
  81         }
  82
  83         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
  84         iommu->prq = NULL;
  85
  86         return 0;
  87 }
  88
  89 static inline bool intel_svm_capable(struct intel_iommu *iommu)
  90 {
  91         return iommu->flags & VTD_FLAG_SVM_CAPABLE;
  92 }
  93
  94 void intel_svm_check(struct intel_iommu *iommu)
  95 {
  96         if (!pasid_supported(iommu))
  97                 return;
  98
  99         if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
 100             !cap_fl1gp_support(iommu->cap)) {
 101                 pr_err("%s SVM disabled, incompatible 1GB page capability\n",
 102                        iommu->name);
 103                 return;
 104         }
 105
 106         if (cpu_feature_enabled(X86_FEATURE_LA57) &&
 107             !cap_5lp_support(iommu->cap)) {
 108                 pr_err("%s SVM disabled, incompatible paging mode\n",
 109                        iommu->name);
 110                 return;
 111         }
 112
 113         iommu->flags |= VTD_FLAG_SVM_CAPABLE;
 114 }
 115
 116 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 117                                 unsigned long address, unsigned long pages, int ih)
 118 {
 119         struct qi_desc desc;
 120
 121         if (pages == -1) {
 122                 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 123                         QI_EIOTLB_DID(sdev->did) |
 124                         QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
 125                         QI_EIOTLB_TYPE;
 126                 desc.qw1 = 0;
 127         } else {
 128                 int mask = ilog2(__roundup_pow_of_two(pages));
 129
 130                 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 131                                 QI_EIOTLB_DID(sdev->did) |
 132                                 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
 133                                 QI_EIOTLB_TYPE;
 134                 desc.qw1 = QI_EIOTLB_ADDR(address) |
 135                                 QI_EIOTLB_IH(ih) |
 136                                 QI_EIOTLB_AM(mask);
 137         }
 138         desc.qw2 = 0;
 139         desc.qw3 = 0;
 140         qi_submit_sync(&desc, svm->iommu);
 141
 142         if (sdev->dev_iotlb) {
 143                 desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
 144                                 QI_DEV_EIOTLB_SID(sdev->sid) |
 145                                 QI_DEV_EIOTLB_QDEP(sdev->qdep) |
 146                                 QI_DEIOTLB_TYPE;
 147                 if (pages == -1) {
 148                         desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) |
 149                                         QI_DEV_EIOTLB_SIZE;
 150                 } else if (pages > 1) {
 151                         /* The least significant zero bit indicates the size. So,
 152                          * for example, an "address" value of 0x12345f000 will
 153                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 154                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 155                         unsigned long mask = __rounddown_pow_of_two(address ^ last);
 156
 157                         desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) |
 158                                         (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 159                 } else {
 160                         desc.qw1 = QI_DEV_EIOTLB_ADDR(address);
 161                 }
 162                 desc.qw2 = 0;
 163                 desc.qw3 = 0;
 164                 qi_submit_sync(&desc, svm->iommu);
 165         }
 166 }
 167
 168 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 169                                 unsigned long pages, int ih)
 170 {
 171         struct intel_svm_dev *sdev;
 172
 173         rcu_read_lock();
 174         list_for_each_entry_rcu(sdev, &svm->devs, list)
 175                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih);
 176         rcu_read_unlock();
 177 }
 178
 179 /* Pages have been freed at this point */
 180 static void intel_invalidate_range(struct mmu_notifier *mn,
 181                                    struct mm_struct *mm,
 182                                    unsigned long start, unsigned long end)
 183 {
 184         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 185
 186         intel_flush_svm_range(svm, start,
 187                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0);
 188 }
 189
 190 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 191 {
 192         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 193         struct intel_svm_dev *sdev;
 194
 195         /* This might end up being called from exit_mmap(), *before* the page
 196          * tables are cleared. And __mmu_notifier_release() will delete us from
 197          * the list of notifiers so that our invalidate_range() callback doesn't
 198          * get called when the page tables are cleared. So we need to protect
 199          * against hardware accessing those page tables.
 200          *
 201          * We do it by clearing the entry in the PASID table and then flushing
 202          * the IOTLB and the PASID table caches. This might upset hardware;
 203          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 204          * page) so that we end up taking a fault that the hardware really
 205          * *has* to handle gracefully without affecting other processes.
 206          */
 207         rcu_read_lock();
 208         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 209                 intel_pasid_tear_down_entry(svm->iommu, sdev->dev, svm->pasid);
 210                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
 211         }
 212         rcu_read_unlock();
 213
 214 }
 215
 216 static const struct mmu_notifier_ops intel_mmuops = {
 217         .release = intel_mm_release,
 218         .invalidate_range = intel_invalidate_range,
 219 };
 220
 221 static DEFINE_MUTEX(pasid_mutex);
 222 static LIST_HEAD(global_svm_list);
 223
 224 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 225 {
 226         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 227         struct device_domain_info *info;
 228         struct intel_svm_dev *sdev;
 229         struct intel_svm *svm = NULL;
 230         struct mm_struct *mm = NULL;
 231         int pasid_max;
 232         int ret;
 233
 234         if (!iommu || dmar_disabled)
 235                 return -EINVAL;
 236
 237         if (!intel_svm_capable(iommu))
 238                 return -ENOTSUPP;
 239
 240         if (dev_is_pci(dev)) {
 241                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 242                 if (pasid_max < 0)
 243                         return -EINVAL;
 244         } else
 245                 pasid_max = 1 << 20;
 246
 247         if (flags & SVM_FLAG_SUPERVISOR_MODE) {
 248                 if (!ecap_srs(iommu->ecap))
 249                         return -EINVAL;
 250         } else if (pasid) {
 251                 mm = get_task_mm(current);
 252                 BUG_ON(!mm);
 253         }
 254
 255         mutex_lock(&pasid_mutex);
 256         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 257                 struct intel_svm *t;
 258
 259                 list_for_each_entry(t, &global_svm_list, list) {
 260                         if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
 261                                 continue;
 262
 263                         svm = t;
 264                         if (svm->pasid >= pasid_max) {
 265                                 dev_warn(dev,
 266                                          "Limited PASID width. Cannot use existing PASID %d\n",
 267                                          svm->pasid);
 268                                 ret = -ENOSPC;
 269                                 goto out;
 270                         }
 271
 272                         list_for_each_entry(sdev, &svm->devs, list) {
 273                                 if (dev == sdev->dev) {
 274                                         if (sdev->ops != ops) {
 275                                                 ret = -EBUSY;
 276                                                 goto out;
 277                                         }
 278                                         sdev->users++;
 279                                         goto success;
 280                                 }
 281                         }
 282
 283                         break;
 284                 }
 285         }
 286
 287         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 288         if (!sdev) {
 289                 ret = -ENOMEM;
 290                 goto out;
 291         }
 292         sdev->dev = dev;
 293
 294         ret = intel_iommu_enable_pasid(iommu, dev);
 295         if (ret || !pasid) {
 296                 /* If they don't actually want to assign a PASID, this is
 297                  * just an enabling check/preparation. */
 298                 kfree(sdev);
 299                 goto out;
 300         }
 301
 302         info = dev->archdata.iommu;
 303         if (!info || !info->pasid_supported) {
 304                 kfree(sdev);
 305                 goto out;
 306         }
 307
 308         sdev->did = FLPT_DEFAULT_DID;
 309         sdev->sid = PCI_DEVID(info->bus, info->devfn);
 310         if (info->ats_enabled) {
 311                 sdev->dev_iotlb = 1;
 312                 sdev->qdep = info->ats_qdep;
 313                 if (sdev->qdep >= QI_DEV_EIOTLB_MAX_INVS)
 314                         sdev->qdep = 0;
 315         }
 316
 317         /* Finish the setup now we know we're keeping it */
 318         sdev->users = 1;
 319         sdev->ops = ops;
 320         init_rcu_head(&sdev->rcu);
 321
 322         if (!svm) {
 323                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 324                 if (!svm) {
 325                         ret = -ENOMEM;
 326                         kfree(sdev);
 327                         goto out;
 328                 }
 329                 svm->iommu = iommu;
 330
 331                 if (pasid_max > intel_pasid_max_id)
 332                         pasid_max = intel_pasid_max_id;
 333
 334                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 335                 ret = intel_pasid_alloc_id(svm,
 336                                            !!cap_caching_mode(iommu->cap),
 337                                            pasid_max, GFP_KERNEL);
 338                 if (ret < 0) {
 339                         kfree(svm);
 340                         kfree(sdev);
 341                         goto out;
 342                 }
 343                 svm->pasid = ret;
 344                 svm->notifier.ops = &intel_mmuops;
 345                 svm->mm = mm;
 346                 svm->flags = flags;
 347                 INIT_LIST_HEAD_RCU(&svm->devs);
 348                 INIT_LIST_HEAD(&svm->list);
 349                 ret = -ENOMEM;
 350                 if (mm) {
 351                         ret = mmu_notifier_register(&svm->notifier, mm);
 352                         if (ret) {
 353                                 intel_pasid_free_id(svm->pasid);
 354                                 kfree(svm);
 355                                 kfree(sdev);
 356                                 goto out;
 357                         }
 358                 }
 359
 360                 spin_lock(&iommu->lock);
 361                 ret = intel_pasid_setup_first_level(iommu, dev,
 362                                 mm ? mm->pgd : init_mm.pgd,
 363                                 svm->pasid, FLPT_DEFAULT_DID,
 364                                 mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
 365                 spin_unlock(&iommu->lock);
 366                 if (ret) {
 367                         if (mm)
 368                                 mmu_notifier_unregister(&svm->notifier, mm);
 369                         intel_pasid_free_id(svm->pasid);
 370                         kfree(svm);
 371                         kfree(sdev);
 372                         goto out;
 373                 }
 374
 375                 list_add_tail(&svm->list, &global_svm_list);
 376         } else {
 377                 /*
 378                  * Binding a new device with existing PASID, need to setup
 379                  * the PASID entry.
 380                  */
 381                 spin_lock(&iommu->lock);
 382                 ret = intel_pasid_setup_first_level(iommu, dev,
 383                                                 mm ? mm->pgd : init_mm.pgd,
 384                                                 svm->pasid, FLPT_DEFAULT_DID,
 385                                                 mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
 386                 spin_unlock(&iommu->lock);
 387                 if (ret) {
 388                         kfree(sdev);
 389                         goto out;
 390                 }
 391         }
 392         list_add_rcu(&sdev->list, &svm->devs);
 393
 394  success:
 395         *pasid = svm->pasid;
 396         ret = 0;
 397  out:
 398         mutex_unlock(&pasid_mutex);
 399         if (mm)
 400                 mmput(mm);
 401         return ret;
 402 }
 403 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 404
 405 int intel_svm_unbind_mm(struct device *dev, int pasid)
 406 {
 407         struct intel_svm_dev *sdev;
 408         struct intel_iommu *iommu;
 409         struct intel_svm *svm;
 410         int ret = -EINVAL;
 411
 412         mutex_lock(&pasid_mutex);
 413         iommu = intel_svm_device_to_iommu(dev);
 414         if (!iommu)
 415                 goto out;
 416
 417         svm = intel_pasid_lookup_id(pasid);
 418         if (!svm)
 419                 goto out;
 420
 421         list_for_each_entry(sdev, &svm->devs, list) {
 422                 if (dev == sdev->dev) {
 423                         ret = 0;
 424                         sdev->users--;
 425                         if (!sdev->users) {
 426                                 list_del_rcu(&sdev->list);
 427                                 /* Flush the PASID cache and IOTLB for this device.
 428                                  * Note that we do depend on the hardware *not* using
 429                                  * the PASID any more. Just as we depend on other
 430                                  * devices never using PASIDs that they have no right
 431                                  * to use. We have a *shared* PASID table, because it's
 432                                  * large and has to be physically contiguous. So it's
 433                                  * hard to be as defensive as we might like. */
 434                                 intel_pasid_tear_down_entry(iommu, dev, svm->pasid);
 435                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
 436                                 kfree_rcu(sdev, rcu);
 437
 438                                 if (list_empty(&svm->devs)) {
 439                                         intel_pasid_free_id(svm->pasid);
 440                                         if (svm->mm)
 441                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 442
 443                                         list_del(&svm->list);
 444
 445                                         /* We mandate that no page faults may be outstanding
 446                                          * for the PASID when intel_svm_unbind_mm() is called.
 447                                          * If that is not obeyed, subtle errors will happen.
 448                                          * Let's make them less subtle... */
 449                                         memset(svm, 0x6b, sizeof(*svm));
 450                                         kfree(svm);
 451                                 }
 452                         }
 453                         break;
 454                 }
 455         }
 456  out:
 457         mutex_unlock(&pasid_mutex);
 458
 459         return ret;
 460 }
 461 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 462
 463 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 464 {
 465         struct intel_iommu *iommu;
 466         struct intel_svm *svm;
 467         int ret = -EINVAL;
 468
 469         mutex_lock(&pasid_mutex);
 470         iommu = intel_svm_device_to_iommu(dev);
 471         if (!iommu)
 472                 goto out;
 473
 474         svm = intel_pasid_lookup_id(pasid);
 475         if (!svm)
 476                 goto out;
 477
 478         /* init_mm is used in this case */
 479         if (!svm->mm)
 480                 ret = 1;
 481         else if (atomic_read(&svm->mm->mm_users) > 0)
 482                 ret = 1;
 483         else
 484                 ret = 0;
 485
 486  out:
 487         mutex_unlock(&pasid_mutex);
 488
 489         return ret;
 490 }
 491 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 492
 493 /* Page request queue descriptor */
 494 struct page_req_dsc {
 495         union {
 496                 struct {
 497                         u64 type:8;
 498                         u64 pasid_present:1;
 499                         u64 priv_data_present:1;
 500                         u64 rsvd:6;
 501                         u64 rid:16;
 502                         u64 pasid:20;
 503                         u64 exe_req:1;
 504                         u64 pm_req:1;
 505                         u64 rsvd2:10;
 506                 };
 507                 u64 qw_0;
 508         };
 509         union {
 510                 struct {
 511                         u64 rd_req:1;
 512                         u64 wr_req:1;
 513                         u64 lpig:1;
 514                         u64 prg_index:9;
 515                         u64 addr:52;
 516                 };
 517                 u64 qw_1;
 518         };
 519         u64 priv_data[2];
 520 };
 521
 522 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 523
 524 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 525 {
 526         unsigned long requested = 0;
 527
 528         if (req->exe_req)
 529                 requested |= VM_EXEC;
 530
 531         if (req->rd_req)
 532                 requested |= VM_READ;
 533
 534         if (req->wr_req)
 535                 requested |= VM_WRITE;
 536
 537         return (requested & ~vma->vm_flags) != 0;
 538 }
 539
 540 static bool is_canonical_address(u64 addr)
 541 {
 542         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 543         long saddr = (long) addr;
 544
 545         return (((saddr << shift) >> shift) == saddr);
 546 }
 547
 548 static irqreturn_t prq_event_thread(int irq, void *d)
 549 {
 550         struct intel_iommu *iommu = d;
 551         struct intel_svm *svm = NULL;
 552         int head, tail, handled = 0;
 553
 554         /* Clear PPR bit before reading head/tail registers, to
 555          * ensure that we get a new interrupt if needed. */
 556         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 557
 558         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 559         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 560         while (head != tail) {
 561                 struct intel_svm_dev *sdev;
 562                 struct vm_area_struct *vma;
 563                 struct page_req_dsc *req;
 564                 struct qi_desc resp;
 565                 int result;
 566                 vm_fault_t ret;
 567                 u64 address;
 568
 569                 handled = 1;
 570
 571                 req = &iommu->prq[head / sizeof(*req)];
 572
 573                 result = QI_RESP_FAILURE;
 574                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 575                 if (!req->pasid_present) {
 576                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 577                                iommu->name, ((unsigned long long *)req)[0],
 578                                ((unsigned long long *)req)[1]);
 579                         goto no_pasid;
 580                 }
 581
 582                 if (!svm || svm->pasid != req->pasid) {
 583                         rcu_read_lock();
 584                         svm = intel_pasid_lookup_id(req->pasid);
 585                         /* It *can't* go away, because the driver is not permitted
 586                          * to unbind the mm while any page faults are outstanding.
 587                          * So we only need RCU to protect the internal idr code. */
 588                         rcu_read_unlock();
 589
 590                         if (!svm) {
 591                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 592                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 593                                        ((unsigned long long *)req)[1]);
 594                                 goto no_pasid;
 595                         }
 596                 }
 597
 598                 result = QI_RESP_INVALID;
 599                 /* Since we're using init_mm.pgd directly, we should never take
 600                  * any faults on kernel addresses. */
 601                 if (!svm->mm)
 602                         goto bad_req;
 603                 /* If the mm is already defunct, don't handle faults. */
 604                 if (!mmget_not_zero(svm->mm))
 605                         goto bad_req;
 606
 607                 /* If address is not canonical, return invalid response */
 608                 if (!is_canonical_address(address))
 609                         goto bad_req;
 610
 611                 down_read(&svm->mm->mmap_sem);
 612                 vma = find_extend_vma(svm->mm, address);
 613                 if (!vma || address < vma->vm_start)
 614                         goto invalid;
 615
 616                 if (access_error(vma, req))
 617                         goto invalid;
 618
 619                 ret = handle_mm_fault(vma, address,
 620                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 621                 if (ret & VM_FAULT_ERROR)
 622                         goto invalid;
 623
 624                 result = QI_RESP_SUCCESS;
 625         invalid:
 626                 up_read(&svm->mm->mmap_sem);
 627                 mmput(svm->mm);
 628         bad_req:
 629                 /* Accounting for major/minor faults? */
 630                 rcu_read_lock();
 631                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 632                         if (sdev->sid == req->rid)
 633                                 break;
 634                 }
 635                 /* Other devices can go away, but the drivers are not permitted
 636                  * to unbind while any page faults might be in flight. So it's
 637                  * OK to drop the 'lock' here now we have it. */
 638                 rcu_read_unlock();
 639
 640                 if (WARN_ON(&sdev->list == &svm->devs))
 641                         sdev = NULL;
 642
 643                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 644                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 645                                 (req->exe_req << 1) | (req->pm_req);
 646                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr,
 647                                             req->priv_data, rwxp, result);
 648                 }
 649                 /* We get here in the error case where the PASID lookup failed,
 650                    and these can be NULL. Do not use them below this point! */
 651                 sdev = NULL;
 652                 svm = NULL;
 653         no_pasid:
 654                 if (req->lpig || req->priv_data_present) {
 655                         /*
 656                          * Per VT-d spec. v3.0 ch7.7, system software must
 657                          * respond with page group response if private data
 658                          * is present (PDP) or last page in group (LPIG) bit
 659                          * is set. This is an additional VT-d feature beyond
 660                          * PCI ATS spec.
 661                          */
 662                         resp.qw0 = QI_PGRP_PASID(req->pasid) |
 663                                 QI_PGRP_DID(req->rid) |
 664                                 QI_PGRP_PASID_P(req->pasid_present) |
 665                                 QI_PGRP_PDP(req->pasid_present) |
 666                                 QI_PGRP_RESP_CODE(result) |
 667                                 QI_PGRP_RESP_TYPE;
 668                         resp.qw1 = QI_PGRP_IDX(req->prg_index) |
 669                                 QI_PGRP_LPIG(req->lpig);
 670
 671                         if (req->priv_data_present)
 672                                 memcpy(&resp.qw2, req->priv_data,
 673                                        sizeof(req->priv_data));
 674                 }
 675                 resp.qw2 = 0;
 676                 resp.qw3 = 0;
 677                 qi_submit_sync(&resp, iommu);
 678
 679                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 680         }
 681
 682         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 683
 684         return IRQ_RETVAL(handled);
 685 }