2 * Copyright © 2015 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * Authors: David Woodhouse <dwmw2@infradead.org>
16 #include <linux/intel-iommu.h>
17 #include <linux/mmu_notifier.h>
18 #include <linux/sched.h>
19 #include <linux/sched/mm.h>
20 #include <linux/slab.h>
21 #include <linux/intel-svm.h>
22 #include <linux/rculist.h>
23 #include <linux/pci.h>
24 #include <linux/pci-ats.h>
25 #include <linux/dmar.h>
26 #include <linux/interrupt.h>
27 #include <linux/mm_types.h>
30 #include "intel-pasid.h"
32 static irqreturn_t prq_event_thread(int irq, void *d);
34 int intel_svm_init(struct intel_iommu *iommu)
36 if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
37 !cap_fl1gp_support(iommu->cap))
40 if (cpu_feature_enabled(X86_FEATURE_LA57) &&
41 !cap_5lp_support(iommu->cap))
49 int intel_svm_enable_prq(struct intel_iommu *iommu)
54 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
56 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
60 iommu->prq = page_address(pages);
62 irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
64 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
68 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
74 snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
76 ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
77 iommu->prq_name, iommu);
79 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
85 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
86 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
87 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
92 int intel_svm_finish_prq(struct intel_iommu *iommu)
94 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
95 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
96 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
99 free_irq(iommu->pr_irq, iommu);
100 dmar_free_hwirq(iommu->pr_irq);
104 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
110 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
111 unsigned long address, unsigned long pages, int ih, int gl)
116 /* For global kernel pages we have to flush them in *all* PASIDs
117 * because that's the only option the hardware gives us. Despite
118 * the fact that they are actually only accessible through one. */
120 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
121 QI_EIOTLB_DID(sdev->did) |
122 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) |
125 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
126 QI_EIOTLB_DID(sdev->did) |
127 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
131 int mask = ilog2(__roundup_pow_of_two(pages));
133 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
134 QI_EIOTLB_DID(sdev->did) |
135 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
137 desc.qw1 = QI_EIOTLB_ADDR(address) |
144 qi_submit_sync(&desc, svm->iommu);
146 if (sdev->dev_iotlb) {
147 desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
148 QI_DEV_EIOTLB_SID(sdev->sid) |
149 QI_DEV_EIOTLB_QDEP(sdev->qdep) |
152 desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) |
154 } else if (pages > 1) {
155 /* The least significant zero bit indicates the size. So,
156 * for example, an "address" value of 0x12345f000 will
157 * flush from 0x123440000 to 0x12347ffff (256KiB). */
158 unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
159 unsigned long mask = __rounddown_pow_of_two(address ^ last);
161 desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) |
162 (mask - 1)) | QI_DEV_EIOTLB_SIZE;
164 desc.qw1 = QI_DEV_EIOTLB_ADDR(address);
168 qi_submit_sync(&desc, svm->iommu);
172 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
173 unsigned long pages, int ih, int gl)
175 struct intel_svm_dev *sdev;
178 list_for_each_entry_rcu(sdev, &svm->devs, list)
179 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
183 /* Pages have been freed at this point */
184 static void intel_invalidate_range(struct mmu_notifier *mn,
185 struct mm_struct *mm,
186 unsigned long start, unsigned long end)
188 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
190 intel_flush_svm_range(svm, start,
191 (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
194 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
196 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
197 struct intel_svm_dev *sdev;
199 /* This might end up being called from exit_mmap(), *before* the page
200 * tables are cleared. And __mmu_notifier_release() will delete us from
201 * the list of notifiers so that our invalidate_range() callback doesn't
202 * get called when the page tables are cleared. So we need to protect
203 * against hardware accessing those page tables.
205 * We do it by clearing the entry in the PASID table and then flushing
206 * the IOTLB and the PASID table caches. This might upset hardware;
207 * perhaps we'll want to point the PASID to a dummy PGD (like the zero
208 * page) so that we end up taking a fault that the hardware really
209 * *has* to handle gracefully without affecting other processes.
212 list_for_each_entry_rcu(sdev, &svm->devs, list) {
213 intel_pasid_tear_down_entry(svm->iommu, sdev->dev, svm->pasid);
214 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
220 static const struct mmu_notifier_ops intel_mmuops = {
221 .release = intel_mm_release,
222 .invalidate_range = intel_invalidate_range,
225 static DEFINE_MUTEX(pasid_mutex);
226 static LIST_HEAD(global_svm_list);
228 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
230 struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
231 struct intel_svm_dev *sdev;
232 struct intel_svm *svm = NULL;
233 struct mm_struct *mm = NULL;
237 if (!iommu || dmar_disabled)
240 if (dev_is_pci(dev)) {
241 pasid_max = pci_max_pasids(to_pci_dev(dev));
247 if (flags & SVM_FLAG_SUPERVISOR_MODE) {
248 if (!ecap_srs(iommu->ecap))
251 mm = get_task_mm(current);
255 mutex_lock(&pasid_mutex);
256 if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
259 list_for_each_entry(t, &global_svm_list, list) {
260 if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
264 if (svm->pasid >= pasid_max) {
266 "Limited PASID width. Cannot use existing PASID %d\n",
272 list_for_each_entry(sdev, &svm->devs, list) {
273 if (dev == sdev->dev) {
274 if (sdev->ops != ops) {
287 sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
294 ret = intel_iommu_enable_pasid(iommu, sdev);
296 /* If they don't actually want to assign a PASID, this is
297 * just an enabling check/preparation. */
301 /* Finish the setup now we know we're keeping it */
304 init_rcu_head(&sdev->rcu);
307 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
315 if (pasid_max > intel_pasid_max_id)
316 pasid_max = intel_pasid_max_id;
318 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
319 ret = intel_pasid_alloc_id(svm,
320 !!cap_caching_mode(iommu->cap),
321 pasid_max - 1, GFP_KERNEL);
328 svm->notifier.ops = &intel_mmuops;
331 INIT_LIST_HEAD_RCU(&svm->devs);
332 INIT_LIST_HEAD(&svm->list);
335 ret = mmu_notifier_register(&svm->notifier, mm);
337 intel_pasid_free_id(svm->pasid);
344 spin_lock(&iommu->lock);
345 ret = intel_pasid_setup_first_level(iommu, dev,
346 mm ? mm->pgd : init_mm.pgd,
347 svm->pasid, FLPT_DEFAULT_DID,
348 mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
349 spin_unlock(&iommu->lock);
352 mmu_notifier_unregister(&svm->notifier, mm);
353 intel_pasid_free_id(svm->pasid);
359 list_add_tail(&svm->list, &global_svm_list);
361 list_add_rcu(&sdev->list, &svm->devs);
367 mutex_unlock(&pasid_mutex);
372 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
374 int intel_svm_unbind_mm(struct device *dev, int pasid)
376 struct intel_svm_dev *sdev;
377 struct intel_iommu *iommu;
378 struct intel_svm *svm;
381 mutex_lock(&pasid_mutex);
382 iommu = intel_svm_device_to_iommu(dev);
386 svm = intel_pasid_lookup_id(pasid);
390 list_for_each_entry(sdev, &svm->devs, list) {
391 if (dev == sdev->dev) {
395 list_del_rcu(&sdev->list);
396 /* Flush the PASID cache and IOTLB for this device.
397 * Note that we do depend on the hardware *not* using
398 * the PASID any more. Just as we depend on other
399 * devices never using PASIDs that they have no right
400 * to use. We have a *shared* PASID table, because it's
401 * large and has to be physically contiguous. So it's
402 * hard to be as defensive as we might like. */
403 intel_pasid_tear_down_entry(iommu, dev, svm->pasid);
404 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
405 kfree_rcu(sdev, rcu);
407 if (list_empty(&svm->devs)) {
408 intel_pasid_free_id(svm->pasid);
410 mmu_notifier_unregister(&svm->notifier, svm->mm);
412 list_del(&svm->list);
414 /* We mandate that no page faults may be outstanding
415 * for the PASID when intel_svm_unbind_mm() is called.
416 * If that is not obeyed, subtle errors will happen.
417 * Let's make them less subtle... */
418 memset(svm, 0x6b, sizeof(*svm));
426 mutex_unlock(&pasid_mutex);
430 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
432 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
434 struct intel_iommu *iommu;
435 struct intel_svm *svm;
438 mutex_lock(&pasid_mutex);
439 iommu = intel_svm_device_to_iommu(dev);
443 svm = intel_pasid_lookup_id(pasid);
447 /* init_mm is used in this case */
450 else if (atomic_read(&svm->mm->mm_users) > 0)
456 mutex_unlock(&pasid_mutex);
460 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
462 /* Page request queue descriptor */
463 struct page_req_dsc {
468 u64 priv_data_present:1;
491 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
493 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
495 unsigned long requested = 0;
498 requested |= VM_EXEC;
501 requested |= VM_READ;
504 requested |= VM_WRITE;
506 return (requested & ~vma->vm_flags) != 0;
509 static bool is_canonical_address(u64 addr)
511 int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
512 long saddr = (long) addr;
514 return (((saddr << shift) >> shift) == saddr);
517 static irqreturn_t prq_event_thread(int irq, void *d)
519 struct intel_iommu *iommu = d;
520 struct intel_svm *svm = NULL;
521 int head, tail, handled = 0;
523 /* Clear PPR bit before reading head/tail registers, to
524 * ensure that we get a new interrupt if needed. */
525 writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
527 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
528 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
529 while (head != tail) {
530 struct intel_svm_dev *sdev;
531 struct vm_area_struct *vma;
532 struct page_req_dsc *req;
540 req = &iommu->prq[head / sizeof(*req)];
542 result = QI_RESP_FAILURE;
543 address = (u64)req->addr << VTD_PAGE_SHIFT;
544 if (!req->pasid_present) {
545 pr_err("%s: Page request without PASID: %08llx %08llx\n",
546 iommu->name, ((unsigned long long *)req)[0],
547 ((unsigned long long *)req)[1]);
551 if (!svm || svm->pasid != req->pasid) {
553 svm = intel_pasid_lookup_id(req->pasid);
554 /* It *can't* go away, because the driver is not permitted
555 * to unbind the mm while any page faults are outstanding.
556 * So we only need RCU to protect the internal idr code. */
560 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
561 iommu->name, req->pasid, ((unsigned long long *)req)[0],
562 ((unsigned long long *)req)[1]);
567 result = QI_RESP_INVALID;
568 /* Since we're using init_mm.pgd directly, we should never take
569 * any faults on kernel addresses. */
572 /* If the mm is already defunct, don't handle faults. */
573 if (!mmget_not_zero(svm->mm))
576 /* If address is not canonical, return invalid response */
577 if (!is_canonical_address(address))
580 down_read(&svm->mm->mmap_sem);
581 vma = find_extend_vma(svm->mm, address);
582 if (!vma || address < vma->vm_start)
585 if (access_error(vma, req))
588 ret = handle_mm_fault(vma, address,
589 req->wr_req ? FAULT_FLAG_WRITE : 0);
590 if (ret & VM_FAULT_ERROR)
593 result = QI_RESP_SUCCESS;
595 up_read(&svm->mm->mmap_sem);
598 /* Accounting for major/minor faults? */
600 list_for_each_entry_rcu(sdev, &svm->devs, list) {
601 if (sdev->sid == req->rid)
604 /* Other devices can go away, but the drivers are not permitted
605 * to unbind while any page faults might be in flight. So it's
606 * OK to drop the 'lock' here now we have it. */
609 if (WARN_ON(&sdev->list == &svm->devs))
612 if (sdev && sdev->ops && sdev->ops->fault_cb) {
613 int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
614 (req->exe_req << 1) | (req->pm_req);
615 sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr,
616 req->priv_data, rwxp, result);
618 /* We get here in the error case where the PASID lookup failed,
619 and these can be NULL. Do not use them below this point! */
623 if (req->lpig || req->priv_data_present) {
625 * Per VT-d spec. v3.0 ch7.7, system software must
626 * respond with page group response if private data
627 * is present (PDP) or last page in group (LPIG) bit
628 * is set. This is an additional VT-d feature beyond
631 resp.qw0 = QI_PGRP_PASID(req->pasid) |
632 QI_PGRP_DID(req->rid) |
633 QI_PGRP_PASID_P(req->pasid_present) |
634 QI_PGRP_PDP(req->pasid_present) |
635 QI_PGRP_RESP_CODE(result) |
637 resp.qw1 = QI_PGRP_IDX(req->prg_index) |
638 QI_PGRP_LPIG(req->lpig);
640 if (req->priv_data_present)
641 memcpy(&resp.qw2, req->priv_data,
642 sizeof(req->priv_data));
646 qi_submit_sync(&resp, iommu);
648 head = (head + sizeof(*req)) & PRQ_RING_MASK;
651 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
653 return IRQ_RETVAL(handled);