drivers/iommu/intel-svm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright © 2015 Intel Corporation.
   4  *
   5  * Authors: David Woodhouse <dwmw2@infradead.org>
   6  */
   7
   8 #include <linux/intel-iommu.h>
   9 #include <linux/mmu_notifier.h>
  10 #include <linux/sched.h>
  11 #include <linux/sched/mm.h>
  12 #include <linux/slab.h>
  13 #include <linux/intel-svm.h>
  14 #include <linux/rculist.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci-ats.h>
  17 #include <linux/dmar.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/mm_types.h>
  20 #include <linux/ioasid.h>
  21 #include <asm/page.h>
  22
  23 #include "intel-pasid.h"
  24
  25 static irqreturn_t prq_event_thread(int irq, void *d);
  26
  27 #define PRQ_ORDER 0
  28
  29 int intel_svm_enable_prq(struct intel_iommu *iommu)
  30 {
  31         struct page *pages;
  32         int irq, ret;
  33
  34         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
  35         if (!pages) {
  36                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
  37                         iommu->name);
  38                 return -ENOMEM;
  39         }
  40         iommu->prq = page_address(pages);
  41
  42         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
  43         if (irq <= 0) {
  44                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
  45                        iommu->name);
  46                 ret = -EINVAL;
  47         err:
  48                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
  49                 iommu->prq = NULL;
  50                 return ret;
  51         }
  52         iommu->pr_irq = irq;
  53
  54         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
  55
  56         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
  57                                    iommu->prq_name, iommu);
  58         if (ret) {
  59                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
  60                        iommu->name);
  61                 dmar_free_hwirq(irq);
  62                 iommu->pr_irq = 0;
  63                 goto err;
  64         }
  65         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  66         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  67         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
  68
  69         return 0;
  70 }
  71
  72 int intel_svm_finish_prq(struct intel_iommu *iommu)
  73 {
  74         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  75         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  76         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
  77
  78         if (iommu->pr_irq) {
  79                 free_irq(iommu->pr_irq, iommu);
  80                 dmar_free_hwirq(iommu->pr_irq);
  81                 iommu->pr_irq = 0;
  82         }
  83
  84         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
  85         iommu->prq = NULL;
  86
  87         return 0;
  88 }
  89
  90 static inline bool intel_svm_capable(struct intel_iommu *iommu)
  91 {
  92         return iommu->flags & VTD_FLAG_SVM_CAPABLE;
  93 }
  94
  95 void intel_svm_check(struct intel_iommu *iommu)
  96 {
  97         if (!pasid_supported(iommu))
  98                 return;
  99
 100         if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
 101             !cap_fl1gp_support(iommu->cap)) {
 102                 pr_err("%s SVM disabled, incompatible 1GB page capability\n",
 103                        iommu->name);
 104                 return;
 105         }
 106
 107         if (cpu_feature_enabled(X86_FEATURE_LA57) &&
 108             !cap_5lp_support(iommu->cap)) {
 109                 pr_err("%s SVM disabled, incompatible paging mode\n",
 110                        iommu->name);
 111                 return;
 112         }
 113
 114         iommu->flags |= VTD_FLAG_SVM_CAPABLE;
 115 }
 116
 117 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 118                                 unsigned long address, unsigned long pages, int ih)
 119 {
 120         struct qi_desc desc;
 121
 122         if (pages == -1) {
 123                 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 124                         QI_EIOTLB_DID(sdev->did) |
 125                         QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
 126                         QI_EIOTLB_TYPE;
 127                 desc.qw1 = 0;
 128         } else {
 129                 int mask = ilog2(__roundup_pow_of_two(pages));
 130
 131                 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 132                                 QI_EIOTLB_DID(sdev->did) |
 133                                 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
 134                                 QI_EIOTLB_TYPE;
 135                 desc.qw1 = QI_EIOTLB_ADDR(address) |
 136                                 QI_EIOTLB_IH(ih) |
 137                                 QI_EIOTLB_AM(mask);
 138         }
 139         desc.qw2 = 0;
 140         desc.qw3 = 0;
 141         qi_submit_sync(&desc, svm->iommu);
 142
 143         if (sdev->dev_iotlb) {
 144                 desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
 145                                 QI_DEV_EIOTLB_SID(sdev->sid) |
 146                                 QI_DEV_EIOTLB_QDEP(sdev->qdep) |
 147                                 QI_DEIOTLB_TYPE;
 148                 if (pages == -1) {
 149                         desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) |
 150                                         QI_DEV_EIOTLB_SIZE;
 151                 } else if (pages > 1) {
 152                         /* The least significant zero bit indicates the size. So,
 153                          * for example, an "address" value of 0x12345f000 will
 154                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 155                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 156                         unsigned long mask = __rounddown_pow_of_two(address ^ last);
 157
 158                         desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) |
 159                                         (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 160                 } else {
 161                         desc.qw1 = QI_DEV_EIOTLB_ADDR(address);
 162                 }
 163                 desc.qw2 = 0;
 164                 desc.qw3 = 0;
 165                 qi_submit_sync(&desc, svm->iommu);
 166         }
 167 }
 168
 169 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 170                                 unsigned long pages, int ih)
 171 {
 172         struct intel_svm_dev *sdev;
 173
 174         rcu_read_lock();
 175         list_for_each_entry_rcu(sdev, &svm->devs, list)
 176                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih);
 177         rcu_read_unlock();
 178 }
 179
 180 /* Pages have been freed at this point */
 181 static void intel_invalidate_range(struct mmu_notifier *mn,
 182                                    struct mm_struct *mm,
 183                                    unsigned long start, unsigned long end)
 184 {
 185         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 186
 187         intel_flush_svm_range(svm, start,
 188                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0);
 189 }
 190
 191 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 192 {
 193         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 194         struct intel_svm_dev *sdev;
 195
 196         /* This might end up being called from exit_mmap(), *before* the page
 197          * tables are cleared. And __mmu_notifier_release() will delete us from
 198          * the list of notifiers so that our invalidate_range() callback doesn't
 199          * get called when the page tables are cleared. So we need to protect
 200          * against hardware accessing those page tables.
 201          *
 202          * We do it by clearing the entry in the PASID table and then flushing
 203          * the IOTLB and the PASID table caches. This might upset hardware;
 204          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 205          * page) so that we end up taking a fault that the hardware really
 206          * *has* to handle gracefully without affecting other processes.
 207          */
 208         rcu_read_lock();
 209         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 210                 intel_pasid_tear_down_entry(svm->iommu, sdev->dev, svm->pasid);
 211                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
 212         }
 213         rcu_read_unlock();
 214
 215 }
 216
 217 static const struct mmu_notifier_ops intel_mmuops = {
 218         .release = intel_mm_release,
 219         .invalidate_range = intel_invalidate_range,
 220 };
 221
 222 static DEFINE_MUTEX(pasid_mutex);
 223 static LIST_HEAD(global_svm_list);
 224
 225 #define for_each_svm_dev(sdev, svm, d)                  \
 226         list_for_each_entry((sdev), &(svm)->devs, list) \
 227                 if ((d) != (sdev)->dev) {} else
 228
 229 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 230 {
 231         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 232         struct device_domain_info *info;
 233         struct intel_svm_dev *sdev;
 234         struct intel_svm *svm = NULL;
 235         struct mm_struct *mm = NULL;
 236         int pasid_max;
 237         int ret;
 238
 239         if (!iommu || dmar_disabled)
 240                 return -EINVAL;
 241
 242         if (!intel_svm_capable(iommu))
 243                 return -ENOTSUPP;
 244
 245         if (dev_is_pci(dev)) {
 246                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 247                 if (pasid_max < 0)
 248                         return -EINVAL;
 249         } else
 250                 pasid_max = 1 << 20;
 251
 252         if (flags & SVM_FLAG_SUPERVISOR_MODE) {
 253                 if (!ecap_srs(iommu->ecap))
 254                         return -EINVAL;
 255         } else if (pasid) {
 256                 mm = get_task_mm(current);
 257                 BUG_ON(!mm);
 258         }
 259
 260         mutex_lock(&pasid_mutex);
 261         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 262                 struct intel_svm *t;
 263
 264                 list_for_each_entry(t, &global_svm_list, list) {
 265                         if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
 266                                 continue;
 267
 268                         svm = t;
 269                         if (svm->pasid >= pasid_max) {
 270                                 dev_warn(dev,
 271                                          "Limited PASID width. Cannot use existing PASID %d\n",
 272                                          svm->pasid);
 273                                 ret = -ENOSPC;
 274                                 goto out;
 275                         }
 276
 277                         /* Find the matching device in svm list */
 278                         for_each_svm_dev(sdev, svm, dev) {
 279                                 if (sdev->ops != ops) {
 280                                         ret = -EBUSY;
 281                                         goto out;
 282                                 }
 283                                 sdev->users++;
 284                                 goto success;
 285                         }
 286
 287                         break;
 288                 }
 289         }
 290
 291         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 292         if (!sdev) {
 293                 ret = -ENOMEM;
 294                 goto out;
 295         }
 296         sdev->dev = dev;
 297
 298         ret = intel_iommu_enable_pasid(iommu, dev);
 299         if (ret || !pasid) {
 300                 /* If they don't actually want to assign a PASID, this is
 301                  * just an enabling check/preparation. */
 302                 kfree(sdev);
 303                 goto out;
 304         }
 305
 306         info = dev->archdata.iommu;
 307         if (!info || !info->pasid_supported) {
 308                 kfree(sdev);
 309                 goto out;
 310         }
 311
 312         sdev->did = FLPT_DEFAULT_DID;
 313         sdev->sid = PCI_DEVID(info->bus, info->devfn);
 314         if (info->ats_enabled) {
 315                 sdev->dev_iotlb = 1;
 316                 sdev->qdep = info->ats_qdep;
 317                 if (sdev->qdep >= QI_DEV_EIOTLB_MAX_INVS)
 318                         sdev->qdep = 0;
 319         }
 320
 321         /* Finish the setup now we know we're keeping it */
 322         sdev->users = 1;
 323         sdev->ops = ops;
 324         init_rcu_head(&sdev->rcu);
 325
 326         if (!svm) {
 327                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 328                 if (!svm) {
 329                         ret = -ENOMEM;
 330                         kfree(sdev);
 331                         goto out;
 332                 }
 333                 svm->iommu = iommu;
 334
 335                 if (pasid_max > intel_pasid_max_id)
 336                         pasid_max = intel_pasid_max_id;
 337
 338                 /* Do not use PASID 0, reserved for RID to PASID */
 339                 svm->pasid = ioasid_alloc(NULL, PASID_MIN,
 340                                           pasid_max - 1, svm);
 341                 if (svm->pasid == INVALID_IOASID) {
 342                         kfree(svm);
 343                         kfree(sdev);
 344                         ret = -ENOSPC;
 345                         goto out;
 346                 }
 347                 svm->notifier.ops = &intel_mmuops;
 348                 svm->mm = mm;
 349                 svm->flags = flags;
 350                 INIT_LIST_HEAD_RCU(&svm->devs);
 351                 INIT_LIST_HEAD(&svm->list);
 352                 ret = -ENOMEM;
 353                 if (mm) {
 354                         ret = mmu_notifier_register(&svm->notifier, mm);
 355                         if (ret) {
 356                                 ioasid_free(svm->pasid);
 357                                 kfree(svm);
 358                                 kfree(sdev);
 359                                 goto out;
 360                         }
 361                 }
 362
 363                 spin_lock(&iommu->lock);
 364                 ret = intel_pasid_setup_first_level(iommu, dev,
 365                                 mm ? mm->pgd : init_mm.pgd,
 366                                 svm->pasid, FLPT_DEFAULT_DID,
 367                                 (mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
 368                                 (cpu_feature_enabled(X86_FEATURE_LA57) ?
 369                                  PASID_FLAG_FL5LP : 0));
 370                 spin_unlock(&iommu->lock);
 371                 if (ret) {
 372                         if (mm)
 373                                 mmu_notifier_unregister(&svm->notifier, mm);
 374                         ioasid_free(svm->pasid);
 375                         kfree(svm);
 376                         kfree(sdev);
 377                         goto out;
 378                 }
 379
 380                 list_add_tail(&svm->list, &global_svm_list);
 381         } else {
 382                 /*
 383                  * Binding a new device with existing PASID, need to setup
 384                  * the PASID entry.
 385                  */
 386                 spin_lock(&iommu->lock);
 387                 ret = intel_pasid_setup_first_level(iommu, dev,
 388                                                 mm ? mm->pgd : init_mm.pgd,
 389                                                 svm->pasid, FLPT_DEFAULT_DID,
 390                                                 (mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
 391                                                 (cpu_feature_enabled(X86_FEATURE_LA57) ?
 392                                                 PASID_FLAG_FL5LP : 0));
 393                 spin_unlock(&iommu->lock);
 394                 if (ret) {
 395                         kfree(sdev);
 396                         goto out;
 397                 }
 398         }
 399         list_add_rcu(&sdev->list, &svm->devs);
 400
 401  success:
 402         *pasid = svm->pasid;
 403         ret = 0;
 404  out:
 405         mutex_unlock(&pasid_mutex);
 406         if (mm)
 407                 mmput(mm);
 408         return ret;
 409 }
 410 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 411
 412 int intel_svm_unbind_mm(struct device *dev, int pasid)
 413 {
 414         struct intel_svm_dev *sdev;
 415         struct intel_iommu *iommu;
 416         struct intel_svm *svm;
 417         int ret = -EINVAL;
 418
 419         mutex_lock(&pasid_mutex);
 420         iommu = intel_svm_device_to_iommu(dev);
 421         if (!iommu)
 422                 goto out;
 423
 424         svm = ioasid_find(NULL, pasid, NULL);
 425         if (!svm)
 426                 goto out;
 427
 428         if (IS_ERR(svm)) {
 429                 ret = PTR_ERR(svm);
 430                 goto out;
 431         }
 432
 433         for_each_svm_dev(sdev, svm, dev) {
 434                 ret = 0;
 435                 sdev->users--;
 436                 if (!sdev->users) {
 437                         list_del_rcu(&sdev->list);
 438                         /* Flush the PASID cache and IOTLB for this device.
 439                          * Note that we do depend on the hardware *not* using
 440                          * the PASID any more. Just as we depend on other
 441                          * devices never using PASIDs that they have no right
 442                          * to use. We have a *shared* PASID table, because it's
 443                          * large and has to be physically contiguous. So it's
 444                          * hard to be as defensive as we might like. */
 445                         intel_pasid_tear_down_entry(iommu, dev, svm->pasid);
 446                         intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
 447                         kfree_rcu(sdev, rcu);
 448
 449                         if (list_empty(&svm->devs)) {
 450                                 ioasid_free(svm->pasid);
 451                                 if (svm->mm)
 452                                         mmu_notifier_unregister(&svm->notifier, svm->mm);
 453                                 list_del(&svm->list);
 454                                 /* We mandate that no page faults may be outstanding
 455                                  * for the PASID when intel_svm_unbind_mm() is called.
 456                                  * If that is not obeyed, subtle errors will happen.
 457                                  * Let's make them less subtle... */
 458                                 memset(svm, 0x6b, sizeof(*svm));
 459                                 kfree(svm);
 460                         }
 461                 }
 462                 break;
 463         }
 464  out:
 465         mutex_unlock(&pasid_mutex);
 466
 467         return ret;
 468 }
 469 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 470
 471 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 472 {
 473         struct intel_iommu *iommu;
 474         struct intel_svm *svm;
 475         int ret = -EINVAL;
 476
 477         mutex_lock(&pasid_mutex);
 478         iommu = intel_svm_device_to_iommu(dev);
 479         if (!iommu)
 480                 goto out;
 481
 482         svm = ioasid_find(NULL, pasid, NULL);
 483         if (!svm)
 484                 goto out;
 485
 486         if (IS_ERR(svm)) {
 487                 ret = PTR_ERR(svm);
 488                 goto out;
 489         }
 490         /* init_mm is used in this case */
 491         if (!svm->mm)
 492                 ret = 1;
 493         else if (atomic_read(&svm->mm->mm_users) > 0)
 494                 ret = 1;
 495         else
 496                 ret = 0;
 497
 498  out:
 499         mutex_unlock(&pasid_mutex);
 500
 501         return ret;
 502 }
 503 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 504
 505 /* Page request queue descriptor */
 506 struct page_req_dsc {
 507         union {
 508                 struct {
 509                         u64 type:8;
 510                         u64 pasid_present:1;
 511                         u64 priv_data_present:1;
 512                         u64 rsvd:6;
 513                         u64 rid:16;
 514                         u64 pasid:20;
 515                         u64 exe_req:1;
 516                         u64 pm_req:1;
 517                         u64 rsvd2:10;
 518                 };
 519                 u64 qw_0;
 520         };
 521         union {
 522                 struct {
 523                         u64 rd_req:1;
 524                         u64 wr_req:1;
 525                         u64 lpig:1;
 526                         u64 prg_index:9;
 527                         u64 addr:52;
 528                 };
 529                 u64 qw_1;
 530         };
 531         u64 priv_data[2];
 532 };
 533
 534 #define PRQ_RING_MASK   ((0x1000 << PRQ_ORDER) - 0x20)
 535
 536 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 537 {
 538         unsigned long requested = 0;
 539
 540         if (req->exe_req)
 541                 requested |= VM_EXEC;
 542
 543         if (req->rd_req)
 544                 requested |= VM_READ;
 545
 546         if (req->wr_req)
 547                 requested |= VM_WRITE;
 548
 549         return (requested & ~vma->vm_flags) != 0;
 550 }
 551
 552 static bool is_canonical_address(u64 addr)
 553 {
 554         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 555         long saddr = (long) addr;
 556
 557         return (((saddr << shift) >> shift) == saddr);
 558 }
 559
 560 static irqreturn_t prq_event_thread(int irq, void *d)
 561 {
 562         struct intel_iommu *iommu = d;
 563         struct intel_svm *svm = NULL;
 564         int head, tail, handled = 0;
 565
 566         /* Clear PPR bit before reading head/tail registers, to
 567          * ensure that we get a new interrupt if needed. */
 568         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 569
 570         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 571         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 572         while (head != tail) {
 573                 struct intel_svm_dev *sdev;
 574                 struct vm_area_struct *vma;
 575                 struct page_req_dsc *req;
 576                 struct qi_desc resp;
 577                 int result;
 578                 vm_fault_t ret;
 579                 u64 address;
 580
 581                 handled = 1;
 582
 583                 req = &iommu->prq[head / sizeof(*req)];
 584
 585                 result = QI_RESP_FAILURE;
 586                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 587                 if (!req->pasid_present) {
 588                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 589                                iommu->name, ((unsigned long long *)req)[0],
 590                                ((unsigned long long *)req)[1]);
 591                         goto no_pasid;
 592                 }
 593
 594                 if (!svm || svm->pasid != req->pasid) {
 595                         rcu_read_lock();
 596                         svm = ioasid_find(NULL, req->pasid, NULL);
 597                         /* It *can't* go away, because the driver is not permitted
 598                          * to unbind the mm while any page faults are outstanding.
 599                          * So we only need RCU to protect the internal idr code. */
 600                         rcu_read_unlock();
 601                         if (IS_ERR_OR_NULL(svm)) {
 602                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 603                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 604                                        ((unsigned long long *)req)[1]);
 605                                 goto no_pasid;
 606                         }
 607                 }
 608
 609                 result = QI_RESP_INVALID;
 610                 /* Since we're using init_mm.pgd directly, we should never take
 611                  * any faults on kernel addresses. */
 612                 if (!svm->mm)
 613                         goto bad_req;
 614
 615                 /* If address is not canonical, return invalid response */
 616                 if (!is_canonical_address(address))
 617                         goto bad_req;
 618
 619                 /* If the mm is already defunct, don't handle faults. */
 620                 if (!mmget_not_zero(svm->mm))
 621                         goto bad_req;
 622
 623                 down_read(&svm->mm->mmap_sem);
 624                 vma = find_extend_vma(svm->mm, address);
 625                 if (!vma || address < vma->vm_start)
 626                         goto invalid;
 627
 628                 if (access_error(vma, req))
 629                         goto invalid;
 630
 631                 ret = handle_mm_fault(vma, address,
 632                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 633                 if (ret & VM_FAULT_ERROR)
 634                         goto invalid;
 635
 636                 result = QI_RESP_SUCCESS;
 637         invalid:
 638                 up_read(&svm->mm->mmap_sem);
 639                 mmput(svm->mm);
 640         bad_req:
 641                 /* Accounting for major/minor faults? */
 642                 rcu_read_lock();
 643                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 644                         if (sdev->sid == req->rid)
 645                                 break;
 646                 }
 647                 /* Other devices can go away, but the drivers are not permitted
 648                  * to unbind while any page faults might be in flight. So it's
 649                  * OK to drop the 'lock' here now we have it. */
 650                 rcu_read_unlock();
 651
 652                 if (WARN_ON(&sdev->list == &svm->devs))
 653                         sdev = NULL;
 654
 655                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 656                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 657                                 (req->exe_req << 1) | (req->pm_req);
 658                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr,
 659                                             req->priv_data, rwxp, result);
 660                 }
 661                 /* We get here in the error case where the PASID lookup failed,
 662                    and these can be NULL. Do not use them below this point! */
 663                 sdev = NULL;
 664                 svm = NULL;
 665         no_pasid:
 666                 if (req->lpig || req->priv_data_present) {
 667                         /*
 668                          * Per VT-d spec. v3.0 ch7.7, system software must
 669                          * respond with page group response if private data
 670                          * is present (PDP) or last page in group (LPIG) bit
 671                          * is set. This is an additional VT-d feature beyond
 672                          * PCI ATS spec.
 673                          */
 674                         resp.qw0 = QI_PGRP_PASID(req->pasid) |
 675                                 QI_PGRP_DID(req->rid) |
 676                                 QI_PGRP_PASID_P(req->pasid_present) |
 677                                 QI_PGRP_PDP(req->pasid_present) |
 678                                 QI_PGRP_RESP_CODE(result) |
 679                                 QI_PGRP_RESP_TYPE;
 680                         resp.qw1 = QI_PGRP_IDX(req->prg_index) |
 681                                 QI_PGRP_LPIG(req->lpig);
 682
 683                         if (req->priv_data_present)
 684                                 memcpy(&resp.qw2, req->priv_data,
 685                                        sizeof(req->priv_data));
 686                         resp.qw2 = 0;
 687                         resp.qw3 = 0;
 688                         qi_submit_sync(&resp, iommu);
 689                 }
 690                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 691         }
 692
 693         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 694
 695         return IRQ_RETVAL(handled);
 696 }