1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/intel-iommu.h>
14 #include <linux/acpi.h>
15 #include <linux/irqdomain.h>
16 #include <linux/crash_dump.h>
17 #include <asm/io_apic.h>
21 #include <asm/irq_remapping.h>
22 #include <asm/pci-direct.h>
23 #include <asm/msidef.h>
25 #include "../irq_remapping.h"
33 struct intel_iommu *iommu;
35 unsigned int bus; /* PCI bus number */
36 unsigned int devfn; /* PCI devfn number */
40 struct intel_iommu *iommu;
47 struct intel_iommu *iommu;
54 struct intel_ir_data {
55 struct irq_2_iommu irq_2_iommu;
56 struct irte irte_entry;
58 struct msi_msg msi_entry;
62 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
63 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
65 static int __read_mostly eim_mode;
66 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
67 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
74 * ->iommu->register_lock
76 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
77 * in single-threaded environment with interrupt disabled, so no need to tabke
78 * the dmar_global_lock.
80 DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
81 static const struct irq_domain_ops intel_ir_domain_ops;
83 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
84 static int __init parse_ioapics_under_ir(void);
86 static bool ir_pre_enabled(struct intel_iommu *iommu)
88 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
91 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
93 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
96 static void init_ir_status(struct intel_iommu *iommu)
100 gsts = readl(iommu->reg + DMAR_GSTS_REG);
101 if (gsts & DMA_GSTS_IRES)
102 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
105 static int alloc_irte(struct intel_iommu *iommu,
106 struct irq_2_iommu *irq_iommu, u16 count)
108 struct ir_table *table = iommu->ir_table;
109 unsigned int mask = 0;
113 if (!count || !irq_iommu)
117 count = __roundup_pow_of_two(count);
121 if (mask > ecap_max_handle_mask(iommu->ecap)) {
122 pr_err("Requested mask %x exceeds the max invalidation handle"
123 " mask value %Lx\n", mask,
124 ecap_max_handle_mask(iommu->ecap));
128 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
129 index = bitmap_find_free_region(table->bitmap,
130 INTR_REMAP_TABLE_ENTRIES, mask);
132 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
134 irq_iommu->iommu = iommu;
135 irq_iommu->irte_index = index;
136 irq_iommu->sub_handle = 0;
137 irq_iommu->irte_mask = mask;
138 irq_iommu->mode = IRQ_REMAPPING;
140 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
145 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
149 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
155 return qi_submit_sync(iommu, &desc, 1, 0);
158 static int modify_irte(struct irq_2_iommu *irq_iommu,
159 struct irte *irte_modified)
161 struct intel_iommu *iommu;
169 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
171 iommu = irq_iommu->iommu;
173 index = irq_iommu->irte_index + irq_iommu->sub_handle;
174 irte = &iommu->ir_table->base[index];
176 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
177 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
180 ret = cmpxchg_double(&irte->low, &irte->high,
181 irte->low, irte->high,
182 irte_modified->low, irte_modified->high);
184 * We use cmpxchg16 to atomically update the 128-bit IRTE,
185 * and it cannot be updated by the hardware or other processors
186 * behind us, so the return value of cmpxchg16 should be the
187 * same as the old value.
193 set_64bit(&irte->low, irte_modified->low);
194 set_64bit(&irte->high, irte_modified->high);
196 __iommu_flush_cache(iommu, irte, sizeof(*irte));
198 rc = qi_flush_iec(iommu, index, 0);
200 /* Update iommu mode according to the IRTE mode */
201 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
202 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
207 static struct irq_domain *map_hpet_to_ir(u8 hpet_id)
211 for (i = 0; i < MAX_HPET_TBS; i++) {
212 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
213 return ir_hpet[i].iommu->ir_domain;
218 static struct intel_iommu *map_ioapic_to_iommu(int apic)
222 for (i = 0; i < MAX_IO_APICS; i++) {
223 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
224 return ir_ioapic[i].iommu;
229 static struct irq_domain *map_ioapic_to_ir(int apic)
231 struct intel_iommu *iommu = map_ioapic_to_iommu(apic);
233 return iommu ? iommu->ir_domain : NULL;
236 static struct irq_domain *map_dev_to_ir(struct pci_dev *dev)
238 struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev);
240 return drhd ? drhd->iommu->ir_msi_domain : NULL;
243 static int clear_entries(struct irq_2_iommu *irq_iommu)
245 struct irte *start, *entry, *end;
246 struct intel_iommu *iommu;
249 if (irq_iommu->sub_handle)
252 iommu = irq_iommu->iommu;
253 index = irq_iommu->irte_index;
255 start = iommu->ir_table->base + index;
256 end = start + (1 << irq_iommu->irte_mask);
258 for (entry = start; entry < end; entry++) {
259 set_64bit(&entry->low, 0);
260 set_64bit(&entry->high, 0);
262 bitmap_release_region(iommu->ir_table->bitmap, index,
263 irq_iommu->irte_mask);
265 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
269 * source validation type
271 #define SVT_NO_VERIFY 0x0 /* no verification is required */
272 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
273 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
276 * source-id qualifier
278 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
279 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
280 * the third least significant bit
282 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
283 * the second and third least significant bits
285 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
286 * the least three significant bits
290 * set SVT, SQ and SID fields of irte to verify
291 * source ids of interrupt requests
293 static void set_irte_sid(struct irte *irte, unsigned int svt,
294 unsigned int sq, unsigned int sid)
296 if (disable_sourceid_checking)
304 * Set an IRTE to match only the bus number. Interrupt requests that reference
305 * this IRTE must have a requester-id whose bus number is between or equal
306 * to the start_bus and end_bus arguments.
308 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
309 unsigned int end_bus)
311 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
312 (start_bus << 8) | end_bus);
315 static int set_ioapic_sid(struct irte *irte, int apic)
323 down_read(&dmar_global_lock);
324 for (i = 0; i < MAX_IO_APICS; i++) {
325 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
326 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
330 up_read(&dmar_global_lock);
333 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
337 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
342 static int set_hpet_sid(struct irte *irte, u8 id)
350 down_read(&dmar_global_lock);
351 for (i = 0; i < MAX_HPET_TBS; i++) {
352 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
353 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
357 up_read(&dmar_global_lock);
360 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
365 * Should really use SQ_ALL_16. Some platforms are broken.
366 * While we figure out the right quirks for these broken platforms, use
367 * SQ_13_IGNORE_3 for now.
369 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
374 struct set_msi_sid_data {
375 struct pci_dev *pdev;
381 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
383 struct set_msi_sid_data *data = opaque;
385 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
386 data->busmatch_count++;
395 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
397 struct set_msi_sid_data data;
403 data.busmatch_count = 0;
404 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
407 * DMA alias provides us with a PCI device and alias. The only case
408 * where the it will return an alias on a different bus than the
409 * device is the case of a PCIe-to-PCI bridge, where the alias is for
410 * the subordinate bus. In this case we can only verify the bus.
412 * If there are multiple aliases, all with the same bus number,
413 * then all we can do is verify the bus. This is typical in NTB
414 * hardware which use proxy IDs where the device will generate traffic
415 * from multiple devfn numbers on the same bus.
417 * If the alias device is on a different bus than our source device
418 * then we have a topology based alias, use it.
420 * Otherwise, the alias is for a device DMA quirk and we cannot
421 * assume that MSI uses the same requester ID. Therefore use the
424 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
425 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
427 else if (data.count >= 2 && data.busmatch_count == data.count)
428 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
429 else if (data.pdev->bus->number != dev->bus->number)
430 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
432 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
438 static int iommu_load_old_irte(struct intel_iommu *iommu)
440 struct irte *old_ir_table;
441 phys_addr_t irt_phys;
446 /* Check whether the old ir-table has the same size as ours */
447 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
448 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
449 != INTR_REMAP_TABLE_REG_SIZE)
452 irt_phys = irta & VTD_PAGE_MASK;
453 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
455 /* Map the old IR table */
456 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
461 memcpy(iommu->ir_table->base, old_ir_table, size);
463 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
466 * Now check the table for used entries and mark those as
467 * allocated in the bitmap
469 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
470 if (iommu->ir_table->base[i].present)
471 bitmap_set(iommu->ir_table->bitmap, i, 1);
474 memunmap(old_ir_table);
480 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
486 addr = virt_to_phys((void *)iommu->ir_table->base);
488 raw_spin_lock_irqsave(&iommu->register_lock, flags);
490 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
491 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
493 /* Set interrupt-remapping table pointer */
494 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
496 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
497 readl, (sts & DMA_GSTS_IRTPS), sts);
498 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
501 * Global invalidation of interrupt entry cache to make sure the
502 * hardware uses the new irq remapping table.
504 qi_global_iec(iommu);
507 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
512 raw_spin_lock_irqsave(&iommu->register_lock, flags);
514 /* Enable interrupt-remapping */
515 iommu->gcmd |= DMA_GCMD_IRE;
516 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
517 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
518 readl, (sts & DMA_GSTS_IRES), sts);
520 /* Block compatibility-format MSIs */
521 if (sts & DMA_GSTS_CFIS) {
522 iommu->gcmd &= ~DMA_GCMD_CFI;
523 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
524 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
525 readl, !(sts & DMA_GSTS_CFIS), sts);
529 * With CFI clear in the Global Command register, we should be
530 * protected from dangerous (i.e. compatibility) interrupts
531 * regardless of x2apic status. Check just to be sure.
533 if (sts & DMA_GSTS_CFIS)
535 "Compatibility-format IRQs enabled despite intr remapping;\n"
536 "you are vulnerable to IRQ injection.\n");
538 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
541 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
543 struct ir_table *ir_table;
544 struct fwnode_handle *fn;
545 unsigned long *bitmap;
551 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
555 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
556 INTR_REMAP_PAGE_ORDER);
558 pr_err("IR%d: failed to allocate pages of order %d\n",
559 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
563 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC);
564 if (bitmap == NULL) {
565 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
569 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
571 goto out_free_bitmap;
574 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
575 0, INTR_REMAP_TABLE_ENTRIES,
576 fn, &intel_ir_domain_ops,
578 if (!iommu->ir_domain) {
579 irq_domain_free_fwnode(fn);
580 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
581 goto out_free_bitmap;
583 iommu->ir_msi_domain =
584 arch_create_remap_msi_irq_domain(iommu->ir_domain,
588 ir_table->base = page_address(pages);
589 ir_table->bitmap = bitmap;
590 iommu->ir_table = ir_table;
593 * If the queued invalidation is already initialized,
594 * shouldn't disable it.
598 * Clear previous faults.
600 dmar_fault(-1, iommu);
601 dmar_disable_qi(iommu);
603 if (dmar_enable_qi(iommu)) {
604 pr_err("Failed to enable queued invalidation\n");
605 goto out_free_bitmap;
609 init_ir_status(iommu);
611 if (ir_pre_enabled(iommu)) {
612 if (!is_kdump_kernel()) {
613 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
615 clear_ir_pre_enabled(iommu);
616 iommu_disable_irq_remapping(iommu);
617 } else if (iommu_load_old_irte(iommu))
618 pr_err("Failed to copy IR table for %s from previous kernel\n",
621 pr_info("Copied IR table for %s from previous kernel\n",
625 iommu_set_irq_remapping(iommu, eim_mode);
632 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
636 iommu->ir_table = NULL;
641 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
643 struct fwnode_handle *fn;
645 if (iommu && iommu->ir_table) {
646 if (iommu->ir_msi_domain) {
647 fn = iommu->ir_msi_domain->fwnode;
649 irq_domain_remove(iommu->ir_msi_domain);
650 irq_domain_free_fwnode(fn);
651 iommu->ir_msi_domain = NULL;
653 if (iommu->ir_domain) {
654 fn = iommu->ir_domain->fwnode;
656 irq_domain_remove(iommu->ir_domain);
657 irq_domain_free_fwnode(fn);
658 iommu->ir_domain = NULL;
660 free_pages((unsigned long)iommu->ir_table->base,
661 INTR_REMAP_PAGE_ORDER);
662 bitmap_free(iommu->ir_table->bitmap);
663 kfree(iommu->ir_table);
664 iommu->ir_table = NULL;
669 * Disable Interrupt Remapping.
671 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
676 if (!ecap_ir_support(iommu->ecap))
680 * global invalidation of interrupt entry cache before disabling
681 * interrupt-remapping.
683 qi_global_iec(iommu);
685 raw_spin_lock_irqsave(&iommu->register_lock, flags);
687 sts = readl(iommu->reg + DMAR_GSTS_REG);
688 if (!(sts & DMA_GSTS_IRES))
691 iommu->gcmd &= ~DMA_GCMD_IRE;
692 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
694 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
695 readl, !(sts & DMA_GSTS_IRES), sts);
698 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
701 static int __init dmar_x2apic_optout(void)
703 struct acpi_table_dmar *dmar;
704 dmar = (struct acpi_table_dmar *)dmar_tbl;
705 if (!dmar || no_x2apic_optout)
707 return dmar->flags & DMAR_X2APIC_OPT_OUT;
710 static void __init intel_cleanup_irq_remapping(void)
712 struct dmar_drhd_unit *drhd;
713 struct intel_iommu *iommu;
715 for_each_iommu(iommu, drhd) {
716 if (ecap_ir_support(iommu->ecap)) {
717 iommu_disable_irq_remapping(iommu);
718 intel_teardown_irq_remapping(iommu);
722 if (x2apic_supported())
723 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
726 static int __init intel_prepare_irq_remapping(void)
728 struct dmar_drhd_unit *drhd;
729 struct intel_iommu *iommu;
732 if (irq_remap_broken) {
733 pr_warn("This system BIOS has enabled interrupt remapping\n"
734 "on a chipset that contains an erratum making that\n"
735 "feature unstable. To maintain system stability\n"
736 "interrupt remapping is being disabled. Please\n"
737 "contact your BIOS vendor for an update\n");
738 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
742 if (dmar_table_init() < 0)
745 if (!dmar_ir_support())
748 if (parse_ioapics_under_ir()) {
749 pr_info("Not enabling interrupt remapping\n");
753 /* First make sure all IOMMUs support IRQ remapping */
754 for_each_iommu(iommu, drhd)
755 if (!ecap_ir_support(iommu->ecap))
758 /* Detect remapping mode: lapic or x2apic */
759 if (x2apic_supported()) {
760 eim = !dmar_x2apic_optout();
762 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
763 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
767 for_each_iommu(iommu, drhd) {
768 if (eim && !ecap_eim_support(iommu->ecap)) {
769 pr_info("%s does not support EIM\n", iommu->name);
776 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
778 /* Do the initializations early */
779 for_each_iommu(iommu, drhd) {
780 if (intel_setup_irq_remapping(iommu)) {
781 pr_err("Failed to setup irq remapping for %s\n",
790 intel_cleanup_irq_remapping();
795 * Set Posted-Interrupts capability.
797 static inline void set_irq_posting_cap(void)
799 struct dmar_drhd_unit *drhd;
800 struct intel_iommu *iommu;
802 if (!disable_irq_post) {
804 * If IRTE is in posted format, the 'pda' field goes across the
805 * 64-bit boundary, we need use cmpxchg16b to atomically update
806 * it. We only expose posted-interrupt when X86_FEATURE_CX16
807 * is supported. Actually, hardware platforms supporting PI
808 * should have X86_FEATURE_CX16 support, this has been confirmed
809 * with Intel hardware guys.
811 if (boot_cpu_has(X86_FEATURE_CX16))
812 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
814 for_each_iommu(iommu, drhd)
815 if (!cap_pi_support(iommu->cap)) {
816 intel_irq_remap_ops.capability &=
817 ~(1 << IRQ_POSTING_CAP);
823 static int __init intel_enable_irq_remapping(void)
825 struct dmar_drhd_unit *drhd;
826 struct intel_iommu *iommu;
830 * Setup Interrupt-remapping for all the DRHD's now.
832 for_each_iommu(iommu, drhd) {
833 if (!ir_pre_enabled(iommu))
834 iommu_enable_irq_remapping(iommu);
841 irq_remapping_enabled = 1;
843 set_irq_posting_cap();
845 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
847 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
850 intel_cleanup_irq_remapping();
854 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
855 struct intel_iommu *iommu,
856 struct acpi_dmar_hardware_unit *drhd)
858 struct acpi_dmar_pci_path *path;
860 int count, free = -1;
863 path = (struct acpi_dmar_pci_path *)(scope + 1);
864 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
865 / sizeof(struct acpi_dmar_pci_path);
867 while (--count > 0) {
869 * Access PCI directly due to the PCI
870 * subsystem isn't initialized yet.
872 bus = read_pci_config_byte(bus, path->device, path->function,
877 for (count = 0; count < MAX_HPET_TBS; count++) {
878 if (ir_hpet[count].iommu == iommu &&
879 ir_hpet[count].id == scope->enumeration_id)
881 else if (ir_hpet[count].iommu == NULL && free == -1)
885 pr_warn("Exceeded Max HPET blocks\n");
889 ir_hpet[free].iommu = iommu;
890 ir_hpet[free].id = scope->enumeration_id;
891 ir_hpet[free].bus = bus;
892 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
893 pr_info("HPET id %d under DRHD base 0x%Lx\n",
894 scope->enumeration_id, drhd->address);
899 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
900 struct intel_iommu *iommu,
901 struct acpi_dmar_hardware_unit *drhd)
903 struct acpi_dmar_pci_path *path;
905 int count, free = -1;
908 path = (struct acpi_dmar_pci_path *)(scope + 1);
909 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
910 / sizeof(struct acpi_dmar_pci_path);
912 while (--count > 0) {
914 * Access PCI directly due to the PCI
915 * subsystem isn't initialized yet.
917 bus = read_pci_config_byte(bus, path->device, path->function,
922 for (count = 0; count < MAX_IO_APICS; count++) {
923 if (ir_ioapic[count].iommu == iommu &&
924 ir_ioapic[count].id == scope->enumeration_id)
926 else if (ir_ioapic[count].iommu == NULL && free == -1)
930 pr_warn("Exceeded Max IO APICS\n");
934 ir_ioapic[free].bus = bus;
935 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
936 ir_ioapic[free].iommu = iommu;
937 ir_ioapic[free].id = scope->enumeration_id;
938 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
939 scope->enumeration_id, drhd->address, iommu->seq_id);
944 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
945 struct intel_iommu *iommu)
948 struct acpi_dmar_hardware_unit *drhd;
949 struct acpi_dmar_device_scope *scope;
952 drhd = (struct acpi_dmar_hardware_unit *)header;
953 start = (void *)(drhd + 1);
954 end = ((void *)drhd) + header->length;
956 while (start < end && ret == 0) {
958 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
959 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
960 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
961 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
962 start += scope->length;
968 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
972 for (i = 0; i < MAX_HPET_TBS; i++)
973 if (ir_hpet[i].iommu == iommu)
974 ir_hpet[i].iommu = NULL;
976 for (i = 0; i < MAX_IO_APICS; i++)
977 if (ir_ioapic[i].iommu == iommu)
978 ir_ioapic[i].iommu = NULL;
982 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
985 static int __init parse_ioapics_under_ir(void)
987 struct dmar_drhd_unit *drhd;
988 struct intel_iommu *iommu;
989 bool ir_supported = false;
992 for_each_iommu(iommu, drhd) {
995 if (!ecap_ir_support(iommu->ecap))
998 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
1002 ir_supported = true;
1008 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1009 int ioapic_id = mpc_ioapic_id(ioapic_idx);
1010 if (!map_ioapic_to_iommu(ioapic_id)) {
1011 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
1012 "interrupt remapping will be disabled\n",
1021 static int __init ir_dev_scope_init(void)
1025 if (!irq_remapping_enabled)
1028 down_write(&dmar_global_lock);
1029 ret = dmar_dev_scope_init();
1030 up_write(&dmar_global_lock);
1034 rootfs_initcall(ir_dev_scope_init);
1036 static void disable_irq_remapping(void)
1038 struct dmar_drhd_unit *drhd;
1039 struct intel_iommu *iommu = NULL;
1042 * Disable Interrupt-remapping for all the DRHD's now.
1044 for_each_iommu(iommu, drhd) {
1045 if (!ecap_ir_support(iommu->ecap))
1048 iommu_disable_irq_remapping(iommu);
1052 * Clear Posted-Interrupts capability.
1054 if (!disable_irq_post)
1055 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1058 static int reenable_irq_remapping(int eim)
1060 struct dmar_drhd_unit *drhd;
1062 struct intel_iommu *iommu = NULL;
1064 for_each_iommu(iommu, drhd)
1066 dmar_reenable_qi(iommu);
1069 * Setup Interrupt-remapping for all the DRHD's now.
1071 for_each_iommu(iommu, drhd) {
1072 if (!ecap_ir_support(iommu->ecap))
1075 /* Set up interrupt remapping for iommu.*/
1076 iommu_set_irq_remapping(iommu, eim);
1077 iommu_enable_irq_remapping(iommu);
1084 set_irq_posting_cap();
1090 * handle error condition gracefully here!
1095 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1097 memset(irte, 0, sizeof(*irte));
1100 irte->dst_mode = apic->irq_dest_mode;
1102 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1103 * actual level or edge trigger will be setup in the IO-APIC
1104 * RTE. This will help simplify level triggered irq migration.
1105 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1106 * irq migration in the presence of interrupt-remapping.
1108 irte->trigger_mode = 0;
1109 irte->dlvry_mode = apic->irq_delivery_mode;
1110 irte->vector = vector;
1111 irte->dest_id = IRTE_DEST(dest);
1112 irte->redir_hint = 1;
1115 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1120 switch (info->type) {
1121 case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT:
1122 return map_ioapic_to_ir(info->ioapic_id);
1123 case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT:
1124 return map_hpet_to_ir(info->hpet_id);
1125 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1126 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1127 return map_dev_to_ir(info->msi_dev);
1134 struct irq_remap_ops intel_irq_remap_ops = {
1135 .prepare = intel_prepare_irq_remapping,
1136 .enable = intel_enable_irq_remapping,
1137 .disable = disable_irq_remapping,
1138 .reenable = reenable_irq_remapping,
1139 .enable_faulting = enable_drhd_fault_handling,
1140 .get_ir_irq_domain = intel_get_irq_domain,
1141 .get_irq_domain = intel_get_irq_domain,
1144 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1146 struct intel_ir_data *ir_data = irqd->chip_data;
1147 struct irte *irte = &ir_data->irte_entry;
1148 struct irq_cfg *cfg = irqd_cfg(irqd);
1151 * Atomically updates the IRTE with the new destination, vector
1152 * and flushes the interrupt entry cache.
1154 irte->vector = cfg->vector;
1155 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1157 /* Update the hardware only if the interrupt is in remapped mode. */
1158 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1159 modify_irte(&ir_data->irq_2_iommu, irte);
1163 * Migrate the IO-APIC irq in the presence of intr-remapping.
1165 * For both level and edge triggered, irq migration is a simple atomic
1166 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1168 * For level triggered, we eliminate the io-apic RTE modification (with the
1169 * updated vector information), by using a virtual vector (io-apic pin number).
1170 * Real vector that is used for interrupting cpu will be coming from
1171 * the interrupt-remapping table entry.
1173 * As the migration is a simple atomic update of IRTE, the same mechanism
1174 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1177 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1180 struct irq_data *parent = data->parent_data;
1181 struct irq_cfg *cfg = irqd_cfg(data);
1184 ret = parent->chip->irq_set_affinity(parent, mask, force);
1185 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1188 intel_ir_reconfigure_irte(data, false);
1190 * After this point, all the interrupts will start arriving
1191 * at the new destination. So, time to cleanup the previous
1192 * vector allocation.
1194 send_cleanup_vector(cfg);
1196 return IRQ_SET_MASK_OK_DONE;
1199 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1200 struct msi_msg *msg)
1202 struct intel_ir_data *ir_data = irq_data->chip_data;
1204 *msg = ir_data->msi_entry;
1207 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1209 struct intel_ir_data *ir_data = data->chip_data;
1210 struct vcpu_data *vcpu_pi_info = info;
1212 /* stop posting interrupts, back to remapping mode */
1213 if (!vcpu_pi_info) {
1214 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1216 struct irte irte_pi;
1219 * We are not caching the posted interrupt entry. We
1220 * copy the data from the remapped entry and modify
1221 * the fields which are relevant for posted mode. The
1222 * cached remapped entry is used for switching back to
1225 memset(&irte_pi, 0, sizeof(irte_pi));
1226 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1228 /* Update the posted mode fields */
1230 irte_pi.p_urgent = 0;
1231 irte_pi.p_vector = vcpu_pi_info->vector;
1232 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1233 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1234 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1235 ~(-1UL << PDA_HIGH_BIT);
1237 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1243 static struct irq_chip intel_ir_chip = {
1245 .irq_ack = apic_ack_irq,
1246 .irq_set_affinity = intel_ir_set_affinity,
1247 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1248 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1251 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1252 struct irq_cfg *irq_cfg,
1253 struct irq_alloc_info *info,
1254 int index, int sub_handle)
1256 struct IR_IO_APIC_route_entry *entry;
1257 struct irte *irte = &data->irte_entry;
1258 struct msi_msg *msg = &data->msi_entry;
1260 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1261 switch (info->type) {
1262 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1263 /* Set source-id of interrupt request */
1264 set_ioapic_sid(irte, info->ioapic_id);
1265 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1266 info->ioapic_id, irte->present, irte->fpd,
1267 irte->dst_mode, irte->redir_hint,
1268 irte->trigger_mode, irte->dlvry_mode,
1269 irte->avail, irte->vector, irte->dest_id,
1270 irte->sid, irte->sq, irte->svt);
1272 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1273 info->ioapic_entry = NULL;
1274 memset(entry, 0, sizeof(*entry));
1275 entry->index2 = (index >> 15) & 0x1;
1278 entry->index = (index & 0x7fff);
1280 * IO-APIC RTE will be configured with virtual vector.
1281 * irq handler will do the explicit EOI to the io-apic.
1283 entry->vector = info->ioapic_pin;
1284 entry->mask = 0; /* enable IRQ */
1285 entry->trigger = info->ioapic_trigger;
1286 entry->polarity = info->ioapic_polarity;
1287 if (info->ioapic_trigger)
1288 entry->mask = 1; /* Mask level triggered irqs. */
1291 case X86_IRQ_ALLOC_TYPE_HPET:
1292 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1293 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1294 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1295 set_hpet_sid(irte, info->hpet_id);
1297 set_msi_sid(irte, info->msi_dev);
1299 msg->address_hi = MSI_ADDR_BASE_HI;
1300 msg->data = sub_handle;
1301 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1303 MSI_ADDR_IR_INDEX1(index) |
1304 MSI_ADDR_IR_INDEX2(index);
1313 static void intel_free_irq_resources(struct irq_domain *domain,
1314 unsigned int virq, unsigned int nr_irqs)
1316 struct irq_data *irq_data;
1317 struct intel_ir_data *data;
1318 struct irq_2_iommu *irq_iommu;
1319 unsigned long flags;
1321 for (i = 0; i < nr_irqs; i++) {
1322 irq_data = irq_domain_get_irq_data(domain, virq + i);
1323 if (irq_data && irq_data->chip_data) {
1324 data = irq_data->chip_data;
1325 irq_iommu = &data->irq_2_iommu;
1326 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1327 clear_entries(irq_iommu);
1328 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1329 irq_domain_reset_irq_data(irq_data);
1335 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1336 unsigned int virq, unsigned int nr_irqs,
1339 struct intel_iommu *iommu = domain->host_data;
1340 struct irq_alloc_info *info = arg;
1341 struct intel_ir_data *data, *ird;
1342 struct irq_data *irq_data;
1343 struct irq_cfg *irq_cfg;
1346 if (!info || !iommu)
1348 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
1349 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
1353 * With IRQ remapping enabled, don't need contiguous CPU vectors
1354 * to support multiple MSI interrupts.
1356 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
1357 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1359 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1364 data = kzalloc(sizeof(*data), GFP_KERNEL);
1366 goto out_free_parent;
1368 down_read(&dmar_global_lock);
1369 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1370 up_read(&dmar_global_lock);
1372 pr_warn("Failed to allocate IRTE\n");
1374 goto out_free_parent;
1377 for (i = 0; i < nr_irqs; i++) {
1378 irq_data = irq_domain_get_irq_data(domain, virq + i);
1379 irq_cfg = irqd_cfg(irq_data);
1380 if (!irq_data || !irq_cfg) {
1386 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1389 /* Initialize the common data */
1390 ird->irq_2_iommu = data->irq_2_iommu;
1391 ird->irq_2_iommu.sub_handle = i;
1396 irq_data->hwirq = (index << 16) + i;
1397 irq_data->chip_data = ird;
1398 irq_data->chip = &intel_ir_chip;
1399 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1400 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1405 intel_free_irq_resources(domain, virq, i);
1407 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1411 static void intel_irq_remapping_free(struct irq_domain *domain,
1412 unsigned int virq, unsigned int nr_irqs)
1414 intel_free_irq_resources(domain, virq, nr_irqs);
1415 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1418 static int intel_irq_remapping_activate(struct irq_domain *domain,
1419 struct irq_data *irq_data, bool reserve)
1421 intel_ir_reconfigure_irte(irq_data, true);
1425 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1426 struct irq_data *irq_data)
1428 struct intel_ir_data *data = irq_data->chip_data;
1431 memset(&entry, 0, sizeof(entry));
1432 modify_irte(&data->irq_2_iommu, &entry);
1435 static const struct irq_domain_ops intel_ir_domain_ops = {
1436 .alloc = intel_irq_remapping_alloc,
1437 .free = intel_irq_remapping_free,
1438 .activate = intel_irq_remapping_activate,
1439 .deactivate = intel_irq_remapping_deactivate,
1443 * Support of Interrupt Remapping Unit Hotplug
1445 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1448 int eim = x2apic_enabled();
1450 if (eim && !ecap_eim_support(iommu->ecap)) {
1451 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1452 iommu->reg_phys, iommu->ecap);
1456 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1457 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1462 /* TODO: check all IOAPICs are covered by IOMMU */
1464 /* Setup Interrupt-remapping now. */
1465 ret = intel_setup_irq_remapping(iommu);
1467 pr_err("Failed to setup irq remapping for %s\n",
1469 intel_teardown_irq_remapping(iommu);
1470 ir_remove_ioapic_hpet_scope(iommu);
1472 iommu_enable_irq_remapping(iommu);
1478 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1481 struct intel_iommu *iommu = dmaru->iommu;
1483 if (!irq_remapping_enabled)
1487 if (!ecap_ir_support(iommu->ecap))
1489 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1490 !cap_pi_support(iommu->cap))
1494 if (!iommu->ir_table)
1495 ret = dmar_ir_add(dmaru, iommu);
1497 if (iommu->ir_table) {
1498 if (!bitmap_empty(iommu->ir_table->bitmap,
1499 INTR_REMAP_TABLE_ENTRIES)) {
1502 iommu_disable_irq_remapping(iommu);
1503 intel_teardown_irq_remapping(iommu);
1504 ir_remove_ioapic_hpet_scope(iommu);