1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/intel-iommu.h>
14 #include <linux/acpi.h>
15 #include <linux/irqdomain.h>
16 #include <linux/crash_dump.h>
17 #include <asm/io_apic.h>
21 #include <asm/irq_remapping.h>
22 #include <asm/pci-direct.h>
24 #include "../irq_remapping.h"
32 struct intel_iommu *iommu;
34 unsigned int bus; /* PCI bus number */
35 unsigned int devfn; /* PCI devfn number */
39 struct intel_iommu *iommu;
46 struct intel_iommu *iommu;
53 struct intel_ir_data {
54 struct irq_2_iommu irq_2_iommu;
55 struct irte irte_entry;
57 struct msi_msg msi_entry;
61 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
62 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
64 static int __read_mostly eim_mode;
65 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
66 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
73 * ->iommu->register_lock
75 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
76 * in single-threaded environment with interrupt disabled, so no need to tabke
77 * the dmar_global_lock.
79 DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
80 static const struct irq_domain_ops intel_ir_domain_ops;
82 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
83 static int __init parse_ioapics_under_ir(void);
85 static bool ir_pre_enabled(struct intel_iommu *iommu)
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
92 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
95 static void init_ir_status(struct intel_iommu *iommu)
99 gsts = readl(iommu->reg + DMAR_GSTS_REG);
100 if (gsts & DMA_GSTS_IRES)
101 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
104 static int alloc_irte(struct intel_iommu *iommu,
105 struct irq_2_iommu *irq_iommu, u16 count)
107 struct ir_table *table = iommu->ir_table;
108 unsigned int mask = 0;
112 if (!count || !irq_iommu)
116 count = __roundup_pow_of_two(count);
120 if (mask > ecap_max_handle_mask(iommu->ecap)) {
121 pr_err("Requested mask %x exceeds the max invalidation handle"
122 " mask value %Lx\n", mask,
123 ecap_max_handle_mask(iommu->ecap));
127 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
128 index = bitmap_find_free_region(table->bitmap,
129 INTR_REMAP_TABLE_ENTRIES, mask);
131 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
133 irq_iommu->iommu = iommu;
134 irq_iommu->irte_index = index;
135 irq_iommu->sub_handle = 0;
136 irq_iommu->irte_mask = mask;
137 irq_iommu->mode = IRQ_REMAPPING;
139 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
144 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
148 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
154 return qi_submit_sync(iommu, &desc, 1, 0);
157 static int modify_irte(struct irq_2_iommu *irq_iommu,
158 struct irte *irte_modified)
160 struct intel_iommu *iommu;
168 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
170 iommu = irq_iommu->iommu;
172 index = irq_iommu->irte_index + irq_iommu->sub_handle;
173 irte = &iommu->ir_table->base[index];
175 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
176 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
179 ret = cmpxchg_double(&irte->low, &irte->high,
180 irte->low, irte->high,
181 irte_modified->low, irte_modified->high);
183 * We use cmpxchg16 to atomically update the 128-bit IRTE,
184 * and it cannot be updated by the hardware or other processors
185 * behind us, so the return value of cmpxchg16 should be the
186 * same as the old value.
192 set_64bit(&irte->low, irte_modified->low);
193 set_64bit(&irte->high, irte_modified->high);
195 __iommu_flush_cache(iommu, irte, sizeof(*irte));
197 rc = qi_flush_iec(iommu, index, 0);
199 /* Update iommu mode according to the IRTE mode */
200 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
201 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
206 static struct irq_domain *map_hpet_to_ir(u8 hpet_id)
210 for (i = 0; i < MAX_HPET_TBS; i++) {
211 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
212 return ir_hpet[i].iommu->ir_domain;
217 static struct intel_iommu *map_ioapic_to_iommu(int apic)
221 for (i = 0; i < MAX_IO_APICS; i++) {
222 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
223 return ir_ioapic[i].iommu;
228 static struct irq_domain *map_ioapic_to_ir(int apic)
230 struct intel_iommu *iommu = map_ioapic_to_iommu(apic);
232 return iommu ? iommu->ir_domain : NULL;
235 static struct irq_domain *map_dev_to_ir(struct pci_dev *dev)
237 struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev);
239 return drhd ? drhd->iommu->ir_msi_domain : NULL;
242 static int clear_entries(struct irq_2_iommu *irq_iommu)
244 struct irte *start, *entry, *end;
245 struct intel_iommu *iommu;
248 if (irq_iommu->sub_handle)
251 iommu = irq_iommu->iommu;
252 index = irq_iommu->irte_index;
254 start = iommu->ir_table->base + index;
255 end = start + (1 << irq_iommu->irte_mask);
257 for (entry = start; entry < end; entry++) {
258 set_64bit(&entry->low, 0);
259 set_64bit(&entry->high, 0);
261 bitmap_release_region(iommu->ir_table->bitmap, index,
262 irq_iommu->irte_mask);
264 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
268 * source validation type
270 #define SVT_NO_VERIFY 0x0 /* no verification is required */
271 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
272 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
275 * source-id qualifier
277 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
278 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
279 * the third least significant bit
281 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
282 * the second and third least significant bits
284 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
285 * the least three significant bits
289 * set SVT, SQ and SID fields of irte to verify
290 * source ids of interrupt requests
292 static void set_irte_sid(struct irte *irte, unsigned int svt,
293 unsigned int sq, unsigned int sid)
295 if (disable_sourceid_checking)
303 * Set an IRTE to match only the bus number. Interrupt requests that reference
304 * this IRTE must have a requester-id whose bus number is between or equal
305 * to the start_bus and end_bus arguments.
307 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
308 unsigned int end_bus)
310 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
311 (start_bus << 8) | end_bus);
314 static int set_ioapic_sid(struct irte *irte, int apic)
322 down_read(&dmar_global_lock);
323 for (i = 0; i < MAX_IO_APICS; i++) {
324 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
325 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
329 up_read(&dmar_global_lock);
332 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
336 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
341 static int set_hpet_sid(struct irte *irte, u8 id)
349 down_read(&dmar_global_lock);
350 for (i = 0; i < MAX_HPET_TBS; i++) {
351 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
352 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
356 up_read(&dmar_global_lock);
359 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
364 * Should really use SQ_ALL_16. Some platforms are broken.
365 * While we figure out the right quirks for these broken platforms, use
366 * SQ_13_IGNORE_3 for now.
368 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
373 struct set_msi_sid_data {
374 struct pci_dev *pdev;
380 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
382 struct set_msi_sid_data *data = opaque;
384 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
385 data->busmatch_count++;
394 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
396 struct set_msi_sid_data data;
402 data.busmatch_count = 0;
403 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
406 * DMA alias provides us with a PCI device and alias. The only case
407 * where the it will return an alias on a different bus than the
408 * device is the case of a PCIe-to-PCI bridge, where the alias is for
409 * the subordinate bus. In this case we can only verify the bus.
411 * If there are multiple aliases, all with the same bus number,
412 * then all we can do is verify the bus. This is typical in NTB
413 * hardware which use proxy IDs where the device will generate traffic
414 * from multiple devfn numbers on the same bus.
416 * If the alias device is on a different bus than our source device
417 * then we have a topology based alias, use it.
419 * Otherwise, the alias is for a device DMA quirk and we cannot
420 * assume that MSI uses the same requester ID. Therefore use the
423 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
424 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
426 else if (data.count >= 2 && data.busmatch_count == data.count)
427 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
428 else if (data.pdev->bus->number != dev->bus->number)
429 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
431 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
437 static int iommu_load_old_irte(struct intel_iommu *iommu)
439 struct irte *old_ir_table;
440 phys_addr_t irt_phys;
445 /* Check whether the old ir-table has the same size as ours */
446 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
447 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
448 != INTR_REMAP_TABLE_REG_SIZE)
451 irt_phys = irta & VTD_PAGE_MASK;
452 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
454 /* Map the old IR table */
455 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
460 memcpy(iommu->ir_table->base, old_ir_table, size);
462 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
465 * Now check the table for used entries and mark those as
466 * allocated in the bitmap
468 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
469 if (iommu->ir_table->base[i].present)
470 bitmap_set(iommu->ir_table->bitmap, i, 1);
473 memunmap(old_ir_table);
479 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
485 addr = virt_to_phys((void *)iommu->ir_table->base);
487 raw_spin_lock_irqsave(&iommu->register_lock, flags);
489 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
490 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
492 /* Set interrupt-remapping table pointer */
493 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
495 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
496 readl, (sts & DMA_GSTS_IRTPS), sts);
497 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
500 * Global invalidation of interrupt entry cache to make sure the
501 * hardware uses the new irq remapping table.
503 qi_global_iec(iommu);
506 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
511 raw_spin_lock_irqsave(&iommu->register_lock, flags);
513 /* Enable interrupt-remapping */
514 iommu->gcmd |= DMA_GCMD_IRE;
515 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
516 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
517 readl, (sts & DMA_GSTS_IRES), sts);
519 /* Block compatibility-format MSIs */
520 if (sts & DMA_GSTS_CFIS) {
521 iommu->gcmd &= ~DMA_GCMD_CFI;
522 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
523 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
524 readl, !(sts & DMA_GSTS_CFIS), sts);
528 * With CFI clear in the Global Command register, we should be
529 * protected from dangerous (i.e. compatibility) interrupts
530 * regardless of x2apic status. Check just to be sure.
532 if (sts & DMA_GSTS_CFIS)
534 "Compatibility-format IRQs enabled despite intr remapping;\n"
535 "you are vulnerable to IRQ injection.\n");
537 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
540 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
542 struct ir_table *ir_table;
543 struct fwnode_handle *fn;
544 unsigned long *bitmap;
550 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
554 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
555 INTR_REMAP_PAGE_ORDER);
557 pr_err("IR%d: failed to allocate pages of order %d\n",
558 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
562 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC);
563 if (bitmap == NULL) {
564 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
568 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
570 goto out_free_bitmap;
573 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
574 0, INTR_REMAP_TABLE_ENTRIES,
575 fn, &intel_ir_domain_ops,
577 if (!iommu->ir_domain) {
578 irq_domain_free_fwnode(fn);
579 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
580 goto out_free_bitmap;
582 iommu->ir_msi_domain =
583 arch_create_remap_msi_irq_domain(iommu->ir_domain,
587 ir_table->base = page_address(pages);
588 ir_table->bitmap = bitmap;
589 iommu->ir_table = ir_table;
592 * If the queued invalidation is already initialized,
593 * shouldn't disable it.
597 * Clear previous faults.
599 dmar_fault(-1, iommu);
600 dmar_disable_qi(iommu);
602 if (dmar_enable_qi(iommu)) {
603 pr_err("Failed to enable queued invalidation\n");
604 goto out_free_bitmap;
608 init_ir_status(iommu);
610 if (ir_pre_enabled(iommu)) {
611 if (!is_kdump_kernel()) {
612 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
614 clear_ir_pre_enabled(iommu);
615 iommu_disable_irq_remapping(iommu);
616 } else if (iommu_load_old_irte(iommu))
617 pr_err("Failed to copy IR table for %s from previous kernel\n",
620 pr_info("Copied IR table for %s from previous kernel\n",
624 iommu_set_irq_remapping(iommu, eim_mode);
631 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
635 iommu->ir_table = NULL;
640 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
642 struct fwnode_handle *fn;
644 if (iommu && iommu->ir_table) {
645 if (iommu->ir_msi_domain) {
646 fn = iommu->ir_msi_domain->fwnode;
648 irq_domain_remove(iommu->ir_msi_domain);
649 irq_domain_free_fwnode(fn);
650 iommu->ir_msi_domain = NULL;
652 if (iommu->ir_domain) {
653 fn = iommu->ir_domain->fwnode;
655 irq_domain_remove(iommu->ir_domain);
656 irq_domain_free_fwnode(fn);
657 iommu->ir_domain = NULL;
659 free_pages((unsigned long)iommu->ir_table->base,
660 INTR_REMAP_PAGE_ORDER);
661 bitmap_free(iommu->ir_table->bitmap);
662 kfree(iommu->ir_table);
663 iommu->ir_table = NULL;
668 * Disable Interrupt Remapping.
670 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
675 if (!ecap_ir_support(iommu->ecap))
679 * global invalidation of interrupt entry cache before disabling
680 * interrupt-remapping.
682 qi_global_iec(iommu);
684 raw_spin_lock_irqsave(&iommu->register_lock, flags);
686 sts = readl(iommu->reg + DMAR_GSTS_REG);
687 if (!(sts & DMA_GSTS_IRES))
690 iommu->gcmd &= ~DMA_GCMD_IRE;
691 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
693 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
694 readl, !(sts & DMA_GSTS_IRES), sts);
697 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
700 static int __init dmar_x2apic_optout(void)
702 struct acpi_table_dmar *dmar;
703 dmar = (struct acpi_table_dmar *)dmar_tbl;
704 if (!dmar || no_x2apic_optout)
706 return dmar->flags & DMAR_X2APIC_OPT_OUT;
709 static void __init intel_cleanup_irq_remapping(void)
711 struct dmar_drhd_unit *drhd;
712 struct intel_iommu *iommu;
714 for_each_iommu(iommu, drhd) {
715 if (ecap_ir_support(iommu->ecap)) {
716 iommu_disable_irq_remapping(iommu);
717 intel_teardown_irq_remapping(iommu);
721 if (x2apic_supported())
722 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
725 static int __init intel_prepare_irq_remapping(void)
727 struct dmar_drhd_unit *drhd;
728 struct intel_iommu *iommu;
731 if (irq_remap_broken) {
732 pr_warn("This system BIOS has enabled interrupt remapping\n"
733 "on a chipset that contains an erratum making that\n"
734 "feature unstable. To maintain system stability\n"
735 "interrupt remapping is being disabled. Please\n"
736 "contact your BIOS vendor for an update\n");
737 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
741 if (dmar_table_init() < 0)
744 if (!dmar_ir_support())
747 if (parse_ioapics_under_ir()) {
748 pr_info("Not enabling interrupt remapping\n");
752 /* First make sure all IOMMUs support IRQ remapping */
753 for_each_iommu(iommu, drhd)
754 if (!ecap_ir_support(iommu->ecap))
757 /* Detect remapping mode: lapic or x2apic */
758 if (x2apic_supported()) {
759 eim = !dmar_x2apic_optout();
761 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
762 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
766 for_each_iommu(iommu, drhd) {
767 if (eim && !ecap_eim_support(iommu->ecap)) {
768 pr_info("%s does not support EIM\n", iommu->name);
775 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
777 /* Do the initializations early */
778 for_each_iommu(iommu, drhd) {
779 if (intel_setup_irq_remapping(iommu)) {
780 pr_err("Failed to setup irq remapping for %s\n",
789 intel_cleanup_irq_remapping();
794 * Set Posted-Interrupts capability.
796 static inline void set_irq_posting_cap(void)
798 struct dmar_drhd_unit *drhd;
799 struct intel_iommu *iommu;
801 if (!disable_irq_post) {
803 * If IRTE is in posted format, the 'pda' field goes across the
804 * 64-bit boundary, we need use cmpxchg16b to atomically update
805 * it. We only expose posted-interrupt when X86_FEATURE_CX16
806 * is supported. Actually, hardware platforms supporting PI
807 * should have X86_FEATURE_CX16 support, this has been confirmed
808 * with Intel hardware guys.
810 if (boot_cpu_has(X86_FEATURE_CX16))
811 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
813 for_each_iommu(iommu, drhd)
814 if (!cap_pi_support(iommu->cap)) {
815 intel_irq_remap_ops.capability &=
816 ~(1 << IRQ_POSTING_CAP);
822 static int __init intel_enable_irq_remapping(void)
824 struct dmar_drhd_unit *drhd;
825 struct intel_iommu *iommu;
829 * Setup Interrupt-remapping for all the DRHD's now.
831 for_each_iommu(iommu, drhd) {
832 if (!ir_pre_enabled(iommu))
833 iommu_enable_irq_remapping(iommu);
840 irq_remapping_enabled = 1;
842 set_irq_posting_cap();
844 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
846 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
849 intel_cleanup_irq_remapping();
853 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
854 struct intel_iommu *iommu,
855 struct acpi_dmar_hardware_unit *drhd)
857 struct acpi_dmar_pci_path *path;
859 int count, free = -1;
862 path = (struct acpi_dmar_pci_path *)(scope + 1);
863 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
864 / sizeof(struct acpi_dmar_pci_path);
866 while (--count > 0) {
868 * Access PCI directly due to the PCI
869 * subsystem isn't initialized yet.
871 bus = read_pci_config_byte(bus, path->device, path->function,
876 for (count = 0; count < MAX_HPET_TBS; count++) {
877 if (ir_hpet[count].iommu == iommu &&
878 ir_hpet[count].id == scope->enumeration_id)
880 else if (ir_hpet[count].iommu == NULL && free == -1)
884 pr_warn("Exceeded Max HPET blocks\n");
888 ir_hpet[free].iommu = iommu;
889 ir_hpet[free].id = scope->enumeration_id;
890 ir_hpet[free].bus = bus;
891 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
892 pr_info("HPET id %d under DRHD base 0x%Lx\n",
893 scope->enumeration_id, drhd->address);
898 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
899 struct intel_iommu *iommu,
900 struct acpi_dmar_hardware_unit *drhd)
902 struct acpi_dmar_pci_path *path;
904 int count, free = -1;
907 path = (struct acpi_dmar_pci_path *)(scope + 1);
908 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
909 / sizeof(struct acpi_dmar_pci_path);
911 while (--count > 0) {
913 * Access PCI directly due to the PCI
914 * subsystem isn't initialized yet.
916 bus = read_pci_config_byte(bus, path->device, path->function,
921 for (count = 0; count < MAX_IO_APICS; count++) {
922 if (ir_ioapic[count].iommu == iommu &&
923 ir_ioapic[count].id == scope->enumeration_id)
925 else if (ir_ioapic[count].iommu == NULL && free == -1)
929 pr_warn("Exceeded Max IO APICS\n");
933 ir_ioapic[free].bus = bus;
934 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
935 ir_ioapic[free].iommu = iommu;
936 ir_ioapic[free].id = scope->enumeration_id;
937 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
938 scope->enumeration_id, drhd->address, iommu->seq_id);
943 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
944 struct intel_iommu *iommu)
947 struct acpi_dmar_hardware_unit *drhd;
948 struct acpi_dmar_device_scope *scope;
951 drhd = (struct acpi_dmar_hardware_unit *)header;
952 start = (void *)(drhd + 1);
953 end = ((void *)drhd) + header->length;
955 while (start < end && ret == 0) {
957 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
958 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
959 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
960 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
961 start += scope->length;
967 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
971 for (i = 0; i < MAX_HPET_TBS; i++)
972 if (ir_hpet[i].iommu == iommu)
973 ir_hpet[i].iommu = NULL;
975 for (i = 0; i < MAX_IO_APICS; i++)
976 if (ir_ioapic[i].iommu == iommu)
977 ir_ioapic[i].iommu = NULL;
981 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
984 static int __init parse_ioapics_under_ir(void)
986 struct dmar_drhd_unit *drhd;
987 struct intel_iommu *iommu;
988 bool ir_supported = false;
991 for_each_iommu(iommu, drhd) {
994 if (!ecap_ir_support(iommu->ecap))
997 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
1001 ir_supported = true;
1007 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1008 int ioapic_id = mpc_ioapic_id(ioapic_idx);
1009 if (!map_ioapic_to_iommu(ioapic_id)) {
1010 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
1011 "interrupt remapping will be disabled\n",
1020 static int __init ir_dev_scope_init(void)
1024 if (!irq_remapping_enabled)
1027 down_write(&dmar_global_lock);
1028 ret = dmar_dev_scope_init();
1029 up_write(&dmar_global_lock);
1033 rootfs_initcall(ir_dev_scope_init);
1035 static void disable_irq_remapping(void)
1037 struct dmar_drhd_unit *drhd;
1038 struct intel_iommu *iommu = NULL;
1041 * Disable Interrupt-remapping for all the DRHD's now.
1043 for_each_iommu(iommu, drhd) {
1044 if (!ecap_ir_support(iommu->ecap))
1047 iommu_disable_irq_remapping(iommu);
1051 * Clear Posted-Interrupts capability.
1053 if (!disable_irq_post)
1054 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1057 static int reenable_irq_remapping(int eim)
1059 struct dmar_drhd_unit *drhd;
1061 struct intel_iommu *iommu = NULL;
1063 for_each_iommu(iommu, drhd)
1065 dmar_reenable_qi(iommu);
1068 * Setup Interrupt-remapping for all the DRHD's now.
1070 for_each_iommu(iommu, drhd) {
1071 if (!ecap_ir_support(iommu->ecap))
1074 /* Set up interrupt remapping for iommu.*/
1075 iommu_set_irq_remapping(iommu, eim);
1076 iommu_enable_irq_remapping(iommu);
1083 set_irq_posting_cap();
1089 * handle error condition gracefully here!
1095 * Store the MSI remapping domain pointer in the device if enabled.
1097 * This is called from dmar_pci_bus_add_dev() so it works even when DMA
1098 * remapping is disabled. Only update the pointer if the device is not
1099 * already handled by a non default PCI/MSI interrupt domain. This protects
1102 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info)
1104 if (!irq_remapping_enabled || pci_dev_has_special_msi_domain(info->dev))
1107 dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev));
1110 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1112 memset(irte, 0, sizeof(*irte));
1115 irte->dst_mode = apic->dest_mode_logical;
1117 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1118 * actual level or edge trigger will be setup in the IO-APIC
1119 * RTE. This will help simplify level triggered irq migration.
1120 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1121 * irq migration in the presence of interrupt-remapping.
1123 irte->trigger_mode = 0;
1124 irte->dlvry_mode = apic->delivery_mode;
1125 irte->vector = vector;
1126 irte->dest_id = IRTE_DEST(dest);
1127 irte->redir_hint = 1;
1130 struct irq_remap_ops intel_irq_remap_ops = {
1131 .prepare = intel_prepare_irq_remapping,
1132 .enable = intel_enable_irq_remapping,
1133 .disable = disable_irq_remapping,
1134 .reenable = reenable_irq_remapping,
1135 .enable_faulting = enable_drhd_fault_handling,
1138 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1140 struct intel_ir_data *ir_data = irqd->chip_data;
1141 struct irte *irte = &ir_data->irte_entry;
1142 struct irq_cfg *cfg = irqd_cfg(irqd);
1145 * Atomically updates the IRTE with the new destination, vector
1146 * and flushes the interrupt entry cache.
1148 irte->vector = cfg->vector;
1149 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1151 /* Update the hardware only if the interrupt is in remapped mode. */
1152 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1153 modify_irte(&ir_data->irq_2_iommu, irte);
1157 * Migrate the IO-APIC irq in the presence of intr-remapping.
1159 * For both level and edge triggered, irq migration is a simple atomic
1160 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1162 * For level triggered, we eliminate the io-apic RTE modification (with the
1163 * updated vector information), by using a virtual vector (io-apic pin number).
1164 * Real vector that is used for interrupting cpu will be coming from
1165 * the interrupt-remapping table entry.
1167 * As the migration is a simple atomic update of IRTE, the same mechanism
1168 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1171 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1174 struct irq_data *parent = data->parent_data;
1175 struct irq_cfg *cfg = irqd_cfg(data);
1178 ret = parent->chip->irq_set_affinity(parent, mask, force);
1179 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1182 intel_ir_reconfigure_irte(data, false);
1184 * After this point, all the interrupts will start arriving
1185 * at the new destination. So, time to cleanup the previous
1186 * vector allocation.
1188 send_cleanup_vector(cfg);
1190 return IRQ_SET_MASK_OK_DONE;
1193 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1194 struct msi_msg *msg)
1196 struct intel_ir_data *ir_data = irq_data->chip_data;
1198 *msg = ir_data->msi_entry;
1201 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1203 struct intel_ir_data *ir_data = data->chip_data;
1204 struct vcpu_data *vcpu_pi_info = info;
1206 /* stop posting interrupts, back to remapping mode */
1207 if (!vcpu_pi_info) {
1208 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1210 struct irte irte_pi;
1213 * We are not caching the posted interrupt entry. We
1214 * copy the data from the remapped entry and modify
1215 * the fields which are relevant for posted mode. The
1216 * cached remapped entry is used for switching back to
1219 memset(&irte_pi, 0, sizeof(irte_pi));
1220 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1222 /* Update the posted mode fields */
1224 irte_pi.p_urgent = 0;
1225 irte_pi.p_vector = vcpu_pi_info->vector;
1226 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1227 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1228 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1229 ~(-1UL << PDA_HIGH_BIT);
1231 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1237 static struct irq_chip intel_ir_chip = {
1239 .irq_ack = apic_ack_irq,
1240 .irq_set_affinity = intel_ir_set_affinity,
1241 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1242 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1245 static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle)
1247 memset(msg, 0, sizeof(*msg));
1249 msg->arch_addr_lo.dmar_base_address = X86_MSI_BASE_ADDRESS_LOW;
1250 msg->arch_addr_lo.dmar_subhandle_valid = true;
1251 msg->arch_addr_lo.dmar_format = true;
1252 msg->arch_addr_lo.dmar_index_0_14 = index & 0x7FFF;
1253 msg->arch_addr_lo.dmar_index_15 = !!(index & 0x8000);
1255 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
1257 msg->arch_data.dmar_subhandle = subhandle;
1260 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1261 struct irq_cfg *irq_cfg,
1262 struct irq_alloc_info *info,
1263 int index, int sub_handle)
1265 struct irte *irte = &data->irte_entry;
1267 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1269 switch (info->type) {
1270 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1271 /* Set source-id of interrupt request */
1272 set_ioapic_sid(irte, info->devid);
1273 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1274 info->devid, irte->present, irte->fpd,
1275 irte->dst_mode, irte->redir_hint,
1276 irte->trigger_mode, irte->dlvry_mode,
1277 irte->avail, irte->vector, irte->dest_id,
1278 irte->sid, irte->sq, irte->svt);
1279 sub_handle = info->ioapic.pin;
1281 case X86_IRQ_ALLOC_TYPE_HPET:
1282 set_hpet_sid(irte, info->devid);
1284 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1285 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1286 set_msi_sid(irte, msi_desc_to_pci_dev(info->desc));
1292 fill_msi_msg(&data->msi_entry, index, sub_handle);
1295 static void intel_free_irq_resources(struct irq_domain *domain,
1296 unsigned int virq, unsigned int nr_irqs)
1298 struct irq_data *irq_data;
1299 struct intel_ir_data *data;
1300 struct irq_2_iommu *irq_iommu;
1301 unsigned long flags;
1303 for (i = 0; i < nr_irqs; i++) {
1304 irq_data = irq_domain_get_irq_data(domain, virq + i);
1305 if (irq_data && irq_data->chip_data) {
1306 data = irq_data->chip_data;
1307 irq_iommu = &data->irq_2_iommu;
1308 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1309 clear_entries(irq_iommu);
1310 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1311 irq_domain_reset_irq_data(irq_data);
1317 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1318 unsigned int virq, unsigned int nr_irqs,
1321 struct intel_iommu *iommu = domain->host_data;
1322 struct irq_alloc_info *info = arg;
1323 struct intel_ir_data *data, *ird;
1324 struct irq_data *irq_data;
1325 struct irq_cfg *irq_cfg;
1328 if (!info || !iommu)
1330 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
1331 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
1335 * With IRQ remapping enabled, don't need contiguous CPU vectors
1336 * to support multiple MSI interrupts.
1338 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
1339 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1341 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1346 data = kzalloc(sizeof(*data), GFP_KERNEL);
1348 goto out_free_parent;
1350 down_read(&dmar_global_lock);
1351 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1352 up_read(&dmar_global_lock);
1354 pr_warn("Failed to allocate IRTE\n");
1356 goto out_free_parent;
1359 for (i = 0; i < nr_irqs; i++) {
1360 irq_data = irq_domain_get_irq_data(domain, virq + i);
1361 irq_cfg = irqd_cfg(irq_data);
1362 if (!irq_data || !irq_cfg) {
1368 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1371 /* Initialize the common data */
1372 ird->irq_2_iommu = data->irq_2_iommu;
1373 ird->irq_2_iommu.sub_handle = i;
1378 irq_data->hwirq = (index << 16) + i;
1379 irq_data->chip_data = ird;
1380 irq_data->chip = &intel_ir_chip;
1381 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1382 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1387 intel_free_irq_resources(domain, virq, i);
1389 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1393 static void intel_irq_remapping_free(struct irq_domain *domain,
1394 unsigned int virq, unsigned int nr_irqs)
1396 intel_free_irq_resources(domain, virq, nr_irqs);
1397 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1400 static int intel_irq_remapping_activate(struct irq_domain *domain,
1401 struct irq_data *irq_data, bool reserve)
1403 intel_ir_reconfigure_irte(irq_data, true);
1407 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1408 struct irq_data *irq_data)
1410 struct intel_ir_data *data = irq_data->chip_data;
1413 memset(&entry, 0, sizeof(entry));
1414 modify_irte(&data->irq_2_iommu, &entry);
1417 static int intel_irq_remapping_select(struct irq_domain *d,
1418 struct irq_fwspec *fwspec,
1419 enum irq_domain_bus_token bus_token)
1421 if (x86_fwspec_is_ioapic(fwspec))
1422 return d == map_ioapic_to_ir(fwspec->param[0]);
1423 else if (x86_fwspec_is_hpet(fwspec))
1424 return d == map_hpet_to_ir(fwspec->param[0]);
1429 static const struct irq_domain_ops intel_ir_domain_ops = {
1430 .select = intel_irq_remapping_select,
1431 .alloc = intel_irq_remapping_alloc,
1432 .free = intel_irq_remapping_free,
1433 .activate = intel_irq_remapping_activate,
1434 .deactivate = intel_irq_remapping_deactivate,
1438 * Support of Interrupt Remapping Unit Hotplug
1440 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1443 int eim = x2apic_enabled();
1445 if (eim && !ecap_eim_support(iommu->ecap)) {
1446 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1447 iommu->reg_phys, iommu->ecap);
1451 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1452 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1457 /* TODO: check all IOAPICs are covered by IOMMU */
1459 /* Setup Interrupt-remapping now. */
1460 ret = intel_setup_irq_remapping(iommu);
1462 pr_err("Failed to setup irq remapping for %s\n",
1464 intel_teardown_irq_remapping(iommu);
1465 ir_remove_ioapic_hpet_scope(iommu);
1467 iommu_enable_irq_remapping(iommu);
1473 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1476 struct intel_iommu *iommu = dmaru->iommu;
1478 if (!irq_remapping_enabled)
1482 if (!ecap_ir_support(iommu->ecap))
1484 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1485 !cap_pi_support(iommu->cap))
1489 if (!iommu->ir_table)
1490 ret = dmar_ir_add(dmaru, iommu);
1492 if (iommu->ir_table) {
1493 if (!bitmap_empty(iommu->ir_table->bitmap,
1494 INTR_REMAP_TABLE_ENTRIES)) {
1497 iommu_disable_irq_remapping(iommu);
1498 intel_teardown_irq_remapping(iommu);
1499 ir_remove_ioapic_hpet_scope(iommu);