drivers/iommu/dmar.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2006, Intel Corporation.
   4  *
   5  * Copyright (C) 2006-2008 Intel Corporation
   6  * Author: Ashok Raj <ashok.raj@intel.com>
   7  * Author: Shaohua Li <shaohua.li@intel.com>
   8  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
   9  *
  10  * This file implements early detection/parsing of Remapping Devices
  11  * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
  12  * tables.
  13  *
  14  * These routines are used by both DMA-remapping and Interrupt-remapping
  15  */
  16
  17 #define pr_fmt(fmt)     "DMAR: " fmt
  18
  19 #include <linux/pci.h>
  20 #include <linux/dmar.h>
  21 #include <linux/iova.h>
  22 #include <linux/intel-iommu.h>
  23 #include <linux/timer.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/tboot.h>
  27 #include <linux/dmi.h>
  28 #include <linux/slab.h>
  29 #include <linux/iommu.h>
  30 #include <linux/numa.h>
  31 #include <linux/limits.h>
  32 #include <asm/irq_remapping.h>
  33 #include <asm/iommu_table.h>
  34
  35 #include "irq_remapping.h"
  36
  37 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
  38 struct dmar_res_callback {
  39         dmar_res_handler_t      cb[ACPI_DMAR_TYPE_RESERVED];
  40         void                    *arg[ACPI_DMAR_TYPE_RESERVED];
  41         bool                    ignore_unhandled;
  42         bool                    print_entry;
  43 };
  44
  45 /*
  46  * Assumptions:
  47  * 1) The hotplug framework guarentees that DMAR unit will be hot-added
  48  *    before IO devices managed by that unit.
  49  * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
  50  *    after IO devices managed by that unit.
  51  * 3) Hotplug events are rare.
  52  *
  53  * Locking rules for DMA and interrupt remapping related global data structures:
  54  * 1) Use dmar_global_lock in process context
  55  * 2) Use RCU in interrupt context
  56  */
  57 DECLARE_RWSEM(dmar_global_lock);
  58 LIST_HEAD(dmar_drhd_units);
  59
  60 struct acpi_table_header * __initdata dmar_tbl;
  61 static int dmar_dev_scope_status = 1;
  62 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
  63
  64 static int alloc_iommu(struct dmar_drhd_unit *drhd);
  65 static void free_iommu(struct intel_iommu *iommu);
  66
  67 extern const struct iommu_ops intel_iommu_ops;
  68
  69 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
  70 {
  71         /*
  72          * add INCLUDE_ALL at the tail, so scan the list will find it at
  73          * the very end.
  74          */
  75         if (drhd->include_all)
  76                 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
  77         else
  78                 list_add_rcu(&drhd->list, &dmar_drhd_units);
  79 }
  80
  81 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
  82 {
  83         struct acpi_dmar_device_scope *scope;
  84
  85         *cnt = 0;
  86         while (start < end) {
  87                 scope = start;
  88                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
  89                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
  90                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
  91                         (*cnt)++;
  92                 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
  93                         scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
  94                         pr_warn("Unsupported device scope\n");
  95                 }
  96                 start += scope->length;
  97         }
  98         if (*cnt == 0)
  99                 return NULL;
 100
 101         return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
 102 }
 103
 104 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
 105 {
 106         int i;
 107         struct device *tmp_dev;
 108
 109         if (*devices && *cnt) {
 110                 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
 111                         put_device(tmp_dev);
 112                 kfree(*devices);
 113         }
 114
 115         *devices = NULL;
 116         *cnt = 0;
 117 }
 118
 119 /* Optimize out kzalloc()/kfree() for normal cases */
 120 static char dmar_pci_notify_info_buf[64];
 121
 122 static struct dmar_pci_notify_info *
 123 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
 124 {
 125         int level = 0;
 126         size_t size;
 127         struct pci_dev *tmp;
 128         struct dmar_pci_notify_info *info;
 129
 130         BUG_ON(dev->is_virtfn);
 131
 132         /*
 133          * Ignore devices that have a domain number higher than what can
 134          * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000
 135          */
 136         if (pci_domain_nr(dev->bus) > U16_MAX)
 137                 return NULL;
 138
 139         /* Only generate path[] for device addition event */
 140         if (event == BUS_NOTIFY_ADD_DEVICE)
 141                 for (tmp = dev; tmp; tmp = tmp->bus->self)
 142                         level++;
 143
 144         size = struct_size(info, path, level);
 145         if (size <= sizeof(dmar_pci_notify_info_buf)) {
 146                 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
 147         } else {
 148                 info = kzalloc(size, GFP_KERNEL);
 149                 if (!info) {
 150                         pr_warn("Out of memory when allocating notify_info "
 151                                 "for %s.\n", pci_name(dev));
 152                         if (dmar_dev_scope_status == 0)
 153                                 dmar_dev_scope_status = -ENOMEM;
 154                         return NULL;
 155                 }
 156         }
 157
 158         info->event = event;
 159         info->dev = dev;
 160         info->seg = pci_domain_nr(dev->bus);
 161         info->level = level;
 162         if (event == BUS_NOTIFY_ADD_DEVICE) {
 163                 for (tmp = dev; tmp; tmp = tmp->bus->self) {
 164                         level--;
 165                         info->path[level].bus = tmp->bus->number;
 166                         info->path[level].device = PCI_SLOT(tmp->devfn);
 167                         info->path[level].function = PCI_FUNC(tmp->devfn);
 168                         if (pci_is_root_bus(tmp->bus))
 169                                 info->bus = tmp->bus->number;
 170                 }
 171         }
 172
 173         return info;
 174 }
 175
 176 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
 177 {
 178         if ((void *)info != dmar_pci_notify_info_buf)
 179                 kfree(info);
 180 }
 181
 182 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
 183                                 struct acpi_dmar_pci_path *path, int count)
 184 {
 185         int i;
 186
 187         if (info->bus != bus)
 188                 goto fallback;
 189         if (info->level != count)
 190                 goto fallback;
 191
 192         for (i = 0; i < count; i++) {
 193                 if (path[i].device != info->path[i].device ||
 194                     path[i].function != info->path[i].function)
 195                         goto fallback;
 196         }
 197
 198         return true;
 199
 200 fallback:
 201
 202         if (count != 1)
 203                 return false;
 204
 205         i = info->level - 1;
 206         if (bus              == info->path[i].bus &&
 207             path[0].device   == info->path[i].device &&
 208             path[0].function == info->path[i].function) {
 209                 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
 210                         bus, path[0].device, path[0].function);
 211                 return true;
 212         }
 213
 214         return false;
 215 }
 216
 217 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
 218 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
 219                           void *start, void*end, u16 segment,
 220                           struct dmar_dev_scope *devices,
 221                           int devices_cnt)
 222 {
 223         int i, level;
 224         struct device *tmp, *dev = &info->dev->dev;
 225         struct acpi_dmar_device_scope *scope;
 226         struct acpi_dmar_pci_path *path;
 227
 228         if (segment != info->seg)
 229                 return 0;
 230
 231         for (; start < end; start += scope->length) {
 232                 scope = start;
 233                 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 234                     scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 235                         continue;
 236
 237                 path = (struct acpi_dmar_pci_path *)(scope + 1);
 238                 level = (scope->length - sizeof(*scope)) / sizeof(*path);
 239                 if (!dmar_match_pci_path(info, scope->bus, path, level))
 240                         continue;
 241
 242                 /*
 243                  * We expect devices with endpoint scope to have normal PCI
 244                  * headers, and devices with bridge scope to have bridge PCI
 245                  * headers.  However PCI NTB devices may be listed in the
 246                  * DMAR table with bridge scope, even though they have a
 247                  * normal PCI header.  NTB devices are identified by class
 248                  * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
 249                  * for this special case.
 250                  */
 251                 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 252                      info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
 253                     (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
 254                      (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
 255                       info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) {
 256                         pr_warn("Device scope type does not match for %s\n",
 257                                 pci_name(info->dev));
 258                         return -EINVAL;
 259                 }
 260
 261                 for_each_dev_scope(devices, devices_cnt, i, tmp)
 262                         if (tmp == NULL) {
 263                                 devices[i].bus = info->dev->bus->number;
 264                                 devices[i].devfn = info->dev->devfn;
 265                                 rcu_assign_pointer(devices[i].dev,
 266                                                    get_device(dev));
 267                                 return 1;
 268                         }
 269                 BUG_ON(i >= devices_cnt);
 270         }
 271
 272         return 0;
 273 }
 274
 275 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
 276                           struct dmar_dev_scope *devices, int count)
 277 {
 278         int index;
 279         struct device *tmp;
 280
 281         if (info->seg != segment)
 282                 return 0;
 283
 284         for_each_active_dev_scope(devices, count, index, tmp)
 285                 if (tmp == &info->dev->dev) {
 286                         RCU_INIT_POINTER(devices[index].dev, NULL);
 287                         synchronize_rcu();
 288                         put_device(tmp);
 289                         return 1;
 290                 }
 291
 292         return 0;
 293 }
 294
 295 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
 296 {
 297         int ret = 0;
 298         struct dmar_drhd_unit *dmaru;
 299         struct acpi_dmar_hardware_unit *drhd;
 300
 301         for_each_drhd_unit(dmaru) {
 302                 if (dmaru->include_all)
 303                         continue;
 304
 305                 drhd = container_of(dmaru->hdr,
 306                                     struct acpi_dmar_hardware_unit, header);
 307                 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
 308                                 ((void *)drhd) + drhd->header.length,
 309                                 dmaru->segment,
 310                                 dmaru->devices, dmaru->devices_cnt);
 311                 if (ret)
 312                         break;
 313         }
 314         if (ret >= 0)
 315                 ret = dmar_iommu_notify_scope_dev(info);
 316         if (ret < 0 && dmar_dev_scope_status == 0)
 317                 dmar_dev_scope_status = ret;
 318
 319         return ret;
 320 }
 321
 322 static void  dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
 323 {
 324         struct dmar_drhd_unit *dmaru;
 325
 326         for_each_drhd_unit(dmaru)
 327                 if (dmar_remove_dev_scope(info, dmaru->segment,
 328                         dmaru->devices, dmaru->devices_cnt))
 329                         break;
 330         dmar_iommu_notify_scope_dev(info);
 331 }
 332
 333 static int dmar_pci_bus_notifier(struct notifier_block *nb,
 334                                  unsigned long action, void *data)
 335 {
 336         struct pci_dev *pdev = to_pci_dev(data);
 337         struct dmar_pci_notify_info *info;
 338
 339         /* Only care about add/remove events for physical functions.
 340          * For VFs we actually do the lookup based on the corresponding
 341          * PF in device_to_iommu() anyway. */
 342         if (pdev->is_virtfn)
 343                 return NOTIFY_DONE;
 344         if (action != BUS_NOTIFY_ADD_DEVICE &&
 345             action != BUS_NOTIFY_REMOVED_DEVICE)
 346                 return NOTIFY_DONE;
 347
 348         info = dmar_alloc_pci_notify_info(pdev, action);
 349         if (!info)
 350                 return NOTIFY_DONE;
 351
 352         down_write(&dmar_global_lock);
 353         if (action == BUS_NOTIFY_ADD_DEVICE)
 354                 dmar_pci_bus_add_dev(info);
 355         else if (action == BUS_NOTIFY_REMOVED_DEVICE)
 356                 dmar_pci_bus_del_dev(info);
 357         up_write(&dmar_global_lock);
 358
 359         dmar_free_pci_notify_info(info);
 360
 361         return NOTIFY_OK;
 362 }
 363
 364 static struct notifier_block dmar_pci_bus_nb = {
 365         .notifier_call = dmar_pci_bus_notifier,
 366         .priority = INT_MIN,
 367 };
 368
 369 static struct dmar_drhd_unit *
 370 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
 371 {
 372         struct dmar_drhd_unit *dmaru;
 373
 374         list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list,
 375                                 dmar_rcu_check())
 376                 if (dmaru->segment == drhd->segment &&
 377                     dmaru->reg_base_addr == drhd->address)
 378                         return dmaru;
 379
 380         return NULL;
 381 }
 382
 383 /**
 384  * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
 385  * structure which uniquely represent one DMA remapping hardware unit
 386  * present in the platform
 387  */
 388 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
 389 {
 390         struct acpi_dmar_hardware_unit *drhd;
 391         struct dmar_drhd_unit *dmaru;
 392         int ret;
 393
 394         drhd = (struct acpi_dmar_hardware_unit *)header;
 395         dmaru = dmar_find_dmaru(drhd);
 396         if (dmaru)
 397                 goto out;
 398
 399         dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
 400         if (!dmaru)
 401                 return -ENOMEM;
 402
 403         /*
 404          * If header is allocated from slab by ACPI _DSM method, we need to
 405          * copy the content because the memory buffer will be freed on return.
 406          */
 407         dmaru->hdr = (void *)(dmaru + 1);
 408         memcpy(dmaru->hdr, header, header->length);
 409         dmaru->reg_base_addr = drhd->address;
 410         dmaru->segment = drhd->segment;
 411         dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
 412         dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
 413                                               ((void *)drhd) + drhd->header.length,
 414                                               &dmaru->devices_cnt);
 415         if (dmaru->devices_cnt && dmaru->devices == NULL) {
 416                 kfree(dmaru);
 417                 return -ENOMEM;
 418         }
 419
 420         ret = alloc_iommu(dmaru);
 421         if (ret) {
 422                 dmar_free_dev_scope(&dmaru->devices,
 423                                     &dmaru->devices_cnt);
 424                 kfree(dmaru);
 425                 return ret;
 426         }
 427         dmar_register_drhd_unit(dmaru);
 428
 429 out:
 430         if (arg)
 431                 (*(int *)arg)++;
 432
 433         return 0;
 434 }
 435
 436 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
 437 {
 438         if (dmaru->devices && dmaru->devices_cnt)
 439                 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
 440         if (dmaru->iommu)
 441                 free_iommu(dmaru->iommu);
 442         kfree(dmaru);
 443 }
 444
 445 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
 446                                       void *arg)
 447 {
 448         struct acpi_dmar_andd *andd = (void *)header;
 449
 450         /* Check for NUL termination within the designated length */
 451         if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
 452                 pr_warn(FW_BUG
 453                            "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
 454                            "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 455                            dmi_get_system_info(DMI_BIOS_VENDOR),
 456                            dmi_get_system_info(DMI_BIOS_VERSION),
 457                            dmi_get_system_info(DMI_PRODUCT_VERSION));
 458                 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 459                 return -EINVAL;
 460         }
 461         pr_info("ANDD device: %x name: %s\n", andd->device_number,
 462                 andd->device_name);
 463
 464         return 0;
 465 }
 466
 467 #ifdef CONFIG_ACPI_NUMA
 468 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
 469 {
 470         struct acpi_dmar_rhsa *rhsa;
 471         struct dmar_drhd_unit *drhd;
 472
 473         rhsa = (struct acpi_dmar_rhsa *)header;
 474         for_each_drhd_unit(drhd) {
 475                 if (drhd->reg_base_addr == rhsa->base_address) {
 476                         int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
 477
 478                         if (!node_online(node))
 479                                 node = NUMA_NO_NODE;
 480                         drhd->iommu->node = node;
 481                         return 0;
 482                 }
 483         }
 484         pr_warn(FW_BUG
 485                 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
 486                 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 487                 rhsa->base_address,
 488                 dmi_get_system_info(DMI_BIOS_VENDOR),
 489                 dmi_get_system_info(DMI_BIOS_VERSION),
 490                 dmi_get_system_info(DMI_PRODUCT_VERSION));
 491         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 492
 493         return 0;
 494 }
 495 #else
 496 #define dmar_parse_one_rhsa             dmar_res_noop
 497 #endif
 498
 499 static void
 500 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
 501 {
 502         struct acpi_dmar_hardware_unit *drhd;
 503         struct acpi_dmar_reserved_memory *rmrr;
 504         struct acpi_dmar_atsr *atsr;
 505         struct acpi_dmar_rhsa *rhsa;
 506
 507         switch (header->type) {
 508         case ACPI_DMAR_TYPE_HARDWARE_UNIT:
 509                 drhd = container_of(header, struct acpi_dmar_hardware_unit,
 510                                     header);
 511                 pr_info("DRHD base: %#016Lx flags: %#x\n",
 512                         (unsigned long long)drhd->address, drhd->flags);
 513                 break;
 514         case ACPI_DMAR_TYPE_RESERVED_MEMORY:
 515                 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
 516                                     header);
 517                 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
 518                         (unsigned long long)rmrr->base_address,
 519                         (unsigned long long)rmrr->end_address);
 520                 break;
 521         case ACPI_DMAR_TYPE_ROOT_ATS:
 522                 atsr = container_of(header, struct acpi_dmar_atsr, header);
 523                 pr_info("ATSR flags: %#x\n", atsr->flags);
 524                 break;
 525         case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
 526                 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
 527                 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
 528                        (unsigned long long)rhsa->base_address,
 529                        rhsa->proximity_domain);
 530                 break;
 531         case ACPI_DMAR_TYPE_NAMESPACE:
 532                 /* We don't print this here because we need to sanity-check
 533                    it first. So print it in dmar_parse_one_andd() instead. */
 534                 break;
 535         }
 536 }
 537
 538 /**
 539  * dmar_table_detect - checks to see if the platform supports DMAR devices
 540  */
 541 static int __init dmar_table_detect(void)
 542 {
 543         acpi_status status = AE_OK;
 544
 545         /* if we could find DMAR table, then there are DMAR devices */
 546         status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
 547
 548         if (ACPI_SUCCESS(status) && !dmar_tbl) {
 549                 pr_warn("Unable to map DMAR\n");
 550                 status = AE_NOT_FOUND;
 551         }
 552
 553         return ACPI_SUCCESS(status) ? 0 : -ENOENT;
 554 }
 555
 556 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
 557                                        size_t len, struct dmar_res_callback *cb)
 558 {
 559         struct acpi_dmar_header *iter, *next;
 560         struct acpi_dmar_header *end = ((void *)start) + len;
 561
 562         for (iter = start; iter < end; iter = next) {
 563                 next = (void *)iter + iter->length;
 564                 if (iter->length == 0) {
 565                         /* Avoid looping forever on bad ACPI tables */
 566                         pr_debug(FW_BUG "Invalid 0-length structure\n");
 567                         break;
 568                 } else if (next > end) {
 569                         /* Avoid passing table end */
 570                         pr_warn(FW_BUG "Record passes table end\n");
 571                         return -EINVAL;
 572                 }
 573
 574                 if (cb->print_entry)
 575                         dmar_table_print_dmar_entry(iter);
 576
 577                 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
 578                         /* continue for forward compatibility */
 579                         pr_debug("Unknown DMAR structure type %d\n",
 580                                  iter->type);
 581                 } else if (cb->cb[iter->type]) {
 582                         int ret;
 583
 584                         ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
 585                         if (ret)
 586                                 return ret;
 587                 } else if (!cb->ignore_unhandled) {
 588                         pr_warn("No handler for DMAR structure type %d\n",
 589                                 iter->type);
 590                         return -EINVAL;
 591                 }
 592         }
 593
 594         return 0;
 595 }
 596
 597 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
 598                                        struct dmar_res_callback *cb)
 599 {
 600         return dmar_walk_remapping_entries((void *)(dmar + 1),
 601                         dmar->header.length - sizeof(*dmar), cb);
 602 }
 603
 604 /**
 605  * parse_dmar_table - parses the DMA reporting table
 606  */
 607 static int __init
 608 parse_dmar_table(void)
 609 {
 610         struct acpi_table_dmar *dmar;
 611         int drhd_count = 0;
 612         int ret;
 613         struct dmar_res_callback cb = {
 614                 .print_entry = true,
 615                 .ignore_unhandled = true,
 616                 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
 617                 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
 618                 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
 619                 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
 620                 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
 621                 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
 622         };
 623
 624         /*
 625          * Do it again, earlier dmar_tbl mapping could be mapped with
 626          * fixed map.
 627          */
 628         dmar_table_detect();
 629
 630         /*
 631          * ACPI tables may not be DMA protected by tboot, so use DMAR copy
 632          * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
 633          */
 634         dmar_tbl = tboot_get_dmar_table(dmar_tbl);
 635
 636         dmar = (struct acpi_table_dmar *)dmar_tbl;
 637         if (!dmar)
 638                 return -ENODEV;
 639
 640         if (dmar->width < PAGE_SHIFT - 1) {
 641                 pr_warn("Invalid DMAR haw\n");
 642                 return -EINVAL;
 643         }
 644
 645         pr_info("Host address width %d\n", dmar->width + 1);
 646         ret = dmar_walk_dmar_table(dmar, &cb);
 647         if (ret == 0 && drhd_count == 0)
 648                 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
 649
 650         return ret;
 651 }
 652
 653 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
 654                                  int cnt, struct pci_dev *dev)
 655 {
 656         int index;
 657         struct device *tmp;
 658
 659         while (dev) {
 660                 for_each_active_dev_scope(devices, cnt, index, tmp)
 661                         if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
 662                                 return 1;
 663
 664                 /* Check our parent */
 665                 dev = dev->bus->self;
 666         }
 667
 668         return 0;
 669 }
 670
 671 struct dmar_drhd_unit *
 672 dmar_find_matched_drhd_unit(struct pci_dev *dev)
 673 {
 674         struct dmar_drhd_unit *dmaru;
 675         struct acpi_dmar_hardware_unit *drhd;
 676
 677         dev = pci_physfn(dev);
 678
 679         rcu_read_lock();
 680         for_each_drhd_unit(dmaru) {
 681                 drhd = container_of(dmaru->hdr,
 682                                     struct acpi_dmar_hardware_unit,
 683                                     header);
 684
 685                 if (dmaru->include_all &&
 686                     drhd->segment == pci_domain_nr(dev->bus))
 687                         goto out;
 688
 689                 if (dmar_pci_device_match(dmaru->devices,
 690                                           dmaru->devices_cnt, dev))
 691                         goto out;
 692         }
 693         dmaru = NULL;
 694 out:
 695         rcu_read_unlock();
 696
 697         return dmaru;
 698 }
 699
 700 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
 701                                               struct acpi_device *adev)
 702 {
 703         struct dmar_drhd_unit *dmaru;
 704         struct acpi_dmar_hardware_unit *drhd;
 705         struct acpi_dmar_device_scope *scope;
 706         struct device *tmp;
 707         int i;
 708         struct acpi_dmar_pci_path *path;
 709
 710         for_each_drhd_unit(dmaru) {
 711                 drhd = container_of(dmaru->hdr,
 712                                     struct acpi_dmar_hardware_unit,
 713                                     header);
 714
 715                 for (scope = (void *)(drhd + 1);
 716                      (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
 717                      scope = ((void *)scope) + scope->length) {
 718                         if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
 719                                 continue;
 720                         if (scope->enumeration_id != device_number)
 721                                 continue;
 722
 723                         path = (void *)(scope + 1);
 724                         pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
 725                                 dev_name(&adev->dev), dmaru->reg_base_addr,
 726                                 scope->bus, path->device, path->function);
 727                         for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
 728                                 if (tmp == NULL) {
 729                                         dmaru->devices[i].bus = scope->bus;
 730                                         dmaru->devices[i].devfn = PCI_DEVFN(path->device,
 731                                                                             path->function);
 732                                         rcu_assign_pointer(dmaru->devices[i].dev,
 733                                                            get_device(&adev->dev));
 734                                         return;
 735                                 }
 736                         BUG_ON(i >= dmaru->devices_cnt);
 737                 }
 738         }
 739         pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
 740                 device_number, dev_name(&adev->dev));
 741 }
 742
 743 static int __init dmar_acpi_dev_scope_init(void)
 744 {
 745         struct acpi_dmar_andd *andd;
 746
 747         if (dmar_tbl == NULL)
 748                 return -ENODEV;
 749
 750         for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
 751              ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
 752              andd = ((void *)andd) + andd->header.length) {
 753                 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
 754                         acpi_handle h;
 755                         struct acpi_device *adev;
 756
 757                         if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
 758                                                           andd->device_name,
 759                                                           &h))) {
 760                                 pr_err("Failed to find handle for ACPI object %s\n",
 761                                        andd->device_name);
 762                                 continue;
 763                         }
 764                         if (acpi_bus_get_device(h, &adev)) {
 765                                 pr_err("Failed to get device for ACPI object %s\n",
 766                                        andd->device_name);
 767                                 continue;
 768                         }
 769                         dmar_acpi_insert_dev_scope(andd->device_number, adev);
 770                 }
 771         }
 772         return 0;
 773 }
 774
 775 int __init dmar_dev_scope_init(void)
 776 {
 777         struct pci_dev *dev = NULL;
 778         struct dmar_pci_notify_info *info;
 779
 780         if (dmar_dev_scope_status != 1)
 781                 return dmar_dev_scope_status;
 782
 783         if (list_empty(&dmar_drhd_units)) {
 784                 dmar_dev_scope_status = -ENODEV;
 785         } else {
 786                 dmar_dev_scope_status = 0;
 787
 788                 dmar_acpi_dev_scope_init();
 789
 790                 for_each_pci_dev(dev) {
 791                         if (dev->is_virtfn)
 792                                 continue;
 793
 794                         info = dmar_alloc_pci_notify_info(dev,
 795                                         BUS_NOTIFY_ADD_DEVICE);
 796                         if (!info) {
 797                                 return dmar_dev_scope_status;
 798                         } else {
 799                                 dmar_pci_bus_add_dev(info);
 800                                 dmar_free_pci_notify_info(info);
 801                         }
 802                 }
 803         }
 804
 805         return dmar_dev_scope_status;
 806 }
 807
 808 void __init dmar_register_bus_notifier(void)
 809 {
 810         bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
 811 }
 812
 813
 814 int __init dmar_table_init(void)
 815 {
 816         static int dmar_table_initialized;
 817         int ret;
 818
 819         if (dmar_table_initialized == 0) {
 820                 ret = parse_dmar_table();
 821                 if (ret < 0) {
 822                         if (ret != -ENODEV)
 823                                 pr_info("Parse DMAR table failure.\n");
 824                 } else  if (list_empty(&dmar_drhd_units)) {
 825                         pr_info("No DMAR devices found\n");
 826                         ret = -ENODEV;
 827                 }
 828
 829                 if (ret < 0)
 830                         dmar_table_initialized = ret;
 831                 else
 832                         dmar_table_initialized = 1;
 833         }
 834
 835         return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
 836 }
 837
 838 static void warn_invalid_dmar(u64 addr, const char *message)
 839 {
 840         pr_warn_once(FW_BUG
 841                 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
 842                 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 843                 addr, message,
 844                 dmi_get_system_info(DMI_BIOS_VENDOR),
 845                 dmi_get_system_info(DMI_BIOS_VERSION),
 846                 dmi_get_system_info(DMI_PRODUCT_VERSION));
 847         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 848 }
 849
 850 static int __ref
 851 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
 852 {
 853         struct acpi_dmar_hardware_unit *drhd;
 854         void __iomem *addr;
 855         u64 cap, ecap;
 856
 857         drhd = (void *)entry;
 858         if (!drhd->address) {
 859                 warn_invalid_dmar(0, "");
 860                 return -EINVAL;
 861         }
 862
 863         if (arg)
 864                 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
 865         else
 866                 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
 867         if (!addr) {
 868                 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
 869                 return -EINVAL;
 870         }
 871
 872         cap = dmar_readq(addr + DMAR_CAP_REG);
 873         ecap = dmar_readq(addr + DMAR_ECAP_REG);
 874
 875         if (arg)
 876                 iounmap(addr);
 877         else
 878                 early_iounmap(addr, VTD_PAGE_SIZE);
 879
 880         if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
 881                 warn_invalid_dmar(drhd->address, " returns all ones");
 882                 return -EINVAL;
 883         }
 884
 885         return 0;
 886 }
 887
 888 int __init detect_intel_iommu(void)
 889 {
 890         int ret;
 891         struct dmar_res_callback validate_drhd_cb = {
 892                 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
 893                 .ignore_unhandled = true,
 894         };
 895
 896         down_write(&dmar_global_lock);
 897         ret = dmar_table_detect();
 898         if (!ret)
 899                 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
 900                                            &validate_drhd_cb);
 901         if (!ret && !no_iommu && !iommu_detected && !dmar_disabled) {
 902                 iommu_detected = 1;
 903                 /* Make sure ACS will be enabled */
 904                 pci_request_acs();
 905         }
 906
 907 #ifdef CONFIG_X86
 908         if (!ret) {
 909                 x86_init.iommu.iommu_init = intel_iommu_init;
 910                 x86_platform.iommu_shutdown = intel_iommu_shutdown;
 911         }
 912
 913 #endif
 914
 915         if (dmar_tbl) {
 916                 acpi_put_table(dmar_tbl);
 917                 dmar_tbl = NULL;
 918         }
 919         up_write(&dmar_global_lock);
 920
 921         return ret ? ret : 1;
 922 }
 923
 924 static void unmap_iommu(struct intel_iommu *iommu)
 925 {
 926         iounmap(iommu->reg);
 927         release_mem_region(iommu->reg_phys, iommu->reg_size);
 928 }
 929
 930 /**
 931  * map_iommu: map the iommu's registers
 932  * @iommu: the iommu to map
 933  * @phys_addr: the physical address of the base resgister
 934  *
 935  * Memory map the iommu's registers.  Start w/ a single page, and
 936  * possibly expand if that turns out to be insufficent.
 937  */
 938 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
 939 {
 940         int map_size, err=0;
 941
 942         iommu->reg_phys = phys_addr;
 943         iommu->reg_size = VTD_PAGE_SIZE;
 944
 945         if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
 946                 pr_err("Can't reserve memory\n");
 947                 err = -EBUSY;
 948                 goto out;
 949         }
 950
 951         iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
 952         if (!iommu->reg) {
 953                 pr_err("Can't map the region\n");
 954                 err = -ENOMEM;
 955                 goto release;
 956         }
 957
 958         iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
 959         iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
 960
 961         if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
 962                 err = -EINVAL;
 963                 warn_invalid_dmar(phys_addr, " returns all ones");
 964                 goto unmap;
 965         }
 966
 967         /* the registers might be more than one page */
 968         map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
 969                          cap_max_fault_reg_offset(iommu->cap));
 970         map_size = VTD_PAGE_ALIGN(map_size);
 971         if (map_size > iommu->reg_size) {
 972                 iounmap(iommu->reg);
 973                 release_mem_region(iommu->reg_phys, iommu->reg_size);
 974                 iommu->reg_size = map_size;
 975                 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
 976                                         iommu->name)) {
 977                         pr_err("Can't reserve memory\n");
 978                         err = -EBUSY;
 979                         goto out;
 980                 }
 981                 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
 982                 if (!iommu->reg) {
 983                         pr_err("Can't map the region\n");
 984                         err = -ENOMEM;
 985                         goto release;
 986                 }
 987         }
 988         err = 0;
 989         goto out;
 990
 991 unmap:
 992         iounmap(iommu->reg);
 993 release:
 994         release_mem_region(iommu->reg_phys, iommu->reg_size);
 995 out:
 996         return err;
 997 }
 998
 999 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
1000 {
1001         iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
1002                                             DMAR_UNITS_SUPPORTED);
1003         if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
1004                 iommu->seq_id = -1;
1005         } else {
1006                 set_bit(iommu->seq_id, dmar_seq_ids);
1007                 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1008         }
1009
1010         return iommu->seq_id;
1011 }
1012
1013 static void dmar_free_seq_id(struct intel_iommu *iommu)
1014 {
1015         if (iommu->seq_id >= 0) {
1016                 clear_bit(iommu->seq_id, dmar_seq_ids);
1017                 iommu->seq_id = -1;
1018         }
1019 }
1020
1021 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1022 {
1023         struct intel_iommu *iommu;
1024         u32 ver, sts;
1025         int agaw = 0;
1026         int msagaw = 0;
1027         int err;
1028
1029         if (!drhd->reg_base_addr) {
1030                 warn_invalid_dmar(0, "");
1031                 return -EINVAL;
1032         }
1033
1034         iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1035         if (!iommu)
1036                 return -ENOMEM;
1037
1038         if (dmar_alloc_seq_id(iommu) < 0) {
1039                 pr_err("Failed to allocate seq_id\n");
1040                 err = -ENOSPC;
1041                 goto error;
1042         }
1043
1044         err = map_iommu(iommu, drhd->reg_base_addr);
1045         if (err) {
1046                 pr_err("Failed to map %s\n", iommu->name);
1047                 goto error_free_seq_id;
1048         }
1049
1050         err = -EINVAL;
1051         agaw = iommu_calculate_agaw(iommu);
1052         if (agaw < 0) {
1053                 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1054                         iommu->seq_id);
1055                 goto err_unmap;
1056         }
1057         msagaw = iommu_calculate_max_sagaw(iommu);
1058         if (msagaw < 0) {
1059                 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1060                         iommu->seq_id);
1061                 goto err_unmap;
1062         }
1063         iommu->agaw = agaw;
1064         iommu->msagaw = msagaw;
1065         iommu->segment = drhd->segment;
1066
1067         iommu->node = NUMA_NO_NODE;
1068
1069         ver = readl(iommu->reg + DMAR_VER_REG);
1070         pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1071                 iommu->name,
1072                 (unsigned long long)drhd->reg_base_addr,
1073                 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1074                 (unsigned long long)iommu->cap,
1075                 (unsigned long long)iommu->ecap);
1076
1077         /* Reflect status in gcmd */
1078         sts = readl(iommu->reg + DMAR_GSTS_REG);
1079         if (sts & DMA_GSTS_IRES)
1080                 iommu->gcmd |= DMA_GCMD_IRE;
1081         if (sts & DMA_GSTS_TES)
1082                 iommu->gcmd |= DMA_GCMD_TE;
1083         if (sts & DMA_GSTS_QIES)
1084                 iommu->gcmd |= DMA_GCMD_QIE;
1085
1086         raw_spin_lock_init(&iommu->register_lock);
1087
1088         if (intel_iommu_enabled) {
1089                 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1090                                              intel_iommu_groups,
1091                                              "%s", iommu->name);
1092                 if (err)
1093                         goto err_unmap;
1094
1095                 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
1096
1097                 err = iommu_device_register(&iommu->iommu);
1098                 if (err)
1099                         goto err_unmap;
1100         }
1101
1102         drhd->iommu = iommu;
1103
1104         return 0;
1105
1106 err_unmap:
1107         unmap_iommu(iommu);
1108 error_free_seq_id:
1109         dmar_free_seq_id(iommu);
1110 error:
1111         kfree(iommu);
1112         return err;
1113 }
1114
1115 static void free_iommu(struct intel_iommu *iommu)
1116 {
1117         if (intel_iommu_enabled) {
1118                 iommu_device_unregister(&iommu->iommu);
1119                 iommu_device_sysfs_remove(&iommu->iommu);
1120         }
1121
1122         if (iommu->irq) {
1123                 if (iommu->pr_irq) {
1124                         free_irq(iommu->pr_irq, iommu);
1125                         dmar_free_hwirq(iommu->pr_irq);
1126                         iommu->pr_irq = 0;
1127                 }
1128                 free_irq(iommu->irq, iommu);
1129                 dmar_free_hwirq(iommu->irq);
1130                 iommu->irq = 0;
1131         }
1132
1133         if (iommu->qi) {
1134                 free_page((unsigned long)iommu->qi->desc);
1135                 kfree(iommu->qi->desc_status);
1136                 kfree(iommu->qi);
1137         }
1138
1139         if (iommu->reg)
1140                 unmap_iommu(iommu);
1141
1142         dmar_free_seq_id(iommu);
1143         kfree(iommu);
1144 }
1145
1146 /*
1147  * Reclaim all the submitted descriptors which have completed its work.
1148  */
1149 static inline void reclaim_free_desc(struct q_inval *qi)
1150 {
1151         while (qi->desc_status[qi->free_tail] == QI_DONE ||
1152                qi->desc_status[qi->free_tail] == QI_ABORT) {
1153                 qi->desc_status[qi->free_tail] = QI_FREE;
1154                 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1155                 qi->free_cnt++;
1156         }
1157 }
1158
1159 static int qi_check_fault(struct intel_iommu *iommu, int index)
1160 {
1161         u32 fault;
1162         int head, tail;
1163         struct q_inval *qi = iommu->qi;
1164         int wait_index = (index + 1) % QI_LENGTH;
1165         int shift = qi_shift(iommu);
1166
1167         if (qi->desc_status[wait_index] == QI_ABORT)
1168                 return -EAGAIN;
1169
1170         fault = readl(iommu->reg + DMAR_FSTS_REG);
1171
1172         /*
1173          * If IQE happens, the head points to the descriptor associated
1174          * with the error. No new descriptors are fetched until the IQE
1175          * is cleared.
1176          */
1177         if (fault & DMA_FSTS_IQE) {
1178                 head = readl(iommu->reg + DMAR_IQH_REG);
1179                 if ((head >> shift) == index) {
1180                         struct qi_desc *desc = qi->desc + head;
1181
1182                         /*
1183                          * desc->qw2 and desc->qw3 are either reserved or
1184                          * used by software as private data. We won't print
1185                          * out these two qw's for security consideration.
1186                          */
1187                         pr_err("VT-d detected invalid descriptor: qw0 = %llx, qw1 = %llx\n",
1188                                (unsigned long long)desc->qw0,
1189                                (unsigned long long)desc->qw1);
1190                         memcpy(desc, qi->desc + (wait_index << shift),
1191                                1 << shift);
1192                         writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1193                         return -EINVAL;
1194                 }
1195         }
1196
1197         /*
1198          * If ITE happens, all pending wait_desc commands are aborted.
1199          * No new descriptors are fetched until the ITE is cleared.
1200          */
1201         if (fault & DMA_FSTS_ITE) {
1202                 head = readl(iommu->reg + DMAR_IQH_REG);
1203                 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1204                 head |= 1;
1205                 tail = readl(iommu->reg + DMAR_IQT_REG);
1206                 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1207
1208                 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1209
1210                 do {
1211                         if (qi->desc_status[head] == QI_IN_USE)
1212                                 qi->desc_status[head] = QI_ABORT;
1213                         head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1214                 } while (head != tail);
1215
1216                 if (qi->desc_status[wait_index] == QI_ABORT)
1217                         return -EAGAIN;
1218         }
1219
1220         if (fault & DMA_FSTS_ICE)
1221                 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1222
1223         return 0;
1224 }
1225
1226 /*
1227  * Submit the queued invalidation descriptor to the remapping
1228  * hardware unit and wait for its completion.
1229  */
1230 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
1231 {
1232         int rc;
1233         struct q_inval *qi = iommu->qi;
1234         int offset, shift, length;
1235         struct qi_desc wait_desc;
1236         int wait_index, index;
1237         unsigned long flags;
1238
1239         if (!qi)
1240                 return 0;
1241
1242 restart:
1243         rc = 0;
1244
1245         raw_spin_lock_irqsave(&qi->q_lock, flags);
1246         while (qi->free_cnt < 3) {
1247                 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1248                 cpu_relax();
1249                 raw_spin_lock_irqsave(&qi->q_lock, flags);
1250         }
1251
1252         index = qi->free_head;
1253         wait_index = (index + 1) % QI_LENGTH;
1254         shift = qi_shift(iommu);
1255         length = 1 << shift;
1256
1257         qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1258
1259         offset = index << shift;
1260         memcpy(qi->desc + offset, desc, length);
1261         wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
1262                         QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1263         wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]);
1264         wait_desc.qw2 = 0;
1265         wait_desc.qw3 = 0;
1266
1267         offset = wait_index << shift;
1268         memcpy(qi->desc + offset, &wait_desc, length);
1269
1270         qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1271         qi->free_cnt -= 2;
1272
1273         /*
1274          * update the HW tail register indicating the presence of
1275          * new descriptors.
1276          */
1277         writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);
1278
1279         while (qi->desc_status[wait_index] != QI_DONE) {
1280                 /*
1281                  * We will leave the interrupts disabled, to prevent interrupt
1282                  * context to queue another cmd while a cmd is already submitted
1283                  * and waiting for completion on this cpu. This is to avoid
1284                  * a deadlock where the interrupt context can wait indefinitely
1285                  * for free slots in the queue.
1286                  */
1287                 rc = qi_check_fault(iommu, index);
1288                 if (rc)
1289                         break;
1290
1291                 raw_spin_unlock(&qi->q_lock);
1292                 cpu_relax();
1293                 raw_spin_lock(&qi->q_lock);
1294         }
1295
1296         qi->desc_status[index] = QI_DONE;
1297
1298         reclaim_free_desc(qi);
1299         raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1300
1301         if (rc == -EAGAIN)
1302                 goto restart;
1303
1304         return rc;
1305 }
1306
1307 /*
1308  * Flush the global interrupt entry cache.
1309  */
1310 void qi_global_iec(struct intel_iommu *iommu)
1311 {
1312         struct qi_desc desc;
1313
1314         desc.qw0 = QI_IEC_TYPE;
1315         desc.qw1 = 0;
1316         desc.qw2 = 0;
1317         desc.qw3 = 0;
1318
1319         /* should never fail */
1320         qi_submit_sync(&desc, iommu);
1321 }
1322
1323 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1324                       u64 type)
1325 {
1326         struct qi_desc desc;
1327
1328         desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1329                         | QI_CC_GRAN(type) | QI_CC_TYPE;
1330         desc.qw1 = 0;
1331         desc.qw2 = 0;
1332         desc.qw3 = 0;
1333
1334         qi_submit_sync(&desc, iommu);
1335 }
1336
1337 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1338                     unsigned int size_order, u64 type)
1339 {
1340         u8 dw = 0, dr = 0;
1341
1342         struct qi_desc desc;
1343         int ih = 0;
1344
1345         if (cap_write_drain(iommu->cap))
1346                 dw = 1;
1347
1348         if (cap_read_drain(iommu->cap))
1349                 dr = 1;
1350
1351         desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1352                 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1353         desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1354                 | QI_IOTLB_AM(size_order);
1355         desc.qw2 = 0;
1356         desc.qw3 = 0;
1357
1358         qi_submit_sync(&desc, iommu);
1359 }
1360
1361 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1362                         u16 qdep, u64 addr, unsigned mask)
1363 {
1364         struct qi_desc desc;
1365
1366         if (mask) {
1367                 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1368                 desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1369         } else
1370                 desc.qw1 = QI_DEV_IOTLB_ADDR(addr);
1371
1372         if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1373                 qdep = 0;
1374
1375         desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1376                    QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1377         desc.qw2 = 0;
1378         desc.qw3 = 0;
1379
1380         qi_submit_sync(&desc, iommu);
1381 }
1382
1383 /* PASID-based IOTLB invalidation */
1384 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
1385                      unsigned long npages, bool ih)
1386 {
1387         struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
1388
1389         /*
1390          * npages == -1 means a PASID-selective invalidation, otherwise,
1391          * a positive value for Page-selective-within-PASID invalidation.
1392          * 0 is not a valid input.
1393          */
1394         if (WARN_ON(!npages)) {
1395                 pr_err("Invalid input npages = %ld\n", npages);
1396                 return;
1397         }
1398
1399         if (npages == -1) {
1400                 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1401                                 QI_EIOTLB_DID(did) |
1402                                 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
1403                                 QI_EIOTLB_TYPE;
1404                 desc.qw1 = 0;
1405         } else {
1406                 int mask = ilog2(__roundup_pow_of_two(npages));
1407                 unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
1408
1409                 if (WARN_ON_ONCE(!ALIGN(addr, align)))
1410                         addr &= ~(align - 1);
1411
1412                 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1413                                 QI_EIOTLB_DID(did) |
1414                                 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
1415                                 QI_EIOTLB_TYPE;
1416                 desc.qw1 = QI_EIOTLB_ADDR(addr) |
1417                                 QI_EIOTLB_IH(ih) |
1418                                 QI_EIOTLB_AM(mask);
1419         }
1420
1421         qi_submit_sync(&desc, iommu);
1422 }
1423
1424 /*
1425  * Disable Queued Invalidation interface.
1426  */
1427 void dmar_disable_qi(struct intel_iommu *iommu)
1428 {
1429         unsigned long flags;
1430         u32 sts;
1431         cycles_t start_time = get_cycles();
1432
1433         if (!ecap_qis(iommu->ecap))
1434                 return;
1435
1436         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1437
1438         sts =  readl(iommu->reg + DMAR_GSTS_REG);
1439         if (!(sts & DMA_GSTS_QIES))
1440                 goto end;
1441
1442         /*
1443          * Give a chance to HW to complete the pending invalidation requests.
1444          */
1445         while ((readl(iommu->reg + DMAR_IQT_REG) !=
1446                 readl(iommu->reg + DMAR_IQH_REG)) &&
1447                 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1448                 cpu_relax();
1449
1450         iommu->gcmd &= ~DMA_GCMD_QIE;
1451         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1452
1453         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1454                       !(sts & DMA_GSTS_QIES), sts);
1455 end:
1456         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1457 }
1458
1459 /*
1460  * Enable queued invalidation.
1461  */
1462 static void __dmar_enable_qi(struct intel_iommu *iommu)
1463 {
1464         u32 sts;
1465         unsigned long flags;
1466         struct q_inval *qi = iommu->qi;
1467         u64 val = virt_to_phys(qi->desc);
1468
1469         qi->free_head = qi->free_tail = 0;
1470         qi->free_cnt = QI_LENGTH;
1471
1472         /*
1473          * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability
1474          * is present.
1475          */
1476         if (ecap_smts(iommu->ecap))
1477                 val |= (1 << 11) | 1;
1478
1479         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1480
1481         /* write zero to the tail reg */
1482         writel(0, iommu->reg + DMAR_IQT_REG);
1483
1484         dmar_writeq(iommu->reg + DMAR_IQA_REG, val);
1485
1486         iommu->gcmd |= DMA_GCMD_QIE;
1487         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1488
1489         /* Make sure hardware complete it */
1490         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1491
1492         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1493 }
1494
1495 /*
1496  * Enable Queued Invalidation interface. This is a must to support
1497  * interrupt-remapping. Also used by DMA-remapping, which replaces
1498  * register based IOTLB invalidation.
1499  */
1500 int dmar_enable_qi(struct intel_iommu *iommu)
1501 {
1502         struct q_inval *qi;
1503         struct page *desc_page;
1504
1505         if (!ecap_qis(iommu->ecap))
1506                 return -ENOENT;
1507
1508         /*
1509          * queued invalidation is already setup and enabled.
1510          */
1511         if (iommu->qi)
1512                 return 0;
1513
1514         iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1515         if (!iommu->qi)
1516                 return -ENOMEM;
1517
1518         qi = iommu->qi;
1519
1520         /*
1521          * Need two pages to accommodate 256 descriptors of 256 bits each
1522          * if the remapping hardware supports scalable mode translation.
1523          */
1524         desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
1525                                      !!ecap_smts(iommu->ecap));
1526         if (!desc_page) {
1527                 kfree(qi);
1528                 iommu->qi = NULL;
1529                 return -ENOMEM;
1530         }
1531
1532         qi->desc = page_address(desc_page);
1533
1534         qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC);
1535         if (!qi->desc_status) {
1536                 free_page((unsigned long) qi->desc);
1537                 kfree(qi);
1538                 iommu->qi = NULL;
1539                 return -ENOMEM;
1540         }
1541
1542         raw_spin_lock_init(&qi->q_lock);
1543
1544         __dmar_enable_qi(iommu);
1545
1546         return 0;
1547 }
1548
1549 /* iommu interrupt handling. Most stuff are MSI-like. */
1550
1551 enum faulttype {
1552         DMA_REMAP,
1553         INTR_REMAP,
1554         UNKNOWN,
1555 };
1556
1557 static const char *dma_remap_fault_reasons[] =
1558 {
1559         "Software",
1560         "Present bit in root entry is clear",
1561         "Present bit in context entry is clear",
1562         "Invalid context entry",
1563         "Access beyond MGAW",
1564         "PTE Write access is not set",
1565         "PTE Read access is not set",
1566         "Next page table ptr is invalid",
1567         "Root table address invalid",
1568         "Context table ptr is invalid",
1569         "non-zero reserved fields in RTP",
1570         "non-zero reserved fields in CTP",
1571         "non-zero reserved fields in PTE",
1572         "PCE for translation request specifies blocking",
1573 };
1574
1575 static const char * const dma_remap_sm_fault_reasons[] = {
1576         "SM: Invalid Root Table Address",
1577         "SM: TTM 0 for request with PASID",
1578         "SM: TTM 0 for page group request",
1579         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1580         "SM: Error attempting to access Root Entry",
1581         "SM: Present bit in Root Entry is clear",
1582         "SM: Non-zero reserved field set in Root Entry",
1583         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1584         "SM: Error attempting to access Context Entry",
1585         "SM: Present bit in Context Entry is clear",
1586         "SM: Non-zero reserved field set in the Context Entry",
1587         "SM: Invalid Context Entry",
1588         "SM: DTE field in Context Entry is clear",
1589         "SM: PASID Enable field in Context Entry is clear",
1590         "SM: PASID is larger than the max in Context Entry",
1591         "SM: PRE field in Context-Entry is clear",
1592         "SM: RID_PASID field error in Context-Entry",
1593         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1594         "SM: Error attempting to access the PASID Directory Entry",
1595         "SM: Present bit in Directory Entry is clear",
1596         "SM: Non-zero reserved field set in PASID Directory Entry",
1597         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1598         "SM: Error attempting to access PASID Table Entry",
1599         "SM: Present bit in PASID Table Entry is clear",
1600         "SM: Non-zero reserved field set in PASID Table Entry",
1601         "SM: Invalid Scalable-Mode PASID Table Entry",
1602         "SM: ERE field is clear in PASID Table Entry",
1603         "SM: SRE field is clear in PASID Table Entry",
1604         "Unknown", "Unknown",/* 0x5E-0x5F */
1605         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */
1606         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */
1607         "SM: Error attempting to access first-level paging entry",
1608         "SM: Present bit in first-level paging entry is clear",
1609         "SM: Non-zero reserved field set in first-level paging entry",
1610         "SM: Error attempting to access FL-PML4 entry",
1611         "SM: First-level entry address beyond MGAW in Nested translation",
1612         "SM: Read permission error in FL-PML4 entry in Nested translation",
1613         "SM: Read permission error in first-level paging entry in Nested translation",
1614         "SM: Write permission error in first-level paging entry in Nested translation",
1615         "SM: Error attempting to access second-level paging entry",
1616         "SM: Read/Write permission error in second-level paging entry",
1617         "SM: Non-zero reserved field set in second-level paging entry",
1618         "SM: Invalid second-level page table pointer",
1619         "SM: A/D bit update needed in second-level entry when set up in no snoop",
1620         "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1621         "SM: Address in first-level translation is not canonical",
1622         "SM: U/S set 0 for first-level translation with user privilege",
1623         "SM: No execute permission for request with PASID and ER=1",
1624         "SM: Address beyond the DMA hardware max",
1625         "SM: Second-level entry address beyond the max",
1626         "SM: No write permission for Write/AtomicOp request",
1627         "SM: No read permission for Read/AtomicOp request",
1628         "SM: Invalid address-interrupt address",
1629         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */
1630         "SM: A/D bit update needed in first-level entry when set up in no snoop",
1631 };
1632
1633 static const char *irq_remap_fault_reasons[] =
1634 {
1635         "Detected reserved fields in the decoded interrupt-remapped request",
1636         "Interrupt index exceeded the interrupt-remapping table size",
1637         "Present field in the IRTE entry is clear",
1638         "Error accessing interrupt-remapping table pointed by IRTA_REG",
1639         "Detected reserved fields in the IRTE entry",
1640         "Blocked a compatibility format interrupt request",
1641         "Blocked an interrupt request due to source-id verification failure",
1642 };
1643
1644 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1645 {
1646         if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1647                                         ARRAY_SIZE(irq_remap_fault_reasons))) {
1648                 *fault_type = INTR_REMAP;
1649                 return irq_remap_fault_reasons[fault_reason - 0x20];
1650         } else if (fault_reason >= 0x30 && (fault_reason - 0x30 <
1651                         ARRAY_SIZE(dma_remap_sm_fault_reasons))) {
1652                 *fault_type = DMA_REMAP;
1653                 return dma_remap_sm_fault_reasons[fault_reason - 0x30];
1654         } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1655                 *fault_type = DMA_REMAP;
1656                 return dma_remap_fault_reasons[fault_reason];
1657         } else {
1658                 *fault_type = UNKNOWN;
1659                 return "Unknown";
1660         }
1661 }
1662
1663
1664 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1665 {
1666         if (iommu->irq == irq)
1667                 return DMAR_FECTL_REG;
1668         else if (iommu->pr_irq == irq)
1669                 return DMAR_PECTL_REG;
1670         else
1671                 BUG();
1672 }
1673
1674 void dmar_msi_unmask(struct irq_data *data)
1675 {
1676         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1677         int reg = dmar_msi_reg(iommu, data->irq);
1678         unsigned long flag;
1679
1680         /* unmask it */
1681         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1682         writel(0, iommu->reg + reg);
1683         /* Read a reg to force flush the post write */
1684         readl(iommu->reg + reg);
1685         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1686 }
1687
1688 void dmar_msi_mask(struct irq_data *data)
1689 {
1690         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1691         int reg = dmar_msi_reg(iommu, data->irq);
1692         unsigned long flag;
1693
1694         /* mask it */
1695         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1696         writel(DMA_FECTL_IM, iommu->reg + reg);
1697         /* Read a reg to force flush the post write */
1698         readl(iommu->reg + reg);
1699         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1700 }
1701
1702 void dmar_msi_write(int irq, struct msi_msg *msg)
1703 {
1704         struct intel_iommu *iommu = irq_get_handler_data(irq);
1705         int reg = dmar_msi_reg(iommu, irq);
1706         unsigned long flag;
1707
1708         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1709         writel(msg->data, iommu->reg + reg + 4);
1710         writel(msg->address_lo, iommu->reg + reg + 8);
1711         writel(msg->address_hi, iommu->reg + reg + 12);
1712         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1713 }
1714
1715 void dmar_msi_read(int irq, struct msi_msg *msg)
1716 {
1717         struct intel_iommu *iommu = irq_get_handler_data(irq);
1718         int reg = dmar_msi_reg(iommu, irq);
1719         unsigned long flag;
1720
1721         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1722         msg->data = readl(iommu->reg + reg + 4);
1723         msg->address_lo = readl(iommu->reg + reg + 8);
1724         msg->address_hi = readl(iommu->reg + reg + 12);
1725         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1726 }
1727
1728 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1729                 u8 fault_reason, int pasid, u16 source_id,
1730                 unsigned long long addr)
1731 {
1732         const char *reason;
1733         int fault_type;
1734
1735         reason = dmar_get_fault_reason(fault_reason, &fault_type);
1736
1737         if (fault_type == INTR_REMAP)
1738                 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n",
1739                         source_id >> 8, PCI_SLOT(source_id & 0xFF),
1740                         PCI_FUNC(source_id & 0xFF), addr >> 48,
1741                         fault_reason, reason);
1742         else
1743                 pr_err("[%s] Request device [%02x:%02x.%d] PASID %x fault addr %llx [fault reason %02d] %s\n",
1744                        type ? "DMA Read" : "DMA Write",
1745                        source_id >> 8, PCI_SLOT(source_id & 0xFF),
1746                        PCI_FUNC(source_id & 0xFF), pasid, addr,
1747                        fault_reason, reason);
1748         return 0;
1749 }
1750
1751 #define PRIMARY_FAULT_REG_LEN (16)
1752 irqreturn_t dmar_fault(int irq, void *dev_id)
1753 {
1754         struct intel_iommu *iommu = dev_id;
1755         int reg, fault_index;
1756         u32 fault_status;
1757         unsigned long flag;
1758         static DEFINE_RATELIMIT_STATE(rs,
1759                                       DEFAULT_RATELIMIT_INTERVAL,
1760                                       DEFAULT_RATELIMIT_BURST);
1761
1762         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1763         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1764         if (fault_status && __ratelimit(&rs))
1765                 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1766
1767         /* TBD: ignore advanced fault log currently */
1768         if (!(fault_status & DMA_FSTS_PPF))
1769                 goto unlock_exit;
1770
1771         fault_index = dma_fsts_fault_record_index(fault_status);
1772         reg = cap_fault_reg_offset(iommu->cap);
1773         while (1) {
1774                 /* Disable printing, simply clear the fault when ratelimited */
1775                 bool ratelimited = !__ratelimit(&rs);
1776                 u8 fault_reason;
1777                 u16 source_id;
1778                 u64 guest_addr;
1779                 int type, pasid;
1780                 u32 data;
1781                 bool pasid_present;
1782
1783                 /* highest 32 bits */
1784                 data = readl(iommu->reg + reg +
1785                                 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1786                 if (!(data & DMA_FRCD_F))
1787                         break;
1788
1789                 if (!ratelimited) {
1790                         fault_reason = dma_frcd_fault_reason(data);
1791                         type = dma_frcd_type(data);
1792
1793                         pasid = dma_frcd_pasid_value(data);
1794                         data = readl(iommu->reg + reg +
1795                                      fault_index * PRIMARY_FAULT_REG_LEN + 8);
1796                         source_id = dma_frcd_source_id(data);
1797
1798                         pasid_present = dma_frcd_pasid_present(data);
1799                         guest_addr = dmar_readq(iommu->reg + reg +
1800                                         fault_index * PRIMARY_FAULT_REG_LEN);
1801                         guest_addr = dma_frcd_page_addr(guest_addr);
1802                 }
1803
1804                 /* clear the fault */
1805                 writel(DMA_FRCD_F, iommu->reg + reg +
1806                         fault_index * PRIMARY_FAULT_REG_LEN + 12);
1807
1808                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1809
1810                 if (!ratelimited)
1811                         /* Using pasid -1 if pasid is not present */
1812                         dmar_fault_do_one(iommu, type, fault_reason,
1813                                           pasid_present ? pasid : -1,
1814                                           source_id, guest_addr);
1815
1816                 fault_index++;
1817                 if (fault_index >= cap_num_fault_regs(iommu->cap))
1818                         fault_index = 0;
1819                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1820         }
1821
1822         writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO,
1823                iommu->reg + DMAR_FSTS_REG);
1824
1825 unlock_exit:
1826         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1827         return IRQ_HANDLED;
1828 }
1829
1830 int dmar_set_interrupt(struct intel_iommu *iommu)
1831 {
1832         int irq, ret;
1833
1834         /*
1835          * Check if the fault interrupt is already initialized.
1836          */
1837         if (iommu->irq)
1838                 return 0;
1839
1840         irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
1841         if (irq > 0) {
1842                 iommu->irq = irq;
1843         } else {
1844                 pr_err("No free IRQ vectors\n");
1845                 return -EINVAL;
1846         }
1847
1848         ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
1849         if (ret)
1850                 pr_err("Can't request irq\n");
1851         return ret;
1852 }
1853
1854 int __init enable_drhd_fault_handling(void)
1855 {
1856         struct dmar_drhd_unit *drhd;
1857         struct intel_iommu *iommu;
1858
1859         /*
1860          * Enable fault control interrupt.
1861          */
1862         for_each_iommu(iommu, drhd) {
1863                 u32 fault_status;
1864                 int ret = dmar_set_interrupt(iommu);
1865
1866                 if (ret) {
1867                         pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
1868                                (unsigned long long)drhd->reg_base_addr, ret);
1869                         return -1;
1870                 }
1871
1872                 /*
1873                  * Clear any previous faults.
1874                  */
1875                 dmar_fault(iommu->irq, iommu);
1876                 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1877                 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1878         }
1879
1880         return 0;
1881 }
1882
1883 /*
1884  * Re-enable Queued Invalidation interface.
1885  */
1886 int dmar_reenable_qi(struct intel_iommu *iommu)
1887 {
1888         if (!ecap_qis(iommu->ecap))
1889                 return -ENOENT;
1890
1891         if (!iommu->qi)
1892                 return -ENOENT;
1893
1894         /*
1895          * First disable queued invalidation.
1896          */
1897         dmar_disable_qi(iommu);
1898         /*
1899          * Then enable queued invalidation again. Since there is no pending
1900          * invalidation requests now, it's safe to re-enable queued
1901          * invalidation.
1902          */
1903         __dmar_enable_qi(iommu);
1904
1905         return 0;
1906 }
1907
1908 /*
1909  * Check interrupt remapping support in DMAR table description.
1910  */
1911 int __init dmar_ir_support(void)
1912 {
1913         struct acpi_table_dmar *dmar;
1914         dmar = (struct acpi_table_dmar *)dmar_tbl;
1915         if (!dmar)
1916                 return 0;
1917         return dmar->flags & 0x1;
1918 }
1919
1920 /* Check whether DMAR units are in use */
1921 static inline bool dmar_in_use(void)
1922 {
1923         return irq_remapping_enabled || intel_iommu_enabled;
1924 }
1925
1926 static int __init dmar_free_unused_resources(void)
1927 {
1928         struct dmar_drhd_unit *dmaru, *dmaru_n;
1929
1930         if (dmar_in_use())
1931                 return 0;
1932
1933         if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1934                 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
1935
1936         down_write(&dmar_global_lock);
1937         list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1938                 list_del(&dmaru->list);
1939                 dmar_free_drhd(dmaru);
1940         }
1941         up_write(&dmar_global_lock);
1942
1943         return 0;
1944 }
1945
1946 late_initcall(dmar_free_unused_resources);
1947 IOMMU_INIT_POST(detect_intel_iommu);
1948
1949 /*
1950  * DMAR Hotplug Support
1951  * For more details, please refer to Intel(R) Virtualization Technology
1952  * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
1953  * "Remapping Hardware Unit Hot Plug".
1954  */
1955 static guid_t dmar_hp_guid =
1956         GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B,
1957                   0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF);
1958
1959 /*
1960  * Currently there's only one revision and BIOS will not check the revision id,
1961  * so use 0 for safety.
1962  */
1963 #define DMAR_DSM_REV_ID                 0
1964 #define DMAR_DSM_FUNC_DRHD              1
1965 #define DMAR_DSM_FUNC_ATSR              2
1966 #define DMAR_DSM_FUNC_RHSA              3
1967
1968 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
1969 {
1970         return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func);
1971 }
1972
1973 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
1974                                   dmar_res_handler_t handler, void *arg)
1975 {
1976         int ret = -ENODEV;
1977         union acpi_object *obj;
1978         struct acpi_dmar_header *start;
1979         struct dmar_res_callback callback;
1980         static int res_type[] = {
1981                 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
1982                 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
1983                 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
1984         };
1985
1986         if (!dmar_detect_dsm(handle, func))
1987                 return 0;
1988
1989         obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID,
1990                                       func, NULL, ACPI_TYPE_BUFFER);
1991         if (!obj)
1992                 return -ENODEV;
1993
1994         memset(&callback, 0, sizeof(callback));
1995         callback.cb[res_type[func]] = handler;
1996         callback.arg[res_type[func]] = arg;
1997         start = (struct acpi_dmar_header *)obj->buffer.pointer;
1998         ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
1999
2000         ACPI_FREE(obj);
2001
2002         return ret;
2003 }
2004
2005 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
2006 {
2007         int ret;
2008         struct dmar_drhd_unit *dmaru;
2009
2010         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2011         if (!dmaru)
2012                 return -ENODEV;
2013
2014         ret = dmar_ir_hotplug(dmaru, true);
2015         if (ret == 0)
2016                 ret = dmar_iommu_hotplug(dmaru, true);
2017
2018         return ret;
2019 }
2020
2021 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
2022 {
2023         int i, ret;
2024         struct device *dev;
2025         struct dmar_drhd_unit *dmaru;
2026
2027         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2028         if (!dmaru)
2029                 return 0;
2030
2031         /*
2032          * All PCI devices managed by this unit should have been destroyed.
2033          */
2034         if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
2035                 for_each_active_dev_scope(dmaru->devices,
2036                                           dmaru->devices_cnt, i, dev)
2037                         return -EBUSY;
2038         }
2039
2040         ret = dmar_ir_hotplug(dmaru, false);
2041         if (ret == 0)
2042                 ret = dmar_iommu_hotplug(dmaru, false);
2043
2044         return ret;
2045 }
2046
2047 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
2048 {
2049         struct dmar_drhd_unit *dmaru;
2050
2051         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2052         if (dmaru) {
2053                 list_del_rcu(&dmaru->list);
2054                 synchronize_rcu();
2055                 dmar_free_drhd(dmaru);
2056         }
2057
2058         return 0;
2059 }
2060
2061 static int dmar_hotplug_insert(acpi_handle handle)
2062 {
2063         int ret;
2064         int drhd_count = 0;
2065
2066         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2067                                      &dmar_validate_one_drhd, (void *)1);
2068         if (ret)
2069                 goto out;
2070
2071         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2072                                      &dmar_parse_one_drhd, (void *)&drhd_count);
2073         if (ret == 0 && drhd_count == 0) {
2074                 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
2075                 goto out;
2076         } else if (ret) {
2077                 goto release_drhd;
2078         }
2079
2080         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
2081                                      &dmar_parse_one_rhsa, NULL);
2082         if (ret)
2083                 goto release_drhd;
2084
2085         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2086                                      &dmar_parse_one_atsr, NULL);
2087         if (ret)
2088                 goto release_atsr;
2089
2090         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2091                                      &dmar_hp_add_drhd, NULL);
2092         if (!ret)
2093                 return 0;
2094
2095         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2096                                &dmar_hp_remove_drhd, NULL);
2097 release_atsr:
2098         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2099                                &dmar_release_one_atsr, NULL);
2100 release_drhd:
2101         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2102                                &dmar_hp_release_drhd, NULL);
2103 out:
2104         return ret;
2105 }
2106
2107 static int dmar_hotplug_remove(acpi_handle handle)
2108 {
2109         int ret;
2110
2111         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2112                                      &dmar_check_one_atsr, NULL);
2113         if (ret)
2114                 return ret;
2115
2116         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2117                                      &dmar_hp_remove_drhd, NULL);
2118         if (ret == 0) {
2119                 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2120                                                &dmar_release_one_atsr, NULL));
2121                 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2122                                                &dmar_hp_release_drhd, NULL));
2123         } else {
2124                 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2125                                        &dmar_hp_add_drhd, NULL);
2126         }
2127
2128         return ret;
2129 }
2130
2131 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
2132                                        void *context, void **retval)
2133 {
2134         acpi_handle *phdl = retval;
2135
2136         if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2137                 *phdl = handle;
2138                 return AE_CTRL_TERMINATE;
2139         }
2140
2141         return AE_OK;
2142 }
2143
2144 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2145 {
2146         int ret;
2147         acpi_handle tmp = NULL;
2148         acpi_status status;
2149
2150         if (!dmar_in_use())
2151                 return 0;
2152
2153         if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2154                 tmp = handle;
2155         } else {
2156                 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2157                                              ACPI_UINT32_MAX,
2158                                              dmar_get_dsm_handle,
2159                                              NULL, NULL, &tmp);
2160                 if (ACPI_FAILURE(status)) {
2161                         pr_warn("Failed to locate _DSM method.\n");
2162                         return -ENXIO;
2163                 }
2164         }
2165         if (tmp == NULL)
2166                 return 0;
2167
2168         down_write(&dmar_global_lock);
2169         if (insert)
2170                 ret = dmar_hotplug_insert(tmp);
2171         else
2172                 ret = dmar_hotplug_remove(tmp);
2173         up_write(&dmar_global_lock);
2174
2175         return ret;
2176 }
2177
2178 int dmar_device_add(acpi_handle handle)
2179 {
2180         return dmar_device_hotplug(handle, true);
2181 }
2182
2183 int dmar_device_remove(acpi_handle handle)
2184 {
2185         return dmar_device_hotplug(handle, false);
2186 }
2187
2188 /*
2189  * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2190  *
2191  * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in
2192  * the ACPI DMAR table. This means that the platform boot firmware has made
2193  * sure no device can issue DMA outside of RMRR regions.
2194  */
2195 bool dmar_platform_optin(void)
2196 {
2197         struct acpi_table_dmar *dmar;
2198         acpi_status status;
2199         bool ret;
2200
2201         status = acpi_get_table(ACPI_SIG_DMAR, 0,
2202                                 (struct acpi_table_header **)&dmar);
2203         if (ACPI_FAILURE(status))
2204                 return false;
2205
2206         ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN);
2207         acpi_put_table((struct acpi_table_header *)dmar);
2208
2209         return ret;
2210 }
2211 EXPORT_SYMBOL_GPL(dmar_platform_optin);