1 // SPDX-License-Identifier: GPL-2.0-only
3 * A fairly generic DMA-API to IOMMU-API glue layer.
5 * Copyright (C) 2014-2015 ARM Ltd.
7 * based in part on arch/arm/mm/dma-mapping.c:
8 * Copyright (C) 2000-2004 Russell King
11 #include <linux/acpi_iort.h>
12 #include <linux/device.h>
13 #include <linux/dma-map-ops.h>
14 #include <linux/dma-iommu.h>
15 #include <linux/gfp.h>
16 #include <linux/huge_mm.h>
17 #include <linux/iommu.h>
18 #include <linux/iova.h>
19 #include <linux/irq.h>
21 #include <linux/mutex.h>
22 #include <linux/pci.h>
23 #include <linux/swiotlb.h>
24 #include <linux/scatterlist.h>
25 #include <linux/vmalloc.h>
26 #include <linux/crash_dump.h>
27 #include <linux/dma-direct.h>
29 struct iommu_dma_msi_page {
30 struct list_head list;
35 enum iommu_dma_cookie_type {
36 IOMMU_DMA_IOVA_COOKIE,
40 struct iommu_dma_cookie {
41 enum iommu_dma_cookie_type type;
43 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */
44 struct iova_domain iovad;
45 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
48 struct list_head msi_page_list;
50 /* Domain for flush queue callback; NULL if flush queue not in use */
51 struct iommu_domain *fq_domain;
54 static DEFINE_STATIC_KEY_FALSE(iommu_deferred_attach_enabled);
56 void iommu_dma_free_cpu_cached_iovas(unsigned int cpu,
57 struct iommu_domain *domain)
59 struct iommu_dma_cookie *cookie = domain->iova_cookie;
60 struct iova_domain *iovad = &cookie->iovad;
62 free_cpu_cached_iovas(cpu, iovad);
65 static void iommu_dma_entry_dtor(unsigned long data)
67 struct page *freelist = (struct page *)data;
70 unsigned long p = (unsigned long)page_address(freelist);
72 freelist = freelist->freelist;
77 static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
79 if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
80 return cookie->iovad.granule;
84 static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
86 struct iommu_dma_cookie *cookie;
88 cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
90 INIT_LIST_HEAD(&cookie->msi_page_list);
97 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
98 * @domain: IOMMU domain to prepare for DMA-API usage
100 * IOMMU drivers should normally call this from their domain_alloc
101 * callback when domain->type == IOMMU_DOMAIN_DMA.
103 int iommu_get_dma_cookie(struct iommu_domain *domain)
105 if (domain->iova_cookie)
108 domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
109 if (!domain->iova_cookie)
114 EXPORT_SYMBOL(iommu_get_dma_cookie);
117 * iommu_get_msi_cookie - Acquire just MSI remapping resources
118 * @domain: IOMMU domain to prepare
119 * @base: Start address of IOVA region for MSI mappings
121 * Users who manage their own IOVA allocation and do not want DMA API support,
122 * but would still like to take advantage of automatic MSI remapping, can use
123 * this to initialise their own domain appropriately. Users should reserve a
124 * contiguous IOVA region, starting at @base, large enough to accommodate the
125 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
126 * used by the devices attached to @domain.
128 int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
130 struct iommu_dma_cookie *cookie;
132 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
135 if (domain->iova_cookie)
138 cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
142 cookie->msi_iova = base;
143 domain->iova_cookie = cookie;
146 EXPORT_SYMBOL(iommu_get_msi_cookie);
149 * iommu_put_dma_cookie - Release a domain's DMA mapping resources
150 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
151 * iommu_get_msi_cookie()
153 * IOMMU drivers should normally call this from their domain_free callback.
155 void iommu_put_dma_cookie(struct iommu_domain *domain)
157 struct iommu_dma_cookie *cookie = domain->iova_cookie;
158 struct iommu_dma_msi_page *msi, *tmp;
163 if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule)
164 put_iova_domain(&cookie->iovad);
166 list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
167 list_del(&msi->list);
171 domain->iova_cookie = NULL;
173 EXPORT_SYMBOL(iommu_put_dma_cookie);
176 * iommu_dma_get_resv_regions - Reserved region driver helper
177 * @dev: Device from iommu_get_resv_regions()
178 * @list: Reserved region list from iommu_get_resv_regions()
180 * IOMMU drivers can use this to implement their .get_resv_regions callback
181 * for general non-IOMMU-specific reservations. Currently, this covers GICv3
182 * ITS region reservation on ACPI based ARM platforms that may require HW MSI
185 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
188 if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode))
189 iort_iommu_msi_get_resv_regions(dev, list);
192 EXPORT_SYMBOL(iommu_dma_get_resv_regions);
194 static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie,
195 phys_addr_t start, phys_addr_t end)
197 struct iova_domain *iovad = &cookie->iovad;
198 struct iommu_dma_msi_page *msi_page;
201 start -= iova_offset(iovad, start);
202 num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
204 for (i = 0; i < num_pages; i++) {
205 msi_page = kmalloc(sizeof(*msi_page), GFP_KERNEL);
209 msi_page->phys = start;
210 msi_page->iova = start;
211 INIT_LIST_HEAD(&msi_page->list);
212 list_add(&msi_page->list, &cookie->msi_page_list);
213 start += iovad->granule;
219 static int iova_reserve_pci_windows(struct pci_dev *dev,
220 struct iova_domain *iovad)
222 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
223 struct resource_entry *window;
224 unsigned long lo, hi;
225 phys_addr_t start = 0, end;
227 resource_list_for_each_entry(window, &bridge->windows) {
228 if (resource_type(window->res) != IORESOURCE_MEM)
231 lo = iova_pfn(iovad, window->res->start - window->offset);
232 hi = iova_pfn(iovad, window->res->end - window->offset);
233 reserve_iova(iovad, lo, hi);
236 /* Get reserved DMA windows from host bridge */
237 resource_list_for_each_entry(window, &bridge->dma_ranges) {
238 end = window->res->start - window->offset;
241 lo = iova_pfn(iovad, start);
242 hi = iova_pfn(iovad, end);
243 reserve_iova(iovad, lo, hi);
245 /* dma_ranges list should be sorted */
246 dev_err(&dev->dev, "Failed to reserve IOVA\n");
250 start = window->res->end - window->offset + 1;
251 /* If window is last entry */
252 if (window->node.next == &bridge->dma_ranges &&
253 end != ~(phys_addr_t)0) {
254 end = ~(phys_addr_t)0;
262 static int iova_reserve_iommu_regions(struct device *dev,
263 struct iommu_domain *domain)
265 struct iommu_dma_cookie *cookie = domain->iova_cookie;
266 struct iova_domain *iovad = &cookie->iovad;
267 struct iommu_resv_region *region;
268 LIST_HEAD(resv_regions);
271 if (dev_is_pci(dev)) {
272 ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad);
277 iommu_get_resv_regions(dev, &resv_regions);
278 list_for_each_entry(region, &resv_regions, list) {
279 unsigned long lo, hi;
281 /* We ARE the software that manages these! */
282 if (region->type == IOMMU_RESV_SW_MSI)
285 lo = iova_pfn(iovad, region->start);
286 hi = iova_pfn(iovad, region->start + region->length - 1);
287 reserve_iova(iovad, lo, hi);
289 if (region->type == IOMMU_RESV_MSI)
290 ret = cookie_init_hw_msi_region(cookie, region->start,
291 region->start + region->length);
295 iommu_put_resv_regions(dev, &resv_regions);
300 static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad)
302 struct iommu_dma_cookie *cookie;
303 struct iommu_domain *domain;
305 cookie = container_of(iovad, struct iommu_dma_cookie, iovad);
306 domain = cookie->fq_domain;
308 * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE
309 * implies that ops->flush_iotlb_all must be non-NULL.
311 domain->ops->flush_iotlb_all(domain);
314 static bool dev_is_untrusted(struct device *dev)
316 return dev_is_pci(dev) && to_pci_dev(dev)->untrusted;
320 * iommu_dma_init_domain - Initialise a DMA mapping domain
321 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
322 * @base: IOVA at which the mappable address space starts
323 * @size: Size of IOVA space
324 * @dev: Device the domain is being initialised for
326 * @base and @size should be exact multiples of IOMMU page granularity to
327 * avoid rounding surprises. If necessary, we reserve the page at address 0
328 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
329 * any change which could make prior IOVAs invalid will fail.
331 static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
332 u64 size, struct device *dev)
334 struct iommu_dma_cookie *cookie = domain->iova_cookie;
335 unsigned long order, base_pfn;
336 struct iova_domain *iovad;
339 if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
342 iovad = &cookie->iovad;
344 /* Use the smallest supported page size for IOVA granularity */
345 order = __ffs(domain->pgsize_bitmap);
346 base_pfn = max_t(unsigned long, 1, base >> order);
348 /* Check the domain allows at least some access to the device... */
349 if (domain->geometry.force_aperture) {
350 if (base > domain->geometry.aperture_end ||
351 base + size <= domain->geometry.aperture_start) {
352 pr_warn("specified DMA range outside IOMMU capability\n");
355 /* ...then finally give it a kicking to make sure it fits */
356 base_pfn = max_t(unsigned long, base_pfn,
357 domain->geometry.aperture_start >> order);
360 /* start_pfn is always nonzero for an already-initialised domain */
361 if (iovad->start_pfn) {
362 if (1UL << order != iovad->granule ||
363 base_pfn != iovad->start_pfn) {
364 pr_warn("Incompatible range for DMA domain\n");
371 init_iova_domain(iovad, 1UL << order, base_pfn);
373 if (!cookie->fq_domain && (!dev || !dev_is_untrusted(dev)) &&
374 !iommu_domain_get_attr(domain, DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) &&
376 if (init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all,
377 iommu_dma_entry_dtor))
378 pr_warn("iova flush queue initialization failed\n");
380 cookie->fq_domain = domain;
386 return iova_reserve_iommu_regions(dev, domain);
390 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
392 * @dir: Direction of DMA transfer
393 * @coherent: Is the DMA master cache-coherent?
394 * @attrs: DMA attributes for the mapping
396 * Return: corresponding IOMMU API page protection flags
398 static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
401 int prot = coherent ? IOMMU_CACHE : 0;
403 if (attrs & DMA_ATTR_PRIVILEGED)
407 case DMA_BIDIRECTIONAL:
408 return prot | IOMMU_READ | IOMMU_WRITE;
410 return prot | IOMMU_READ;
411 case DMA_FROM_DEVICE:
412 return prot | IOMMU_WRITE;
418 static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
419 size_t size, u64 dma_limit, struct device *dev)
421 struct iommu_dma_cookie *cookie = domain->iova_cookie;
422 struct iova_domain *iovad = &cookie->iovad;
423 unsigned long shift, iova_len, iova = 0;
425 if (cookie->type == IOMMU_DMA_MSI_COOKIE) {
426 cookie->msi_iova += size;
427 return cookie->msi_iova - size;
430 shift = iova_shift(iovad);
431 iova_len = size >> shift;
433 * Freeing non-power-of-two-sized allocations back into the IOVA caches
434 * will come back to bite us badly, so we have to waste a bit of space
435 * rounding up anything cacheable to make sure that can't happen. The
436 * order of the unadjusted size will still match upon freeing.
438 if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1)))
439 iova_len = roundup_pow_of_two(iova_len);
441 dma_limit = min_not_zero(dma_limit, dev->bus_dma_limit);
443 if (domain->geometry.force_aperture)
444 dma_limit = min(dma_limit, (u64)domain->geometry.aperture_end);
446 /* Try to get PCI devices a SAC address */
447 if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev))
448 iova = alloc_iova_fast(iovad, iova_len,
449 DMA_BIT_MASK(32) >> shift, false);
452 iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift,
455 return (dma_addr_t)iova << shift;
458 static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie,
459 dma_addr_t iova, size_t size, struct page *freelist)
461 struct iova_domain *iovad = &cookie->iovad;
463 /* The MSI case is only ever cleaning up its most recent allocation */
464 if (cookie->type == IOMMU_DMA_MSI_COOKIE)
465 cookie->msi_iova -= size;
466 else if (cookie->fq_domain) /* non-strict mode */
467 queue_iova(iovad, iova_pfn(iovad, iova),
468 size >> iova_shift(iovad),
469 (unsigned long)freelist);
471 free_iova_fast(iovad, iova_pfn(iovad, iova),
472 size >> iova_shift(iovad));
475 static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr,
478 struct iommu_domain *domain = iommu_get_dma_domain(dev);
479 struct iommu_dma_cookie *cookie = domain->iova_cookie;
480 struct iova_domain *iovad = &cookie->iovad;
481 size_t iova_off = iova_offset(iovad, dma_addr);
482 struct iommu_iotlb_gather iotlb_gather;
485 dma_addr -= iova_off;
486 size = iova_align(iovad, size + iova_off);
487 iommu_iotlb_gather_init(&iotlb_gather);
489 unmapped = iommu_unmap_fast(domain, dma_addr, size, &iotlb_gather);
490 WARN_ON(unmapped != size);
492 if (!cookie->fq_domain)
493 iommu_iotlb_sync(domain, &iotlb_gather);
494 iommu_dma_free_iova(cookie, dma_addr, size, iotlb_gather.freelist);
497 static void __iommu_dma_unmap_swiotlb(struct device *dev, dma_addr_t dma_addr,
498 size_t size, enum dma_data_direction dir,
501 struct iommu_domain *domain = iommu_get_dma_domain(dev);
502 struct iommu_dma_cookie *cookie = domain->iova_cookie;
503 struct iova_domain *iovad = &cookie->iovad;
506 phys = iommu_iova_to_phys(domain, dma_addr);
510 __iommu_dma_unmap(dev, dma_addr, size);
512 if (unlikely(is_swiotlb_buffer(phys)))
513 swiotlb_tbl_unmap_single(dev, phys, size,
514 iova_align(iovad, size), dir, attrs);
517 static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
518 size_t size, int prot, u64 dma_mask)
520 struct iommu_domain *domain = iommu_get_dma_domain(dev);
521 struct iommu_dma_cookie *cookie = domain->iova_cookie;
522 struct iova_domain *iovad = &cookie->iovad;
523 size_t iova_off = iova_offset(iovad, phys);
526 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
527 iommu_deferred_attach(dev, domain))
528 return DMA_MAPPING_ERROR;
530 size = iova_align(iovad, size + iova_off);
532 iova = iommu_dma_alloc_iova(domain, size, dma_mask, dev);
534 return DMA_MAPPING_ERROR;
536 if (iommu_map_atomic(domain, iova, phys - iova_off, size, prot)) {
537 iommu_dma_free_iova(cookie, iova, size, NULL);
538 return DMA_MAPPING_ERROR;
540 return iova + iova_off;
543 static dma_addr_t __iommu_dma_map_swiotlb(struct device *dev, phys_addr_t phys,
544 size_t org_size, dma_addr_t dma_mask, bool coherent,
545 enum dma_data_direction dir, unsigned long attrs)
547 int prot = dma_info_to_prot(dir, coherent, attrs);
548 struct iommu_domain *domain = iommu_get_dma_domain(dev);
549 struct iommu_dma_cookie *cookie = domain->iova_cookie;
550 struct iova_domain *iovad = &cookie->iovad;
551 size_t aligned_size = org_size;
557 * If both the physical buffer start address and size are
558 * page aligned, we don't need to use a bounce page.
560 if (IS_ENABLED(CONFIG_SWIOTLB) && dev_is_untrusted(dev) &&
561 iova_offset(iovad, phys | org_size)) {
562 aligned_size = iova_align(iovad, org_size);
563 phys = swiotlb_tbl_map_single(dev, phys, org_size,
564 aligned_size, dir, attrs);
566 if (phys == DMA_MAPPING_ERROR)
567 return DMA_MAPPING_ERROR;
569 /* Cleanup the padding area. */
570 padding_start = phys_to_virt(phys);
571 padding_size = aligned_size;
573 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
574 (dir == DMA_TO_DEVICE ||
575 dir == DMA_BIDIRECTIONAL)) {
576 padding_start += org_size;
577 padding_size -= org_size;
580 memset(padding_start, 0, padding_size);
583 iova = __iommu_dma_map(dev, phys, aligned_size, prot, dma_mask);
584 if ((iova == DMA_MAPPING_ERROR) && is_swiotlb_buffer(phys))
585 swiotlb_tbl_unmap_single(dev, phys, org_size,
586 aligned_size, dir, attrs);
591 static void __iommu_dma_free_pages(struct page **pages, int count)
594 __free_page(pages[count]);
598 static struct page **__iommu_dma_alloc_pages(struct device *dev,
599 unsigned int count, unsigned long order_mask, gfp_t gfp)
602 unsigned int i = 0, nid = dev_to_node(dev);
604 order_mask &= (2U << MAX_ORDER) - 1;
608 pages = kvzalloc(count * sizeof(*pages), GFP_KERNEL);
612 /* IOMMU can map any pages, so himem can also be used here */
613 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
615 /* It makes no sense to muck about with huge pages */
619 struct page *page = NULL;
620 unsigned int order_size;
623 * Higher-order allocations are a convenience rather
624 * than a necessity, hence using __GFP_NORETRY until
625 * falling back to minimum-order allocations.
627 for (order_mask &= (2U << __fls(count)) - 1;
628 order_mask; order_mask &= ~order_size) {
629 unsigned int order = __fls(order_mask);
630 gfp_t alloc_flags = gfp;
632 order_size = 1U << order;
633 if (order_mask > order_size)
634 alloc_flags |= __GFP_NORETRY;
635 page = alloc_pages_node(nid, alloc_flags, order);
639 split_page(page, order);
643 __iommu_dma_free_pages(pages, i);
654 * iommu_dma_alloc_remap - Allocate and map a buffer contiguous in IOVA space
655 * @dev: Device to allocate memory for. Must be a real device
656 * attached to an iommu_dma_domain
657 * @size: Size of buffer in bytes
658 * @dma_handle: Out argument for allocated DMA handle
659 * @gfp: Allocation flags
660 * @prot: pgprot_t to use for the remapped mapping
661 * @attrs: DMA attributes for this allocation
663 * If @size is less than PAGE_SIZE, then a full CPU page will be allocated,
664 * but an IOMMU which supports smaller pages might not map the whole thing.
666 * Return: Mapped virtual address, or NULL on failure.
668 static void *iommu_dma_alloc_remap(struct device *dev, size_t size,
669 dma_addr_t *dma_handle, gfp_t gfp, pgprot_t prot,
672 struct iommu_domain *domain = iommu_get_dma_domain(dev);
673 struct iommu_dma_cookie *cookie = domain->iova_cookie;
674 struct iova_domain *iovad = &cookie->iovad;
675 bool coherent = dev_is_dma_coherent(dev);
676 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
677 unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
683 *dma_handle = DMA_MAPPING_ERROR;
685 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
686 iommu_deferred_attach(dev, domain))
689 min_size = alloc_sizes & -alloc_sizes;
690 if (min_size < PAGE_SIZE) {
691 min_size = PAGE_SIZE;
692 alloc_sizes |= PAGE_SIZE;
694 size = ALIGN(size, min_size);
696 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
697 alloc_sizes = min_size;
699 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
700 pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT,
705 size = iova_align(iovad, size);
706 iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev);
710 if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL))
713 if (!(ioprot & IOMMU_CACHE)) {
714 struct scatterlist *sg;
717 for_each_sg(sgt.sgl, sg, sgt.orig_nents, i)
718 arch_dma_prep_coherent(sg_page(sg), sg->length);
721 if (iommu_map_sg_atomic(domain, iova, sgt.sgl, sgt.orig_nents, ioprot)
725 vaddr = dma_common_pages_remap(pages, size, prot,
726 __builtin_return_address(0));
735 __iommu_dma_unmap(dev, iova, size);
739 iommu_dma_free_iova(cookie, iova, size, NULL);
741 __iommu_dma_free_pages(pages, count);
745 static void iommu_dma_sync_single_for_cpu(struct device *dev,
746 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
750 if (dev_is_dma_coherent(dev) && !dev_is_untrusted(dev))
753 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
754 if (!dev_is_dma_coherent(dev))
755 arch_sync_dma_for_cpu(phys, size, dir);
757 if (is_swiotlb_buffer(phys))
758 swiotlb_tbl_sync_single(dev, phys, size, dir, SYNC_FOR_CPU);
761 static void iommu_dma_sync_single_for_device(struct device *dev,
762 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
766 if (dev_is_dma_coherent(dev) && !dev_is_untrusted(dev))
769 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
770 if (is_swiotlb_buffer(phys))
771 swiotlb_tbl_sync_single(dev, phys, size, dir, SYNC_FOR_DEVICE);
773 if (!dev_is_dma_coherent(dev))
774 arch_sync_dma_for_device(phys, size, dir);
777 static void iommu_dma_sync_sg_for_cpu(struct device *dev,
778 struct scatterlist *sgl, int nelems,
779 enum dma_data_direction dir)
781 struct scatterlist *sg;
784 if (dev_is_dma_coherent(dev) && !dev_is_untrusted(dev))
787 for_each_sg(sgl, sg, nelems, i) {
788 if (!dev_is_dma_coherent(dev))
789 arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir);
791 if (is_swiotlb_buffer(sg_phys(sg)))
792 swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length,
797 static void iommu_dma_sync_sg_for_device(struct device *dev,
798 struct scatterlist *sgl, int nelems,
799 enum dma_data_direction dir)
801 struct scatterlist *sg;
804 if (dev_is_dma_coherent(dev) && !dev_is_untrusted(dev))
807 for_each_sg(sgl, sg, nelems, i) {
808 if (is_swiotlb_buffer(sg_phys(sg)))
809 swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length,
810 dir, SYNC_FOR_DEVICE);
812 if (!dev_is_dma_coherent(dev))
813 arch_sync_dma_for_device(sg_phys(sg), sg->length, dir);
817 static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
818 unsigned long offset, size_t size, enum dma_data_direction dir,
821 phys_addr_t phys = page_to_phys(page) + offset;
822 bool coherent = dev_is_dma_coherent(dev);
823 dma_addr_t dma_handle;
825 dma_handle = __iommu_dma_map_swiotlb(dev, phys, size, dma_get_mask(dev),
826 coherent, dir, attrs);
827 if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
828 dma_handle != DMA_MAPPING_ERROR)
829 arch_sync_dma_for_device(phys, size, dir);
833 static void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
834 size_t size, enum dma_data_direction dir, unsigned long attrs)
836 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
837 iommu_dma_sync_single_for_cpu(dev, dma_handle, size, dir);
838 __iommu_dma_unmap_swiotlb(dev, dma_handle, size, dir, attrs);
842 * Prepare a successfully-mapped scatterlist to give back to the caller.
844 * At this point the segments are already laid out by iommu_dma_map_sg() to
845 * avoid individually crossing any boundaries, so we merely need to check a
846 * segment's start address to avoid concatenating across one.
848 static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents,
851 struct scatterlist *s, *cur = sg;
852 unsigned long seg_mask = dma_get_seg_boundary(dev);
853 unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
856 for_each_sg(sg, s, nents, i) {
857 /* Restore this segment's original unaligned fields first */
858 unsigned int s_iova_off = sg_dma_address(s);
859 unsigned int s_length = sg_dma_len(s);
860 unsigned int s_iova_len = s->length;
862 s->offset += s_iova_off;
863 s->length = s_length;
864 sg_dma_address(s) = DMA_MAPPING_ERROR;
868 * Now fill in the real DMA data. If...
869 * - there is a valid output segment to append to
870 * - and this segment starts on an IOVA page boundary
871 * - but doesn't fall at a segment boundary
872 * - and wouldn't make the resulting output segment too long
874 if (cur_len && !s_iova_off && (dma_addr & seg_mask) &&
875 (max_len - cur_len >= s_length)) {
876 /* ...then concatenate it with the previous one */
879 /* Otherwise start the next output segment */
885 sg_dma_address(cur) = dma_addr + s_iova_off;
888 sg_dma_len(cur) = cur_len;
889 dma_addr += s_iova_len;
891 if (s_length + s_iova_off < s_iova_len)
898 * If mapping failed, then just restore the original list,
899 * but making sure the DMA fields are invalidated.
901 static void __invalidate_sg(struct scatterlist *sg, int nents)
903 struct scatterlist *s;
906 for_each_sg(sg, s, nents, i) {
907 if (sg_dma_address(s) != DMA_MAPPING_ERROR)
908 s->offset += sg_dma_address(s);
910 s->length = sg_dma_len(s);
911 sg_dma_address(s) = DMA_MAPPING_ERROR;
916 static void iommu_dma_unmap_sg_swiotlb(struct device *dev, struct scatterlist *sg,
917 int nents, enum dma_data_direction dir, unsigned long attrs)
919 struct scatterlist *s;
922 for_each_sg(sg, s, nents, i)
923 __iommu_dma_unmap_swiotlb(dev, sg_dma_address(s),
924 sg_dma_len(s), dir, attrs);
927 static int iommu_dma_map_sg_swiotlb(struct device *dev, struct scatterlist *sg,
928 int nents, enum dma_data_direction dir, unsigned long attrs)
930 struct scatterlist *s;
933 for_each_sg(sg, s, nents, i) {
934 sg_dma_address(s) = __iommu_dma_map_swiotlb(dev, sg_phys(s),
935 s->length, dma_get_mask(dev),
936 dev_is_dma_coherent(dev), dir, attrs);
937 if (sg_dma_address(s) == DMA_MAPPING_ERROR)
939 sg_dma_len(s) = s->length;
945 iommu_dma_unmap_sg_swiotlb(dev, sg, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
950 * The DMA API client is passing in a scatterlist which could describe
951 * any old buffer layout, but the IOMMU API requires everything to be
952 * aligned to IOMMU pages. Hence the need for this complicated bit of
953 * impedance-matching, to be able to hand off a suitably-aligned list,
954 * but still preserve the original offsets and sizes for the caller.
956 static int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg,
957 int nents, enum dma_data_direction dir, unsigned long attrs)
959 struct iommu_domain *domain = iommu_get_dma_domain(dev);
960 struct iommu_dma_cookie *cookie = domain->iova_cookie;
961 struct iova_domain *iovad = &cookie->iovad;
962 struct scatterlist *s, *prev = NULL;
963 int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs);
966 unsigned long mask = dma_get_seg_boundary(dev);
969 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
970 iommu_deferred_attach(dev, domain))
973 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
974 iommu_dma_sync_sg_for_device(dev, sg, nents, dir);
976 if (dev_is_untrusted(dev))
977 return iommu_dma_map_sg_swiotlb(dev, sg, nents, dir, attrs);
980 * Work out how much IOVA space we need, and align the segments to
981 * IOVA granules for the IOMMU driver to handle. With some clever
982 * trickery we can modify the list in-place, but reversibly, by
983 * stashing the unaligned parts in the as-yet-unused DMA fields.
985 for_each_sg(sg, s, nents, i) {
986 size_t s_iova_off = iova_offset(iovad, s->offset);
987 size_t s_length = s->length;
988 size_t pad_len = (mask - iova_len + 1) & mask;
990 sg_dma_address(s) = s_iova_off;
991 sg_dma_len(s) = s_length;
992 s->offset -= s_iova_off;
993 s_length = iova_align(iovad, s_length + s_iova_off);
994 s->length = s_length;
997 * Due to the alignment of our single IOVA allocation, we can
998 * depend on these assumptions about the segment boundary mask:
999 * - If mask size >= IOVA size, then the IOVA range cannot
1000 * possibly fall across a boundary, so we don't care.
1001 * - If mask size < IOVA size, then the IOVA range must start
1002 * exactly on a boundary, therefore we can lay things out
1003 * based purely on segment lengths without needing to know
1004 * the actual addresses beforehand.
1005 * - The mask must be a power of 2, so pad_len == 0 if
1006 * iova_len == 0, thus we cannot dereference prev the first
1007 * time through here (i.e. before it has a meaningful value).
1009 if (pad_len && pad_len < s_length - 1) {
1010 prev->length += pad_len;
1011 iova_len += pad_len;
1014 iova_len += s_length;
1018 iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev);
1020 goto out_restore_sg;
1023 * We'll leave any physical concatenation to the IOMMU driver's
1024 * implementation - it knows better than we do.
1026 if (iommu_map_sg_atomic(domain, iova, sg, nents, prot) < iova_len)
1029 return __finalise_sg(dev, sg, nents, iova);
1032 iommu_dma_free_iova(cookie, iova, iova_len, NULL);
1034 __invalidate_sg(sg, nents);
1038 static void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
1039 int nents, enum dma_data_direction dir, unsigned long attrs)
1041 dma_addr_t start, end;
1042 struct scatterlist *tmp;
1045 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1046 iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir);
1048 if (dev_is_untrusted(dev)) {
1049 iommu_dma_unmap_sg_swiotlb(dev, sg, nents, dir, attrs);
1054 * The scatterlist segments are mapped into a single
1055 * contiguous IOVA allocation, so this is incredibly easy.
1057 start = sg_dma_address(sg);
1058 for_each_sg(sg_next(sg), tmp, nents - 1, i) {
1059 if (sg_dma_len(tmp) == 0)
1063 end = sg_dma_address(sg) + sg_dma_len(sg);
1064 __iommu_dma_unmap(dev, start, end - start);
1067 static dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
1068 size_t size, enum dma_data_direction dir, unsigned long attrs)
1070 return __iommu_dma_map(dev, phys, size,
1071 dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
1075 static void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
1076 size_t size, enum dma_data_direction dir, unsigned long attrs)
1078 __iommu_dma_unmap(dev, handle, size);
1081 static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
1083 size_t alloc_size = PAGE_ALIGN(size);
1084 int count = alloc_size >> PAGE_SHIFT;
1085 struct page *page = NULL, **pages = NULL;
1087 /* Non-coherent atomic allocation? Easy */
1088 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1089 dma_free_from_pool(dev, cpu_addr, alloc_size))
1092 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1094 * If it the address is remapped, then it's either non-coherent
1095 * or highmem CMA, or an iommu_dma_alloc_remap() construction.
1097 pages = dma_common_find_pages(cpu_addr);
1099 page = vmalloc_to_page(cpu_addr);
1100 dma_common_free_remap(cpu_addr, alloc_size);
1102 /* Lowmem means a coherent atomic or CMA allocation */
1103 page = virt_to_page(cpu_addr);
1107 __iommu_dma_free_pages(pages, count);
1109 dma_free_contiguous(dev, page, alloc_size);
1112 static void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
1113 dma_addr_t handle, unsigned long attrs)
1115 __iommu_dma_unmap(dev, handle, size);
1116 __iommu_dma_free(dev, size, cpu_addr);
1119 static void *iommu_dma_alloc_pages(struct device *dev, size_t size,
1120 struct page **pagep, gfp_t gfp, unsigned long attrs)
1122 bool coherent = dev_is_dma_coherent(dev);
1123 size_t alloc_size = PAGE_ALIGN(size);
1124 int node = dev_to_node(dev);
1125 struct page *page = NULL;
1128 page = dma_alloc_contiguous(dev, alloc_size, gfp);
1130 page = alloc_pages_node(node, gfp, get_order(alloc_size));
1134 if (IS_ENABLED(CONFIG_DMA_REMAP) && (!coherent || PageHighMem(page))) {
1135 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
1137 cpu_addr = dma_common_contiguous_remap(page, alloc_size,
1138 prot, __builtin_return_address(0));
1140 goto out_free_pages;
1143 arch_dma_prep_coherent(page, size);
1145 cpu_addr = page_address(page);
1149 memset(cpu_addr, 0, alloc_size);
1152 dma_free_contiguous(dev, page, alloc_size);
1156 static void *iommu_dma_alloc(struct device *dev, size_t size,
1157 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1159 bool coherent = dev_is_dma_coherent(dev);
1160 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
1161 struct page *page = NULL;
1166 if (IS_ENABLED(CONFIG_DMA_REMAP) && gfpflags_allow_blocking(gfp) &&
1167 !(attrs & DMA_ATTR_FORCE_CONTIGUOUS)) {
1168 return iommu_dma_alloc_remap(dev, size, handle, gfp,
1169 dma_pgprot(dev, PAGE_KERNEL, attrs), attrs);
1172 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1173 !gfpflags_allow_blocking(gfp) && !coherent)
1174 page = dma_alloc_from_pool(dev, PAGE_ALIGN(size), &cpu_addr,
1177 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs);
1181 *handle = __iommu_dma_map(dev, page_to_phys(page), size, ioprot,
1182 dev->coherent_dma_mask);
1183 if (*handle == DMA_MAPPING_ERROR) {
1184 __iommu_dma_free(dev, size, cpu_addr);
1191 static int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
1192 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1193 unsigned long attrs)
1195 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1196 unsigned long pfn, off = vma->vm_pgoff;
1199 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
1201 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
1204 if (off >= nr_pages || vma_pages(vma) > nr_pages - off)
1207 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1208 struct page **pages = dma_common_find_pages(cpu_addr);
1211 return vm_map_pages(vma, pages, nr_pages);
1212 pfn = vmalloc_to_pfn(cpu_addr);
1214 pfn = page_to_pfn(virt_to_page(cpu_addr));
1217 return remap_pfn_range(vma, vma->vm_start, pfn + off,
1218 vma->vm_end - vma->vm_start,
1222 static int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
1223 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1224 unsigned long attrs)
1229 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1230 struct page **pages = dma_common_find_pages(cpu_addr);
1233 return sg_alloc_table_from_pages(sgt, pages,
1234 PAGE_ALIGN(size) >> PAGE_SHIFT,
1235 0, size, GFP_KERNEL);
1238 page = vmalloc_to_page(cpu_addr);
1240 page = virt_to_page(cpu_addr);
1243 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
1245 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
1249 static unsigned long iommu_dma_get_merge_boundary(struct device *dev)
1251 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1253 return (1UL << __ffs(domain->pgsize_bitmap)) - 1;
1256 static const struct dma_map_ops iommu_dma_ops = {
1257 .alloc = iommu_dma_alloc,
1258 .free = iommu_dma_free,
1259 .alloc_pages = dma_common_alloc_pages,
1260 .free_pages = dma_common_free_pages,
1261 .mmap = iommu_dma_mmap,
1262 .get_sgtable = iommu_dma_get_sgtable,
1263 .map_page = iommu_dma_map_page,
1264 .unmap_page = iommu_dma_unmap_page,
1265 .map_sg = iommu_dma_map_sg,
1266 .unmap_sg = iommu_dma_unmap_sg,
1267 .sync_single_for_cpu = iommu_dma_sync_single_for_cpu,
1268 .sync_single_for_device = iommu_dma_sync_single_for_device,
1269 .sync_sg_for_cpu = iommu_dma_sync_sg_for_cpu,
1270 .sync_sg_for_device = iommu_dma_sync_sg_for_device,
1271 .map_resource = iommu_dma_map_resource,
1272 .unmap_resource = iommu_dma_unmap_resource,
1273 .get_merge_boundary = iommu_dma_get_merge_boundary,
1277 * The IOMMU core code allocates the default DMA domain, which the underlying
1278 * IOMMU driver needs to support via the dma-iommu layer.
1280 void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size)
1282 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1288 * The IOMMU core code allocates the default DMA domain, which the
1289 * underlying IOMMU driver needs to support via the dma-iommu layer.
1291 if (domain->type == IOMMU_DOMAIN_DMA) {
1292 if (iommu_dma_init_domain(domain, dma_base, size, dev))
1294 dev->dma_ops = &iommu_dma_ops;
1299 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
1303 static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
1304 phys_addr_t msi_addr, struct iommu_domain *domain)
1306 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1307 struct iommu_dma_msi_page *msi_page;
1309 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
1310 size_t size = cookie_msi_granule(cookie);
1312 msi_addr &= ~(phys_addr_t)(size - 1);
1313 list_for_each_entry(msi_page, &cookie->msi_page_list, list)
1314 if (msi_page->phys == msi_addr)
1317 msi_page = kzalloc(sizeof(*msi_page), GFP_KERNEL);
1321 iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
1325 if (iommu_map(domain, iova, msi_addr, size, prot))
1328 INIT_LIST_HEAD(&msi_page->list);
1329 msi_page->phys = msi_addr;
1330 msi_page->iova = iova;
1331 list_add(&msi_page->list, &cookie->msi_page_list);
1335 iommu_dma_free_iova(cookie, iova, size, NULL);
1341 int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
1343 struct device *dev = msi_desc_to_dev(desc);
1344 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1345 struct iommu_dma_msi_page *msi_page;
1346 static DEFINE_MUTEX(msi_prepare_lock); /* see below */
1348 if (!domain || !domain->iova_cookie) {
1349 desc->iommu_cookie = NULL;
1354 * In fact the whole prepare operation should already be serialised by
1355 * irq_domain_mutex further up the callchain, but that's pretty subtle
1356 * on its own, so consider this locking as failsafe documentation...
1358 mutex_lock(&msi_prepare_lock);
1359 msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
1360 mutex_unlock(&msi_prepare_lock);
1362 msi_desc_set_iommu_cookie(desc, msi_page);
1369 void iommu_dma_compose_msi_msg(struct msi_desc *desc,
1370 struct msi_msg *msg)
1372 struct device *dev = msi_desc_to_dev(desc);
1373 const struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1374 const struct iommu_dma_msi_page *msi_page;
1376 msi_page = msi_desc_get_iommu_cookie(desc);
1378 if (!domain || !domain->iova_cookie || WARN_ON(!msi_page))
1381 msg->address_hi = upper_32_bits(msi_page->iova);
1382 msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1;
1383 msg->address_lo += lower_32_bits(msi_page->iova);
1386 static int iommu_dma_init(void)
1388 if (is_kdump_kernel())
1389 static_branch_enable(&iommu_deferred_attach_enabled);
1391 return iova_cache_get();
1393 arch_initcall(iommu_dma_init);