1 // SPDX-License-Identifier: GPL-2.0-only
3 * A fairly generic DMA-API to IOMMU-API glue layer.
5 * Copyright (C) 2014-2015 ARM Ltd.
7 * based in part on arch/arm/mm/dma-mapping.c:
8 * Copyright (C) 2000-2004 Russell King
11 #include <linux/acpi_iort.h>
12 #include <linux/atomic.h>
13 #include <linux/crash_dump.h>
14 #include <linux/device.h>
15 #include <linux/dma-direct.h>
16 #include <linux/dma-map-ops.h>
17 #include <linux/gfp.h>
18 #include <linux/huge_mm.h>
19 #include <linux/iommu.h>
20 #include <linux/iova.h>
21 #include <linux/irq.h>
22 #include <linux/list_sort.h>
23 #include <linux/memremap.h>
25 #include <linux/mutex.h>
26 #include <linux/of_iommu.h>
27 #include <linux/pci.h>
28 #include <linux/scatterlist.h>
29 #include <linux/spinlock.h>
30 #include <linux/swiotlb.h>
31 #include <linux/vmalloc.h>
33 #include "dma-iommu.h"
35 struct iommu_dma_msi_page {
36 struct list_head list;
41 enum iommu_dma_cookie_type {
42 IOMMU_DMA_IOVA_COOKIE,
46 struct iommu_dma_cookie {
47 enum iommu_dma_cookie_type type;
49 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */
51 struct iova_domain iovad;
53 struct iova_fq __percpu *fq; /* Flush queue */
54 /* Number of TLB flushes that have been started */
55 atomic64_t fq_flush_start_cnt;
56 /* Number of TLB flushes that have been finished */
57 atomic64_t fq_flush_finish_cnt;
58 /* Timer to regularily empty the flush queues */
59 struct timer_list fq_timer;
60 /* 1 when timer is active, 0 when not */
63 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
66 struct list_head msi_page_list;
68 /* Domain for flush queue callback; NULL if flush queue not in use */
69 struct iommu_domain *fq_domain;
73 static DEFINE_STATIC_KEY_FALSE(iommu_deferred_attach_enabled);
74 bool iommu_dma_forcedac __read_mostly;
76 static int __init iommu_dma_forcedac_setup(char *str)
78 int ret = kstrtobool(str, &iommu_dma_forcedac);
80 if (!ret && iommu_dma_forcedac)
81 pr_info("Forcing DAC for PCI devices\n");
84 early_param("iommu.forcedac", iommu_dma_forcedac_setup);
86 /* Number of entries per flush queue */
87 #define IOVA_FQ_SIZE 256
89 /* Timeout (in ms) after which entries are flushed from the queue */
90 #define IOVA_FQ_TIMEOUT 10
92 /* Flush queue entry for deferred flushing */
93 struct iova_fq_entry {
94 unsigned long iova_pfn;
96 struct list_head freelist;
97 u64 counter; /* Flush counter when this entry was added */
100 /* Per-CPU flush queue structure */
102 struct iova_fq_entry entries[IOVA_FQ_SIZE];
103 unsigned int head, tail;
107 #define fq_ring_for_each(i, fq) \
108 for ((i) = (fq)->head; (i) != (fq)->tail; (i) = ((i) + 1) % IOVA_FQ_SIZE)
110 static inline bool fq_full(struct iova_fq *fq)
112 assert_spin_locked(&fq->lock);
113 return (((fq->tail + 1) % IOVA_FQ_SIZE) == fq->head);
116 static inline unsigned int fq_ring_add(struct iova_fq *fq)
118 unsigned int idx = fq->tail;
120 assert_spin_locked(&fq->lock);
122 fq->tail = (idx + 1) % IOVA_FQ_SIZE;
127 static void fq_ring_free(struct iommu_dma_cookie *cookie, struct iova_fq *fq)
129 u64 counter = atomic64_read(&cookie->fq_flush_finish_cnt);
132 assert_spin_locked(&fq->lock);
134 fq_ring_for_each(idx, fq) {
136 if (fq->entries[idx].counter >= counter)
139 put_pages_list(&fq->entries[idx].freelist);
140 free_iova_fast(&cookie->iovad,
141 fq->entries[idx].iova_pfn,
142 fq->entries[idx].pages);
144 fq->head = (fq->head + 1) % IOVA_FQ_SIZE;
148 static void fq_flush_iotlb(struct iommu_dma_cookie *cookie)
150 atomic64_inc(&cookie->fq_flush_start_cnt);
151 cookie->fq_domain->ops->flush_iotlb_all(cookie->fq_domain);
152 atomic64_inc(&cookie->fq_flush_finish_cnt);
155 static void fq_flush_timeout(struct timer_list *t)
157 struct iommu_dma_cookie *cookie = from_timer(cookie, t, fq_timer);
160 atomic_set(&cookie->fq_timer_on, 0);
161 fq_flush_iotlb(cookie);
163 for_each_possible_cpu(cpu) {
167 fq = per_cpu_ptr(cookie->fq, cpu);
168 spin_lock_irqsave(&fq->lock, flags);
169 fq_ring_free(cookie, fq);
170 spin_unlock_irqrestore(&fq->lock, flags);
174 static void queue_iova(struct iommu_dma_cookie *cookie,
175 unsigned long pfn, unsigned long pages,
176 struct list_head *freelist)
183 * Order against the IOMMU driver's pagetable update from unmapping
184 * @pte, to guarantee that fq_flush_iotlb() observes that if called
185 * from a different CPU before we release the lock below. Full barrier
186 * so it also pairs with iommu_dma_init_fq() to avoid seeing partially
187 * written fq state here.
191 fq = raw_cpu_ptr(cookie->fq);
192 spin_lock_irqsave(&fq->lock, flags);
195 * First remove all entries from the flush queue that have already been
196 * flushed out on another CPU. This makes the fq_full() check below less
199 fq_ring_free(cookie, fq);
202 fq_flush_iotlb(cookie);
203 fq_ring_free(cookie, fq);
206 idx = fq_ring_add(fq);
208 fq->entries[idx].iova_pfn = pfn;
209 fq->entries[idx].pages = pages;
210 fq->entries[idx].counter = atomic64_read(&cookie->fq_flush_start_cnt);
211 list_splice(freelist, &fq->entries[idx].freelist);
213 spin_unlock_irqrestore(&fq->lock, flags);
215 /* Avoid false sharing as much as possible. */
216 if (!atomic_read(&cookie->fq_timer_on) &&
217 !atomic_xchg(&cookie->fq_timer_on, 1))
218 mod_timer(&cookie->fq_timer,
219 jiffies + msecs_to_jiffies(IOVA_FQ_TIMEOUT));
222 static void iommu_dma_free_fq(struct iommu_dma_cookie *cookie)
229 del_timer_sync(&cookie->fq_timer);
230 /* The IOVAs will be torn down separately, so just free our queued pages */
231 for_each_possible_cpu(cpu) {
232 struct iova_fq *fq = per_cpu_ptr(cookie->fq, cpu);
234 fq_ring_for_each(idx, fq)
235 put_pages_list(&fq->entries[idx].freelist);
238 free_percpu(cookie->fq);
241 /* sysfs updates are serialised by the mutex of the group owning @domain */
242 int iommu_dma_init_fq(struct iommu_domain *domain)
244 struct iommu_dma_cookie *cookie = domain->iova_cookie;
245 struct iova_fq __percpu *queue;
248 if (cookie->fq_domain)
251 atomic64_set(&cookie->fq_flush_start_cnt, 0);
252 atomic64_set(&cookie->fq_flush_finish_cnt, 0);
254 queue = alloc_percpu(struct iova_fq);
256 pr_warn("iova flush queue initialization failed\n");
260 for_each_possible_cpu(cpu) {
261 struct iova_fq *fq = per_cpu_ptr(queue, cpu);
266 spin_lock_init(&fq->lock);
268 for (i = 0; i < IOVA_FQ_SIZE; i++)
269 INIT_LIST_HEAD(&fq->entries[i].freelist);
274 timer_setup(&cookie->fq_timer, fq_flush_timeout, 0);
275 atomic_set(&cookie->fq_timer_on, 0);
277 * Prevent incomplete fq state being observable. Pairs with path from
278 * __iommu_dma_unmap() through iommu_dma_free_iova() to queue_iova()
281 WRITE_ONCE(cookie->fq_domain, domain);
285 static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
287 if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
288 return cookie->iovad.granule;
292 static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
294 struct iommu_dma_cookie *cookie;
296 cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
298 INIT_LIST_HEAD(&cookie->msi_page_list);
305 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
306 * @domain: IOMMU domain to prepare for DMA-API usage
308 int iommu_get_dma_cookie(struct iommu_domain *domain)
310 if (domain->iova_cookie)
313 domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
314 if (!domain->iova_cookie)
317 mutex_init(&domain->iova_cookie->mutex);
322 * iommu_get_msi_cookie - Acquire just MSI remapping resources
323 * @domain: IOMMU domain to prepare
324 * @base: Start address of IOVA region for MSI mappings
326 * Users who manage their own IOVA allocation and do not want DMA API support,
327 * but would still like to take advantage of automatic MSI remapping, can use
328 * this to initialise their own domain appropriately. Users should reserve a
329 * contiguous IOVA region, starting at @base, large enough to accommodate the
330 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
331 * used by the devices attached to @domain.
333 int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
335 struct iommu_dma_cookie *cookie;
337 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
340 if (domain->iova_cookie)
343 cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
347 cookie->msi_iova = base;
348 domain->iova_cookie = cookie;
351 EXPORT_SYMBOL(iommu_get_msi_cookie);
354 * iommu_put_dma_cookie - Release a domain's DMA mapping resources
355 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
356 * iommu_get_msi_cookie()
358 void iommu_put_dma_cookie(struct iommu_domain *domain)
360 struct iommu_dma_cookie *cookie = domain->iova_cookie;
361 struct iommu_dma_msi_page *msi, *tmp;
366 if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule) {
367 iommu_dma_free_fq(cookie);
368 put_iova_domain(&cookie->iovad);
371 list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
372 list_del(&msi->list);
376 domain->iova_cookie = NULL;
380 * iommu_dma_get_resv_regions - Reserved region driver helper
381 * @dev: Device from iommu_get_resv_regions()
382 * @list: Reserved region list from iommu_get_resv_regions()
384 * IOMMU drivers can use this to implement their .get_resv_regions callback
385 * for general non-IOMMU-specific reservations. Currently, this covers GICv3
386 * ITS region reservation on ACPI based ARM platforms that may require HW MSI
389 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
392 if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode))
393 iort_iommu_get_resv_regions(dev, list);
396 of_iommu_get_resv_regions(dev, list);
398 EXPORT_SYMBOL(iommu_dma_get_resv_regions);
400 static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie,
401 phys_addr_t start, phys_addr_t end)
403 struct iova_domain *iovad = &cookie->iovad;
404 struct iommu_dma_msi_page *msi_page;
407 start -= iova_offset(iovad, start);
408 num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
410 for (i = 0; i < num_pages; i++) {
411 msi_page = kmalloc(sizeof(*msi_page), GFP_KERNEL);
415 msi_page->phys = start;
416 msi_page->iova = start;
417 INIT_LIST_HEAD(&msi_page->list);
418 list_add(&msi_page->list, &cookie->msi_page_list);
419 start += iovad->granule;
425 static int iommu_dma_ranges_sort(void *priv, const struct list_head *a,
426 const struct list_head *b)
428 struct resource_entry *res_a = list_entry(a, typeof(*res_a), node);
429 struct resource_entry *res_b = list_entry(b, typeof(*res_b), node);
431 return res_a->res->start > res_b->res->start;
434 static int iova_reserve_pci_windows(struct pci_dev *dev,
435 struct iova_domain *iovad)
437 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
438 struct resource_entry *window;
439 unsigned long lo, hi;
440 phys_addr_t start = 0, end;
442 resource_list_for_each_entry(window, &bridge->windows) {
443 if (resource_type(window->res) != IORESOURCE_MEM)
446 lo = iova_pfn(iovad, window->res->start - window->offset);
447 hi = iova_pfn(iovad, window->res->end - window->offset);
448 reserve_iova(iovad, lo, hi);
451 /* Get reserved DMA windows from host bridge */
452 list_sort(NULL, &bridge->dma_ranges, iommu_dma_ranges_sort);
453 resource_list_for_each_entry(window, &bridge->dma_ranges) {
454 end = window->res->start - window->offset;
457 lo = iova_pfn(iovad, start);
458 hi = iova_pfn(iovad, end);
459 reserve_iova(iovad, lo, hi);
460 } else if (end < start) {
461 /* DMA ranges should be non-overlapping */
463 "Failed to reserve IOVA [%pa-%pa]\n",
468 start = window->res->end - window->offset + 1;
469 /* If window is last entry */
470 if (window->node.next == &bridge->dma_ranges &&
471 end != ~(phys_addr_t)0) {
472 end = ~(phys_addr_t)0;
480 static int iova_reserve_iommu_regions(struct device *dev,
481 struct iommu_domain *domain)
483 struct iommu_dma_cookie *cookie = domain->iova_cookie;
484 struct iova_domain *iovad = &cookie->iovad;
485 struct iommu_resv_region *region;
486 LIST_HEAD(resv_regions);
489 if (dev_is_pci(dev)) {
490 ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad);
495 iommu_get_resv_regions(dev, &resv_regions);
496 list_for_each_entry(region, &resv_regions, list) {
497 unsigned long lo, hi;
499 /* We ARE the software that manages these! */
500 if (region->type == IOMMU_RESV_SW_MSI)
503 lo = iova_pfn(iovad, region->start);
504 hi = iova_pfn(iovad, region->start + region->length - 1);
505 reserve_iova(iovad, lo, hi);
507 if (region->type == IOMMU_RESV_MSI)
508 ret = cookie_init_hw_msi_region(cookie, region->start,
509 region->start + region->length);
513 iommu_put_resv_regions(dev, &resv_regions);
518 static bool dev_is_untrusted(struct device *dev)
520 return dev_is_pci(dev) && to_pci_dev(dev)->untrusted;
523 static bool dev_use_swiotlb(struct device *dev)
525 return IS_ENABLED(CONFIG_SWIOTLB) && dev_is_untrusted(dev);
529 * iommu_dma_init_domain - Initialise a DMA mapping domain
530 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
531 * @base: IOVA at which the mappable address space starts
532 * @limit: Last address of the IOVA space
533 * @dev: Device the domain is being initialised for
535 * @base and @limit + 1 should be exact multiples of IOMMU page granularity to
536 * avoid rounding surprises. If necessary, we reserve the page at address 0
537 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
538 * any change which could make prior IOVAs invalid will fail.
540 static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
541 dma_addr_t limit, struct device *dev)
543 struct iommu_dma_cookie *cookie = domain->iova_cookie;
544 unsigned long order, base_pfn;
545 struct iova_domain *iovad;
548 if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
551 iovad = &cookie->iovad;
553 /* Use the smallest supported page size for IOVA granularity */
554 order = __ffs(domain->pgsize_bitmap);
555 base_pfn = max_t(unsigned long, 1, base >> order);
557 /* Check the domain allows at least some access to the device... */
558 if (domain->geometry.force_aperture) {
559 if (base > domain->geometry.aperture_end ||
560 limit < domain->geometry.aperture_start) {
561 pr_warn("specified DMA range outside IOMMU capability\n");
564 /* ...then finally give it a kicking to make sure it fits */
565 base_pfn = max_t(unsigned long, base_pfn,
566 domain->geometry.aperture_start >> order);
569 /* start_pfn is always nonzero for an already-initialised domain */
570 mutex_lock(&cookie->mutex);
571 if (iovad->start_pfn) {
572 if (1UL << order != iovad->granule ||
573 base_pfn != iovad->start_pfn) {
574 pr_warn("Incompatible range for DMA domain\n");
583 init_iova_domain(iovad, 1UL << order, base_pfn);
584 ret = iova_domain_init_rcaches(iovad);
588 /* If the FQ fails we can simply fall back to strict mode */
589 if (domain->type == IOMMU_DOMAIN_DMA_FQ && iommu_dma_init_fq(domain))
590 domain->type = IOMMU_DOMAIN_DMA;
592 ret = iova_reserve_iommu_regions(dev, domain);
595 mutex_unlock(&cookie->mutex);
600 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
602 * @dir: Direction of DMA transfer
603 * @coherent: Is the DMA master cache-coherent?
604 * @attrs: DMA attributes for the mapping
606 * Return: corresponding IOMMU API page protection flags
608 static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
611 int prot = coherent ? IOMMU_CACHE : 0;
613 if (attrs & DMA_ATTR_PRIVILEGED)
617 case DMA_BIDIRECTIONAL:
618 return prot | IOMMU_READ | IOMMU_WRITE;
620 return prot | IOMMU_READ;
621 case DMA_FROM_DEVICE:
622 return prot | IOMMU_WRITE;
628 static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
629 size_t size, u64 dma_limit, struct device *dev)
631 struct iommu_dma_cookie *cookie = domain->iova_cookie;
632 struct iova_domain *iovad = &cookie->iovad;
633 unsigned long shift, iova_len, iova = 0;
635 if (cookie->type == IOMMU_DMA_MSI_COOKIE) {
636 cookie->msi_iova += size;
637 return cookie->msi_iova - size;
640 shift = iova_shift(iovad);
641 iova_len = size >> shift;
643 dma_limit = min_not_zero(dma_limit, dev->bus_dma_limit);
645 if (domain->geometry.force_aperture)
646 dma_limit = min(dma_limit, (u64)domain->geometry.aperture_end);
648 /* Try to get PCI devices a SAC address */
649 if (dma_limit > DMA_BIT_MASK(32) && !iommu_dma_forcedac && dev_is_pci(dev))
650 iova = alloc_iova_fast(iovad, iova_len,
651 DMA_BIT_MASK(32) >> shift, false);
654 iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift,
657 return (dma_addr_t)iova << shift;
660 static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie,
661 dma_addr_t iova, size_t size, struct iommu_iotlb_gather *gather)
663 struct iova_domain *iovad = &cookie->iovad;
665 /* The MSI case is only ever cleaning up its most recent allocation */
666 if (cookie->type == IOMMU_DMA_MSI_COOKIE)
667 cookie->msi_iova -= size;
668 else if (gather && gather->queued)
669 queue_iova(cookie, iova_pfn(iovad, iova),
670 size >> iova_shift(iovad),
673 free_iova_fast(iovad, iova_pfn(iovad, iova),
674 size >> iova_shift(iovad));
677 static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr,
680 struct iommu_domain *domain = iommu_get_dma_domain(dev);
681 struct iommu_dma_cookie *cookie = domain->iova_cookie;
682 struct iova_domain *iovad = &cookie->iovad;
683 size_t iova_off = iova_offset(iovad, dma_addr);
684 struct iommu_iotlb_gather iotlb_gather;
687 dma_addr -= iova_off;
688 size = iova_align(iovad, size + iova_off);
689 iommu_iotlb_gather_init(&iotlb_gather);
690 iotlb_gather.queued = READ_ONCE(cookie->fq_domain);
692 unmapped = iommu_unmap_fast(domain, dma_addr, size, &iotlb_gather);
693 WARN_ON(unmapped != size);
695 if (!iotlb_gather.queued)
696 iommu_iotlb_sync(domain, &iotlb_gather);
697 iommu_dma_free_iova(cookie, dma_addr, size, &iotlb_gather);
700 static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
701 size_t size, int prot, u64 dma_mask)
703 struct iommu_domain *domain = iommu_get_dma_domain(dev);
704 struct iommu_dma_cookie *cookie = domain->iova_cookie;
705 struct iova_domain *iovad = &cookie->iovad;
706 size_t iova_off = iova_offset(iovad, phys);
709 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
710 iommu_deferred_attach(dev, domain))
711 return DMA_MAPPING_ERROR;
713 size = iova_align(iovad, size + iova_off);
715 iova = iommu_dma_alloc_iova(domain, size, dma_mask, dev);
717 return DMA_MAPPING_ERROR;
719 if (iommu_map(domain, iova, phys - iova_off, size, prot, GFP_ATOMIC)) {
720 iommu_dma_free_iova(cookie, iova, size, NULL);
721 return DMA_MAPPING_ERROR;
723 return iova + iova_off;
726 static void __iommu_dma_free_pages(struct page **pages, int count)
729 __free_page(pages[count]);
733 static struct page **__iommu_dma_alloc_pages(struct device *dev,
734 unsigned int count, unsigned long order_mask, gfp_t gfp)
737 unsigned int i = 0, nid = dev_to_node(dev);
739 order_mask &= (2U << MAX_ORDER) - 1;
743 pages = kvcalloc(count, sizeof(*pages), GFP_KERNEL);
747 /* IOMMU can map any pages, so himem can also be used here */
748 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
751 struct page *page = NULL;
752 unsigned int order_size;
755 * Higher-order allocations are a convenience rather
756 * than a necessity, hence using __GFP_NORETRY until
757 * falling back to minimum-order allocations.
759 for (order_mask &= (2U << __fls(count)) - 1;
760 order_mask; order_mask &= ~order_size) {
761 unsigned int order = __fls(order_mask);
762 gfp_t alloc_flags = gfp;
764 order_size = 1U << order;
765 if (order_mask > order_size)
766 alloc_flags |= __GFP_NORETRY;
767 page = alloc_pages_node(nid, alloc_flags, order);
771 split_page(page, order);
775 __iommu_dma_free_pages(pages, i);
786 * If size is less than PAGE_SIZE, then a full CPU page will be allocated,
787 * but an IOMMU which supports smaller pages might not map the whole thing.
789 static struct page **__iommu_dma_alloc_noncontiguous(struct device *dev,
790 size_t size, struct sg_table *sgt, gfp_t gfp, pgprot_t prot,
793 struct iommu_domain *domain = iommu_get_dma_domain(dev);
794 struct iommu_dma_cookie *cookie = domain->iova_cookie;
795 struct iova_domain *iovad = &cookie->iovad;
796 bool coherent = dev_is_dma_coherent(dev);
797 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
798 unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
803 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
804 iommu_deferred_attach(dev, domain))
807 min_size = alloc_sizes & -alloc_sizes;
808 if (min_size < PAGE_SIZE) {
809 min_size = PAGE_SIZE;
810 alloc_sizes |= PAGE_SIZE;
812 size = ALIGN(size, min_size);
814 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
815 alloc_sizes = min_size;
817 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
818 pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT,
823 size = iova_align(iovad, size);
824 iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev);
829 * Remove the zone/policy flags from the GFP - these are applied to the
830 * __iommu_dma_alloc_pages() but are not used for the supporting
831 * internal allocations that follow.
833 gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM | __GFP_COMP);
835 if (sg_alloc_table_from_pages(sgt, pages, count, 0, size, gfp))
838 if (!(ioprot & IOMMU_CACHE)) {
839 struct scatterlist *sg;
842 for_each_sg(sgt->sgl, sg, sgt->orig_nents, i)
843 arch_dma_prep_coherent(sg_page(sg), sg->length);
846 ret = iommu_map_sg(domain, iova, sgt->sgl, sgt->orig_nents, ioprot,
848 if (ret < 0 || ret < size)
851 sgt->sgl->dma_address = iova;
852 sgt->sgl->dma_length = size;
858 iommu_dma_free_iova(cookie, iova, size, NULL);
860 __iommu_dma_free_pages(pages, count);
864 static void *iommu_dma_alloc_remap(struct device *dev, size_t size,
865 dma_addr_t *dma_handle, gfp_t gfp, pgprot_t prot,
872 pages = __iommu_dma_alloc_noncontiguous(dev, size, &sgt, gfp, prot,
876 *dma_handle = sgt.sgl->dma_address;
878 vaddr = dma_common_pages_remap(pages, size, prot,
879 __builtin_return_address(0));
885 __iommu_dma_unmap(dev, *dma_handle, size);
886 __iommu_dma_free_pages(pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
890 static struct sg_table *iommu_dma_alloc_noncontiguous(struct device *dev,
891 size_t size, enum dma_data_direction dir, gfp_t gfp,
894 struct dma_sgt_handle *sh;
896 sh = kmalloc(sizeof(*sh), gfp);
900 sh->pages = __iommu_dma_alloc_noncontiguous(dev, size, &sh->sgt, gfp,
909 static void iommu_dma_free_noncontiguous(struct device *dev, size_t size,
910 struct sg_table *sgt, enum dma_data_direction dir)
912 struct dma_sgt_handle *sh = sgt_handle(sgt);
914 __iommu_dma_unmap(dev, sgt->sgl->dma_address, size);
915 __iommu_dma_free_pages(sh->pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
916 sg_free_table(&sh->sgt);
920 static void iommu_dma_sync_single_for_cpu(struct device *dev,
921 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
925 if (dev_is_dma_coherent(dev) && !dev_use_swiotlb(dev))
928 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
929 if (!dev_is_dma_coherent(dev))
930 arch_sync_dma_for_cpu(phys, size, dir);
932 if (is_swiotlb_buffer(dev, phys))
933 swiotlb_sync_single_for_cpu(dev, phys, size, dir);
936 static void iommu_dma_sync_single_for_device(struct device *dev,
937 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
941 if (dev_is_dma_coherent(dev) && !dev_use_swiotlb(dev))
944 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
945 if (is_swiotlb_buffer(dev, phys))
946 swiotlb_sync_single_for_device(dev, phys, size, dir);
948 if (!dev_is_dma_coherent(dev))
949 arch_sync_dma_for_device(phys, size, dir);
952 static void iommu_dma_sync_sg_for_cpu(struct device *dev,
953 struct scatterlist *sgl, int nelems,
954 enum dma_data_direction dir)
956 struct scatterlist *sg;
959 if (dev_use_swiotlb(dev))
960 for_each_sg(sgl, sg, nelems, i)
961 iommu_dma_sync_single_for_cpu(dev, sg_dma_address(sg),
963 else if (!dev_is_dma_coherent(dev))
964 for_each_sg(sgl, sg, nelems, i)
965 arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir);
968 static void iommu_dma_sync_sg_for_device(struct device *dev,
969 struct scatterlist *sgl, int nelems,
970 enum dma_data_direction dir)
972 struct scatterlist *sg;
975 if (dev_use_swiotlb(dev))
976 for_each_sg(sgl, sg, nelems, i)
977 iommu_dma_sync_single_for_device(dev,
980 else if (!dev_is_dma_coherent(dev))
981 for_each_sg(sgl, sg, nelems, i)
982 arch_sync_dma_for_device(sg_phys(sg), sg->length, dir);
985 static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
986 unsigned long offset, size_t size, enum dma_data_direction dir,
989 phys_addr_t phys = page_to_phys(page) + offset;
990 bool coherent = dev_is_dma_coherent(dev);
991 int prot = dma_info_to_prot(dir, coherent, attrs);
992 struct iommu_domain *domain = iommu_get_dma_domain(dev);
993 struct iommu_dma_cookie *cookie = domain->iova_cookie;
994 struct iova_domain *iovad = &cookie->iovad;
995 dma_addr_t iova, dma_mask = dma_get_mask(dev);
998 * If both the physical buffer start address and size are
999 * page aligned, we don't need to use a bounce page.
1001 if (dev_use_swiotlb(dev) && iova_offset(iovad, phys | size)) {
1002 void *padding_start;
1003 size_t padding_size, aligned_size;
1005 if (!is_swiotlb_active(dev)) {
1006 dev_warn_once(dev, "DMA bounce buffers are inactive, unable to map unaligned transaction.\n");
1007 return DMA_MAPPING_ERROR;
1010 aligned_size = iova_align(iovad, size);
1011 phys = swiotlb_tbl_map_single(dev, phys, size, aligned_size,
1012 iova_mask(iovad), dir, attrs);
1014 if (phys == DMA_MAPPING_ERROR)
1015 return DMA_MAPPING_ERROR;
1017 /* Cleanup the padding area. */
1018 padding_start = phys_to_virt(phys);
1019 padding_size = aligned_size;
1021 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
1022 (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) {
1023 padding_start += size;
1024 padding_size -= size;
1027 memset(padding_start, 0, padding_size);
1030 if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1031 arch_sync_dma_for_device(phys, size, dir);
1033 iova = __iommu_dma_map(dev, phys, size, prot, dma_mask);
1034 if (iova == DMA_MAPPING_ERROR && is_swiotlb_buffer(dev, phys))
1035 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
1039 static void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
1040 size_t size, enum dma_data_direction dir, unsigned long attrs)
1042 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1045 phys = iommu_iova_to_phys(domain, dma_handle);
1049 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && !dev_is_dma_coherent(dev))
1050 arch_sync_dma_for_cpu(phys, size, dir);
1052 __iommu_dma_unmap(dev, dma_handle, size);
1054 if (unlikely(is_swiotlb_buffer(dev, phys)))
1055 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
1059 * Prepare a successfully-mapped scatterlist to give back to the caller.
1061 * At this point the segments are already laid out by iommu_dma_map_sg() to
1062 * avoid individually crossing any boundaries, so we merely need to check a
1063 * segment's start address to avoid concatenating across one.
1065 static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents,
1066 dma_addr_t dma_addr)
1068 struct scatterlist *s, *cur = sg;
1069 unsigned long seg_mask = dma_get_seg_boundary(dev);
1070 unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
1073 for_each_sg(sg, s, nents, i) {
1074 /* Restore this segment's original unaligned fields first */
1075 dma_addr_t s_dma_addr = sg_dma_address(s);
1076 unsigned int s_iova_off = sg_dma_address(s);
1077 unsigned int s_length = sg_dma_len(s);
1078 unsigned int s_iova_len = s->length;
1080 sg_dma_address(s) = DMA_MAPPING_ERROR;
1083 if (sg_is_dma_bus_address(s)) {
1087 sg_dma_unmark_bus_address(s);
1088 sg_dma_address(cur) = s_dma_addr;
1089 sg_dma_len(cur) = s_length;
1090 sg_dma_mark_bus_address(cur);
1096 s->offset += s_iova_off;
1097 s->length = s_length;
1100 * Now fill in the real DMA data. If...
1101 * - there is a valid output segment to append to
1102 * - and this segment starts on an IOVA page boundary
1103 * - but doesn't fall at a segment boundary
1104 * - and wouldn't make the resulting output segment too long
1106 if (cur_len && !s_iova_off && (dma_addr & seg_mask) &&
1107 (max_len - cur_len >= s_length)) {
1108 /* ...then concatenate it with the previous one */
1109 cur_len += s_length;
1111 /* Otherwise start the next output segment */
1117 sg_dma_address(cur) = dma_addr + s_iova_off;
1120 sg_dma_len(cur) = cur_len;
1121 dma_addr += s_iova_len;
1123 if (s_length + s_iova_off < s_iova_len)
1130 * If mapping failed, then just restore the original list,
1131 * but making sure the DMA fields are invalidated.
1133 static void __invalidate_sg(struct scatterlist *sg, int nents)
1135 struct scatterlist *s;
1138 for_each_sg(sg, s, nents, i) {
1139 if (sg_is_dma_bus_address(s)) {
1140 sg_dma_unmark_bus_address(s);
1142 if (sg_dma_address(s) != DMA_MAPPING_ERROR)
1143 s->offset += sg_dma_address(s);
1145 s->length = sg_dma_len(s);
1147 sg_dma_address(s) = DMA_MAPPING_ERROR;
1152 static void iommu_dma_unmap_sg_swiotlb(struct device *dev, struct scatterlist *sg,
1153 int nents, enum dma_data_direction dir, unsigned long attrs)
1155 struct scatterlist *s;
1158 for_each_sg(sg, s, nents, i)
1159 iommu_dma_unmap_page(dev, sg_dma_address(s),
1160 sg_dma_len(s), dir, attrs);
1163 static int iommu_dma_map_sg_swiotlb(struct device *dev, struct scatterlist *sg,
1164 int nents, enum dma_data_direction dir, unsigned long attrs)
1166 struct scatterlist *s;
1169 for_each_sg(sg, s, nents, i) {
1170 sg_dma_address(s) = iommu_dma_map_page(dev, sg_page(s),
1171 s->offset, s->length, dir, attrs);
1172 if (sg_dma_address(s) == DMA_MAPPING_ERROR)
1174 sg_dma_len(s) = s->length;
1180 iommu_dma_unmap_sg_swiotlb(dev, sg, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
1185 * The DMA API client is passing in a scatterlist which could describe
1186 * any old buffer layout, but the IOMMU API requires everything to be
1187 * aligned to IOMMU pages. Hence the need for this complicated bit of
1188 * impedance-matching, to be able to hand off a suitably-aligned list,
1189 * but still preserve the original offsets and sizes for the caller.
1191 static int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg,
1192 int nents, enum dma_data_direction dir, unsigned long attrs)
1194 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1195 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1196 struct iova_domain *iovad = &cookie->iovad;
1197 struct scatterlist *s, *prev = NULL;
1198 int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs);
1199 struct pci_p2pdma_map_state p2pdma_state = {};
1200 enum pci_p2pdma_map_type map;
1202 size_t iova_len = 0;
1203 unsigned long mask = dma_get_seg_boundary(dev);
1207 if (static_branch_unlikely(&iommu_deferred_attach_enabled)) {
1208 ret = iommu_deferred_attach(dev, domain);
1213 if (dev_use_swiotlb(dev))
1214 return iommu_dma_map_sg_swiotlb(dev, sg, nents, dir, attrs);
1216 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1217 iommu_dma_sync_sg_for_device(dev, sg, nents, dir);
1220 * Work out how much IOVA space we need, and align the segments to
1221 * IOVA granules for the IOMMU driver to handle. With some clever
1222 * trickery we can modify the list in-place, but reversibly, by
1223 * stashing the unaligned parts in the as-yet-unused DMA fields.
1225 for_each_sg(sg, s, nents, i) {
1226 size_t s_iova_off = iova_offset(iovad, s->offset);
1227 size_t s_length = s->length;
1228 size_t pad_len = (mask - iova_len + 1) & mask;
1230 if (is_pci_p2pdma_page(sg_page(s))) {
1231 map = pci_p2pdma_map_segment(&p2pdma_state, dev, s);
1233 case PCI_P2PDMA_MAP_BUS_ADDR:
1235 * iommu_map_sg() will skip this segment as
1236 * it is marked as a bus address,
1237 * __finalise_sg() will copy the dma address
1238 * into the output segment.
1241 case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
1243 * Mapping through host bridge should be
1244 * mapped with regular IOVAs, thus we
1245 * do nothing here and continue below.
1250 goto out_restore_sg;
1254 sg_dma_address(s) = s_iova_off;
1255 sg_dma_len(s) = s_length;
1256 s->offset -= s_iova_off;
1257 s_length = iova_align(iovad, s_length + s_iova_off);
1258 s->length = s_length;
1261 * Due to the alignment of our single IOVA allocation, we can
1262 * depend on these assumptions about the segment boundary mask:
1263 * - If mask size >= IOVA size, then the IOVA range cannot
1264 * possibly fall across a boundary, so we don't care.
1265 * - If mask size < IOVA size, then the IOVA range must start
1266 * exactly on a boundary, therefore we can lay things out
1267 * based purely on segment lengths without needing to know
1268 * the actual addresses beforehand.
1269 * - The mask must be a power of 2, so pad_len == 0 if
1270 * iova_len == 0, thus we cannot dereference prev the first
1271 * time through here (i.e. before it has a meaningful value).
1273 if (pad_len && pad_len < s_length - 1) {
1274 prev->length += pad_len;
1275 iova_len += pad_len;
1278 iova_len += s_length;
1283 return __finalise_sg(dev, sg, nents, 0);
1285 iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev);
1288 goto out_restore_sg;
1292 * We'll leave any physical concatenation to the IOMMU driver's
1293 * implementation - it knows better than we do.
1295 ret = iommu_map_sg(domain, iova, sg, nents, prot, GFP_ATOMIC);
1296 if (ret < 0 || ret < iova_len)
1299 return __finalise_sg(dev, sg, nents, iova);
1302 iommu_dma_free_iova(cookie, iova, iova_len, NULL);
1304 __invalidate_sg(sg, nents);
1306 if (ret != -ENOMEM && ret != -EREMOTEIO)
1311 static void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
1312 int nents, enum dma_data_direction dir, unsigned long attrs)
1314 dma_addr_t end = 0, start;
1315 struct scatterlist *tmp;
1318 if (dev_use_swiotlb(dev)) {
1319 iommu_dma_unmap_sg_swiotlb(dev, sg, nents, dir, attrs);
1323 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1324 iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir);
1327 * The scatterlist segments are mapped into a single
1328 * contiguous IOVA allocation, the start and end points
1329 * just have to be determined.
1331 for_each_sg(sg, tmp, nents, i) {
1332 if (sg_is_dma_bus_address(tmp)) {
1333 sg_dma_unmark_bus_address(tmp);
1337 if (sg_dma_len(tmp) == 0)
1340 start = sg_dma_address(tmp);
1345 for_each_sg(tmp, tmp, nents, i) {
1346 if (sg_is_dma_bus_address(tmp)) {
1347 sg_dma_unmark_bus_address(tmp);
1351 if (sg_dma_len(tmp) == 0)
1354 end = sg_dma_address(tmp) + sg_dma_len(tmp);
1358 __iommu_dma_unmap(dev, start, end - start);
1361 static dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
1362 size_t size, enum dma_data_direction dir, unsigned long attrs)
1364 return __iommu_dma_map(dev, phys, size,
1365 dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
1369 static void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
1370 size_t size, enum dma_data_direction dir, unsigned long attrs)
1372 __iommu_dma_unmap(dev, handle, size);
1375 static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
1377 size_t alloc_size = PAGE_ALIGN(size);
1378 int count = alloc_size >> PAGE_SHIFT;
1379 struct page *page = NULL, **pages = NULL;
1381 /* Non-coherent atomic allocation? Easy */
1382 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1383 dma_free_from_pool(dev, cpu_addr, alloc_size))
1386 if (is_vmalloc_addr(cpu_addr)) {
1388 * If it the address is remapped, then it's either non-coherent
1389 * or highmem CMA, or an iommu_dma_alloc_remap() construction.
1391 pages = dma_common_find_pages(cpu_addr);
1393 page = vmalloc_to_page(cpu_addr);
1394 dma_common_free_remap(cpu_addr, alloc_size);
1396 /* Lowmem means a coherent atomic or CMA allocation */
1397 page = virt_to_page(cpu_addr);
1401 __iommu_dma_free_pages(pages, count);
1403 dma_free_contiguous(dev, page, alloc_size);
1406 static void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
1407 dma_addr_t handle, unsigned long attrs)
1409 __iommu_dma_unmap(dev, handle, size);
1410 __iommu_dma_free(dev, size, cpu_addr);
1413 static void *iommu_dma_alloc_pages(struct device *dev, size_t size,
1414 struct page **pagep, gfp_t gfp, unsigned long attrs)
1416 bool coherent = dev_is_dma_coherent(dev);
1417 size_t alloc_size = PAGE_ALIGN(size);
1418 int node = dev_to_node(dev);
1419 struct page *page = NULL;
1422 page = dma_alloc_contiguous(dev, alloc_size, gfp);
1424 page = alloc_pages_node(node, gfp, get_order(alloc_size));
1428 if (!coherent || PageHighMem(page)) {
1429 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
1431 cpu_addr = dma_common_contiguous_remap(page, alloc_size,
1432 prot, __builtin_return_address(0));
1434 goto out_free_pages;
1437 arch_dma_prep_coherent(page, size);
1439 cpu_addr = page_address(page);
1443 memset(cpu_addr, 0, alloc_size);
1446 dma_free_contiguous(dev, page, alloc_size);
1450 static void *iommu_dma_alloc(struct device *dev, size_t size,
1451 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1453 bool coherent = dev_is_dma_coherent(dev);
1454 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
1455 struct page *page = NULL;
1460 if (gfpflags_allow_blocking(gfp) &&
1461 !(attrs & DMA_ATTR_FORCE_CONTIGUOUS)) {
1462 return iommu_dma_alloc_remap(dev, size, handle, gfp,
1463 dma_pgprot(dev, PAGE_KERNEL, attrs), attrs);
1466 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1467 !gfpflags_allow_blocking(gfp) && !coherent)
1468 page = dma_alloc_from_pool(dev, PAGE_ALIGN(size), &cpu_addr,
1471 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs);
1475 *handle = __iommu_dma_map(dev, page_to_phys(page), size, ioprot,
1476 dev->coherent_dma_mask);
1477 if (*handle == DMA_MAPPING_ERROR) {
1478 __iommu_dma_free(dev, size, cpu_addr);
1485 static int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
1486 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1487 unsigned long attrs)
1489 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1490 unsigned long pfn, off = vma->vm_pgoff;
1493 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
1495 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
1498 if (off >= nr_pages || vma_pages(vma) > nr_pages - off)
1501 if (is_vmalloc_addr(cpu_addr)) {
1502 struct page **pages = dma_common_find_pages(cpu_addr);
1505 return vm_map_pages(vma, pages, nr_pages);
1506 pfn = vmalloc_to_pfn(cpu_addr);
1508 pfn = page_to_pfn(virt_to_page(cpu_addr));
1511 return remap_pfn_range(vma, vma->vm_start, pfn + off,
1512 vma->vm_end - vma->vm_start,
1516 static int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
1517 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1518 unsigned long attrs)
1523 if (is_vmalloc_addr(cpu_addr)) {
1524 struct page **pages = dma_common_find_pages(cpu_addr);
1527 return sg_alloc_table_from_pages(sgt, pages,
1528 PAGE_ALIGN(size) >> PAGE_SHIFT,
1529 0, size, GFP_KERNEL);
1532 page = vmalloc_to_page(cpu_addr);
1534 page = virt_to_page(cpu_addr);
1537 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
1539 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
1543 static unsigned long iommu_dma_get_merge_boundary(struct device *dev)
1545 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1547 return (1UL << __ffs(domain->pgsize_bitmap)) - 1;
1550 static size_t iommu_dma_opt_mapping_size(void)
1552 return iova_rcache_range();
1555 static const struct dma_map_ops iommu_dma_ops = {
1556 .flags = DMA_F_PCI_P2PDMA_SUPPORTED,
1557 .alloc = iommu_dma_alloc,
1558 .free = iommu_dma_free,
1559 .alloc_pages = dma_common_alloc_pages,
1560 .free_pages = dma_common_free_pages,
1561 .alloc_noncontiguous = iommu_dma_alloc_noncontiguous,
1562 .free_noncontiguous = iommu_dma_free_noncontiguous,
1563 .mmap = iommu_dma_mmap,
1564 .get_sgtable = iommu_dma_get_sgtable,
1565 .map_page = iommu_dma_map_page,
1566 .unmap_page = iommu_dma_unmap_page,
1567 .map_sg = iommu_dma_map_sg,
1568 .unmap_sg = iommu_dma_unmap_sg,
1569 .sync_single_for_cpu = iommu_dma_sync_single_for_cpu,
1570 .sync_single_for_device = iommu_dma_sync_single_for_device,
1571 .sync_sg_for_cpu = iommu_dma_sync_sg_for_cpu,
1572 .sync_sg_for_device = iommu_dma_sync_sg_for_device,
1573 .map_resource = iommu_dma_map_resource,
1574 .unmap_resource = iommu_dma_unmap_resource,
1575 .get_merge_boundary = iommu_dma_get_merge_boundary,
1576 .opt_mapping_size = iommu_dma_opt_mapping_size,
1580 * The IOMMU core code allocates the default DMA domain, which the underlying
1581 * IOMMU driver needs to support via the dma-iommu layer.
1583 void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit)
1585 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1591 * The IOMMU core code allocates the default DMA domain, which the
1592 * underlying IOMMU driver needs to support via the dma-iommu layer.
1594 if (iommu_is_dma_domain(domain)) {
1595 if (iommu_dma_init_domain(domain, dma_base, dma_limit, dev))
1597 dev->dma_ops = &iommu_dma_ops;
1602 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
1605 EXPORT_SYMBOL_GPL(iommu_setup_dma_ops);
1607 static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
1608 phys_addr_t msi_addr, struct iommu_domain *domain)
1610 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1611 struct iommu_dma_msi_page *msi_page;
1613 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
1614 size_t size = cookie_msi_granule(cookie);
1616 msi_addr &= ~(phys_addr_t)(size - 1);
1617 list_for_each_entry(msi_page, &cookie->msi_page_list, list)
1618 if (msi_page->phys == msi_addr)
1621 msi_page = kzalloc(sizeof(*msi_page), GFP_KERNEL);
1625 iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
1629 if (iommu_map(domain, iova, msi_addr, size, prot, GFP_KERNEL))
1632 INIT_LIST_HEAD(&msi_page->list);
1633 msi_page->phys = msi_addr;
1634 msi_page->iova = iova;
1635 list_add(&msi_page->list, &cookie->msi_page_list);
1639 iommu_dma_free_iova(cookie, iova, size, NULL);
1646 * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU domain
1647 * @desc: MSI descriptor, will store the MSI page
1648 * @msi_addr: MSI target address to be mapped
1650 * Return: 0 on success or negative error code if the mapping failed.
1652 int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
1654 struct device *dev = msi_desc_to_dev(desc);
1655 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1656 struct iommu_dma_msi_page *msi_page;
1657 static DEFINE_MUTEX(msi_prepare_lock); /* see below */
1659 if (!domain || !domain->iova_cookie) {
1660 desc->iommu_cookie = NULL;
1665 * In fact the whole prepare operation should already be serialised by
1666 * irq_domain_mutex further up the callchain, but that's pretty subtle
1667 * on its own, so consider this locking as failsafe documentation...
1669 mutex_lock(&msi_prepare_lock);
1670 msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
1671 mutex_unlock(&msi_prepare_lock);
1673 msi_desc_set_iommu_cookie(desc, msi_page);
1681 * iommu_dma_compose_msi_msg() - Apply translation to an MSI message
1682 * @desc: MSI descriptor prepared by iommu_dma_prepare_msi()
1683 * @msg: MSI message containing target physical address
1685 void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1687 struct device *dev = msi_desc_to_dev(desc);
1688 const struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1689 const struct iommu_dma_msi_page *msi_page;
1691 msi_page = msi_desc_get_iommu_cookie(desc);
1693 if (!domain || !domain->iova_cookie || WARN_ON(!msi_page))
1696 msg->address_hi = upper_32_bits(msi_page->iova);
1697 msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1;
1698 msg->address_lo += lower_32_bits(msi_page->iova);
1701 static int iommu_dma_init(void)
1703 if (is_kdump_kernel())
1704 static_branch_enable(&iommu_deferred_attach_enabled);
1706 return iova_cache_get();
1708 arch_initcall(iommu_dma_init);