2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <asm/msidef.h>
35 #include <asm/proto.h>
36 #include <asm/iommu.h>
40 #include "amd_iommu_proto.h"
41 #include "amd_iommu_types.h"
43 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
45 #define LOOP_TIMEOUT 100000
48 * This bitmap is used to advertise the page sizes our hardware support
49 * to the IOMMU core, which will then use this information to split
50 * physically contiguous memory regions it is mapping into page sizes
53 * Traditionally the IOMMU core just handed us the mappings directly,
54 * after making sure the size is an order of a 4KiB page and that the
55 * mapping has natural alignment.
57 * To retain this behavior, we currently advertise that we support
58 * all page sizes that are an order of 4KiB.
60 * If at some point we'd like to utilize the IOMMU core's new behavior,
61 * we could change this to advertise the real page sizes we support.
63 #define AMD_IOMMU_PGSIZES (~0xFFFUL)
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
76 * Domain for untranslated devices - only allocated
77 * if iommu=pt passed on kernel cmd line.
79 static struct protection_domain *pt_domain;
81 static struct iommu_ops amd_iommu_ops;
83 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
84 int amd_iommu_max_glx_val = -1;
87 * general struct to manage commands send to an IOMMU
93 static void update_domain(struct protection_domain *domain);
94 static int __init alloc_passthrough_domain(void);
96 /****************************************************************************
100 ****************************************************************************/
102 static struct iommu_dev_data *alloc_dev_data(u16 devid)
104 struct iommu_dev_data *dev_data;
107 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
111 dev_data->devid = devid;
112 atomic_set(&dev_data->bind, 0);
114 spin_lock_irqsave(&dev_data_list_lock, flags);
115 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
116 spin_unlock_irqrestore(&dev_data_list_lock, flags);
121 static void free_dev_data(struct iommu_dev_data *dev_data)
125 spin_lock_irqsave(&dev_data_list_lock, flags);
126 list_del(&dev_data->dev_data_list);
127 spin_unlock_irqrestore(&dev_data_list_lock, flags);
132 static struct iommu_dev_data *search_dev_data(u16 devid)
134 struct iommu_dev_data *dev_data;
137 spin_lock_irqsave(&dev_data_list_lock, flags);
138 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
139 if (dev_data->devid == devid)
146 spin_unlock_irqrestore(&dev_data_list_lock, flags);
151 static struct iommu_dev_data *find_dev_data(u16 devid)
153 struct iommu_dev_data *dev_data;
155 dev_data = search_dev_data(devid);
157 if (dev_data == NULL)
158 dev_data = alloc_dev_data(devid);
163 static inline u16 get_device_id(struct device *dev)
165 struct pci_dev *pdev = to_pci_dev(dev);
167 return calc_devid(pdev->bus->number, pdev->devfn);
170 static struct iommu_dev_data *get_dev_data(struct device *dev)
172 return dev->archdata.iommu;
175 static bool pci_iommuv2_capable(struct pci_dev *pdev)
177 static const int caps[] = {
180 PCI_EXT_CAP_ID_PASID,
184 for (i = 0; i < 3; ++i) {
185 pos = pci_find_ext_capability(pdev, caps[i]);
193 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
195 struct iommu_dev_data *dev_data;
197 dev_data = get_dev_data(&pdev->dev);
199 return dev_data->errata & (1 << erratum) ? true : false;
203 * In this function the list of preallocated protection domains is traversed to
204 * find the domain for a specific device
206 static struct dma_ops_domain *find_protection_domain(u16 devid)
208 struct dma_ops_domain *entry, *ret = NULL;
210 u16 alias = amd_iommu_alias_table[devid];
212 if (list_empty(&iommu_pd_list))
215 spin_lock_irqsave(&iommu_pd_list_lock, flags);
217 list_for_each_entry(entry, &iommu_pd_list, list) {
218 if (entry->target_dev == devid ||
219 entry->target_dev == alias) {
225 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
231 * This function checks if the driver got a valid device from the caller to
232 * avoid dereferencing invalid pointers.
234 static bool check_device(struct device *dev)
238 if (!dev || !dev->dma_mask)
241 /* No device or no PCI device */
242 if (dev->bus != &pci_bus_type)
245 devid = get_device_id(dev);
247 /* Out of our scope? */
248 if (devid > amd_iommu_last_bdf)
251 if (amd_iommu_rlookup_table[devid] == NULL)
257 static int iommu_init_device(struct device *dev)
259 struct pci_dev *pdev = to_pci_dev(dev);
260 struct iommu_dev_data *dev_data;
263 if (dev->archdata.iommu)
266 dev_data = find_dev_data(get_device_id(dev));
270 alias = amd_iommu_alias_table[dev_data->devid];
271 if (alias != dev_data->devid) {
272 struct iommu_dev_data *alias_data;
274 alias_data = find_dev_data(alias);
275 if (alias_data == NULL) {
276 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
278 free_dev_data(dev_data);
281 dev_data->alias_data = alias_data;
284 if (pci_iommuv2_capable(pdev)) {
285 struct amd_iommu *iommu;
287 iommu = amd_iommu_rlookup_table[dev_data->devid];
288 dev_data->iommu_v2 = iommu->is_iommu_v2;
291 dev->archdata.iommu = dev_data;
296 static void iommu_ignore_device(struct device *dev)
300 devid = get_device_id(dev);
301 alias = amd_iommu_alias_table[devid];
303 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
304 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
306 amd_iommu_rlookup_table[devid] = NULL;
307 amd_iommu_rlookup_table[alias] = NULL;
310 static void iommu_uninit_device(struct device *dev)
313 * Nothing to do here - we keep dev_data around for unplugged devices
314 * and reuse it when the device is re-plugged - not doing so would
315 * introduce a ton of races.
319 void __init amd_iommu_uninit_devices(void)
321 struct iommu_dev_data *dev_data, *n;
322 struct pci_dev *pdev = NULL;
324 for_each_pci_dev(pdev) {
326 if (!check_device(&pdev->dev))
329 iommu_uninit_device(&pdev->dev);
332 /* Free all of our dev_data structures */
333 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
334 free_dev_data(dev_data);
337 int __init amd_iommu_init_devices(void)
339 struct pci_dev *pdev = NULL;
342 for_each_pci_dev(pdev) {
344 if (!check_device(&pdev->dev))
347 ret = iommu_init_device(&pdev->dev);
348 if (ret == -ENOTSUPP)
349 iommu_ignore_device(&pdev->dev);
358 amd_iommu_uninit_devices();
362 #ifdef CONFIG_AMD_IOMMU_STATS
365 * Initialization code for statistics collection
368 DECLARE_STATS_COUNTER(compl_wait);
369 DECLARE_STATS_COUNTER(cnt_map_single);
370 DECLARE_STATS_COUNTER(cnt_unmap_single);
371 DECLARE_STATS_COUNTER(cnt_map_sg);
372 DECLARE_STATS_COUNTER(cnt_unmap_sg);
373 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
374 DECLARE_STATS_COUNTER(cnt_free_coherent);
375 DECLARE_STATS_COUNTER(cross_page);
376 DECLARE_STATS_COUNTER(domain_flush_single);
377 DECLARE_STATS_COUNTER(domain_flush_all);
378 DECLARE_STATS_COUNTER(alloced_io_mem);
379 DECLARE_STATS_COUNTER(total_map_requests);
380 DECLARE_STATS_COUNTER(complete_ppr);
381 DECLARE_STATS_COUNTER(invalidate_iotlb);
382 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
383 DECLARE_STATS_COUNTER(pri_requests);
386 static struct dentry *stats_dir;
387 static struct dentry *de_fflush;
389 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
391 if (stats_dir == NULL)
394 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
398 static void amd_iommu_stats_init(void)
400 stats_dir = debugfs_create_dir("amd-iommu", NULL);
401 if (stats_dir == NULL)
404 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
405 (u32 *)&amd_iommu_unmap_flush);
407 amd_iommu_stats_add(&compl_wait);
408 amd_iommu_stats_add(&cnt_map_single);
409 amd_iommu_stats_add(&cnt_unmap_single);
410 amd_iommu_stats_add(&cnt_map_sg);
411 amd_iommu_stats_add(&cnt_unmap_sg);
412 amd_iommu_stats_add(&cnt_alloc_coherent);
413 amd_iommu_stats_add(&cnt_free_coherent);
414 amd_iommu_stats_add(&cross_page);
415 amd_iommu_stats_add(&domain_flush_single);
416 amd_iommu_stats_add(&domain_flush_all);
417 amd_iommu_stats_add(&alloced_io_mem);
418 amd_iommu_stats_add(&total_map_requests);
419 amd_iommu_stats_add(&complete_ppr);
420 amd_iommu_stats_add(&invalidate_iotlb);
421 amd_iommu_stats_add(&invalidate_iotlb_all);
422 amd_iommu_stats_add(&pri_requests);
427 /****************************************************************************
429 * Interrupt handling functions
431 ****************************************************************************/
433 static void dump_dte_entry(u16 devid)
437 for (i = 0; i < 4; ++i)
438 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
439 amd_iommu_dev_table[devid].data[i]);
442 static void dump_command(unsigned long phys_addr)
444 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
447 for (i = 0; i < 4; ++i)
448 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
451 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
453 int type, devid, domid, flags;
454 volatile u32 *event = __evt;
459 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
460 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
461 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
462 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
463 address = (u64)(((u64)event[3]) << 32) | event[2];
466 /* Did we hit the erratum? */
467 if (++count == LOOP_TIMEOUT) {
468 pr_err("AMD-Vi: No event written to event log\n");
475 printk(KERN_ERR "AMD-Vi: Event logged [");
478 case EVENT_TYPE_ILL_DEV:
479 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
480 "address=0x%016llx flags=0x%04x]\n",
481 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
483 dump_dte_entry(devid);
485 case EVENT_TYPE_IO_FAULT:
486 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
487 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
488 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
489 domid, address, flags);
491 case EVENT_TYPE_DEV_TAB_ERR:
492 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
493 "address=0x%016llx flags=0x%04x]\n",
494 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
497 case EVENT_TYPE_PAGE_TAB_ERR:
498 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
499 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
500 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
501 domid, address, flags);
503 case EVENT_TYPE_ILL_CMD:
504 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
505 dump_command(address);
507 case EVENT_TYPE_CMD_HARD_ERR:
508 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
509 "flags=0x%04x]\n", address, flags);
511 case EVENT_TYPE_IOTLB_INV_TO:
512 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
513 "address=0x%016llx]\n",
514 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
517 case EVENT_TYPE_INV_DEV_REQ:
518 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
519 "address=0x%016llx flags=0x%04x]\n",
520 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
524 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
527 memset(__evt, 0, 4 * sizeof(u32));
530 static void iommu_poll_events(struct amd_iommu *iommu)
535 spin_lock_irqsave(&iommu->lock, flags);
537 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
538 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
540 while (head != tail) {
541 iommu_print_event(iommu, iommu->evt_buf + head);
542 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
545 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
547 spin_unlock_irqrestore(&iommu->lock, flags);
550 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
552 struct amd_iommu_fault fault;
554 INC_STATS_COUNTER(pri_requests);
556 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
557 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
561 fault.address = raw[1];
562 fault.pasid = PPR_PASID(raw[0]);
563 fault.device_id = PPR_DEVID(raw[0]);
564 fault.tag = PPR_TAG(raw[0]);
565 fault.flags = PPR_FLAGS(raw[0]);
567 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
570 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
575 if (iommu->ppr_log == NULL)
578 /* enable ppr interrupts again */
579 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
581 spin_lock_irqsave(&iommu->lock, flags);
583 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
584 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
586 while (head != tail) {
591 raw = (u64 *)(iommu->ppr_log + head);
594 * Hardware bug: Interrupt may arrive before the entry is
595 * written to memory. If this happens we need to wait for the
598 for (i = 0; i < LOOP_TIMEOUT; ++i) {
599 if (PPR_REQ_TYPE(raw[0]) != 0)
604 /* Avoid memcpy function-call overhead */
609 * To detect the hardware bug we need to clear the entry
612 raw[0] = raw[1] = 0UL;
614 /* Update head pointer of hardware ring-buffer */
615 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
616 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
619 * Release iommu->lock because ppr-handling might need to
622 spin_unlock_irqrestore(&iommu->lock, flags);
624 /* Handle PPR entry */
625 iommu_handle_ppr_entry(iommu, entry);
627 spin_lock_irqsave(&iommu->lock, flags);
629 /* Refresh ring-buffer information */
630 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
631 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
634 spin_unlock_irqrestore(&iommu->lock, flags);
637 irqreturn_t amd_iommu_int_thread(int irq, void *data)
639 struct amd_iommu *iommu;
641 for_each_iommu(iommu) {
642 iommu_poll_events(iommu);
643 iommu_poll_ppr_log(iommu);
649 irqreturn_t amd_iommu_int_handler(int irq, void *data)
651 return IRQ_WAKE_THREAD;
654 /****************************************************************************
656 * IOMMU command queuing functions
658 ****************************************************************************/
660 static int wait_on_sem(volatile u64 *sem)
664 while (*sem == 0 && i < LOOP_TIMEOUT) {
669 if (i == LOOP_TIMEOUT) {
670 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
677 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
678 struct iommu_cmd *cmd,
683 target = iommu->cmd_buf + tail;
684 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
686 /* Copy command to buffer */
687 memcpy(target, cmd, sizeof(*cmd));
689 /* Tell the IOMMU about it */
690 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
693 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
695 WARN_ON(address & 0x7ULL);
697 memset(cmd, 0, sizeof(*cmd));
698 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
699 cmd->data[1] = upper_32_bits(__pa(address));
701 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
704 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
706 memset(cmd, 0, sizeof(*cmd));
707 cmd->data[0] = devid;
708 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
711 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
712 size_t size, u16 domid, int pde)
717 pages = iommu_num_pages(address, size, PAGE_SIZE);
722 * If we have to flush more than one page, flush all
723 * TLB entries for this domain
725 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
729 address &= PAGE_MASK;
731 memset(cmd, 0, sizeof(*cmd));
732 cmd->data[1] |= domid;
733 cmd->data[2] = lower_32_bits(address);
734 cmd->data[3] = upper_32_bits(address);
735 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
736 if (s) /* size bit - we flush more than one 4kb page */
737 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
738 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
739 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
742 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
743 u64 address, size_t size)
748 pages = iommu_num_pages(address, size, PAGE_SIZE);
753 * If we have to flush more than one page, flush all
754 * TLB entries for this domain
756 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
760 address &= PAGE_MASK;
762 memset(cmd, 0, sizeof(*cmd));
763 cmd->data[0] = devid;
764 cmd->data[0] |= (qdep & 0xff) << 24;
765 cmd->data[1] = devid;
766 cmd->data[2] = lower_32_bits(address);
767 cmd->data[3] = upper_32_bits(address);
768 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
770 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
773 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
774 u64 address, bool size)
776 memset(cmd, 0, sizeof(*cmd));
778 address &= ~(0xfffULL);
780 cmd->data[0] = pasid & PASID_MASK;
781 cmd->data[1] = domid;
782 cmd->data[2] = lower_32_bits(address);
783 cmd->data[3] = upper_32_bits(address);
784 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
785 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
787 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
788 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
791 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
792 int qdep, u64 address, bool size)
794 memset(cmd, 0, sizeof(*cmd));
796 address &= ~(0xfffULL);
798 cmd->data[0] = devid;
799 cmd->data[0] |= (pasid & 0xff) << 16;
800 cmd->data[0] |= (qdep & 0xff) << 24;
801 cmd->data[1] = devid;
802 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
803 cmd->data[2] = lower_32_bits(address);
804 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
805 cmd->data[3] = upper_32_bits(address);
807 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
808 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
811 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
812 int status, int tag, bool gn)
814 memset(cmd, 0, sizeof(*cmd));
816 cmd->data[0] = devid;
818 cmd->data[1] = pasid & PASID_MASK;
819 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
821 cmd->data[3] = tag & 0x1ff;
822 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
824 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
827 static void build_inv_all(struct iommu_cmd *cmd)
829 memset(cmd, 0, sizeof(*cmd));
830 CMD_SET_TYPE(cmd, CMD_INV_ALL);
834 * Writes the command to the IOMMUs command buffer and informs the
835 * hardware about the new command.
837 static int iommu_queue_command_sync(struct amd_iommu *iommu,
838 struct iommu_cmd *cmd,
841 u32 left, tail, head, next_tail;
844 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
847 spin_lock_irqsave(&iommu->lock, flags);
849 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
850 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
851 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
852 left = (head - next_tail) % iommu->cmd_buf_size;
855 struct iommu_cmd sync_cmd;
856 volatile u64 sem = 0;
859 build_completion_wait(&sync_cmd, (u64)&sem);
860 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
862 spin_unlock_irqrestore(&iommu->lock, flags);
864 if ((ret = wait_on_sem(&sem)) != 0)
870 copy_cmd_to_buffer(iommu, cmd, tail);
872 /* We need to sync now to make sure all commands are processed */
873 iommu->need_sync = sync;
875 spin_unlock_irqrestore(&iommu->lock, flags);
880 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
882 return iommu_queue_command_sync(iommu, cmd, true);
886 * This function queues a completion wait command into the command
889 static int iommu_completion_wait(struct amd_iommu *iommu)
891 struct iommu_cmd cmd;
892 volatile u64 sem = 0;
895 if (!iommu->need_sync)
898 build_completion_wait(&cmd, (u64)&sem);
900 ret = iommu_queue_command_sync(iommu, &cmd, false);
904 return wait_on_sem(&sem);
907 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
909 struct iommu_cmd cmd;
911 build_inv_dte(&cmd, devid);
913 return iommu_queue_command(iommu, &cmd);
916 static void iommu_flush_dte_all(struct amd_iommu *iommu)
920 for (devid = 0; devid <= 0xffff; ++devid)
921 iommu_flush_dte(iommu, devid);
923 iommu_completion_wait(iommu);
927 * This function uses heavy locking and may disable irqs for some time. But
928 * this is no issue because it is only called during resume.
930 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
934 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
935 struct iommu_cmd cmd;
936 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
938 iommu_queue_command(iommu, &cmd);
941 iommu_completion_wait(iommu);
944 static void iommu_flush_all(struct amd_iommu *iommu)
946 struct iommu_cmd cmd;
950 iommu_queue_command(iommu, &cmd);
951 iommu_completion_wait(iommu);
954 void iommu_flush_all_caches(struct amd_iommu *iommu)
956 if (iommu_feature(iommu, FEATURE_IA)) {
957 iommu_flush_all(iommu);
959 iommu_flush_dte_all(iommu);
960 iommu_flush_tlb_all(iommu);
965 * Command send function for flushing on-device TLB
967 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
968 u64 address, size_t size)
970 struct amd_iommu *iommu;
971 struct iommu_cmd cmd;
974 qdep = dev_data->ats.qdep;
975 iommu = amd_iommu_rlookup_table[dev_data->devid];
977 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
979 return iommu_queue_command(iommu, &cmd);
983 * Command send function for invalidating a device table entry
985 static int device_flush_dte(struct iommu_dev_data *dev_data)
987 struct amd_iommu *iommu;
990 iommu = amd_iommu_rlookup_table[dev_data->devid];
992 ret = iommu_flush_dte(iommu, dev_data->devid);
996 if (dev_data->ats.enabled)
997 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1003 * TLB invalidation function which is called from the mapping functions.
1004 * It invalidates a single PTE if the range to flush is within a single
1005 * page. Otherwise it flushes the whole TLB of the IOMMU.
1007 static void __domain_flush_pages(struct protection_domain *domain,
1008 u64 address, size_t size, int pde)
1010 struct iommu_dev_data *dev_data;
1011 struct iommu_cmd cmd;
1014 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1016 for (i = 0; i < amd_iommus_present; ++i) {
1017 if (!domain->dev_iommu[i])
1021 * Devices of this domain are behind this IOMMU
1022 * We need a TLB flush
1024 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1027 list_for_each_entry(dev_data, &domain->dev_list, list) {
1029 if (!dev_data->ats.enabled)
1032 ret |= device_flush_iotlb(dev_data, address, size);
1038 static void domain_flush_pages(struct protection_domain *domain,
1039 u64 address, size_t size)
1041 __domain_flush_pages(domain, address, size, 0);
1044 /* Flush the whole IO/TLB for a given protection domain */
1045 static void domain_flush_tlb(struct protection_domain *domain)
1047 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1050 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1051 static void domain_flush_tlb_pde(struct protection_domain *domain)
1053 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1056 static void domain_flush_complete(struct protection_domain *domain)
1060 for (i = 0; i < amd_iommus_present; ++i) {
1061 if (!domain->dev_iommu[i])
1065 * Devices of this domain are behind this IOMMU
1066 * We need to wait for completion of all commands.
1068 iommu_completion_wait(amd_iommus[i]);
1074 * This function flushes the DTEs for all devices in domain
1076 static void domain_flush_devices(struct protection_domain *domain)
1078 struct iommu_dev_data *dev_data;
1080 list_for_each_entry(dev_data, &domain->dev_list, list)
1081 device_flush_dte(dev_data);
1084 /****************************************************************************
1086 * The functions below are used the create the page table mappings for
1087 * unity mapped regions.
1089 ****************************************************************************/
1092 * This function is used to add another level to an IO page table. Adding
1093 * another level increases the size of the address space by 9 bits to a size up
1096 static bool increase_address_space(struct protection_domain *domain,
1101 if (domain->mode == PAGE_MODE_6_LEVEL)
1102 /* address space already 64 bit large */
1105 pte = (void *)get_zeroed_page(gfp);
1109 *pte = PM_LEVEL_PDE(domain->mode,
1110 virt_to_phys(domain->pt_root));
1111 domain->pt_root = pte;
1113 domain->updated = true;
1118 static u64 *alloc_pte(struct protection_domain *domain,
1119 unsigned long address,
1120 unsigned long page_size,
1127 BUG_ON(!is_power_of_2(page_size));
1129 while (address > PM_LEVEL_SIZE(domain->mode))
1130 increase_address_space(domain, gfp);
1132 level = domain->mode - 1;
1133 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1134 address = PAGE_SIZE_ALIGN(address, page_size);
1135 end_lvl = PAGE_SIZE_LEVEL(page_size);
1137 while (level > end_lvl) {
1138 if (!IOMMU_PTE_PRESENT(*pte)) {
1139 page = (u64 *)get_zeroed_page(gfp);
1142 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1145 /* No level skipping support yet */
1146 if (PM_PTE_LEVEL(*pte) != level)
1151 pte = IOMMU_PTE_PAGE(*pte);
1153 if (pte_page && level == end_lvl)
1156 pte = &pte[PM_LEVEL_INDEX(level, address)];
1163 * This function checks if there is a PTE for a given dma address. If
1164 * there is one, it returns the pointer to it.
1166 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1171 if (address > PM_LEVEL_SIZE(domain->mode))
1174 level = domain->mode - 1;
1175 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1180 if (!IOMMU_PTE_PRESENT(*pte))
1184 if (PM_PTE_LEVEL(*pte) == 0x07) {
1185 unsigned long pte_mask, __pte;
1188 * If we have a series of large PTEs, make
1189 * sure to return a pointer to the first one.
1191 pte_mask = PTE_PAGE_SIZE(*pte);
1192 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1193 __pte = ((unsigned long)pte) & pte_mask;
1195 return (u64 *)__pte;
1198 /* No level skipping support yet */
1199 if (PM_PTE_LEVEL(*pte) != level)
1204 /* Walk to the next level */
1205 pte = IOMMU_PTE_PAGE(*pte);
1206 pte = &pte[PM_LEVEL_INDEX(level, address)];
1213 * Generic mapping functions. It maps a physical address into a DMA
1214 * address space. It allocates the page table pages if necessary.
1215 * In the future it can be extended to a generic mapping function
1216 * supporting all features of AMD IOMMU page tables like level skipping
1217 * and full 64 bit address spaces.
1219 static int iommu_map_page(struct protection_domain *dom,
1220 unsigned long bus_addr,
1221 unsigned long phys_addr,
1223 unsigned long page_size)
1228 if (!(prot & IOMMU_PROT_MASK))
1231 bus_addr = PAGE_ALIGN(bus_addr);
1232 phys_addr = PAGE_ALIGN(phys_addr);
1233 count = PAGE_SIZE_PTE_COUNT(page_size);
1234 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1236 for (i = 0; i < count; ++i)
1237 if (IOMMU_PTE_PRESENT(pte[i]))
1240 if (page_size > PAGE_SIZE) {
1241 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1242 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1244 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1246 if (prot & IOMMU_PROT_IR)
1247 __pte |= IOMMU_PTE_IR;
1248 if (prot & IOMMU_PROT_IW)
1249 __pte |= IOMMU_PTE_IW;
1251 for (i = 0; i < count; ++i)
1259 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1260 unsigned long bus_addr,
1261 unsigned long page_size)
1263 unsigned long long unmap_size, unmapped;
1266 BUG_ON(!is_power_of_2(page_size));
1270 while (unmapped < page_size) {
1272 pte = fetch_pte(dom, bus_addr);
1276 * No PTE for this address
1277 * move forward in 4kb steps
1279 unmap_size = PAGE_SIZE;
1280 } else if (PM_PTE_LEVEL(*pte) == 0) {
1281 /* 4kb PTE found for this address */
1282 unmap_size = PAGE_SIZE;
1287 /* Large PTE found which maps this address */
1288 unmap_size = PTE_PAGE_SIZE(*pte);
1289 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1290 for (i = 0; i < count; i++)
1294 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1295 unmapped += unmap_size;
1298 BUG_ON(!is_power_of_2(unmapped));
1304 * This function checks if a specific unity mapping entry is needed for
1305 * this specific IOMMU.
1307 static int iommu_for_unity_map(struct amd_iommu *iommu,
1308 struct unity_map_entry *entry)
1312 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1313 bdf = amd_iommu_alias_table[i];
1314 if (amd_iommu_rlookup_table[bdf] == iommu)
1322 * This function actually applies the mapping to the page table of the
1325 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1326 struct unity_map_entry *e)
1331 for (addr = e->address_start; addr < e->address_end;
1332 addr += PAGE_SIZE) {
1333 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1338 * if unity mapping is in aperture range mark the page
1339 * as allocated in the aperture
1341 if (addr < dma_dom->aperture_size)
1342 __set_bit(addr >> PAGE_SHIFT,
1343 dma_dom->aperture[0]->bitmap);
1350 * Init the unity mappings for a specific IOMMU in the system
1352 * Basically iterates over all unity mapping entries and applies them to
1353 * the default domain DMA of that IOMMU if necessary.
1355 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1357 struct unity_map_entry *entry;
1360 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1361 if (!iommu_for_unity_map(iommu, entry))
1363 ret = dma_ops_unity_map(iommu->default_dom, entry);
1372 * Inits the unity mappings required for a specific device
1374 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1377 struct unity_map_entry *e;
1380 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1381 if (!(devid >= e->devid_start && devid <= e->devid_end))
1383 ret = dma_ops_unity_map(dma_dom, e);
1391 /****************************************************************************
1393 * The next functions belong to the address allocator for the dma_ops
1394 * interface functions. They work like the allocators in the other IOMMU
1395 * drivers. Its basically a bitmap which marks the allocated pages in
1396 * the aperture. Maybe it could be enhanced in the future to a more
1397 * efficient allocator.
1399 ****************************************************************************/
1402 * The address allocator core functions.
1404 * called with domain->lock held
1408 * Used to reserve address ranges in the aperture (e.g. for exclusion
1411 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1412 unsigned long start_page,
1415 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1417 if (start_page + pages > last_page)
1418 pages = last_page - start_page;
1420 for (i = start_page; i < start_page + pages; ++i) {
1421 int index = i / APERTURE_RANGE_PAGES;
1422 int page = i % APERTURE_RANGE_PAGES;
1423 __set_bit(page, dom->aperture[index]->bitmap);
1428 * This function is used to add a new aperture range to an existing
1429 * aperture in case of dma_ops domain allocation or address allocation
1432 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1433 bool populate, gfp_t gfp)
1435 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1436 struct amd_iommu *iommu;
1437 unsigned long i, old_size;
1439 #ifdef CONFIG_IOMMU_STRESS
1443 if (index >= APERTURE_MAX_RANGES)
1446 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1447 if (!dma_dom->aperture[index])
1450 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1451 if (!dma_dom->aperture[index]->bitmap)
1454 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1457 unsigned long address = dma_dom->aperture_size;
1458 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1459 u64 *pte, *pte_page;
1461 for (i = 0; i < num_ptes; ++i) {
1462 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1467 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1469 address += APERTURE_RANGE_SIZE / 64;
1473 old_size = dma_dom->aperture_size;
1474 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1476 /* Reserve address range used for MSI messages */
1477 if (old_size < MSI_ADDR_BASE_LO &&
1478 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1479 unsigned long spage;
1482 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1483 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1485 dma_ops_reserve_addresses(dma_dom, spage, pages);
1488 /* Initialize the exclusion range if necessary */
1489 for_each_iommu(iommu) {
1490 if (iommu->exclusion_start &&
1491 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1492 && iommu->exclusion_start < dma_dom->aperture_size) {
1493 unsigned long startpage;
1494 int pages = iommu_num_pages(iommu->exclusion_start,
1495 iommu->exclusion_length,
1497 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1498 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1503 * Check for areas already mapped as present in the new aperture
1504 * range and mark those pages as reserved in the allocator. Such
1505 * mappings may already exist as a result of requested unity
1506 * mappings for devices.
1508 for (i = dma_dom->aperture[index]->offset;
1509 i < dma_dom->aperture_size;
1511 u64 *pte = fetch_pte(&dma_dom->domain, i);
1512 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1515 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1518 update_domain(&dma_dom->domain);
1523 update_domain(&dma_dom->domain);
1525 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1527 kfree(dma_dom->aperture[index]);
1528 dma_dom->aperture[index] = NULL;
1533 static unsigned long dma_ops_area_alloc(struct device *dev,
1534 struct dma_ops_domain *dom,
1536 unsigned long align_mask,
1538 unsigned long start)
1540 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1541 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1542 int i = start >> APERTURE_RANGE_SHIFT;
1543 unsigned long boundary_size;
1544 unsigned long address = -1;
1545 unsigned long limit;
1547 next_bit >>= PAGE_SHIFT;
1549 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1550 PAGE_SIZE) >> PAGE_SHIFT;
1552 for (;i < max_index; ++i) {
1553 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1555 if (dom->aperture[i]->offset >= dma_mask)
1558 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1559 dma_mask >> PAGE_SHIFT);
1561 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1562 limit, next_bit, pages, 0,
1563 boundary_size, align_mask);
1564 if (address != -1) {
1565 address = dom->aperture[i]->offset +
1566 (address << PAGE_SHIFT);
1567 dom->next_address = address + (pages << PAGE_SHIFT);
1577 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1578 struct dma_ops_domain *dom,
1580 unsigned long align_mask,
1583 unsigned long address;
1585 #ifdef CONFIG_IOMMU_STRESS
1586 dom->next_address = 0;
1587 dom->need_flush = true;
1590 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1591 dma_mask, dom->next_address);
1593 if (address == -1) {
1594 dom->next_address = 0;
1595 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1597 dom->need_flush = true;
1600 if (unlikely(address == -1))
1601 address = DMA_ERROR_CODE;
1603 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1609 * The address free function.
1611 * called with domain->lock held
1613 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1614 unsigned long address,
1617 unsigned i = address >> APERTURE_RANGE_SHIFT;
1618 struct aperture_range *range = dom->aperture[i];
1620 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1622 #ifdef CONFIG_IOMMU_STRESS
1627 if (address >= dom->next_address)
1628 dom->need_flush = true;
1630 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1632 bitmap_clear(range->bitmap, address, pages);
1636 /****************************************************************************
1638 * The next functions belong to the domain allocation. A domain is
1639 * allocated for every IOMMU as the default domain. If device isolation
1640 * is enabled, every device get its own domain. The most important thing
1641 * about domains is the page table mapping the DMA address space they
1644 ****************************************************************************/
1647 * This function adds a protection domain to the global protection domain list
1649 static void add_domain_to_list(struct protection_domain *domain)
1651 unsigned long flags;
1653 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1654 list_add(&domain->list, &amd_iommu_pd_list);
1655 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1659 * This function removes a protection domain to the global
1660 * protection domain list
1662 static void del_domain_from_list(struct protection_domain *domain)
1664 unsigned long flags;
1666 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1667 list_del(&domain->list);
1668 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1671 static u16 domain_id_alloc(void)
1673 unsigned long flags;
1676 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1677 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1679 if (id > 0 && id < MAX_DOMAIN_ID)
1680 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1683 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1688 static void domain_id_free(int id)
1690 unsigned long flags;
1692 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1693 if (id > 0 && id < MAX_DOMAIN_ID)
1694 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1695 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1698 static void free_pagetable(struct protection_domain *domain)
1703 p1 = domain->pt_root;
1708 for (i = 0; i < 512; ++i) {
1709 if (!IOMMU_PTE_PRESENT(p1[i]))
1712 p2 = IOMMU_PTE_PAGE(p1[i]);
1713 for (j = 0; j < 512; ++j) {
1714 if (!IOMMU_PTE_PRESENT(p2[j]))
1716 p3 = IOMMU_PTE_PAGE(p2[j]);
1717 free_page((unsigned long)p3);
1720 free_page((unsigned long)p2);
1723 free_page((unsigned long)p1);
1725 domain->pt_root = NULL;
1728 static void free_gcr3_tbl_level1(u64 *tbl)
1733 for (i = 0; i < 512; ++i) {
1734 if (!(tbl[i] & GCR3_VALID))
1737 ptr = __va(tbl[i] & PAGE_MASK);
1739 free_page((unsigned long)ptr);
1743 static void free_gcr3_tbl_level2(u64 *tbl)
1748 for (i = 0; i < 512; ++i) {
1749 if (!(tbl[i] & GCR3_VALID))
1752 ptr = __va(tbl[i] & PAGE_MASK);
1754 free_gcr3_tbl_level1(ptr);
1758 static void free_gcr3_table(struct protection_domain *domain)
1760 if (domain->glx == 2)
1761 free_gcr3_tbl_level2(domain->gcr3_tbl);
1762 else if (domain->glx == 1)
1763 free_gcr3_tbl_level1(domain->gcr3_tbl);
1764 else if (domain->glx != 0)
1767 free_page((unsigned long)domain->gcr3_tbl);
1771 * Free a domain, only used if something went wrong in the
1772 * allocation path and we need to free an already allocated page table
1774 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1781 del_domain_from_list(&dom->domain);
1783 free_pagetable(&dom->domain);
1785 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1786 if (!dom->aperture[i])
1788 free_page((unsigned long)dom->aperture[i]->bitmap);
1789 kfree(dom->aperture[i]);
1796 * Allocates a new protection domain usable for the dma_ops functions.
1797 * It also initializes the page table and the address allocator data
1798 * structures required for the dma_ops interface
1800 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1802 struct dma_ops_domain *dma_dom;
1804 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1808 spin_lock_init(&dma_dom->domain.lock);
1810 dma_dom->domain.id = domain_id_alloc();
1811 if (dma_dom->domain.id == 0)
1813 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1814 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1815 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1816 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1817 dma_dom->domain.priv = dma_dom;
1818 if (!dma_dom->domain.pt_root)
1821 dma_dom->need_flush = false;
1822 dma_dom->target_dev = 0xffff;
1824 add_domain_to_list(&dma_dom->domain);
1826 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1830 * mark the first page as allocated so we never return 0 as
1831 * a valid dma-address. So we can use 0 as error value
1833 dma_dom->aperture[0]->bitmap[0] = 1;
1834 dma_dom->next_address = 0;
1840 dma_ops_domain_free(dma_dom);
1846 * little helper function to check whether a given protection domain is a
1849 static bool dma_ops_domain(struct protection_domain *domain)
1851 return domain->flags & PD_DMA_OPS_MASK;
1854 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1859 if (domain->mode != PAGE_MODE_NONE)
1860 pte_root = virt_to_phys(domain->pt_root);
1862 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1863 << DEV_ENTRY_MODE_SHIFT;
1864 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1866 flags = amd_iommu_dev_table[devid].data[1];
1869 flags |= DTE_FLAG_IOTLB;
1871 if (domain->flags & PD_IOMMUV2_MASK) {
1872 u64 gcr3 = __pa(domain->gcr3_tbl);
1873 u64 glx = domain->glx;
1876 pte_root |= DTE_FLAG_GV;
1877 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1879 /* First mask out possible old values for GCR3 table */
1880 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1883 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1886 /* Encode GCR3 table into DTE */
1887 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1890 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1893 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1897 flags &= ~(0xffffUL);
1898 flags |= domain->id;
1900 amd_iommu_dev_table[devid].data[1] = flags;
1901 amd_iommu_dev_table[devid].data[0] = pte_root;
1904 static void clear_dte_entry(u16 devid)
1906 /* remove entry from the device table seen by the hardware */
1907 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1908 amd_iommu_dev_table[devid].data[1] = 0;
1910 amd_iommu_apply_erratum_63(devid);
1913 static void do_attach(struct iommu_dev_data *dev_data,
1914 struct protection_domain *domain)
1916 struct amd_iommu *iommu;
1919 iommu = amd_iommu_rlookup_table[dev_data->devid];
1920 ats = dev_data->ats.enabled;
1922 /* Update data structures */
1923 dev_data->domain = domain;
1924 list_add(&dev_data->list, &domain->dev_list);
1925 set_dte_entry(dev_data->devid, domain, ats);
1927 /* Do reference counting */
1928 domain->dev_iommu[iommu->index] += 1;
1929 domain->dev_cnt += 1;
1931 /* Flush the DTE entry */
1932 device_flush_dte(dev_data);
1935 static void do_detach(struct iommu_dev_data *dev_data)
1937 struct amd_iommu *iommu;
1939 iommu = amd_iommu_rlookup_table[dev_data->devid];
1941 /* decrease reference counters */
1942 dev_data->domain->dev_iommu[iommu->index] -= 1;
1943 dev_data->domain->dev_cnt -= 1;
1945 /* Update data structures */
1946 dev_data->domain = NULL;
1947 list_del(&dev_data->list);
1948 clear_dte_entry(dev_data->devid);
1950 /* Flush the DTE entry */
1951 device_flush_dte(dev_data);
1955 * If a device is not yet associated with a domain, this function does
1956 * assigns it visible for the hardware
1958 static int __attach_device(struct iommu_dev_data *dev_data,
1959 struct protection_domain *domain)
1964 spin_lock(&domain->lock);
1966 if (dev_data->alias_data != NULL) {
1967 struct iommu_dev_data *alias_data = dev_data->alias_data;
1969 /* Some sanity checks */
1971 if (alias_data->domain != NULL &&
1972 alias_data->domain != domain)
1975 if (dev_data->domain != NULL &&
1976 dev_data->domain != domain)
1979 /* Do real assignment */
1980 if (alias_data->domain == NULL)
1981 do_attach(alias_data, domain);
1983 atomic_inc(&alias_data->bind);
1986 if (dev_data->domain == NULL)
1987 do_attach(dev_data, domain);
1989 atomic_inc(&dev_data->bind);
1996 spin_unlock(&domain->lock);
2002 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2004 pci_disable_ats(pdev);
2005 pci_disable_pri(pdev);
2006 pci_disable_pasid(pdev);
2009 /* FIXME: Change generic reset-function to do the same */
2010 static int pri_reset_while_enabled(struct pci_dev *pdev)
2015 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2019 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2020 control |= PCI_PRI_CTRL_RESET;
2021 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2026 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2031 /* FIXME: Hardcode number of outstanding requests for now */
2033 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2035 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2037 /* Only allow access to user-accessible pages */
2038 ret = pci_enable_pasid(pdev, 0);
2042 /* First reset the PRI state of the device */
2043 ret = pci_reset_pri(pdev);
2048 ret = pci_enable_pri(pdev, reqs);
2053 ret = pri_reset_while_enabled(pdev);
2058 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2065 pci_disable_pri(pdev);
2066 pci_disable_pasid(pdev);
2071 /* FIXME: Move this to PCI code */
2072 #define PCI_PRI_TLP_OFF (1 << 15)
2074 bool pci_pri_tlp_required(struct pci_dev *pdev)
2079 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2083 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2085 return (status & PCI_PRI_TLP_OFF) ? true : false;
2089 * If a device is not yet associated with a domain, this function does
2090 * assigns it visible for the hardware
2092 static int attach_device(struct device *dev,
2093 struct protection_domain *domain)
2095 struct pci_dev *pdev = to_pci_dev(dev);
2096 struct iommu_dev_data *dev_data;
2097 unsigned long flags;
2100 dev_data = get_dev_data(dev);
2102 if (domain->flags & PD_IOMMUV2_MASK) {
2103 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2106 if (pdev_iommuv2_enable(pdev) != 0)
2109 dev_data->ats.enabled = true;
2110 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2111 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2112 } else if (amd_iommu_iotlb_sup &&
2113 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2114 dev_data->ats.enabled = true;
2115 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2118 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2119 ret = __attach_device(dev_data, domain);
2120 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2123 * We might boot into a crash-kernel here. The crashed kernel
2124 * left the caches in the IOMMU dirty. So we have to flush
2125 * here to evict all dirty stuff.
2127 domain_flush_tlb_pde(domain);
2133 * Removes a device from a protection domain (unlocked)
2135 static void __detach_device(struct iommu_dev_data *dev_data)
2137 struct protection_domain *domain;
2138 unsigned long flags;
2140 BUG_ON(!dev_data->domain);
2142 domain = dev_data->domain;
2144 spin_lock_irqsave(&domain->lock, flags);
2146 if (dev_data->alias_data != NULL) {
2147 struct iommu_dev_data *alias_data = dev_data->alias_data;
2149 if (atomic_dec_and_test(&alias_data->bind))
2150 do_detach(alias_data);
2153 if (atomic_dec_and_test(&dev_data->bind))
2154 do_detach(dev_data);
2156 spin_unlock_irqrestore(&domain->lock, flags);
2159 * If we run in passthrough mode the device must be assigned to the
2160 * passthrough domain if it is detached from any other domain.
2161 * Make sure we can deassign from the pt_domain itself.
2163 if (dev_data->passthrough &&
2164 (dev_data->domain == NULL && domain != pt_domain))
2165 __attach_device(dev_data, pt_domain);
2169 * Removes a device from a protection domain (with devtable_lock held)
2171 static void detach_device(struct device *dev)
2173 struct protection_domain *domain;
2174 struct iommu_dev_data *dev_data;
2175 unsigned long flags;
2177 dev_data = get_dev_data(dev);
2178 domain = dev_data->domain;
2180 /* lock device table */
2181 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2182 __detach_device(dev_data);
2183 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2185 if (domain->flags & PD_IOMMUV2_MASK)
2186 pdev_iommuv2_disable(to_pci_dev(dev));
2187 else if (dev_data->ats.enabled)
2188 pci_disable_ats(to_pci_dev(dev));
2190 dev_data->ats.enabled = false;
2194 * Find out the protection domain structure for a given PCI device. This
2195 * will give us the pointer to the page table root for example.
2197 static struct protection_domain *domain_for_device(struct device *dev)
2199 struct iommu_dev_data *dev_data;
2200 struct protection_domain *dom = NULL;
2201 unsigned long flags;
2203 dev_data = get_dev_data(dev);
2205 if (dev_data->domain)
2206 return dev_data->domain;
2208 if (dev_data->alias_data != NULL) {
2209 struct iommu_dev_data *alias_data = dev_data->alias_data;
2211 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2212 if (alias_data->domain != NULL) {
2213 __attach_device(dev_data, alias_data->domain);
2214 dom = alias_data->domain;
2216 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2222 static int device_change_notifier(struct notifier_block *nb,
2223 unsigned long action, void *data)
2225 struct dma_ops_domain *dma_domain;
2226 struct protection_domain *domain;
2227 struct iommu_dev_data *dev_data;
2228 struct device *dev = data;
2229 struct amd_iommu *iommu;
2230 unsigned long flags;
2233 if (!check_device(dev))
2236 devid = get_device_id(dev);
2237 iommu = amd_iommu_rlookup_table[devid];
2238 dev_data = get_dev_data(dev);
2241 case BUS_NOTIFY_UNBOUND_DRIVER:
2243 domain = domain_for_device(dev);
2247 if (dev_data->passthrough)
2251 case BUS_NOTIFY_ADD_DEVICE:
2253 iommu_init_device(dev);
2255 domain = domain_for_device(dev);
2257 /* allocate a protection domain if a device is added */
2258 dma_domain = find_protection_domain(devid);
2261 dma_domain = dma_ops_domain_alloc();
2264 dma_domain->target_dev = devid;
2266 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2267 list_add_tail(&dma_domain->list, &iommu_pd_list);
2268 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2271 case BUS_NOTIFY_DEL_DEVICE:
2273 iommu_uninit_device(dev);
2279 iommu_completion_wait(iommu);
2285 static struct notifier_block device_nb = {
2286 .notifier_call = device_change_notifier,
2289 void amd_iommu_init_notifier(void)
2291 bus_register_notifier(&pci_bus_type, &device_nb);
2294 /*****************************************************************************
2296 * The next functions belong to the dma_ops mapping/unmapping code.
2298 *****************************************************************************/
2301 * In the dma_ops path we only have the struct device. This function
2302 * finds the corresponding IOMMU, the protection domain and the
2303 * requestor id for a given device.
2304 * If the device is not yet associated with a domain this is also done
2307 static struct protection_domain *get_domain(struct device *dev)
2309 struct protection_domain *domain;
2310 struct dma_ops_domain *dma_dom;
2311 u16 devid = get_device_id(dev);
2313 if (!check_device(dev))
2314 return ERR_PTR(-EINVAL);
2316 domain = domain_for_device(dev);
2317 if (domain != NULL && !dma_ops_domain(domain))
2318 return ERR_PTR(-EBUSY);
2323 /* Device not bount yet - bind it */
2324 dma_dom = find_protection_domain(devid);
2326 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2327 attach_device(dev, &dma_dom->domain);
2328 DUMP_printk("Using protection domain %d for device %s\n",
2329 dma_dom->domain.id, dev_name(dev));
2331 return &dma_dom->domain;
2334 static void update_device_table(struct protection_domain *domain)
2336 struct iommu_dev_data *dev_data;
2338 list_for_each_entry(dev_data, &domain->dev_list, list)
2339 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2342 static void update_domain(struct protection_domain *domain)
2344 if (!domain->updated)
2347 update_device_table(domain);
2349 domain_flush_devices(domain);
2350 domain_flush_tlb_pde(domain);
2352 domain->updated = false;
2356 * This function fetches the PTE for a given address in the aperture
2358 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2359 unsigned long address)
2361 struct aperture_range *aperture;
2362 u64 *pte, *pte_page;
2364 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2368 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2370 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2372 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2374 pte += PM_LEVEL_INDEX(0, address);
2376 update_domain(&dom->domain);
2382 * This is the generic map function. It maps one 4kb page at paddr to
2383 * the given address in the DMA address space for the domain.
2385 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2386 unsigned long address,
2392 WARN_ON(address > dom->aperture_size);
2396 pte = dma_ops_get_pte(dom, address);
2398 return DMA_ERROR_CODE;
2400 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2402 if (direction == DMA_TO_DEVICE)
2403 __pte |= IOMMU_PTE_IR;
2404 else if (direction == DMA_FROM_DEVICE)
2405 __pte |= IOMMU_PTE_IW;
2406 else if (direction == DMA_BIDIRECTIONAL)
2407 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2413 return (dma_addr_t)address;
2417 * The generic unmapping function for on page in the DMA address space.
2419 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2420 unsigned long address)
2422 struct aperture_range *aperture;
2425 if (address >= dom->aperture_size)
2428 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2432 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2436 pte += PM_LEVEL_INDEX(0, address);
2444 * This function contains common code for mapping of a physically
2445 * contiguous memory region into DMA address space. It is used by all
2446 * mapping functions provided with this IOMMU driver.
2447 * Must be called with the domain lock held.
2449 static dma_addr_t __map_single(struct device *dev,
2450 struct dma_ops_domain *dma_dom,
2457 dma_addr_t offset = paddr & ~PAGE_MASK;
2458 dma_addr_t address, start, ret;
2460 unsigned long align_mask = 0;
2463 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2466 INC_STATS_COUNTER(total_map_requests);
2469 INC_STATS_COUNTER(cross_page);
2472 align_mask = (1UL << get_order(size)) - 1;
2475 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2477 if (unlikely(address == DMA_ERROR_CODE)) {
2479 * setting next_address here will let the address
2480 * allocator only scan the new allocated range in the
2481 * first run. This is a small optimization.
2483 dma_dom->next_address = dma_dom->aperture_size;
2485 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2489 * aperture was successfully enlarged by 128 MB, try
2496 for (i = 0; i < pages; ++i) {
2497 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2498 if (ret == DMA_ERROR_CODE)
2506 ADD_STATS_COUNTER(alloced_io_mem, size);
2508 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2509 domain_flush_tlb(&dma_dom->domain);
2510 dma_dom->need_flush = false;
2511 } else if (unlikely(amd_iommu_np_cache))
2512 domain_flush_pages(&dma_dom->domain, address, size);
2519 for (--i; i >= 0; --i) {
2521 dma_ops_domain_unmap(dma_dom, start);
2524 dma_ops_free_addresses(dma_dom, address, pages);
2526 return DMA_ERROR_CODE;
2530 * Does the reverse of the __map_single function. Must be called with
2531 * the domain lock held too
2533 static void __unmap_single(struct dma_ops_domain *dma_dom,
2534 dma_addr_t dma_addr,
2538 dma_addr_t flush_addr;
2539 dma_addr_t i, start;
2542 if ((dma_addr == DMA_ERROR_CODE) ||
2543 (dma_addr + size > dma_dom->aperture_size))
2546 flush_addr = dma_addr;
2547 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2548 dma_addr &= PAGE_MASK;
2551 for (i = 0; i < pages; ++i) {
2552 dma_ops_domain_unmap(dma_dom, start);
2556 SUB_STATS_COUNTER(alloced_io_mem, size);
2558 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2560 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2561 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2562 dma_dom->need_flush = false;
2567 * The exported map_single function for dma_ops.
2569 static dma_addr_t map_page(struct device *dev, struct page *page,
2570 unsigned long offset, size_t size,
2571 enum dma_data_direction dir,
2572 struct dma_attrs *attrs)
2574 unsigned long flags;
2575 struct protection_domain *domain;
2578 phys_addr_t paddr = page_to_phys(page) + offset;
2580 INC_STATS_COUNTER(cnt_map_single);
2582 domain = get_domain(dev);
2583 if (PTR_ERR(domain) == -EINVAL)
2584 return (dma_addr_t)paddr;
2585 else if (IS_ERR(domain))
2586 return DMA_ERROR_CODE;
2588 dma_mask = *dev->dma_mask;
2590 spin_lock_irqsave(&domain->lock, flags);
2592 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2594 if (addr == DMA_ERROR_CODE)
2597 domain_flush_complete(domain);
2600 spin_unlock_irqrestore(&domain->lock, flags);
2606 * The exported unmap_single function for dma_ops.
2608 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2609 enum dma_data_direction dir, struct dma_attrs *attrs)
2611 unsigned long flags;
2612 struct protection_domain *domain;
2614 INC_STATS_COUNTER(cnt_unmap_single);
2616 domain = get_domain(dev);
2620 spin_lock_irqsave(&domain->lock, flags);
2622 __unmap_single(domain->priv, dma_addr, size, dir);
2624 domain_flush_complete(domain);
2626 spin_unlock_irqrestore(&domain->lock, flags);
2630 * This is a special map_sg function which is used if we should map a
2631 * device which is not handled by an AMD IOMMU in the system.
2633 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2634 int nelems, int dir)
2636 struct scatterlist *s;
2639 for_each_sg(sglist, s, nelems, i) {
2640 s->dma_address = (dma_addr_t)sg_phys(s);
2641 s->dma_length = s->length;
2648 * The exported map_sg function for dma_ops (handles scatter-gather
2651 static int map_sg(struct device *dev, struct scatterlist *sglist,
2652 int nelems, enum dma_data_direction dir,
2653 struct dma_attrs *attrs)
2655 unsigned long flags;
2656 struct protection_domain *domain;
2658 struct scatterlist *s;
2660 int mapped_elems = 0;
2663 INC_STATS_COUNTER(cnt_map_sg);
2665 domain = get_domain(dev);
2666 if (PTR_ERR(domain) == -EINVAL)
2667 return map_sg_no_iommu(dev, sglist, nelems, dir);
2668 else if (IS_ERR(domain))
2671 dma_mask = *dev->dma_mask;
2673 spin_lock_irqsave(&domain->lock, flags);
2675 for_each_sg(sglist, s, nelems, i) {
2678 s->dma_address = __map_single(dev, domain->priv,
2679 paddr, s->length, dir, false,
2682 if (s->dma_address) {
2683 s->dma_length = s->length;
2689 domain_flush_complete(domain);
2692 spin_unlock_irqrestore(&domain->lock, flags);
2694 return mapped_elems;
2696 for_each_sg(sglist, s, mapped_elems, i) {
2698 __unmap_single(domain->priv, s->dma_address,
2699 s->dma_length, dir);
2700 s->dma_address = s->dma_length = 0;
2709 * The exported map_sg function for dma_ops (handles scatter-gather
2712 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2713 int nelems, enum dma_data_direction dir,
2714 struct dma_attrs *attrs)
2716 unsigned long flags;
2717 struct protection_domain *domain;
2718 struct scatterlist *s;
2721 INC_STATS_COUNTER(cnt_unmap_sg);
2723 domain = get_domain(dev);
2727 spin_lock_irqsave(&domain->lock, flags);
2729 for_each_sg(sglist, s, nelems, i) {
2730 __unmap_single(domain->priv, s->dma_address,
2731 s->dma_length, dir);
2732 s->dma_address = s->dma_length = 0;
2735 domain_flush_complete(domain);
2737 spin_unlock_irqrestore(&domain->lock, flags);
2741 * The exported alloc_coherent function for dma_ops.
2743 static void *alloc_coherent(struct device *dev, size_t size,
2744 dma_addr_t *dma_addr, gfp_t flag,
2745 struct dma_attrs *attrs)
2747 unsigned long flags;
2749 struct protection_domain *domain;
2751 u64 dma_mask = dev->coherent_dma_mask;
2753 INC_STATS_COUNTER(cnt_alloc_coherent);
2755 domain = get_domain(dev);
2756 if (PTR_ERR(domain) == -EINVAL) {
2757 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2758 *dma_addr = __pa(virt_addr);
2760 } else if (IS_ERR(domain))
2763 dma_mask = dev->coherent_dma_mask;
2764 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2767 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2771 paddr = virt_to_phys(virt_addr);
2774 dma_mask = *dev->dma_mask;
2776 spin_lock_irqsave(&domain->lock, flags);
2778 *dma_addr = __map_single(dev, domain->priv, paddr,
2779 size, DMA_BIDIRECTIONAL, true, dma_mask);
2781 if (*dma_addr == DMA_ERROR_CODE) {
2782 spin_unlock_irqrestore(&domain->lock, flags);
2786 domain_flush_complete(domain);
2788 spin_unlock_irqrestore(&domain->lock, flags);
2794 free_pages((unsigned long)virt_addr, get_order(size));
2800 * The exported free_coherent function for dma_ops.
2802 static void free_coherent(struct device *dev, size_t size,
2803 void *virt_addr, dma_addr_t dma_addr,
2804 struct dma_attrs *attrs)
2806 unsigned long flags;
2807 struct protection_domain *domain;
2809 INC_STATS_COUNTER(cnt_free_coherent);
2811 domain = get_domain(dev);
2815 spin_lock_irqsave(&domain->lock, flags);
2817 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2819 domain_flush_complete(domain);
2821 spin_unlock_irqrestore(&domain->lock, flags);
2824 free_pages((unsigned long)virt_addr, get_order(size));
2828 * This function is called by the DMA layer to find out if we can handle a
2829 * particular device. It is part of the dma_ops.
2831 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2833 return check_device(dev);
2837 * The function for pre-allocating protection domains.
2839 * If the driver core informs the DMA layer if a driver grabs a device
2840 * we don't need to preallocate the protection domains anymore.
2841 * For now we have to.
2843 static void __init prealloc_protection_domains(void)
2845 struct iommu_dev_data *dev_data;
2846 struct dma_ops_domain *dma_dom;
2847 struct pci_dev *dev = NULL;
2850 for_each_pci_dev(dev) {
2852 /* Do we handle this device? */
2853 if (!check_device(&dev->dev))
2856 dev_data = get_dev_data(&dev->dev);
2857 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
2858 /* Make sure passthrough domain is allocated */
2859 alloc_passthrough_domain();
2860 dev_data->passthrough = true;
2861 attach_device(&dev->dev, pt_domain);
2862 pr_info("AMD-Vi: Using passthough domain for device %s\n",
2863 dev_name(&dev->dev));
2866 /* Is there already any domain for it? */
2867 if (domain_for_device(&dev->dev))
2870 devid = get_device_id(&dev->dev);
2872 dma_dom = dma_ops_domain_alloc();
2875 init_unity_mappings_for_device(dma_dom, devid);
2876 dma_dom->target_dev = devid;
2878 attach_device(&dev->dev, &dma_dom->domain);
2880 list_add_tail(&dma_dom->list, &iommu_pd_list);
2884 static struct dma_map_ops amd_iommu_dma_ops = {
2885 .alloc = alloc_coherent,
2886 .free = free_coherent,
2887 .map_page = map_page,
2888 .unmap_page = unmap_page,
2890 .unmap_sg = unmap_sg,
2891 .dma_supported = amd_iommu_dma_supported,
2894 static unsigned device_dma_ops_init(void)
2896 struct iommu_dev_data *dev_data;
2897 struct pci_dev *pdev = NULL;
2898 unsigned unhandled = 0;
2900 for_each_pci_dev(pdev) {
2901 if (!check_device(&pdev->dev)) {
2903 iommu_ignore_device(&pdev->dev);
2909 dev_data = get_dev_data(&pdev->dev);
2911 if (!dev_data->passthrough)
2912 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2914 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
2921 * The function which clues the AMD IOMMU driver into dma_ops.
2924 void __init amd_iommu_init_api(void)
2926 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2929 int __init amd_iommu_init_dma_ops(void)
2931 struct amd_iommu *iommu;
2935 * first allocate a default protection domain for every IOMMU we
2936 * found in the system. Devices not assigned to any other
2937 * protection domain will be assigned to the default one.
2939 for_each_iommu(iommu) {
2940 iommu->default_dom = dma_ops_domain_alloc();
2941 if (iommu->default_dom == NULL)
2943 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2944 ret = iommu_init_unity_mappings(iommu);
2950 * Pre-allocate the protection domains for each device.
2952 prealloc_protection_domains();
2957 /* Make the driver finally visible to the drivers */
2958 unhandled = device_dma_ops_init();
2959 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2960 /* There are unhandled devices - initialize swiotlb for them */
2964 amd_iommu_stats_init();
2970 for_each_iommu(iommu) {
2971 if (iommu->default_dom)
2972 dma_ops_domain_free(iommu->default_dom);
2978 /*****************************************************************************
2980 * The following functions belong to the exported interface of AMD IOMMU
2982 * This interface allows access to lower level functions of the IOMMU
2983 * like protection domain handling and assignement of devices to domains
2984 * which is not possible with the dma_ops interface.
2986 *****************************************************************************/
2988 static void cleanup_domain(struct protection_domain *domain)
2990 struct iommu_dev_data *dev_data, *next;
2991 unsigned long flags;
2993 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2995 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2996 __detach_device(dev_data);
2997 atomic_set(&dev_data->bind, 0);
3000 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3003 static void protection_domain_free(struct protection_domain *domain)
3008 del_domain_from_list(domain);
3011 domain_id_free(domain->id);
3016 static struct protection_domain *protection_domain_alloc(void)
3018 struct protection_domain *domain;
3020 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3024 spin_lock_init(&domain->lock);
3025 mutex_init(&domain->api_lock);
3026 domain->id = domain_id_alloc();
3029 INIT_LIST_HEAD(&domain->dev_list);
3031 add_domain_to_list(domain);
3041 static int __init alloc_passthrough_domain(void)
3043 if (pt_domain != NULL)
3046 /* allocate passthrough domain */
3047 pt_domain = protection_domain_alloc();
3051 pt_domain->mode = PAGE_MODE_NONE;
3055 static int amd_iommu_domain_init(struct iommu_domain *dom)
3057 struct protection_domain *domain;
3059 domain = protection_domain_alloc();
3063 domain->mode = PAGE_MODE_3_LEVEL;
3064 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3065 if (!domain->pt_root)
3068 domain->iommu_domain = dom;
3075 protection_domain_free(domain);
3080 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3082 struct protection_domain *domain = dom->priv;
3087 if (domain->dev_cnt > 0)
3088 cleanup_domain(domain);
3090 BUG_ON(domain->dev_cnt != 0);
3092 if (domain->mode != PAGE_MODE_NONE)
3093 free_pagetable(domain);
3095 if (domain->flags & PD_IOMMUV2_MASK)
3096 free_gcr3_table(domain);
3098 protection_domain_free(domain);
3103 static void amd_iommu_detach_device(struct iommu_domain *dom,
3106 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3107 struct amd_iommu *iommu;
3110 if (!check_device(dev))
3113 devid = get_device_id(dev);
3115 if (dev_data->domain != NULL)
3118 iommu = amd_iommu_rlookup_table[devid];
3122 iommu_completion_wait(iommu);
3125 static int amd_iommu_attach_device(struct iommu_domain *dom,
3128 struct protection_domain *domain = dom->priv;
3129 struct iommu_dev_data *dev_data;
3130 struct amd_iommu *iommu;
3133 if (!check_device(dev))
3136 dev_data = dev->archdata.iommu;
3138 iommu = amd_iommu_rlookup_table[dev_data->devid];
3142 if (dev_data->domain)
3145 ret = attach_device(dev, domain);
3147 iommu_completion_wait(iommu);
3152 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3153 phys_addr_t paddr, size_t page_size, int iommu_prot)
3155 struct protection_domain *domain = dom->priv;
3159 if (domain->mode == PAGE_MODE_NONE)
3162 if (iommu_prot & IOMMU_READ)
3163 prot |= IOMMU_PROT_IR;
3164 if (iommu_prot & IOMMU_WRITE)
3165 prot |= IOMMU_PROT_IW;
3167 mutex_lock(&domain->api_lock);
3168 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3169 mutex_unlock(&domain->api_lock);
3174 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3177 struct protection_domain *domain = dom->priv;
3180 if (domain->mode == PAGE_MODE_NONE)
3183 mutex_lock(&domain->api_lock);
3184 unmap_size = iommu_unmap_page(domain, iova, page_size);
3185 mutex_unlock(&domain->api_lock);
3187 domain_flush_tlb_pde(domain);
3192 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3195 struct protection_domain *domain = dom->priv;
3196 unsigned long offset_mask;
3200 if (domain->mode == PAGE_MODE_NONE)
3203 pte = fetch_pte(domain, iova);
3205 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3208 if (PM_PTE_LEVEL(*pte) == 0)
3209 offset_mask = PAGE_SIZE - 1;
3211 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3213 __pte = *pte & PM_ADDR_MASK;
3214 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3219 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3223 case IOMMU_CAP_CACHE_COHERENCY:
3230 static int amd_iommu_device_group(struct device *dev, unsigned int *groupid)
3232 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3233 struct pci_dev *pdev = to_pci_dev(dev);
3239 if (pdev->is_virtfn || !iommu_group_mf)
3240 devid = dev_data->devid;
3242 devid = calc_devid(pdev->bus->number,
3243 PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
3245 *groupid = amd_iommu_alias_table[devid];
3250 static struct iommu_ops amd_iommu_ops = {
3251 .domain_init = amd_iommu_domain_init,
3252 .domain_destroy = amd_iommu_domain_destroy,
3253 .attach_dev = amd_iommu_attach_device,
3254 .detach_dev = amd_iommu_detach_device,
3255 .map = amd_iommu_map,
3256 .unmap = amd_iommu_unmap,
3257 .iova_to_phys = amd_iommu_iova_to_phys,
3258 .domain_has_cap = amd_iommu_domain_has_cap,
3259 .device_group = amd_iommu_device_group,
3260 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3263 /*****************************************************************************
3265 * The next functions do a basic initialization of IOMMU for pass through
3268 * In passthrough mode the IOMMU is initialized and enabled but not used for
3269 * DMA-API translation.
3271 *****************************************************************************/
3273 int __init amd_iommu_init_passthrough(void)
3275 struct iommu_dev_data *dev_data;
3276 struct pci_dev *dev = NULL;
3277 struct amd_iommu *iommu;
3281 ret = alloc_passthrough_domain();
3285 for_each_pci_dev(dev) {
3286 if (!check_device(&dev->dev))
3289 dev_data = get_dev_data(&dev->dev);
3290 dev_data->passthrough = true;
3292 devid = get_device_id(&dev->dev);
3294 iommu = amd_iommu_rlookup_table[devid];
3298 attach_device(&dev->dev, pt_domain);
3301 amd_iommu_stats_init();
3303 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3308 /* IOMMUv2 specific functions */
3309 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3311 return atomic_notifier_chain_register(&ppr_notifier, nb);
3313 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3315 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3317 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3319 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3321 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3323 struct protection_domain *domain = dom->priv;
3324 unsigned long flags;
3326 spin_lock_irqsave(&domain->lock, flags);
3328 /* Update data structure */
3329 domain->mode = PAGE_MODE_NONE;
3330 domain->updated = true;
3332 /* Make changes visible to IOMMUs */
3333 update_domain(domain);
3335 /* Page-table is not visible to IOMMU anymore, so free it */
3336 free_pagetable(domain);
3338 spin_unlock_irqrestore(&domain->lock, flags);
3340 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3342 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3344 struct protection_domain *domain = dom->priv;
3345 unsigned long flags;
3348 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3351 /* Number of GCR3 table levels required */
3352 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3355 if (levels > amd_iommu_max_glx_val)
3358 spin_lock_irqsave(&domain->lock, flags);
3361 * Save us all sanity checks whether devices already in the
3362 * domain support IOMMUv2. Just force that the domain has no
3363 * devices attached when it is switched into IOMMUv2 mode.
3366 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3370 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3371 if (domain->gcr3_tbl == NULL)
3374 domain->glx = levels;
3375 domain->flags |= PD_IOMMUV2_MASK;
3376 domain->updated = true;
3378 update_domain(domain);
3383 spin_unlock_irqrestore(&domain->lock, flags);
3387 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3389 static int __flush_pasid(struct protection_domain *domain, int pasid,
3390 u64 address, bool size)
3392 struct iommu_dev_data *dev_data;
3393 struct iommu_cmd cmd;
3396 if (!(domain->flags & PD_IOMMUV2_MASK))
3399 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3402 * IOMMU TLB needs to be flushed before Device TLB to
3403 * prevent device TLB refill from IOMMU TLB
3405 for (i = 0; i < amd_iommus_present; ++i) {
3406 if (domain->dev_iommu[i] == 0)
3409 ret = iommu_queue_command(amd_iommus[i], &cmd);
3414 /* Wait until IOMMU TLB flushes are complete */
3415 domain_flush_complete(domain);
3417 /* Now flush device TLBs */
3418 list_for_each_entry(dev_data, &domain->dev_list, list) {
3419 struct amd_iommu *iommu;
3422 BUG_ON(!dev_data->ats.enabled);
3424 qdep = dev_data->ats.qdep;
3425 iommu = amd_iommu_rlookup_table[dev_data->devid];
3427 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3428 qdep, address, size);
3430 ret = iommu_queue_command(iommu, &cmd);
3435 /* Wait until all device TLBs are flushed */
3436 domain_flush_complete(domain);
3445 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3448 INC_STATS_COUNTER(invalidate_iotlb);
3450 return __flush_pasid(domain, pasid, address, false);
3453 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3456 struct protection_domain *domain = dom->priv;
3457 unsigned long flags;
3460 spin_lock_irqsave(&domain->lock, flags);
3461 ret = __amd_iommu_flush_page(domain, pasid, address);
3462 spin_unlock_irqrestore(&domain->lock, flags);
3466 EXPORT_SYMBOL(amd_iommu_flush_page);
3468 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3470 INC_STATS_COUNTER(invalidate_iotlb_all);
3472 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3476 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3478 struct protection_domain *domain = dom->priv;
3479 unsigned long flags;
3482 spin_lock_irqsave(&domain->lock, flags);
3483 ret = __amd_iommu_flush_tlb(domain, pasid);
3484 spin_unlock_irqrestore(&domain->lock, flags);
3488 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3490 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3497 index = (pasid >> (9 * level)) & 0x1ff;
3503 if (!(*pte & GCR3_VALID)) {
3507 root = (void *)get_zeroed_page(GFP_ATOMIC);
3511 *pte = __pa(root) | GCR3_VALID;
3514 root = __va(*pte & PAGE_MASK);
3522 static int __set_gcr3(struct protection_domain *domain, int pasid,
3527 if (domain->mode != PAGE_MODE_NONE)
3530 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3534 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3536 return __amd_iommu_flush_tlb(domain, pasid);
3539 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3543 if (domain->mode != PAGE_MODE_NONE)
3546 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3552 return __amd_iommu_flush_tlb(domain, pasid);
3555 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3558 struct protection_domain *domain = dom->priv;
3559 unsigned long flags;
3562 spin_lock_irqsave(&domain->lock, flags);
3563 ret = __set_gcr3(domain, pasid, cr3);
3564 spin_unlock_irqrestore(&domain->lock, flags);
3568 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3570 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3572 struct protection_domain *domain = dom->priv;
3573 unsigned long flags;
3576 spin_lock_irqsave(&domain->lock, flags);
3577 ret = __clear_gcr3(domain, pasid);
3578 spin_unlock_irqrestore(&domain->lock, flags);
3582 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3584 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3585 int status, int tag)
3587 struct iommu_dev_data *dev_data;
3588 struct amd_iommu *iommu;
3589 struct iommu_cmd cmd;
3591 INC_STATS_COUNTER(complete_ppr);
3593 dev_data = get_dev_data(&pdev->dev);
3594 iommu = amd_iommu_rlookup_table[dev_data->devid];
3596 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3597 tag, dev_data->pri_tlp);
3599 return iommu_queue_command(iommu, &cmd);
3601 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3603 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3605 struct protection_domain *domain;
3607 domain = get_domain(&pdev->dev);
3611 /* Only return IOMMUv2 domains */
3612 if (!(domain->flags & PD_IOMMUV2_MASK))
3615 return domain->iommu_domain;
3617 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3619 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3621 struct iommu_dev_data *dev_data;
3623 if (!amd_iommu_v2_supported())
3626 dev_data = get_dev_data(&pdev->dev);
3627 dev_data->errata |= (1 << erratum);
3629 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3631 int amd_iommu_device_info(struct pci_dev *pdev,
3632 struct amd_iommu_device_info *info)
3637 if (pdev == NULL || info == NULL)
3640 if (!amd_iommu_v2_supported())
3643 memset(info, 0, sizeof(*info));
3645 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3647 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3649 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3651 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3653 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3657 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3658 max_pasids = min(max_pasids, (1 << 20));
3660 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3661 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3663 features = pci_pasid_features(pdev);
3664 if (features & PCI_PASID_CAP_EXEC)
3665 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3666 if (features & PCI_PASID_CAP_PRIV)
3667 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3672 EXPORT_SYMBOL(amd_iommu_device_info);