2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
58 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
60 #define LOOP_TIMEOUT 100000
62 /* IO virtual address start page frame number */
63 #define IOVA_START_PFN (1)
64 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
78 * 512GB Pages are not supported due to a hardware bug
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
82 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
83 static DEFINE_SPINLOCK(pd_bitmap_lock);
85 /* List of all available dev_data structures */
86 static LLIST_HEAD(dev_data_list);
88 LIST_HEAD(ioapic_map);
90 LIST_HEAD(acpihid_map);
93 * Domain for untranslated devices - only allocated
94 * if iommu=pt passed on kernel cmd line.
96 const struct iommu_ops amd_iommu_ops;
98 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
99 int amd_iommu_max_glx_val = -1;
101 static const struct dma_map_ops amd_iommu_dma_ops;
104 * general struct to manage commands send to an IOMMU
110 struct kmem_cache *amd_iommu_irq_cache;
112 static void update_domain(struct protection_domain *domain);
113 static int protection_domain_init(struct protection_domain *domain);
114 static void detach_device(struct device *dev);
115 static void iova_domain_flush_tlb(struct iova_domain *iovad);
118 * Data container for a dma_ops specific protection domain
120 struct dma_ops_domain {
121 /* generic protection domain information */
122 struct protection_domain domain;
125 struct iova_domain iovad;
128 static struct iova_domain reserved_iova_ranges;
129 static struct lock_class_key reserved_rbtree_key;
131 /****************************************************************************
135 ****************************************************************************/
137 static inline int match_hid_uid(struct device *dev,
138 struct acpihid_map_entry *entry)
140 const char *hid, *uid;
142 hid = acpi_device_hid(ACPI_COMPANION(dev));
143 uid = acpi_device_uid(ACPI_COMPANION(dev));
149 return strcmp(hid, entry->hid);
152 return strcmp(hid, entry->hid);
154 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
157 static inline u16 get_pci_device_id(struct device *dev)
159 struct pci_dev *pdev = to_pci_dev(dev);
161 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164 static inline int get_acpihid_device_id(struct device *dev,
165 struct acpihid_map_entry **entry)
167 struct acpihid_map_entry *p;
169 list_for_each_entry(p, &acpihid_map, list) {
170 if (!match_hid_uid(dev, p)) {
179 static inline int get_device_id(struct device *dev)
184 devid = get_pci_device_id(dev);
186 devid = get_acpihid_device_id(dev, NULL);
191 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
193 return container_of(dom, struct protection_domain, domain);
196 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
198 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
199 return container_of(domain, struct dma_ops_domain, domain);
202 static struct iommu_dev_data *alloc_dev_data(u16 devid)
204 struct iommu_dev_data *dev_data;
206 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
210 dev_data->devid = devid;
211 ratelimit_default_init(&dev_data->rs);
213 llist_add(&dev_data->dev_data_list, &dev_data_list);
217 static struct iommu_dev_data *search_dev_data(u16 devid)
219 struct iommu_dev_data *dev_data;
220 struct llist_node *node;
222 if (llist_empty(&dev_data_list))
225 node = dev_data_list.first;
226 llist_for_each_entry(dev_data, node, dev_data_list) {
227 if (dev_data->devid == devid)
234 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
236 *(u16 *)data = alias;
240 static u16 get_alias(struct device *dev)
242 struct pci_dev *pdev = to_pci_dev(dev);
243 u16 devid, ivrs_alias, pci_alias;
245 /* The callers make sure that get_device_id() does not fail here */
246 devid = get_device_id(dev);
248 /* For ACPI HID devices, we simply return the devid as such */
249 if (!dev_is_pci(dev))
252 ivrs_alias = amd_iommu_alias_table[devid];
254 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
256 if (ivrs_alias == pci_alias)
262 * The IVRS is fairly reliable in telling us about aliases, but it
263 * can't know about every screwy device. If we don't have an IVRS
264 * reported alias, use the PCI reported alias. In that case we may
265 * still need to initialize the rlookup and dev_table entries if the
266 * alias is to a non-existent device.
268 if (ivrs_alias == devid) {
269 if (!amd_iommu_rlookup_table[pci_alias]) {
270 amd_iommu_rlookup_table[pci_alias] =
271 amd_iommu_rlookup_table[devid];
272 memcpy(amd_iommu_dev_table[pci_alias].data,
273 amd_iommu_dev_table[devid].data,
274 sizeof(amd_iommu_dev_table[pci_alias].data));
280 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
281 "for device %s[%04x:%04x], kernel reported alias "
282 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
283 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
284 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
285 PCI_FUNC(pci_alias));
288 * If we don't have a PCI DMA alias and the IVRS alias is on the same
289 * bus, then the IVRS table may know about a quirk that we don't.
291 if (pci_alias == devid &&
292 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
293 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
294 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
295 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
302 static struct iommu_dev_data *find_dev_data(u16 devid)
304 struct iommu_dev_data *dev_data;
305 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
307 dev_data = search_dev_data(devid);
309 if (dev_data == NULL) {
310 dev_data = alloc_dev_data(devid);
314 if (translation_pre_enabled(iommu))
315 dev_data->defer_attach = true;
321 struct iommu_dev_data *get_dev_data(struct device *dev)
323 return dev->archdata.iommu;
325 EXPORT_SYMBOL(get_dev_data);
328 * Find or create an IOMMU group for a acpihid device.
330 static struct iommu_group *acpihid_device_group(struct device *dev)
332 struct acpihid_map_entry *p, *entry = NULL;
335 devid = get_acpihid_device_id(dev, &entry);
337 return ERR_PTR(devid);
339 list_for_each_entry(p, &acpihid_map, list) {
340 if ((devid == p->devid) && p->group)
341 entry->group = p->group;
345 entry->group = generic_device_group(dev);
347 iommu_group_ref_get(entry->group);
352 static bool pci_iommuv2_capable(struct pci_dev *pdev)
354 static const int caps[] = {
357 PCI_EXT_CAP_ID_PASID,
361 if (pci_ats_disabled())
364 for (i = 0; i < 3; ++i) {
365 pos = pci_find_ext_capability(pdev, caps[i]);
373 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
375 struct iommu_dev_data *dev_data;
377 dev_data = get_dev_data(&pdev->dev);
379 return dev_data->errata & (1 << erratum) ? true : false;
383 * This function checks if the driver got a valid device from the caller to
384 * avoid dereferencing invalid pointers.
386 static bool check_device(struct device *dev)
390 if (!dev || !dev->dma_mask)
393 devid = get_device_id(dev);
397 /* Out of our scope? */
398 if (devid > amd_iommu_last_bdf)
401 if (amd_iommu_rlookup_table[devid] == NULL)
407 static void init_iommu_group(struct device *dev)
409 struct iommu_group *group;
411 group = iommu_group_get_for_dev(dev);
415 iommu_group_put(group);
418 static int iommu_init_device(struct device *dev)
420 struct iommu_dev_data *dev_data;
421 struct amd_iommu *iommu;
424 if (dev->archdata.iommu)
427 devid = get_device_id(dev);
431 iommu = amd_iommu_rlookup_table[devid];
433 dev_data = find_dev_data(devid);
437 dev_data->alias = get_alias(dev);
439 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
440 struct amd_iommu *iommu;
442 iommu = amd_iommu_rlookup_table[dev_data->devid];
443 dev_data->iommu_v2 = iommu->is_iommu_v2;
446 dev->archdata.iommu = dev_data;
448 iommu_device_link(&iommu->iommu, dev);
453 static void iommu_ignore_device(struct device *dev)
458 devid = get_device_id(dev);
462 alias = get_alias(dev);
464 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
465 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
467 amd_iommu_rlookup_table[devid] = NULL;
468 amd_iommu_rlookup_table[alias] = NULL;
471 static void iommu_uninit_device(struct device *dev)
473 struct iommu_dev_data *dev_data;
474 struct amd_iommu *iommu;
477 devid = get_device_id(dev);
481 iommu = amd_iommu_rlookup_table[devid];
483 dev_data = search_dev_data(devid);
487 if (dev_data->domain)
490 iommu_device_unlink(&iommu->iommu, dev);
492 iommu_group_remove_device(dev);
498 * We keep dev_data around for unplugged devices and reuse it when the
499 * device is re-plugged - not doing so would introduce a ton of races.
503 /****************************************************************************
505 * Interrupt handling functions
507 ****************************************************************************/
509 static void dump_dte_entry(u16 devid)
513 for (i = 0; i < 4; ++i)
514 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
515 amd_iommu_dev_table[devid].data[i]);
518 static void dump_command(unsigned long phys_addr)
520 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
523 for (i = 0; i < 4; ++i)
524 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
527 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
528 u64 address, int flags)
530 struct iommu_dev_data *dev_data = NULL;
531 struct pci_dev *pdev;
533 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
536 dev_data = get_dev_data(&pdev->dev);
538 if (dev_data && __ratelimit(&dev_data->rs)) {
539 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
540 domain_id, address, flags);
541 } else if (printk_ratelimit()) {
542 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
543 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
544 domain_id, address, flags);
551 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
553 struct device *dev = iommu->iommu.dev;
554 int type, devid, pasid, flags, tag;
555 volatile u32 *event = __evt;
560 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
561 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
562 pasid = PPR_PASID(*(u64 *)&event[0]);
563 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
564 address = (u64)(((u64)event[3]) << 32) | event[2];
567 /* Did we hit the erratum? */
568 if (++count == LOOP_TIMEOUT) {
569 pr_err("AMD-Vi: No event written to event log\n");
576 if (type == EVENT_TYPE_IO_FAULT) {
577 amd_iommu_report_page_fault(devid, pasid, address, flags);
580 dev_err(dev, "AMD-Vi: Event logged [");
584 case EVENT_TYPE_ILL_DEV:
585 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
586 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
587 pasid, address, flags);
588 dump_dte_entry(devid);
590 case EVENT_TYPE_DEV_TAB_ERR:
591 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
592 "address=0x%016llx flags=0x%04x]\n",
593 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
596 case EVENT_TYPE_PAGE_TAB_ERR:
597 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
598 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
599 pasid, address, flags);
601 case EVENT_TYPE_ILL_CMD:
602 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
603 dump_command(address);
605 case EVENT_TYPE_CMD_HARD_ERR:
606 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
609 case EVENT_TYPE_IOTLB_INV_TO:
610 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
611 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
614 case EVENT_TYPE_INV_DEV_REQ:
615 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
617 pasid, address, flags);
619 case EVENT_TYPE_INV_PPR_REQ:
620 pasid = ((event[0] >> 16) & 0xFFFF)
621 | ((event[1] << 6) & 0xF0000);
622 tag = event[1] & 0x03FF;
623 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
624 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
625 pasid, address, flags);
628 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
629 event[0], event[1], event[2], event[3]);
632 memset(__evt, 0, 4 * sizeof(u32));
635 static void iommu_poll_events(struct amd_iommu *iommu)
639 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
640 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
642 while (head != tail) {
643 iommu_print_event(iommu, iommu->evt_buf + head);
644 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
647 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
650 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
652 struct amd_iommu_fault fault;
654 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
655 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
659 fault.address = raw[1];
660 fault.pasid = PPR_PASID(raw[0]);
661 fault.device_id = PPR_DEVID(raw[0]);
662 fault.tag = PPR_TAG(raw[0]);
663 fault.flags = PPR_FLAGS(raw[0]);
665 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
668 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
672 if (iommu->ppr_log == NULL)
675 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
676 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
678 while (head != tail) {
683 raw = (u64 *)(iommu->ppr_log + head);
686 * Hardware bug: Interrupt may arrive before the entry is
687 * written to memory. If this happens we need to wait for the
690 for (i = 0; i < LOOP_TIMEOUT; ++i) {
691 if (PPR_REQ_TYPE(raw[0]) != 0)
696 /* Avoid memcpy function-call overhead */
701 * To detect the hardware bug we need to clear the entry
704 raw[0] = raw[1] = 0UL;
706 /* Update head pointer of hardware ring-buffer */
707 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
708 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
710 /* Handle PPR entry */
711 iommu_handle_ppr_entry(iommu, entry);
713 /* Refresh ring-buffer information */
714 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
715 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
719 #ifdef CONFIG_IRQ_REMAP
720 static int (*iommu_ga_log_notifier)(u32);
722 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
724 iommu_ga_log_notifier = notifier;
728 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
730 static void iommu_poll_ga_log(struct amd_iommu *iommu)
732 u32 head, tail, cnt = 0;
734 if (iommu->ga_log == NULL)
737 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
738 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
740 while (head != tail) {
744 raw = (u64 *)(iommu->ga_log + head);
747 /* Avoid memcpy function-call overhead */
750 /* Update head pointer of hardware ring-buffer */
751 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
752 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
754 /* Handle GA entry */
755 switch (GA_REQ_TYPE(log_entry)) {
757 if (!iommu_ga_log_notifier)
760 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
761 __func__, GA_DEVID(log_entry),
764 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
765 pr_err("AMD-Vi: GA log notifier failed.\n");
772 #endif /* CONFIG_IRQ_REMAP */
774 #define AMD_IOMMU_INT_MASK \
775 (MMIO_STATUS_EVT_INT_MASK | \
776 MMIO_STATUS_PPR_INT_MASK | \
777 MMIO_STATUS_GALOG_INT_MASK)
779 irqreturn_t amd_iommu_int_thread(int irq, void *data)
781 struct amd_iommu *iommu = (struct amd_iommu *) data;
782 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
784 while (status & AMD_IOMMU_INT_MASK) {
785 /* Enable EVT and PPR and GA interrupts again */
786 writel(AMD_IOMMU_INT_MASK,
787 iommu->mmio_base + MMIO_STATUS_OFFSET);
789 if (status & MMIO_STATUS_EVT_INT_MASK) {
790 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
791 iommu_poll_events(iommu);
794 if (status & MMIO_STATUS_PPR_INT_MASK) {
795 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
796 iommu_poll_ppr_log(iommu);
799 #ifdef CONFIG_IRQ_REMAP
800 if (status & MMIO_STATUS_GALOG_INT_MASK) {
801 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
802 iommu_poll_ga_log(iommu);
807 * Hardware bug: ERBT1312
808 * When re-enabling interrupt (by writing 1
809 * to clear the bit), the hardware might also try to set
810 * the interrupt bit in the event status register.
811 * In this scenario, the bit will be set, and disable
812 * subsequent interrupts.
814 * Workaround: The IOMMU driver should read back the
815 * status register and check if the interrupt bits are cleared.
816 * If not, driver will need to go through the interrupt handler
817 * again and re-clear the bits
819 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
824 irqreturn_t amd_iommu_int_handler(int irq, void *data)
826 return IRQ_WAKE_THREAD;
829 /****************************************************************************
831 * IOMMU command queuing functions
833 ****************************************************************************/
835 static int wait_on_sem(volatile u64 *sem)
839 while (*sem == 0 && i < LOOP_TIMEOUT) {
844 if (i == LOOP_TIMEOUT) {
845 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
852 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
853 struct iommu_cmd *cmd)
857 target = iommu->cmd_buf + iommu->cmd_buf_tail;
859 iommu->cmd_buf_tail += sizeof(*cmd);
860 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
862 /* Copy command to buffer */
863 memcpy(target, cmd, sizeof(*cmd));
865 /* Tell the IOMMU about it */
866 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
869 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
871 u64 paddr = iommu_virt_to_phys((void *)address);
873 WARN_ON(address & 0x7ULL);
875 memset(cmd, 0, sizeof(*cmd));
876 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
877 cmd->data[1] = upper_32_bits(paddr);
879 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
882 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
884 memset(cmd, 0, sizeof(*cmd));
885 cmd->data[0] = devid;
886 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
889 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
890 size_t size, u16 domid, int pde)
895 pages = iommu_num_pages(address, size, PAGE_SIZE);
900 * If we have to flush more than one page, flush all
901 * TLB entries for this domain
903 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
907 address &= PAGE_MASK;
909 memset(cmd, 0, sizeof(*cmd));
910 cmd->data[1] |= domid;
911 cmd->data[2] = lower_32_bits(address);
912 cmd->data[3] = upper_32_bits(address);
913 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
914 if (s) /* size bit - we flush more than one 4kb page */
915 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
916 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
920 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
921 u64 address, size_t size)
926 pages = iommu_num_pages(address, size, PAGE_SIZE);
931 * If we have to flush more than one page, flush all
932 * TLB entries for this domain
934 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
938 address &= PAGE_MASK;
940 memset(cmd, 0, sizeof(*cmd));
941 cmd->data[0] = devid;
942 cmd->data[0] |= (qdep & 0xff) << 24;
943 cmd->data[1] = devid;
944 cmd->data[2] = lower_32_bits(address);
945 cmd->data[3] = upper_32_bits(address);
946 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
948 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
951 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
952 u64 address, bool size)
954 memset(cmd, 0, sizeof(*cmd));
956 address &= ~(0xfffULL);
958 cmd->data[0] = pasid;
959 cmd->data[1] = domid;
960 cmd->data[2] = lower_32_bits(address);
961 cmd->data[3] = upper_32_bits(address);
962 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
963 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
965 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
966 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
969 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
970 int qdep, u64 address, bool size)
972 memset(cmd, 0, sizeof(*cmd));
974 address &= ~(0xfffULL);
976 cmd->data[0] = devid;
977 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
978 cmd->data[0] |= (qdep & 0xff) << 24;
979 cmd->data[1] = devid;
980 cmd->data[1] |= (pasid & 0xff) << 16;
981 cmd->data[2] = lower_32_bits(address);
982 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
983 cmd->data[3] = upper_32_bits(address);
985 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
986 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
989 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
990 int status, int tag, bool gn)
992 memset(cmd, 0, sizeof(*cmd));
994 cmd->data[0] = devid;
996 cmd->data[1] = pasid;
997 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
999 cmd->data[3] = tag & 0x1ff;
1000 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1002 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1005 static void build_inv_all(struct iommu_cmd *cmd)
1007 memset(cmd, 0, sizeof(*cmd));
1008 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1011 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1013 memset(cmd, 0, sizeof(*cmd));
1014 cmd->data[0] = devid;
1015 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1019 * Writes the command to the IOMMUs command buffer and informs the
1020 * hardware about the new command.
1022 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1023 struct iommu_cmd *cmd,
1026 unsigned int count = 0;
1027 u32 left, next_tail;
1029 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1031 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1034 /* Skip udelay() the first time around */
1036 if (count == LOOP_TIMEOUT) {
1037 pr_err("AMD-Vi: Command buffer timeout\n");
1044 /* Update head and recheck remaining space */
1045 iommu->cmd_buf_head = readl(iommu->mmio_base +
1046 MMIO_CMD_HEAD_OFFSET);
1051 copy_cmd_to_buffer(iommu, cmd);
1053 /* Do we need to make sure all commands are processed? */
1054 iommu->need_sync = sync;
1059 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1060 struct iommu_cmd *cmd,
1063 unsigned long flags;
1066 raw_spin_lock_irqsave(&iommu->lock, flags);
1067 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1068 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1073 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1075 return iommu_queue_command_sync(iommu, cmd, true);
1079 * This function queues a completion wait command into the command
1080 * buffer of an IOMMU
1082 static int iommu_completion_wait(struct amd_iommu *iommu)
1084 struct iommu_cmd cmd;
1085 unsigned long flags;
1088 if (!iommu->need_sync)
1092 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1094 raw_spin_lock_irqsave(&iommu->lock, flags);
1098 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1102 ret = wait_on_sem(&iommu->cmd_sem);
1105 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1110 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1112 struct iommu_cmd cmd;
1114 build_inv_dte(&cmd, devid);
1116 return iommu_queue_command(iommu, &cmd);
1119 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1123 for (devid = 0; devid <= 0xffff; ++devid)
1124 iommu_flush_dte(iommu, devid);
1126 iommu_completion_wait(iommu);
1130 * This function uses heavy locking and may disable irqs for some time. But
1131 * this is no issue because it is only called during resume.
1133 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1137 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1138 struct iommu_cmd cmd;
1139 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1141 iommu_queue_command(iommu, &cmd);
1144 iommu_completion_wait(iommu);
1147 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1149 struct iommu_cmd cmd;
1151 build_inv_all(&cmd);
1153 iommu_queue_command(iommu, &cmd);
1154 iommu_completion_wait(iommu);
1157 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1159 struct iommu_cmd cmd;
1161 build_inv_irt(&cmd, devid);
1163 iommu_queue_command(iommu, &cmd);
1166 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1170 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1171 iommu_flush_irt(iommu, devid);
1173 iommu_completion_wait(iommu);
1176 void iommu_flush_all_caches(struct amd_iommu *iommu)
1178 if (iommu_feature(iommu, FEATURE_IA)) {
1179 amd_iommu_flush_all(iommu);
1181 amd_iommu_flush_dte_all(iommu);
1182 amd_iommu_flush_irt_all(iommu);
1183 amd_iommu_flush_tlb_all(iommu);
1188 * Command send function for flushing on-device TLB
1190 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1191 u64 address, size_t size)
1193 struct amd_iommu *iommu;
1194 struct iommu_cmd cmd;
1197 qdep = dev_data->ats.qdep;
1198 iommu = amd_iommu_rlookup_table[dev_data->devid];
1200 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1202 return iommu_queue_command(iommu, &cmd);
1206 * Command send function for invalidating a device table entry
1208 static int device_flush_dte(struct iommu_dev_data *dev_data)
1210 struct amd_iommu *iommu;
1214 iommu = amd_iommu_rlookup_table[dev_data->devid];
1215 alias = dev_data->alias;
1217 ret = iommu_flush_dte(iommu, dev_data->devid);
1218 if (!ret && alias != dev_data->devid)
1219 ret = iommu_flush_dte(iommu, alias);
1223 if (dev_data->ats.enabled)
1224 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1230 * TLB invalidation function which is called from the mapping functions.
1231 * It invalidates a single PTE if the range to flush is within a single
1232 * page. Otherwise it flushes the whole TLB of the IOMMU.
1234 static void __domain_flush_pages(struct protection_domain *domain,
1235 u64 address, size_t size, int pde)
1237 struct iommu_dev_data *dev_data;
1238 struct iommu_cmd cmd;
1241 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1243 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1244 if (!domain->dev_iommu[i])
1248 * Devices of this domain are behind this IOMMU
1249 * We need a TLB flush
1251 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1254 list_for_each_entry(dev_data, &domain->dev_list, list) {
1256 if (!dev_data->ats.enabled)
1259 ret |= device_flush_iotlb(dev_data, address, size);
1265 static void domain_flush_pages(struct protection_domain *domain,
1266 u64 address, size_t size)
1268 __domain_flush_pages(domain, address, size, 0);
1271 /* Flush the whole IO/TLB for a given protection domain */
1272 static void domain_flush_tlb(struct protection_domain *domain)
1274 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1277 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1278 static void domain_flush_tlb_pde(struct protection_domain *domain)
1280 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1283 static void domain_flush_complete(struct protection_domain *domain)
1287 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1288 if (domain && !domain->dev_iommu[i])
1292 * Devices of this domain are behind this IOMMU
1293 * We need to wait for completion of all commands.
1295 iommu_completion_wait(amd_iommus[i]);
1301 * This function flushes the DTEs for all devices in domain
1303 static void domain_flush_devices(struct protection_domain *domain)
1305 struct iommu_dev_data *dev_data;
1307 list_for_each_entry(dev_data, &domain->dev_list, list)
1308 device_flush_dte(dev_data);
1311 /****************************************************************************
1313 * The functions below are used the create the page table mappings for
1314 * unity mapped regions.
1316 ****************************************************************************/
1319 * This function is used to add another level to an IO page table. Adding
1320 * another level increases the size of the address space by 9 bits to a size up
1323 static bool increase_address_space(struct protection_domain *domain,
1328 if (domain->mode == PAGE_MODE_6_LEVEL)
1329 /* address space already 64 bit large */
1332 pte = (void *)get_zeroed_page(gfp);
1336 *pte = PM_LEVEL_PDE(domain->mode,
1337 iommu_virt_to_phys(domain->pt_root));
1338 domain->pt_root = pte;
1340 domain->updated = true;
1345 static u64 *alloc_pte(struct protection_domain *domain,
1346 unsigned long address,
1347 unsigned long page_size,
1354 BUG_ON(!is_power_of_2(page_size));
1356 while (address > PM_LEVEL_SIZE(domain->mode))
1357 increase_address_space(domain, gfp);
1359 level = domain->mode - 1;
1360 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1361 address = PAGE_SIZE_ALIGN(address, page_size);
1362 end_lvl = PAGE_SIZE_LEVEL(page_size);
1364 while (level > end_lvl) {
1369 if (!IOMMU_PTE_PRESENT(__pte)) {
1370 page = (u64 *)get_zeroed_page(gfp);
1374 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1376 /* pte could have been changed somewhere. */
1377 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1378 free_page((unsigned long)page);
1383 /* No level skipping support yet */
1384 if (PM_PTE_LEVEL(*pte) != level)
1389 pte = IOMMU_PTE_PAGE(*pte);
1391 if (pte_page && level == end_lvl)
1394 pte = &pte[PM_LEVEL_INDEX(level, address)];
1401 * This function checks if there is a PTE for a given dma address. If
1402 * there is one, it returns the pointer to it.
1404 static u64 *fetch_pte(struct protection_domain *domain,
1405 unsigned long address,
1406 unsigned long *page_size)
1413 if (address > PM_LEVEL_SIZE(domain->mode))
1416 level = domain->mode - 1;
1417 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1418 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1423 if (!IOMMU_PTE_PRESENT(*pte))
1427 if (PM_PTE_LEVEL(*pte) == 7 ||
1428 PM_PTE_LEVEL(*pte) == 0)
1431 /* No level skipping support yet */
1432 if (PM_PTE_LEVEL(*pte) != level)
1437 /* Walk to the next level */
1438 pte = IOMMU_PTE_PAGE(*pte);
1439 pte = &pte[PM_LEVEL_INDEX(level, address)];
1440 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1443 if (PM_PTE_LEVEL(*pte) == 0x07) {
1444 unsigned long pte_mask;
1447 * If we have a series of large PTEs, make
1448 * sure to return a pointer to the first one.
1450 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1451 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1452 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1459 * Generic mapping functions. It maps a physical address into a DMA
1460 * address space. It allocates the page table pages if necessary.
1461 * In the future it can be extended to a generic mapping function
1462 * supporting all features of AMD IOMMU page tables like level skipping
1463 * and full 64 bit address spaces.
1465 static int iommu_map_page(struct protection_domain *dom,
1466 unsigned long bus_addr,
1467 unsigned long phys_addr,
1468 unsigned long page_size,
1475 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1476 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1478 if (!(prot & IOMMU_PROT_MASK))
1481 count = PAGE_SIZE_PTE_COUNT(page_size);
1482 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1487 for (i = 0; i < count; ++i)
1488 if (IOMMU_PTE_PRESENT(pte[i]))
1492 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1493 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1495 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1497 if (prot & IOMMU_PROT_IR)
1498 __pte |= IOMMU_PTE_IR;
1499 if (prot & IOMMU_PROT_IW)
1500 __pte |= IOMMU_PTE_IW;
1502 for (i = 0; i < count; ++i)
1510 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1511 unsigned long bus_addr,
1512 unsigned long page_size)
1514 unsigned long long unmapped;
1515 unsigned long unmap_size;
1518 BUG_ON(!is_power_of_2(page_size));
1522 while (unmapped < page_size) {
1524 pte = fetch_pte(dom, bus_addr, &unmap_size);
1529 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1530 for (i = 0; i < count; i++)
1534 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1535 unmapped += unmap_size;
1538 BUG_ON(unmapped && !is_power_of_2(unmapped));
1543 /****************************************************************************
1545 * The next functions belong to the address allocator for the dma_ops
1546 * interface functions.
1548 ****************************************************************************/
1551 static unsigned long dma_ops_alloc_iova(struct device *dev,
1552 struct dma_ops_domain *dma_dom,
1553 unsigned int pages, u64 dma_mask)
1555 unsigned long pfn = 0;
1557 pages = __roundup_pow_of_two(pages);
1559 if (dma_mask > DMA_BIT_MASK(32))
1560 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1561 IOVA_PFN(DMA_BIT_MASK(32)), false);
1564 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1565 IOVA_PFN(dma_mask), true);
1567 return (pfn << PAGE_SHIFT);
1570 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1571 unsigned long address,
1574 pages = __roundup_pow_of_two(pages);
1575 address >>= PAGE_SHIFT;
1577 free_iova_fast(&dma_dom->iovad, address, pages);
1580 /****************************************************************************
1582 * The next functions belong to the domain allocation. A domain is
1583 * allocated for every IOMMU as the default domain. If device isolation
1584 * is enabled, every device get its own domain. The most important thing
1585 * about domains is the page table mapping the DMA address space they
1588 ****************************************************************************/
1591 * This function adds a protection domain to the global protection domain list
1593 static void add_domain_to_list(struct protection_domain *domain)
1595 unsigned long flags;
1597 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1598 list_add(&domain->list, &amd_iommu_pd_list);
1599 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1603 * This function removes a protection domain to the global
1604 * protection domain list
1606 static void del_domain_from_list(struct protection_domain *domain)
1608 unsigned long flags;
1610 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1611 list_del(&domain->list);
1612 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1615 static u16 domain_id_alloc(void)
1619 spin_lock(&pd_bitmap_lock);
1620 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1622 if (id > 0 && id < MAX_DOMAIN_ID)
1623 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1626 spin_unlock(&pd_bitmap_lock);
1631 static void domain_id_free(int id)
1633 spin_lock(&pd_bitmap_lock);
1634 if (id > 0 && id < MAX_DOMAIN_ID)
1635 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1636 spin_unlock(&pd_bitmap_lock);
1639 #define DEFINE_FREE_PT_FN(LVL, FN) \
1640 static void free_pt_##LVL (unsigned long __pt) \
1648 for (i = 0; i < 512; ++i) { \
1649 /* PTE present? */ \
1650 if (!IOMMU_PTE_PRESENT(pt[i])) \
1654 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1655 PM_PTE_LEVEL(pt[i]) == 7) \
1658 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1661 free_page((unsigned long)pt); \
1664 DEFINE_FREE_PT_FN(l2, free_page)
1665 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1666 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1667 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1668 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1670 static void free_pagetable(struct protection_domain *domain)
1672 unsigned long root = (unsigned long)domain->pt_root;
1674 switch (domain->mode) {
1675 case PAGE_MODE_NONE:
1677 case PAGE_MODE_1_LEVEL:
1680 case PAGE_MODE_2_LEVEL:
1683 case PAGE_MODE_3_LEVEL:
1686 case PAGE_MODE_4_LEVEL:
1689 case PAGE_MODE_5_LEVEL:
1692 case PAGE_MODE_6_LEVEL:
1700 static void free_gcr3_tbl_level1(u64 *tbl)
1705 for (i = 0; i < 512; ++i) {
1706 if (!(tbl[i] & GCR3_VALID))
1709 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1711 free_page((unsigned long)ptr);
1715 static void free_gcr3_tbl_level2(u64 *tbl)
1720 for (i = 0; i < 512; ++i) {
1721 if (!(tbl[i] & GCR3_VALID))
1724 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1726 free_gcr3_tbl_level1(ptr);
1730 static void free_gcr3_table(struct protection_domain *domain)
1732 if (domain->glx == 2)
1733 free_gcr3_tbl_level2(domain->gcr3_tbl);
1734 else if (domain->glx == 1)
1735 free_gcr3_tbl_level1(domain->gcr3_tbl);
1737 BUG_ON(domain->glx != 0);
1739 free_page((unsigned long)domain->gcr3_tbl);
1742 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1744 domain_flush_tlb(&dom->domain);
1745 domain_flush_complete(&dom->domain);
1748 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1750 struct dma_ops_domain *dom;
1752 dom = container_of(iovad, struct dma_ops_domain, iovad);
1754 dma_ops_domain_flush_tlb(dom);
1758 * Free a domain, only used if something went wrong in the
1759 * allocation path and we need to free an already allocated page table
1761 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1766 del_domain_from_list(&dom->domain);
1768 put_iova_domain(&dom->iovad);
1770 free_pagetable(&dom->domain);
1773 domain_id_free(dom->domain.id);
1779 * Allocates a new protection domain usable for the dma_ops functions.
1780 * It also initializes the page table and the address allocator data
1781 * structures required for the dma_ops interface
1783 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1785 struct dma_ops_domain *dma_dom;
1787 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1791 if (protection_domain_init(&dma_dom->domain))
1794 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1795 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1796 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1797 if (!dma_dom->domain.pt_root)
1800 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1802 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1805 /* Initialize reserved ranges */
1806 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1808 add_domain_to_list(&dma_dom->domain);
1813 dma_ops_domain_free(dma_dom);
1819 * little helper function to check whether a given protection domain is a
1822 static bool dma_ops_domain(struct protection_domain *domain)
1824 return domain->flags & PD_DMA_OPS_MASK;
1827 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1833 if (domain->mode != PAGE_MODE_NONE)
1834 pte_root = iommu_virt_to_phys(domain->pt_root);
1836 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1837 << DEV_ENTRY_MODE_SHIFT;
1838 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1840 flags = amd_iommu_dev_table[devid].data[1];
1843 flags |= DTE_FLAG_IOTLB;
1846 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1848 if (iommu_feature(iommu, FEATURE_EPHSUP))
1849 pte_root |= 1ULL << DEV_ENTRY_PPR;
1852 if (domain->flags & PD_IOMMUV2_MASK) {
1853 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1854 u64 glx = domain->glx;
1857 pte_root |= DTE_FLAG_GV;
1858 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1860 /* First mask out possible old values for GCR3 table */
1861 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1864 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1867 /* Encode GCR3 table into DTE */
1868 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1871 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1874 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1878 flags &= ~DEV_DOMID_MASK;
1879 flags |= domain->id;
1881 amd_iommu_dev_table[devid].data[1] = flags;
1882 amd_iommu_dev_table[devid].data[0] = pte_root;
1885 static void clear_dte_entry(u16 devid)
1887 /* remove entry from the device table seen by the hardware */
1888 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1889 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1891 amd_iommu_apply_erratum_63(devid);
1894 static void do_attach(struct iommu_dev_data *dev_data,
1895 struct protection_domain *domain)
1897 struct amd_iommu *iommu;
1901 iommu = amd_iommu_rlookup_table[dev_data->devid];
1902 alias = dev_data->alias;
1903 ats = dev_data->ats.enabled;
1905 /* Update data structures */
1906 dev_data->domain = domain;
1907 list_add(&dev_data->list, &domain->dev_list);
1909 /* Do reference counting */
1910 domain->dev_iommu[iommu->index] += 1;
1911 domain->dev_cnt += 1;
1913 /* Update device table */
1914 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1915 if (alias != dev_data->devid)
1916 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1918 device_flush_dte(dev_data);
1921 static void do_detach(struct iommu_dev_data *dev_data)
1923 struct amd_iommu *iommu;
1926 iommu = amd_iommu_rlookup_table[dev_data->devid];
1927 alias = dev_data->alias;
1929 /* decrease reference counters */
1930 dev_data->domain->dev_iommu[iommu->index] -= 1;
1931 dev_data->domain->dev_cnt -= 1;
1933 /* Update data structures */
1934 dev_data->domain = NULL;
1935 list_del(&dev_data->list);
1936 clear_dte_entry(dev_data->devid);
1937 if (alias != dev_data->devid)
1938 clear_dte_entry(alias);
1940 /* Flush the DTE entry */
1941 device_flush_dte(dev_data);
1945 * If a device is not yet associated with a domain, this function makes the
1946 * device visible in the domain
1948 static int __attach_device(struct iommu_dev_data *dev_data,
1949 struct protection_domain *domain)
1954 spin_lock(&domain->lock);
1957 if (dev_data->domain != NULL)
1960 /* Attach alias group root */
1961 do_attach(dev_data, domain);
1968 spin_unlock(&domain->lock);
1974 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1976 pci_disable_ats(pdev);
1977 pci_disable_pri(pdev);
1978 pci_disable_pasid(pdev);
1981 /* FIXME: Change generic reset-function to do the same */
1982 static int pri_reset_while_enabled(struct pci_dev *pdev)
1987 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1991 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1992 control |= PCI_PRI_CTRL_RESET;
1993 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1998 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2003 /* FIXME: Hardcode number of outstanding requests for now */
2005 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2007 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2009 /* Only allow access to user-accessible pages */
2010 ret = pci_enable_pasid(pdev, 0);
2014 /* First reset the PRI state of the device */
2015 ret = pci_reset_pri(pdev);
2020 ret = pci_enable_pri(pdev, reqs);
2025 ret = pri_reset_while_enabled(pdev);
2030 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2037 pci_disable_pri(pdev);
2038 pci_disable_pasid(pdev);
2043 /* FIXME: Move this to PCI code */
2044 #define PCI_PRI_TLP_OFF (1 << 15)
2046 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2051 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2055 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2057 return (status & PCI_PRI_TLP_OFF) ? true : false;
2061 * If a device is not yet associated with a domain, this function makes the
2062 * device visible in the domain
2064 static int attach_device(struct device *dev,
2065 struct protection_domain *domain)
2067 struct pci_dev *pdev;
2068 struct iommu_dev_data *dev_data;
2069 unsigned long flags;
2072 dev_data = get_dev_data(dev);
2074 if (!dev_is_pci(dev))
2075 goto skip_ats_check;
2077 pdev = to_pci_dev(dev);
2078 if (domain->flags & PD_IOMMUV2_MASK) {
2079 if (!dev_data->passthrough)
2082 if (dev_data->iommu_v2) {
2083 if (pdev_iommuv2_enable(pdev) != 0)
2086 dev_data->ats.enabled = true;
2087 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2088 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2090 } else if (amd_iommu_iotlb_sup &&
2091 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2092 dev_data->ats.enabled = true;
2093 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2097 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2098 ret = __attach_device(dev_data, domain);
2099 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2102 * We might boot into a crash-kernel here. The crashed kernel
2103 * left the caches in the IOMMU dirty. So we have to flush
2104 * here to evict all dirty stuff.
2106 domain_flush_tlb_pde(domain);
2112 * Removes a device from a protection domain (unlocked)
2114 static void __detach_device(struct iommu_dev_data *dev_data)
2116 struct protection_domain *domain;
2118 domain = dev_data->domain;
2120 spin_lock(&domain->lock);
2122 do_detach(dev_data);
2124 spin_unlock(&domain->lock);
2128 * Removes a device from a protection domain (with devtable_lock held)
2130 static void detach_device(struct device *dev)
2132 struct protection_domain *domain;
2133 struct iommu_dev_data *dev_data;
2134 unsigned long flags;
2136 dev_data = get_dev_data(dev);
2137 domain = dev_data->domain;
2140 * First check if the device is still attached. It might already
2141 * be detached from its domain because the generic
2142 * iommu_detach_group code detached it and we try again here in
2143 * our alias handling.
2145 if (WARN_ON(!dev_data->domain))
2148 /* lock device table */
2149 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2150 __detach_device(dev_data);
2151 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2153 if (!dev_is_pci(dev))
2156 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2157 pdev_iommuv2_disable(to_pci_dev(dev));
2158 else if (dev_data->ats.enabled)
2159 pci_disable_ats(to_pci_dev(dev));
2161 dev_data->ats.enabled = false;
2164 static int amd_iommu_add_device(struct device *dev)
2166 struct iommu_dev_data *dev_data;
2167 struct iommu_domain *domain;
2168 struct amd_iommu *iommu;
2171 if (!check_device(dev) || get_dev_data(dev))
2174 devid = get_device_id(dev);
2178 iommu = amd_iommu_rlookup_table[devid];
2180 ret = iommu_init_device(dev);
2182 if (ret != -ENOTSUPP)
2183 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2186 iommu_ignore_device(dev);
2187 dev->dma_ops = NULL;
2190 init_iommu_group(dev);
2192 dev_data = get_dev_data(dev);
2196 if (iommu_pass_through || dev_data->iommu_v2)
2197 iommu_request_dm_for_dev(dev);
2199 /* Domains are initialized for this device - have a look what we ended up with */
2200 domain = iommu_get_domain_for_dev(dev);
2201 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2202 dev_data->passthrough = true;
2204 dev->dma_ops = &amd_iommu_dma_ops;
2207 iommu_completion_wait(iommu);
2212 static void amd_iommu_remove_device(struct device *dev)
2214 struct amd_iommu *iommu;
2217 if (!check_device(dev))
2220 devid = get_device_id(dev);
2224 iommu = amd_iommu_rlookup_table[devid];
2226 iommu_uninit_device(dev);
2227 iommu_completion_wait(iommu);
2230 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2232 if (dev_is_pci(dev))
2233 return pci_device_group(dev);
2235 return acpihid_device_group(dev);
2238 /*****************************************************************************
2240 * The next functions belong to the dma_ops mapping/unmapping code.
2242 *****************************************************************************/
2245 * In the dma_ops path we only have the struct device. This function
2246 * finds the corresponding IOMMU, the protection domain and the
2247 * requestor id for a given device.
2248 * If the device is not yet associated with a domain this is also done
2251 static struct protection_domain *get_domain(struct device *dev)
2253 struct protection_domain *domain;
2254 struct iommu_domain *io_domain;
2256 if (!check_device(dev))
2257 return ERR_PTR(-EINVAL);
2259 domain = get_dev_data(dev)->domain;
2260 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2261 get_dev_data(dev)->defer_attach = false;
2262 io_domain = iommu_get_domain_for_dev(dev);
2263 domain = to_pdomain(io_domain);
2264 attach_device(dev, domain);
2267 return ERR_PTR(-EBUSY);
2269 if (!dma_ops_domain(domain))
2270 return ERR_PTR(-EBUSY);
2275 static void update_device_table(struct protection_domain *domain)
2277 struct iommu_dev_data *dev_data;
2279 list_for_each_entry(dev_data, &domain->dev_list, list) {
2280 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2281 dev_data->iommu_v2);
2283 if (dev_data->devid == dev_data->alias)
2286 /* There is an alias, update device table entry for it */
2287 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2288 dev_data->iommu_v2);
2292 static void update_domain(struct protection_domain *domain)
2294 if (!domain->updated)
2297 update_device_table(domain);
2299 domain_flush_devices(domain);
2300 domain_flush_tlb_pde(domain);
2302 domain->updated = false;
2305 static int dir2prot(enum dma_data_direction direction)
2307 if (direction == DMA_TO_DEVICE)
2308 return IOMMU_PROT_IR;
2309 else if (direction == DMA_FROM_DEVICE)
2310 return IOMMU_PROT_IW;
2311 else if (direction == DMA_BIDIRECTIONAL)
2312 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2318 * This function contains common code for mapping of a physically
2319 * contiguous memory region into DMA address space. It is used by all
2320 * mapping functions provided with this IOMMU driver.
2321 * Must be called with the domain lock held.
2323 static dma_addr_t __map_single(struct device *dev,
2324 struct dma_ops_domain *dma_dom,
2327 enum dma_data_direction direction,
2330 dma_addr_t offset = paddr & ~PAGE_MASK;
2331 dma_addr_t address, start, ret;
2336 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2339 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2343 prot = dir2prot(direction);
2346 for (i = 0; i < pages; ++i) {
2347 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2348 PAGE_SIZE, prot, GFP_ATOMIC);
2357 if (unlikely(amd_iommu_np_cache)) {
2358 domain_flush_pages(&dma_dom->domain, address, size);
2359 domain_flush_complete(&dma_dom->domain);
2367 for (--i; i >= 0; --i) {
2369 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2372 domain_flush_tlb(&dma_dom->domain);
2373 domain_flush_complete(&dma_dom->domain);
2375 dma_ops_free_iova(dma_dom, address, pages);
2377 return DMA_MAPPING_ERROR;
2381 * Does the reverse of the __map_single function. Must be called with
2382 * the domain lock held too
2384 static void __unmap_single(struct dma_ops_domain *dma_dom,
2385 dma_addr_t dma_addr,
2389 dma_addr_t i, start;
2392 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2393 dma_addr &= PAGE_MASK;
2396 for (i = 0; i < pages; ++i) {
2397 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2401 if (amd_iommu_unmap_flush) {
2402 domain_flush_tlb(&dma_dom->domain);
2403 domain_flush_complete(&dma_dom->domain);
2404 dma_ops_free_iova(dma_dom, dma_addr, pages);
2406 pages = __roundup_pow_of_two(pages);
2407 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2412 * The exported map_single function for dma_ops.
2414 static dma_addr_t map_page(struct device *dev, struct page *page,
2415 unsigned long offset, size_t size,
2416 enum dma_data_direction dir,
2417 unsigned long attrs)
2419 phys_addr_t paddr = page_to_phys(page) + offset;
2420 struct protection_domain *domain;
2421 struct dma_ops_domain *dma_dom;
2424 domain = get_domain(dev);
2425 if (PTR_ERR(domain) == -EINVAL)
2426 return (dma_addr_t)paddr;
2427 else if (IS_ERR(domain))
2428 return DMA_MAPPING_ERROR;
2430 dma_mask = *dev->dma_mask;
2431 dma_dom = to_dma_ops_domain(domain);
2433 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2437 * The exported unmap_single function for dma_ops.
2439 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2440 enum dma_data_direction dir, unsigned long attrs)
2442 struct protection_domain *domain;
2443 struct dma_ops_domain *dma_dom;
2445 domain = get_domain(dev);
2449 dma_dom = to_dma_ops_domain(domain);
2451 __unmap_single(dma_dom, dma_addr, size, dir);
2454 static int sg_num_pages(struct device *dev,
2455 struct scatterlist *sglist,
2458 unsigned long mask, boundary_size;
2459 struct scatterlist *s;
2462 mask = dma_get_seg_boundary(dev);
2463 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2464 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2466 for_each_sg(sglist, s, nelems, i) {
2469 s->dma_address = npages << PAGE_SHIFT;
2470 p = npages % boundary_size;
2471 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2472 if (p + n > boundary_size)
2473 npages += boundary_size - p;
2481 * The exported map_sg function for dma_ops (handles scatter-gather
2484 static int map_sg(struct device *dev, struct scatterlist *sglist,
2485 int nelems, enum dma_data_direction direction,
2486 unsigned long attrs)
2488 int mapped_pages = 0, npages = 0, prot = 0, i;
2489 struct protection_domain *domain;
2490 struct dma_ops_domain *dma_dom;
2491 struct scatterlist *s;
2492 unsigned long address;
2495 domain = get_domain(dev);
2499 dma_dom = to_dma_ops_domain(domain);
2500 dma_mask = *dev->dma_mask;
2502 npages = sg_num_pages(dev, sglist, nelems);
2504 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2505 if (address == DMA_MAPPING_ERROR)
2508 prot = dir2prot(direction);
2510 /* Map all sg entries */
2511 for_each_sg(sglist, s, nelems, i) {
2512 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2514 for (j = 0; j < pages; ++j) {
2515 unsigned long bus_addr, phys_addr;
2518 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2519 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2520 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2528 /* Everything is mapped - write the right values into s->dma_address */
2529 for_each_sg(sglist, s, nelems, i) {
2530 s->dma_address += address + s->offset;
2531 s->dma_length = s->length;
2537 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2538 dev_name(dev), npages);
2540 for_each_sg(sglist, s, nelems, i) {
2541 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2543 for (j = 0; j < pages; ++j) {
2544 unsigned long bus_addr;
2546 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2547 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2555 free_iova_fast(&dma_dom->iovad, address, npages);
2562 * The exported map_sg function for dma_ops (handles scatter-gather
2565 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2566 int nelems, enum dma_data_direction dir,
2567 unsigned long attrs)
2569 struct protection_domain *domain;
2570 struct dma_ops_domain *dma_dom;
2571 unsigned long startaddr;
2574 domain = get_domain(dev);
2578 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2579 dma_dom = to_dma_ops_domain(domain);
2580 npages = sg_num_pages(dev, sglist, nelems);
2582 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2586 * The exported alloc_coherent function for dma_ops.
2588 static void *alloc_coherent(struct device *dev, size_t size,
2589 dma_addr_t *dma_addr, gfp_t flag,
2590 unsigned long attrs)
2592 u64 dma_mask = dev->coherent_dma_mask;
2593 struct protection_domain *domain;
2594 struct dma_ops_domain *dma_dom;
2597 domain = get_domain(dev);
2598 if (PTR_ERR(domain) == -EINVAL) {
2599 page = alloc_pages(flag, get_order(size));
2600 *dma_addr = page_to_phys(page);
2601 return page_address(page);
2602 } else if (IS_ERR(domain))
2605 dma_dom = to_dma_ops_domain(domain);
2606 size = PAGE_ALIGN(size);
2607 dma_mask = dev->coherent_dma_mask;
2608 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2611 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2613 if (!gfpflags_allow_blocking(flag))
2616 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2617 get_order(size), flag & __GFP_NOWARN);
2623 dma_mask = *dev->dma_mask;
2625 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2626 size, DMA_BIDIRECTIONAL, dma_mask);
2628 if (*dma_addr == DMA_MAPPING_ERROR)
2631 return page_address(page);
2635 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2636 __free_pages(page, get_order(size));
2642 * The exported free_coherent function for dma_ops.
2644 static void free_coherent(struct device *dev, size_t size,
2645 void *virt_addr, dma_addr_t dma_addr,
2646 unsigned long attrs)
2648 struct protection_domain *domain;
2649 struct dma_ops_domain *dma_dom;
2652 page = virt_to_page(virt_addr);
2653 size = PAGE_ALIGN(size);
2655 domain = get_domain(dev);
2659 dma_dom = to_dma_ops_domain(domain);
2661 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2664 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2665 __free_pages(page, get_order(size));
2669 * This function is called by the DMA layer to find out if we can handle a
2670 * particular device. It is part of the dma_ops.
2672 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2674 if (!dma_direct_supported(dev, mask))
2676 return check_device(dev);
2679 static const struct dma_map_ops amd_iommu_dma_ops = {
2680 .alloc = alloc_coherent,
2681 .free = free_coherent,
2682 .map_page = map_page,
2683 .unmap_page = unmap_page,
2685 .unmap_sg = unmap_sg,
2686 .dma_supported = amd_iommu_dma_supported,
2689 static int init_reserved_iova_ranges(void)
2691 struct pci_dev *pdev = NULL;
2694 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2696 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2697 &reserved_rbtree_key);
2699 /* MSI memory range */
2700 val = reserve_iova(&reserved_iova_ranges,
2701 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2703 pr_err("Reserving MSI range failed\n");
2707 /* HT memory range */
2708 val = reserve_iova(&reserved_iova_ranges,
2709 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2711 pr_err("Reserving HT range failed\n");
2716 * Memory used for PCI resources
2717 * FIXME: Check whether we can reserve the PCI-hole completly
2719 for_each_pci_dev(pdev) {
2722 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2723 struct resource *r = &pdev->resource[i];
2725 if (!(r->flags & IORESOURCE_MEM))
2728 val = reserve_iova(&reserved_iova_ranges,
2732 pr_err("Reserve pci-resource range failed\n");
2741 int __init amd_iommu_init_api(void)
2745 ret = iova_cache_get();
2749 ret = init_reserved_iova_ranges();
2753 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2756 #ifdef CONFIG_ARM_AMBA
2757 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2761 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2768 int __init amd_iommu_init_dma_ops(void)
2770 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2773 if (amd_iommu_unmap_flush)
2774 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2776 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2782 /*****************************************************************************
2784 * The following functions belong to the exported interface of AMD IOMMU
2786 * This interface allows access to lower level functions of the IOMMU
2787 * like protection domain handling and assignement of devices to domains
2788 * which is not possible with the dma_ops interface.
2790 *****************************************************************************/
2792 static void cleanup_domain(struct protection_domain *domain)
2794 struct iommu_dev_data *entry;
2795 unsigned long flags;
2797 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2799 while (!list_empty(&domain->dev_list)) {
2800 entry = list_first_entry(&domain->dev_list,
2801 struct iommu_dev_data, list);
2802 BUG_ON(!entry->domain);
2803 __detach_device(entry);
2806 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2809 static void protection_domain_free(struct protection_domain *domain)
2814 del_domain_from_list(domain);
2817 domain_id_free(domain->id);
2822 static int protection_domain_init(struct protection_domain *domain)
2824 spin_lock_init(&domain->lock);
2825 mutex_init(&domain->api_lock);
2826 domain->id = domain_id_alloc();
2829 INIT_LIST_HEAD(&domain->dev_list);
2834 static struct protection_domain *protection_domain_alloc(void)
2836 struct protection_domain *domain;
2838 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2842 if (protection_domain_init(domain))
2845 add_domain_to_list(domain);
2855 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2857 struct protection_domain *pdomain;
2858 struct dma_ops_domain *dma_domain;
2861 case IOMMU_DOMAIN_UNMANAGED:
2862 pdomain = protection_domain_alloc();
2866 pdomain->mode = PAGE_MODE_3_LEVEL;
2867 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2868 if (!pdomain->pt_root) {
2869 protection_domain_free(pdomain);
2873 pdomain->domain.geometry.aperture_start = 0;
2874 pdomain->domain.geometry.aperture_end = ~0ULL;
2875 pdomain->domain.geometry.force_aperture = true;
2878 case IOMMU_DOMAIN_DMA:
2879 dma_domain = dma_ops_domain_alloc();
2881 pr_err("AMD-Vi: Failed to allocate\n");
2884 pdomain = &dma_domain->domain;
2886 case IOMMU_DOMAIN_IDENTITY:
2887 pdomain = protection_domain_alloc();
2891 pdomain->mode = PAGE_MODE_NONE;
2897 return &pdomain->domain;
2900 static void amd_iommu_domain_free(struct iommu_domain *dom)
2902 struct protection_domain *domain;
2903 struct dma_ops_domain *dma_dom;
2905 domain = to_pdomain(dom);
2907 if (domain->dev_cnt > 0)
2908 cleanup_domain(domain);
2910 BUG_ON(domain->dev_cnt != 0);
2915 switch (dom->type) {
2916 case IOMMU_DOMAIN_DMA:
2917 /* Now release the domain */
2918 dma_dom = to_dma_ops_domain(domain);
2919 dma_ops_domain_free(dma_dom);
2922 if (domain->mode != PAGE_MODE_NONE)
2923 free_pagetable(domain);
2925 if (domain->flags & PD_IOMMUV2_MASK)
2926 free_gcr3_table(domain);
2928 protection_domain_free(domain);
2933 static void amd_iommu_detach_device(struct iommu_domain *dom,
2936 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2937 struct amd_iommu *iommu;
2940 if (!check_device(dev))
2943 devid = get_device_id(dev);
2947 if (dev_data->domain != NULL)
2950 iommu = amd_iommu_rlookup_table[devid];
2954 #ifdef CONFIG_IRQ_REMAP
2955 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2956 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2957 dev_data->use_vapic = 0;
2960 iommu_completion_wait(iommu);
2963 static int amd_iommu_attach_device(struct iommu_domain *dom,
2966 struct protection_domain *domain = to_pdomain(dom);
2967 struct iommu_dev_data *dev_data;
2968 struct amd_iommu *iommu;
2971 if (!check_device(dev))
2974 dev_data = dev->archdata.iommu;
2976 iommu = amd_iommu_rlookup_table[dev_data->devid];
2980 if (dev_data->domain)
2983 ret = attach_device(dev, domain);
2985 #ifdef CONFIG_IRQ_REMAP
2986 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2987 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2988 dev_data->use_vapic = 1;
2990 dev_data->use_vapic = 0;
2994 iommu_completion_wait(iommu);
2999 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3000 phys_addr_t paddr, size_t page_size, int iommu_prot)
3002 struct protection_domain *domain = to_pdomain(dom);
3006 if (domain->mode == PAGE_MODE_NONE)
3009 if (iommu_prot & IOMMU_READ)
3010 prot |= IOMMU_PROT_IR;
3011 if (iommu_prot & IOMMU_WRITE)
3012 prot |= IOMMU_PROT_IW;
3014 mutex_lock(&domain->api_lock);
3015 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3016 mutex_unlock(&domain->api_lock);
3021 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3024 struct protection_domain *domain = to_pdomain(dom);
3027 if (domain->mode == PAGE_MODE_NONE)
3030 mutex_lock(&domain->api_lock);
3031 unmap_size = iommu_unmap_page(domain, iova, page_size);
3032 mutex_unlock(&domain->api_lock);
3037 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3040 struct protection_domain *domain = to_pdomain(dom);
3041 unsigned long offset_mask, pte_pgsize;
3044 if (domain->mode == PAGE_MODE_NONE)
3047 pte = fetch_pte(domain, iova, &pte_pgsize);
3049 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3052 offset_mask = pte_pgsize - 1;
3053 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3055 return (__pte & ~offset_mask) | (iova & offset_mask);
3058 static bool amd_iommu_capable(enum iommu_cap cap)
3061 case IOMMU_CAP_CACHE_COHERENCY:
3063 case IOMMU_CAP_INTR_REMAP:
3064 return (irq_remapping_enabled == 1);
3065 case IOMMU_CAP_NOEXEC:
3074 static void amd_iommu_get_resv_regions(struct device *dev,
3075 struct list_head *head)
3077 struct iommu_resv_region *region;
3078 struct unity_map_entry *entry;
3081 devid = get_device_id(dev);
3085 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3089 if (devid < entry->devid_start || devid > entry->devid_end)
3092 length = entry->address_end - entry->address_start;
3093 if (entry->prot & IOMMU_PROT_IR)
3095 if (entry->prot & IOMMU_PROT_IW)
3096 prot |= IOMMU_WRITE;
3098 region = iommu_alloc_resv_region(entry->address_start,
3102 pr_err("Out of memory allocating dm-regions for %s\n",
3106 list_add_tail(®ion->list, head);
3109 region = iommu_alloc_resv_region(MSI_RANGE_START,
3110 MSI_RANGE_END - MSI_RANGE_START + 1,
3114 list_add_tail(®ion->list, head);
3116 region = iommu_alloc_resv_region(HT_RANGE_START,
3117 HT_RANGE_END - HT_RANGE_START + 1,
3118 0, IOMMU_RESV_RESERVED);
3121 list_add_tail(®ion->list, head);
3124 static void amd_iommu_put_resv_regions(struct device *dev,
3125 struct list_head *head)
3127 struct iommu_resv_region *entry, *next;
3129 list_for_each_entry_safe(entry, next, head, list)
3133 static void amd_iommu_apply_resv_region(struct device *dev,
3134 struct iommu_domain *domain,
3135 struct iommu_resv_region *region)
3137 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3138 unsigned long start, end;
3140 start = IOVA_PFN(region->start);
3141 end = IOVA_PFN(region->start + region->length - 1);
3143 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3146 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3149 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3150 return dev_data->defer_attach;
3153 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3155 struct protection_domain *dom = to_pdomain(domain);
3157 domain_flush_tlb_pde(dom);
3158 domain_flush_complete(dom);
3161 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3162 unsigned long iova, size_t size)
3166 const struct iommu_ops amd_iommu_ops = {
3167 .capable = amd_iommu_capable,
3168 .domain_alloc = amd_iommu_domain_alloc,
3169 .domain_free = amd_iommu_domain_free,
3170 .attach_dev = amd_iommu_attach_device,
3171 .detach_dev = amd_iommu_detach_device,
3172 .map = amd_iommu_map,
3173 .unmap = amd_iommu_unmap,
3174 .iova_to_phys = amd_iommu_iova_to_phys,
3175 .add_device = amd_iommu_add_device,
3176 .remove_device = amd_iommu_remove_device,
3177 .device_group = amd_iommu_device_group,
3178 .get_resv_regions = amd_iommu_get_resv_regions,
3179 .put_resv_regions = amd_iommu_put_resv_regions,
3180 .apply_resv_region = amd_iommu_apply_resv_region,
3181 .is_attach_deferred = amd_iommu_is_attach_deferred,
3182 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3183 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3184 .iotlb_range_add = amd_iommu_iotlb_range_add,
3185 .iotlb_sync = amd_iommu_flush_iotlb_all,
3188 /*****************************************************************************
3190 * The next functions do a basic initialization of IOMMU for pass through
3193 * In passthrough mode the IOMMU is initialized and enabled but not used for
3194 * DMA-API translation.
3196 *****************************************************************************/
3198 /* IOMMUv2 specific functions */
3199 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3201 return atomic_notifier_chain_register(&ppr_notifier, nb);
3203 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3205 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3207 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3209 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3211 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3213 struct protection_domain *domain = to_pdomain(dom);
3214 unsigned long flags;
3216 spin_lock_irqsave(&domain->lock, flags);
3218 /* Update data structure */
3219 domain->mode = PAGE_MODE_NONE;
3220 domain->updated = true;
3222 /* Make changes visible to IOMMUs */
3223 update_domain(domain);
3225 /* Page-table is not visible to IOMMU anymore, so free it */
3226 free_pagetable(domain);
3228 spin_unlock_irqrestore(&domain->lock, flags);
3230 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3232 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3234 struct protection_domain *domain = to_pdomain(dom);
3235 unsigned long flags;
3238 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3241 /* Number of GCR3 table levels required */
3242 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3245 if (levels > amd_iommu_max_glx_val)
3248 spin_lock_irqsave(&domain->lock, flags);
3251 * Save us all sanity checks whether devices already in the
3252 * domain support IOMMUv2. Just force that the domain has no
3253 * devices attached when it is switched into IOMMUv2 mode.
3256 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3260 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3261 if (domain->gcr3_tbl == NULL)
3264 domain->glx = levels;
3265 domain->flags |= PD_IOMMUV2_MASK;
3266 domain->updated = true;
3268 update_domain(domain);
3273 spin_unlock_irqrestore(&domain->lock, flags);
3277 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3279 static int __flush_pasid(struct protection_domain *domain, int pasid,
3280 u64 address, bool size)
3282 struct iommu_dev_data *dev_data;
3283 struct iommu_cmd cmd;
3286 if (!(domain->flags & PD_IOMMUV2_MASK))
3289 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3292 * IOMMU TLB needs to be flushed before Device TLB to
3293 * prevent device TLB refill from IOMMU TLB
3295 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3296 if (domain->dev_iommu[i] == 0)
3299 ret = iommu_queue_command(amd_iommus[i], &cmd);
3304 /* Wait until IOMMU TLB flushes are complete */
3305 domain_flush_complete(domain);
3307 /* Now flush device TLBs */
3308 list_for_each_entry(dev_data, &domain->dev_list, list) {
3309 struct amd_iommu *iommu;
3313 There might be non-IOMMUv2 capable devices in an IOMMUv2
3316 if (!dev_data->ats.enabled)
3319 qdep = dev_data->ats.qdep;
3320 iommu = amd_iommu_rlookup_table[dev_data->devid];
3322 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3323 qdep, address, size);
3325 ret = iommu_queue_command(iommu, &cmd);
3330 /* Wait until all device TLBs are flushed */
3331 domain_flush_complete(domain);
3340 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3343 return __flush_pasid(domain, pasid, address, false);
3346 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3349 struct protection_domain *domain = to_pdomain(dom);
3350 unsigned long flags;
3353 spin_lock_irqsave(&domain->lock, flags);
3354 ret = __amd_iommu_flush_page(domain, pasid, address);
3355 spin_unlock_irqrestore(&domain->lock, flags);
3359 EXPORT_SYMBOL(amd_iommu_flush_page);
3361 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3363 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3367 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3369 struct protection_domain *domain = to_pdomain(dom);
3370 unsigned long flags;
3373 spin_lock_irqsave(&domain->lock, flags);
3374 ret = __amd_iommu_flush_tlb(domain, pasid);
3375 spin_unlock_irqrestore(&domain->lock, flags);
3379 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3381 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3388 index = (pasid >> (9 * level)) & 0x1ff;
3394 if (!(*pte & GCR3_VALID)) {
3398 root = (void *)get_zeroed_page(GFP_ATOMIC);
3402 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3405 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3413 static int __set_gcr3(struct protection_domain *domain, int pasid,
3418 if (domain->mode != PAGE_MODE_NONE)
3421 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3425 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3427 return __amd_iommu_flush_tlb(domain, pasid);
3430 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3434 if (domain->mode != PAGE_MODE_NONE)
3437 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3443 return __amd_iommu_flush_tlb(domain, pasid);
3446 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3449 struct protection_domain *domain = to_pdomain(dom);
3450 unsigned long flags;
3453 spin_lock_irqsave(&domain->lock, flags);
3454 ret = __set_gcr3(domain, pasid, cr3);
3455 spin_unlock_irqrestore(&domain->lock, flags);
3459 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3461 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3463 struct protection_domain *domain = to_pdomain(dom);
3464 unsigned long flags;
3467 spin_lock_irqsave(&domain->lock, flags);
3468 ret = __clear_gcr3(domain, pasid);
3469 spin_unlock_irqrestore(&domain->lock, flags);
3473 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3475 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3476 int status, int tag)
3478 struct iommu_dev_data *dev_data;
3479 struct amd_iommu *iommu;
3480 struct iommu_cmd cmd;
3482 dev_data = get_dev_data(&pdev->dev);
3483 iommu = amd_iommu_rlookup_table[dev_data->devid];
3485 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3486 tag, dev_data->pri_tlp);
3488 return iommu_queue_command(iommu, &cmd);
3490 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3492 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3494 struct protection_domain *pdomain;
3496 pdomain = get_domain(&pdev->dev);
3497 if (IS_ERR(pdomain))
3500 /* Only return IOMMUv2 domains */
3501 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3504 return &pdomain->domain;
3506 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3508 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3510 struct iommu_dev_data *dev_data;
3512 if (!amd_iommu_v2_supported())
3515 dev_data = get_dev_data(&pdev->dev);
3516 dev_data->errata |= (1 << erratum);
3518 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3520 int amd_iommu_device_info(struct pci_dev *pdev,
3521 struct amd_iommu_device_info *info)
3526 if (pdev == NULL || info == NULL)
3529 if (!amd_iommu_v2_supported())
3532 memset(info, 0, sizeof(*info));
3534 if (!pci_ats_disabled()) {
3535 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3537 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3540 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3542 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3544 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3548 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3549 max_pasids = min(max_pasids, (1 << 20));
3551 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3552 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3554 features = pci_pasid_features(pdev);
3555 if (features & PCI_PASID_CAP_EXEC)
3556 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3557 if (features & PCI_PASID_CAP_PRIV)
3558 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3563 EXPORT_SYMBOL(amd_iommu_device_info);
3565 #ifdef CONFIG_IRQ_REMAP
3567 /*****************************************************************************
3569 * Interrupt Remapping Implementation
3571 *****************************************************************************/
3573 static struct irq_chip amd_ir_chip;
3574 static DEFINE_SPINLOCK(iommu_table_lock);
3576 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3580 dte = amd_iommu_dev_table[devid].data[2];
3581 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3582 dte |= iommu_virt_to_phys(table->table);
3583 dte |= DTE_IRQ_REMAP_INTCTL;
3584 dte |= DTE_IRQ_TABLE_LEN;
3585 dte |= DTE_IRQ_REMAP_ENABLE;
3587 amd_iommu_dev_table[devid].data[2] = dte;
3590 static struct irq_remap_table *get_irq_table(u16 devid)
3592 struct irq_remap_table *table;
3594 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3595 "%s: no iommu for devid %x\n", __func__, devid))
3598 table = irq_lookup_table[devid];
3599 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3605 static struct irq_remap_table *__alloc_irq_table(void)
3607 struct irq_remap_table *table;
3609 table = kzalloc(sizeof(*table), GFP_KERNEL);
3613 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3614 if (!table->table) {
3618 raw_spin_lock_init(&table->lock);
3620 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3621 memset(table->table, 0,
3622 MAX_IRQS_PER_TABLE * sizeof(u32));
3624 memset(table->table, 0,
3625 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3629 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3630 struct irq_remap_table *table)
3632 irq_lookup_table[devid] = table;
3633 set_dte_irq_entry(devid, table);
3634 iommu_flush_dte(iommu, devid);
3637 static struct irq_remap_table *alloc_irq_table(u16 devid)
3639 struct irq_remap_table *table = NULL;
3640 struct irq_remap_table *new_table = NULL;
3641 struct amd_iommu *iommu;
3642 unsigned long flags;
3645 spin_lock_irqsave(&iommu_table_lock, flags);
3647 iommu = amd_iommu_rlookup_table[devid];
3651 table = irq_lookup_table[devid];
3655 alias = amd_iommu_alias_table[devid];
3656 table = irq_lookup_table[alias];
3658 set_remap_table_entry(iommu, devid, table);
3661 spin_unlock_irqrestore(&iommu_table_lock, flags);
3663 /* Nothing there yet, allocate new irq remapping table */
3664 new_table = __alloc_irq_table();
3668 spin_lock_irqsave(&iommu_table_lock, flags);
3670 table = irq_lookup_table[devid];
3674 table = irq_lookup_table[alias];
3676 set_remap_table_entry(iommu, devid, table);
3683 set_remap_table_entry(iommu, devid, table);
3685 set_remap_table_entry(iommu, alias, table);
3688 iommu_completion_wait(iommu);
3691 spin_unlock_irqrestore(&iommu_table_lock, flags);
3694 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3700 static int alloc_irq_index(u16 devid, int count, bool align)
3702 struct irq_remap_table *table;
3703 int index, c, alignment = 1;
3704 unsigned long flags;
3705 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3710 table = alloc_irq_table(devid);
3715 alignment = roundup_pow_of_two(count);
3717 raw_spin_lock_irqsave(&table->lock, flags);
3719 /* Scan table for free entries */
3720 for (index = ALIGN(table->min_index, alignment), c = 0;
3721 index < MAX_IRQS_PER_TABLE;) {
3722 if (!iommu->irte_ops->is_allocated(table, index)) {
3726 index = ALIGN(index + 1, alignment);
3732 iommu->irte_ops->set_allocated(table, index - c + 1);
3744 raw_spin_unlock_irqrestore(&table->lock, flags);
3749 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3750 struct amd_ir_data *data)
3752 struct irq_remap_table *table;
3753 struct amd_iommu *iommu;
3754 unsigned long flags;
3755 struct irte_ga *entry;
3757 iommu = amd_iommu_rlookup_table[devid];
3761 table = get_irq_table(devid);
3765 raw_spin_lock_irqsave(&table->lock, flags);
3767 entry = (struct irte_ga *)table->table;
3768 entry = &entry[index];
3769 entry->lo.fields_remap.valid = 0;
3770 entry->hi.val = irte->hi.val;
3771 entry->lo.val = irte->lo.val;
3772 entry->lo.fields_remap.valid = 1;
3776 raw_spin_unlock_irqrestore(&table->lock, flags);
3778 iommu_flush_irt(iommu, devid);
3779 iommu_completion_wait(iommu);
3784 static int modify_irte(u16 devid, int index, union irte *irte)
3786 struct irq_remap_table *table;
3787 struct amd_iommu *iommu;
3788 unsigned long flags;
3790 iommu = amd_iommu_rlookup_table[devid];
3794 table = get_irq_table(devid);
3798 raw_spin_lock_irqsave(&table->lock, flags);
3799 table->table[index] = irte->val;
3800 raw_spin_unlock_irqrestore(&table->lock, flags);
3802 iommu_flush_irt(iommu, devid);
3803 iommu_completion_wait(iommu);
3808 static void free_irte(u16 devid, int index)
3810 struct irq_remap_table *table;
3811 struct amd_iommu *iommu;
3812 unsigned long flags;
3814 iommu = amd_iommu_rlookup_table[devid];
3818 table = get_irq_table(devid);
3822 raw_spin_lock_irqsave(&table->lock, flags);
3823 iommu->irte_ops->clear_allocated(table, index);
3824 raw_spin_unlock_irqrestore(&table->lock, flags);
3826 iommu_flush_irt(iommu, devid);
3827 iommu_completion_wait(iommu);
3830 static void irte_prepare(void *entry,
3831 u32 delivery_mode, u32 dest_mode,
3832 u8 vector, u32 dest_apicid, int devid)
3834 union irte *irte = (union irte *) entry;
3837 irte->fields.vector = vector;
3838 irte->fields.int_type = delivery_mode;
3839 irte->fields.destination = dest_apicid;
3840 irte->fields.dm = dest_mode;
3841 irte->fields.valid = 1;
3844 static void irte_ga_prepare(void *entry,
3845 u32 delivery_mode, u32 dest_mode,
3846 u8 vector, u32 dest_apicid, int devid)
3848 struct irte_ga *irte = (struct irte_ga *) entry;
3852 irte->lo.fields_remap.int_type = delivery_mode;
3853 irte->lo.fields_remap.dm = dest_mode;
3854 irte->hi.fields.vector = vector;
3855 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3856 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3857 irte->lo.fields_remap.valid = 1;
3860 static void irte_activate(void *entry, u16 devid, u16 index)
3862 union irte *irte = (union irte *) entry;
3864 irte->fields.valid = 1;
3865 modify_irte(devid, index, irte);
3868 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3870 struct irte_ga *irte = (struct irte_ga *) entry;
3872 irte->lo.fields_remap.valid = 1;
3873 modify_irte_ga(devid, index, irte, NULL);
3876 static void irte_deactivate(void *entry, u16 devid, u16 index)
3878 union irte *irte = (union irte *) entry;
3880 irte->fields.valid = 0;
3881 modify_irte(devid, index, irte);
3884 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3886 struct irte_ga *irte = (struct irte_ga *) entry;
3888 irte->lo.fields_remap.valid = 0;
3889 modify_irte_ga(devid, index, irte, NULL);
3892 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3893 u8 vector, u32 dest_apicid)
3895 union irte *irte = (union irte *) entry;
3897 irte->fields.vector = vector;
3898 irte->fields.destination = dest_apicid;
3899 modify_irte(devid, index, irte);
3902 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3903 u8 vector, u32 dest_apicid)
3905 struct irte_ga *irte = (struct irte_ga *) entry;
3907 if (!irte->lo.fields_remap.guest_mode) {
3908 irte->hi.fields.vector = vector;
3909 irte->lo.fields_remap.destination =
3910 APICID_TO_IRTE_DEST_LO(dest_apicid);
3911 irte->hi.fields.destination =
3912 APICID_TO_IRTE_DEST_HI(dest_apicid);
3913 modify_irte_ga(devid, index, irte, NULL);
3917 #define IRTE_ALLOCATED (~1U)
3918 static void irte_set_allocated(struct irq_remap_table *table, int index)
3920 table->table[index] = IRTE_ALLOCATED;
3923 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3925 struct irte_ga *ptr = (struct irte_ga *)table->table;
3926 struct irte_ga *irte = &ptr[index];
3928 memset(&irte->lo.val, 0, sizeof(u64));
3929 memset(&irte->hi.val, 0, sizeof(u64));
3930 irte->hi.fields.vector = 0xff;
3933 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3935 union irte *ptr = (union irte *)table->table;
3936 union irte *irte = &ptr[index];
3938 return irte->val != 0;
3941 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3943 struct irte_ga *ptr = (struct irte_ga *)table->table;
3944 struct irte_ga *irte = &ptr[index];
3946 return irte->hi.fields.vector != 0;
3949 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3951 table->table[index] = 0;
3954 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3956 struct irte_ga *ptr = (struct irte_ga *)table->table;
3957 struct irte_ga *irte = &ptr[index];
3959 memset(&irte->lo.val, 0, sizeof(u64));
3960 memset(&irte->hi.val, 0, sizeof(u64));
3963 static int get_devid(struct irq_alloc_info *info)
3967 switch (info->type) {
3968 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3969 devid = get_ioapic_devid(info->ioapic_id);
3971 case X86_IRQ_ALLOC_TYPE_HPET:
3972 devid = get_hpet_devid(info->hpet_id);
3974 case X86_IRQ_ALLOC_TYPE_MSI:
3975 case X86_IRQ_ALLOC_TYPE_MSIX:
3976 devid = get_device_id(&info->msi_dev->dev);
3986 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3988 struct amd_iommu *iommu;
3994 devid = get_devid(info);
3996 iommu = amd_iommu_rlookup_table[devid];
3998 return iommu->ir_domain;
4004 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4006 struct amd_iommu *iommu;
4012 switch (info->type) {
4013 case X86_IRQ_ALLOC_TYPE_MSI:
4014 case X86_IRQ_ALLOC_TYPE_MSIX:
4015 devid = get_device_id(&info->msi_dev->dev);
4019 iommu = amd_iommu_rlookup_table[devid];
4021 return iommu->msi_domain;
4030 struct irq_remap_ops amd_iommu_irq_ops = {
4031 .prepare = amd_iommu_prepare,
4032 .enable = amd_iommu_enable,
4033 .disable = amd_iommu_disable,
4034 .reenable = amd_iommu_reenable,
4035 .enable_faulting = amd_iommu_enable_faulting,
4036 .get_ir_irq_domain = get_ir_irq_domain,
4037 .get_irq_domain = get_irq_domain,
4040 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4041 struct irq_cfg *irq_cfg,
4042 struct irq_alloc_info *info,
4043 int devid, int index, int sub_handle)
4045 struct irq_2_irte *irte_info = &data->irq_2_irte;
4046 struct msi_msg *msg = &data->msi_entry;
4047 struct IO_APIC_route_entry *entry;
4048 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4053 data->irq_2_irte.devid = devid;
4054 data->irq_2_irte.index = index + sub_handle;
4055 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4056 apic->irq_dest_mode, irq_cfg->vector,
4057 irq_cfg->dest_apicid, devid);
4059 switch (info->type) {
4060 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4061 /* Setup IOAPIC entry */
4062 entry = info->ioapic_entry;
4063 info->ioapic_entry = NULL;
4064 memset(entry, 0, sizeof(*entry));
4065 entry->vector = index;
4067 entry->trigger = info->ioapic_trigger;
4068 entry->polarity = info->ioapic_polarity;
4069 /* Mask level triggered irqs. */
4070 if (info->ioapic_trigger)
4074 case X86_IRQ_ALLOC_TYPE_HPET:
4075 case X86_IRQ_ALLOC_TYPE_MSI:
4076 case X86_IRQ_ALLOC_TYPE_MSIX:
4077 msg->address_hi = MSI_ADDR_BASE_HI;
4078 msg->address_lo = MSI_ADDR_BASE_LO;
4079 msg->data = irte_info->index;
4088 struct amd_irte_ops irte_32_ops = {
4089 .prepare = irte_prepare,
4090 .activate = irte_activate,
4091 .deactivate = irte_deactivate,
4092 .set_affinity = irte_set_affinity,
4093 .set_allocated = irte_set_allocated,
4094 .is_allocated = irte_is_allocated,
4095 .clear_allocated = irte_clear_allocated,
4098 struct amd_irte_ops irte_128_ops = {
4099 .prepare = irte_ga_prepare,
4100 .activate = irte_ga_activate,
4101 .deactivate = irte_ga_deactivate,
4102 .set_affinity = irte_ga_set_affinity,
4103 .set_allocated = irte_ga_set_allocated,
4104 .is_allocated = irte_ga_is_allocated,
4105 .clear_allocated = irte_ga_clear_allocated,
4108 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4109 unsigned int nr_irqs, void *arg)
4111 struct irq_alloc_info *info = arg;
4112 struct irq_data *irq_data;
4113 struct amd_ir_data *data = NULL;
4114 struct irq_cfg *cfg;
4120 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4121 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4125 * With IRQ remapping enabled, don't need contiguous CPU vectors
4126 * to support multiple MSI interrupts.
4128 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4129 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4131 devid = get_devid(info);
4135 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4139 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4140 struct irq_remap_table *table;
4141 struct amd_iommu *iommu;
4143 table = alloc_irq_table(devid);
4145 if (!table->min_index) {
4147 * Keep the first 32 indexes free for IOAPIC
4150 table->min_index = 32;
4151 iommu = amd_iommu_rlookup_table[devid];
4152 for (i = 0; i < 32; ++i)
4153 iommu->irte_ops->set_allocated(table, i);
4155 WARN_ON(table->min_index != 32);
4156 index = info->ioapic_pin;
4161 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4163 index = alloc_irq_index(devid, nr_irqs, align);
4166 pr_warn("Failed to allocate IRTE\n");
4168 goto out_free_parent;
4171 for (i = 0; i < nr_irqs; i++) {
4172 irq_data = irq_domain_get_irq_data(domain, virq + i);
4173 cfg = irqd_cfg(irq_data);
4174 if (!irq_data || !cfg) {
4180 data = kzalloc(sizeof(*data), GFP_KERNEL);
4184 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4185 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4187 data->entry = kzalloc(sizeof(struct irte_ga),
4194 irq_data->hwirq = (devid << 16) + i;
4195 irq_data->chip_data = data;
4196 irq_data->chip = &amd_ir_chip;
4197 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4198 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4204 for (i--; i >= 0; i--) {
4205 irq_data = irq_domain_get_irq_data(domain, virq + i);
4207 kfree(irq_data->chip_data);
4209 for (i = 0; i < nr_irqs; i++)
4210 free_irte(devid, index + i);
4212 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4216 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4217 unsigned int nr_irqs)
4219 struct irq_2_irte *irte_info;
4220 struct irq_data *irq_data;
4221 struct amd_ir_data *data;
4224 for (i = 0; i < nr_irqs; i++) {
4225 irq_data = irq_domain_get_irq_data(domain, virq + i);
4226 if (irq_data && irq_data->chip_data) {
4227 data = irq_data->chip_data;
4228 irte_info = &data->irq_2_irte;
4229 free_irte(irte_info->devid, irte_info->index);
4234 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4237 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4238 struct amd_ir_data *ir_data,
4239 struct irq_2_irte *irte_info,
4240 struct irq_cfg *cfg);
4242 static int irq_remapping_activate(struct irq_domain *domain,
4243 struct irq_data *irq_data, bool reserve)
4245 struct amd_ir_data *data = irq_data->chip_data;
4246 struct irq_2_irte *irte_info = &data->irq_2_irte;
4247 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4248 struct irq_cfg *cfg = irqd_cfg(irq_data);
4253 iommu->irte_ops->activate(data->entry, irte_info->devid,
4255 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4259 static void irq_remapping_deactivate(struct irq_domain *domain,
4260 struct irq_data *irq_data)
4262 struct amd_ir_data *data = irq_data->chip_data;
4263 struct irq_2_irte *irte_info = &data->irq_2_irte;
4264 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4267 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4271 static const struct irq_domain_ops amd_ir_domain_ops = {
4272 .alloc = irq_remapping_alloc,
4273 .free = irq_remapping_free,
4274 .activate = irq_remapping_activate,
4275 .deactivate = irq_remapping_deactivate,
4278 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4280 struct amd_iommu *iommu;
4281 struct amd_iommu_pi_data *pi_data = vcpu_info;
4282 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4283 struct amd_ir_data *ir_data = data->chip_data;
4284 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4285 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4286 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4289 * This device has never been set up for guest mode.
4290 * we should not modify the IRTE
4292 if (!dev_data || !dev_data->use_vapic)
4295 pi_data->ir_data = ir_data;
4298 * SVM tries to set up for VAPIC mode, but we are in
4299 * legacy mode. So, we force legacy mode instead.
4301 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4302 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4304 pi_data->is_guest_mode = false;
4307 iommu = amd_iommu_rlookup_table[irte_info->devid];
4311 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4312 if (pi_data->is_guest_mode) {
4314 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4315 irte->hi.fields.vector = vcpu_pi_info->vector;
4316 irte->lo.fields_vapic.ga_log_intr = 1;
4317 irte->lo.fields_vapic.guest_mode = 1;
4318 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4320 ir_data->cached_ga_tag = pi_data->ga_tag;
4323 struct irq_cfg *cfg = irqd_cfg(data);
4327 irte->hi.fields.vector = cfg->vector;
4328 irte->lo.fields_remap.guest_mode = 0;
4329 irte->lo.fields_remap.destination =
4330 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4331 irte->hi.fields.destination =
4332 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4333 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4334 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4337 * This communicates the ga_tag back to the caller
4338 * so that it can do all the necessary clean up.
4340 ir_data->cached_ga_tag = 0;
4343 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4347 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4348 struct amd_ir_data *ir_data,
4349 struct irq_2_irte *irte_info,
4350 struct irq_cfg *cfg)
4354 * Atomically updates the IRTE with the new destination, vector
4355 * and flushes the interrupt entry cache.
4357 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4358 irte_info->index, cfg->vector,
4362 static int amd_ir_set_affinity(struct irq_data *data,
4363 const struct cpumask *mask, bool force)
4365 struct amd_ir_data *ir_data = data->chip_data;
4366 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4367 struct irq_cfg *cfg = irqd_cfg(data);
4368 struct irq_data *parent = data->parent_data;
4369 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4375 ret = parent->chip->irq_set_affinity(parent, mask, force);
4376 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4379 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4381 * After this point, all the interrupts will start arriving
4382 * at the new destination. So, time to cleanup the previous
4383 * vector allocation.
4385 send_cleanup_vector(cfg);
4387 return IRQ_SET_MASK_OK_DONE;
4390 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4392 struct amd_ir_data *ir_data = irq_data->chip_data;
4394 *msg = ir_data->msi_entry;
4397 static struct irq_chip amd_ir_chip = {
4399 .irq_ack = apic_ack_irq,
4400 .irq_set_affinity = amd_ir_set_affinity,
4401 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4402 .irq_compose_msi_msg = ir_compose_msi_msg,
4405 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4407 struct fwnode_handle *fn;
4409 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4412 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4413 irq_domain_free_fwnode(fn);
4414 if (!iommu->ir_domain)
4417 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4418 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4424 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4426 unsigned long flags;
4427 struct amd_iommu *iommu;
4428 struct irq_remap_table *table;
4429 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4430 int devid = ir_data->irq_2_irte.devid;
4431 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4432 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4434 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4435 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4438 iommu = amd_iommu_rlookup_table[devid];
4442 table = get_irq_table(devid);
4446 raw_spin_lock_irqsave(&table->lock, flags);
4448 if (ref->lo.fields_vapic.guest_mode) {
4450 ref->lo.fields_vapic.destination =
4451 APICID_TO_IRTE_DEST_LO(cpu);
4452 ref->hi.fields.destination =
4453 APICID_TO_IRTE_DEST_HI(cpu);
4455 ref->lo.fields_vapic.is_run = is_run;
4459 raw_spin_unlock_irqrestore(&table->lock, flags);
4461 iommu_flush_irt(iommu, devid);
4462 iommu_completion_wait(iommu);
4465 EXPORT_SYMBOL(amd_iommu_update_ga);