2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
58 #define AMD_IOMMU_MAPPING_ERROR 0
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
62 #define LOOP_TIMEOUT 100000
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
80 * 512GB Pages are not supported due to a hardware bug
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
90 LIST_HEAD(ioapic_map);
92 LIST_HEAD(acpihid_map);
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
98 const struct iommu_ops amd_iommu_ops;
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
103 static const struct dma_map_ops amd_iommu_dma_ops;
106 * general struct to manage commands send to an IOMMU
112 struct kmem_cache *amd_iommu_irq_cache;
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
120 * Data container for a dma_ops specific protection domain
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
127 struct iova_domain iovad;
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
133 /****************************************************************************
137 ****************************************************************************/
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
142 const char *hid, *uid;
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
151 return strcmp(hid, entry->hid);
154 return strcmp(hid, entry->hid);
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
159 static inline u16 get_pci_device_id(struct device *dev)
161 struct pci_dev *pdev = to_pci_dev(dev);
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
169 struct acpihid_map_entry *p;
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
181 static inline int get_device_id(struct device *dev)
186 devid = get_pci_device_id(dev);
188 devid = get_acpihid_device_id(dev, NULL);
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
195 return container_of(dom, struct protection_domain, domain);
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
206 struct iommu_dev_data *dev_data;
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
212 dev_data->devid = devid;
213 ratelimit_default_init(&dev_data->rs);
215 llist_add(&dev_data->dev_data_list, &dev_data_list);
219 static struct iommu_dev_data *search_dev_data(u16 devid)
221 struct iommu_dev_data *dev_data;
222 struct llist_node *node;
224 if (llist_empty(&dev_data_list))
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
229 if (dev_data->devid == devid)
236 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
238 *(u16 *)data = alias;
242 static u16 get_alias(struct device *dev)
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
247 /* The callers make sure that get_device_id() does not fail here */
248 devid = get_device_id(dev);
249 ivrs_alias = amd_iommu_alias_table[devid];
250 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
252 if (ivrs_alias == pci_alias)
258 * The IVRS is fairly reliable in telling us about aliases, but it
259 * can't know about every screwy device. If we don't have an IVRS
260 * reported alias, use the PCI reported alias. In that case we may
261 * still need to initialize the rlookup and dev_table entries if the
262 * alias is to a non-existent device.
264 if (ivrs_alias == devid) {
265 if (!amd_iommu_rlookup_table[pci_alias]) {
266 amd_iommu_rlookup_table[pci_alias] =
267 amd_iommu_rlookup_table[devid];
268 memcpy(amd_iommu_dev_table[pci_alias].data,
269 amd_iommu_dev_table[devid].data,
270 sizeof(amd_iommu_dev_table[pci_alias].data));
276 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
277 "for device %s[%04x:%04x], kernel reported alias "
278 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
279 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
280 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
281 PCI_FUNC(pci_alias));
284 * If we don't have a PCI DMA alias and the IVRS alias is on the same
285 * bus, then the IVRS table may know about a quirk that we don't.
287 if (pci_alias == devid &&
288 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
289 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
290 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
291 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
298 static struct iommu_dev_data *find_dev_data(u16 devid)
300 struct iommu_dev_data *dev_data;
301 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
303 dev_data = search_dev_data(devid);
305 if (dev_data == NULL) {
306 dev_data = alloc_dev_data(devid);
310 if (translation_pre_enabled(iommu))
311 dev_data->defer_attach = true;
317 struct iommu_dev_data *get_dev_data(struct device *dev)
319 return dev->archdata.iommu;
321 EXPORT_SYMBOL(get_dev_data);
324 * Find or create an IOMMU group for a acpihid device.
326 static struct iommu_group *acpihid_device_group(struct device *dev)
328 struct acpihid_map_entry *p, *entry = NULL;
331 devid = get_acpihid_device_id(dev, &entry);
333 return ERR_PTR(devid);
335 list_for_each_entry(p, &acpihid_map, list) {
336 if ((devid == p->devid) && p->group)
337 entry->group = p->group;
341 entry->group = generic_device_group(dev);
343 iommu_group_ref_get(entry->group);
348 static bool pci_iommuv2_capable(struct pci_dev *pdev)
350 static const int caps[] = {
353 PCI_EXT_CAP_ID_PASID,
357 if (pci_ats_disabled())
360 for (i = 0; i < 3; ++i) {
361 pos = pci_find_ext_capability(pdev, caps[i]);
369 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
371 struct iommu_dev_data *dev_data;
373 dev_data = get_dev_data(&pdev->dev);
375 return dev_data->errata & (1 << erratum) ? true : false;
379 * This function checks if the driver got a valid device from the caller to
380 * avoid dereferencing invalid pointers.
382 static bool check_device(struct device *dev)
386 if (!dev || !dev->dma_mask)
389 devid = get_device_id(dev);
393 /* Out of our scope? */
394 if (devid > amd_iommu_last_bdf)
397 if (amd_iommu_rlookup_table[devid] == NULL)
403 static void init_iommu_group(struct device *dev)
405 struct iommu_group *group;
407 group = iommu_group_get_for_dev(dev);
411 iommu_group_put(group);
414 static int iommu_init_device(struct device *dev)
416 struct iommu_dev_data *dev_data;
417 struct amd_iommu *iommu;
420 if (dev->archdata.iommu)
423 devid = get_device_id(dev);
427 iommu = amd_iommu_rlookup_table[devid];
429 dev_data = find_dev_data(devid);
433 dev_data->alias = get_alias(dev);
435 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
436 struct amd_iommu *iommu;
438 iommu = amd_iommu_rlookup_table[dev_data->devid];
439 dev_data->iommu_v2 = iommu->is_iommu_v2;
442 dev->archdata.iommu = dev_data;
444 iommu_device_link(&iommu->iommu, dev);
449 static void iommu_ignore_device(struct device *dev)
454 devid = get_device_id(dev);
458 alias = get_alias(dev);
460 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
461 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
463 amd_iommu_rlookup_table[devid] = NULL;
464 amd_iommu_rlookup_table[alias] = NULL;
467 static void iommu_uninit_device(struct device *dev)
469 struct iommu_dev_data *dev_data;
470 struct amd_iommu *iommu;
473 devid = get_device_id(dev);
477 iommu = amd_iommu_rlookup_table[devid];
479 dev_data = search_dev_data(devid);
483 if (dev_data->domain)
486 iommu_device_unlink(&iommu->iommu, dev);
488 iommu_group_remove_device(dev);
494 * We keep dev_data around for unplugged devices and reuse it when the
495 * device is re-plugged - not doing so would introduce a ton of races.
499 /****************************************************************************
501 * Interrupt handling functions
503 ****************************************************************************/
505 static void dump_dte_entry(u16 devid)
509 for (i = 0; i < 4; ++i)
510 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
511 amd_iommu_dev_table[devid].data[i]);
514 static void dump_command(unsigned long phys_addr)
516 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
519 for (i = 0; i < 4; ++i)
520 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
523 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
524 u64 address, int flags)
526 struct iommu_dev_data *dev_data = NULL;
527 struct pci_dev *pdev;
529 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
532 dev_data = get_dev_data(&pdev->dev);
534 if (dev_data && __ratelimit(&dev_data->rs)) {
535 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 domain_id, address, flags);
537 } else if (printk_ratelimit()) {
538 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
539 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
540 domain_id, address, flags);
547 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 struct device *dev = iommu->iommu.dev;
550 int type, devid, pasid, flags, tag;
551 volatile u32 *event = __evt;
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 pasid = PPR_PASID(*(u64 *)&event[0]);
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
572 if (type == EVENT_TYPE_IO_FAULT) {
573 amd_iommu_report_page_fault(devid, pasid, address, flags);
576 dev_err(dev, "AMD-Vi: Event logged [");
580 case EVENT_TYPE_ILL_DEV:
581 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
582 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
583 pasid, address, flags);
584 dump_dte_entry(devid);
586 case EVENT_TYPE_DEV_TAB_ERR:
587 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
588 "address=0x%016llx flags=0x%04x]\n",
589 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
592 case EVENT_TYPE_PAGE_TAB_ERR:
593 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
594 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
595 pasid, address, flags);
597 case EVENT_TYPE_ILL_CMD:
598 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
599 dump_command(address);
601 case EVENT_TYPE_CMD_HARD_ERR:
602 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
605 case EVENT_TYPE_IOTLB_INV_TO:
606 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
607 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
610 case EVENT_TYPE_INV_DEV_REQ:
611 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
612 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
613 pasid, address, flags);
615 case EVENT_TYPE_INV_PPR_REQ:
616 pasid = ((event[0] >> 16) & 0xFFFF)
617 | ((event[1] << 6) & 0xF0000);
618 tag = event[1] & 0x03FF;
619 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 pasid, address, flags);
624 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
625 event[0], event[1], event[2], event[3]);
628 memset(__evt, 0, 4 * sizeof(u32));
631 static void iommu_poll_events(struct amd_iommu *iommu)
635 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
636 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
638 while (head != tail) {
639 iommu_print_event(iommu, iommu->evt_buf + head);
640 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
643 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
646 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
648 struct amd_iommu_fault fault;
650 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
651 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
655 fault.address = raw[1];
656 fault.pasid = PPR_PASID(raw[0]);
657 fault.device_id = PPR_DEVID(raw[0]);
658 fault.tag = PPR_TAG(raw[0]);
659 fault.flags = PPR_FLAGS(raw[0]);
661 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
664 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
668 if (iommu->ppr_log == NULL)
671 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
672 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
674 while (head != tail) {
679 raw = (u64 *)(iommu->ppr_log + head);
682 * Hardware bug: Interrupt may arrive before the entry is
683 * written to memory. If this happens we need to wait for the
686 for (i = 0; i < LOOP_TIMEOUT; ++i) {
687 if (PPR_REQ_TYPE(raw[0]) != 0)
692 /* Avoid memcpy function-call overhead */
697 * To detect the hardware bug we need to clear the entry
700 raw[0] = raw[1] = 0UL;
702 /* Update head pointer of hardware ring-buffer */
703 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
704 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
706 /* Handle PPR entry */
707 iommu_handle_ppr_entry(iommu, entry);
709 /* Refresh ring-buffer information */
710 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
711 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
715 #ifdef CONFIG_IRQ_REMAP
716 static int (*iommu_ga_log_notifier)(u32);
718 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
720 iommu_ga_log_notifier = notifier;
724 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
726 static void iommu_poll_ga_log(struct amd_iommu *iommu)
728 u32 head, tail, cnt = 0;
730 if (iommu->ga_log == NULL)
733 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
734 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
736 while (head != tail) {
740 raw = (u64 *)(iommu->ga_log + head);
743 /* Avoid memcpy function-call overhead */
746 /* Update head pointer of hardware ring-buffer */
747 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
748 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
750 /* Handle GA entry */
751 switch (GA_REQ_TYPE(log_entry)) {
753 if (!iommu_ga_log_notifier)
756 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
757 __func__, GA_DEVID(log_entry),
760 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
761 pr_err("AMD-Vi: GA log notifier failed.\n");
768 #endif /* CONFIG_IRQ_REMAP */
770 #define AMD_IOMMU_INT_MASK \
771 (MMIO_STATUS_EVT_INT_MASK | \
772 MMIO_STATUS_PPR_INT_MASK | \
773 MMIO_STATUS_GALOG_INT_MASK)
775 irqreturn_t amd_iommu_int_thread(int irq, void *data)
777 struct amd_iommu *iommu = (struct amd_iommu *) data;
778 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
780 while (status & AMD_IOMMU_INT_MASK) {
781 /* Enable EVT and PPR and GA interrupts again */
782 writel(AMD_IOMMU_INT_MASK,
783 iommu->mmio_base + MMIO_STATUS_OFFSET);
785 if (status & MMIO_STATUS_EVT_INT_MASK) {
786 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
787 iommu_poll_events(iommu);
790 if (status & MMIO_STATUS_PPR_INT_MASK) {
791 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
792 iommu_poll_ppr_log(iommu);
795 #ifdef CONFIG_IRQ_REMAP
796 if (status & MMIO_STATUS_GALOG_INT_MASK) {
797 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
798 iommu_poll_ga_log(iommu);
803 * Hardware bug: ERBT1312
804 * When re-enabling interrupt (by writing 1
805 * to clear the bit), the hardware might also try to set
806 * the interrupt bit in the event status register.
807 * In this scenario, the bit will be set, and disable
808 * subsequent interrupts.
810 * Workaround: The IOMMU driver should read back the
811 * status register and check if the interrupt bits are cleared.
812 * If not, driver will need to go through the interrupt handler
813 * again and re-clear the bits
815 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
820 irqreturn_t amd_iommu_int_handler(int irq, void *data)
822 return IRQ_WAKE_THREAD;
825 /****************************************************************************
827 * IOMMU command queuing functions
829 ****************************************************************************/
831 static int wait_on_sem(volatile u64 *sem)
835 while (*sem == 0 && i < LOOP_TIMEOUT) {
840 if (i == LOOP_TIMEOUT) {
841 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
848 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
849 struct iommu_cmd *cmd)
853 target = iommu->cmd_buf + iommu->cmd_buf_tail;
855 iommu->cmd_buf_tail += sizeof(*cmd);
856 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
858 /* Copy command to buffer */
859 memcpy(target, cmd, sizeof(*cmd));
861 /* Tell the IOMMU about it */
862 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
865 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
867 u64 paddr = iommu_virt_to_phys((void *)address);
869 WARN_ON(address & 0x7ULL);
871 memset(cmd, 0, sizeof(*cmd));
872 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
873 cmd->data[1] = upper_32_bits(paddr);
875 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
878 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
880 memset(cmd, 0, sizeof(*cmd));
881 cmd->data[0] = devid;
882 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
885 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
886 size_t size, u16 domid, int pde)
891 pages = iommu_num_pages(address, size, PAGE_SIZE);
896 * If we have to flush more than one page, flush all
897 * TLB entries for this domain
899 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
903 address &= PAGE_MASK;
905 memset(cmd, 0, sizeof(*cmd));
906 cmd->data[1] |= domid;
907 cmd->data[2] = lower_32_bits(address);
908 cmd->data[3] = upper_32_bits(address);
909 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
910 if (s) /* size bit - we flush more than one 4kb page */
911 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
912 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
913 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
916 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
917 u64 address, size_t size)
922 pages = iommu_num_pages(address, size, PAGE_SIZE);
927 * If we have to flush more than one page, flush all
928 * TLB entries for this domain
930 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
934 address &= PAGE_MASK;
936 memset(cmd, 0, sizeof(*cmd));
937 cmd->data[0] = devid;
938 cmd->data[0] |= (qdep & 0xff) << 24;
939 cmd->data[1] = devid;
940 cmd->data[2] = lower_32_bits(address);
941 cmd->data[3] = upper_32_bits(address);
942 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
944 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
947 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
948 u64 address, bool size)
950 memset(cmd, 0, sizeof(*cmd));
952 address &= ~(0xfffULL);
954 cmd->data[0] = pasid;
955 cmd->data[1] = domid;
956 cmd->data[2] = lower_32_bits(address);
957 cmd->data[3] = upper_32_bits(address);
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
962 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
965 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
966 int qdep, u64 address, bool size)
968 memset(cmd, 0, sizeof(*cmd));
970 address &= ~(0xfffULL);
972 cmd->data[0] = devid;
973 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
974 cmd->data[0] |= (qdep & 0xff) << 24;
975 cmd->data[1] = devid;
976 cmd->data[1] |= (pasid & 0xff) << 16;
977 cmd->data[2] = lower_32_bits(address);
978 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
979 cmd->data[3] = upper_32_bits(address);
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
982 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
985 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
986 int status, int tag, bool gn)
988 memset(cmd, 0, sizeof(*cmd));
990 cmd->data[0] = devid;
992 cmd->data[1] = pasid;
993 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
995 cmd->data[3] = tag & 0x1ff;
996 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
998 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1001 static void build_inv_all(struct iommu_cmd *cmd)
1003 memset(cmd, 0, sizeof(*cmd));
1004 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1007 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1009 memset(cmd, 0, sizeof(*cmd));
1010 cmd->data[0] = devid;
1011 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1015 * Writes the command to the IOMMUs command buffer and informs the
1016 * hardware about the new command.
1018 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1019 struct iommu_cmd *cmd,
1022 unsigned int count = 0;
1023 u32 left, next_tail;
1025 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1027 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1030 /* Skip udelay() the first time around */
1032 if (count == LOOP_TIMEOUT) {
1033 pr_err("AMD-Vi: Command buffer timeout\n");
1040 /* Update head and recheck remaining space */
1041 iommu->cmd_buf_head = readl(iommu->mmio_base +
1042 MMIO_CMD_HEAD_OFFSET);
1047 copy_cmd_to_buffer(iommu, cmd);
1049 /* Do we need to make sure all commands are processed? */
1050 iommu->need_sync = sync;
1055 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1056 struct iommu_cmd *cmd,
1059 unsigned long flags;
1062 raw_spin_lock_irqsave(&iommu->lock, flags);
1063 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1064 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1069 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1071 return iommu_queue_command_sync(iommu, cmd, true);
1075 * This function queues a completion wait command into the command
1076 * buffer of an IOMMU
1078 static int iommu_completion_wait(struct amd_iommu *iommu)
1080 struct iommu_cmd cmd;
1081 unsigned long flags;
1084 if (!iommu->need_sync)
1088 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1090 raw_spin_lock_irqsave(&iommu->lock, flags);
1094 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1098 ret = wait_on_sem(&iommu->cmd_sem);
1101 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1106 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1108 struct iommu_cmd cmd;
1110 build_inv_dte(&cmd, devid);
1112 return iommu_queue_command(iommu, &cmd);
1115 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1119 for (devid = 0; devid <= 0xffff; ++devid)
1120 iommu_flush_dte(iommu, devid);
1122 iommu_completion_wait(iommu);
1126 * This function uses heavy locking and may disable irqs for some time. But
1127 * this is no issue because it is only called during resume.
1129 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1133 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1134 struct iommu_cmd cmd;
1135 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1137 iommu_queue_command(iommu, &cmd);
1140 iommu_completion_wait(iommu);
1143 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1145 struct iommu_cmd cmd;
1147 build_inv_all(&cmd);
1149 iommu_queue_command(iommu, &cmd);
1150 iommu_completion_wait(iommu);
1153 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1155 struct iommu_cmd cmd;
1157 build_inv_irt(&cmd, devid);
1159 iommu_queue_command(iommu, &cmd);
1162 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1166 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1167 iommu_flush_irt(iommu, devid);
1169 iommu_completion_wait(iommu);
1172 void iommu_flush_all_caches(struct amd_iommu *iommu)
1174 if (iommu_feature(iommu, FEATURE_IA)) {
1175 amd_iommu_flush_all(iommu);
1177 amd_iommu_flush_dte_all(iommu);
1178 amd_iommu_flush_irt_all(iommu);
1179 amd_iommu_flush_tlb_all(iommu);
1184 * Command send function for flushing on-device TLB
1186 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1187 u64 address, size_t size)
1189 struct amd_iommu *iommu;
1190 struct iommu_cmd cmd;
1193 qdep = dev_data->ats.qdep;
1194 iommu = amd_iommu_rlookup_table[dev_data->devid];
1196 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1198 return iommu_queue_command(iommu, &cmd);
1202 * Command send function for invalidating a device table entry
1204 static int device_flush_dte(struct iommu_dev_data *dev_data)
1206 struct amd_iommu *iommu;
1210 iommu = amd_iommu_rlookup_table[dev_data->devid];
1211 alias = dev_data->alias;
1213 ret = iommu_flush_dte(iommu, dev_data->devid);
1214 if (!ret && alias != dev_data->devid)
1215 ret = iommu_flush_dte(iommu, alias);
1219 if (dev_data->ats.enabled)
1220 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1226 * TLB invalidation function which is called from the mapping functions.
1227 * It invalidates a single PTE if the range to flush is within a single
1228 * page. Otherwise it flushes the whole TLB of the IOMMU.
1230 static void __domain_flush_pages(struct protection_domain *domain,
1231 u64 address, size_t size, int pde)
1233 struct iommu_dev_data *dev_data;
1234 struct iommu_cmd cmd;
1237 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1239 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1240 if (!domain->dev_iommu[i])
1244 * Devices of this domain are behind this IOMMU
1245 * We need a TLB flush
1247 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1250 list_for_each_entry(dev_data, &domain->dev_list, list) {
1252 if (!dev_data->ats.enabled)
1255 ret |= device_flush_iotlb(dev_data, address, size);
1261 static void domain_flush_pages(struct protection_domain *domain,
1262 u64 address, size_t size)
1264 __domain_flush_pages(domain, address, size, 0);
1267 /* Flush the whole IO/TLB for a given protection domain */
1268 static void domain_flush_tlb(struct protection_domain *domain)
1270 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1273 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1274 static void domain_flush_tlb_pde(struct protection_domain *domain)
1276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1279 static void domain_flush_complete(struct protection_domain *domain)
1283 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1284 if (domain && !domain->dev_iommu[i])
1288 * Devices of this domain are behind this IOMMU
1289 * We need to wait for completion of all commands.
1291 iommu_completion_wait(amd_iommus[i]);
1297 * This function flushes the DTEs for all devices in domain
1299 static void domain_flush_devices(struct protection_domain *domain)
1301 struct iommu_dev_data *dev_data;
1303 list_for_each_entry(dev_data, &domain->dev_list, list)
1304 device_flush_dte(dev_data);
1307 /****************************************************************************
1309 * The functions below are used the create the page table mappings for
1310 * unity mapped regions.
1312 ****************************************************************************/
1315 * This function is used to add another level to an IO page table. Adding
1316 * another level increases the size of the address space by 9 bits to a size up
1319 static bool increase_address_space(struct protection_domain *domain,
1324 if (domain->mode == PAGE_MODE_6_LEVEL)
1325 /* address space already 64 bit large */
1328 pte = (void *)get_zeroed_page(gfp);
1332 *pte = PM_LEVEL_PDE(domain->mode,
1333 iommu_virt_to_phys(domain->pt_root));
1334 domain->pt_root = pte;
1336 domain->updated = true;
1341 static u64 *alloc_pte(struct protection_domain *domain,
1342 unsigned long address,
1343 unsigned long page_size,
1350 BUG_ON(!is_power_of_2(page_size));
1352 while (address > PM_LEVEL_SIZE(domain->mode))
1353 increase_address_space(domain, gfp);
1355 level = domain->mode - 1;
1356 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1357 address = PAGE_SIZE_ALIGN(address, page_size);
1358 end_lvl = PAGE_SIZE_LEVEL(page_size);
1360 while (level > end_lvl) {
1365 if (!IOMMU_PTE_PRESENT(__pte)) {
1366 page = (u64 *)get_zeroed_page(gfp);
1370 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1372 /* pte could have been changed somewhere. */
1373 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1374 free_page((unsigned long)page);
1379 /* No level skipping support yet */
1380 if (PM_PTE_LEVEL(*pte) != level)
1385 pte = IOMMU_PTE_PAGE(*pte);
1387 if (pte_page && level == end_lvl)
1390 pte = &pte[PM_LEVEL_INDEX(level, address)];
1397 * This function checks if there is a PTE for a given dma address. If
1398 * there is one, it returns the pointer to it.
1400 static u64 *fetch_pte(struct protection_domain *domain,
1401 unsigned long address,
1402 unsigned long *page_size)
1409 if (address > PM_LEVEL_SIZE(domain->mode))
1412 level = domain->mode - 1;
1413 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1414 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1419 if (!IOMMU_PTE_PRESENT(*pte))
1423 if (PM_PTE_LEVEL(*pte) == 7 ||
1424 PM_PTE_LEVEL(*pte) == 0)
1427 /* No level skipping support yet */
1428 if (PM_PTE_LEVEL(*pte) != level)
1433 /* Walk to the next level */
1434 pte = IOMMU_PTE_PAGE(*pte);
1435 pte = &pte[PM_LEVEL_INDEX(level, address)];
1436 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1439 if (PM_PTE_LEVEL(*pte) == 0x07) {
1440 unsigned long pte_mask;
1443 * If we have a series of large PTEs, make
1444 * sure to return a pointer to the first one.
1446 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1447 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1448 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1455 * Generic mapping functions. It maps a physical address into a DMA
1456 * address space. It allocates the page table pages if necessary.
1457 * In the future it can be extended to a generic mapping function
1458 * supporting all features of AMD IOMMU page tables like level skipping
1459 * and full 64 bit address spaces.
1461 static int iommu_map_page(struct protection_domain *dom,
1462 unsigned long bus_addr,
1463 unsigned long phys_addr,
1464 unsigned long page_size,
1471 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1472 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1474 if (!(prot & IOMMU_PROT_MASK))
1477 count = PAGE_SIZE_PTE_COUNT(page_size);
1478 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1483 for (i = 0; i < count; ++i)
1484 if (IOMMU_PTE_PRESENT(pte[i]))
1488 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1489 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1491 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1493 if (prot & IOMMU_PROT_IR)
1494 __pte |= IOMMU_PTE_IR;
1495 if (prot & IOMMU_PROT_IW)
1496 __pte |= IOMMU_PTE_IW;
1498 for (i = 0; i < count; ++i)
1506 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1507 unsigned long bus_addr,
1508 unsigned long page_size)
1510 unsigned long long unmapped;
1511 unsigned long unmap_size;
1514 BUG_ON(!is_power_of_2(page_size));
1518 while (unmapped < page_size) {
1520 pte = fetch_pte(dom, bus_addr, &unmap_size);
1525 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1526 for (i = 0; i < count; i++)
1530 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1531 unmapped += unmap_size;
1534 BUG_ON(unmapped && !is_power_of_2(unmapped));
1539 /****************************************************************************
1541 * The next functions belong to the address allocator for the dma_ops
1542 * interface functions.
1544 ****************************************************************************/
1547 static unsigned long dma_ops_alloc_iova(struct device *dev,
1548 struct dma_ops_domain *dma_dom,
1549 unsigned int pages, u64 dma_mask)
1551 unsigned long pfn = 0;
1553 pages = __roundup_pow_of_two(pages);
1555 if (dma_mask > DMA_BIT_MASK(32))
1556 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1557 IOVA_PFN(DMA_BIT_MASK(32)), false);
1560 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1561 IOVA_PFN(dma_mask), true);
1563 return (pfn << PAGE_SHIFT);
1566 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1567 unsigned long address,
1570 pages = __roundup_pow_of_two(pages);
1571 address >>= PAGE_SHIFT;
1573 free_iova_fast(&dma_dom->iovad, address, pages);
1576 /****************************************************************************
1578 * The next functions belong to the domain allocation. A domain is
1579 * allocated for every IOMMU as the default domain. If device isolation
1580 * is enabled, every device get its own domain. The most important thing
1581 * about domains is the page table mapping the DMA address space they
1584 ****************************************************************************/
1587 * This function adds a protection domain to the global protection domain list
1589 static void add_domain_to_list(struct protection_domain *domain)
1591 unsigned long flags;
1593 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1594 list_add(&domain->list, &amd_iommu_pd_list);
1595 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1599 * This function removes a protection domain to the global
1600 * protection domain list
1602 static void del_domain_from_list(struct protection_domain *domain)
1604 unsigned long flags;
1606 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1607 list_del(&domain->list);
1608 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1611 static u16 domain_id_alloc(void)
1615 spin_lock(&pd_bitmap_lock);
1616 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1618 if (id > 0 && id < MAX_DOMAIN_ID)
1619 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1622 spin_unlock(&pd_bitmap_lock);
1627 static void domain_id_free(int id)
1629 spin_lock(&pd_bitmap_lock);
1630 if (id > 0 && id < MAX_DOMAIN_ID)
1631 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1632 spin_unlock(&pd_bitmap_lock);
1635 #define DEFINE_FREE_PT_FN(LVL, FN) \
1636 static void free_pt_##LVL (unsigned long __pt) \
1644 for (i = 0; i < 512; ++i) { \
1645 /* PTE present? */ \
1646 if (!IOMMU_PTE_PRESENT(pt[i])) \
1650 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1651 PM_PTE_LEVEL(pt[i]) == 7) \
1654 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1657 free_page((unsigned long)pt); \
1660 DEFINE_FREE_PT_FN(l2, free_page)
1661 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1662 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1663 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1664 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1666 static void free_pagetable(struct protection_domain *domain)
1668 unsigned long root = (unsigned long)domain->pt_root;
1670 switch (domain->mode) {
1671 case PAGE_MODE_NONE:
1673 case PAGE_MODE_1_LEVEL:
1676 case PAGE_MODE_2_LEVEL:
1679 case PAGE_MODE_3_LEVEL:
1682 case PAGE_MODE_4_LEVEL:
1685 case PAGE_MODE_5_LEVEL:
1688 case PAGE_MODE_6_LEVEL:
1696 static void free_gcr3_tbl_level1(u64 *tbl)
1701 for (i = 0; i < 512; ++i) {
1702 if (!(tbl[i] & GCR3_VALID))
1705 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1707 free_page((unsigned long)ptr);
1711 static void free_gcr3_tbl_level2(u64 *tbl)
1716 for (i = 0; i < 512; ++i) {
1717 if (!(tbl[i] & GCR3_VALID))
1720 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1722 free_gcr3_tbl_level1(ptr);
1726 static void free_gcr3_table(struct protection_domain *domain)
1728 if (domain->glx == 2)
1729 free_gcr3_tbl_level2(domain->gcr3_tbl);
1730 else if (domain->glx == 1)
1731 free_gcr3_tbl_level1(domain->gcr3_tbl);
1733 BUG_ON(domain->glx != 0);
1735 free_page((unsigned long)domain->gcr3_tbl);
1738 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1740 domain_flush_tlb(&dom->domain);
1741 domain_flush_complete(&dom->domain);
1744 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1746 struct dma_ops_domain *dom;
1748 dom = container_of(iovad, struct dma_ops_domain, iovad);
1750 dma_ops_domain_flush_tlb(dom);
1754 * Free a domain, only used if something went wrong in the
1755 * allocation path and we need to free an already allocated page table
1757 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1762 del_domain_from_list(&dom->domain);
1764 put_iova_domain(&dom->iovad);
1766 free_pagetable(&dom->domain);
1769 domain_id_free(dom->domain.id);
1775 * Allocates a new protection domain usable for the dma_ops functions.
1776 * It also initializes the page table and the address allocator data
1777 * structures required for the dma_ops interface
1779 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1781 struct dma_ops_domain *dma_dom;
1783 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1787 if (protection_domain_init(&dma_dom->domain))
1790 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1791 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1792 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1793 if (!dma_dom->domain.pt_root)
1796 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1798 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1801 /* Initialize reserved ranges */
1802 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1804 add_domain_to_list(&dma_dom->domain);
1809 dma_ops_domain_free(dma_dom);
1815 * little helper function to check whether a given protection domain is a
1818 static bool dma_ops_domain(struct protection_domain *domain)
1820 return domain->flags & PD_DMA_OPS_MASK;
1823 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1829 if (domain->mode != PAGE_MODE_NONE)
1830 pte_root = iommu_virt_to_phys(domain->pt_root);
1832 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1833 << DEV_ENTRY_MODE_SHIFT;
1834 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1836 flags = amd_iommu_dev_table[devid].data[1];
1839 flags |= DTE_FLAG_IOTLB;
1842 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1844 if (iommu_feature(iommu, FEATURE_EPHSUP))
1845 pte_root |= 1ULL << DEV_ENTRY_PPR;
1848 if (domain->flags & PD_IOMMUV2_MASK) {
1849 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1850 u64 glx = domain->glx;
1853 pte_root |= DTE_FLAG_GV;
1854 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1856 /* First mask out possible old values for GCR3 table */
1857 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1860 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1863 /* Encode GCR3 table into DTE */
1864 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1867 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1870 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1874 flags &= ~DEV_DOMID_MASK;
1875 flags |= domain->id;
1877 amd_iommu_dev_table[devid].data[1] = flags;
1878 amd_iommu_dev_table[devid].data[0] = pte_root;
1881 static void clear_dte_entry(u16 devid)
1883 /* remove entry from the device table seen by the hardware */
1884 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1885 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1887 amd_iommu_apply_erratum_63(devid);
1890 static void do_attach(struct iommu_dev_data *dev_data,
1891 struct protection_domain *domain)
1893 struct amd_iommu *iommu;
1897 iommu = amd_iommu_rlookup_table[dev_data->devid];
1898 alias = dev_data->alias;
1899 ats = dev_data->ats.enabled;
1901 /* Update data structures */
1902 dev_data->domain = domain;
1903 list_add(&dev_data->list, &domain->dev_list);
1905 /* Do reference counting */
1906 domain->dev_iommu[iommu->index] += 1;
1907 domain->dev_cnt += 1;
1909 /* Update device table */
1910 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1911 if (alias != dev_data->devid)
1912 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1914 device_flush_dte(dev_data);
1917 static void do_detach(struct iommu_dev_data *dev_data)
1919 struct amd_iommu *iommu;
1922 iommu = amd_iommu_rlookup_table[dev_data->devid];
1923 alias = dev_data->alias;
1925 /* decrease reference counters */
1926 dev_data->domain->dev_iommu[iommu->index] -= 1;
1927 dev_data->domain->dev_cnt -= 1;
1929 /* Update data structures */
1930 dev_data->domain = NULL;
1931 list_del(&dev_data->list);
1932 clear_dte_entry(dev_data->devid);
1933 if (alias != dev_data->devid)
1934 clear_dte_entry(alias);
1936 /* Flush the DTE entry */
1937 device_flush_dte(dev_data);
1941 * If a device is not yet associated with a domain, this function makes the
1942 * device visible in the domain
1944 static int __attach_device(struct iommu_dev_data *dev_data,
1945 struct protection_domain *domain)
1950 * Must be called with IRQs disabled. Warn here to detect early
1953 WARN_ON(!irqs_disabled());
1956 spin_lock(&domain->lock);
1959 if (dev_data->domain != NULL)
1962 /* Attach alias group root */
1963 do_attach(dev_data, domain);
1970 spin_unlock(&domain->lock);
1976 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1978 pci_disable_ats(pdev);
1979 pci_disable_pri(pdev);
1980 pci_disable_pasid(pdev);
1983 /* FIXME: Change generic reset-function to do the same */
1984 static int pri_reset_while_enabled(struct pci_dev *pdev)
1989 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1993 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1994 control |= PCI_PRI_CTRL_RESET;
1995 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2000 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2005 /* FIXME: Hardcode number of outstanding requests for now */
2007 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2009 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2011 /* Only allow access to user-accessible pages */
2012 ret = pci_enable_pasid(pdev, 0);
2016 /* First reset the PRI state of the device */
2017 ret = pci_reset_pri(pdev);
2022 ret = pci_enable_pri(pdev, reqs);
2027 ret = pri_reset_while_enabled(pdev);
2032 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2039 pci_disable_pri(pdev);
2040 pci_disable_pasid(pdev);
2045 /* FIXME: Move this to PCI code */
2046 #define PCI_PRI_TLP_OFF (1 << 15)
2048 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2053 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2057 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2059 return (status & PCI_PRI_TLP_OFF) ? true : false;
2063 * If a device is not yet associated with a domain, this function makes the
2064 * device visible in the domain
2066 static int attach_device(struct device *dev,
2067 struct protection_domain *domain)
2069 struct pci_dev *pdev;
2070 struct iommu_dev_data *dev_data;
2071 unsigned long flags;
2074 dev_data = get_dev_data(dev);
2076 if (!dev_is_pci(dev))
2077 goto skip_ats_check;
2079 pdev = to_pci_dev(dev);
2080 if (domain->flags & PD_IOMMUV2_MASK) {
2081 if (!dev_data->passthrough)
2084 if (dev_data->iommu_v2) {
2085 if (pdev_iommuv2_enable(pdev) != 0)
2088 dev_data->ats.enabled = true;
2089 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2090 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2092 } else if (amd_iommu_iotlb_sup &&
2093 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2094 dev_data->ats.enabled = true;
2095 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2099 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2100 ret = __attach_device(dev_data, domain);
2101 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2104 * We might boot into a crash-kernel here. The crashed kernel
2105 * left the caches in the IOMMU dirty. So we have to flush
2106 * here to evict all dirty stuff.
2108 domain_flush_tlb_pde(domain);
2114 * Removes a device from a protection domain (unlocked)
2116 static void __detach_device(struct iommu_dev_data *dev_data)
2118 struct protection_domain *domain;
2121 * Must be called with IRQs disabled. Warn here to detect early
2124 WARN_ON(!irqs_disabled());
2126 domain = dev_data->domain;
2128 spin_lock(&domain->lock);
2130 do_detach(dev_data);
2132 spin_unlock(&domain->lock);
2136 * Removes a device from a protection domain (with devtable_lock held)
2138 static void detach_device(struct device *dev)
2140 struct protection_domain *domain;
2141 struct iommu_dev_data *dev_data;
2142 unsigned long flags;
2144 dev_data = get_dev_data(dev);
2145 domain = dev_data->domain;
2148 * First check if the device is still attached. It might already
2149 * be detached from its domain because the generic
2150 * iommu_detach_group code detached it and we try again here in
2151 * our alias handling.
2153 if (WARN_ON(!dev_data->domain))
2156 /* lock device table */
2157 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2158 __detach_device(dev_data);
2159 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2161 if (!dev_is_pci(dev))
2164 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2165 pdev_iommuv2_disable(to_pci_dev(dev));
2166 else if (dev_data->ats.enabled)
2167 pci_disable_ats(to_pci_dev(dev));
2169 dev_data->ats.enabled = false;
2172 static int amd_iommu_add_device(struct device *dev)
2174 struct iommu_dev_data *dev_data;
2175 struct iommu_domain *domain;
2176 struct amd_iommu *iommu;
2179 if (!check_device(dev) || get_dev_data(dev))
2182 devid = get_device_id(dev);
2186 iommu = amd_iommu_rlookup_table[devid];
2188 ret = iommu_init_device(dev);
2190 if (ret != -ENOTSUPP)
2191 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2194 iommu_ignore_device(dev);
2195 dev->dma_ops = &dma_direct_ops;
2198 init_iommu_group(dev);
2200 dev_data = get_dev_data(dev);
2204 if (iommu_pass_through || dev_data->iommu_v2)
2205 iommu_request_dm_for_dev(dev);
2207 /* Domains are initialized for this device - have a look what we ended up with */
2208 domain = iommu_get_domain_for_dev(dev);
2209 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2210 dev_data->passthrough = true;
2212 dev->dma_ops = &amd_iommu_dma_ops;
2215 iommu_completion_wait(iommu);
2220 static void amd_iommu_remove_device(struct device *dev)
2222 struct amd_iommu *iommu;
2225 if (!check_device(dev))
2228 devid = get_device_id(dev);
2232 iommu = amd_iommu_rlookup_table[devid];
2234 iommu_uninit_device(dev);
2235 iommu_completion_wait(iommu);
2238 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2240 if (dev_is_pci(dev))
2241 return pci_device_group(dev);
2243 return acpihid_device_group(dev);
2246 /*****************************************************************************
2248 * The next functions belong to the dma_ops mapping/unmapping code.
2250 *****************************************************************************/
2253 * In the dma_ops path we only have the struct device. This function
2254 * finds the corresponding IOMMU, the protection domain and the
2255 * requestor id for a given device.
2256 * If the device is not yet associated with a domain this is also done
2259 static struct protection_domain *get_domain(struct device *dev)
2261 struct protection_domain *domain;
2262 struct iommu_domain *io_domain;
2264 if (!check_device(dev))
2265 return ERR_PTR(-EINVAL);
2267 domain = get_dev_data(dev)->domain;
2268 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2269 get_dev_data(dev)->defer_attach = false;
2270 io_domain = iommu_get_domain_for_dev(dev);
2271 domain = to_pdomain(io_domain);
2272 attach_device(dev, domain);
2275 return ERR_PTR(-EBUSY);
2277 if (!dma_ops_domain(domain))
2278 return ERR_PTR(-EBUSY);
2283 static void update_device_table(struct protection_domain *domain)
2285 struct iommu_dev_data *dev_data;
2287 list_for_each_entry(dev_data, &domain->dev_list, list) {
2288 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2289 dev_data->iommu_v2);
2291 if (dev_data->devid == dev_data->alias)
2294 /* There is an alias, update device table entry for it */
2295 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2296 dev_data->iommu_v2);
2300 static void update_domain(struct protection_domain *domain)
2302 if (!domain->updated)
2305 update_device_table(domain);
2307 domain_flush_devices(domain);
2308 domain_flush_tlb_pde(domain);
2310 domain->updated = false;
2313 static int dir2prot(enum dma_data_direction direction)
2315 if (direction == DMA_TO_DEVICE)
2316 return IOMMU_PROT_IR;
2317 else if (direction == DMA_FROM_DEVICE)
2318 return IOMMU_PROT_IW;
2319 else if (direction == DMA_BIDIRECTIONAL)
2320 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2326 * This function contains common code for mapping of a physically
2327 * contiguous memory region into DMA address space. It is used by all
2328 * mapping functions provided with this IOMMU driver.
2329 * Must be called with the domain lock held.
2331 static dma_addr_t __map_single(struct device *dev,
2332 struct dma_ops_domain *dma_dom,
2335 enum dma_data_direction direction,
2338 dma_addr_t offset = paddr & ~PAGE_MASK;
2339 dma_addr_t address, start, ret;
2344 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2347 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2348 if (address == AMD_IOMMU_MAPPING_ERROR)
2351 prot = dir2prot(direction);
2354 for (i = 0; i < pages; ++i) {
2355 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2356 PAGE_SIZE, prot, GFP_ATOMIC);
2365 if (unlikely(amd_iommu_np_cache)) {
2366 domain_flush_pages(&dma_dom->domain, address, size);
2367 domain_flush_complete(&dma_dom->domain);
2375 for (--i; i >= 0; --i) {
2377 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2380 domain_flush_tlb(&dma_dom->domain);
2381 domain_flush_complete(&dma_dom->domain);
2383 dma_ops_free_iova(dma_dom, address, pages);
2385 return AMD_IOMMU_MAPPING_ERROR;
2389 * Does the reverse of the __map_single function. Must be called with
2390 * the domain lock held too
2392 static void __unmap_single(struct dma_ops_domain *dma_dom,
2393 dma_addr_t dma_addr,
2397 dma_addr_t i, start;
2400 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2401 dma_addr &= PAGE_MASK;
2404 for (i = 0; i < pages; ++i) {
2405 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2409 if (amd_iommu_unmap_flush) {
2410 domain_flush_tlb(&dma_dom->domain);
2411 domain_flush_complete(&dma_dom->domain);
2412 dma_ops_free_iova(dma_dom, dma_addr, pages);
2414 pages = __roundup_pow_of_two(pages);
2415 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2420 * The exported map_single function for dma_ops.
2422 static dma_addr_t map_page(struct device *dev, struct page *page,
2423 unsigned long offset, size_t size,
2424 enum dma_data_direction dir,
2425 unsigned long attrs)
2427 phys_addr_t paddr = page_to_phys(page) + offset;
2428 struct protection_domain *domain;
2429 struct dma_ops_domain *dma_dom;
2432 domain = get_domain(dev);
2433 if (PTR_ERR(domain) == -EINVAL)
2434 return (dma_addr_t)paddr;
2435 else if (IS_ERR(domain))
2436 return AMD_IOMMU_MAPPING_ERROR;
2438 dma_mask = *dev->dma_mask;
2439 dma_dom = to_dma_ops_domain(domain);
2441 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2445 * The exported unmap_single function for dma_ops.
2447 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2448 enum dma_data_direction dir, unsigned long attrs)
2450 struct protection_domain *domain;
2451 struct dma_ops_domain *dma_dom;
2453 domain = get_domain(dev);
2457 dma_dom = to_dma_ops_domain(domain);
2459 __unmap_single(dma_dom, dma_addr, size, dir);
2462 static int sg_num_pages(struct device *dev,
2463 struct scatterlist *sglist,
2466 unsigned long mask, boundary_size;
2467 struct scatterlist *s;
2470 mask = dma_get_seg_boundary(dev);
2471 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2472 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2474 for_each_sg(sglist, s, nelems, i) {
2477 s->dma_address = npages << PAGE_SHIFT;
2478 p = npages % boundary_size;
2479 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2480 if (p + n > boundary_size)
2481 npages += boundary_size - p;
2489 * The exported map_sg function for dma_ops (handles scatter-gather
2492 static int map_sg(struct device *dev, struct scatterlist *sglist,
2493 int nelems, enum dma_data_direction direction,
2494 unsigned long attrs)
2496 int mapped_pages = 0, npages = 0, prot = 0, i;
2497 struct protection_domain *domain;
2498 struct dma_ops_domain *dma_dom;
2499 struct scatterlist *s;
2500 unsigned long address;
2503 domain = get_domain(dev);
2507 dma_dom = to_dma_ops_domain(domain);
2508 dma_mask = *dev->dma_mask;
2510 npages = sg_num_pages(dev, sglist, nelems);
2512 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2513 if (address == AMD_IOMMU_MAPPING_ERROR)
2516 prot = dir2prot(direction);
2518 /* Map all sg entries */
2519 for_each_sg(sglist, s, nelems, i) {
2520 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2522 for (j = 0; j < pages; ++j) {
2523 unsigned long bus_addr, phys_addr;
2526 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2527 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2528 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2536 /* Everything is mapped - write the right values into s->dma_address */
2537 for_each_sg(sglist, s, nelems, i) {
2538 s->dma_address += address + s->offset;
2539 s->dma_length = s->length;
2545 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2546 dev_name(dev), npages);
2548 for_each_sg(sglist, s, nelems, i) {
2549 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2551 for (j = 0; j < pages; ++j) {
2552 unsigned long bus_addr;
2554 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2555 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2563 free_iova_fast(&dma_dom->iovad, address, npages);
2570 * The exported map_sg function for dma_ops (handles scatter-gather
2573 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2574 int nelems, enum dma_data_direction dir,
2575 unsigned long attrs)
2577 struct protection_domain *domain;
2578 struct dma_ops_domain *dma_dom;
2579 unsigned long startaddr;
2582 domain = get_domain(dev);
2586 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2587 dma_dom = to_dma_ops_domain(domain);
2588 npages = sg_num_pages(dev, sglist, nelems);
2590 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2594 * The exported alloc_coherent function for dma_ops.
2596 static void *alloc_coherent(struct device *dev, size_t size,
2597 dma_addr_t *dma_addr, gfp_t flag,
2598 unsigned long attrs)
2600 u64 dma_mask = dev->coherent_dma_mask;
2601 struct protection_domain *domain;
2602 struct dma_ops_domain *dma_dom;
2605 domain = get_domain(dev);
2606 if (PTR_ERR(domain) == -EINVAL) {
2607 page = alloc_pages(flag, get_order(size));
2608 *dma_addr = page_to_phys(page);
2609 return page_address(page);
2610 } else if (IS_ERR(domain))
2613 dma_dom = to_dma_ops_domain(domain);
2614 size = PAGE_ALIGN(size);
2615 dma_mask = dev->coherent_dma_mask;
2616 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2619 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2621 if (!gfpflags_allow_blocking(flag))
2624 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2625 get_order(size), flag);
2631 dma_mask = *dev->dma_mask;
2633 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2634 size, DMA_BIDIRECTIONAL, dma_mask);
2636 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2639 return page_address(page);
2643 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2644 __free_pages(page, get_order(size));
2650 * The exported free_coherent function for dma_ops.
2652 static void free_coherent(struct device *dev, size_t size,
2653 void *virt_addr, dma_addr_t dma_addr,
2654 unsigned long attrs)
2656 struct protection_domain *domain;
2657 struct dma_ops_domain *dma_dom;
2660 page = virt_to_page(virt_addr);
2661 size = PAGE_ALIGN(size);
2663 domain = get_domain(dev);
2667 dma_dom = to_dma_ops_domain(domain);
2669 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2672 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2673 __free_pages(page, get_order(size));
2677 * This function is called by the DMA layer to find out if we can handle a
2678 * particular device. It is part of the dma_ops.
2680 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2682 if (!dma_direct_supported(dev, mask))
2684 return check_device(dev);
2687 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2689 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2692 static const struct dma_map_ops amd_iommu_dma_ops = {
2693 .alloc = alloc_coherent,
2694 .free = free_coherent,
2695 .map_page = map_page,
2696 .unmap_page = unmap_page,
2698 .unmap_sg = unmap_sg,
2699 .dma_supported = amd_iommu_dma_supported,
2700 .mapping_error = amd_iommu_mapping_error,
2703 static int init_reserved_iova_ranges(void)
2705 struct pci_dev *pdev = NULL;
2708 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2710 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2711 &reserved_rbtree_key);
2713 /* MSI memory range */
2714 val = reserve_iova(&reserved_iova_ranges,
2715 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2717 pr_err("Reserving MSI range failed\n");
2721 /* HT memory range */
2722 val = reserve_iova(&reserved_iova_ranges,
2723 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2725 pr_err("Reserving HT range failed\n");
2730 * Memory used for PCI resources
2731 * FIXME: Check whether we can reserve the PCI-hole completly
2733 for_each_pci_dev(pdev) {
2736 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2737 struct resource *r = &pdev->resource[i];
2739 if (!(r->flags & IORESOURCE_MEM))
2742 val = reserve_iova(&reserved_iova_ranges,
2746 pr_err("Reserve pci-resource range failed\n");
2755 int __init amd_iommu_init_api(void)
2759 ret = iova_cache_get();
2763 ret = init_reserved_iova_ranges();
2767 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2770 #ifdef CONFIG_ARM_AMBA
2771 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2775 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2782 int __init amd_iommu_init_dma_ops(void)
2784 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2788 * In case we don't initialize SWIOTLB (actually the common case
2789 * when AMD IOMMU is enabled and SME is not active), make sure there
2790 * are global dma_ops set as a fall-back for devices not handled by
2791 * this driver (for example non-PCI devices). When SME is active,
2792 * make sure that swiotlb variable remains set so the global dma_ops
2793 * continue to be SWIOTLB.
2796 dma_ops = &dma_direct_ops;
2798 if (amd_iommu_unmap_flush)
2799 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2801 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2807 /*****************************************************************************
2809 * The following functions belong to the exported interface of AMD IOMMU
2811 * This interface allows access to lower level functions of the IOMMU
2812 * like protection domain handling and assignement of devices to domains
2813 * which is not possible with the dma_ops interface.
2815 *****************************************************************************/
2817 static void cleanup_domain(struct protection_domain *domain)
2819 struct iommu_dev_data *entry;
2820 unsigned long flags;
2822 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2824 while (!list_empty(&domain->dev_list)) {
2825 entry = list_first_entry(&domain->dev_list,
2826 struct iommu_dev_data, list);
2827 BUG_ON(!entry->domain);
2828 __detach_device(entry);
2831 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2834 static void protection_domain_free(struct protection_domain *domain)
2839 del_domain_from_list(domain);
2842 domain_id_free(domain->id);
2847 static int protection_domain_init(struct protection_domain *domain)
2849 spin_lock_init(&domain->lock);
2850 mutex_init(&domain->api_lock);
2851 domain->id = domain_id_alloc();
2854 INIT_LIST_HEAD(&domain->dev_list);
2859 static struct protection_domain *protection_domain_alloc(void)
2861 struct protection_domain *domain;
2863 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2867 if (protection_domain_init(domain))
2870 add_domain_to_list(domain);
2880 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2882 struct protection_domain *pdomain;
2883 struct dma_ops_domain *dma_domain;
2886 case IOMMU_DOMAIN_UNMANAGED:
2887 pdomain = protection_domain_alloc();
2891 pdomain->mode = PAGE_MODE_3_LEVEL;
2892 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2893 if (!pdomain->pt_root) {
2894 protection_domain_free(pdomain);
2898 pdomain->domain.geometry.aperture_start = 0;
2899 pdomain->domain.geometry.aperture_end = ~0ULL;
2900 pdomain->domain.geometry.force_aperture = true;
2903 case IOMMU_DOMAIN_DMA:
2904 dma_domain = dma_ops_domain_alloc();
2906 pr_err("AMD-Vi: Failed to allocate\n");
2909 pdomain = &dma_domain->domain;
2911 case IOMMU_DOMAIN_IDENTITY:
2912 pdomain = protection_domain_alloc();
2916 pdomain->mode = PAGE_MODE_NONE;
2922 return &pdomain->domain;
2925 static void amd_iommu_domain_free(struct iommu_domain *dom)
2927 struct protection_domain *domain;
2928 struct dma_ops_domain *dma_dom;
2930 domain = to_pdomain(dom);
2932 if (domain->dev_cnt > 0)
2933 cleanup_domain(domain);
2935 BUG_ON(domain->dev_cnt != 0);
2940 switch (dom->type) {
2941 case IOMMU_DOMAIN_DMA:
2942 /* Now release the domain */
2943 dma_dom = to_dma_ops_domain(domain);
2944 dma_ops_domain_free(dma_dom);
2947 if (domain->mode != PAGE_MODE_NONE)
2948 free_pagetable(domain);
2950 if (domain->flags & PD_IOMMUV2_MASK)
2951 free_gcr3_table(domain);
2953 protection_domain_free(domain);
2958 static void amd_iommu_detach_device(struct iommu_domain *dom,
2961 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2962 struct amd_iommu *iommu;
2965 if (!check_device(dev))
2968 devid = get_device_id(dev);
2972 if (dev_data->domain != NULL)
2975 iommu = amd_iommu_rlookup_table[devid];
2979 #ifdef CONFIG_IRQ_REMAP
2980 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2981 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2982 dev_data->use_vapic = 0;
2985 iommu_completion_wait(iommu);
2988 static int amd_iommu_attach_device(struct iommu_domain *dom,
2991 struct protection_domain *domain = to_pdomain(dom);
2992 struct iommu_dev_data *dev_data;
2993 struct amd_iommu *iommu;
2996 if (!check_device(dev))
2999 dev_data = dev->archdata.iommu;
3001 iommu = amd_iommu_rlookup_table[dev_data->devid];
3005 if (dev_data->domain)
3008 ret = attach_device(dev, domain);
3010 #ifdef CONFIG_IRQ_REMAP
3011 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3012 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3013 dev_data->use_vapic = 1;
3015 dev_data->use_vapic = 0;
3019 iommu_completion_wait(iommu);
3024 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3025 phys_addr_t paddr, size_t page_size, int iommu_prot)
3027 struct protection_domain *domain = to_pdomain(dom);
3031 if (domain->mode == PAGE_MODE_NONE)
3034 if (iommu_prot & IOMMU_READ)
3035 prot |= IOMMU_PROT_IR;
3036 if (iommu_prot & IOMMU_WRITE)
3037 prot |= IOMMU_PROT_IW;
3039 mutex_lock(&domain->api_lock);
3040 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3041 mutex_unlock(&domain->api_lock);
3046 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3049 struct protection_domain *domain = to_pdomain(dom);
3052 if (domain->mode == PAGE_MODE_NONE)
3055 mutex_lock(&domain->api_lock);
3056 unmap_size = iommu_unmap_page(domain, iova, page_size);
3057 mutex_unlock(&domain->api_lock);
3062 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3065 struct protection_domain *domain = to_pdomain(dom);
3066 unsigned long offset_mask, pte_pgsize;
3069 if (domain->mode == PAGE_MODE_NONE)
3072 pte = fetch_pte(domain, iova, &pte_pgsize);
3074 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3077 offset_mask = pte_pgsize - 1;
3078 __pte = *pte & PM_ADDR_MASK;
3080 return (__pte & ~offset_mask) | (iova & offset_mask);
3083 static bool amd_iommu_capable(enum iommu_cap cap)
3086 case IOMMU_CAP_CACHE_COHERENCY:
3088 case IOMMU_CAP_INTR_REMAP:
3089 return (irq_remapping_enabled == 1);
3090 case IOMMU_CAP_NOEXEC:
3097 static void amd_iommu_get_resv_regions(struct device *dev,
3098 struct list_head *head)
3100 struct iommu_resv_region *region;
3101 struct unity_map_entry *entry;
3104 devid = get_device_id(dev);
3108 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3112 if (devid < entry->devid_start || devid > entry->devid_end)
3115 length = entry->address_end - entry->address_start;
3116 if (entry->prot & IOMMU_PROT_IR)
3118 if (entry->prot & IOMMU_PROT_IW)
3119 prot |= IOMMU_WRITE;
3121 region = iommu_alloc_resv_region(entry->address_start,
3125 pr_err("Out of memory allocating dm-regions for %s\n",
3129 list_add_tail(®ion->list, head);
3132 region = iommu_alloc_resv_region(MSI_RANGE_START,
3133 MSI_RANGE_END - MSI_RANGE_START + 1,
3137 list_add_tail(®ion->list, head);
3139 region = iommu_alloc_resv_region(HT_RANGE_START,
3140 HT_RANGE_END - HT_RANGE_START + 1,
3141 0, IOMMU_RESV_RESERVED);
3144 list_add_tail(®ion->list, head);
3147 static void amd_iommu_put_resv_regions(struct device *dev,
3148 struct list_head *head)
3150 struct iommu_resv_region *entry, *next;
3152 list_for_each_entry_safe(entry, next, head, list)
3156 static void amd_iommu_apply_resv_region(struct device *dev,
3157 struct iommu_domain *domain,
3158 struct iommu_resv_region *region)
3160 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3161 unsigned long start, end;
3163 start = IOVA_PFN(region->start);
3164 end = IOVA_PFN(region->start + region->length - 1);
3166 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3169 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3172 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3173 return dev_data->defer_attach;
3176 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3178 struct protection_domain *dom = to_pdomain(domain);
3180 domain_flush_tlb_pde(dom);
3181 domain_flush_complete(dom);
3184 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3185 unsigned long iova, size_t size)
3189 const struct iommu_ops amd_iommu_ops = {
3190 .capable = amd_iommu_capable,
3191 .domain_alloc = amd_iommu_domain_alloc,
3192 .domain_free = amd_iommu_domain_free,
3193 .attach_dev = amd_iommu_attach_device,
3194 .detach_dev = amd_iommu_detach_device,
3195 .map = amd_iommu_map,
3196 .unmap = amd_iommu_unmap,
3197 .map_sg = default_iommu_map_sg,
3198 .iova_to_phys = amd_iommu_iova_to_phys,
3199 .add_device = amd_iommu_add_device,
3200 .remove_device = amd_iommu_remove_device,
3201 .device_group = amd_iommu_device_group,
3202 .get_resv_regions = amd_iommu_get_resv_regions,
3203 .put_resv_regions = amd_iommu_put_resv_regions,
3204 .apply_resv_region = amd_iommu_apply_resv_region,
3205 .is_attach_deferred = amd_iommu_is_attach_deferred,
3206 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3207 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3208 .iotlb_range_add = amd_iommu_iotlb_range_add,
3209 .iotlb_sync = amd_iommu_flush_iotlb_all,
3212 /*****************************************************************************
3214 * The next functions do a basic initialization of IOMMU for pass through
3217 * In passthrough mode the IOMMU is initialized and enabled but not used for
3218 * DMA-API translation.
3220 *****************************************************************************/
3222 /* IOMMUv2 specific functions */
3223 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3225 return atomic_notifier_chain_register(&ppr_notifier, nb);
3227 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3229 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3231 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3233 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3235 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3237 struct protection_domain *domain = to_pdomain(dom);
3238 unsigned long flags;
3240 spin_lock_irqsave(&domain->lock, flags);
3242 /* Update data structure */
3243 domain->mode = PAGE_MODE_NONE;
3244 domain->updated = true;
3246 /* Make changes visible to IOMMUs */
3247 update_domain(domain);
3249 /* Page-table is not visible to IOMMU anymore, so free it */
3250 free_pagetable(domain);
3252 spin_unlock_irqrestore(&domain->lock, flags);
3254 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3256 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3258 struct protection_domain *domain = to_pdomain(dom);
3259 unsigned long flags;
3262 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3265 /* Number of GCR3 table levels required */
3266 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3269 if (levels > amd_iommu_max_glx_val)
3272 spin_lock_irqsave(&domain->lock, flags);
3275 * Save us all sanity checks whether devices already in the
3276 * domain support IOMMUv2. Just force that the domain has no
3277 * devices attached when it is switched into IOMMUv2 mode.
3280 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3284 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3285 if (domain->gcr3_tbl == NULL)
3288 domain->glx = levels;
3289 domain->flags |= PD_IOMMUV2_MASK;
3290 domain->updated = true;
3292 update_domain(domain);
3297 spin_unlock_irqrestore(&domain->lock, flags);
3301 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3303 static int __flush_pasid(struct protection_domain *domain, int pasid,
3304 u64 address, bool size)
3306 struct iommu_dev_data *dev_data;
3307 struct iommu_cmd cmd;
3310 if (!(domain->flags & PD_IOMMUV2_MASK))
3313 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3316 * IOMMU TLB needs to be flushed before Device TLB to
3317 * prevent device TLB refill from IOMMU TLB
3319 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3320 if (domain->dev_iommu[i] == 0)
3323 ret = iommu_queue_command(amd_iommus[i], &cmd);
3328 /* Wait until IOMMU TLB flushes are complete */
3329 domain_flush_complete(domain);
3331 /* Now flush device TLBs */
3332 list_for_each_entry(dev_data, &domain->dev_list, list) {
3333 struct amd_iommu *iommu;
3337 There might be non-IOMMUv2 capable devices in an IOMMUv2
3340 if (!dev_data->ats.enabled)
3343 qdep = dev_data->ats.qdep;
3344 iommu = amd_iommu_rlookup_table[dev_data->devid];
3346 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3347 qdep, address, size);
3349 ret = iommu_queue_command(iommu, &cmd);
3354 /* Wait until all device TLBs are flushed */
3355 domain_flush_complete(domain);
3364 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3367 return __flush_pasid(domain, pasid, address, false);
3370 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3373 struct protection_domain *domain = to_pdomain(dom);
3374 unsigned long flags;
3377 spin_lock_irqsave(&domain->lock, flags);
3378 ret = __amd_iommu_flush_page(domain, pasid, address);
3379 spin_unlock_irqrestore(&domain->lock, flags);
3383 EXPORT_SYMBOL(amd_iommu_flush_page);
3385 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3387 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3391 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3393 struct protection_domain *domain = to_pdomain(dom);
3394 unsigned long flags;
3397 spin_lock_irqsave(&domain->lock, flags);
3398 ret = __amd_iommu_flush_tlb(domain, pasid);
3399 spin_unlock_irqrestore(&domain->lock, flags);
3403 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3405 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3412 index = (pasid >> (9 * level)) & 0x1ff;
3418 if (!(*pte & GCR3_VALID)) {
3422 root = (void *)get_zeroed_page(GFP_ATOMIC);
3426 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3429 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3437 static int __set_gcr3(struct protection_domain *domain, int pasid,
3442 if (domain->mode != PAGE_MODE_NONE)
3445 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3449 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3451 return __amd_iommu_flush_tlb(domain, pasid);
3454 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3458 if (domain->mode != PAGE_MODE_NONE)
3461 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3467 return __amd_iommu_flush_tlb(domain, pasid);
3470 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3473 struct protection_domain *domain = to_pdomain(dom);
3474 unsigned long flags;
3477 spin_lock_irqsave(&domain->lock, flags);
3478 ret = __set_gcr3(domain, pasid, cr3);
3479 spin_unlock_irqrestore(&domain->lock, flags);
3483 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3485 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3487 struct protection_domain *domain = to_pdomain(dom);
3488 unsigned long flags;
3491 spin_lock_irqsave(&domain->lock, flags);
3492 ret = __clear_gcr3(domain, pasid);
3493 spin_unlock_irqrestore(&domain->lock, flags);
3497 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3499 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3500 int status, int tag)
3502 struct iommu_dev_data *dev_data;
3503 struct amd_iommu *iommu;
3504 struct iommu_cmd cmd;
3506 dev_data = get_dev_data(&pdev->dev);
3507 iommu = amd_iommu_rlookup_table[dev_data->devid];
3509 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3510 tag, dev_data->pri_tlp);
3512 return iommu_queue_command(iommu, &cmd);
3514 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3516 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3518 struct protection_domain *pdomain;
3520 pdomain = get_domain(&pdev->dev);
3521 if (IS_ERR(pdomain))
3524 /* Only return IOMMUv2 domains */
3525 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3528 return &pdomain->domain;
3530 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3532 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3534 struct iommu_dev_data *dev_data;
3536 if (!amd_iommu_v2_supported())
3539 dev_data = get_dev_data(&pdev->dev);
3540 dev_data->errata |= (1 << erratum);
3542 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3544 int amd_iommu_device_info(struct pci_dev *pdev,
3545 struct amd_iommu_device_info *info)
3550 if (pdev == NULL || info == NULL)
3553 if (!amd_iommu_v2_supported())
3556 memset(info, 0, sizeof(*info));
3558 if (!pci_ats_disabled()) {
3559 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3561 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3564 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3566 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3568 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3572 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3573 max_pasids = min(max_pasids, (1 << 20));
3575 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3576 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3578 features = pci_pasid_features(pdev);
3579 if (features & PCI_PASID_CAP_EXEC)
3580 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3581 if (features & PCI_PASID_CAP_PRIV)
3582 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3587 EXPORT_SYMBOL(amd_iommu_device_info);
3589 #ifdef CONFIG_IRQ_REMAP
3591 /*****************************************************************************
3593 * Interrupt Remapping Implementation
3595 *****************************************************************************/
3597 static struct irq_chip amd_ir_chip;
3598 static DEFINE_SPINLOCK(iommu_table_lock);
3600 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3604 dte = amd_iommu_dev_table[devid].data[2];
3605 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3606 dte |= iommu_virt_to_phys(table->table);
3607 dte |= DTE_IRQ_REMAP_INTCTL;
3608 dte |= DTE_IRQ_TABLE_LEN;
3609 dte |= DTE_IRQ_REMAP_ENABLE;
3611 amd_iommu_dev_table[devid].data[2] = dte;
3614 static struct irq_remap_table *get_irq_table(u16 devid)
3616 struct irq_remap_table *table;
3618 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3619 "%s: no iommu for devid %x\n", __func__, devid))
3622 table = irq_lookup_table[devid];
3623 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3629 static struct irq_remap_table *__alloc_irq_table(void)
3631 struct irq_remap_table *table;
3633 table = kzalloc(sizeof(*table), GFP_KERNEL);
3637 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3638 if (!table->table) {
3642 raw_spin_lock_init(&table->lock);
3644 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3645 memset(table->table, 0,
3646 MAX_IRQS_PER_TABLE * sizeof(u32));
3648 memset(table->table, 0,
3649 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3653 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3654 struct irq_remap_table *table)
3656 irq_lookup_table[devid] = table;
3657 set_dte_irq_entry(devid, table);
3658 iommu_flush_dte(iommu, devid);
3661 static struct irq_remap_table *alloc_irq_table(u16 devid)
3663 struct irq_remap_table *table = NULL;
3664 struct irq_remap_table *new_table = NULL;
3665 struct amd_iommu *iommu;
3666 unsigned long flags;
3669 spin_lock_irqsave(&iommu_table_lock, flags);
3671 iommu = amd_iommu_rlookup_table[devid];
3675 table = irq_lookup_table[devid];
3679 alias = amd_iommu_alias_table[devid];
3680 table = irq_lookup_table[alias];
3682 set_remap_table_entry(iommu, devid, table);
3685 spin_unlock_irqrestore(&iommu_table_lock, flags);
3687 /* Nothing there yet, allocate new irq remapping table */
3688 new_table = __alloc_irq_table();
3692 spin_lock_irqsave(&iommu_table_lock, flags);
3694 table = irq_lookup_table[devid];
3698 table = irq_lookup_table[alias];
3700 set_remap_table_entry(iommu, devid, table);
3707 set_remap_table_entry(iommu, devid, table);
3709 set_remap_table_entry(iommu, alias, table);
3712 iommu_completion_wait(iommu);
3715 spin_unlock_irqrestore(&iommu_table_lock, flags);
3718 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3724 static int alloc_irq_index(u16 devid, int count, bool align)
3726 struct irq_remap_table *table;
3727 int index, c, alignment = 1;
3728 unsigned long flags;
3729 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3734 table = alloc_irq_table(devid);
3739 alignment = roundup_pow_of_two(count);
3741 raw_spin_lock_irqsave(&table->lock, flags);
3743 /* Scan table for free entries */
3744 for (index = ALIGN(table->min_index, alignment), c = 0;
3745 index < MAX_IRQS_PER_TABLE;) {
3746 if (!iommu->irte_ops->is_allocated(table, index)) {
3750 index = ALIGN(index + 1, alignment);
3756 iommu->irte_ops->set_allocated(table, index - c + 1);
3768 raw_spin_unlock_irqrestore(&table->lock, flags);
3773 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3774 struct amd_ir_data *data)
3776 struct irq_remap_table *table;
3777 struct amd_iommu *iommu;
3778 unsigned long flags;
3779 struct irte_ga *entry;
3781 iommu = amd_iommu_rlookup_table[devid];
3785 table = get_irq_table(devid);
3789 raw_spin_lock_irqsave(&table->lock, flags);
3791 entry = (struct irte_ga *)table->table;
3792 entry = &entry[index];
3793 entry->lo.fields_remap.valid = 0;
3794 entry->hi.val = irte->hi.val;
3795 entry->lo.val = irte->lo.val;
3796 entry->lo.fields_remap.valid = 1;
3800 raw_spin_unlock_irqrestore(&table->lock, flags);
3802 iommu_flush_irt(iommu, devid);
3803 iommu_completion_wait(iommu);
3808 static int modify_irte(u16 devid, int index, union irte *irte)
3810 struct irq_remap_table *table;
3811 struct amd_iommu *iommu;
3812 unsigned long flags;
3814 iommu = amd_iommu_rlookup_table[devid];
3818 table = get_irq_table(devid);
3822 raw_spin_lock_irqsave(&table->lock, flags);
3823 table->table[index] = irte->val;
3824 raw_spin_unlock_irqrestore(&table->lock, flags);
3826 iommu_flush_irt(iommu, devid);
3827 iommu_completion_wait(iommu);
3832 static void free_irte(u16 devid, int index)
3834 struct irq_remap_table *table;
3835 struct amd_iommu *iommu;
3836 unsigned long flags;
3838 iommu = amd_iommu_rlookup_table[devid];
3842 table = get_irq_table(devid);
3846 raw_spin_lock_irqsave(&table->lock, flags);
3847 iommu->irte_ops->clear_allocated(table, index);
3848 raw_spin_unlock_irqrestore(&table->lock, flags);
3850 iommu_flush_irt(iommu, devid);
3851 iommu_completion_wait(iommu);
3854 static void irte_prepare(void *entry,
3855 u32 delivery_mode, u32 dest_mode,
3856 u8 vector, u32 dest_apicid, int devid)
3858 union irte *irte = (union irte *) entry;
3861 irte->fields.vector = vector;
3862 irte->fields.int_type = delivery_mode;
3863 irte->fields.destination = dest_apicid;
3864 irte->fields.dm = dest_mode;
3865 irte->fields.valid = 1;
3868 static void irte_ga_prepare(void *entry,
3869 u32 delivery_mode, u32 dest_mode,
3870 u8 vector, u32 dest_apicid, int devid)
3872 struct irte_ga *irte = (struct irte_ga *) entry;
3876 irte->lo.fields_remap.int_type = delivery_mode;
3877 irte->lo.fields_remap.dm = dest_mode;
3878 irte->hi.fields.vector = vector;
3879 irte->lo.fields_remap.destination = dest_apicid;
3880 irte->lo.fields_remap.valid = 1;
3883 static void irte_activate(void *entry, u16 devid, u16 index)
3885 union irte *irte = (union irte *) entry;
3887 irte->fields.valid = 1;
3888 modify_irte(devid, index, irte);
3891 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3893 struct irte_ga *irte = (struct irte_ga *) entry;
3895 irte->lo.fields_remap.valid = 1;
3896 modify_irte_ga(devid, index, irte, NULL);
3899 static void irte_deactivate(void *entry, u16 devid, u16 index)
3901 union irte *irte = (union irte *) entry;
3903 irte->fields.valid = 0;
3904 modify_irte(devid, index, irte);
3907 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3909 struct irte_ga *irte = (struct irte_ga *) entry;
3911 irte->lo.fields_remap.valid = 0;
3912 modify_irte_ga(devid, index, irte, NULL);
3915 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3916 u8 vector, u32 dest_apicid)
3918 union irte *irte = (union irte *) entry;
3920 irte->fields.vector = vector;
3921 irte->fields.destination = dest_apicid;
3922 modify_irte(devid, index, irte);
3925 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3926 u8 vector, u32 dest_apicid)
3928 struct irte_ga *irte = (struct irte_ga *) entry;
3930 if (!irte->lo.fields_remap.guest_mode) {
3931 irte->hi.fields.vector = vector;
3932 irte->lo.fields_remap.destination = dest_apicid;
3933 modify_irte_ga(devid, index, irte, NULL);
3937 #define IRTE_ALLOCATED (~1U)
3938 static void irte_set_allocated(struct irq_remap_table *table, int index)
3940 table->table[index] = IRTE_ALLOCATED;
3943 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3945 struct irte_ga *ptr = (struct irte_ga *)table->table;
3946 struct irte_ga *irte = &ptr[index];
3948 memset(&irte->lo.val, 0, sizeof(u64));
3949 memset(&irte->hi.val, 0, sizeof(u64));
3950 irte->hi.fields.vector = 0xff;
3953 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3955 union irte *ptr = (union irte *)table->table;
3956 union irte *irte = &ptr[index];
3958 return irte->val != 0;
3961 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3963 struct irte_ga *ptr = (struct irte_ga *)table->table;
3964 struct irte_ga *irte = &ptr[index];
3966 return irte->hi.fields.vector != 0;
3969 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3971 table->table[index] = 0;
3974 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3976 struct irte_ga *ptr = (struct irte_ga *)table->table;
3977 struct irte_ga *irte = &ptr[index];
3979 memset(&irte->lo.val, 0, sizeof(u64));
3980 memset(&irte->hi.val, 0, sizeof(u64));
3983 static int get_devid(struct irq_alloc_info *info)
3987 switch (info->type) {
3988 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3989 devid = get_ioapic_devid(info->ioapic_id);
3991 case X86_IRQ_ALLOC_TYPE_HPET:
3992 devid = get_hpet_devid(info->hpet_id);
3994 case X86_IRQ_ALLOC_TYPE_MSI:
3995 case X86_IRQ_ALLOC_TYPE_MSIX:
3996 devid = get_device_id(&info->msi_dev->dev);
4006 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4008 struct amd_iommu *iommu;
4014 devid = get_devid(info);
4016 iommu = amd_iommu_rlookup_table[devid];
4018 return iommu->ir_domain;
4024 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4026 struct amd_iommu *iommu;
4032 switch (info->type) {
4033 case X86_IRQ_ALLOC_TYPE_MSI:
4034 case X86_IRQ_ALLOC_TYPE_MSIX:
4035 devid = get_device_id(&info->msi_dev->dev);
4039 iommu = amd_iommu_rlookup_table[devid];
4041 return iommu->msi_domain;
4050 struct irq_remap_ops amd_iommu_irq_ops = {
4051 .prepare = amd_iommu_prepare,
4052 .enable = amd_iommu_enable,
4053 .disable = amd_iommu_disable,
4054 .reenable = amd_iommu_reenable,
4055 .enable_faulting = amd_iommu_enable_faulting,
4056 .get_ir_irq_domain = get_ir_irq_domain,
4057 .get_irq_domain = get_irq_domain,
4060 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4061 struct irq_cfg *irq_cfg,
4062 struct irq_alloc_info *info,
4063 int devid, int index, int sub_handle)
4065 struct irq_2_irte *irte_info = &data->irq_2_irte;
4066 struct msi_msg *msg = &data->msi_entry;
4067 struct IO_APIC_route_entry *entry;
4068 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4073 data->irq_2_irte.devid = devid;
4074 data->irq_2_irte.index = index + sub_handle;
4075 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4076 apic->irq_dest_mode, irq_cfg->vector,
4077 irq_cfg->dest_apicid, devid);
4079 switch (info->type) {
4080 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4081 /* Setup IOAPIC entry */
4082 entry = info->ioapic_entry;
4083 info->ioapic_entry = NULL;
4084 memset(entry, 0, sizeof(*entry));
4085 entry->vector = index;
4087 entry->trigger = info->ioapic_trigger;
4088 entry->polarity = info->ioapic_polarity;
4089 /* Mask level triggered irqs. */
4090 if (info->ioapic_trigger)
4094 case X86_IRQ_ALLOC_TYPE_HPET:
4095 case X86_IRQ_ALLOC_TYPE_MSI:
4096 case X86_IRQ_ALLOC_TYPE_MSIX:
4097 msg->address_hi = MSI_ADDR_BASE_HI;
4098 msg->address_lo = MSI_ADDR_BASE_LO;
4099 msg->data = irte_info->index;
4108 struct amd_irte_ops irte_32_ops = {
4109 .prepare = irte_prepare,
4110 .activate = irte_activate,
4111 .deactivate = irte_deactivate,
4112 .set_affinity = irte_set_affinity,
4113 .set_allocated = irte_set_allocated,
4114 .is_allocated = irte_is_allocated,
4115 .clear_allocated = irte_clear_allocated,
4118 struct amd_irte_ops irte_128_ops = {
4119 .prepare = irte_ga_prepare,
4120 .activate = irte_ga_activate,
4121 .deactivate = irte_ga_deactivate,
4122 .set_affinity = irte_ga_set_affinity,
4123 .set_allocated = irte_ga_set_allocated,
4124 .is_allocated = irte_ga_is_allocated,
4125 .clear_allocated = irte_ga_clear_allocated,
4128 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4129 unsigned int nr_irqs, void *arg)
4131 struct irq_alloc_info *info = arg;
4132 struct irq_data *irq_data;
4133 struct amd_ir_data *data = NULL;
4134 struct irq_cfg *cfg;
4140 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4141 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4145 * With IRQ remapping enabled, don't need contiguous CPU vectors
4146 * to support multiple MSI interrupts.
4148 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4149 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4151 devid = get_devid(info);
4155 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4159 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4160 struct irq_remap_table *table;
4161 struct amd_iommu *iommu;
4163 table = alloc_irq_table(devid);
4165 if (!table->min_index) {
4167 * Keep the first 32 indexes free for IOAPIC
4170 table->min_index = 32;
4171 iommu = amd_iommu_rlookup_table[devid];
4172 for (i = 0; i < 32; ++i)
4173 iommu->irte_ops->set_allocated(table, i);
4175 WARN_ON(table->min_index != 32);
4176 index = info->ioapic_pin;
4181 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4183 index = alloc_irq_index(devid, nr_irqs, align);
4186 pr_warn("Failed to allocate IRTE\n");
4188 goto out_free_parent;
4191 for (i = 0; i < nr_irqs; i++) {
4192 irq_data = irq_domain_get_irq_data(domain, virq + i);
4193 cfg = irqd_cfg(irq_data);
4194 if (!irq_data || !cfg) {
4200 data = kzalloc(sizeof(*data), GFP_KERNEL);
4204 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4205 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4207 data->entry = kzalloc(sizeof(struct irte_ga),
4214 irq_data->hwirq = (devid << 16) + i;
4215 irq_data->chip_data = data;
4216 irq_data->chip = &amd_ir_chip;
4217 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4218 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4224 for (i--; i >= 0; i--) {
4225 irq_data = irq_domain_get_irq_data(domain, virq + i);
4227 kfree(irq_data->chip_data);
4229 for (i = 0; i < nr_irqs; i++)
4230 free_irte(devid, index + i);
4232 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4236 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4237 unsigned int nr_irqs)
4239 struct irq_2_irte *irte_info;
4240 struct irq_data *irq_data;
4241 struct amd_ir_data *data;
4244 for (i = 0; i < nr_irqs; i++) {
4245 irq_data = irq_domain_get_irq_data(domain, virq + i);
4246 if (irq_data && irq_data->chip_data) {
4247 data = irq_data->chip_data;
4248 irte_info = &data->irq_2_irte;
4249 free_irte(irte_info->devid, irte_info->index);
4254 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4257 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4258 struct amd_ir_data *ir_data,
4259 struct irq_2_irte *irte_info,
4260 struct irq_cfg *cfg);
4262 static int irq_remapping_activate(struct irq_domain *domain,
4263 struct irq_data *irq_data, bool reserve)
4265 struct amd_ir_data *data = irq_data->chip_data;
4266 struct irq_2_irte *irte_info = &data->irq_2_irte;
4267 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4268 struct irq_cfg *cfg = irqd_cfg(irq_data);
4273 iommu->irte_ops->activate(data->entry, irte_info->devid,
4275 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4279 static void irq_remapping_deactivate(struct irq_domain *domain,
4280 struct irq_data *irq_data)
4282 struct amd_ir_data *data = irq_data->chip_data;
4283 struct irq_2_irte *irte_info = &data->irq_2_irte;
4284 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4287 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4291 static const struct irq_domain_ops amd_ir_domain_ops = {
4292 .alloc = irq_remapping_alloc,
4293 .free = irq_remapping_free,
4294 .activate = irq_remapping_activate,
4295 .deactivate = irq_remapping_deactivate,
4298 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4300 struct amd_iommu *iommu;
4301 struct amd_iommu_pi_data *pi_data = vcpu_info;
4302 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4303 struct amd_ir_data *ir_data = data->chip_data;
4304 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4305 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4306 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4309 * This device has never been set up for guest mode.
4310 * we should not modify the IRTE
4312 if (!dev_data || !dev_data->use_vapic)
4315 pi_data->ir_data = ir_data;
4318 * SVM tries to set up for VAPIC mode, but we are in
4319 * legacy mode. So, we force legacy mode instead.
4321 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4322 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4324 pi_data->is_guest_mode = false;
4327 iommu = amd_iommu_rlookup_table[irte_info->devid];
4331 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4332 if (pi_data->is_guest_mode) {
4334 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4335 irte->hi.fields.vector = vcpu_pi_info->vector;
4336 irte->lo.fields_vapic.ga_log_intr = 1;
4337 irte->lo.fields_vapic.guest_mode = 1;
4338 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4340 ir_data->cached_ga_tag = pi_data->ga_tag;
4343 struct irq_cfg *cfg = irqd_cfg(data);
4347 irte->hi.fields.vector = cfg->vector;
4348 irte->lo.fields_remap.guest_mode = 0;
4349 irte->lo.fields_remap.destination = cfg->dest_apicid;
4350 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4351 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4354 * This communicates the ga_tag back to the caller
4355 * so that it can do all the necessary clean up.
4357 ir_data->cached_ga_tag = 0;
4360 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4364 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4365 struct amd_ir_data *ir_data,
4366 struct irq_2_irte *irte_info,
4367 struct irq_cfg *cfg)
4371 * Atomically updates the IRTE with the new destination, vector
4372 * and flushes the interrupt entry cache.
4374 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4375 irte_info->index, cfg->vector,
4379 static int amd_ir_set_affinity(struct irq_data *data,
4380 const struct cpumask *mask, bool force)
4382 struct amd_ir_data *ir_data = data->chip_data;
4383 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4384 struct irq_cfg *cfg = irqd_cfg(data);
4385 struct irq_data *parent = data->parent_data;
4386 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4392 ret = parent->chip->irq_set_affinity(parent, mask, force);
4393 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4396 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4398 * After this point, all the interrupts will start arriving
4399 * at the new destination. So, time to cleanup the previous
4400 * vector allocation.
4402 send_cleanup_vector(cfg);
4404 return IRQ_SET_MASK_OK_DONE;
4407 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4409 struct amd_ir_data *ir_data = irq_data->chip_data;
4411 *msg = ir_data->msi_entry;
4414 static struct irq_chip amd_ir_chip = {
4416 .irq_ack = apic_ack_irq,
4417 .irq_set_affinity = amd_ir_set_affinity,
4418 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4419 .irq_compose_msi_msg = ir_compose_msi_msg,
4422 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4424 struct fwnode_handle *fn;
4426 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4429 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4430 irq_domain_free_fwnode(fn);
4431 if (!iommu->ir_domain)
4434 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4435 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4441 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4443 unsigned long flags;
4444 struct amd_iommu *iommu;
4445 struct irq_remap_table *table;
4446 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4447 int devid = ir_data->irq_2_irte.devid;
4448 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4449 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4451 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4452 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4455 iommu = amd_iommu_rlookup_table[devid];
4459 table = get_irq_table(devid);
4463 raw_spin_lock_irqsave(&table->lock, flags);
4465 if (ref->lo.fields_vapic.guest_mode) {
4467 ref->lo.fields_vapic.destination = cpu;
4468 ref->lo.fields_vapic.is_run = is_run;
4472 raw_spin_unlock_irqrestore(&table->lock, flags);
4474 iommu_flush_irt(iommu, devid);
4475 iommu_completion_wait(iommu);
4478 EXPORT_SYMBOL(amd_iommu_update_ga);