1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-map-ops.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/irqdomain.h>
32 #include <linux/percpu.h>
33 #include <linux/io-pgtable.h>
34 #include <asm/irq_remapping.h>
35 #include <asm/io_apic.h>
37 #include <asm/hw_irq.h>
38 #include <asm/proto.h>
39 #include <asm/iommu.h>
43 #include "amd_iommu.h"
44 #include "../irq_remapping.h"
46 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
48 #define LOOP_TIMEOUT 100000
50 /* IO virtual address start page frame number */
51 #define IOVA_START_PFN (1)
52 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
54 /* Reserved IOVA ranges */
55 #define MSI_RANGE_START (0xfee00000)
56 #define MSI_RANGE_END (0xfeefffff)
57 #define HT_RANGE_START (0xfd00000000ULL)
58 #define HT_RANGE_END (0xffffffffffULL)
60 #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL
62 static DEFINE_SPINLOCK(pd_bitmap_lock);
64 /* List of all available dev_data structures */
65 static LLIST_HEAD(dev_data_list);
67 LIST_HEAD(ioapic_map);
69 LIST_HEAD(acpihid_map);
72 * Domain for untranslated devices - only allocated
73 * if iommu=pt passed on kernel cmd line.
75 const struct iommu_ops amd_iommu_ops;
77 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
78 int amd_iommu_max_glx_val = -1;
81 * general struct to manage commands send to an IOMMU
87 struct kmem_cache *amd_iommu_irq_cache;
89 static void detach_device(struct device *dev);
91 /****************************************************************************
95 ****************************************************************************/
97 static inline u16 get_pci_device_id(struct device *dev)
99 struct pci_dev *pdev = to_pci_dev(dev);
101 return pci_dev_id(pdev);
104 static inline int get_acpihid_device_id(struct device *dev,
105 struct acpihid_map_entry **entry)
107 struct acpi_device *adev = ACPI_COMPANION(dev);
108 struct acpihid_map_entry *p;
113 list_for_each_entry(p, &acpihid_map, list) {
114 if (acpi_dev_hid_uid_match(adev, p->hid,
115 p->uid[0] ? p->uid : NULL)) {
124 static inline int get_device_id(struct device *dev)
129 devid = get_pci_device_id(dev);
131 devid = get_acpihid_device_id(dev, NULL);
136 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
138 return container_of(dom, struct protection_domain, domain);
141 static struct iommu_dev_data *alloc_dev_data(u16 devid)
143 struct iommu_dev_data *dev_data;
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
149 spin_lock_init(&dev_data->lock);
150 dev_data->devid = devid;
151 ratelimit_default_init(&dev_data->rs);
153 llist_add(&dev_data->dev_data_list, &dev_data_list);
157 static struct iommu_dev_data *search_dev_data(u16 devid)
159 struct iommu_dev_data *dev_data;
160 struct llist_node *node;
162 if (llist_empty(&dev_data_list))
165 node = dev_data_list.first;
166 llist_for_each_entry(dev_data, node, dev_data_list) {
167 if (dev_data->devid == devid)
174 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
176 u16 devid = pci_dev_id(pdev);
181 amd_iommu_rlookup_table[alias] =
182 amd_iommu_rlookup_table[devid];
183 memcpy(amd_iommu_dev_table[alias].data,
184 amd_iommu_dev_table[devid].data,
185 sizeof(amd_iommu_dev_table[alias].data));
190 static void clone_aliases(struct pci_dev *pdev)
196 * The IVRS alias stored in the alias table may not be
197 * part of the PCI DMA aliases if it's bus differs
198 * from the original device.
200 clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
202 pci_for_each_dma_alias(pdev, clone_alias, NULL);
205 static struct pci_dev *setup_aliases(struct device *dev)
207 struct pci_dev *pdev = to_pci_dev(dev);
210 /* For ACPI HID devices, there are no aliases */
211 if (!dev_is_pci(dev))
215 * Add the IVRS alias to the pci aliases if it is on the same
216 * bus. The IVRS table may know about a quirk that we don't.
218 ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
219 if (ivrs_alias != pci_dev_id(pdev) &&
220 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
221 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
228 static struct iommu_dev_data *find_dev_data(u16 devid)
230 struct iommu_dev_data *dev_data;
231 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
233 dev_data = search_dev_data(devid);
235 if (dev_data == NULL) {
236 dev_data = alloc_dev_data(devid);
240 if (translation_pre_enabled(iommu))
241 dev_data->defer_attach = true;
248 * Find or create an IOMMU group for a acpihid device.
250 static struct iommu_group *acpihid_device_group(struct device *dev)
252 struct acpihid_map_entry *p, *entry = NULL;
255 devid = get_acpihid_device_id(dev, &entry);
257 return ERR_PTR(devid);
259 list_for_each_entry(p, &acpihid_map, list) {
260 if ((devid == p->devid) && p->group)
261 entry->group = p->group;
265 entry->group = generic_device_group(dev);
267 iommu_group_ref_get(entry->group);
272 static bool pci_iommuv2_capable(struct pci_dev *pdev)
274 static const int caps[] = {
276 PCI_EXT_CAP_ID_PASID,
280 if (!pci_ats_supported(pdev))
283 for (i = 0; i < 2; ++i) {
284 pos = pci_find_ext_capability(pdev, caps[i]);
293 * This function checks if the driver got a valid device from the caller to
294 * avoid dereferencing invalid pointers.
296 static bool check_device(struct device *dev)
303 devid = get_device_id(dev);
307 /* Out of our scope? */
308 if (devid > amd_iommu_last_bdf)
311 if (amd_iommu_rlookup_table[devid] == NULL)
317 static int iommu_init_device(struct device *dev)
319 struct iommu_dev_data *dev_data;
322 if (dev_iommu_priv_get(dev))
325 devid = get_device_id(dev);
329 dev_data = find_dev_data(devid);
333 dev_data->pdev = setup_aliases(dev);
336 * By default we use passthrough mode for IOMMUv2 capable device.
337 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
338 * invalid address), we ignore the capability for the device so
339 * it'll be forced to go into translation mode.
341 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
342 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
343 struct amd_iommu *iommu;
345 iommu = amd_iommu_rlookup_table[dev_data->devid];
346 dev_data->iommu_v2 = iommu->is_iommu_v2;
349 dev_iommu_priv_set(dev, dev_data);
354 static void iommu_ignore_device(struct device *dev)
358 devid = get_device_id(dev);
362 amd_iommu_rlookup_table[devid] = NULL;
363 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
368 static void amd_iommu_uninit_device(struct device *dev)
370 struct iommu_dev_data *dev_data;
372 dev_data = dev_iommu_priv_get(dev);
376 if (dev_data->domain)
379 dev_iommu_priv_set(dev, NULL);
382 * We keep dev_data around for unplugged devices and reuse it when the
383 * device is re-plugged - not doing so would introduce a ton of races.
387 /****************************************************************************
389 * Interrupt handling functions
391 ****************************************************************************/
393 static void dump_dte_entry(u16 devid)
397 for (i = 0; i < 4; ++i)
398 pr_err("DTE[%d]: %016llx\n", i,
399 amd_iommu_dev_table[devid].data[i]);
402 static void dump_command(unsigned long phys_addr)
404 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
407 for (i = 0; i < 4; ++i)
408 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
411 static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
413 struct iommu_dev_data *dev_data = NULL;
414 int devid, vmg_tag, flags;
415 struct pci_dev *pdev;
418 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
419 vmg_tag = (event[1]) & 0xFFFF;
420 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
421 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
423 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
426 dev_data = dev_iommu_priv_get(&pdev->dev);
428 if (dev_data && __ratelimit(&dev_data->rs)) {
429 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
430 vmg_tag, spa, flags);
432 pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
433 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
434 vmg_tag, spa, flags);
441 static void amd_iommu_report_rmp_fault(volatile u32 *event)
443 struct iommu_dev_data *dev_data = NULL;
444 int devid, flags_rmp, vmg_tag, flags;
445 struct pci_dev *pdev;
448 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
449 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF;
450 vmg_tag = (event[1]) & 0xFFFF;
451 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
452 gpa = ((u64)event[3] << 32) | event[2];
454 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
457 dev_data = dev_iommu_priv_get(&pdev->dev);
459 if (dev_data && __ratelimit(&dev_data->rs)) {
460 pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
461 vmg_tag, gpa, flags_rmp, flags);
463 pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
464 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
465 vmg_tag, gpa, flags_rmp, flags);
472 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
473 u64 address, int flags)
475 struct iommu_dev_data *dev_data = NULL;
476 struct pci_dev *pdev;
478 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
481 dev_data = dev_iommu_priv_get(&pdev->dev);
483 if (dev_data && __ratelimit(&dev_data->rs)) {
484 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
485 domain_id, address, flags);
486 } else if (printk_ratelimit()) {
487 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
488 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
489 domain_id, address, flags);
496 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
498 struct device *dev = iommu->iommu.dev;
499 int type, devid, flags, tag;
500 volatile u32 *event = __evt;
506 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
507 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
508 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
509 (event[1] & EVENT_DOMID_MASK_LO);
510 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
511 address = (u64)(((u64)event[3]) << 32) | event[2];
514 /* Did we hit the erratum? */
515 if (++count == LOOP_TIMEOUT) {
516 pr_err("No event written to event log\n");
523 if (type == EVENT_TYPE_IO_FAULT) {
524 amd_iommu_report_page_fault(devid, pasid, address, flags);
529 case EVENT_TYPE_ILL_DEV:
530 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
531 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
532 pasid, address, flags);
533 dump_dte_entry(devid);
535 case EVENT_TYPE_DEV_TAB_ERR:
536 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
537 "address=0x%llx flags=0x%04x]\n",
538 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
541 case EVENT_TYPE_PAGE_TAB_ERR:
542 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
543 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
544 pasid, address, flags);
546 case EVENT_TYPE_ILL_CMD:
547 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
548 dump_command(address);
550 case EVENT_TYPE_CMD_HARD_ERR:
551 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
554 case EVENT_TYPE_IOTLB_INV_TO:
555 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
556 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
559 case EVENT_TYPE_INV_DEV_REQ:
560 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
561 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
562 pasid, address, flags);
564 case EVENT_TYPE_RMP_FAULT:
565 amd_iommu_report_rmp_fault(event);
567 case EVENT_TYPE_RMP_HW_ERR:
568 amd_iommu_report_rmp_hw_error(event);
570 case EVENT_TYPE_INV_PPR_REQ:
571 pasid = PPR_PASID(*((u64 *)__evt));
572 tag = event[1] & 0x03FF;
573 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
574 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
575 pasid, address, flags, tag);
578 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
579 event[0], event[1], event[2], event[3]);
582 memset(__evt, 0, 4 * sizeof(u32));
585 static void iommu_poll_events(struct amd_iommu *iommu)
589 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
590 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
592 while (head != tail) {
593 iommu_print_event(iommu, iommu->evt_buf + head);
594 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
597 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
600 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
602 struct amd_iommu_fault fault;
604 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
605 pr_err_ratelimited("Unknown PPR request received\n");
609 fault.address = raw[1];
610 fault.pasid = PPR_PASID(raw[0]);
611 fault.device_id = PPR_DEVID(raw[0]);
612 fault.tag = PPR_TAG(raw[0]);
613 fault.flags = PPR_FLAGS(raw[0]);
615 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
618 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
622 if (iommu->ppr_log == NULL)
625 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
626 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
628 while (head != tail) {
633 raw = (u64 *)(iommu->ppr_log + head);
636 * Hardware bug: Interrupt may arrive before the entry is
637 * written to memory. If this happens we need to wait for the
640 for (i = 0; i < LOOP_TIMEOUT; ++i) {
641 if (PPR_REQ_TYPE(raw[0]) != 0)
646 /* Avoid memcpy function-call overhead */
651 * To detect the hardware bug we need to clear the entry
654 raw[0] = raw[1] = 0UL;
656 /* Update head pointer of hardware ring-buffer */
657 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
658 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
660 /* Handle PPR entry */
661 iommu_handle_ppr_entry(iommu, entry);
663 /* Refresh ring-buffer information */
664 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
665 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
669 #ifdef CONFIG_IRQ_REMAP
670 static int (*iommu_ga_log_notifier)(u32);
672 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
674 iommu_ga_log_notifier = notifier;
678 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
680 static void iommu_poll_ga_log(struct amd_iommu *iommu)
682 u32 head, tail, cnt = 0;
684 if (iommu->ga_log == NULL)
687 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
688 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
690 while (head != tail) {
694 raw = (u64 *)(iommu->ga_log + head);
697 /* Avoid memcpy function-call overhead */
700 /* Update head pointer of hardware ring-buffer */
701 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
702 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
704 /* Handle GA entry */
705 switch (GA_REQ_TYPE(log_entry)) {
707 if (!iommu_ga_log_notifier)
710 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
711 __func__, GA_DEVID(log_entry),
714 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
715 pr_err("GA log notifier failed.\n");
724 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu)
726 if (!irq_remapping_enabled || !dev_is_pci(dev) ||
727 pci_dev_has_special_msi_domain(to_pci_dev(dev)))
730 dev_set_msi_domain(dev, iommu->msi_domain);
733 #else /* CONFIG_IRQ_REMAP */
735 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { }
736 #endif /* !CONFIG_IRQ_REMAP */
738 #define AMD_IOMMU_INT_MASK \
739 (MMIO_STATUS_EVT_INT_MASK | \
740 MMIO_STATUS_PPR_INT_MASK | \
741 MMIO_STATUS_GALOG_INT_MASK)
743 irqreturn_t amd_iommu_int_thread(int irq, void *data)
745 struct amd_iommu *iommu = (struct amd_iommu *) data;
746 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
748 while (status & AMD_IOMMU_INT_MASK) {
749 /* Enable EVT and PPR and GA interrupts again */
750 writel(AMD_IOMMU_INT_MASK,
751 iommu->mmio_base + MMIO_STATUS_OFFSET);
753 if (status & MMIO_STATUS_EVT_INT_MASK) {
754 pr_devel("Processing IOMMU Event Log\n");
755 iommu_poll_events(iommu);
758 if (status & MMIO_STATUS_PPR_INT_MASK) {
759 pr_devel("Processing IOMMU PPR Log\n");
760 iommu_poll_ppr_log(iommu);
763 #ifdef CONFIG_IRQ_REMAP
764 if (status & MMIO_STATUS_GALOG_INT_MASK) {
765 pr_devel("Processing IOMMU GA Log\n");
766 iommu_poll_ga_log(iommu);
771 * Hardware bug: ERBT1312
772 * When re-enabling interrupt (by writing 1
773 * to clear the bit), the hardware might also try to set
774 * the interrupt bit in the event status register.
775 * In this scenario, the bit will be set, and disable
776 * subsequent interrupts.
778 * Workaround: The IOMMU driver should read back the
779 * status register and check if the interrupt bits are cleared.
780 * If not, driver will need to go through the interrupt handler
781 * again and re-clear the bits
783 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
788 irqreturn_t amd_iommu_int_handler(int irq, void *data)
790 return IRQ_WAKE_THREAD;
793 /****************************************************************************
795 * IOMMU command queuing functions
797 ****************************************************************************/
799 static int wait_on_sem(struct amd_iommu *iommu, u64 data)
803 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) {
808 if (i == LOOP_TIMEOUT) {
809 pr_alert("Completion-Wait loop timed out\n");
816 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
817 struct iommu_cmd *cmd)
822 /* Copy command to buffer */
823 tail = iommu->cmd_buf_tail;
824 target = iommu->cmd_buf + tail;
825 memcpy(target, cmd, sizeof(*cmd));
827 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
828 iommu->cmd_buf_tail = tail;
830 /* Tell the IOMMU about it */
831 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
834 static void build_completion_wait(struct iommu_cmd *cmd,
835 struct amd_iommu *iommu,
838 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
840 memset(cmd, 0, sizeof(*cmd));
841 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
842 cmd->data[1] = upper_32_bits(paddr);
844 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
847 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
849 memset(cmd, 0, sizeof(*cmd));
850 cmd->data[0] = devid;
851 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
855 * Builds an invalidation address which is suitable for one page or multiple
856 * pages. Sets the size bit (S) as needed is more than one page is flushed.
858 static inline u64 build_inv_address(u64 address, size_t size)
860 u64 pages, end, msb_diff;
862 pages = iommu_num_pages(address, size, PAGE_SIZE);
865 return address & PAGE_MASK;
867 end = address + size - 1;
870 * msb_diff would hold the index of the most significant bit that
871 * flipped between the start and end.
873 msb_diff = fls64(end ^ address) - 1;
876 * Bits 63:52 are sign extended. If for some reason bit 51 is different
877 * between the start and the end, invalidate everything.
879 if (unlikely(msb_diff > 51)) {
880 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
883 * The msb-bit must be clear on the address. Just set all the
886 address |= (1ull << msb_diff) - 1;
889 /* Clear bits 11:0 */
890 address &= PAGE_MASK;
892 /* Set the size bit - we flush more than one 4kb page */
893 return address | CMD_INV_IOMMU_PAGES_SIZE_MASK;
896 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
897 size_t size, u16 domid, int pde)
899 u64 inv_address = build_inv_address(address, size);
901 memset(cmd, 0, sizeof(*cmd));
902 cmd->data[1] |= domid;
903 cmd->data[2] = lower_32_bits(inv_address);
904 cmd->data[3] = upper_32_bits(inv_address);
905 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
906 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
907 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
910 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
911 u64 address, size_t size)
913 u64 inv_address = build_inv_address(address, size);
915 memset(cmd, 0, sizeof(*cmd));
916 cmd->data[0] = devid;
917 cmd->data[0] |= (qdep & 0xff) << 24;
918 cmd->data[1] = devid;
919 cmd->data[2] = lower_32_bits(inv_address);
920 cmd->data[3] = upper_32_bits(inv_address);
921 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
924 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
925 u64 address, bool size)
927 memset(cmd, 0, sizeof(*cmd));
929 address &= ~(0xfffULL);
931 cmd->data[0] = pasid;
932 cmd->data[1] = domid;
933 cmd->data[2] = lower_32_bits(address);
934 cmd->data[3] = upper_32_bits(address);
935 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
936 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
938 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
939 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
942 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
943 int qdep, u64 address, bool size)
945 memset(cmd, 0, sizeof(*cmd));
947 address &= ~(0xfffULL);
949 cmd->data[0] = devid;
950 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
951 cmd->data[0] |= (qdep & 0xff) << 24;
952 cmd->data[1] = devid;
953 cmd->data[1] |= (pasid & 0xff) << 16;
954 cmd->data[2] = lower_32_bits(address);
955 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
956 cmd->data[3] = upper_32_bits(address);
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
959 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
962 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
963 int status, int tag, bool gn)
965 memset(cmd, 0, sizeof(*cmd));
967 cmd->data[0] = devid;
969 cmd->data[1] = pasid;
970 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
972 cmd->data[3] = tag & 0x1ff;
973 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
975 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
978 static void build_inv_all(struct iommu_cmd *cmd)
980 memset(cmd, 0, sizeof(*cmd));
981 CMD_SET_TYPE(cmd, CMD_INV_ALL);
984 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
986 memset(cmd, 0, sizeof(*cmd));
987 cmd->data[0] = devid;
988 CMD_SET_TYPE(cmd, CMD_INV_IRT);
992 * Writes the command to the IOMMUs command buffer and informs the
993 * hardware about the new command.
995 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
996 struct iommu_cmd *cmd,
999 unsigned int count = 0;
1000 u32 left, next_tail;
1002 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1004 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1007 /* Skip udelay() the first time around */
1009 if (count == LOOP_TIMEOUT) {
1010 pr_err("Command buffer timeout\n");
1017 /* Update head and recheck remaining space */
1018 iommu->cmd_buf_head = readl(iommu->mmio_base +
1019 MMIO_CMD_HEAD_OFFSET);
1024 copy_cmd_to_buffer(iommu, cmd);
1026 /* Do we need to make sure all commands are processed? */
1027 iommu->need_sync = sync;
1032 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1033 struct iommu_cmd *cmd,
1036 unsigned long flags;
1039 raw_spin_lock_irqsave(&iommu->lock, flags);
1040 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1041 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1046 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1048 return iommu_queue_command_sync(iommu, cmd, true);
1052 * This function queues a completion wait command into the command
1053 * buffer of an IOMMU
1055 static int iommu_completion_wait(struct amd_iommu *iommu)
1057 struct iommu_cmd cmd;
1058 unsigned long flags;
1062 if (!iommu->need_sync)
1065 raw_spin_lock_irqsave(&iommu->lock, flags);
1067 data = ++iommu->cmd_sem_val;
1068 build_completion_wait(&cmd, iommu, data);
1070 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1074 ret = wait_on_sem(iommu, data);
1077 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1082 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1084 struct iommu_cmd cmd;
1086 build_inv_dte(&cmd, devid);
1088 return iommu_queue_command(iommu, &cmd);
1091 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1095 for (devid = 0; devid <= 0xffff; ++devid)
1096 iommu_flush_dte(iommu, devid);
1098 iommu_completion_wait(iommu);
1102 * This function uses heavy locking and may disable irqs for some time. But
1103 * this is no issue because it is only called during resume.
1105 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1109 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1110 struct iommu_cmd cmd;
1111 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1113 iommu_queue_command(iommu, &cmd);
1116 iommu_completion_wait(iommu);
1119 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1121 struct iommu_cmd cmd;
1123 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1125 iommu_queue_command(iommu, &cmd);
1127 iommu_completion_wait(iommu);
1130 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1132 struct iommu_cmd cmd;
1134 build_inv_all(&cmd);
1136 iommu_queue_command(iommu, &cmd);
1137 iommu_completion_wait(iommu);
1140 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1142 struct iommu_cmd cmd;
1144 build_inv_irt(&cmd, devid);
1146 iommu_queue_command(iommu, &cmd);
1149 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1153 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1154 iommu_flush_irt(iommu, devid);
1156 iommu_completion_wait(iommu);
1159 void iommu_flush_all_caches(struct amd_iommu *iommu)
1161 if (iommu_feature(iommu, FEATURE_IA)) {
1162 amd_iommu_flush_all(iommu);
1164 amd_iommu_flush_dte_all(iommu);
1165 amd_iommu_flush_irt_all(iommu);
1166 amd_iommu_flush_tlb_all(iommu);
1171 * Command send function for flushing on-device TLB
1173 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1174 u64 address, size_t size)
1176 struct amd_iommu *iommu;
1177 struct iommu_cmd cmd;
1180 qdep = dev_data->ats.qdep;
1181 iommu = amd_iommu_rlookup_table[dev_data->devid];
1183 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1185 return iommu_queue_command(iommu, &cmd);
1188 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1190 struct amd_iommu *iommu = data;
1192 return iommu_flush_dte(iommu, alias);
1196 * Command send function for invalidating a device table entry
1198 static int device_flush_dte(struct iommu_dev_data *dev_data)
1200 struct amd_iommu *iommu;
1204 iommu = amd_iommu_rlookup_table[dev_data->devid];
1207 ret = pci_for_each_dma_alias(dev_data->pdev,
1208 device_flush_dte_alias, iommu);
1210 ret = iommu_flush_dte(iommu, dev_data->devid);
1214 alias = amd_iommu_alias_table[dev_data->devid];
1215 if (alias != dev_data->devid) {
1216 ret = iommu_flush_dte(iommu, alias);
1221 if (dev_data->ats.enabled)
1222 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1228 * TLB invalidation function which is called from the mapping functions.
1229 * It invalidates a single PTE if the range to flush is within a single
1230 * page. Otherwise it flushes the whole TLB of the IOMMU.
1232 static void __domain_flush_pages(struct protection_domain *domain,
1233 u64 address, size_t size, int pde)
1235 struct iommu_dev_data *dev_data;
1236 struct iommu_cmd cmd;
1239 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1241 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1242 if (!domain->dev_iommu[i])
1246 * Devices of this domain are behind this IOMMU
1247 * We need a TLB flush
1249 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1252 list_for_each_entry(dev_data, &domain->dev_list, list) {
1254 if (!dev_data->ats.enabled)
1257 ret |= device_flush_iotlb(dev_data, address, size);
1263 static void domain_flush_pages(struct protection_domain *domain,
1264 u64 address, size_t size)
1266 __domain_flush_pages(domain, address, size, 0);
1269 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1270 void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain)
1272 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1275 void amd_iommu_domain_flush_complete(struct protection_domain *domain)
1279 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1280 if (domain && !domain->dev_iommu[i])
1284 * Devices of this domain are behind this IOMMU
1285 * We need to wait for completion of all commands.
1287 iommu_completion_wait(amd_iommus[i]);
1291 /* Flush the not present cache if it exists */
1292 static void domain_flush_np_cache(struct protection_domain *domain,
1293 dma_addr_t iova, size_t size)
1295 if (unlikely(amd_iommu_np_cache)) {
1296 unsigned long flags;
1298 spin_lock_irqsave(&domain->lock, flags);
1299 domain_flush_pages(domain, iova, size);
1300 amd_iommu_domain_flush_complete(domain);
1301 spin_unlock_irqrestore(&domain->lock, flags);
1307 * This function flushes the DTEs for all devices in domain
1309 static void domain_flush_devices(struct protection_domain *domain)
1311 struct iommu_dev_data *dev_data;
1313 list_for_each_entry(dev_data, &domain->dev_list, list)
1314 device_flush_dte(dev_data);
1317 /****************************************************************************
1319 * The next functions belong to the domain allocation. A domain is
1320 * allocated for every IOMMU as the default domain. If device isolation
1321 * is enabled, every device get its own domain. The most important thing
1322 * about domains is the page table mapping the DMA address space they
1325 ****************************************************************************/
1327 static u16 domain_id_alloc(void)
1331 spin_lock(&pd_bitmap_lock);
1332 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1334 if (id > 0 && id < MAX_DOMAIN_ID)
1335 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1338 spin_unlock(&pd_bitmap_lock);
1343 static void domain_id_free(int id)
1345 spin_lock(&pd_bitmap_lock);
1346 if (id > 0 && id < MAX_DOMAIN_ID)
1347 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1348 spin_unlock(&pd_bitmap_lock);
1351 static void free_gcr3_tbl_level1(u64 *tbl)
1356 for (i = 0; i < 512; ++i) {
1357 if (!(tbl[i] & GCR3_VALID))
1360 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1362 free_page((unsigned long)ptr);
1366 static void free_gcr3_tbl_level2(u64 *tbl)
1371 for (i = 0; i < 512; ++i) {
1372 if (!(tbl[i] & GCR3_VALID))
1375 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1377 free_gcr3_tbl_level1(ptr);
1381 static void free_gcr3_table(struct protection_domain *domain)
1383 if (domain->glx == 2)
1384 free_gcr3_tbl_level2(domain->gcr3_tbl);
1385 else if (domain->glx == 1)
1386 free_gcr3_tbl_level1(domain->gcr3_tbl);
1388 BUG_ON(domain->glx != 0);
1390 free_page((unsigned long)domain->gcr3_tbl);
1393 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1400 if (domain->iop.mode != PAGE_MODE_NONE)
1401 pte_root = iommu_virt_to_phys(domain->iop.root);
1403 pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK)
1404 << DEV_ENTRY_MODE_SHIFT;
1405 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1407 flags = amd_iommu_dev_table[devid].data[1];
1410 flags |= DTE_FLAG_IOTLB;
1413 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1415 if (iommu_feature(iommu, FEATURE_EPHSUP))
1416 pte_root |= 1ULL << DEV_ENTRY_PPR;
1419 if (domain->flags & PD_IOMMUV2_MASK) {
1420 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1421 u64 glx = domain->glx;
1424 pte_root |= DTE_FLAG_GV;
1425 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1427 /* First mask out possible old values for GCR3 table */
1428 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1431 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1434 /* Encode GCR3 table into DTE */
1435 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1438 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1441 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1445 flags &= ~DEV_DOMID_MASK;
1446 flags |= domain->id;
1448 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1449 amd_iommu_dev_table[devid].data[1] = flags;
1450 amd_iommu_dev_table[devid].data[0] = pte_root;
1453 * A kdump kernel might be replacing a domain ID that was copied from
1454 * the previous kernel--if so, it needs to flush the translation cache
1455 * entries for the old domain ID that is being overwritten
1458 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1460 amd_iommu_flush_tlb_domid(iommu, old_domid);
1464 static void clear_dte_entry(u16 devid)
1466 /* remove entry from the device table seen by the hardware */
1467 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1468 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1470 amd_iommu_apply_erratum_63(devid);
1473 static void do_attach(struct iommu_dev_data *dev_data,
1474 struct protection_domain *domain)
1476 struct amd_iommu *iommu;
1479 iommu = amd_iommu_rlookup_table[dev_data->devid];
1480 ats = dev_data->ats.enabled;
1482 /* Update data structures */
1483 dev_data->domain = domain;
1484 list_add(&dev_data->list, &domain->dev_list);
1486 /* Do reference counting */
1487 domain->dev_iommu[iommu->index] += 1;
1488 domain->dev_cnt += 1;
1490 /* Update device table */
1491 set_dte_entry(dev_data->devid, domain,
1492 ats, dev_data->iommu_v2);
1493 clone_aliases(dev_data->pdev);
1495 device_flush_dte(dev_data);
1498 static void do_detach(struct iommu_dev_data *dev_data)
1500 struct protection_domain *domain = dev_data->domain;
1501 struct amd_iommu *iommu;
1503 iommu = amd_iommu_rlookup_table[dev_data->devid];
1505 /* Update data structures */
1506 dev_data->domain = NULL;
1507 list_del(&dev_data->list);
1508 clear_dte_entry(dev_data->devid);
1509 clone_aliases(dev_data->pdev);
1511 /* Flush the DTE entry */
1512 device_flush_dte(dev_data);
1515 amd_iommu_domain_flush_tlb_pde(domain);
1517 /* Wait for the flushes to finish */
1518 amd_iommu_domain_flush_complete(domain);
1520 /* decrease reference counters - needs to happen after the flushes */
1521 domain->dev_iommu[iommu->index] -= 1;
1522 domain->dev_cnt -= 1;
1525 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1527 pci_disable_ats(pdev);
1528 pci_disable_pri(pdev);
1529 pci_disable_pasid(pdev);
1532 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1536 /* Only allow access to user-accessible pages */
1537 ret = pci_enable_pasid(pdev, 0);
1541 /* First reset the PRI state of the device */
1542 ret = pci_reset_pri(pdev);
1547 /* FIXME: Hardcode number of outstanding requests for now */
1548 ret = pci_enable_pri(pdev, 32);
1552 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1559 pci_disable_pri(pdev);
1560 pci_disable_pasid(pdev);
1566 * If a device is not yet associated with a domain, this function makes the
1567 * device visible in the domain
1569 static int attach_device(struct device *dev,
1570 struct protection_domain *domain)
1572 struct iommu_dev_data *dev_data;
1573 struct pci_dev *pdev;
1574 unsigned long flags;
1577 spin_lock_irqsave(&domain->lock, flags);
1579 dev_data = dev_iommu_priv_get(dev);
1581 spin_lock(&dev_data->lock);
1584 if (dev_data->domain != NULL)
1587 if (!dev_is_pci(dev))
1588 goto skip_ats_check;
1590 pdev = to_pci_dev(dev);
1591 if (domain->flags & PD_IOMMUV2_MASK) {
1592 struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
1595 if (def_domain->type != IOMMU_DOMAIN_IDENTITY)
1598 if (dev_data->iommu_v2) {
1599 if (pdev_iommuv2_enable(pdev) != 0)
1602 dev_data->ats.enabled = true;
1603 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1604 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
1606 } else if (amd_iommu_iotlb_sup &&
1607 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1608 dev_data->ats.enabled = true;
1609 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1615 do_attach(dev_data, domain);
1618 * We might boot into a crash-kernel here. The crashed kernel
1619 * left the caches in the IOMMU dirty. So we have to flush
1620 * here to evict all dirty stuff.
1622 amd_iommu_domain_flush_tlb_pde(domain);
1624 amd_iommu_domain_flush_complete(domain);
1627 spin_unlock(&dev_data->lock);
1629 spin_unlock_irqrestore(&domain->lock, flags);
1635 * Removes a device from a protection domain (with devtable_lock held)
1637 static void detach_device(struct device *dev)
1639 struct protection_domain *domain;
1640 struct iommu_dev_data *dev_data;
1641 unsigned long flags;
1643 dev_data = dev_iommu_priv_get(dev);
1644 domain = dev_data->domain;
1646 spin_lock_irqsave(&domain->lock, flags);
1648 spin_lock(&dev_data->lock);
1651 * First check if the device is still attached. It might already
1652 * be detached from its domain because the generic
1653 * iommu_detach_group code detached it and we try again here in
1654 * our alias handling.
1656 if (WARN_ON(!dev_data->domain))
1659 do_detach(dev_data);
1661 if (!dev_is_pci(dev))
1664 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
1665 pdev_iommuv2_disable(to_pci_dev(dev));
1666 else if (dev_data->ats.enabled)
1667 pci_disable_ats(to_pci_dev(dev));
1669 dev_data->ats.enabled = false;
1672 spin_unlock(&dev_data->lock);
1674 spin_unlock_irqrestore(&domain->lock, flags);
1677 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
1679 struct iommu_device *iommu_dev;
1680 struct amd_iommu *iommu;
1683 if (!check_device(dev))
1684 return ERR_PTR(-ENODEV);
1686 devid = get_device_id(dev);
1687 iommu = amd_iommu_rlookup_table[devid];
1689 if (dev_iommu_priv_get(dev))
1690 return &iommu->iommu;
1692 ret = iommu_init_device(dev);
1694 if (ret != -ENOTSUPP)
1695 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
1696 iommu_dev = ERR_PTR(ret);
1697 iommu_ignore_device(dev);
1699 amd_iommu_set_pci_msi_domain(dev, iommu);
1700 iommu_dev = &iommu->iommu;
1703 iommu_completion_wait(iommu);
1708 static void amd_iommu_probe_finalize(struct device *dev)
1710 struct iommu_domain *domain;
1712 /* Domains are initialized for this device - have a look what we ended up with */
1713 domain = iommu_get_domain_for_dev(dev);
1714 if (domain->type == IOMMU_DOMAIN_DMA)
1715 iommu_setup_dma_ops(dev, 0, U64_MAX);
1717 set_dma_ops(dev, NULL);
1720 static void amd_iommu_release_device(struct device *dev)
1722 int devid = get_device_id(dev);
1723 struct amd_iommu *iommu;
1725 if (!check_device(dev))
1728 iommu = amd_iommu_rlookup_table[devid];
1730 amd_iommu_uninit_device(dev);
1731 iommu_completion_wait(iommu);
1734 static struct iommu_group *amd_iommu_device_group(struct device *dev)
1736 if (dev_is_pci(dev))
1737 return pci_device_group(dev);
1739 return acpihid_device_group(dev);
1742 /*****************************************************************************
1744 * The next functions belong to the dma_ops mapping/unmapping code.
1746 *****************************************************************************/
1748 static void update_device_table(struct protection_domain *domain)
1750 struct iommu_dev_data *dev_data;
1752 list_for_each_entry(dev_data, &domain->dev_list, list) {
1753 set_dte_entry(dev_data->devid, domain,
1754 dev_data->ats.enabled, dev_data->iommu_v2);
1755 clone_aliases(dev_data->pdev);
1759 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain)
1761 update_device_table(domain);
1762 domain_flush_devices(domain);
1765 void amd_iommu_domain_update(struct protection_domain *domain)
1767 /* Update device table */
1768 amd_iommu_update_and_flush_device_table(domain);
1770 /* Flush domain TLB(s) and wait for completion */
1771 amd_iommu_domain_flush_tlb_pde(domain);
1772 amd_iommu_domain_flush_complete(domain);
1775 static void __init amd_iommu_init_dma_ops(void)
1777 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
1779 if (amd_iommu_unmap_flush)
1780 pr_info("IO/TLB flush on unmap enabled\n");
1782 pr_info("Lazy IO/TLB flushing enabled\n");
1783 iommu_set_dma_strict(amd_iommu_unmap_flush);
1786 int __init amd_iommu_init_api(void)
1790 amd_iommu_init_dma_ops();
1792 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
1795 #ifdef CONFIG_ARM_AMBA
1796 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
1800 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
1807 /*****************************************************************************
1809 * The following functions belong to the exported interface of AMD IOMMU
1811 * This interface allows access to lower level functions of the IOMMU
1812 * like protection domain handling and assignement of devices to domains
1813 * which is not possible with the dma_ops interface.
1815 *****************************************************************************/
1817 static void cleanup_domain(struct protection_domain *domain)
1819 struct iommu_dev_data *entry;
1820 unsigned long flags;
1822 spin_lock_irqsave(&domain->lock, flags);
1824 while (!list_empty(&domain->dev_list)) {
1825 entry = list_first_entry(&domain->dev_list,
1826 struct iommu_dev_data, list);
1827 BUG_ON(!entry->domain);
1831 spin_unlock_irqrestore(&domain->lock, flags);
1834 static void protection_domain_free(struct protection_domain *domain)
1840 domain_id_free(domain->id);
1842 if (domain->iop.pgtbl_cfg.tlb)
1843 free_io_pgtable_ops(&domain->iop.iop.ops);
1848 static int protection_domain_init_v1(struct protection_domain *domain, int mode)
1850 u64 *pt_root = NULL;
1852 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
1854 spin_lock_init(&domain->lock);
1855 domain->id = domain_id_alloc();
1858 INIT_LIST_HEAD(&domain->dev_list);
1860 if (mode != PAGE_MODE_NONE) {
1861 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1866 amd_iommu_domain_set_pgtable(domain, pt_root, mode);
1871 static struct protection_domain *protection_domain_alloc(unsigned int type)
1873 struct io_pgtable_ops *pgtbl_ops;
1874 struct protection_domain *domain;
1875 int pgtable = amd_iommu_pgtable;
1876 int mode = DEFAULT_PGTABLE_LEVEL;
1879 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1884 * Force IOMMU v1 page table when iommu=pt and
1885 * when allocating domain for pass-through devices.
1887 if (type == IOMMU_DOMAIN_IDENTITY) {
1888 pgtable = AMD_IOMMU_V1;
1889 mode = PAGE_MODE_NONE;
1890 } else if (type == IOMMU_DOMAIN_UNMANAGED) {
1891 pgtable = AMD_IOMMU_V1;
1896 ret = protection_domain_init_v1(domain, mode);
1905 pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain);
1915 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
1917 struct protection_domain *domain;
1919 domain = protection_domain_alloc(type);
1923 domain->domain.geometry.aperture_start = 0;
1924 domain->domain.geometry.aperture_end = ~0ULL;
1925 domain->domain.geometry.force_aperture = true;
1927 if (type == IOMMU_DOMAIN_DMA &&
1928 iommu_get_dma_cookie(&domain->domain) == -ENOMEM)
1931 return &domain->domain;
1934 protection_domain_free(domain);
1939 static void amd_iommu_domain_free(struct iommu_domain *dom)
1941 struct protection_domain *domain;
1943 domain = to_pdomain(dom);
1945 if (domain->dev_cnt > 0)
1946 cleanup_domain(domain);
1948 BUG_ON(domain->dev_cnt != 0);
1953 if (dom->type == IOMMU_DOMAIN_DMA)
1954 iommu_put_dma_cookie(&domain->domain);
1956 if (domain->flags & PD_IOMMUV2_MASK)
1957 free_gcr3_table(domain);
1959 protection_domain_free(domain);
1962 static void amd_iommu_detach_device(struct iommu_domain *dom,
1965 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
1966 int devid = get_device_id(dev);
1967 struct amd_iommu *iommu;
1969 if (!check_device(dev))
1972 if (dev_data->domain != NULL)
1975 iommu = amd_iommu_rlookup_table[devid];
1979 #ifdef CONFIG_IRQ_REMAP
1980 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
1981 (dom->type == IOMMU_DOMAIN_UNMANAGED))
1982 dev_data->use_vapic = 0;
1985 iommu_completion_wait(iommu);
1988 static int amd_iommu_attach_device(struct iommu_domain *dom,
1991 struct protection_domain *domain = to_pdomain(dom);
1992 struct iommu_dev_data *dev_data;
1993 struct amd_iommu *iommu;
1996 if (!check_device(dev))
1999 dev_data = dev_iommu_priv_get(dev);
2000 dev_data->defer_attach = false;
2002 iommu = amd_iommu_rlookup_table[dev_data->devid];
2006 if (dev_data->domain)
2009 ret = attach_device(dev, domain);
2011 #ifdef CONFIG_IRQ_REMAP
2012 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2013 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2014 dev_data->use_vapic = 1;
2016 dev_data->use_vapic = 0;
2020 iommu_completion_wait(iommu);
2025 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2026 phys_addr_t paddr, size_t page_size, int iommu_prot,
2029 struct protection_domain *domain = to_pdomain(dom);
2030 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2034 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2035 (domain->iop.mode == PAGE_MODE_NONE))
2038 if (iommu_prot & IOMMU_READ)
2039 prot |= IOMMU_PROT_IR;
2040 if (iommu_prot & IOMMU_WRITE)
2041 prot |= IOMMU_PROT_IW;
2044 ret = ops->map(ops, iova, paddr, page_size, prot, gfp);
2045 domain_flush_np_cache(domain, iova, page_size);
2051 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2053 struct iommu_iotlb_gather *gather)
2055 struct protection_domain *domain = to_pdomain(dom);
2056 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2058 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2059 (domain->iop.mode == PAGE_MODE_NONE))
2062 return (ops->unmap) ? ops->unmap(ops, iova, page_size, gather) : 0;
2065 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2068 struct protection_domain *domain = to_pdomain(dom);
2069 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2071 return ops->iova_to_phys(ops, iova);
2074 static bool amd_iommu_capable(enum iommu_cap cap)
2077 case IOMMU_CAP_CACHE_COHERENCY:
2079 case IOMMU_CAP_INTR_REMAP:
2080 return (irq_remapping_enabled == 1);
2081 case IOMMU_CAP_NOEXEC:
2090 static void amd_iommu_get_resv_regions(struct device *dev,
2091 struct list_head *head)
2093 struct iommu_resv_region *region;
2094 struct unity_map_entry *entry;
2097 devid = get_device_id(dev);
2101 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2105 if (devid < entry->devid_start || devid > entry->devid_end)
2108 type = IOMMU_RESV_DIRECT;
2109 length = entry->address_end - entry->address_start;
2110 if (entry->prot & IOMMU_PROT_IR)
2112 if (entry->prot & IOMMU_PROT_IW)
2113 prot |= IOMMU_WRITE;
2114 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2115 /* Exclusion range */
2116 type = IOMMU_RESV_RESERVED;
2118 region = iommu_alloc_resv_region(entry->address_start,
2119 length, prot, type);
2121 dev_err(dev, "Out of memory allocating dm-regions\n");
2124 list_add_tail(®ion->list, head);
2127 region = iommu_alloc_resv_region(MSI_RANGE_START,
2128 MSI_RANGE_END - MSI_RANGE_START + 1,
2132 list_add_tail(®ion->list, head);
2134 region = iommu_alloc_resv_region(HT_RANGE_START,
2135 HT_RANGE_END - HT_RANGE_START + 1,
2136 0, IOMMU_RESV_RESERVED);
2139 list_add_tail(®ion->list, head);
2142 bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
2145 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2147 return dev_data->defer_attach;
2149 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2151 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2153 struct protection_domain *dom = to_pdomain(domain);
2154 unsigned long flags;
2156 spin_lock_irqsave(&dom->lock, flags);
2157 amd_iommu_domain_flush_tlb_pde(dom);
2158 amd_iommu_domain_flush_complete(dom);
2159 spin_unlock_irqrestore(&dom->lock, flags);
2162 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2163 struct iommu_iotlb_gather *gather)
2165 amd_iommu_flush_iotlb_all(domain);
2168 static int amd_iommu_def_domain_type(struct device *dev)
2170 struct iommu_dev_data *dev_data;
2172 dev_data = dev_iommu_priv_get(dev);
2177 * Do not identity map IOMMUv2 capable devices when memory encryption is
2178 * active, because some of those devices (AMD GPUs) don't have the
2179 * encryption bit in their DMA-mask and require remapping.
2181 if (!mem_encrypt_active() && dev_data->iommu_v2)
2182 return IOMMU_DOMAIN_IDENTITY;
2187 const struct iommu_ops amd_iommu_ops = {
2188 .capable = amd_iommu_capable,
2189 .domain_alloc = amd_iommu_domain_alloc,
2190 .domain_free = amd_iommu_domain_free,
2191 .attach_dev = amd_iommu_attach_device,
2192 .detach_dev = amd_iommu_detach_device,
2193 .map = amd_iommu_map,
2194 .unmap = amd_iommu_unmap,
2195 .iova_to_phys = amd_iommu_iova_to_phys,
2196 .probe_device = amd_iommu_probe_device,
2197 .release_device = amd_iommu_release_device,
2198 .probe_finalize = amd_iommu_probe_finalize,
2199 .device_group = amd_iommu_device_group,
2200 .get_resv_regions = amd_iommu_get_resv_regions,
2201 .put_resv_regions = generic_iommu_put_resv_regions,
2202 .is_attach_deferred = amd_iommu_is_attach_deferred,
2203 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2204 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2205 .iotlb_sync = amd_iommu_iotlb_sync,
2206 .def_domain_type = amd_iommu_def_domain_type,
2209 /*****************************************************************************
2211 * The next functions do a basic initialization of IOMMU for pass through
2214 * In passthrough mode the IOMMU is initialized and enabled but not used for
2215 * DMA-API translation.
2217 *****************************************************************************/
2219 /* IOMMUv2 specific functions */
2220 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2222 return atomic_notifier_chain_register(&ppr_notifier, nb);
2224 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2226 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2228 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2230 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2232 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2234 struct protection_domain *domain = to_pdomain(dom);
2235 unsigned long flags;
2237 spin_lock_irqsave(&domain->lock, flags);
2239 if (domain->iop.pgtbl_cfg.tlb)
2240 free_io_pgtable_ops(&domain->iop.iop.ops);
2242 spin_unlock_irqrestore(&domain->lock, flags);
2244 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2246 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2248 struct protection_domain *domain = to_pdomain(dom);
2249 unsigned long flags;
2252 /* Number of GCR3 table levels required */
2253 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2256 if (levels > amd_iommu_max_glx_val)
2259 spin_lock_irqsave(&domain->lock, flags);
2262 * Save us all sanity checks whether devices already in the
2263 * domain support IOMMUv2. Just force that the domain has no
2264 * devices attached when it is switched into IOMMUv2 mode.
2267 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2271 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2272 if (domain->gcr3_tbl == NULL)
2275 domain->glx = levels;
2276 domain->flags |= PD_IOMMUV2_MASK;
2278 amd_iommu_domain_update(domain);
2283 spin_unlock_irqrestore(&domain->lock, flags);
2287 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2289 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2290 u64 address, bool size)
2292 struct iommu_dev_data *dev_data;
2293 struct iommu_cmd cmd;
2296 if (!(domain->flags & PD_IOMMUV2_MASK))
2299 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2302 * IOMMU TLB needs to be flushed before Device TLB to
2303 * prevent device TLB refill from IOMMU TLB
2305 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2306 if (domain->dev_iommu[i] == 0)
2309 ret = iommu_queue_command(amd_iommus[i], &cmd);
2314 /* Wait until IOMMU TLB flushes are complete */
2315 amd_iommu_domain_flush_complete(domain);
2317 /* Now flush device TLBs */
2318 list_for_each_entry(dev_data, &domain->dev_list, list) {
2319 struct amd_iommu *iommu;
2323 There might be non-IOMMUv2 capable devices in an IOMMUv2
2326 if (!dev_data->ats.enabled)
2329 qdep = dev_data->ats.qdep;
2330 iommu = amd_iommu_rlookup_table[dev_data->devid];
2332 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2333 qdep, address, size);
2335 ret = iommu_queue_command(iommu, &cmd);
2340 /* Wait until all device TLBs are flushed */
2341 amd_iommu_domain_flush_complete(domain);
2350 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2353 return __flush_pasid(domain, pasid, address, false);
2356 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2359 struct protection_domain *domain = to_pdomain(dom);
2360 unsigned long flags;
2363 spin_lock_irqsave(&domain->lock, flags);
2364 ret = __amd_iommu_flush_page(domain, pasid, address);
2365 spin_unlock_irqrestore(&domain->lock, flags);
2369 EXPORT_SYMBOL(amd_iommu_flush_page);
2371 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2373 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2377 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2379 struct protection_domain *domain = to_pdomain(dom);
2380 unsigned long flags;
2383 spin_lock_irqsave(&domain->lock, flags);
2384 ret = __amd_iommu_flush_tlb(domain, pasid);
2385 spin_unlock_irqrestore(&domain->lock, flags);
2389 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2391 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2398 index = (pasid >> (9 * level)) & 0x1ff;
2404 if (!(*pte & GCR3_VALID)) {
2408 root = (void *)get_zeroed_page(GFP_ATOMIC);
2412 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
2415 root = iommu_phys_to_virt(*pte & PAGE_MASK);
2423 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
2428 if (domain->iop.mode != PAGE_MODE_NONE)
2431 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2435 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
2437 return __amd_iommu_flush_tlb(domain, pasid);
2440 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
2444 if (domain->iop.mode != PAGE_MODE_NONE)
2447 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2453 return __amd_iommu_flush_tlb(domain, pasid);
2456 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
2459 struct protection_domain *domain = to_pdomain(dom);
2460 unsigned long flags;
2463 spin_lock_irqsave(&domain->lock, flags);
2464 ret = __set_gcr3(domain, pasid, cr3);
2465 spin_unlock_irqrestore(&domain->lock, flags);
2469 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
2471 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
2473 struct protection_domain *domain = to_pdomain(dom);
2474 unsigned long flags;
2477 spin_lock_irqsave(&domain->lock, flags);
2478 ret = __clear_gcr3(domain, pasid);
2479 spin_unlock_irqrestore(&domain->lock, flags);
2483 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
2485 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
2486 int status, int tag)
2488 struct iommu_dev_data *dev_data;
2489 struct amd_iommu *iommu;
2490 struct iommu_cmd cmd;
2492 dev_data = dev_iommu_priv_get(&pdev->dev);
2493 iommu = amd_iommu_rlookup_table[dev_data->devid];
2495 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
2496 tag, dev_data->pri_tlp);
2498 return iommu_queue_command(iommu, &cmd);
2500 EXPORT_SYMBOL(amd_iommu_complete_ppr);
2502 int amd_iommu_device_info(struct pci_dev *pdev,
2503 struct amd_iommu_device_info *info)
2508 if (pdev == NULL || info == NULL)
2511 if (!amd_iommu_v2_supported())
2514 memset(info, 0, sizeof(*info));
2516 if (pci_ats_supported(pdev))
2517 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
2519 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2521 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
2523 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
2527 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
2528 max_pasids = min(max_pasids, (1 << 20));
2530 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
2531 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
2533 features = pci_pasid_features(pdev);
2534 if (features & PCI_PASID_CAP_EXEC)
2535 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
2536 if (features & PCI_PASID_CAP_PRIV)
2537 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
2542 EXPORT_SYMBOL(amd_iommu_device_info);
2544 #ifdef CONFIG_IRQ_REMAP
2546 /*****************************************************************************
2548 * Interrupt Remapping Implementation
2550 *****************************************************************************/
2552 static struct irq_chip amd_ir_chip;
2553 static DEFINE_SPINLOCK(iommu_table_lock);
2555 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
2559 dte = amd_iommu_dev_table[devid].data[2];
2560 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
2561 dte |= iommu_virt_to_phys(table->table);
2562 dte |= DTE_IRQ_REMAP_INTCTL;
2563 dte |= DTE_INTTABLEN;
2564 dte |= DTE_IRQ_REMAP_ENABLE;
2566 amd_iommu_dev_table[devid].data[2] = dte;
2569 static struct irq_remap_table *get_irq_table(u16 devid)
2571 struct irq_remap_table *table;
2573 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
2574 "%s: no iommu for devid %x\n", __func__, devid))
2577 table = irq_lookup_table[devid];
2578 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
2584 static struct irq_remap_table *__alloc_irq_table(void)
2586 struct irq_remap_table *table;
2588 table = kzalloc(sizeof(*table), GFP_KERNEL);
2592 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
2593 if (!table->table) {
2597 raw_spin_lock_init(&table->lock);
2599 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2600 memset(table->table, 0,
2601 MAX_IRQS_PER_TABLE * sizeof(u32));
2603 memset(table->table, 0,
2604 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
2608 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
2609 struct irq_remap_table *table)
2611 irq_lookup_table[devid] = table;
2612 set_dte_irq_entry(devid, table);
2613 iommu_flush_dte(iommu, devid);
2616 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
2619 struct irq_remap_table *table = data;
2621 irq_lookup_table[alias] = table;
2622 set_dte_irq_entry(alias, table);
2624 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
2629 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
2631 struct irq_remap_table *table = NULL;
2632 struct irq_remap_table *new_table = NULL;
2633 struct amd_iommu *iommu;
2634 unsigned long flags;
2637 spin_lock_irqsave(&iommu_table_lock, flags);
2639 iommu = amd_iommu_rlookup_table[devid];
2643 table = irq_lookup_table[devid];
2647 alias = amd_iommu_alias_table[devid];
2648 table = irq_lookup_table[alias];
2650 set_remap_table_entry(iommu, devid, table);
2653 spin_unlock_irqrestore(&iommu_table_lock, flags);
2655 /* Nothing there yet, allocate new irq remapping table */
2656 new_table = __alloc_irq_table();
2660 spin_lock_irqsave(&iommu_table_lock, flags);
2662 table = irq_lookup_table[devid];
2666 table = irq_lookup_table[alias];
2668 set_remap_table_entry(iommu, devid, table);
2676 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
2679 set_remap_table_entry(iommu, devid, table);
2682 set_remap_table_entry(iommu, alias, table);
2685 iommu_completion_wait(iommu);
2688 spin_unlock_irqrestore(&iommu_table_lock, flags);
2691 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
2697 static int alloc_irq_index(u16 devid, int count, bool align,
2698 struct pci_dev *pdev)
2700 struct irq_remap_table *table;
2701 int index, c, alignment = 1;
2702 unsigned long flags;
2703 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2708 table = alloc_irq_table(devid, pdev);
2713 alignment = roundup_pow_of_two(count);
2715 raw_spin_lock_irqsave(&table->lock, flags);
2717 /* Scan table for free entries */
2718 for (index = ALIGN(table->min_index, alignment), c = 0;
2719 index < MAX_IRQS_PER_TABLE;) {
2720 if (!iommu->irte_ops->is_allocated(table, index)) {
2724 index = ALIGN(index + 1, alignment);
2730 iommu->irte_ops->set_allocated(table, index - c + 1);
2742 raw_spin_unlock_irqrestore(&table->lock, flags);
2747 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
2748 struct amd_ir_data *data)
2751 struct irq_remap_table *table;
2752 struct amd_iommu *iommu;
2753 unsigned long flags;
2754 struct irte_ga *entry;
2756 iommu = amd_iommu_rlookup_table[devid];
2760 table = get_irq_table(devid);
2764 raw_spin_lock_irqsave(&table->lock, flags);
2766 entry = (struct irte_ga *)table->table;
2767 entry = &entry[index];
2769 ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
2770 entry->lo.val, entry->hi.val,
2771 irte->lo.val, irte->hi.val);
2773 * We use cmpxchg16 to atomically update the 128-bit IRTE,
2774 * and it cannot be updated by the hardware or other processors
2775 * behind us, so the return value of cmpxchg16 should be the
2776 * same as the old value.
2783 raw_spin_unlock_irqrestore(&table->lock, flags);
2785 iommu_flush_irt(iommu, devid);
2786 iommu_completion_wait(iommu);
2791 static int modify_irte(u16 devid, int index, union irte *irte)
2793 struct irq_remap_table *table;
2794 struct amd_iommu *iommu;
2795 unsigned long flags;
2797 iommu = amd_iommu_rlookup_table[devid];
2801 table = get_irq_table(devid);
2805 raw_spin_lock_irqsave(&table->lock, flags);
2806 table->table[index] = irte->val;
2807 raw_spin_unlock_irqrestore(&table->lock, flags);
2809 iommu_flush_irt(iommu, devid);
2810 iommu_completion_wait(iommu);
2815 static void free_irte(u16 devid, int index)
2817 struct irq_remap_table *table;
2818 struct amd_iommu *iommu;
2819 unsigned long flags;
2821 iommu = amd_iommu_rlookup_table[devid];
2825 table = get_irq_table(devid);
2829 raw_spin_lock_irqsave(&table->lock, flags);
2830 iommu->irte_ops->clear_allocated(table, index);
2831 raw_spin_unlock_irqrestore(&table->lock, flags);
2833 iommu_flush_irt(iommu, devid);
2834 iommu_completion_wait(iommu);
2837 static void irte_prepare(void *entry,
2838 u32 delivery_mode, bool dest_mode,
2839 u8 vector, u32 dest_apicid, int devid)
2841 union irte *irte = (union irte *) entry;
2844 irte->fields.vector = vector;
2845 irte->fields.int_type = delivery_mode;
2846 irte->fields.destination = dest_apicid;
2847 irte->fields.dm = dest_mode;
2848 irte->fields.valid = 1;
2851 static void irte_ga_prepare(void *entry,
2852 u32 delivery_mode, bool dest_mode,
2853 u8 vector, u32 dest_apicid, int devid)
2855 struct irte_ga *irte = (struct irte_ga *) entry;
2859 irte->lo.fields_remap.int_type = delivery_mode;
2860 irte->lo.fields_remap.dm = dest_mode;
2861 irte->hi.fields.vector = vector;
2862 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
2863 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
2864 irte->lo.fields_remap.valid = 1;
2867 static void irte_activate(void *entry, u16 devid, u16 index)
2869 union irte *irte = (union irte *) entry;
2871 irte->fields.valid = 1;
2872 modify_irte(devid, index, irte);
2875 static void irte_ga_activate(void *entry, u16 devid, u16 index)
2877 struct irte_ga *irte = (struct irte_ga *) entry;
2879 irte->lo.fields_remap.valid = 1;
2880 modify_irte_ga(devid, index, irte, NULL);
2883 static void irte_deactivate(void *entry, u16 devid, u16 index)
2885 union irte *irte = (union irte *) entry;
2887 irte->fields.valid = 0;
2888 modify_irte(devid, index, irte);
2891 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
2893 struct irte_ga *irte = (struct irte_ga *) entry;
2895 irte->lo.fields_remap.valid = 0;
2896 modify_irte_ga(devid, index, irte, NULL);
2899 static void irte_set_affinity(void *entry, u16 devid, u16 index,
2900 u8 vector, u32 dest_apicid)
2902 union irte *irte = (union irte *) entry;
2904 irte->fields.vector = vector;
2905 irte->fields.destination = dest_apicid;
2906 modify_irte(devid, index, irte);
2909 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
2910 u8 vector, u32 dest_apicid)
2912 struct irte_ga *irte = (struct irte_ga *) entry;
2914 if (!irte->lo.fields_remap.guest_mode) {
2915 irte->hi.fields.vector = vector;
2916 irte->lo.fields_remap.destination =
2917 APICID_TO_IRTE_DEST_LO(dest_apicid);
2918 irte->hi.fields.destination =
2919 APICID_TO_IRTE_DEST_HI(dest_apicid);
2920 modify_irte_ga(devid, index, irte, NULL);
2924 #define IRTE_ALLOCATED (~1U)
2925 static void irte_set_allocated(struct irq_remap_table *table, int index)
2927 table->table[index] = IRTE_ALLOCATED;
2930 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
2932 struct irte_ga *ptr = (struct irte_ga *)table->table;
2933 struct irte_ga *irte = &ptr[index];
2935 memset(&irte->lo.val, 0, sizeof(u64));
2936 memset(&irte->hi.val, 0, sizeof(u64));
2937 irte->hi.fields.vector = 0xff;
2940 static bool irte_is_allocated(struct irq_remap_table *table, int index)
2942 union irte *ptr = (union irte *)table->table;
2943 union irte *irte = &ptr[index];
2945 return irte->val != 0;
2948 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
2950 struct irte_ga *ptr = (struct irte_ga *)table->table;
2951 struct irte_ga *irte = &ptr[index];
2953 return irte->hi.fields.vector != 0;
2956 static void irte_clear_allocated(struct irq_remap_table *table, int index)
2958 table->table[index] = 0;
2961 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
2963 struct irte_ga *ptr = (struct irte_ga *)table->table;
2964 struct irte_ga *irte = &ptr[index];
2966 memset(&irte->lo.val, 0, sizeof(u64));
2967 memset(&irte->hi.val, 0, sizeof(u64));
2970 static int get_devid(struct irq_alloc_info *info)
2972 switch (info->type) {
2973 case X86_IRQ_ALLOC_TYPE_IOAPIC:
2974 return get_ioapic_devid(info->devid);
2975 case X86_IRQ_ALLOC_TYPE_HPET:
2976 return get_hpet_devid(info->devid);
2977 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
2978 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
2979 return get_device_id(msi_desc_to_dev(info->desc));
2986 struct irq_remap_ops amd_iommu_irq_ops = {
2987 .prepare = amd_iommu_prepare,
2988 .enable = amd_iommu_enable,
2989 .disable = amd_iommu_disable,
2990 .reenable = amd_iommu_reenable,
2991 .enable_faulting = amd_iommu_enable_faulting,
2994 static void fill_msi_msg(struct msi_msg *msg, u32 index)
2997 msg->address_lo = 0;
2998 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
2999 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
3002 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3003 struct irq_cfg *irq_cfg,
3004 struct irq_alloc_info *info,
3005 int devid, int index, int sub_handle)
3007 struct irq_2_irte *irte_info = &data->irq_2_irte;
3008 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3013 data->irq_2_irte.devid = devid;
3014 data->irq_2_irte.index = index + sub_handle;
3015 iommu->irte_ops->prepare(data->entry, apic->delivery_mode,
3016 apic->dest_mode_logical, irq_cfg->vector,
3017 irq_cfg->dest_apicid, devid);
3019 switch (info->type) {
3020 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3021 case X86_IRQ_ALLOC_TYPE_HPET:
3022 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3023 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3024 fill_msi_msg(&data->msi_entry, irte_info->index);
3033 struct amd_irte_ops irte_32_ops = {
3034 .prepare = irte_prepare,
3035 .activate = irte_activate,
3036 .deactivate = irte_deactivate,
3037 .set_affinity = irte_set_affinity,
3038 .set_allocated = irte_set_allocated,
3039 .is_allocated = irte_is_allocated,
3040 .clear_allocated = irte_clear_allocated,
3043 struct amd_irte_ops irte_128_ops = {
3044 .prepare = irte_ga_prepare,
3045 .activate = irte_ga_activate,
3046 .deactivate = irte_ga_deactivate,
3047 .set_affinity = irte_ga_set_affinity,
3048 .set_allocated = irte_ga_set_allocated,
3049 .is_allocated = irte_ga_is_allocated,
3050 .clear_allocated = irte_ga_clear_allocated,
3053 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3054 unsigned int nr_irqs, void *arg)
3056 struct irq_alloc_info *info = arg;
3057 struct irq_data *irq_data;
3058 struct amd_ir_data *data = NULL;
3059 struct irq_cfg *cfg;
3065 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
3066 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
3070 * With IRQ remapping enabled, don't need contiguous CPU vectors
3071 * to support multiple MSI interrupts.
3073 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
3074 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3076 devid = get_devid(info);
3080 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3084 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3085 struct irq_remap_table *table;
3086 struct amd_iommu *iommu;
3088 table = alloc_irq_table(devid, NULL);
3090 if (!table->min_index) {
3092 * Keep the first 32 indexes free for IOAPIC
3095 table->min_index = 32;
3096 iommu = amd_iommu_rlookup_table[devid];
3097 for (i = 0; i < 32; ++i)
3098 iommu->irte_ops->set_allocated(table, i);
3100 WARN_ON(table->min_index != 32);
3101 index = info->ioapic.pin;
3105 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI ||
3106 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) {
3107 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
3109 index = alloc_irq_index(devid, nr_irqs, align,
3110 msi_desc_to_pci_dev(info->desc));
3112 index = alloc_irq_index(devid, nr_irqs, false, NULL);
3116 pr_warn("Failed to allocate IRTE\n");
3118 goto out_free_parent;
3121 for (i = 0; i < nr_irqs; i++) {
3122 irq_data = irq_domain_get_irq_data(domain, virq + i);
3123 cfg = irq_data ? irqd_cfg(irq_data) : NULL;
3130 data = kzalloc(sizeof(*data), GFP_KERNEL);
3134 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3135 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3137 data->entry = kzalloc(sizeof(struct irte_ga),
3144 irq_data->hwirq = (devid << 16) + i;
3145 irq_data->chip_data = data;
3146 irq_data->chip = &amd_ir_chip;
3147 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3148 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3154 for (i--; i >= 0; i--) {
3155 irq_data = irq_domain_get_irq_data(domain, virq + i);
3157 kfree(irq_data->chip_data);
3159 for (i = 0; i < nr_irqs; i++)
3160 free_irte(devid, index + i);
3162 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3166 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3167 unsigned int nr_irqs)
3169 struct irq_2_irte *irte_info;
3170 struct irq_data *irq_data;
3171 struct amd_ir_data *data;
3174 for (i = 0; i < nr_irqs; i++) {
3175 irq_data = irq_domain_get_irq_data(domain, virq + i);
3176 if (irq_data && irq_data->chip_data) {
3177 data = irq_data->chip_data;
3178 irte_info = &data->irq_2_irte;
3179 free_irte(irte_info->devid, irte_info->index);
3184 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3187 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3188 struct amd_ir_data *ir_data,
3189 struct irq_2_irte *irte_info,
3190 struct irq_cfg *cfg);
3192 static int irq_remapping_activate(struct irq_domain *domain,
3193 struct irq_data *irq_data, bool reserve)
3195 struct amd_ir_data *data = irq_data->chip_data;
3196 struct irq_2_irte *irte_info = &data->irq_2_irte;
3197 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3198 struct irq_cfg *cfg = irqd_cfg(irq_data);
3203 iommu->irte_ops->activate(data->entry, irte_info->devid,
3205 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3209 static void irq_remapping_deactivate(struct irq_domain *domain,
3210 struct irq_data *irq_data)
3212 struct amd_ir_data *data = irq_data->chip_data;
3213 struct irq_2_irte *irte_info = &data->irq_2_irte;
3214 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3217 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3221 static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
3222 enum irq_domain_bus_token bus_token)
3224 struct amd_iommu *iommu;
3227 if (!amd_iommu_irq_remap)
3230 if (x86_fwspec_is_ioapic(fwspec))
3231 devid = get_ioapic_devid(fwspec->param[0]);
3232 else if (x86_fwspec_is_hpet(fwspec))
3233 devid = get_hpet_devid(fwspec->param[0]);
3238 iommu = amd_iommu_rlookup_table[devid];
3239 return iommu && iommu->ir_domain == d;
3242 static const struct irq_domain_ops amd_ir_domain_ops = {
3243 .select = irq_remapping_select,
3244 .alloc = irq_remapping_alloc,
3245 .free = irq_remapping_free,
3246 .activate = irq_remapping_activate,
3247 .deactivate = irq_remapping_deactivate,
3250 int amd_iommu_activate_guest_mode(void *data)
3252 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3253 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3256 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3257 !entry || entry->lo.fields_vapic.guest_mode)
3260 valid = entry->lo.fields_vapic.valid;
3265 entry->lo.fields_vapic.valid = valid;
3266 entry->lo.fields_vapic.guest_mode = 1;
3267 entry->lo.fields_vapic.ga_log_intr = 1;
3268 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3269 entry->hi.fields.vector = ir_data->ga_vector;
3270 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3272 return modify_irte_ga(ir_data->irq_2_irte.devid,
3273 ir_data->irq_2_irte.index, entry, ir_data);
3275 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3277 int amd_iommu_deactivate_guest_mode(void *data)
3279 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3280 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3281 struct irq_cfg *cfg = ir_data->cfg;
3284 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3285 !entry || !entry->lo.fields_vapic.guest_mode)
3288 valid = entry->lo.fields_remap.valid;
3293 entry->lo.fields_remap.valid = valid;
3294 entry->lo.fields_remap.dm = apic->dest_mode_logical;
3295 entry->lo.fields_remap.int_type = apic->delivery_mode;
3296 entry->hi.fields.vector = cfg->vector;
3297 entry->lo.fields_remap.destination =
3298 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3299 entry->hi.fields.destination =
3300 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3302 return modify_irte_ga(ir_data->irq_2_irte.devid,
3303 ir_data->irq_2_irte.index, entry, ir_data);
3305 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3307 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3310 struct amd_iommu *iommu;
3311 struct amd_iommu_pi_data *pi_data = vcpu_info;
3312 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3313 struct amd_ir_data *ir_data = data->chip_data;
3314 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3315 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3318 * This device has never been set up for guest mode.
3319 * we should not modify the IRTE
3321 if (!dev_data || !dev_data->use_vapic)
3324 ir_data->cfg = irqd_cfg(data);
3325 pi_data->ir_data = ir_data;
3328 * SVM tries to set up for VAPIC mode, but we are in
3329 * legacy mode. So, we force legacy mode instead.
3331 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3332 pr_debug("%s: Fall back to using intr legacy remap\n",
3334 pi_data->is_guest_mode = false;
3337 iommu = amd_iommu_rlookup_table[irte_info->devid];
3341 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3342 if (pi_data->is_guest_mode) {
3343 ir_data->ga_root_ptr = (pi_data->base >> 12);
3344 ir_data->ga_vector = vcpu_pi_info->vector;
3345 ir_data->ga_tag = pi_data->ga_tag;
3346 ret = amd_iommu_activate_guest_mode(ir_data);
3348 ir_data->cached_ga_tag = pi_data->ga_tag;
3350 ret = amd_iommu_deactivate_guest_mode(ir_data);
3353 * This communicates the ga_tag back to the caller
3354 * so that it can do all the necessary clean up.
3357 ir_data->cached_ga_tag = 0;
3364 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3365 struct amd_ir_data *ir_data,
3366 struct irq_2_irte *irte_info,
3367 struct irq_cfg *cfg)
3371 * Atomically updates the IRTE with the new destination, vector
3372 * and flushes the interrupt entry cache.
3374 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
3375 irte_info->index, cfg->vector,
3379 static int amd_ir_set_affinity(struct irq_data *data,
3380 const struct cpumask *mask, bool force)
3382 struct amd_ir_data *ir_data = data->chip_data;
3383 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3384 struct irq_cfg *cfg = irqd_cfg(data);
3385 struct irq_data *parent = data->parent_data;
3386 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3392 ret = parent->chip->irq_set_affinity(parent, mask, force);
3393 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3396 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
3398 * After this point, all the interrupts will start arriving
3399 * at the new destination. So, time to cleanup the previous
3400 * vector allocation.
3402 send_cleanup_vector(cfg);
3404 return IRQ_SET_MASK_OK_DONE;
3407 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3409 struct amd_ir_data *ir_data = irq_data->chip_data;
3411 *msg = ir_data->msi_entry;
3414 static struct irq_chip amd_ir_chip = {
3416 .irq_ack = apic_ack_irq,
3417 .irq_set_affinity = amd_ir_set_affinity,
3418 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
3419 .irq_compose_msi_msg = ir_compose_msi_msg,
3422 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3424 struct fwnode_handle *fn;
3426 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
3429 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
3430 if (!iommu->ir_domain) {
3431 irq_domain_free_fwnode(fn);
3435 iommu->ir_domain->parent = arch_get_ir_parent_domain();
3436 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
3442 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
3444 unsigned long flags;
3445 struct amd_iommu *iommu;
3446 struct irq_remap_table *table;
3447 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3448 int devid = ir_data->irq_2_irte.devid;
3449 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3450 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
3452 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3453 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
3456 iommu = amd_iommu_rlookup_table[devid];
3460 table = get_irq_table(devid);
3464 raw_spin_lock_irqsave(&table->lock, flags);
3466 if (ref->lo.fields_vapic.guest_mode) {
3468 ref->lo.fields_vapic.destination =
3469 APICID_TO_IRTE_DEST_LO(cpu);
3470 ref->hi.fields.destination =
3471 APICID_TO_IRTE_DEST_HI(cpu);
3473 ref->lo.fields_vapic.is_run = is_run;
3477 raw_spin_unlock_irqrestore(&table->lock, flags);
3479 iommu_flush_irt(iommu, devid);
3480 iommu_completion_wait(iommu);
3483 EXPORT_SYMBOL(amd_iommu_update_ga);