1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/pci.h>
12 #include <linux/acpi.h>
13 #include <linux/list.h>
14 #include <linux/bitmap.h>
15 #include <linux/slab.h>
16 #include <linux/syscore_ops.h>
17 #include <linux/interrupt.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/amd-iommu.h>
21 #include <linux/export.h>
22 #include <linux/kmemleak.h>
23 #include <linux/mem_encrypt.h>
24 #include <asm/pci-direct.h>
25 #include <asm/iommu.h>
28 #include <asm/x86_init.h>
29 #include <asm/iommu_table.h>
30 #include <asm/io_apic.h>
31 #include <asm/irq_remapping.h>
32 #include <asm/set_memory.h>
34 #include <linux/crash_dump.h>
36 #include "amd_iommu.h"
37 #include "../irq_remapping.h"
40 * definitions for the ACPI scanning code
42 #define IVRS_HEADER_LENGTH 48
44 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
45 #define ACPI_IVMD_TYPE_ALL 0x20
46 #define ACPI_IVMD_TYPE 0x21
47 #define ACPI_IVMD_TYPE_RANGE 0x22
49 #define IVHD_DEV_ALL 0x01
50 #define IVHD_DEV_SELECT 0x02
51 #define IVHD_DEV_SELECT_RANGE_START 0x03
52 #define IVHD_DEV_RANGE_END 0x04
53 #define IVHD_DEV_ALIAS 0x42
54 #define IVHD_DEV_ALIAS_RANGE 0x43
55 #define IVHD_DEV_EXT_SELECT 0x46
56 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
57 #define IVHD_DEV_SPECIAL 0x48
58 #define IVHD_DEV_ACPI_HID 0xf0
60 #define UID_NOT_PRESENT 0
61 #define UID_IS_INTEGER 1
62 #define UID_IS_CHARACTER 2
64 #define IVHD_SPECIAL_IOAPIC 1
65 #define IVHD_SPECIAL_HPET 2
67 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
68 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
69 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
70 #define IVHD_FLAG_ISOC_EN_MASK 0x08
72 #define IVMD_FLAG_EXCL_RANGE 0x08
73 #define IVMD_FLAG_IW 0x04
74 #define IVMD_FLAG_IR 0x02
75 #define IVMD_FLAG_UNITY_MAP 0x01
77 #define ACPI_DEVFLAG_INITPASS 0x01
78 #define ACPI_DEVFLAG_EXTINT 0x02
79 #define ACPI_DEVFLAG_NMI 0x04
80 #define ACPI_DEVFLAG_SYSMGT1 0x10
81 #define ACPI_DEVFLAG_SYSMGT2 0x20
82 #define ACPI_DEVFLAG_LINT0 0x40
83 #define ACPI_DEVFLAG_LINT1 0x80
84 #define ACPI_DEVFLAG_ATSDIS 0x10000000
86 #define LOOP_TIMEOUT 100000
88 * ACPI table definitions
90 * These data structures are laid over the table to parse the important values
94 extern const struct iommu_ops amd_iommu_ops;
97 * structure describing one IOMMU in the ACPI table. Typically followed by one
98 * or more ivhd_entrys.
111 /* Following only valid on IVHD type 11h and 40h */
112 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
114 } __attribute__((packed));
117 * A device entry describing which devices a specific IOMMU translates and
118 * which requestor ids they use.
130 } __attribute__((packed));
133 * An AMD IOMMU memory definition structure. It defines things like exclusion
134 * ranges for devices and regions that should be unity mapped.
145 } __attribute__((packed));
148 bool amd_iommu_irq_remap __read_mostly;
150 enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1;
152 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
153 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
155 static bool amd_iommu_detected;
156 static bool amd_iommu_disabled __initdata;
157 static bool amd_iommu_force_enable __initdata;
158 static int amd_iommu_target_ivhd_type;
160 u16 amd_iommu_last_bdf; /* largest PCI device id we have
162 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
164 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
166 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
169 /* Array to assign indices to IOMMUs*/
170 struct amd_iommu *amd_iommus[MAX_IOMMUS];
172 /* Number of IOMMUs present in the system */
173 static int amd_iommus_present;
175 /* IOMMUs have a non-present cache? */
176 bool amd_iommu_np_cache __read_mostly;
177 bool amd_iommu_iotlb_sup __read_mostly = true;
179 u32 amd_iommu_max_pasid __read_mostly = ~0;
181 bool amd_iommu_v2_present __read_mostly;
182 static bool amd_iommu_pc_present __read_mostly;
184 bool amd_iommu_force_isolation __read_mostly;
187 * Pointer to the device table which is shared by all AMD IOMMUs
188 * it is indexed by the PCI device id or the HT unit id and contains
189 * information about the domain the device belongs to as well as the
190 * page table root pointer.
192 struct dev_table_entry *amd_iommu_dev_table;
194 * Pointer to a device table which the content of old device table
195 * will be copied to. It's only be used in kdump kernel.
197 static struct dev_table_entry *old_dev_tbl_cpy;
200 * The alias table is a driver specific data structure which contains the
201 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
202 * More than one device can share the same requestor id.
204 u16 *amd_iommu_alias_table;
207 * The rlookup table is used to find the IOMMU which is responsible
208 * for a specific device. It is also indexed by the PCI device id.
210 struct amd_iommu **amd_iommu_rlookup_table;
213 * This table is used to find the irq remapping table for a given device id
216 struct irq_remap_table **irq_lookup_table;
219 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
220 * to know which ones are already in use.
222 unsigned long *amd_iommu_pd_alloc_bitmap;
224 static u32 dev_table_size; /* size of the device table */
225 static u32 alias_table_size; /* size of the alias table */
226 static u32 rlookup_table_size; /* size if the rlookup table */
228 enum iommu_init_state {
238 IOMMU_CMDLINE_DISABLED,
241 /* Early ioapic and hpet maps from kernel command line */
242 #define EARLY_MAP_SIZE 4
243 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
244 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
245 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
247 static int __initdata early_ioapic_map_size;
248 static int __initdata early_hpet_map_size;
249 static int __initdata early_acpihid_map_size;
251 static bool __initdata cmdline_maps;
253 static enum iommu_init_state init_state = IOMMU_START_STATE;
255 static int amd_iommu_enable_interrupts(void);
256 static int __init iommu_go_to_state(enum iommu_init_state state);
257 static void init_device_table_dma(void);
259 static bool amd_iommu_pre_enabled = true;
261 static u32 amd_iommu_ivinfo __initdata;
263 bool translation_pre_enabled(struct amd_iommu *iommu)
265 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
268 static void clear_translation_pre_enabled(struct amd_iommu *iommu)
270 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
273 static void init_translation_status(struct amd_iommu *iommu)
277 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
278 if (ctrl & (1<<CONTROL_IOMMU_EN))
279 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
282 static inline void update_last_devid(u16 devid)
284 if (devid > amd_iommu_last_bdf)
285 amd_iommu_last_bdf = devid;
288 static inline unsigned long tbl_size(int entry_size)
290 unsigned shift = PAGE_SHIFT +
291 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
296 int amd_iommu_get_num_iommus(void)
298 return amd_iommus_present;
302 * For IVHD type 0x11/0x40, EFR is also available via IVHD.
303 * Default to IVHD EFR since it is available sooner
304 * (i.e. before PCI init).
306 static void __init early_iommu_features_init(struct amd_iommu *iommu,
307 struct ivhd_header *h)
309 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP)
310 iommu->features = h->efr_reg;
313 /* Access to l1 and l2 indexed register spaces */
315 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
319 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
320 pci_read_config_dword(iommu->dev, 0xfc, &val);
324 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
326 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
327 pci_write_config_dword(iommu->dev, 0xfc, val);
328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
331 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
335 pci_write_config_dword(iommu->dev, 0xf0, address);
336 pci_read_config_dword(iommu->dev, 0xf4, &val);
340 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
342 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
343 pci_write_config_dword(iommu->dev, 0xf4, val);
346 /****************************************************************************
348 * AMD IOMMU MMIO register space handling functions
350 * These functions are used to program the IOMMU device registers in
351 * MMIO space required for that driver.
353 ****************************************************************************/
356 * This function set the exclusion range in the IOMMU. DMA accesses to the
357 * exclusion range are passed through untranslated
359 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
361 u64 start = iommu->exclusion_start & PAGE_MASK;
362 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
365 if (!iommu->exclusion_start)
368 entry = start | MMIO_EXCL_ENABLE_MASK;
369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
370 &entry, sizeof(entry));
373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
374 &entry, sizeof(entry));
377 static void iommu_set_cwwb_range(struct amd_iommu *iommu)
379 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem);
380 u64 entry = start & PM_ADDR_MASK;
382 if (!iommu_feature(iommu, FEATURE_SNP))
386 * Re-purpose Exclusion base/limit registers for Completion wait
387 * write-back base/limit.
389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
390 &entry, sizeof(entry));
393 * Default to 4 Kbytes, which can be specified by setting base
394 * address equal to the limit address.
396 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
397 &entry, sizeof(entry));
400 /* Programs the physical address of the device table into the IOMMU hardware */
401 static void iommu_set_device_table(struct amd_iommu *iommu)
405 BUG_ON(iommu->mmio_base == NULL);
407 entry = iommu_virt_to_phys(amd_iommu_dev_table);
408 entry |= (dev_table_size >> 12) - 1;
409 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
410 &entry, sizeof(entry));
413 /* Generic functions to enable/disable certain features of the IOMMU. */
414 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
418 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
419 ctrl |= (1ULL << bit);
420 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
423 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
427 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
428 ctrl &= ~(1ULL << bit);
429 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
432 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
436 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
437 ctrl &= ~CTRL_INV_TO_MASK;
438 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
439 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
442 /* Function to enable the hardware */
443 static void iommu_enable(struct amd_iommu *iommu)
445 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
448 static void iommu_disable(struct amd_iommu *iommu)
450 if (!iommu->mmio_base)
453 /* Disable command buffer */
454 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
456 /* Disable event logging and event interrupts */
457 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
458 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
460 /* Disable IOMMU GA_LOG */
461 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
462 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
464 /* Disable IOMMU hardware itself */
465 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
469 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
470 * the system has one.
472 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
474 if (!request_mem_region(address, end, "amd_iommu")) {
475 pr_err("Can not reserve memory region %llx-%llx for mmio\n",
477 pr_err("This is a BIOS bug. Please contact your hardware vendor\n");
481 return (u8 __iomem *)ioremap(address, end);
484 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
486 if (iommu->mmio_base)
487 iounmap(iommu->mmio_base);
488 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
491 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
507 /****************************************************************************
509 * The functions below belong to the first pass of AMD IOMMU ACPI table
510 * parsing. In this pass we try to find out the highest device id this
511 * code has to handle. Upon this information the size of the shared data
512 * structures is determined later.
514 ****************************************************************************/
517 * This function calculates the length of a given IVHD entry
519 static inline int ivhd_entry_length(u8 *ivhd)
521 u32 type = ((struct ivhd_entry *)ivhd)->type;
524 return 0x04 << (*ivhd >> 6);
525 } else if (type == IVHD_DEV_ACPI_HID) {
526 /* For ACPI_HID, offset 21 is uid len */
527 return *((u8 *)ivhd + 21) + 22;
533 * After reading the highest device id from the IOMMU PCI capability header
534 * this function looks if there is a higher device id defined in the ACPI table
536 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
538 u8 *p = (void *)h, *end = (void *)h;
539 struct ivhd_entry *dev;
541 u32 ivhd_size = get_ivhd_header_size(h);
544 pr_err("Unsupported IVHD type %#x\n", h->type);
552 dev = (struct ivhd_entry *)p;
555 /* Use maximum BDF value for DEV_ALL */
556 update_last_devid(0xffff);
558 case IVHD_DEV_SELECT:
559 case IVHD_DEV_RANGE_END:
561 case IVHD_DEV_EXT_SELECT:
562 /* all the above subfield types refer to device ids */
563 update_last_devid(dev->devid);
568 p += ivhd_entry_length(p);
576 static int __init check_ivrs_checksum(struct acpi_table_header *table)
579 u8 checksum = 0, *p = (u8 *)table;
581 for (i = 0; i < table->length; ++i)
584 /* ACPI table corrupt */
585 pr_err(FW_BUG "IVRS invalid checksum\n");
593 * Iterate over all IVHD entries in the ACPI table and find the highest device
594 * id which we need to handle. This is the first of three functions which parse
595 * the ACPI table. So we check the checksum here.
597 static int __init find_last_devid_acpi(struct acpi_table_header *table)
599 u8 *p = (u8 *)table, *end = (u8 *)table;
600 struct ivhd_header *h;
602 p += IVRS_HEADER_LENGTH;
604 end += table->length;
606 h = (struct ivhd_header *)p;
607 if (h->type == amd_iommu_target_ivhd_type) {
608 int ret = find_last_devid_from_ivhd(h);
620 /****************************************************************************
622 * The following functions belong to the code path which parses the ACPI table
623 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
624 * data structures, initialize the device/alias/rlookup table and also
625 * basically initialize the hardware.
627 ****************************************************************************/
630 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
631 * write commands to that buffer later and the IOMMU will execute them
634 static int __init alloc_command_buffer(struct amd_iommu *iommu)
636 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
637 get_order(CMD_BUFFER_SIZE));
639 return iommu->cmd_buf ? 0 : -ENOMEM;
643 * This function resets the command buffer if the IOMMU stopped fetching
646 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
648 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
650 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
651 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
652 iommu->cmd_buf_head = 0;
653 iommu->cmd_buf_tail = 0;
655 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
659 * This function writes the command buffer address to the hardware and
662 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
666 BUG_ON(iommu->cmd_buf == NULL);
668 entry = iommu_virt_to_phys(iommu->cmd_buf);
669 entry |= MMIO_CMD_SIZE_512;
671 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
672 &entry, sizeof(entry));
674 amd_iommu_reset_cmd_buffer(iommu);
678 * This function disables the command buffer
680 static void iommu_disable_command_buffer(struct amd_iommu *iommu)
682 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
685 static void __init free_command_buffer(struct amd_iommu *iommu)
687 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
690 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
691 gfp_t gfp, size_t size)
693 int order = get_order(size);
694 void *buf = (void *)__get_free_pages(gfp, order);
697 iommu_feature(iommu, FEATURE_SNP) &&
698 set_memory_4k((unsigned long)buf, (1 << order))) {
699 free_pages((unsigned long)buf, order);
706 /* allocates the memory where the IOMMU will log its events to */
707 static int __init alloc_event_buffer(struct amd_iommu *iommu)
709 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO,
712 return iommu->evt_buf ? 0 : -ENOMEM;
715 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
719 BUG_ON(iommu->evt_buf == NULL);
721 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
723 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
724 &entry, sizeof(entry));
726 /* set head and tail to zero manually */
727 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
728 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
730 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
734 * This function disables the event log buffer
736 static void iommu_disable_event_buffer(struct amd_iommu *iommu)
738 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
741 static void __init free_event_buffer(struct amd_iommu *iommu)
743 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
746 /* allocates the memory where the IOMMU will log its events to */
747 static int __init alloc_ppr_log(struct amd_iommu *iommu)
749 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO,
752 return iommu->ppr_log ? 0 : -ENOMEM;
755 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
759 if (iommu->ppr_log == NULL)
762 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
764 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
765 &entry, sizeof(entry));
767 /* set head and tail to zero manually */
768 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
769 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
771 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN);
772 iommu_feature_enable(iommu, CONTROL_PPR_EN);
775 static void __init free_ppr_log(struct amd_iommu *iommu)
777 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
780 static void free_ga_log(struct amd_iommu *iommu)
782 #ifdef CONFIG_IRQ_REMAP
783 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE));
784 free_pages((unsigned long)iommu->ga_log_tail, get_order(8));
788 static int iommu_ga_log_enable(struct amd_iommu *iommu)
790 #ifdef CONFIG_IRQ_REMAP
796 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
798 /* Check if already running */
799 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
802 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
803 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
805 for (i = 0; i < LOOP_TIMEOUT; ++i) {
806 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
807 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
811 if (i >= LOOP_TIMEOUT)
813 #endif /* CONFIG_IRQ_REMAP */
817 #ifdef CONFIG_IRQ_REMAP
818 static int iommu_init_ga_log(struct amd_iommu *iommu)
822 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
825 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
826 get_order(GA_LOG_SIZE));
830 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
832 if (!iommu->ga_log_tail)
835 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
836 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
837 &entry, sizeof(entry));
838 entry = (iommu_virt_to_phys(iommu->ga_log_tail) &
839 (BIT_ULL(52)-1)) & ~7ULL;
840 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
841 &entry, sizeof(entry));
842 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
843 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
850 #endif /* CONFIG_IRQ_REMAP */
852 static int iommu_init_ga(struct amd_iommu *iommu)
856 #ifdef CONFIG_IRQ_REMAP
857 /* Note: We have already checked GASup from IVRS table.
858 * Now, we need to make sure that GAMSup is set.
860 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
861 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
862 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
864 ret = iommu_init_ga_log(iommu);
865 #endif /* CONFIG_IRQ_REMAP */
870 static int __init alloc_cwwb_sem(struct amd_iommu *iommu)
872 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1);
874 return iommu->cmd_sem ? 0 : -ENOMEM;
877 static void __init free_cwwb_sem(struct amd_iommu *iommu)
880 free_page((unsigned long)iommu->cmd_sem);
883 static void iommu_enable_xt(struct amd_iommu *iommu)
885 #ifdef CONFIG_IRQ_REMAP
887 * XT mode (32-bit APIC destination ID) requires
888 * GA mode (128-bit IRTE support) as a prerequisite.
890 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
891 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
892 iommu_feature_enable(iommu, CONTROL_XT_EN);
893 #endif /* CONFIG_IRQ_REMAP */
896 static void iommu_enable_gt(struct amd_iommu *iommu)
898 if (!iommu_feature(iommu, FEATURE_GT))
901 iommu_feature_enable(iommu, CONTROL_GT_EN);
904 /* sets a specific bit in the device table entry. */
905 static void set_dev_entry_bit(u16 devid, u8 bit)
907 int i = (bit >> 6) & 0x03;
908 int _bit = bit & 0x3f;
910 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
913 static int get_dev_entry_bit(u16 devid, u8 bit)
915 int i = (bit >> 6) & 0x03;
916 int _bit = bit & 0x3f;
918 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
922 static bool copy_device_table(void)
924 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
925 struct dev_table_entry *old_devtb = NULL;
926 u32 lo, hi, devid, old_devtb_size;
927 phys_addr_t old_devtb_phys;
928 struct amd_iommu *iommu;
929 u16 dom_id, dte_v, irq_v;
933 if (!amd_iommu_pre_enabled)
936 pr_warn("Translation is already enabled - trying to copy translation structures\n");
937 for_each_iommu(iommu) {
938 /* All IOMMUs should use the same device table with the same size */
939 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
940 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
941 entry = (((u64) hi) << 32) + lo;
942 if (last_entry && last_entry != entry) {
943 pr_err("IOMMU:%d should use the same dev table as others!\n",
949 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
950 if (old_devtb_size != dev_table_size) {
951 pr_err("The device table size of IOMMU:%d is not expected!\n",
958 * When SME is enabled in the first kernel, the entry includes the
959 * memory encryption mask(sme_me_mask), we must remove the memory
960 * encryption mask to obtain the true physical address in kdump kernel.
962 old_devtb_phys = __sme_clr(entry) & PAGE_MASK;
964 if (old_devtb_phys >= 0x100000000ULL) {
965 pr_err("The address of old device table is above 4G, not trustworthy!\n");
968 old_devtb = (sme_active() && is_kdump_kernel())
969 ? (__force void *)ioremap_encrypted(old_devtb_phys,
971 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
976 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
977 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
978 get_order(dev_table_size));
979 if (old_dev_tbl_cpy == NULL) {
980 pr_err("Failed to allocate memory for copying old device table!\n");
984 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
985 old_dev_tbl_cpy[devid] = old_devtb[devid];
986 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
987 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
989 if (dte_v && dom_id) {
990 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
991 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
992 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
993 /* If gcr3 table existed, mask it out */
994 if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
995 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
996 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
997 old_dev_tbl_cpy[devid].data[1] &= ~tmp;
998 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
1000 old_dev_tbl_cpy[devid].data[0] &= ~tmp;
1004 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
1005 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
1006 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK;
1007 if (irq_v && (int_ctl || int_tab_len)) {
1008 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
1009 (int_tab_len != DTE_INTTABLEN)) {
1010 pr_err("Wrong old irq remapping flag: %#x\n", devid);
1014 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
1017 memunmap(old_devtb);
1022 void amd_iommu_apply_erratum_63(u16 devid)
1026 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
1027 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
1030 set_dev_entry_bit(devid, DEV_ENTRY_IW);
1033 /* Writes the specific IOMMU for a device into the rlookup table */
1034 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
1036 amd_iommu_rlookup_table[devid] = iommu;
1040 * This function takes the device specific flags read from the ACPI
1041 * table and sets up the device table entry with that information
1043 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
1044 u16 devid, u32 flags, u32 ext_flags)
1046 if (flags & ACPI_DEVFLAG_INITPASS)
1047 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
1048 if (flags & ACPI_DEVFLAG_EXTINT)
1049 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
1050 if (flags & ACPI_DEVFLAG_NMI)
1051 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
1052 if (flags & ACPI_DEVFLAG_SYSMGT1)
1053 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
1054 if (flags & ACPI_DEVFLAG_SYSMGT2)
1055 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
1056 if (flags & ACPI_DEVFLAG_LINT0)
1057 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
1058 if (flags & ACPI_DEVFLAG_LINT1)
1059 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
1061 amd_iommu_apply_erratum_63(devid);
1063 set_iommu_for_device(iommu, devid);
1066 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
1068 struct devid_map *entry;
1069 struct list_head *list;
1071 if (type == IVHD_SPECIAL_IOAPIC)
1073 else if (type == IVHD_SPECIAL_HPET)
1078 list_for_each_entry(entry, list, list) {
1079 if (!(entry->id == id && entry->cmd_line))
1082 pr_info("Command-line override present for %s id %d - ignoring\n",
1083 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
1085 *devid = entry->devid;
1090 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1095 entry->devid = *devid;
1096 entry->cmd_line = cmd_line;
1098 list_add_tail(&entry->list, list);
1103 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
1106 struct acpihid_map_entry *entry;
1107 struct list_head *list = &acpihid_map;
1109 list_for_each_entry(entry, list, list) {
1110 if (strcmp(entry->hid, hid) ||
1111 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
1115 pr_info("Command-line override for hid:%s uid:%s\n",
1117 *devid = entry->devid;
1121 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1125 memcpy(entry->uid, uid, strlen(uid));
1126 memcpy(entry->hid, hid, strlen(hid));
1127 entry->devid = *devid;
1128 entry->cmd_line = cmd_line;
1129 entry->root_devid = (entry->devid & (~0x7));
1131 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n",
1132 entry->cmd_line ? "cmd" : "ivrs",
1133 entry->hid, entry->uid, entry->root_devid);
1135 list_add_tail(&entry->list, list);
1139 static int __init add_early_maps(void)
1143 for (i = 0; i < early_ioapic_map_size; ++i) {
1144 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
1145 early_ioapic_map[i].id,
1146 &early_ioapic_map[i].devid,
1147 early_ioapic_map[i].cmd_line);
1152 for (i = 0; i < early_hpet_map_size; ++i) {
1153 ret = add_special_device(IVHD_SPECIAL_HPET,
1154 early_hpet_map[i].id,
1155 &early_hpet_map[i].devid,
1156 early_hpet_map[i].cmd_line);
1161 for (i = 0; i < early_acpihid_map_size; ++i) {
1162 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
1163 early_acpihid_map[i].uid,
1164 &early_acpihid_map[i].devid,
1165 early_acpihid_map[i].cmd_line);
1174 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1175 * initializes the hardware and our data structures with it.
1177 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
1178 struct ivhd_header *h)
1181 u8 *end = p, flags = 0;
1182 u16 devid = 0, devid_start = 0, devid_to = 0;
1183 u32 dev_i, ext_flags = 0;
1185 struct ivhd_entry *e;
1190 ret = add_early_maps();
1194 amd_iommu_apply_ivrs_quirks();
1197 * First save the recommended feature enable bits from ACPI
1199 iommu->acpi_flags = h->flags;
1202 * Done. Now parse the device entries
1204 ivhd_size = get_ivhd_header_size(h);
1206 pr_err("Unsupported IVHD type %#x\n", h->type);
1216 e = (struct ivhd_entry *)p;
1220 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1222 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1223 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1225 case IVHD_DEV_SELECT:
1227 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1229 PCI_BUS_NUM(e->devid),
1235 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1237 case IVHD_DEV_SELECT_RANGE_START:
1239 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1240 "devid: %02x:%02x.%x flags: %02x\n",
1241 PCI_BUS_NUM(e->devid),
1246 devid_start = e->devid;
1251 case IVHD_DEV_ALIAS:
1253 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1254 "flags: %02x devid_to: %02x:%02x.%x\n",
1255 PCI_BUS_NUM(e->devid),
1259 PCI_BUS_NUM(e->ext >> 8),
1260 PCI_SLOT(e->ext >> 8),
1261 PCI_FUNC(e->ext >> 8));
1264 devid_to = e->ext >> 8;
1265 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1266 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1267 amd_iommu_alias_table[devid] = devid_to;
1269 case IVHD_DEV_ALIAS_RANGE:
1271 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1272 "devid: %02x:%02x.%x flags: %02x "
1273 "devid_to: %02x:%02x.%x\n",
1274 PCI_BUS_NUM(e->devid),
1278 PCI_BUS_NUM(e->ext >> 8),
1279 PCI_SLOT(e->ext >> 8),
1280 PCI_FUNC(e->ext >> 8));
1282 devid_start = e->devid;
1284 devid_to = e->ext >> 8;
1288 case IVHD_DEV_EXT_SELECT:
1290 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1291 "flags: %02x ext: %08x\n",
1292 PCI_BUS_NUM(e->devid),
1298 set_dev_entry_from_acpi(iommu, devid, e->flags,
1301 case IVHD_DEV_EXT_SELECT_RANGE:
1303 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1304 "%02x:%02x.%x flags: %02x ext: %08x\n",
1305 PCI_BUS_NUM(e->devid),
1310 devid_start = e->devid;
1315 case IVHD_DEV_RANGE_END:
1317 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1318 PCI_BUS_NUM(e->devid),
1320 PCI_FUNC(e->devid));
1323 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1325 amd_iommu_alias_table[dev_i] = devid_to;
1326 set_dev_entry_from_acpi(iommu,
1327 devid_to, flags, ext_flags);
1329 set_dev_entry_from_acpi(iommu, dev_i,
1333 case IVHD_DEV_SPECIAL: {
1339 handle = e->ext & 0xff;
1340 devid = (e->ext >> 8) & 0xffff;
1341 type = (e->ext >> 24) & 0xff;
1343 if (type == IVHD_SPECIAL_IOAPIC)
1345 else if (type == IVHD_SPECIAL_HPET)
1350 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1356 ret = add_special_device(type, handle, &devid, false);
1361 * add_special_device might update the devid in case a
1362 * command-line override is present. So call
1363 * set_dev_entry_from_acpi after add_special_device.
1365 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1369 case IVHD_DEV_ACPI_HID: {
1371 u8 hid[ACPIHID_HID_LEN];
1372 u8 uid[ACPIHID_UID_LEN];
1375 if (h->type != 0x40) {
1376 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1381 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1382 hid[ACPIHID_HID_LEN - 1] = '\0';
1385 pr_err(FW_BUG "Invalid HID.\n");
1391 case UID_NOT_PRESENT:
1394 pr_warn(FW_BUG "Invalid UID length.\n");
1397 case UID_IS_INTEGER:
1399 sprintf(uid, "%d", e->uid);
1402 case UID_IS_CHARACTER:
1404 memcpy(uid, &e->uid, e->uidl);
1405 uid[e->uidl] = '\0';
1413 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1421 ret = add_acpi_hid_device(hid, uid, &devid, false);
1426 * add_special_device might update the devid in case a
1427 * command-line override is present. So call
1428 * set_dev_entry_from_acpi after add_special_device.
1430 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1438 p += ivhd_entry_length(p);
1444 static void __init free_iommu_one(struct amd_iommu *iommu)
1446 free_cwwb_sem(iommu);
1447 free_command_buffer(iommu);
1448 free_event_buffer(iommu);
1449 free_ppr_log(iommu);
1451 iommu_unmap_mmio_space(iommu);
1454 static void __init free_iommu_all(void)
1456 struct amd_iommu *iommu, *next;
1458 for_each_iommu_safe(iommu, next) {
1459 list_del(&iommu->list);
1460 free_iommu_one(iommu);
1466 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1468 * BIOS should disable L2B micellaneous clock gating by setting
1469 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1471 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1475 if ((boot_cpu_data.x86 != 0x15) ||
1476 (boot_cpu_data.x86_model < 0x10) ||
1477 (boot_cpu_data.x86_model > 0x1f))
1480 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1481 pci_read_config_dword(iommu->dev, 0xf4, &value);
1486 /* Select NB indirect register 0x90 and enable writing */
1487 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1489 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1490 pci_info(iommu->dev, "Applying erratum 746 workaround\n");
1492 /* Clear the enable writing bit */
1493 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1497 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1499 * BIOS should enable ATS write permission check by setting
1500 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1502 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1506 if ((boot_cpu_data.x86 != 0x15) ||
1507 (boot_cpu_data.x86_model < 0x30) ||
1508 (boot_cpu_data.x86_model > 0x3f))
1511 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1512 value = iommu_read_l2(iommu, 0x47);
1517 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1518 iommu_write_l2(iommu, 0x47, value | BIT(0));
1520 pci_info(iommu->dev, "Applying ATS write check workaround\n");
1524 * This function clues the initialization function for one IOMMU
1525 * together and also allocates the command buffer and programs the
1526 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1528 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1532 raw_spin_lock_init(&iommu->lock);
1533 iommu->cmd_sem_val = 0;
1535 /* Add IOMMU to internal data structures */
1536 list_add_tail(&iommu->list, &amd_iommu_list);
1537 iommu->index = amd_iommus_present++;
1539 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1540 WARN(1, "System has more IOMMUs than supported by this driver\n");
1544 /* Index is fine - add IOMMU to the array */
1545 amd_iommus[iommu->index] = iommu;
1548 * Copy data from ACPI table entry to the iommu struct
1550 iommu->devid = h->devid;
1551 iommu->cap_ptr = h->cap_ptr;
1552 iommu->pci_seg = h->pci_seg;
1553 iommu->mmio_phys = h->mmio_phys;
1557 /* Check if IVHD EFR contains proper max banks/counters */
1558 if ((h->efr_attr != 0) &&
1559 ((h->efr_attr & (0xF << 13)) != 0) &&
1560 ((h->efr_attr & (0x3F << 17)) != 0))
1561 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1563 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1566 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.
1567 * GAM also requires GA mode. Therefore, we need to
1568 * check cmpxchg16b support before enabling it.
1570 if (!boot_cpu_has(X86_FEATURE_CX16) ||
1571 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1572 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1576 if (h->efr_reg & (1 << 9))
1577 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1579 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1582 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.
1583 * XT, GAM also requires GA mode. Therefore, we need to
1584 * check cmpxchg16b support before enabling them.
1586 if (!boot_cpu_has(X86_FEATURE_CX16) ||
1587 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) {
1588 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1592 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT))
1593 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
1595 early_iommu_features_init(iommu, h);
1602 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1603 iommu->mmio_phys_end);
1604 if (!iommu->mmio_base)
1607 if (alloc_cwwb_sem(iommu))
1610 if (alloc_command_buffer(iommu))
1613 if (alloc_event_buffer(iommu))
1616 iommu->int_enabled = false;
1618 init_translation_status(iommu);
1619 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
1620 iommu_disable(iommu);
1621 clear_translation_pre_enabled(iommu);
1622 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1625 if (amd_iommu_pre_enabled)
1626 amd_iommu_pre_enabled = translation_pre_enabled(iommu);
1628 ret = init_iommu_from_acpi(iommu, h);
1632 if (amd_iommu_irq_remap) {
1633 ret = amd_iommu_create_irq_domain(iommu);
1639 * Make sure IOMMU is not considered to translate itself. The IVRS
1640 * table tells us so, but this is a lie!
1642 amd_iommu_rlookup_table[iommu->devid] = NULL;
1648 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1649 * @ivrs: Pointer to the IVRS header
1651 * This function search through all IVDB of the maximum supported IVHD
1653 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1655 u8 *base = (u8 *)ivrs;
1656 struct ivhd_header *ivhd = (struct ivhd_header *)
1657 (base + IVRS_HEADER_LENGTH);
1658 u8 last_type = ivhd->type;
1659 u16 devid = ivhd->devid;
1661 while (((u8 *)ivhd - base < ivrs->length) &&
1662 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1663 u8 *p = (u8 *) ivhd;
1665 if (ivhd->devid == devid)
1666 last_type = ivhd->type;
1667 ivhd = (struct ivhd_header *)(p + ivhd->length);
1674 * Iterates over all IOMMU entries in the ACPI table, allocates the
1675 * IOMMU structure and initializes it with init_iommu_one()
1677 static int __init init_iommu_all(struct acpi_table_header *table)
1679 u8 *p = (u8 *)table, *end = (u8 *)table;
1680 struct ivhd_header *h;
1681 struct amd_iommu *iommu;
1684 end += table->length;
1685 p += IVRS_HEADER_LENGTH;
1688 h = (struct ivhd_header *)p;
1689 if (*p == amd_iommu_target_ivhd_type) {
1691 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1692 "seg: %d flags: %01x info %04x\n",
1693 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1694 PCI_FUNC(h->devid), h->cap_ptr,
1695 h->pci_seg, h->flags, h->info);
1696 DUMP_printk(" mmio-addr: %016llx\n",
1699 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1703 ret = init_iommu_one(iommu, h);
1715 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1718 struct pci_dev *pdev = iommu->dev;
1720 if (!iommu_feature(iommu, FEATURE_PC))
1723 amd_iommu_pc_present = true;
1725 pci_info(pdev, "IOMMU performance counters supported\n");
1727 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1728 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1729 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1734 static ssize_t amd_iommu_show_cap(struct device *dev,
1735 struct device_attribute *attr,
1738 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1739 return sprintf(buf, "%x\n", iommu->cap);
1741 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1743 static ssize_t amd_iommu_show_features(struct device *dev,
1744 struct device_attribute *attr,
1747 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1748 return sprintf(buf, "%llx\n", iommu->features);
1750 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1752 static struct attribute *amd_iommu_attrs[] = {
1754 &dev_attr_features.attr,
1758 static struct attribute_group amd_iommu_group = {
1759 .name = "amd-iommu",
1760 .attrs = amd_iommu_attrs,
1763 static const struct attribute_group *amd_iommu_groups[] = {
1769 * Note: IVHD 0x11 and 0x40 also contains exact copy
1770 * of the IOMMU Extended Feature Register [MMIO Offset 0030h].
1771 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init).
1773 static void __init late_iommu_features_init(struct amd_iommu *iommu)
1777 if (!(iommu->cap & (1 << IOMMU_CAP_EFR)))
1780 /* read extended feature bits */
1781 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES);
1783 if (!iommu->features) {
1784 iommu->features = features;
1789 * Sanity check and warn if EFR values from
1790 * IVHD and MMIO conflict.
1792 if (features != iommu->features)
1793 pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx).\n",
1794 features, iommu->features);
1797 static int __init iommu_init_pci(struct amd_iommu *iommu)
1799 int cap_ptr = iommu->cap_ptr;
1802 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
1803 iommu->devid & 0xff);
1807 /* Prevent binding other PCI device drivers to IOMMU devices */
1808 iommu->dev->match_driver = false;
1810 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1813 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1814 amd_iommu_iotlb_sup = false;
1816 late_iommu_features_init(iommu);
1818 if (iommu_feature(iommu, FEATURE_GT)) {
1823 pasmax = iommu->features & FEATURE_PASID_MASK;
1824 pasmax >>= FEATURE_PASID_SHIFT;
1825 max_pasid = (1 << (pasmax + 1)) - 1;
1827 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1829 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1831 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1832 glxval >>= FEATURE_GLXVAL_SHIFT;
1834 if (amd_iommu_max_glx_val == -1)
1835 amd_iommu_max_glx_val = glxval;
1837 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1840 if (iommu_feature(iommu, FEATURE_GT) &&
1841 iommu_feature(iommu, FEATURE_PPR)) {
1842 iommu->is_iommu_v2 = true;
1843 amd_iommu_v2_present = true;
1846 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1849 ret = iommu_init_ga(iommu);
1853 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1854 amd_iommu_np_cache = true;
1856 init_iommu_perf_ctr(iommu);
1858 if (is_rd890_iommu(iommu->dev)) {
1862 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
1866 * Some rd890 systems may not be fully reconfigured by the
1867 * BIOS, so it's necessary for us to store this information so
1868 * it can be reprogrammed on resume
1870 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1871 &iommu->stored_addr_lo);
1872 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1873 &iommu->stored_addr_hi);
1875 /* Low bit locks writes to configuration space */
1876 iommu->stored_addr_lo &= ~1;
1878 for (i = 0; i < 6; i++)
1879 for (j = 0; j < 0x12; j++)
1880 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1882 for (i = 0; i < 0x83; i++)
1883 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1886 amd_iommu_erratum_746_workaround(iommu);
1887 amd_iommu_ats_write_check_workaround(iommu);
1889 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1890 amd_iommu_groups, "ivhd%d", iommu->index);
1891 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL);
1893 return pci_enable_device(iommu->dev);
1896 static void print_iommu_info(void)
1898 static const char * const feat_str[] = {
1899 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1900 "IA", "GA", "HE", "PC"
1902 struct amd_iommu *iommu;
1904 for_each_iommu(iommu) {
1905 struct pci_dev *pdev = iommu->dev;
1908 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr);
1910 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1911 pr_info("Extended features (%#llx):", iommu->features);
1913 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1914 if (iommu_feature(iommu, (1ULL << i)))
1915 pr_cont(" %s", feat_str[i]);
1918 if (iommu->features & FEATURE_GAM_VAPIC)
1919 pr_cont(" GA_vAPIC");
1924 if (irq_remapping_enabled) {
1925 pr_info("Interrupt remapping enabled\n");
1926 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1927 pr_info("Virtual APIC enabled\n");
1928 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
1929 pr_info("X2APIC enabled\n");
1933 static int __init amd_iommu_init_pci(void)
1935 struct amd_iommu *iommu;
1938 for_each_iommu(iommu) {
1939 ret = iommu_init_pci(iommu);
1943 /* Need to setup range after PCI init */
1944 iommu_set_cwwb_range(iommu);
1948 * Order is important here to make sure any unity map requirements are
1949 * fulfilled. The unity mappings are created and written to the device
1950 * table during the amd_iommu_init_api() call.
1952 * After that we call init_device_table_dma() to make sure any
1953 * uninitialized DTE will block DMA, and in the end we flush the caches
1954 * of all IOMMUs to make sure the changes to the device table are
1957 ret = amd_iommu_init_api();
1959 init_device_table_dma();
1961 for_each_iommu(iommu)
1962 iommu_flush_all_caches(iommu);
1970 /****************************************************************************
1972 * The following functions initialize the MSI interrupts for all IOMMUs
1973 * in the system. It's a bit challenging because there could be multiple
1974 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1977 ****************************************************************************/
1979 static int iommu_setup_msi(struct amd_iommu *iommu)
1983 r = pci_enable_msi(iommu->dev);
1987 r = request_threaded_irq(iommu->dev->irq,
1988 amd_iommu_int_handler,
1989 amd_iommu_int_thread,
1994 pci_disable_msi(iommu->dev);
2005 dest_mode_logical : 1,
2012 } __attribute__ ((packed));
2015 * There isn't really any need to mask/unmask at the irqchip level because
2016 * the 64-bit INTCAPXT registers can be updated atomically without tearing
2017 * when the affinity is being updated.
2019 static void intcapxt_unmask_irq(struct irq_data *data)
2023 static void intcapxt_mask_irq(struct irq_data *data)
2027 static struct irq_chip intcapxt_controller;
2029 static int intcapxt_irqdomain_activate(struct irq_domain *domain,
2030 struct irq_data *irqd, bool reserve)
2032 struct amd_iommu *iommu = irqd->chip_data;
2033 struct irq_cfg *cfg = irqd_cfg(irqd);
2037 xt.dest_mode_logical = apic->dest_mode_logical;
2038 xt.vector = cfg->vector;
2039 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0);
2040 xt.destid_24_31 = cfg->dest_apicid >> 24;
2043 * Current IOMMU implemtation uses the same IRQ for all
2044 * 3 IOMMU interrupts.
2046 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET);
2047 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET);
2048 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET);
2052 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain,
2053 struct irq_data *irqd)
2055 intcapxt_mask_irq(irqd);
2059 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2060 unsigned int nr_irqs, void *arg)
2062 struct irq_alloc_info *info = arg;
2065 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI)
2068 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
2072 for (i = virq; i < virq + nr_irqs; i++) {
2073 struct irq_data *irqd = irq_domain_get_irq_data(domain, i);
2075 irqd->chip = &intcapxt_controller;
2076 irqd->chip_data = info->data;
2077 __irq_set_handler(i, handle_edge_irq, 0, "edge");
2083 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2084 unsigned int nr_irqs)
2086 irq_domain_free_irqs_top(domain, virq, nr_irqs);
2089 static int intcapxt_set_affinity(struct irq_data *irqd,
2090 const struct cpumask *mask, bool force)
2092 struct irq_data *parent = irqd->parent_data;
2095 ret = parent->chip->irq_set_affinity(parent, mask, force);
2096 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
2099 return intcapxt_irqdomain_activate(irqd->domain, irqd, false);
2102 static struct irq_chip intcapxt_controller = {
2103 .name = "IOMMU-MSI",
2104 .irq_unmask = intcapxt_unmask_irq,
2105 .irq_mask = intcapxt_mask_irq,
2106 .irq_ack = irq_chip_ack_parent,
2107 .irq_retrigger = irq_chip_retrigger_hierarchy,
2108 .irq_set_affinity = intcapxt_set_affinity,
2109 .flags = IRQCHIP_SKIP_SET_WAKE,
2112 static const struct irq_domain_ops intcapxt_domain_ops = {
2113 .alloc = intcapxt_irqdomain_alloc,
2114 .free = intcapxt_irqdomain_free,
2115 .activate = intcapxt_irqdomain_activate,
2116 .deactivate = intcapxt_irqdomain_deactivate,
2120 static struct irq_domain *iommu_irqdomain;
2122 static struct irq_domain *iommu_get_irqdomain(void)
2124 struct fwnode_handle *fn;
2126 /* No need for locking here (yet) as the init is single-threaded */
2127 if (iommu_irqdomain)
2128 return iommu_irqdomain;
2130 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI");
2134 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0,
2135 fn, &intcapxt_domain_ops,
2137 if (!iommu_irqdomain)
2138 irq_domain_free_fwnode(fn);
2140 return iommu_irqdomain;
2143 static int iommu_setup_intcapxt(struct amd_iommu *iommu)
2145 struct irq_domain *domain;
2146 struct irq_alloc_info info;
2149 domain = iommu_get_irqdomain();
2153 init_irq_alloc_info(&info, NULL);
2154 info.type = X86_IRQ_ALLOC_TYPE_AMDVI;
2157 irq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
2159 irq_domain_remove(domain);
2163 ret = request_threaded_irq(irq, amd_iommu_int_handler,
2164 amd_iommu_int_thread, 0, "AMD-Vi", iommu);
2166 irq_domain_free_irqs(irq, 1);
2167 irq_domain_remove(domain);
2171 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN);
2175 static int iommu_init_irq(struct amd_iommu *iommu)
2179 if (iommu->int_enabled)
2182 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
2183 ret = iommu_setup_intcapxt(iommu);
2184 else if (iommu->dev->msi_cap)
2185 ret = iommu_setup_msi(iommu);
2192 iommu->int_enabled = true;
2194 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
2196 if (iommu->ppr_log != NULL)
2197 iommu_feature_enable(iommu, CONTROL_PPRINT_EN);
2199 iommu_ga_log_enable(iommu);
2204 /****************************************************************************
2206 * The next functions belong to the third pass of parsing the ACPI
2207 * table. In this last pass the memory mapping requirements are
2208 * gathered (like exclusion and unity mapping ranges).
2210 ****************************************************************************/
2212 static void __init free_unity_maps(void)
2214 struct unity_map_entry *entry, *next;
2216 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
2217 list_del(&entry->list);
2222 /* called for unity map ACPI definition */
2223 static int __init init_unity_map_range(struct ivmd_header *m)
2225 struct unity_map_entry *e = NULL;
2228 e = kzalloc(sizeof(*e), GFP_KERNEL);
2236 case ACPI_IVMD_TYPE:
2237 s = "IVMD_TYPEi\t\t\t";
2238 e->devid_start = e->devid_end = m->devid;
2240 case ACPI_IVMD_TYPE_ALL:
2241 s = "IVMD_TYPE_ALL\t\t";
2243 e->devid_end = amd_iommu_last_bdf;
2245 case ACPI_IVMD_TYPE_RANGE:
2246 s = "IVMD_TYPE_RANGE\t\t";
2247 e->devid_start = m->devid;
2248 e->devid_end = m->aux;
2251 e->address_start = PAGE_ALIGN(m->range_start);
2252 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
2253 e->prot = m->flags >> 1;
2256 * Treat per-device exclusion ranges as r/w unity-mapped regions
2257 * since some buggy BIOSes might lead to the overwritten exclusion
2258 * range (exclusion_start and exclusion_length members). This
2259 * happens when there are multiple exclusion ranges (IVMD entries)
2260 * defined in ACPI table.
2262 if (m->flags & IVMD_FLAG_EXCL_RANGE)
2263 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1;
2265 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2266 " range_start: %016llx range_end: %016llx flags: %x\n", s,
2267 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
2268 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
2269 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
2270 e->address_start, e->address_end, m->flags);
2272 list_add_tail(&e->list, &amd_iommu_unity_map);
2277 /* iterates over all memory definitions we find in the ACPI table */
2278 static int __init init_memory_definitions(struct acpi_table_header *table)
2280 u8 *p = (u8 *)table, *end = (u8 *)table;
2281 struct ivmd_header *m;
2283 end += table->length;
2284 p += IVRS_HEADER_LENGTH;
2287 m = (struct ivmd_header *)p;
2288 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE))
2289 init_unity_map_range(m);
2298 * Init the device table to not allow DMA access for devices
2300 static void init_device_table_dma(void)
2304 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2305 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2306 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2310 static void __init uninit_device_table_dma(void)
2314 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2315 amd_iommu_dev_table[devid].data[0] = 0ULL;
2316 amd_iommu_dev_table[devid].data[1] = 0ULL;
2320 static void init_device_table(void)
2324 if (!amd_iommu_irq_remap)
2327 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2328 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
2331 static void iommu_init_flags(struct amd_iommu *iommu)
2333 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
2334 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
2335 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
2337 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
2338 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
2339 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
2341 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
2342 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
2343 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
2345 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
2346 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
2347 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
2350 * make IOMMU memory accesses cache coherent
2352 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
2354 /* Set IOTLB invalidation timeout to 1s */
2355 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
2358 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
2361 u32 ioc_feature_control;
2362 struct pci_dev *pdev = iommu->root_pdev;
2364 /* RD890 BIOSes may not have completely reconfigured the iommu */
2365 if (!is_rd890_iommu(iommu->dev) || !pdev)
2369 * First, we need to ensure that the iommu is enabled. This is
2370 * controlled by a register in the northbridge
2373 /* Select Northbridge indirect register 0x75 and enable writing */
2374 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
2375 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
2377 /* Enable the iommu */
2378 if (!(ioc_feature_control & 0x1))
2379 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
2381 /* Restore the iommu BAR */
2382 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2383 iommu->stored_addr_lo);
2384 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
2385 iommu->stored_addr_hi);
2387 /* Restore the l1 indirect regs for each of the 6 l1s */
2388 for (i = 0; i < 6; i++)
2389 for (j = 0; j < 0x12; j++)
2390 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
2392 /* Restore the l2 indirect regs */
2393 for (i = 0; i < 0x83; i++)
2394 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2396 /* Lock PCI setup registers */
2397 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2398 iommu->stored_addr_lo | 1);
2401 static void iommu_enable_ga(struct amd_iommu *iommu)
2403 #ifdef CONFIG_IRQ_REMAP
2404 switch (amd_iommu_guest_ir) {
2405 case AMD_IOMMU_GUEST_IR_VAPIC:
2406 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2408 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2409 iommu_feature_enable(iommu, CONTROL_GA_EN);
2410 iommu->irte_ops = &irte_128_ops;
2413 iommu->irte_ops = &irte_32_ops;
2419 static void early_enable_iommu(struct amd_iommu *iommu)
2421 iommu_disable(iommu);
2422 iommu_init_flags(iommu);
2423 iommu_set_device_table(iommu);
2424 iommu_enable_command_buffer(iommu);
2425 iommu_enable_event_buffer(iommu);
2426 iommu_set_exclusion_range(iommu);
2427 iommu_enable_ga(iommu);
2428 iommu_enable_xt(iommu);
2429 iommu_enable(iommu);
2430 iommu_flush_all_caches(iommu);
2434 * This function finally enables all IOMMUs found in the system after
2435 * they have been initialized.
2437 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2438 * the old content of device table entries. Not this case or copy failed,
2439 * just continue as normal kernel does.
2441 static void early_enable_iommus(void)
2443 struct amd_iommu *iommu;
2446 if (!copy_device_table()) {
2448 * If come here because of failure in copying device table from old
2449 * kernel with all IOMMUs enabled, print error message and try to
2450 * free allocated old_dev_tbl_cpy.
2452 if (amd_iommu_pre_enabled)
2453 pr_err("Failed to copy DEV table from previous kernel.\n");
2454 if (old_dev_tbl_cpy != NULL)
2455 free_pages((unsigned long)old_dev_tbl_cpy,
2456 get_order(dev_table_size));
2458 for_each_iommu(iommu) {
2459 clear_translation_pre_enabled(iommu);
2460 early_enable_iommu(iommu);
2463 pr_info("Copied DEV table from previous kernel.\n");
2464 free_pages((unsigned long)amd_iommu_dev_table,
2465 get_order(dev_table_size));
2466 amd_iommu_dev_table = old_dev_tbl_cpy;
2467 for_each_iommu(iommu) {
2468 iommu_disable_command_buffer(iommu);
2469 iommu_disable_event_buffer(iommu);
2470 iommu_enable_command_buffer(iommu);
2471 iommu_enable_event_buffer(iommu);
2472 iommu_enable_ga(iommu);
2473 iommu_enable_xt(iommu);
2474 iommu_set_device_table(iommu);
2475 iommu_flush_all_caches(iommu);
2479 #ifdef CONFIG_IRQ_REMAP
2480 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2481 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2485 static void enable_iommus_v2(void)
2487 struct amd_iommu *iommu;
2489 for_each_iommu(iommu) {
2490 iommu_enable_ppr_log(iommu);
2491 iommu_enable_gt(iommu);
2495 static void enable_iommus(void)
2497 early_enable_iommus();
2502 static void disable_iommus(void)
2504 struct amd_iommu *iommu;
2506 for_each_iommu(iommu)
2507 iommu_disable(iommu);
2509 #ifdef CONFIG_IRQ_REMAP
2510 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2511 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2516 * Suspend/Resume support
2517 * disable suspend until real resume implemented
2520 static void amd_iommu_resume(void)
2522 struct amd_iommu *iommu;
2524 for_each_iommu(iommu)
2525 iommu_apply_resume_quirks(iommu);
2527 /* re-load the hardware */
2530 amd_iommu_enable_interrupts();
2533 static int amd_iommu_suspend(void)
2535 /* disable IOMMUs to go out of the way for BIOS */
2541 static struct syscore_ops amd_iommu_syscore_ops = {
2542 .suspend = amd_iommu_suspend,
2543 .resume = amd_iommu_resume,
2546 static void __init free_iommu_resources(void)
2548 kmemleak_free(irq_lookup_table);
2549 free_pages((unsigned long)irq_lookup_table,
2550 get_order(rlookup_table_size));
2551 irq_lookup_table = NULL;
2553 kmem_cache_destroy(amd_iommu_irq_cache);
2554 amd_iommu_irq_cache = NULL;
2556 free_pages((unsigned long)amd_iommu_rlookup_table,
2557 get_order(rlookup_table_size));
2558 amd_iommu_rlookup_table = NULL;
2560 free_pages((unsigned long)amd_iommu_alias_table,
2561 get_order(alias_table_size));
2562 amd_iommu_alias_table = NULL;
2564 free_pages((unsigned long)amd_iommu_dev_table,
2565 get_order(dev_table_size));
2566 amd_iommu_dev_table = NULL;
2571 /* SB IOAPIC is always on this device in AMD systems */
2572 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2574 static bool __init check_ioapic_information(void)
2576 const char *fw_bug = FW_BUG;
2577 bool ret, has_sb_ioapic;
2580 has_sb_ioapic = false;
2584 * If we have map overrides on the kernel command line the
2585 * messages in this function might not describe firmware bugs
2586 * anymore - so be careful
2591 for (idx = 0; idx < nr_ioapics; idx++) {
2592 int devid, id = mpc_ioapic_id(idx);
2594 devid = get_ioapic_devid(id);
2596 pr_err("%s: IOAPIC[%d] not in IVRS table\n",
2599 } else if (devid == IOAPIC_SB_DEVID) {
2600 has_sb_ioapic = true;
2605 if (!has_sb_ioapic) {
2607 * We expect the SB IOAPIC to be listed in the IVRS
2608 * table. The system timer is connected to the SB IOAPIC
2609 * and if we don't have it in the list the system will
2610 * panic at boot time. This situation usually happens
2611 * when the BIOS is buggy and provides us the wrong
2612 * device id for the IOAPIC in the system.
2614 pr_err("%s: No southbridge IOAPIC found\n", fw_bug);
2618 pr_err("Disabling interrupt remapping\n");
2623 static void __init free_dma_resources(void)
2625 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2626 get_order(MAX_DOMAIN_ID/8));
2627 amd_iommu_pd_alloc_bitmap = NULL;
2632 static void __init ivinfo_init(void *ivrs)
2634 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET));
2638 * This is the hardware init function for AMD IOMMU in the system.
2639 * This function is called either from amd_iommu_init or from the interrupt
2640 * remapping setup code.
2642 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2645 * 1 pass) Discover the most comprehensive IVHD type to use.
2647 * 2 pass) Find the highest PCI device id the driver has to handle.
2648 * Upon this information the size of the data structures is
2649 * determined that needs to be allocated.
2651 * 3 pass) Initialize the data structures just allocated with the
2652 * information in the ACPI table about available AMD IOMMUs
2653 * in the system. It also maps the PCI devices in the
2654 * system to specific IOMMUs
2656 * 4 pass) After the basic data structures are allocated and
2657 * initialized we update them with information about memory
2658 * remapping requirements parsed out of the ACPI table in
2661 * After everything is set up the IOMMUs are enabled and the necessary
2662 * hotplug and suspend notifiers are registered.
2664 static int __init early_amd_iommu_init(void)
2666 struct acpi_table_header *ivrs_base;
2667 int i, remap_cache_sz, ret;
2670 if (!amd_iommu_detected)
2673 status = acpi_get_table("IVRS", 0, &ivrs_base);
2674 if (status == AE_NOT_FOUND)
2676 else if (ACPI_FAILURE(status)) {
2677 const char *err = acpi_format_exception(status);
2678 pr_err("IVRS table error: %s\n", err);
2683 * Validate checksum here so we don't need to do it when
2684 * we actually parse the table
2686 ret = check_ivrs_checksum(ivrs_base);
2690 ivinfo_init(ivrs_base);
2692 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2693 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2696 * First parse ACPI tables to find the largest Bus/Dev/Func
2697 * we need to handle. Upon this information the shared data
2698 * structures for the IOMMUs in the system will be allocated
2700 ret = find_last_devid_acpi(ivrs_base);
2704 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2705 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2706 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2708 /* Device table - directly used by all IOMMUs */
2710 amd_iommu_dev_table = (void *)__get_free_pages(
2711 GFP_KERNEL | __GFP_ZERO | GFP_DMA32,
2712 get_order(dev_table_size));
2713 if (amd_iommu_dev_table == NULL)
2717 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2718 * IOMMU see for that device
2720 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2721 get_order(alias_table_size));
2722 if (amd_iommu_alias_table == NULL)
2725 /* IOMMU rlookup table - find the IOMMU for a specific device */
2726 amd_iommu_rlookup_table = (void *)__get_free_pages(
2727 GFP_KERNEL | __GFP_ZERO,
2728 get_order(rlookup_table_size));
2729 if (amd_iommu_rlookup_table == NULL)
2732 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2733 GFP_KERNEL | __GFP_ZERO,
2734 get_order(MAX_DOMAIN_ID/8));
2735 if (amd_iommu_pd_alloc_bitmap == NULL)
2739 * let all alias entries point to itself
2741 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2742 amd_iommu_alias_table[i] = i;
2745 * never allocate domain 0 because its used as the non-allocated and
2746 * error value placeholder
2748 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2751 * now the data structures are allocated and basically initialized
2752 * start the real acpi table scan
2754 ret = init_iommu_all(ivrs_base);
2758 /* Disable any previously enabled IOMMUs */
2759 if (!is_kdump_kernel() || amd_iommu_disabled)
2762 if (amd_iommu_irq_remap)
2763 amd_iommu_irq_remap = check_ioapic_information();
2765 if (amd_iommu_irq_remap) {
2767 * Interrupt remapping enabled, create kmem_cache for the
2771 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2772 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2774 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2775 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2777 DTE_INTTAB_ALIGNMENT,
2779 if (!amd_iommu_irq_cache)
2782 irq_lookup_table = (void *)__get_free_pages(
2783 GFP_KERNEL | __GFP_ZERO,
2784 get_order(rlookup_table_size));
2785 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2787 if (!irq_lookup_table)
2791 ret = init_memory_definitions(ivrs_base);
2795 /* init the device table */
2796 init_device_table();
2799 /* Don't leak any ACPI memory */
2800 acpi_put_table(ivrs_base);
2805 static int amd_iommu_enable_interrupts(void)
2807 struct amd_iommu *iommu;
2810 for_each_iommu(iommu) {
2811 ret = iommu_init_irq(iommu);
2820 static bool __init detect_ivrs(void)
2822 struct acpi_table_header *ivrs_base;
2826 status = acpi_get_table("IVRS", 0, &ivrs_base);
2827 if (status == AE_NOT_FOUND)
2829 else if (ACPI_FAILURE(status)) {
2830 const char *err = acpi_format_exception(status);
2831 pr_err("IVRS table error: %s\n", err);
2835 acpi_put_table(ivrs_base);
2837 if (amd_iommu_force_enable)
2840 /* Don't use IOMMU if there is Stoney Ridge graphics */
2841 for (i = 0; i < 32; i++) {
2844 pci_id = read_pci_config(0, i, 0, 0);
2845 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) {
2846 pr_info("Disable IOMMU on Stoney Ridge\n");
2852 /* Make sure ACS will be enabled during PCI probe */
2858 /****************************************************************************
2860 * AMD IOMMU Initialization State Machine
2862 ****************************************************************************/
2864 static int __init state_next(void)
2868 switch (init_state) {
2869 case IOMMU_START_STATE:
2870 if (!detect_ivrs()) {
2871 init_state = IOMMU_NOT_FOUND;
2874 init_state = IOMMU_IVRS_DETECTED;
2877 case IOMMU_IVRS_DETECTED:
2878 if (amd_iommu_disabled) {
2879 init_state = IOMMU_CMDLINE_DISABLED;
2882 ret = early_amd_iommu_init();
2883 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2886 case IOMMU_ACPI_FINISHED:
2887 early_enable_iommus();
2888 x86_platform.iommu_shutdown = disable_iommus;
2889 init_state = IOMMU_ENABLED;
2892 register_syscore_ops(&amd_iommu_syscore_ops);
2893 ret = amd_iommu_init_pci();
2894 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2897 case IOMMU_PCI_INIT:
2898 ret = amd_iommu_enable_interrupts();
2899 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2901 case IOMMU_INTERRUPTS_EN:
2902 init_state = IOMMU_INITIALIZED;
2904 case IOMMU_INITIALIZED:
2907 case IOMMU_NOT_FOUND:
2908 case IOMMU_INIT_ERROR:
2909 case IOMMU_CMDLINE_DISABLED:
2910 /* Error states => do nothing */
2919 free_dma_resources();
2920 if (!irq_remapping_enabled) {
2922 free_iommu_resources();
2924 struct amd_iommu *iommu;
2926 uninit_device_table_dma();
2927 for_each_iommu(iommu)
2928 iommu_flush_all_caches(iommu);
2934 static int __init iommu_go_to_state(enum iommu_init_state state)
2938 while (init_state != state) {
2939 if (init_state == IOMMU_NOT_FOUND ||
2940 init_state == IOMMU_INIT_ERROR ||
2941 init_state == IOMMU_CMDLINE_DISABLED)
2949 #ifdef CONFIG_IRQ_REMAP
2950 int __init amd_iommu_prepare(void)
2954 amd_iommu_irq_remap = true;
2956 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2958 amd_iommu_irq_remap = false;
2962 return amd_iommu_irq_remap ? 0 : -ENODEV;
2965 int __init amd_iommu_enable(void)
2969 ret = iommu_go_to_state(IOMMU_ENABLED);
2973 irq_remapping_enabled = 1;
2974 return amd_iommu_xt_mode;
2977 void amd_iommu_disable(void)
2979 amd_iommu_suspend();
2982 int amd_iommu_reenable(int mode)
2989 int __init amd_iommu_enable_faulting(void)
2991 /* We enable MSI later when PCI is initialized */
2997 * This is the core init function for AMD IOMMU hardware in the system.
2998 * This function is called from the generic x86 DMA layer initialization
3001 static int __init amd_iommu_init(void)
3003 struct amd_iommu *iommu;
3006 ret = iommu_go_to_state(IOMMU_INITIALIZED);
3007 #ifdef CONFIG_GART_IOMMU
3008 if (ret && list_empty(&amd_iommu_list)) {
3010 * We failed to initialize the AMD IOMMU - try fallback
3011 * to GART if possible.
3017 for_each_iommu(iommu)
3018 amd_iommu_debugfs_setup(iommu);
3023 static bool amd_iommu_sme_check(void)
3025 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
3028 /* For Fam17h, a specific level of support is required */
3029 if (boot_cpu_data.microcode >= 0x08001205)
3032 if ((boot_cpu_data.microcode >= 0x08001126) &&
3033 (boot_cpu_data.microcode <= 0x080011ff))
3036 pr_notice("IOMMU not currently supported when SME is active\n");
3041 /****************************************************************************
3043 * Early detect code. This code runs at IOMMU detection time in the DMA
3044 * layer. It just looks if there is an IVRS ACPI table to detect AMD
3047 ****************************************************************************/
3048 int __init amd_iommu_detect(void)
3052 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
3055 if (!amd_iommu_sme_check())
3058 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
3062 amd_iommu_detected = true;
3064 x86_init.iommu.iommu_init = amd_iommu_init;
3069 /****************************************************************************
3071 * Parsing functions for the AMD IOMMU specific kernel command line
3074 ****************************************************************************/
3076 static int __init parse_amd_iommu_dump(char *str)
3078 amd_iommu_dump = true;
3083 static int __init parse_amd_iommu_intr(char *str)
3085 for (; *str; ++str) {
3086 if (strncmp(str, "legacy", 6) == 0) {
3087 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
3090 if (strncmp(str, "vapic", 5) == 0) {
3091 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
3098 static int __init parse_amd_iommu_options(char *str)
3100 for (; *str; ++str) {
3101 if (strncmp(str, "fullflush", 9) == 0)
3102 amd_iommu_unmap_flush = true;
3103 if (strncmp(str, "force_enable", 12) == 0)
3104 amd_iommu_force_enable = true;
3105 if (strncmp(str, "off", 3) == 0)
3106 amd_iommu_disabled = true;
3107 if (strncmp(str, "force_isolation", 15) == 0)
3108 amd_iommu_force_isolation = true;
3114 static int __init parse_ivrs_ioapic(char *str)
3116 unsigned int bus, dev, fn;
3120 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
3123 pr_err("Invalid command line: ivrs_ioapic%s\n", str);
3127 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
3128 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
3133 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
3135 cmdline_maps = true;
3136 i = early_ioapic_map_size++;
3137 early_ioapic_map[i].id = id;
3138 early_ioapic_map[i].devid = devid;
3139 early_ioapic_map[i].cmd_line = true;
3144 static int __init parse_ivrs_hpet(char *str)
3146 unsigned int bus, dev, fn;
3150 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
3153 pr_err("Invalid command line: ivrs_hpet%s\n", str);
3157 if (early_hpet_map_size == EARLY_MAP_SIZE) {
3158 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n",
3163 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
3165 cmdline_maps = true;
3166 i = early_hpet_map_size++;
3167 early_hpet_map[i].id = id;
3168 early_hpet_map[i].devid = devid;
3169 early_hpet_map[i].cmd_line = true;
3174 static int __init parse_ivrs_acpihid(char *str)
3177 char *hid, *uid, *p;
3178 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
3181 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
3183 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str);
3188 hid = strsep(&p, ":");
3191 if (!hid || !(*hid) || !uid) {
3192 pr_err("Invalid command line: hid or uid\n");
3196 i = early_acpihid_map_size++;
3197 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
3198 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
3199 early_acpihid_map[i].devid =
3200 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
3201 early_acpihid_map[i].cmd_line = true;
3206 __setup("amd_iommu_dump", parse_amd_iommu_dump);
3207 __setup("amd_iommu=", parse_amd_iommu_options);
3208 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
3209 __setup("ivrs_ioapic", parse_ivrs_ioapic);
3210 __setup("ivrs_hpet", parse_ivrs_hpet);
3211 __setup("ivrs_acpihid", parse_ivrs_acpihid);
3213 IOMMU_INIT_FINISH(amd_iommu_detect,
3214 gart_iommu_hole_init,
3218 bool amd_iommu_v2_supported(void)
3220 return amd_iommu_v2_present;
3222 EXPORT_SYMBOL(amd_iommu_v2_supported);
3224 struct amd_iommu *get_amd_iommu(unsigned int idx)
3227 struct amd_iommu *iommu;
3229 for_each_iommu(iommu)
3235 /****************************************************************************
3237 * IOMMU EFR Performance Counter support functionality. This code allows
3238 * access to the IOMMU PC functionality.
3240 ****************************************************************************/
3242 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
3244 struct amd_iommu *iommu = get_amd_iommu(idx);
3247 return iommu->max_banks;
3251 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
3253 bool amd_iommu_pc_supported(void)
3255 return amd_iommu_pc_present;
3257 EXPORT_SYMBOL(amd_iommu_pc_supported);
3259 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
3261 struct amd_iommu *iommu = get_amd_iommu(idx);
3264 return iommu->max_counters;
3268 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
3270 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
3271 u8 fxn, u64 *value, bool is_write)
3276 /* Make sure the IOMMU PC resource is available */
3277 if (!amd_iommu_pc_present)
3280 /* Check for valid iommu and pc register indexing */
3281 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
3284 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3286 /* Limit the offset to the hw defined mmio region aperture */
3287 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
3288 (iommu->max_counters << 8) | 0x28);
3289 if ((offset < MMIO_CNTR_REG_OFFSET) ||
3290 (offset > max_offset_lim))
3294 u64 val = *value & GENMASK_ULL(47, 0);
3296 writel((u32)val, iommu->mmio_base + offset);
3297 writel((val >> 32), iommu->mmio_base + offset + 4);
3299 *value = readl(iommu->mmio_base + offset + 4);
3301 *value |= readl(iommu->mmio_base + offset);
3302 *value &= GENMASK_ULL(47, 0);
3308 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3313 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3316 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3321 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);