1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
9 #define _ASM_X86_AMD_IOMMU_TYPES_H
11 #include <linux/types.h>
12 #include <linux/mutex.h>
13 #include <linux/msi.h>
14 #include <linux/list.h>
15 #include <linux/spinlock.h>
16 #include <linux/pci.h>
17 #include <linux/irqreturn.h>
20 * Maximum number of IOMMUs supported
25 * some size calculation constants
27 #define DEV_TABLE_ENTRY_SIZE 32
28 #define ALIAS_TABLE_ENTRY_SIZE 2
29 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
31 /* Capability offsets used by the driver */
32 #define MMIO_CAP_HDR_OFFSET 0x00
33 #define MMIO_RANGE_OFFSET 0x0c
34 #define MMIO_MISC_OFFSET 0x10
36 /* Masks, shifts and macros to parse the device range capability */
37 #define MMIO_RANGE_LD_MASK 0xff000000
38 #define MMIO_RANGE_FD_MASK 0x00ff0000
39 #define MMIO_RANGE_BUS_MASK 0x0000ff00
40 #define MMIO_RANGE_LD_SHIFT 24
41 #define MMIO_RANGE_FD_SHIFT 16
42 #define MMIO_RANGE_BUS_SHIFT 8
43 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
44 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
45 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
46 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
48 /* Flag masks for the AMD IOMMU exclusion range */
49 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
50 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
52 /* Used offsets into the MMIO space */
53 #define MMIO_DEV_TABLE_OFFSET 0x0000
54 #define MMIO_CMD_BUF_OFFSET 0x0008
55 #define MMIO_EVT_BUF_OFFSET 0x0010
56 #define MMIO_CONTROL_OFFSET 0x0018
57 #define MMIO_EXCL_BASE_OFFSET 0x0020
58 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
59 #define MMIO_EXT_FEATURES 0x0030
60 #define MMIO_PPR_LOG_OFFSET 0x0038
61 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
62 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
63 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C
64 #define MMIO_MSI_ADDR_HI_OFFSET 0x0160
65 #define MMIO_MSI_DATA_OFFSET 0x0164
66 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170
67 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178
68 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180
69 #define MMIO_CMD_HEAD_OFFSET 0x2000
70 #define MMIO_CMD_TAIL_OFFSET 0x2008
71 #define MMIO_EVT_HEAD_OFFSET 0x2010
72 #define MMIO_EVT_TAIL_OFFSET 0x2018
73 #define MMIO_STATUS_OFFSET 0x2020
74 #define MMIO_PPR_HEAD_OFFSET 0x2030
75 #define MMIO_PPR_TAIL_OFFSET 0x2038
76 #define MMIO_GA_HEAD_OFFSET 0x2040
77 #define MMIO_GA_TAIL_OFFSET 0x2048
78 #define MMIO_CNTR_CONF_OFFSET 0x4000
79 #define MMIO_CNTR_REG_OFFSET 0x40000
80 #define MMIO_REG_END_OFFSET 0x80000
84 /* Extended Feature Bits */
85 #define FEATURE_PREFETCH (1ULL<<0)
86 #define FEATURE_PPR (1ULL<<1)
87 #define FEATURE_X2APIC (1ULL<<2)
88 #define FEATURE_NX (1ULL<<3)
89 #define FEATURE_GT (1ULL<<4)
90 #define FEATURE_IA (1ULL<<6)
91 #define FEATURE_GA (1ULL<<7)
92 #define FEATURE_HE (1ULL<<8)
93 #define FEATURE_PC (1ULL<<9)
94 #define FEATURE_GAM_VAPIC (1ULL<<21)
95 #define FEATURE_EPHSUP (1ULL<<50)
96 #define FEATURE_SNP (1ULL<<63)
98 #define FEATURE_PASID_SHIFT 32
99 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
101 #define FEATURE_GLXVAL_SHIFT 14
102 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
105 * The current driver only support 16-bit PASID.
106 * Currently, hardware only implement upto 16-bit PASID
107 * even though the spec says it could have upto 20 bits.
109 #define PASID_MASK 0x0000ffff
111 /* MMIO status bits */
112 #define MMIO_STATUS_EVT_INT_MASK (1 << 1)
113 #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
114 #define MMIO_STATUS_PPR_INT_MASK (1 << 6)
115 #define MMIO_STATUS_GALOG_RUN_MASK (1 << 8)
116 #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
117 #define MMIO_STATUS_GALOG_INT_MASK (1 << 10)
119 /* event logging constants */
120 #define EVENT_ENTRY_SIZE 0x10
121 #define EVENT_TYPE_SHIFT 28
122 #define EVENT_TYPE_MASK 0xf
123 #define EVENT_TYPE_ILL_DEV 0x1
124 #define EVENT_TYPE_IO_FAULT 0x2
125 #define EVENT_TYPE_DEV_TAB_ERR 0x3
126 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
127 #define EVENT_TYPE_ILL_CMD 0x5
128 #define EVENT_TYPE_CMD_HARD_ERR 0x6
129 #define EVENT_TYPE_IOTLB_INV_TO 0x7
130 #define EVENT_TYPE_INV_DEV_REQ 0x8
131 #define EVENT_TYPE_INV_PPR_REQ 0x9
132 #define EVENT_TYPE_RMP_FAULT 0xd
133 #define EVENT_TYPE_RMP_HW_ERR 0xe
134 #define EVENT_DEVID_MASK 0xffff
135 #define EVENT_DEVID_SHIFT 0
136 #define EVENT_DOMID_MASK_LO 0xffff
137 #define EVENT_DOMID_MASK_HI 0xf0000
138 #define EVENT_FLAGS_MASK 0xfff
139 #define EVENT_FLAGS_SHIFT 0x10
141 /* feature control bits */
142 #define CONTROL_IOMMU_EN 0x00ULL
143 #define CONTROL_HT_TUN_EN 0x01ULL
144 #define CONTROL_EVT_LOG_EN 0x02ULL
145 #define CONTROL_EVT_INT_EN 0x03ULL
146 #define CONTROL_COMWAIT_EN 0x04ULL
147 #define CONTROL_INV_TIMEOUT 0x05ULL
148 #define CONTROL_PASSPW_EN 0x08ULL
149 #define CONTROL_RESPASSPW_EN 0x09ULL
150 #define CONTROL_COHERENT_EN 0x0aULL
151 #define CONTROL_ISOC_EN 0x0bULL
152 #define CONTROL_CMDBUF_EN 0x0cULL
153 #define CONTROL_PPRLOG_EN 0x0dULL
154 #define CONTROL_PPRINT_EN 0x0eULL
155 #define CONTROL_PPR_EN 0x0fULL
156 #define CONTROL_GT_EN 0x10ULL
157 #define CONTROL_GA_EN 0x11ULL
158 #define CONTROL_GAM_EN 0x19ULL
159 #define CONTROL_GALOG_EN 0x1CULL
160 #define CONTROL_GAINT_EN 0x1DULL
161 #define CONTROL_XT_EN 0x32ULL
162 #define CONTROL_INTCAPXT_EN 0x33ULL
164 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
165 #define CTRL_INV_TO_NONE 0
166 #define CTRL_INV_TO_1MS 1
167 #define CTRL_INV_TO_10MS 2
168 #define CTRL_INV_TO_100MS 3
169 #define CTRL_INV_TO_1S 4
170 #define CTRL_INV_TO_10S 5
171 #define CTRL_INV_TO_100S 6
173 /* command specific defines */
174 #define CMD_COMPL_WAIT 0x01
175 #define CMD_INV_DEV_ENTRY 0x02
176 #define CMD_INV_IOMMU_PAGES 0x03
177 #define CMD_INV_IOTLB_PAGES 0x04
178 #define CMD_INV_IRT 0x05
179 #define CMD_COMPLETE_PPR 0x07
180 #define CMD_INV_ALL 0x08
182 #define CMD_COMPL_WAIT_STORE_MASK 0x01
183 #define CMD_COMPL_WAIT_INT_MASK 0x02
184 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
185 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
186 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
188 #define PPR_STATUS_MASK 0xf
189 #define PPR_STATUS_SHIFT 12
191 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
193 /* macros and definitions for device table entries */
194 #define DEV_ENTRY_VALID 0x00
195 #define DEV_ENTRY_TRANSLATION 0x01
196 #define DEV_ENTRY_PPR 0x34
197 #define DEV_ENTRY_IR 0x3d
198 #define DEV_ENTRY_IW 0x3e
199 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
200 #define DEV_ENTRY_EX 0x67
201 #define DEV_ENTRY_SYSMGT1 0x68
202 #define DEV_ENTRY_SYSMGT2 0x69
203 #define DEV_ENTRY_IRQ_TBL_EN 0x80
204 #define DEV_ENTRY_INIT_PASS 0xb8
205 #define DEV_ENTRY_EINT_PASS 0xb9
206 #define DEV_ENTRY_NMI_PASS 0xba
207 #define DEV_ENTRY_LINT0_PASS 0xbe
208 #define DEV_ENTRY_LINT1_PASS 0xbf
209 #define DEV_ENTRY_MODE_MASK 0x07
210 #define DEV_ENTRY_MODE_SHIFT 0x09
212 #define MAX_DEV_TABLE_ENTRIES 0xffff
214 /* constants to configure the command buffer */
215 #define CMD_BUFFER_SIZE 8192
216 #define CMD_BUFFER_UNINITIALIZED 1
217 #define CMD_BUFFER_ENTRIES 512
218 #define MMIO_CMD_SIZE_SHIFT 56
219 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
221 /* constants for event buffer handling */
222 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
223 #define EVT_LEN_MASK (0x9ULL << 56)
225 /* Constants for PPR Log handling */
226 #define PPR_LOG_ENTRIES 512
227 #define PPR_LOG_SIZE_SHIFT 56
228 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
229 #define PPR_ENTRY_SIZE 16
230 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
232 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
233 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
234 #define PPR_DEVID(x) ((x) & 0xffffULL)
235 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
236 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
237 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
238 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
240 #define PPR_REQ_FAULT 0x01
242 /* Constants for GA Log handling */
243 #define GA_LOG_ENTRIES 512
244 #define GA_LOG_SIZE_SHIFT 56
245 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
246 #define GA_ENTRY_SIZE 8
247 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
249 #define GA_TAG(x) (u32)(x & 0xffffffffULL)
250 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
251 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
253 #define GA_GUEST_NR 0x1
255 /* Bit value definition for dte irq remapping fields*/
256 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
257 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
258 #define DTE_IRQ_TABLE_LEN_MASK (0xfULL << 1)
259 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
260 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
261 #define DTE_IRQ_REMAP_ENABLE 1ULL
263 #define PAGE_MODE_NONE 0x00
264 #define PAGE_MODE_1_LEVEL 0x01
265 #define PAGE_MODE_2_LEVEL 0x02
266 #define PAGE_MODE_3_LEVEL 0x03
267 #define PAGE_MODE_4_LEVEL 0x04
268 #define PAGE_MODE_5_LEVEL 0x05
269 #define PAGE_MODE_6_LEVEL 0x06
270 #define PAGE_MODE_7_LEVEL 0x07
272 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
273 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
274 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
275 (0xffffffffffffffffULL))
276 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
277 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
278 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
279 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
280 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
283 #define PM_ADDR_MASK 0x000ffffffffff000ULL
284 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
285 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
286 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
289 * Returns the page table level to use for a given page size
290 * Pagesize is expected to be a power-of-two
292 #define PAGE_SIZE_LEVEL(pagesize) \
293 ((__ffs(pagesize) - 12) / 9)
295 * Returns the number of ptes to use for a given page size
296 * Pagesize is expected to be a power-of-two
298 #define PAGE_SIZE_PTE_COUNT(pagesize) \
299 (1ULL << ((__ffs(pagesize) - 12) % 9))
302 * Aligns a given io-virtual address to a given page size
303 * Pagesize is expected to be a power-of-two
305 #define PAGE_SIZE_ALIGN(address, pagesize) \
306 ((address) & ~((pagesize) - 1))
308 * Creates an IOMMU PTE for an address and a given pagesize
309 * The PTE has no permission bits set
310 * Pagesize is expected to be a power-of-two larger than 4096
312 #define PAGE_SIZE_PTE(address, pagesize) \
313 (((address) | ((pagesize) - 1)) & \
314 (~(pagesize >> 1)) & PM_ADDR_MASK)
317 * Takes a PTE value with mode=0x07 and returns the page size it maps
319 #define PTE_PAGE_SIZE(pte) \
320 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
323 * Takes a page-table level and returns the default page-size for this level
325 #define PTE_LEVEL_PAGE_SIZE(level) \
326 (1ULL << (12 + (9 * (level))))
329 * Bit value definition for I/O PTE fields
331 #define IOMMU_PTE_PR (1ULL << 0)
332 #define IOMMU_PTE_U (1ULL << 59)
333 #define IOMMU_PTE_FC (1ULL << 60)
334 #define IOMMU_PTE_IR (1ULL << 61)
335 #define IOMMU_PTE_IW (1ULL << 62)
338 * Bit value definition for DTE fields
340 #define DTE_FLAG_V (1ULL << 0)
341 #define DTE_FLAG_TV (1ULL << 1)
342 #define DTE_FLAG_IR (1ULL << 61)
343 #define DTE_FLAG_IW (1ULL << 62)
345 #define DTE_FLAG_IOTLB (1ULL << 32)
346 #define DTE_FLAG_GV (1ULL << 55)
347 #define DTE_FLAG_MASK (0x3ffULL << 32)
348 #define DTE_GLX_SHIFT (56)
349 #define DTE_GLX_MASK (3)
350 #define DEV_DOMID_MASK 0xffffULL
352 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
353 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
354 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL)
356 #define DTE_GCR3_INDEX_A 0
357 #define DTE_GCR3_INDEX_B 1
358 #define DTE_GCR3_INDEX_C 1
360 #define DTE_GCR3_SHIFT_A 58
361 #define DTE_GCR3_SHIFT_B 16
362 #define DTE_GCR3_SHIFT_C 43
364 #define GCR3_VALID 0x01ULL
366 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
367 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR)
368 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK))
369 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
371 #define IOMMU_PROT_MASK 0x03
372 #define IOMMU_PROT_IR 0x01
373 #define IOMMU_PROT_IW 0x02
375 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
377 /* IOMMU capabilities */
378 #define IOMMU_CAP_IOTLB 24
379 #define IOMMU_CAP_NPCACHE 26
380 #define IOMMU_CAP_EFR 27
382 /* IOMMU Feature Reporting Field (for IVHD type 10h */
383 #define IOMMU_FEAT_GASUP_SHIFT 6
385 /* IOMMU Extended Feature Register (EFR) */
386 #define IOMMU_EFR_XTSUP_SHIFT 2
387 #define IOMMU_EFR_GASUP_SHIFT 7
388 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46
390 #define MAX_DOMAIN_ID 65536
392 /* Protection domain flags */
393 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
394 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
395 domain for an IOMMU */
396 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
398 #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */
400 extern bool amd_iommu_dump;
401 #define DUMP_printk(format, arg...) \
403 if (amd_iommu_dump) \
404 pr_info("AMD-Vi: " format, ## arg); \
407 /* global flag if IOMMUs cache non-present entries */
408 extern bool amd_iommu_np_cache;
409 /* Only true if all IOMMUs support device IOTLBs */
410 extern bool amd_iommu_iotlb_sup;
413 * AMD IOMMU hardware only support 512 IRTEs despite
414 * the architectural limitation of 2048 entries.
416 #define MAX_IRQS_PER_TABLE 512
417 #define IRQ_TABLE_ALIGNMENT 128
419 struct irq_remap_table {
425 extern struct irq_remap_table **irq_lookup_table;
427 /* Interrupt remapping feature used? */
428 extern bool amd_iommu_irq_remap;
430 /* kmem_cache to get tables with 128 byte alignement */
431 extern struct kmem_cache *amd_iommu_irq_cache;
434 * Make iterating over all IOMMUs easier
436 #define for_each_iommu(iommu) \
437 list_for_each_entry((iommu), &amd_iommu_list, list)
438 #define for_each_iommu_safe(iommu, next) \
439 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
441 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
442 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
443 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
444 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
445 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
446 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
449 * This struct is used to pass information about
450 * incoming PPR faults around.
452 struct amd_iommu_fault {
453 u64 address; /* IO virtual address of the fault*/
454 u32 pasid; /* Address space identifier */
455 u16 device_id; /* Originating PCI device id */
456 u16 tag; /* PPR tag */
457 u16 flags; /* Fault flags */
466 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
469 * This structure contains generic data for IOMMU protection domains
470 * independent of their use.
472 struct protection_domain {
473 struct list_head dev_list; /* List of all devices in this domain */
474 struct iommu_domain domain; /* generic domain handle used by
476 spinlock_t lock; /* mostly used to lock the page table*/
477 u16 id; /* the domain id written to the device table */
478 atomic64_t pt_root; /* pgtable root and pgtable mode */
479 int glx; /* Number of levels for GCR3 table */
480 u64 *gcr3_tbl; /* Guest CR3 table */
481 unsigned long flags; /* flags to find out type of domain */
482 unsigned dev_cnt; /* devices assigned to this domain */
483 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
486 /* For decocded pt_root */
487 struct domain_pgtable {
493 * Structure where we save information about one hardware AMD IOMMU in the
497 struct list_head list;
499 /* Index within the IOMMU array */
502 /* locks the accesses to the hardware */
505 /* Pointer to PCI device of this IOMMU */
508 /* Cache pdev to root device for resume quirks */
509 struct pci_dev *root_pdev;
511 /* physical address of MMIO space */
514 /* physical end address of MMIO space */
517 /* virtual address of MMIO space */
518 u8 __iomem *mmio_base;
520 /* capabilities of that IOMMU read from ACPI */
523 /* flags read from acpi table */
526 /* Extended features */
532 /* PCI device id of the IOMMU device */
536 * Capability pointer. There could be more than one IOMMU per PCI
537 * device function if there are more than one AMD IOMMU capability
542 /* pci domain of this IOMMU */
545 /* start of exclusion range of that IOMMU */
547 /* length of exclusion range of that IOMMU */
548 u64 exclusion_length;
550 /* command buffer virtual address */
555 /* event buffer virtual address */
558 /* Base of the PPR log, if present */
561 /* Base of the GA log, if present */
564 /* Tail of the GA log, if present */
567 /* true if interrupts for this IOMMU are already enabled */
570 /* if one, we need to send a completion wait command */
573 /* Handle for IOMMU core code */
574 struct iommu_device iommu;
577 * We can't rely on the BIOS to restore all values on reinit, so we
586 * Each iommu has 6 l1s, each of which is documented as having 0x12
589 u32 stored_l1[6][0x12];
591 /* The l2 indirect registers */
594 /* The maximum PC banks and counters/bank (PCSup=1) */
597 #ifdef CONFIG_IRQ_REMAP
598 struct irq_domain *ir_domain;
599 struct irq_domain *msi_domain;
601 struct amd_irte_ops *irte_ops;
605 volatile u64 *cmd_sem;
608 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
610 struct dentry *debugfs;
612 /* IRQ notifier for IntCapXT interrupt */
613 struct irq_affinity_notify intcapxt_notify;
616 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
618 struct iommu_device *iommu = dev_to_iommu_device(dev);
620 return container_of(iommu, struct amd_iommu, iommu);
623 #define ACPIHID_UID_LEN 256
624 #define ACPIHID_HID_LEN 9
626 struct acpihid_map_entry {
627 struct list_head list;
628 u8 uid[ACPIHID_UID_LEN];
629 u8 hid[ACPIHID_HID_LEN];
633 struct iommu_group *group;
637 struct list_head list;
644 * This struct contains device specific data for the IOMMU
646 struct iommu_dev_data {
647 /*Protect against attach/detach races */
650 struct list_head list; /* For domain->dev_list */
651 struct llist_node dev_data_list; /* For global dev_data_list */
652 struct protection_domain *domain; /* Domain the device is bound to */
653 struct pci_dev *pdev;
654 u16 devid; /* PCI Device ID */
655 bool iommu_v2; /* Device can make use of IOMMUv2 */
659 } ats; /* ATS state */
660 bool pri_tlp; /* PASID TLB required for
662 u32 errata; /* Bitmap for errata to apply */
663 bool use_vapic; /* Enable device to use vapic mode */
666 struct ratelimit_state rs; /* Ratelimit IOPF messages */
669 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
670 extern struct list_head ioapic_map;
671 extern struct list_head hpet_map;
672 extern struct list_head acpihid_map;
675 * List with all IOMMUs in the system. This list is not locked because it is
676 * only written and read at driver initialization or suspend time
678 extern struct list_head amd_iommu_list;
681 * Array with pointers to each IOMMU struct
682 * The indices are referenced in the protection domains
684 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
687 * Structure defining one entry in the device table
689 struct dev_table_entry {
694 * One entry for unity mappings parsed out of the ACPI table.
696 struct unity_map_entry {
697 struct list_head list;
699 /* starting device id this entry is used for (including) */
701 /* end device id this entry is used for (including) */
704 /* start address to unity map (including) */
706 /* end address to unity map (including) */
709 /* required protection */
714 * List of all unity mappings. It is not locked because as runtime it is only
715 * read. It is created at ACPI table parsing time.
717 extern struct list_head amd_iommu_unity_map;
720 * Data structures for device handling
724 * Device table used by hardware. Read and write accesses by software are
725 * locked with the amd_iommu_pd_table lock.
727 extern struct dev_table_entry *amd_iommu_dev_table;
730 * Alias table to find requestor ids to device ids. Not locked because only
733 extern u16 *amd_iommu_alias_table;
736 * Reverse lookup table to find the IOMMU which translates a specific device.
738 extern struct amd_iommu **amd_iommu_rlookup_table;
740 /* size of the dma_ops aperture as power of 2 */
741 extern unsigned amd_iommu_aperture_order;
743 /* largest PCI device id we expect translation requests for */
744 extern u16 amd_iommu_last_bdf;
746 /* allocation bitmap for domain ids */
747 extern unsigned long *amd_iommu_pd_alloc_bitmap;
750 * If true, the addresses will be flushed on unmap time, not when
753 extern bool amd_iommu_unmap_flush;
755 /* Smallest max PASID supported by any IOMMU in the system */
756 extern u32 amd_iommu_max_pasid;
758 extern bool amd_iommu_v2_present;
760 extern bool amd_iommu_force_isolation;
762 /* Max levels of glxval supported */
763 extern int amd_iommu_max_glx_val;
766 * This function flushes all internal caches of
767 * the IOMMU used by this driver.
769 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
771 static inline int get_ioapic_devid(int id)
773 struct devid_map *entry;
775 list_for_each_entry(entry, &ioapic_map, list) {
783 static inline int get_hpet_devid(int id)
785 struct devid_map *entry;
787 list_for_each_entry(entry, &hpet_map, list) {
795 enum amd_iommu_intr_mode_type {
796 AMD_IOMMU_GUEST_IR_LEGACY,
798 /* This mode is not visible to users. It is used when
799 * we cannot fully enable vAPIC and fallback to only support
800 * legacy interrupt remapping via 128-bit IRTE.
802 AMD_IOMMU_GUEST_IR_LEGACY_GA,
803 AMD_IOMMU_GUEST_IR_VAPIC,
806 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
807 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
809 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
826 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff)
827 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff)
832 /* For int remapping */
846 /* For guest vAPIC */
878 u16 devid; /* Device ID for IRTE table */
879 u16 index; /* Index into IRTE table*/
884 struct irq_2_irte irq_2_irte;
885 struct msi_msg msi_entry;
886 void *entry; /* Pointer to union irte or struct irte_ga */
887 void *ref; /* Pointer to the actual irte */
890 * Store information for activate/de-activate
891 * Guest virtual APIC mode during runtime.
899 struct amd_irte_ops {
900 void (*prepare)(void *, u32, u32, u8, u32, int);
901 void (*activate)(void *, u16, u16);
902 void (*deactivate)(void *, u16, u16);
903 void (*set_affinity)(void *, u16, u16, u8, u32);
904 void *(*get)(struct irq_remap_table *, int);
905 void (*set_allocated)(struct irq_remap_table *, int);
906 bool (*is_allocated)(struct irq_remap_table *, int);
907 void (*clear_allocated)(struct irq_remap_table *, int);
910 #ifdef CONFIG_IRQ_REMAP
911 extern struct amd_irte_ops irte_32_ops;
912 extern struct amd_irte_ops irte_128_ops;
915 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */