drivers/interconnect/qcom/sm8550.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
   5  * Copyright (c) 2022, Linaro Limited
   6  *
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/interconnect.h>
  11 #include <linux/interconnect-provider.h>
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/property.h>
  16 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
  17
  18 #include "bcm-voter.h"
  19 #include "icc-common.h"
  20 #include "icc-rpmh.h"
  21 #include "sm8550.h"
  22
  23 static struct qcom_icc_node qhm_qspi = {
  24         .name = "qhm_qspi",
  25         .id = SM8550_MASTER_QSPI_0,
  26         .channels = 1,
  27         .buswidth = 4,
  28         .num_links = 1,
  29         .links = { SM8550_SLAVE_A1NOC_SNOC },
  30 };
  31
  32 static struct qcom_icc_node qhm_qup1 = {
  33         .name = "qhm_qup1",
  34         .id = SM8550_MASTER_QUP_1,
  35         .channels = 1,
  36         .buswidth = 4,
  37         .num_links = 1,
  38         .links = { SM8550_SLAVE_A1NOC_SNOC },
  39 };
  40
  41 static struct qcom_icc_node xm_sdc4 = {
  42         .name = "xm_sdc4",
  43         .id = SM8550_MASTER_SDCC_4,
  44         .channels = 1,
  45         .buswidth = 8,
  46         .num_links = 1,
  47         .links = { SM8550_SLAVE_A1NOC_SNOC },
  48 };
  49
  50 static struct qcom_icc_node xm_ufs_mem = {
  51         .name = "xm_ufs_mem",
  52         .id = SM8550_MASTER_UFS_MEM,
  53         .channels = 1,
  54         .buswidth = 16,
  55         .num_links = 1,
  56         .links = { SM8550_SLAVE_A1NOC_SNOC },
  57 };
  58
  59 static struct qcom_icc_node xm_usb3_0 = {
  60         .name = "xm_usb3_0",
  61         .id = SM8550_MASTER_USB3_0,
  62         .channels = 1,
  63         .buswidth = 8,
  64         .num_links = 1,
  65         .links = { SM8550_SLAVE_A1NOC_SNOC },
  66 };
  67
  68 static struct qcom_icc_node qhm_qdss_bam = {
  69         .name = "qhm_qdss_bam",
  70         .id = SM8550_MASTER_QDSS_BAM,
  71         .channels = 1,
  72         .buswidth = 4,
  73         .num_links = 1,
  74         .links = { SM8550_SLAVE_A2NOC_SNOC },
  75 };
  76
  77 static struct qcom_icc_node qhm_qup2 = {
  78         .name = "qhm_qup2",
  79         .id = SM8550_MASTER_QUP_2,
  80         .channels = 1,
  81         .buswidth = 4,
  82         .num_links = 1,
  83         .links = { SM8550_SLAVE_A2NOC_SNOC },
  84 };
  85
  86 static struct qcom_icc_node qxm_crypto = {
  87         .name = "qxm_crypto",
  88         .id = SM8550_MASTER_CRYPTO,
  89         .channels = 1,
  90         .buswidth = 8,
  91         .num_links = 1,
  92         .links = { SM8550_SLAVE_A2NOC_SNOC },
  93 };
  94
  95 static struct qcom_icc_node qxm_ipa = {
  96         .name = "qxm_ipa",
  97         .id = SM8550_MASTER_IPA,
  98         .channels = 1,
  99         .buswidth = 8,
 100         .num_links = 1,
 101         .links = { SM8550_SLAVE_A2NOC_SNOC },
 102 };
 103
 104 static struct qcom_icc_node qxm_sp = {
 105         .name = "qxm_sp",
 106         .id = SM8550_MASTER_SP,
 107         .channels = 1,
 108         .buswidth = 8,
 109         .num_links = 1,
 110         .links = { SM8550_SLAVE_A2NOC_SNOC },
 111 };
 112
 113 static struct qcom_icc_node xm_qdss_etr_0 = {
 114         .name = "xm_qdss_etr_0",
 115         .id = SM8550_MASTER_QDSS_ETR,
 116         .channels = 1,
 117         .buswidth = 8,
 118         .num_links = 1,
 119         .links = { SM8550_SLAVE_A2NOC_SNOC },
 120 };
 121
 122 static struct qcom_icc_node xm_qdss_etr_1 = {
 123         .name = "xm_qdss_etr_1",
 124         .id = SM8550_MASTER_QDSS_ETR_1,
 125         .channels = 1,
 126         .buswidth = 8,
 127         .num_links = 1,
 128         .links = { SM8550_SLAVE_A2NOC_SNOC },
 129 };
 130
 131 static struct qcom_icc_node xm_sdc2 = {
 132         .name = "xm_sdc2",
 133         .id = SM8550_MASTER_SDCC_2,
 134         .channels = 1,
 135         .buswidth = 8,
 136         .num_links = 1,
 137         .links = { SM8550_SLAVE_A2NOC_SNOC },
 138 };
 139
 140 static struct qcom_icc_node qup0_core_master = {
 141         .name = "qup0_core_master",
 142         .id = SM8550_MASTER_QUP_CORE_0,
 143         .channels = 1,
 144         .buswidth = 4,
 145         .num_links = 1,
 146         .links = { SM8550_SLAVE_QUP_CORE_0 },
 147 };
 148
 149 static struct qcom_icc_node qup1_core_master = {
 150         .name = "qup1_core_master",
 151         .id = SM8550_MASTER_QUP_CORE_1,
 152         .channels = 1,
 153         .buswidth = 4,
 154         .num_links = 1,
 155         .links = { SM8550_SLAVE_QUP_CORE_1 },
 156 };
 157
 158 static struct qcom_icc_node qup2_core_master = {
 159         .name = "qup2_core_master",
 160         .id = SM8550_MASTER_QUP_CORE_2,
 161         .channels = 1,
 162         .buswidth = 4,
 163         .num_links = 1,
 164         .links = { SM8550_SLAVE_QUP_CORE_2 },
 165 };
 166
 167 static struct qcom_icc_node qsm_cfg = {
 168         .name = "qsm_cfg",
 169         .id = SM8550_MASTER_CNOC_CFG,
 170         .channels = 1,
 171         .buswidth = 4,
 172         .num_links = 44,
 173         .links = { SM8550_SLAVE_AHB2PHY_SOUTH, SM8550_SLAVE_AHB2PHY_NORTH,
 174                    SM8550_SLAVE_APPSS, SM8550_SLAVE_CAMERA_CFG,
 175                    SM8550_SLAVE_CLK_CTL, SM8550_SLAVE_RBCPR_CX_CFG,
 176                    SM8550_SLAVE_RBCPR_MMCX_CFG, SM8550_SLAVE_RBCPR_MXA_CFG,
 177                    SM8550_SLAVE_RBCPR_MXC_CFG, SM8550_SLAVE_CPR_NSPCX,
 178                    SM8550_SLAVE_CRYPTO_0_CFG, SM8550_SLAVE_CX_RDPM,
 179                    SM8550_SLAVE_DISPLAY_CFG, SM8550_SLAVE_GFX3D_CFG,
 180                    SM8550_SLAVE_I2C, SM8550_SLAVE_IMEM_CFG,
 181                    SM8550_SLAVE_IPA_CFG, SM8550_SLAVE_IPC_ROUTER_CFG,
 182                    SM8550_SLAVE_CNOC_MSS, SM8550_SLAVE_MX_RDPM,
 183                    SM8550_SLAVE_PCIE_0_CFG, SM8550_SLAVE_PCIE_1_CFG,
 184                    SM8550_SLAVE_PDM, SM8550_SLAVE_PIMEM_CFG,
 185                    SM8550_SLAVE_PRNG, SM8550_SLAVE_QDSS_CFG,
 186                    SM8550_SLAVE_QSPI_0, SM8550_SLAVE_QUP_1,
 187                    SM8550_SLAVE_QUP_2, SM8550_SLAVE_SDCC_2,
 188                    SM8550_SLAVE_SDCC_4, SM8550_SLAVE_SPSS_CFG,
 189                    SM8550_SLAVE_TCSR, SM8550_SLAVE_TLMM,
 190                    SM8550_SLAVE_UFS_MEM_CFG, SM8550_SLAVE_USB3_0,
 191                    SM8550_SLAVE_VENUS_CFG, SM8550_SLAVE_VSENSE_CTRL_CFG,
 192                    SM8550_SLAVE_LPASS_QTB_CFG, SM8550_SLAVE_CNOC_MNOC_CFG,
 193                    SM8550_SLAVE_NSP_QTB_CFG, SM8550_SLAVE_PCIE_ANOC_CFG,
 194                    SM8550_SLAVE_QDSS_STM, SM8550_SLAVE_TCU },
 195 };
 196
 197 static struct qcom_icc_node qnm_gemnoc_cnoc = {
 198         .name = "qnm_gemnoc_cnoc",
 199         .id = SM8550_MASTER_GEM_NOC_CNOC,
 200         .channels = 1,
 201         .buswidth = 16,
 202         .num_links = 6,
 203         .links = { SM8550_SLAVE_AOSS, SM8550_SLAVE_TME_CFG,
 204                    SM8550_SLAVE_CNOC_CFG, SM8550_SLAVE_DDRSS_CFG,
 205                    SM8550_SLAVE_BOOT_IMEM, SM8550_SLAVE_IMEM },
 206 };
 207
 208 static struct qcom_icc_node qnm_gemnoc_pcie = {
 209         .name = "qnm_gemnoc_pcie",
 210         .id = SM8550_MASTER_GEM_NOC_PCIE_SNOC,
 211         .channels = 1,
 212         .buswidth = 8,
 213         .num_links = 2,
 214         .links = { SM8550_SLAVE_PCIE_0, SM8550_SLAVE_PCIE_1 },
 215 };
 216
 217 static struct qcom_icc_node alm_gpu_tcu = {
 218         .name = "alm_gpu_tcu",
 219         .id = SM8550_MASTER_GPU_TCU,
 220         .channels = 1,
 221         .buswidth = 8,
 222         .num_links = 2,
 223         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 224 };
 225
 226 static struct qcom_icc_node alm_sys_tcu = {
 227         .name = "alm_sys_tcu",
 228         .id = SM8550_MASTER_SYS_TCU,
 229         .channels = 1,
 230         .buswidth = 8,
 231         .num_links = 2,
 232         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 233 };
 234
 235 static struct qcom_icc_node chm_apps = {
 236         .name = "chm_apps",
 237         .id = SM8550_MASTER_APPSS_PROC,
 238         .channels = 3,
 239         .buswidth = 32,
 240         .num_links = 3,
 241         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
 242                    SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
 243 };
 244
 245 static struct qcom_icc_node qnm_gpu = {
 246         .name = "qnm_gpu",
 247         .id = SM8550_MASTER_GFX3D,
 248         .channels = 2,
 249         .buswidth = 32,
 250         .num_links = 2,
 251         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 252 };
 253
 254 static struct qcom_icc_node qnm_lpass_gemnoc = {
 255         .name = "qnm_lpass_gemnoc",
 256         .id = SM8550_MASTER_LPASS_GEM_NOC,
 257         .channels = 1,
 258         .buswidth = 16,
 259         .num_links = 3,
 260         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
 261                    SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
 262 };
 263
 264 static struct qcom_icc_node qnm_mdsp = {
 265         .name = "qnm_mdsp",
 266         .id = SM8550_MASTER_MSS_PROC,
 267         .channels = 1,
 268         .buswidth = 16,
 269         .num_links = 3,
 270         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
 271                    SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
 272 };
 273
 274 static struct qcom_icc_node qnm_mnoc_hf = {
 275         .name = "qnm_mnoc_hf",
 276         .id = SM8550_MASTER_MNOC_HF_MEM_NOC,
 277         .channels = 2,
 278         .buswidth = 32,
 279         .num_links = 2,
 280         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 281 };
 282
 283 static struct qcom_icc_node qnm_mnoc_sf = {
 284         .name = "qnm_mnoc_sf",
 285         .id = SM8550_MASTER_MNOC_SF_MEM_NOC,
 286         .channels = 2,
 287         .buswidth = 32,
 288         .num_links = 2,
 289         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 290 };
 291
 292 static struct qcom_icc_node qnm_nsp_gemnoc = {
 293         .name = "qnm_nsp_gemnoc",
 294         .id = SM8550_MASTER_COMPUTE_NOC,
 295         .channels = 2,
 296         .buswidth = 32,
 297         .num_links = 2,
 298         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 299 };
 300
 301 static struct qcom_icc_node qnm_pcie = {
 302         .name = "qnm_pcie",
 303         .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC,
 304         .channels = 1,
 305         .buswidth = 16,
 306         .num_links = 2,
 307         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 308 };
 309
 310 static struct qcom_icc_node qnm_snoc_gc = {
 311         .name = "qnm_snoc_gc",
 312         .id = SM8550_MASTER_SNOC_GC_MEM_NOC,
 313         .channels = 1,
 314         .buswidth = 8,
 315         .num_links = 1,
 316         .links = { SM8550_SLAVE_LLCC },
 317 };
 318
 319 static struct qcom_icc_node qnm_snoc_sf = {
 320         .name = "qnm_snoc_sf",
 321         .id = SM8550_MASTER_SNOC_SF_MEM_NOC,
 322         .channels = 1,
 323         .buswidth = 16,
 324         .num_links = 3,
 325         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
 326                    SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
 327 };
 328
 329 static struct qcom_icc_node qnm_lpiaon_noc = {
 330         .name = "qnm_lpiaon_noc",
 331         .id = SM8550_MASTER_LPIAON_NOC,
 332         .channels = 1,
 333         .buswidth = 16,
 334         .num_links = 1,
 335         .links = { SM8550_SLAVE_LPASS_GEM_NOC },
 336 };
 337
 338 static struct qcom_icc_node qnm_lpass_lpinoc = {
 339         .name = "qnm_lpass_lpinoc",
 340         .id = SM8550_MASTER_LPASS_LPINOC,
 341         .channels = 1,
 342         .buswidth = 16,
 343         .num_links = 1,
 344         .links = { SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
 345 };
 346
 347 static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
 348         .name = "qxm_lpinoc_dsp_axim",
 349         .id = SM8550_MASTER_LPASS_PROC,
 350         .channels = 1,
 351         .buswidth = 16,
 352         .num_links = 1,
 353         .links = { SM8550_SLAVE_LPICX_NOC_LPIAON_NOC },
 354 };
 355
 356 static struct qcom_icc_node llcc_mc = {
 357         .name = "llcc_mc",
 358         .id = SM8550_MASTER_LLCC,
 359         .channels = 4,
 360         .buswidth = 4,
 361         .num_links = 1,
 362         .links = { SM8550_SLAVE_EBI1 },
 363 };
 364
 365 static struct qcom_icc_node qnm_camnoc_hf = {
 366         .name = "qnm_camnoc_hf",
 367         .id = SM8550_MASTER_CAMNOC_HF,
 368         .channels = 2,
 369         .buswidth = 32,
 370         .num_links = 1,
 371         .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
 372 };
 373
 374 static struct qcom_icc_node qnm_camnoc_icp = {
 375         .name = "qnm_camnoc_icp",
 376         .id = SM8550_MASTER_CAMNOC_ICP,
 377         .channels = 1,
 378         .buswidth = 8,
 379         .num_links = 1,
 380         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 381 };
 382
 383 static struct qcom_icc_node qnm_camnoc_sf = {
 384         .name = "qnm_camnoc_sf",
 385         .id = SM8550_MASTER_CAMNOC_SF,
 386         .channels = 2,
 387         .buswidth = 32,
 388         .num_links = 1,
 389         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 390 };
 391
 392 static struct qcom_icc_node qnm_mdp = {
 393         .name = "qnm_mdp",
 394         .id = SM8550_MASTER_MDP,
 395         .channels = 2,
 396         .buswidth = 32,
 397         .num_links = 1,
 398         .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
 399 };
 400
 401 static struct qcom_icc_node qnm_vapss_hcp = {
 402         .name = "qnm_vapss_hcp",
 403         .id = SM8550_MASTER_CDSP_HCP,
 404         .channels = 1,
 405         .buswidth = 32,
 406         .num_links = 1,
 407         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 408 };
 409
 410 static struct qcom_icc_node qnm_video = {
 411         .name = "qnm_video",
 412         .id = SM8550_MASTER_VIDEO,
 413         .channels = 2,
 414         .buswidth = 32,
 415         .num_links = 1,
 416         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 417 };
 418
 419 static struct qcom_icc_node qnm_video_cv_cpu = {
 420         .name = "qnm_video_cv_cpu",
 421         .id = SM8550_MASTER_VIDEO_CV_PROC,
 422         .channels = 1,
 423         .buswidth = 8,
 424         .num_links = 1,
 425         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 426 };
 427
 428 static struct qcom_icc_node qnm_video_cvp = {
 429         .name = "qnm_video_cvp",
 430         .id = SM8550_MASTER_VIDEO_PROC,
 431         .channels = 1,
 432         .buswidth = 32,
 433         .num_links = 1,
 434         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 435 };
 436
 437 static struct qcom_icc_node qnm_video_v_cpu = {
 438         .name = "qnm_video_v_cpu",
 439         .id = SM8550_MASTER_VIDEO_V_PROC,
 440         .channels = 1,
 441         .buswidth = 8,
 442         .num_links = 1,
 443         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 444 };
 445
 446 static struct qcom_icc_node qsm_mnoc_cfg = {
 447         .name = "qsm_mnoc_cfg",
 448         .id = SM8550_MASTER_CNOC_MNOC_CFG,
 449         .channels = 1,
 450         .buswidth = 4,
 451         .num_links = 1,
 452         .links = { SM8550_SLAVE_SERVICE_MNOC },
 453 };
 454
 455 static struct qcom_icc_node qxm_nsp = {
 456         .name = "qxm_nsp",
 457         .id = SM8550_MASTER_CDSP_PROC,
 458         .channels = 2,
 459         .buswidth = 32,
 460         .num_links = 1,
 461         .links = { SM8550_SLAVE_CDSP_MEM_NOC },
 462 };
 463
 464 static struct qcom_icc_node qsm_pcie_anoc_cfg = {
 465         .name = "qsm_pcie_anoc_cfg",
 466         .id = SM8550_MASTER_PCIE_ANOC_CFG,
 467         .channels = 1,
 468         .buswidth = 4,
 469         .num_links = 1,
 470         .links = { SM8550_SLAVE_SERVICE_PCIE_ANOC },
 471 };
 472
 473 static struct qcom_icc_node xm_pcie3_0 = {
 474         .name = "xm_pcie3_0",
 475         .id = SM8550_MASTER_PCIE_0,
 476         .channels = 1,
 477         .buswidth = 8,
 478         .num_links = 1,
 479         .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
 480 };
 481
 482 static struct qcom_icc_node xm_pcie3_1 = {
 483         .name = "xm_pcie3_1",
 484         .id = SM8550_MASTER_PCIE_1,
 485         .channels = 1,
 486         .buswidth = 16,
 487         .num_links = 1,
 488         .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
 489 };
 490
 491 static struct qcom_icc_node qhm_gic = {
 492         .name = "qhm_gic",
 493         .id = SM8550_MASTER_GIC_AHB,
 494         .channels = 1,
 495         .buswidth = 4,
 496         .num_links = 1,
 497         .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
 498 };
 499
 500 static struct qcom_icc_node qnm_aggre1_noc = {
 501         .name = "qnm_aggre1_noc",
 502         .id = SM8550_MASTER_A1NOC_SNOC,
 503         .channels = 1,
 504         .buswidth = 16,
 505         .num_links = 1,
 506         .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
 507 };
 508
 509 static struct qcom_icc_node qnm_aggre2_noc = {
 510         .name = "qnm_aggre2_noc",
 511         .id = SM8550_MASTER_A2NOC_SNOC,
 512         .channels = 1,
 513         .buswidth = 16,
 514         .num_links = 1,
 515         .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
 516 };
 517
 518 static struct qcom_icc_node xm_gic = {
 519         .name = "xm_gic",
 520         .id = SM8550_MASTER_GIC,
 521         .channels = 1,
 522         .buswidth = 8,
 523         .num_links = 1,
 524         .links = { SM8550_SLAVE_SNOC_GEM_NOC_GC },
 525 };
 526
 527 static struct qcom_icc_node qns_a1noc_snoc = {
 528         .name = "qns_a1noc_snoc",
 529         .id = SM8550_SLAVE_A1NOC_SNOC,
 530         .channels = 1,
 531         .buswidth = 16,
 532         .num_links = 1,
 533         .links = { SM8550_MASTER_A1NOC_SNOC },
 534 };
 535
 536 static struct qcom_icc_node qns_a2noc_snoc = {
 537         .name = "qns_a2noc_snoc",
 538         .id = SM8550_SLAVE_A2NOC_SNOC,
 539         .channels = 1,
 540         .buswidth = 16,
 541         .num_links = 1,
 542         .links = { SM8550_MASTER_A2NOC_SNOC },
 543 };
 544
 545 static struct qcom_icc_node qup0_core_slave = {
 546         .name = "qup0_core_slave",
 547         .id = SM8550_SLAVE_QUP_CORE_0,
 548         .channels = 1,
 549         .buswidth = 4,
 550         .num_links = 0,
 551 };
 552
 553 static struct qcom_icc_node qup1_core_slave = {
 554         .name = "qup1_core_slave",
 555         .id = SM8550_SLAVE_QUP_CORE_1,
 556         .channels = 1,
 557         .buswidth = 4,
 558         .num_links = 0,
 559 };
 560
 561 static struct qcom_icc_node qup2_core_slave = {
 562         .name = "qup2_core_slave",
 563         .id = SM8550_SLAVE_QUP_CORE_2,
 564         .channels = 1,
 565         .buswidth = 4,
 566         .num_links = 0,
 567 };
 568
 569 static struct qcom_icc_node qhs_ahb2phy0 = {
 570         .name = "qhs_ahb2phy0",
 571         .id = SM8550_SLAVE_AHB2PHY_SOUTH,
 572         .channels = 1,
 573         .buswidth = 4,
 574         .num_links = 0,
 575 };
 576
 577 static struct qcom_icc_node qhs_ahb2phy1 = {
 578         .name = "qhs_ahb2phy1",
 579         .id = SM8550_SLAVE_AHB2PHY_NORTH,
 580         .channels = 1,
 581         .buswidth = 4,
 582         .num_links = 0,
 583 };
 584
 585 static struct qcom_icc_node qhs_apss = {
 586         .name = "qhs_apss",
 587         .id = SM8550_SLAVE_APPSS,
 588         .channels = 1,
 589         .buswidth = 8,
 590         .num_links = 0,
 591 };
 592
 593 static struct qcom_icc_node qhs_camera_cfg = {
 594         .name = "qhs_camera_cfg",
 595         .id = SM8550_SLAVE_CAMERA_CFG,
 596         .channels = 1,
 597         .buswidth = 4,
 598         .num_links = 0,
 599 };
 600
 601 static struct qcom_icc_node qhs_clk_ctl = {
 602         .name = "qhs_clk_ctl",
 603         .id = SM8550_SLAVE_CLK_CTL,
 604         .channels = 1,
 605         .buswidth = 4,
 606         .num_links = 0,
 607 };
 608
 609 static struct qcom_icc_node qhs_cpr_cx = {
 610         .name = "qhs_cpr_cx",
 611         .id = SM8550_SLAVE_RBCPR_CX_CFG,
 612         .channels = 1,
 613         .buswidth = 4,
 614         .num_links = 0,
 615 };
 616
 617 static struct qcom_icc_node qhs_cpr_mmcx = {
 618         .name = "qhs_cpr_mmcx",
 619         .id = SM8550_SLAVE_RBCPR_MMCX_CFG,
 620         .channels = 1,
 621         .buswidth = 4,
 622         .num_links = 0,
 623 };
 624
 625 static struct qcom_icc_node qhs_cpr_mxa = {
 626         .name = "qhs_cpr_mxa",
 627         .id = SM8550_SLAVE_RBCPR_MXA_CFG,
 628         .channels = 1,
 629         .buswidth = 4,
 630         .num_links = 0,
 631 };
 632
 633 static struct qcom_icc_node qhs_cpr_mxc = {
 634         .name = "qhs_cpr_mxc",
 635         .id = SM8550_SLAVE_RBCPR_MXC_CFG,
 636         .channels = 1,
 637         .buswidth = 4,
 638         .num_links = 0,
 639 };
 640
 641 static struct qcom_icc_node qhs_cpr_nspcx = {
 642         .name = "qhs_cpr_nspcx",
 643         .id = SM8550_SLAVE_CPR_NSPCX,
 644         .channels = 1,
 645         .buswidth = 4,
 646         .num_links = 0,
 647 };
 648
 649 static struct qcom_icc_node qhs_crypto0_cfg = {
 650         .name = "qhs_crypto0_cfg",
 651         .id = SM8550_SLAVE_CRYPTO_0_CFG,
 652         .channels = 1,
 653         .buswidth = 4,
 654         .num_links = 0,
 655 };
 656
 657 static struct qcom_icc_node qhs_cx_rdpm = {
 658         .name = "qhs_cx_rdpm",
 659         .id = SM8550_SLAVE_CX_RDPM,
 660         .channels = 1,
 661         .buswidth = 4,
 662         .num_links = 0,
 663 };
 664
 665 static struct qcom_icc_node qhs_display_cfg = {
 666         .name = "qhs_display_cfg",
 667         .id = SM8550_SLAVE_DISPLAY_CFG,
 668         .channels = 1,
 669         .buswidth = 4,
 670         .num_links = 0,
 671 };
 672
 673 static struct qcom_icc_node qhs_gpuss_cfg = {
 674         .name = "qhs_gpuss_cfg",
 675         .id = SM8550_SLAVE_GFX3D_CFG,
 676         .channels = 1,
 677         .buswidth = 8,
 678         .num_links = 0,
 679 };
 680
 681 static struct qcom_icc_node qhs_i2c = {
 682         .name = "qhs_i2c",
 683         .id = SM8550_SLAVE_I2C,
 684         .channels = 1,
 685         .buswidth = 4,
 686         .num_links = 0,
 687 };
 688
 689 static struct qcom_icc_node qhs_imem_cfg = {
 690         .name = "qhs_imem_cfg",
 691         .id = SM8550_SLAVE_IMEM_CFG,
 692         .channels = 1,
 693         .buswidth = 4,
 694         .num_links = 0,
 695 };
 696
 697 static struct qcom_icc_node qhs_ipa = {
 698         .name = "qhs_ipa",
 699         .id = SM8550_SLAVE_IPA_CFG,
 700         .channels = 1,
 701         .buswidth = 4,
 702         .num_links = 0,
 703 };
 704
 705 static struct qcom_icc_node qhs_ipc_router = {
 706         .name = "qhs_ipc_router",
 707         .id = SM8550_SLAVE_IPC_ROUTER_CFG,
 708         .channels = 1,
 709         .buswidth = 4,
 710         .num_links = 0,
 711 };
 712
 713 static struct qcom_icc_node qhs_mss_cfg = {
 714         .name = "qhs_mss_cfg",
 715         .id = SM8550_SLAVE_CNOC_MSS,
 716         .channels = 1,
 717         .buswidth = 4,
 718         .num_links = 0,
 719 };
 720
 721 static struct qcom_icc_node qhs_mx_rdpm = {
 722         .name = "qhs_mx_rdpm",
 723         .id = SM8550_SLAVE_MX_RDPM,
 724         .channels = 1,
 725         .buswidth = 4,
 726         .num_links = 0,
 727 };
 728
 729 static struct qcom_icc_node qhs_pcie0_cfg = {
 730         .name = "qhs_pcie0_cfg",
 731         .id = SM8550_SLAVE_PCIE_0_CFG,
 732         .channels = 1,
 733         .buswidth = 4,
 734         .num_links = 0,
 735 };
 736
 737 static struct qcom_icc_node qhs_pcie1_cfg = {
 738         .name = "qhs_pcie1_cfg",
 739         .id = SM8550_SLAVE_PCIE_1_CFG,
 740         .channels = 1,
 741         .buswidth = 4,
 742         .num_links = 0,
 743 };
 744
 745 static struct qcom_icc_node qhs_pdm = {
 746         .name = "qhs_pdm",
 747         .id = SM8550_SLAVE_PDM,
 748         .channels = 1,
 749         .buswidth = 4,
 750         .num_links = 0,
 751 };
 752
 753 static struct qcom_icc_node qhs_pimem_cfg = {
 754         .name = "qhs_pimem_cfg",
 755         .id = SM8550_SLAVE_PIMEM_CFG,
 756         .channels = 1,
 757         .buswidth = 4,
 758         .num_links = 0,
 759 };
 760
 761 static struct qcom_icc_node qhs_prng = {
 762         .name = "qhs_prng",
 763         .id = SM8550_SLAVE_PRNG,
 764         .channels = 1,
 765         .buswidth = 4,
 766         .num_links = 0,
 767 };
 768
 769 static struct qcom_icc_node qhs_qdss_cfg = {
 770         .name = "qhs_qdss_cfg",
 771         .id = SM8550_SLAVE_QDSS_CFG,
 772         .channels = 1,
 773         .buswidth = 4,
 774         .num_links = 0,
 775 };
 776
 777 static struct qcom_icc_node qhs_qspi = {
 778         .name = "qhs_qspi",
 779         .id = SM8550_SLAVE_QSPI_0,
 780         .channels = 1,
 781         .buswidth = 4,
 782         .num_links = 0,
 783 };
 784
 785 static struct qcom_icc_node qhs_qup1 = {
 786         .name = "qhs_qup1",
 787         .id = SM8550_SLAVE_QUP_1,
 788         .channels = 1,
 789         .buswidth = 4,
 790         .num_links = 0,
 791 };
 792
 793 static struct qcom_icc_node qhs_qup2 = {
 794         .name = "qhs_qup2",
 795         .id = SM8550_SLAVE_QUP_2,
 796         .channels = 1,
 797         .buswidth = 4,
 798         .num_links = 0,
 799 };
 800
 801 static struct qcom_icc_node qhs_sdc2 = {
 802         .name = "qhs_sdc2",
 803         .id = SM8550_SLAVE_SDCC_2,
 804         .channels = 1,
 805         .buswidth = 4,
 806         .num_links = 0,
 807 };
 808
 809 static struct qcom_icc_node qhs_sdc4 = {
 810         .name = "qhs_sdc4",
 811         .id = SM8550_SLAVE_SDCC_4,
 812         .channels = 1,
 813         .buswidth = 4,
 814         .num_links = 0,
 815 };
 816
 817 static struct qcom_icc_node qhs_spss_cfg = {
 818         .name = "qhs_spss_cfg",
 819         .id = SM8550_SLAVE_SPSS_CFG,
 820         .channels = 1,
 821         .buswidth = 4,
 822         .num_links = 0,
 823 };
 824
 825 static struct qcom_icc_node qhs_tcsr = {
 826         .name = "qhs_tcsr",
 827         .id = SM8550_SLAVE_TCSR,
 828         .channels = 1,
 829         .buswidth = 4,
 830         .num_links = 0,
 831 };
 832
 833 static struct qcom_icc_node qhs_tlmm = {
 834         .name = "qhs_tlmm",
 835         .id = SM8550_SLAVE_TLMM,
 836         .channels = 1,
 837         .buswidth = 4,
 838         .num_links = 0,
 839 };
 840
 841 static struct qcom_icc_node qhs_ufs_mem_cfg = {
 842         .name = "qhs_ufs_mem_cfg",
 843         .id = SM8550_SLAVE_UFS_MEM_CFG,
 844         .channels = 1,
 845         .buswidth = 4,
 846         .num_links = 0,
 847 };
 848
 849 static struct qcom_icc_node qhs_usb3_0 = {
 850         .name = "qhs_usb3_0",
 851         .id = SM8550_SLAVE_USB3_0,
 852         .channels = 1,
 853         .buswidth = 4,
 854         .num_links = 0,
 855 };
 856
 857 static struct qcom_icc_node qhs_venus_cfg = {
 858         .name = "qhs_venus_cfg",
 859         .id = SM8550_SLAVE_VENUS_CFG,
 860         .channels = 1,
 861         .buswidth = 4,
 862         .num_links = 0,
 863 };
 864
 865 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
 866         .name = "qhs_vsense_ctrl_cfg",
 867         .id = SM8550_SLAVE_VSENSE_CTRL_CFG,
 868         .channels = 1,
 869         .buswidth = 4,
 870         .num_links = 0,
 871 };
 872
 873 static struct qcom_icc_node qss_lpass_qtb_cfg = {
 874         .name = "qss_lpass_qtb_cfg",
 875         .id = SM8550_SLAVE_LPASS_QTB_CFG,
 876         .channels = 1,
 877         .buswidth = 4,
 878         .num_links = 0,
 879 };
 880
 881 static struct qcom_icc_node qss_mnoc_cfg = {
 882         .name = "qss_mnoc_cfg",
 883         .id = SM8550_SLAVE_CNOC_MNOC_CFG,
 884         .channels = 1,
 885         .buswidth = 4,
 886         .num_links = 1,
 887         .links = { SM8550_MASTER_CNOC_MNOC_CFG },
 888 };
 889
 890 static struct qcom_icc_node qss_nsp_qtb_cfg = {
 891         .name = "qss_nsp_qtb_cfg",
 892         .id = SM8550_SLAVE_NSP_QTB_CFG,
 893         .channels = 1,
 894         .buswidth = 4,
 895         .num_links = 0,
 896 };
 897
 898 static struct qcom_icc_node qss_pcie_anoc_cfg = {
 899         .name = "qss_pcie_anoc_cfg",
 900         .id = SM8550_SLAVE_PCIE_ANOC_CFG,
 901         .channels = 1,
 902         .buswidth = 4,
 903         .num_links = 1,
 904         .links = { SM8550_MASTER_PCIE_ANOC_CFG },
 905 };
 906
 907 static struct qcom_icc_node xs_qdss_stm = {
 908         .name = "xs_qdss_stm",
 909         .id = SM8550_SLAVE_QDSS_STM,
 910         .channels = 1,
 911         .buswidth = 4,
 912         .num_links = 0,
 913 };
 914
 915 static struct qcom_icc_node xs_sys_tcu_cfg = {
 916         .name = "xs_sys_tcu_cfg",
 917         .id = SM8550_SLAVE_TCU,
 918         .channels = 1,
 919         .buswidth = 8,
 920         .num_links = 0,
 921 };
 922
 923 static struct qcom_icc_node qhs_aoss = {
 924         .name = "qhs_aoss",
 925         .id = SM8550_SLAVE_AOSS,
 926         .channels = 1,
 927         .buswidth = 4,
 928         .num_links = 0,
 929 };
 930
 931 static struct qcom_icc_node qhs_tme_cfg = {
 932         .name = "qhs_tme_cfg",
 933         .id = SM8550_SLAVE_TME_CFG,
 934         .channels = 1,
 935         .buswidth = 4,
 936         .num_links = 0,
 937 };
 938
 939 static struct qcom_icc_node qss_cfg = {
 940         .name = "qss_cfg",
 941         .id = SM8550_SLAVE_CNOC_CFG,
 942         .channels = 1,
 943         .buswidth = 4,
 944         .num_links = 1,
 945         .links = { SM8550_MASTER_CNOC_CFG },
 946 };
 947
 948 static struct qcom_icc_node qss_ddrss_cfg = {
 949         .name = "qss_ddrss_cfg",
 950         .id = SM8550_SLAVE_DDRSS_CFG,
 951         .channels = 1,
 952         .buswidth = 4,
 953         .num_links = 0,
 954 };
 955
 956 static struct qcom_icc_node qxs_boot_imem = {
 957         .name = "qxs_boot_imem",
 958         .id = SM8550_SLAVE_BOOT_IMEM,
 959         .channels = 1,
 960         .buswidth = 8,
 961         .num_links = 0,
 962 };
 963
 964 static struct qcom_icc_node qxs_imem = {
 965         .name = "qxs_imem",
 966         .id = SM8550_SLAVE_IMEM,
 967         .channels = 1,
 968         .buswidth = 8,
 969         .num_links = 0,
 970 };
 971
 972 static struct qcom_icc_node xs_pcie_0 = {
 973         .name = "xs_pcie_0",
 974         .id = SM8550_SLAVE_PCIE_0,
 975         .channels = 1,
 976         .buswidth = 8,
 977         .num_links = 0,
 978 };
 979
 980 static struct qcom_icc_node xs_pcie_1 = {
 981         .name = "xs_pcie_1",
 982         .id = SM8550_SLAVE_PCIE_1,
 983         .channels = 1,
 984         .buswidth = 16,
 985         .num_links = 0,
 986 };
 987
 988 static struct qcom_icc_node qns_gem_noc_cnoc = {
 989         .name = "qns_gem_noc_cnoc",
 990         .id = SM8550_SLAVE_GEM_NOC_CNOC,
 991         .channels = 1,
 992         .buswidth = 16,
 993         .num_links = 1,
 994         .links = { SM8550_MASTER_GEM_NOC_CNOC },
 995 };
 996
 997 static struct qcom_icc_node qns_llcc = {
 998         .name = "qns_llcc",
 999         .id = SM8550_SLAVE_LLCC,
1000         .channels = 4,
1001         .buswidth = 16,
1002         .num_links = 1,
1003         .links = { SM8550_MASTER_LLCC },
1004 };
1005
1006 static struct qcom_icc_node qns_pcie = {
1007         .name = "qns_pcie",
1008         .id = SM8550_SLAVE_MEM_NOC_PCIE_SNOC,
1009         .channels = 1,
1010         .buswidth = 8,
1011         .num_links = 1,
1012         .links = { SM8550_MASTER_GEM_NOC_PCIE_SNOC },
1013 };
1014
1015 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
1016         .name = "qns_lpass_ag_noc_gemnoc",
1017         .id = SM8550_SLAVE_LPASS_GEM_NOC,
1018         .channels = 1,
1019         .buswidth = 16,
1020         .num_links = 1,
1021         .links = { SM8550_MASTER_LPASS_GEM_NOC },
1022 };
1023
1024 static struct qcom_icc_node qns_lpass_aggnoc = {
1025         .name = "qns_lpass_aggnoc",
1026         .id = SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
1027         .channels = 1,
1028         .buswidth = 16,
1029         .num_links = 1,
1030         .links = { SM8550_MASTER_LPIAON_NOC },
1031 };
1032
1033 static struct qcom_icc_node qns_lpi_aon_noc = {
1034         .name = "qns_lpi_aon_noc",
1035         .id = SM8550_SLAVE_LPICX_NOC_LPIAON_NOC,
1036         .channels = 1,
1037         .buswidth = 16,
1038         .num_links = 1,
1039         .links = { SM8550_MASTER_LPASS_LPINOC },
1040 };
1041
1042 static struct qcom_icc_node ebi = {
1043         .name = "ebi",
1044         .id = SM8550_SLAVE_EBI1,
1045         .channels = 4,
1046         .buswidth = 4,
1047         .num_links = 0,
1048 };
1049
1050 static struct qcom_icc_node qns_mem_noc_hf = {
1051         .name = "qns_mem_noc_hf",
1052         .id = SM8550_SLAVE_MNOC_HF_MEM_NOC,
1053         .channels = 2,
1054         .buswidth = 32,
1055         .num_links = 1,
1056         .links = { SM8550_MASTER_MNOC_HF_MEM_NOC },
1057 };
1058
1059 static struct qcom_icc_node qns_mem_noc_sf = {
1060         .name = "qns_mem_noc_sf",
1061         .id = SM8550_SLAVE_MNOC_SF_MEM_NOC,
1062         .channels = 2,
1063         .buswidth = 32,
1064         .num_links = 1,
1065         .links = { SM8550_MASTER_MNOC_SF_MEM_NOC },
1066 };
1067
1068 static struct qcom_icc_node srvc_mnoc = {
1069         .name = "srvc_mnoc",
1070         .id = SM8550_SLAVE_SERVICE_MNOC,
1071         .channels = 1,
1072         .buswidth = 4,
1073         .num_links = 0,
1074 };
1075
1076 static struct qcom_icc_node qns_nsp_gemnoc = {
1077         .name = "qns_nsp_gemnoc",
1078         .id = SM8550_SLAVE_CDSP_MEM_NOC,
1079         .channels = 2,
1080         .buswidth = 32,
1081         .num_links = 1,
1082         .links = { SM8550_MASTER_COMPUTE_NOC },
1083 };
1084
1085 static struct qcom_icc_node qns_pcie_mem_noc = {
1086         .name = "qns_pcie_mem_noc",
1087         .id = SM8550_SLAVE_ANOC_PCIE_GEM_NOC,
1088         .channels = 1,
1089         .buswidth = 16,
1090         .num_links = 1,
1091         .links = { SM8550_MASTER_ANOC_PCIE_GEM_NOC },
1092 };
1093
1094 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1095         .name = "srvc_pcie_aggre_noc",
1096         .id = SM8550_SLAVE_SERVICE_PCIE_ANOC,
1097         .channels = 1,
1098         .buswidth = 4,
1099         .num_links = 0,
1100 };
1101
1102 static struct qcom_icc_node qns_gemnoc_gc = {
1103         .name = "qns_gemnoc_gc",
1104         .id = SM8550_SLAVE_SNOC_GEM_NOC_GC,
1105         .channels = 1,
1106         .buswidth = 8,
1107         .num_links = 1,
1108         .links = { SM8550_MASTER_SNOC_GC_MEM_NOC },
1109 };
1110
1111 static struct qcom_icc_node qns_gemnoc_sf = {
1112         .name = "qns_gemnoc_sf",
1113         .id = SM8550_SLAVE_SNOC_GEM_NOC_SF,
1114         .channels = 1,
1115         .buswidth = 16,
1116         .num_links = 1,
1117         .links = { SM8550_MASTER_SNOC_SF_MEM_NOC },
1118 };
1119
1120 static struct qcom_icc_bcm bcm_acv = {
1121         .name = "ACV",
1122         .enable_mask = 0x8,
1123         .num_nodes = 1,
1124         .nodes = { &ebi },
1125 };
1126
1127 static struct qcom_icc_bcm bcm_ce0 = {
1128         .name = "CE0",
1129         .num_nodes = 1,
1130         .nodes = { &qxm_crypto },
1131 };
1132
1133 static struct qcom_icc_bcm bcm_cn0 = {
1134         .name = "CN0",
1135         .enable_mask = 0x1,
1136         .keepalive = true,
1137         .num_nodes = 54,
1138         .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1139                    &qhs_ahb2phy1, &qhs_apss,
1140                    &qhs_camera_cfg, &qhs_clk_ctl,
1141                    &qhs_cpr_cx, &qhs_cpr_mmcx,
1142                    &qhs_cpr_mxa, &qhs_cpr_mxc,
1143                    &qhs_cpr_nspcx, &qhs_crypto0_cfg,
1144                    &qhs_cx_rdpm, &qhs_gpuss_cfg,
1145                    &qhs_i2c, &qhs_imem_cfg,
1146                    &qhs_ipa, &qhs_ipc_router,
1147                    &qhs_mss_cfg, &qhs_mx_rdpm,
1148                    &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1149                    &qhs_pdm, &qhs_pimem_cfg,
1150                    &qhs_prng, &qhs_qdss_cfg,
1151                    &qhs_qspi, &qhs_qup1,
1152                    &qhs_qup2, &qhs_sdc2,
1153                    &qhs_sdc4, &qhs_spss_cfg,
1154                    &qhs_tcsr, &qhs_tlmm,
1155                    &qhs_ufs_mem_cfg, &qhs_usb3_0,
1156                    &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1157                    &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
1158                    &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
1159                    &xs_qdss_stm, &xs_sys_tcu_cfg,
1160                    &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1161                    &qhs_aoss, &qhs_tme_cfg,
1162                    &qss_cfg, &qss_ddrss_cfg,
1163                    &qxs_boot_imem, &qxs_imem,
1164                    &xs_pcie_0, &xs_pcie_1 },
1165 };
1166
1167 static struct qcom_icc_bcm bcm_cn1 = {
1168         .name = "CN1",
1169         .num_nodes = 1,
1170         .nodes = { &qhs_display_cfg },
1171 };
1172
1173 static struct qcom_icc_bcm bcm_co0 = {
1174         .name = "CO0",
1175         .enable_mask = 0x1,
1176         .num_nodes = 2,
1177         .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1178 };
1179
1180 static struct qcom_icc_bcm bcm_lp0 = {
1181         .name = "LP0",
1182         .num_nodes = 2,
1183         .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1184 };
1185
1186 static struct qcom_icc_bcm bcm_mc0 = {
1187         .name = "MC0",
1188         .keepalive = true,
1189         .num_nodes = 1,
1190         .nodes = { &ebi },
1191 };
1192
1193 static struct qcom_icc_bcm bcm_mm0 = {
1194         .name = "MM0",
1195         .num_nodes = 1,
1196         .nodes = { &qns_mem_noc_hf },
1197 };
1198
1199 static struct qcom_icc_bcm bcm_mm1 = {
1200         .name = "MM1",
1201         .enable_mask = 0x1,
1202         .num_nodes = 8,
1203         .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1204                    &qnm_camnoc_sf, &qnm_vapss_hcp,
1205                    &qnm_video_cv_cpu, &qnm_video_cvp,
1206                    &qnm_video_v_cpu, &qns_mem_noc_sf },
1207 };
1208
1209 static struct qcom_icc_bcm bcm_qup0 = {
1210         .name = "QUP0",
1211         .keepalive = true,
1212         .vote_scale = 1,
1213         .num_nodes = 1,
1214         .nodes = { &qup0_core_slave },
1215 };
1216
1217 static struct qcom_icc_bcm bcm_qup1 = {
1218         .name = "QUP1",
1219         .keepalive = true,
1220         .vote_scale = 1,
1221         .num_nodes = 1,
1222         .nodes = { &qup1_core_slave },
1223 };
1224
1225 static struct qcom_icc_bcm bcm_qup2 = {
1226         .name = "QUP2",
1227         .keepalive = true,
1228         .vote_scale = 1,
1229         .num_nodes = 1,
1230         .nodes = { &qup2_core_slave },
1231 };
1232
1233 static struct qcom_icc_bcm bcm_sh0 = {
1234         .name = "SH0",
1235         .keepalive = true,
1236         .num_nodes = 1,
1237         .nodes = { &qns_llcc },
1238 };
1239
1240 static struct qcom_icc_bcm bcm_sh1 = {
1241         .name = "SH1",
1242         .enable_mask = 0x1,
1243         .num_nodes = 13,
1244         .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1245                    &chm_apps, &qnm_gpu,
1246                    &qnm_mdsp, &qnm_mnoc_hf,
1247                    &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1248                    &qnm_pcie, &qnm_snoc_gc,
1249                    &qnm_snoc_sf, &qns_gem_noc_cnoc,
1250                    &qns_pcie },
1251 };
1252
1253 static struct qcom_icc_bcm bcm_sn0 = {
1254         .name = "SN0",
1255         .keepalive = true,
1256         .num_nodes = 1,
1257         .nodes = { &qns_gemnoc_sf },
1258 };
1259
1260 static struct qcom_icc_bcm bcm_sn1 = {
1261         .name = "SN1",
1262         .enable_mask = 0x1,
1263         .num_nodes = 3,
1264         .nodes = { &qhm_gic, &xm_gic,
1265                    &qns_gemnoc_gc },
1266 };
1267
1268 static struct qcom_icc_bcm bcm_sn2 = {
1269         .name = "SN2",
1270         .num_nodes = 1,
1271         .nodes = { &qnm_aggre1_noc },
1272 };
1273
1274 static struct qcom_icc_bcm bcm_sn3 = {
1275         .name = "SN3",
1276         .num_nodes = 1,
1277         .nodes = { &qnm_aggre2_noc },
1278 };
1279
1280 static struct qcom_icc_bcm bcm_sn7 = {
1281         .name = "SN7",
1282         .num_nodes = 1,
1283         .nodes = { &qns_pcie_mem_noc },
1284 };
1285
1286 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1287 };
1288
1289 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1290         [MASTER_QSPI_0] = &qhm_qspi,
1291         [MASTER_QUP_1] = &qhm_qup1,
1292         [MASTER_SDCC_4] = &xm_sdc4,
1293         [MASTER_UFS_MEM] = &xm_ufs_mem,
1294         [MASTER_USB3_0] = &xm_usb3_0,
1295         [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1296 };
1297
1298 static const struct qcom_icc_desc sm8550_aggre1_noc = {
1299         .nodes = aggre1_noc_nodes,
1300         .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1301         .bcms = aggre1_noc_bcms,
1302         .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1303 };
1304
1305 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1306         &bcm_ce0,
1307 };
1308
1309 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1310         [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1311         [MASTER_QUP_2] = &qhm_qup2,
1312         [MASTER_CRYPTO] = &qxm_crypto,
1313         [MASTER_IPA] = &qxm_ipa,
1314         [MASTER_SP] = &qxm_sp,
1315         [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1316         [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1317         [MASTER_SDCC_2] = &xm_sdc2,
1318         [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1319 };
1320
1321 static const struct qcom_icc_desc sm8550_aggre2_noc = {
1322         .nodes = aggre2_noc_nodes,
1323         .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1324         .bcms = aggre2_noc_bcms,
1325         .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1326 };
1327
1328 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1329         &bcm_qup0,
1330         &bcm_qup1,
1331         &bcm_qup2,
1332 };
1333
1334 static struct qcom_icc_node * const clk_virt_nodes[] = {
1335         [MASTER_QUP_CORE_0] = &qup0_core_master,
1336         [MASTER_QUP_CORE_1] = &qup1_core_master,
1337         [MASTER_QUP_CORE_2] = &qup2_core_master,
1338         [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1339         [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1340         [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1341 };
1342
1343 static const struct qcom_icc_desc sm8550_clk_virt = {
1344         .nodes = clk_virt_nodes,
1345         .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1346         .bcms = clk_virt_bcms,
1347         .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1348 };
1349
1350 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1351         &bcm_cn0,
1352         &bcm_cn1,
1353 };
1354
1355 static struct qcom_icc_node * const config_noc_nodes[] = {
1356         [MASTER_CNOC_CFG] = &qsm_cfg,
1357         [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1358         [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1359         [SLAVE_APPSS] = &qhs_apss,
1360         [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1361         [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1362         [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1363         [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1364         [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1365         [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1366         [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1367         [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1368         [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1369         [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1370         [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1371         [SLAVE_I2C] = &qhs_i2c,
1372         [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1373         [SLAVE_IPA_CFG] = &qhs_ipa,
1374         [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1375         [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1376         [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1377         [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1378         [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1379         [SLAVE_PDM] = &qhs_pdm,
1380         [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1381         [SLAVE_PRNG] = &qhs_prng,
1382         [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1383         [SLAVE_QSPI_0] = &qhs_qspi,
1384         [SLAVE_QUP_1] = &qhs_qup1,
1385         [SLAVE_QUP_2] = &qhs_qup2,
1386         [SLAVE_SDCC_2] = &qhs_sdc2,
1387         [SLAVE_SDCC_4] = &qhs_sdc4,
1388         [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1389         [SLAVE_TCSR] = &qhs_tcsr,
1390         [SLAVE_TLMM] = &qhs_tlmm,
1391         [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1392         [SLAVE_USB3_0] = &qhs_usb3_0,
1393         [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1394         [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1395         [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
1396         [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1397         [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
1398         [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1399         [SLAVE_QDSS_STM] = &xs_qdss_stm,
1400         [SLAVE_TCU] = &xs_sys_tcu_cfg,
1401 };
1402
1403 static const struct qcom_icc_desc sm8550_config_noc = {
1404         .nodes = config_noc_nodes,
1405         .num_nodes = ARRAY_SIZE(config_noc_nodes),
1406         .bcms = config_noc_bcms,
1407         .num_bcms = ARRAY_SIZE(config_noc_bcms),
1408 };
1409
1410 static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1411         &bcm_cn0,
1412 };
1413
1414 static struct qcom_icc_node * const cnoc_main_nodes[] = {
1415         [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1416         [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1417         [SLAVE_AOSS] = &qhs_aoss,
1418         [SLAVE_TME_CFG] = &qhs_tme_cfg,
1419         [SLAVE_CNOC_CFG] = &qss_cfg,
1420         [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1421         [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1422         [SLAVE_IMEM] = &qxs_imem,
1423         [SLAVE_PCIE_0] = &xs_pcie_0,
1424         [SLAVE_PCIE_1] = &xs_pcie_1,
1425 };
1426
1427 static const struct qcom_icc_desc sm8550_cnoc_main = {
1428         .nodes = cnoc_main_nodes,
1429         .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1430         .bcms = cnoc_main_bcms,
1431         .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1432 };
1433
1434 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1435         &bcm_sh0,
1436         &bcm_sh1,
1437 };
1438
1439 static struct qcom_icc_node * const gem_noc_nodes[] = {
1440         [MASTER_GPU_TCU] = &alm_gpu_tcu,
1441         [MASTER_SYS_TCU] = &alm_sys_tcu,
1442         [MASTER_APPSS_PROC] = &chm_apps,
1443         [MASTER_GFX3D] = &qnm_gpu,
1444         [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1445         [MASTER_MSS_PROC] = &qnm_mdsp,
1446         [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1447         [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1448         [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1449         [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1450         [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1451         [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1452         [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1453         [SLAVE_LLCC] = &qns_llcc,
1454         [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1455 };
1456
1457 static const struct qcom_icc_desc sm8550_gem_noc = {
1458         .nodes = gem_noc_nodes,
1459         .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1460         .bcms = gem_noc_bcms,
1461         .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1462 };
1463
1464 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1465 };
1466
1467 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1468         [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1469         [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1470 };
1471
1472 static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
1473         .nodes = lpass_ag_noc_nodes,
1474         .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1475         .bcms = lpass_ag_noc_bcms,
1476         .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1477 };
1478
1479 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1480         &bcm_lp0,
1481 };
1482
1483 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1484         [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1485         [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1486 };
1487
1488 static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
1489         .nodes = lpass_lpiaon_noc_nodes,
1490         .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1491         .bcms = lpass_lpiaon_noc_bcms,
1492         .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1493 };
1494
1495 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = {
1496 };
1497
1498 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1499         [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim,
1500         [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1501 };
1502
1503 static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
1504         .nodes = lpass_lpicx_noc_nodes,
1505         .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1506         .bcms = lpass_lpicx_noc_bcms,
1507         .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms),
1508 };
1509
1510 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1511         &bcm_acv,
1512         &bcm_mc0,
1513 };
1514
1515 static struct qcom_icc_node * const mc_virt_nodes[] = {
1516         [MASTER_LLCC] = &llcc_mc,
1517         [SLAVE_EBI1] = &ebi,
1518 };
1519
1520 static const struct qcom_icc_desc sm8550_mc_virt = {
1521         .nodes = mc_virt_nodes,
1522         .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1523         .bcms = mc_virt_bcms,
1524         .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1525 };
1526
1527 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1528         &bcm_mm0,
1529         &bcm_mm1,
1530 };
1531
1532 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1533         [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1534         [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1535         [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1536         [MASTER_MDP] = &qnm_mdp,
1537         [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1538         [MASTER_VIDEO] = &qnm_video,
1539         [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1540         [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1541         [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1542         [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
1543         [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1544         [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1545         [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1546 };
1547
1548 static const struct qcom_icc_desc sm8550_mmss_noc = {
1549         .nodes = mmss_noc_nodes,
1550         .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1551         .bcms = mmss_noc_bcms,
1552         .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1553 };
1554
1555 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1556         &bcm_co0,
1557 };
1558
1559 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1560         [MASTER_CDSP_PROC] = &qxm_nsp,
1561         [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1562 };
1563
1564 static const struct qcom_icc_desc sm8550_nsp_noc = {
1565         .nodes = nsp_noc_nodes,
1566         .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1567         .bcms = nsp_noc_bcms,
1568         .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1569 };
1570
1571 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1572         &bcm_sn7,
1573 };
1574
1575 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1576         [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
1577         [MASTER_PCIE_0] = &xm_pcie3_0,
1578         [MASTER_PCIE_1] = &xm_pcie3_1,
1579         [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1580         [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1581 };
1582
1583 static const struct qcom_icc_desc sm8550_pcie_anoc = {
1584         .nodes = pcie_anoc_nodes,
1585         .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1586         .bcms = pcie_anoc_bcms,
1587         .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1588 };
1589
1590 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1591         &bcm_sn0,
1592         &bcm_sn1,
1593         &bcm_sn2,
1594         &bcm_sn3,
1595 };
1596
1597 static struct qcom_icc_node * const system_noc_nodes[] = {
1598         [MASTER_GIC_AHB] = &qhm_gic,
1599         [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1600         [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1601         [MASTER_GIC] = &xm_gic,
1602         [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1603         [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1604 };
1605
1606 static const struct qcom_icc_desc sm8550_system_noc = {
1607         .nodes = system_noc_nodes,
1608         .num_nodes = ARRAY_SIZE(system_noc_nodes),
1609         .bcms = system_noc_bcms,
1610         .num_bcms = ARRAY_SIZE(system_noc_bcms),
1611 };
1612
1613 static const struct of_device_id qnoc_of_match[] = {
1614         { .compatible = "qcom,sm8550-aggre1-noc",
1615           .data = &sm8550_aggre1_noc},
1616         { .compatible = "qcom,sm8550-aggre2-noc",
1617           .data = &sm8550_aggre2_noc},
1618         { .compatible = "qcom,sm8550-clk-virt",
1619           .data = &sm8550_clk_virt},
1620         { .compatible = "qcom,sm8550-config-noc",
1621           .data = &sm8550_config_noc},
1622         { .compatible = "qcom,sm8550-cnoc-main",
1623           .data = &sm8550_cnoc_main},
1624         { .compatible = "qcom,sm8550-gem-noc",
1625           .data = &sm8550_gem_noc},
1626         { .compatible = "qcom,sm8550-lpass-ag-noc",
1627           .data = &sm8550_lpass_ag_noc},
1628         { .compatible = "qcom,sm8550-lpass-lpiaon-noc",
1629           .data = &sm8550_lpass_lpiaon_noc},
1630         { .compatible = "qcom,sm8550-lpass-lpicx-noc",
1631           .data = &sm8550_lpass_lpicx_noc},
1632         { .compatible = "qcom,sm8550-mc-virt",
1633           .data = &sm8550_mc_virt},
1634         { .compatible = "qcom,sm8550-mmss-noc",
1635           .data = &sm8550_mmss_noc},
1636         { .compatible = "qcom,sm8550-nsp-noc",
1637           .data = &sm8550_nsp_noc},
1638         { .compatible = "qcom,sm8550-pcie-anoc",
1639           .data = &sm8550_pcie_anoc},
1640         { .compatible = "qcom,sm8550-system-noc",
1641           .data = &sm8550_system_noc},
1642         { }
1643 };
1644 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1645
1646 static struct platform_driver qnoc_driver = {
1647         .probe = qcom_icc_rpmh_probe,
1648         .remove_new = qcom_icc_rpmh_remove,
1649         .driver = {
1650                 .name = "qnoc-sm8550",
1651                 .of_match_table = qnoc_of_match,
1652                 .sync_state = icc_sync_state,
1653         },
1654 };
1655
1656 static int __init qnoc_driver_init(void)
1657 {
1658         return platform_driver_register(&qnoc_driver);
1659 }
1660 core_initcall(qnoc_driver_init);
1661
1662 static void __exit qnoc_driver_exit(void)
1663 {
1664         platform_driver_unregister(&qnoc_driver);
1665 }
1666 module_exit(qnoc_driver_exit);
1667
1668 MODULE_DESCRIPTION("sm8550 NoC driver");
1669 MODULE_LICENSE("GPL");