drivers/interconnect/qcom/sm8150.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  *
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/interconnect.h>
   9 #include <linux/interconnect-provider.h>
  10 #include <linux/module.h>
  11 #include <linux/of_platform.h>
  12 #include <dt-bindings/interconnect/qcom,sm8150.h>
  13
  14 #include "bcm-voter.h"
  15 #include "icc-rpmh.h"
  16 #include "sm8150.h"
  17
  18 DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC);
  19 DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV);
  20 DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV);
  21 DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV);
  22 DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV);
  23 DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV);
  24 DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC);
  25 DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV);
  26 DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV);
  27 DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV);
  28 DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV);
  29 DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV);
  30 DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV);
  31 DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV);
  32 DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV);
  33 DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV);
  34 DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
  35 DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
  36 DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV);
  37 DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV);
  38 DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV);
  39 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
  40 DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
  41 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
  42 DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC);
  43 DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC);
  44 DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
  45 DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
  46 DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG);
  47 DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  48 DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  49 DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  50 DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG);
  51 DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  52 DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  53 DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC);
  54 DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  55 DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  56 DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
  57 DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
  58 DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
  59 DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
  60 DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
  61 DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
  62 DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
  63 DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
  64 DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  65 DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
  66 DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
  67 DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  68 DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  69 DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  70 DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  71 DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC);
  72 DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM);
  73 DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
  74 DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
  75 DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
  76 DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
  77 DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS);
  78 DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4);
  79 DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS);
  80 DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC);
  81 DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4);
  82 DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32);
  83 DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC);
  84 DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG);
  85 DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG);
  86 DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4);
  87 DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4);
  88 DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4);
  89 DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4);
  90 DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4);
  91 DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4);
  92 DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4);
  93 DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4);
  94 DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4);
  95 DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4);
  96 DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC);
  97 DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4);
  98 DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4);
  99 DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4);
 100 DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8);
 101 DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4);
 102 DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4);
 103 DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG);
 104 DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4);
 105 DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4);
 106 DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4);
 107 DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4);
 108 DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4);
 109 DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4);
 110 DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4);
 111 DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4);
 112 DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4);
 113 DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4);
 114 DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4);
 115 DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4);
 116 DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4);
 117 DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG);
 118 DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4);
 119 DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4);
 120 DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4);
 121 DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4);
 122 DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4);
 123 DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4);
 124 DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4);
 125 DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4);
 126 DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4);
 127 DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4);
 128 DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4);
 129 DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4);
 130 DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4);
 131 DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4);
 132 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4);
 133 DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC);
 134 DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4);
 135 DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4);
 136 DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG);
 137 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
 138 DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
 139 DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
 140 DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
 141 DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
 142 DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
 143 DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
 144 DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
 145 DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
 146 DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4);
 147 DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8);
 148 DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS);
 149 DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC);
 150 DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC);
 151 DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8);
 152 DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8);
 153 DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4);
 154 DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8);
 155 DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8);
 156 DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4);
 157 DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8);
 158
 159 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
 160 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
 161 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
 162 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
 163 DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
 164 DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
 165 DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
 166 DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
 167 DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
 168 DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
 169 DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
 170 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
 171 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
 172 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
 173 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
 174 DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
 175 DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
 176 DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
 177 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
 178 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
 179 DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
 180 DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
 181 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
 182 DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
 183 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
 184 DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
 185 DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
 186 DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
 187 DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);
 188
 189 static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
 190         &bcm_qup0,
 191         &bcm_sn3,
 192 };
 193
 194 static struct qcom_icc_node *aggre1_noc_nodes[] = {
 195         [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
 196         [MASTER_QUP_0] = &qhm_qup0,
 197         [MASTER_EMAC] = &xm_emac,
 198         [MASTER_UFS_MEM] = &xm_ufs_mem,
 199         [MASTER_USB3] = &xm_usb3_0,
 200         [MASTER_USB3_1] = &xm_usb3_1,
 201         [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
 202         [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
 203 };
 204
 205 static struct qcom_icc_desc sm8150_aggre1_noc = {
 206         .nodes = aggre1_noc_nodes,
 207         .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
 208         .bcms = aggre1_noc_bcms,
 209         .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
 210 };
 211
 212 static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
 213         &bcm_ce0,
 214         &bcm_qup0,
 215         &bcm_sn14,
 216         &bcm_sn3,
 217 };
 218
 219 static struct qcom_icc_node *aggre2_noc_nodes[] = {
 220         [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
 221         [MASTER_QDSS_BAM] = &qhm_qdss_bam,
 222         [MASTER_QSPI] = &qhm_qspi,
 223         [MASTER_QUP_1] = &qhm_qup1,
 224         [MASTER_QUP_2] = &qhm_qup2,
 225         [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb,
 226         [MASTER_TSIF] = &qhm_tsif,
 227         [MASTER_CNOC_A2NOC] = &qnm_cnoc,
 228         [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
 229         [MASTER_IPA] = &qxm_ipa,
 230         [MASTER_PCIE] = &xm_pcie3_0,
 231         [MASTER_PCIE_1] = &xm_pcie3_1,
 232         [MASTER_QDSS_ETR] = &xm_qdss_etr,
 233         [MASTER_SDCC_2] = &xm_sdc2,
 234         [MASTER_SDCC_4] = &xm_sdc4,
 235         [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
 236         [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
 237         [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
 238 };
 239
 240 static struct qcom_icc_desc sm8150_aggre2_noc = {
 241         .nodes = aggre2_noc_nodes,
 242         .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
 243         .bcms = aggre2_noc_bcms,
 244         .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
 245 };
 246
 247 static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
 248         &bcm_mm1,
 249 };
 250
 251 static struct qcom_icc_node *camnoc_virt_nodes[] = {
 252         [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
 253         [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
 254         [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
 255         [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
 256 };
 257
 258 static struct qcom_icc_desc sm8150_camnoc_virt = {
 259         .nodes = camnoc_virt_nodes,
 260         .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
 261         .bcms = camnoc_virt_bcms,
 262         .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
 263 };
 264
 265 static struct qcom_icc_bcm *compute_noc_bcms[] = {
 266         &bcm_co0,
 267         &bcm_co1,
 268 };
 269
 270 static struct qcom_icc_node *compute_noc_nodes[] = {
 271         [MASTER_NPU] = &qnm_npu,
 272         [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
 273 };
 274
 275 static struct qcom_icc_desc sm8150_compute_noc = {
 276         .nodes = compute_noc_nodes,
 277         .num_nodes = ARRAY_SIZE(compute_noc_nodes),
 278         .bcms = compute_noc_bcms,
 279         .num_bcms = ARRAY_SIZE(compute_noc_bcms),
 280 };
 281
 282 static struct qcom_icc_bcm *config_noc_bcms[] = {
 283         &bcm_cn0,
 284 };
 285
 286 static struct qcom_icc_node *config_noc_nodes[] = {
 287         [MASTER_SPDM] = &qhm_spdm,
 288         [SNOC_CNOC_MAS] = &qnm_snoc,
 289         [MASTER_QDSS_DAP] = &xm_qdss_dap,
 290         [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
 291         [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
 292         [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
 293         [SLAVE_AOP] = &qhs_aop,
 294         [SLAVE_AOSS] = &qhs_aoss,
 295         [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
 296         [SLAVE_CLK_CTL] = &qhs_clk_ctl,
 297         [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
 298         [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
 299         [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
 300         [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
 301         [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
 302         [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
 303         [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
 304         [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
 305         [SLAVE_GLM] = &qhs_glm,
 306         [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
 307         [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
 308         [SLAVE_IPA_CFG] = &qhs_ipa,
 309         [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
 310         [SLAVE_NPU_CFG] = &qhs_npu_cfg,
 311         [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
 312         [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
 313         [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north,
 314         [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
 315         [SLAVE_PRNG] = &qhs_prng,
 316         [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
 317         [SLAVE_QSPI] = &qhs_qspi,
 318         [SLAVE_QUP_2] = &qhs_qupv3_east,
 319         [SLAVE_QUP_1] = &qhs_qupv3_north,
 320         [SLAVE_QUP_0] = &qhs_qupv3_south,
 321         [SLAVE_SDCC_2] = &qhs_sdc2,
 322         [SLAVE_SDCC_4] = &qhs_sdc4,
 323         [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
 324         [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
 325         [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
 326         [SLAVE_SSC_CFG] = &qhs_ssc_cfg,
 327         [SLAVE_TCSR] = &qhs_tcsr,
 328         [SLAVE_TLMM_EAST] = &qhs_tlmm_east,
 329         [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
 330         [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
 331         [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
 332         [SLAVE_TSIF] = &qhs_tsif,
 333         [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
 334         [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
 335         [SLAVE_USB3] = &qhs_usb3_0,
 336         [SLAVE_USB3_1] = &qhs_usb3_1,
 337         [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
 338         [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
 339         [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
 340         [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
 341 };
 342
 343 static struct qcom_icc_desc sm8150_config_noc = {
 344         .nodes = config_noc_nodes,
 345         .num_nodes = ARRAY_SIZE(config_noc_nodes),
 346         .bcms = config_noc_bcms,
 347         .num_bcms = ARRAY_SIZE(config_noc_bcms),
 348 };
 349
 350 static struct qcom_icc_bcm *dc_noc_bcms[] = {
 351 };
 352
 353 static struct qcom_icc_node *dc_noc_nodes[] = {
 354         [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
 355         [SLAVE_LLCC_CFG] = &qhs_llcc,
 356         [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
 357 };
 358
 359 static struct qcom_icc_desc sm8150_dc_noc = {
 360         .nodes = dc_noc_nodes,
 361         .num_nodes = ARRAY_SIZE(dc_noc_nodes),
 362         .bcms = dc_noc_bcms,
 363         .num_bcms = ARRAY_SIZE(dc_noc_bcms),
 364 };
 365
 366 static struct qcom_icc_bcm *gem_noc_bcms[] = {
 367         &bcm_sh0,
 368         &bcm_sh2,
 369         &bcm_sh3,
 370         &bcm_sh4,
 371         &bcm_sh5,
 372 };
 373
 374 static struct qcom_icc_node *gem_noc_nodes[] = {
 375         [MASTER_AMPSS_M0] = &acm_apps,
 376         [MASTER_GPU_TCU] = &acm_gpu_tcu,
 377         [MASTER_SYS_TCU] = &acm_sys_tcu,
 378         [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
 379         [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
 380         [MASTER_GRAPHICS_3D] = &qnm_gpu,
 381         [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
 382         [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
 383         [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
 384         [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
 385         [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
 386         [MASTER_ECC] = &qxm_ecc,
 387         [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
 388         [SLAVE_ECC] = &qns_ecc,
 389         [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
 390         [SLAVE_LLCC] = &qns_llcc,
 391         [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
 392 };
 393
 394 static struct qcom_icc_desc sm8150_gem_noc = {
 395         .nodes = gem_noc_nodes,
 396         .num_nodes = ARRAY_SIZE(gem_noc_nodes),
 397         .bcms = gem_noc_bcms,
 398         .num_bcms = ARRAY_SIZE(gem_noc_bcms),
 399 };
 400
 401 static struct qcom_icc_bcm *ipa_virt_bcms[] = {
 402         &bcm_ip0,
 403 };
 404
 405 static struct qcom_icc_node *ipa_virt_nodes[] = {
 406         [MASTER_IPA_CORE] = &ipa_core_master,
 407         [SLAVE_IPA_CORE] = &ipa_core_slave,
 408 };
 409
 410 static struct qcom_icc_desc sm8150_ipa_virt = {
 411         .nodes = ipa_virt_nodes,
 412         .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
 413         .bcms = ipa_virt_bcms,
 414         .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
 415 };
 416
 417 static struct qcom_icc_bcm *mc_virt_bcms[] = {
 418         &bcm_acv,
 419         &bcm_mc0,
 420 };
 421
 422 static struct qcom_icc_node *mc_virt_nodes[] = {
 423         [MASTER_LLCC] = &llcc_mc,
 424         [SLAVE_EBI_CH0] = &ebi,
 425 };
 426
 427 static struct qcom_icc_desc sm8150_mc_virt = {
 428         .nodes = mc_virt_nodes,
 429         .num_nodes = ARRAY_SIZE(mc_virt_nodes),
 430         .bcms = mc_virt_bcms,
 431         .num_bcms = ARRAY_SIZE(mc_virt_bcms),
 432 };
 433
 434 static struct qcom_icc_bcm *mmss_noc_bcms[] = {
 435         &bcm_mm0,
 436         &bcm_mm1,
 437         &bcm_mm2,
 438         &bcm_mm3,
 439 };
 440
 441 static struct qcom_icc_node *mmss_noc_nodes[] = {
 442         [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
 443         [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
 444         [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
 445         [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
 446         [MASTER_MDP_PORT0] = &qxm_mdp0,
 447         [MASTER_MDP_PORT1] = &qxm_mdp1,
 448         [MASTER_ROTATOR] = &qxm_rot,
 449         [MASTER_VIDEO_P0] = &qxm_venus0,
 450         [MASTER_VIDEO_P1] = &qxm_venus1,
 451         [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
 452         [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
 453         [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
 454         [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
 455 };
 456
 457 static struct qcom_icc_desc sm8150_mmss_noc = {
 458         .nodes = mmss_noc_nodes,
 459         .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
 460         .bcms = mmss_noc_bcms,
 461         .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
 462 };
 463
 464 static struct qcom_icc_bcm *system_noc_bcms[] = {
 465         &bcm_sn0,
 466         &bcm_sn1,
 467         &bcm_sn11,
 468         &bcm_sn12,
 469         &bcm_sn15,
 470         &bcm_sn2,
 471         &bcm_sn3,
 472         &bcm_sn4,
 473         &bcm_sn5,
 474         &bcm_sn8,
 475         &bcm_sn9,
 476 };
 477
 478 static struct qcom_icc_node *system_noc_nodes[] = {
 479         [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
 480         [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
 481         [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
 482         [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
 483         [MASTER_PIMEM] = &qxm_pimem,
 484         [MASTER_GIC] = &xm_gic,
 485         [SLAVE_APPSS] = &qhs_apss,
 486         [SNOC_CNOC_SLV] = &qns_cnoc,
 487         [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
 488         [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
 489         [SLAVE_OCIMEM] = &qxs_imem,
 490         [SLAVE_PIMEM] = &qxs_pimem,
 491         [SLAVE_SERVICE_SNOC] = &srvc_snoc,
 492         [SLAVE_PCIE_0] = &xs_pcie_0,
 493         [SLAVE_PCIE_1] = &xs_pcie_1,
 494         [SLAVE_QDSS_STM] = &xs_qdss_stm,
 495         [SLAVE_TCU] = &xs_sys_tcu_cfg,
 496 };
 497
 498 static struct qcom_icc_desc sm8150_system_noc = {
 499         .nodes = system_noc_nodes,
 500         .num_nodes = ARRAY_SIZE(system_noc_nodes),
 501         .bcms = system_noc_bcms,
 502         .num_bcms = ARRAY_SIZE(system_noc_bcms),
 503 };
 504
 505 static int qnoc_probe(struct platform_device *pdev)
 506 {
 507         const struct qcom_icc_desc *desc;
 508         struct icc_onecell_data *data;
 509         struct icc_provider *provider;
 510         struct qcom_icc_node **qnodes;
 511         struct qcom_icc_provider *qp;
 512         struct icc_node *node;
 513         size_t num_nodes, i;
 514         int ret;
 515
 516         desc = device_get_match_data(&pdev->dev);
 517         if (!desc)
 518                 return -EINVAL;
 519
 520         qnodes = desc->nodes;
 521         num_nodes = desc->num_nodes;
 522
 523         qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
 524         if (!qp)
 525                 return -ENOMEM;
 526
 527         data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
 528         if (!data)
 529                 return -ENOMEM;
 530
 531         provider = &qp->provider;
 532         provider->dev = &pdev->dev;
 533         provider->set = qcom_icc_set;
 534         provider->pre_aggregate = qcom_icc_pre_aggregate;
 535         provider->aggregate = qcom_icc_aggregate;
 536         provider->xlate = of_icc_xlate_onecell;
 537         INIT_LIST_HEAD(&provider->nodes);
 538         provider->data = data;
 539
 540         qp->dev = &pdev->dev;
 541         qp->bcms = desc->bcms;
 542         qp->num_bcms = desc->num_bcms;
 543
 544         qp->voter = of_bcm_voter_get(qp->dev, NULL);
 545         if (IS_ERR(qp->voter))
 546                 return PTR_ERR(qp->voter);
 547
 548         ret = icc_provider_add(provider);
 549         if (ret) {
 550                 dev_err(&pdev->dev, "error adding interconnect provider\n");
 551                 return ret;
 552         }
 553
 554         for (i = 0; i < qp->num_bcms; i++)
 555                 qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
 556
 557         for (i = 0; i < num_nodes; i++) {
 558                 size_t j;
 559
 560                 if (!qnodes[i])
 561                         continue;
 562
 563                 node = icc_node_create(qnodes[i]->id);
 564                 if (IS_ERR(node)) {
 565                         ret = PTR_ERR(node);
 566                         goto err;
 567                 }
 568
 569                 node->name = qnodes[i]->name;
 570                 node->data = qnodes[i];
 571                 icc_node_add(node, provider);
 572
 573                 for (j = 0; j < qnodes[i]->num_links; j++)
 574                         icc_link_create(node, qnodes[i]->links[j]);
 575
 576                 data->nodes[i] = node;
 577         }
 578         data->num_nodes = num_nodes;
 579
 580         platform_set_drvdata(pdev, qp);
 581
 582         return 0;
 583 err:
 584         icc_nodes_remove(provider);
 585         icc_provider_del(provider);
 586         return ret;
 587 }
 588
 589 static int qnoc_remove(struct platform_device *pdev)
 590 {
 591         struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
 592
 593         icc_nodes_remove(&qp->provider);
 594         return icc_provider_del(&qp->provider);
 595 }
 596
 597 static const struct of_device_id qnoc_of_match[] = {
 598         { .compatible = "qcom,sm8150-aggre1-noc",
 599           .data = &sm8150_aggre1_noc},
 600         { .compatible = "qcom,sm8150-aggre2-noc",
 601           .data = &sm8150_aggre2_noc},
 602         { .compatible = "qcom,sm8150-camnoc-virt",
 603           .data = &sm8150_camnoc_virt},
 604         { .compatible = "qcom,sm8150-compute-noc",
 605           .data = &sm8150_compute_noc},
 606         { .compatible = "qcom,sm8150-config-noc",
 607           .data = &sm8150_config_noc},
 608         { .compatible = "qcom,sm8150-dc-noc",
 609           .data = &sm8150_dc_noc},
 610         { .compatible = "qcom,sm8150-gem-noc",
 611           .data = &sm8150_gem_noc},
 612         { .compatible = "qcom,sm8150-ipa-virt",
 613           .data = &sm8150_ipa_virt},
 614         { .compatible = "qcom,sm8150-mc-virt",
 615           .data = &sm8150_mc_virt},
 616         { .compatible = "qcom,sm8150-mmss-noc",
 617           .data = &sm8150_mmss_noc},
 618         { .compatible = "qcom,sm8150-system-noc",
 619           .data = &sm8150_system_noc},
 620         { }
 621 };
 622 MODULE_DEVICE_TABLE(of, qnoc_of_match);
 623
 624 static struct platform_driver qnoc_driver = {
 625         .probe = qnoc_probe,
 626         .remove = qnoc_remove,
 627         .driver = {
 628                 .name = "qnoc-sm8150",
 629                 .of_match_table = qnoc_of_match,
 630                 .sync_state = icc_sync_state,
 631         },
 632 };
 633 module_platform_driver(qnoc_driver);
 634
 635 MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver");
 636 MODULE_LICENSE("GPL v2");