drivers/interconnect/qcom/sdm660.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver
   4  * Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
   5  */
   6
   7 #include <dt-bindings/interconnect/qcom,sdm660.h>
   8 #include <linux/clk.h>
   9 #include <linux/device.h>
  10 #include <linux/interconnect-provider.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/regmap.h>
  17 #include <linux/slab.h>
  18
  19 #include "smd-rpm.h"
  20
  21 #define RPM_BUS_MASTER_REQ      0x73616d62
  22 #define RPM_BUS_SLAVE_REQ       0x766c7362
  23
  24 /* BIMC QoS */
  25 #define M_BKE_REG_BASE(n)               (0x300 + (0x4000 * n))
  26 #define M_BKE_EN_ADDR(n)                (M_BKE_REG_BASE(n))
  27 #define M_BKE_HEALTH_CFG_ADDR(i, n)     (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i))
  28
  29 #define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000
  30 #define M_BKE_HEALTH_CFG_AREQPRIO_MASK  0x300
  31 #define M_BKE_HEALTH_CFG_PRIOLVL_MASK   0x3
  32 #define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8
  33 #define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f
  34
  35 #define M_BKE_EN_EN_BMASK               0x1
  36
  37 /* Valid for both NoC and BIMC */
  38 #define NOC_QOS_MODE_FIXED              0x0
  39 #define NOC_QOS_MODE_LIMITER            0x1
  40 #define NOC_QOS_MODE_BYPASS             0x2
  41
  42 /* NoC QoS */
  43 #define NOC_PERM_MODE_FIXED             1
  44 #define NOC_PERM_MODE_BYPASS            (1 << NOC_QOS_MODE_BYPASS)
  45
  46 #define NOC_QOS_PRIORITYn_ADDR(n)       (0x8 + (n * 0x1000))
  47 #define NOC_QOS_PRIORITY_MASK           0xf
  48 #define NOC_QOS_PRIORITY_P1_SHIFT       0x2
  49 #define NOC_QOS_PRIORITY_P0_SHIFT       0x3
  50
  51 #define NOC_QOS_MODEn_ADDR(n)           (0xc + (n * 0x1000))
  52 #define NOC_QOS_MODEn_MASK              0x3
  53
  54 enum {
  55         SDM660_MASTER_IPA = 1,
  56         SDM660_MASTER_CNOC_A2NOC,
  57         SDM660_MASTER_SDCC_1,
  58         SDM660_MASTER_SDCC_2,
  59         SDM660_MASTER_BLSP_1,
  60         SDM660_MASTER_BLSP_2,
  61         SDM660_MASTER_UFS,
  62         SDM660_MASTER_USB_HS,
  63         SDM660_MASTER_USB3,
  64         SDM660_MASTER_CRYPTO_C0,
  65         SDM660_MASTER_GNOC_BIMC,
  66         SDM660_MASTER_OXILI,
  67         SDM660_MASTER_MNOC_BIMC,
  68         SDM660_MASTER_SNOC_BIMC,
  69         SDM660_MASTER_PIMEM,
  70         SDM660_MASTER_SNOC_CNOC,
  71         SDM660_MASTER_QDSS_DAP,
  72         SDM660_MASTER_APPS_PROC,
  73         SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
  74         SDM660_MASTER_CNOC_MNOC_CFG,
  75         SDM660_MASTER_CPP,
  76         SDM660_MASTER_JPEG,
  77         SDM660_MASTER_MDP_P0,
  78         SDM660_MASTER_MDP_P1,
  79         SDM660_MASTER_VENUS,
  80         SDM660_MASTER_VFE,
  81         SDM660_MASTER_QDSS_ETR,
  82         SDM660_MASTER_QDSS_BAM,
  83         SDM660_MASTER_SNOC_CFG,
  84         SDM660_MASTER_BIMC_SNOC,
  85         SDM660_MASTER_A2NOC_SNOC,
  86         SDM660_MASTER_GNOC_SNOC,
  87
  88         SDM660_SLAVE_A2NOC_SNOC,
  89         SDM660_SLAVE_EBI,
  90         SDM660_SLAVE_HMSS_L3,
  91         SDM660_SLAVE_BIMC_SNOC,
  92         SDM660_SLAVE_CNOC_A2NOC,
  93         SDM660_SLAVE_MPM,
  94         SDM660_SLAVE_PMIC_ARB,
  95         SDM660_SLAVE_TLMM_NORTH,
  96         SDM660_SLAVE_TCSR,
  97         SDM660_SLAVE_PIMEM_CFG,
  98         SDM660_SLAVE_IMEM_CFG,
  99         SDM660_SLAVE_MESSAGE_RAM,
 100         SDM660_SLAVE_GLM,
 101         SDM660_SLAVE_BIMC_CFG,
 102         SDM660_SLAVE_PRNG,
 103         SDM660_SLAVE_SPDM,
 104         SDM660_SLAVE_QDSS_CFG,
 105         SDM660_SLAVE_CNOC_MNOC_CFG,
 106         SDM660_SLAVE_SNOC_CFG,
 107         SDM660_SLAVE_QM_CFG,
 108         SDM660_SLAVE_CLK_CTL,
 109         SDM660_SLAVE_MSS_CFG,
 110         SDM660_SLAVE_TLMM_SOUTH,
 111         SDM660_SLAVE_UFS_CFG,
 112         SDM660_SLAVE_A2NOC_CFG,
 113         SDM660_SLAVE_A2NOC_SMMU_CFG,
 114         SDM660_SLAVE_GPUSS_CFG,
 115         SDM660_SLAVE_AHB2PHY,
 116         SDM660_SLAVE_BLSP_1,
 117         SDM660_SLAVE_SDCC_1,
 118         SDM660_SLAVE_SDCC_2,
 119         SDM660_SLAVE_TLMM_CENTER,
 120         SDM660_SLAVE_BLSP_2,
 121         SDM660_SLAVE_PDM,
 122         SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
 123         SDM660_SLAVE_USB_HS,
 124         SDM660_SLAVE_USB3_0,
 125         SDM660_SLAVE_SRVC_CNOC,
 126         SDM660_SLAVE_GNOC_BIMC,
 127         SDM660_SLAVE_GNOC_SNOC,
 128         SDM660_SLAVE_CAMERA_CFG,
 129         SDM660_SLAVE_CAMERA_THROTTLE_CFG,
 130         SDM660_SLAVE_MISC_CFG,
 131         SDM660_SLAVE_VENUS_THROTTLE_CFG,
 132         SDM660_SLAVE_VENUS_CFG,
 133         SDM660_SLAVE_MMSS_CLK_XPU_CFG,
 134         SDM660_SLAVE_MMSS_CLK_CFG,
 135         SDM660_SLAVE_MNOC_MPU_CFG,
 136         SDM660_SLAVE_DISPLAY_CFG,
 137         SDM660_SLAVE_CSI_PHY_CFG,
 138         SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
 139         SDM660_SLAVE_SMMU_CFG,
 140         SDM660_SLAVE_MNOC_BIMC,
 141         SDM660_SLAVE_SRVC_MNOC,
 142         SDM660_SLAVE_HMSS,
 143         SDM660_SLAVE_LPASS,
 144         SDM660_SLAVE_WLAN,
 145         SDM660_SLAVE_CDSP,
 146         SDM660_SLAVE_IPA,
 147         SDM660_SLAVE_SNOC_BIMC,
 148         SDM660_SLAVE_SNOC_CNOC,
 149         SDM660_SLAVE_IMEM,
 150         SDM660_SLAVE_PIMEM,
 151         SDM660_SLAVE_QDSS_STM,
 152         SDM660_SLAVE_SRVC_SNOC,
 153
 154         SDM660_A2NOC,
 155         SDM660_BIMC,
 156         SDM660_CNOC,
 157         SDM660_GNOC,
 158         SDM660_MNOC,
 159         SDM660_SNOC,
 160 };
 161
 162 #define to_qcom_provider(_provider) \
 163         container_of(_provider, struct qcom_icc_provider, provider)
 164
 165 static const struct clk_bulk_data bus_clocks[] = {
 166         { .id = "bus" },
 167         { .id = "bus_a" },
 168 };
 169
 170 static const struct clk_bulk_data bus_mm_clocks[] = {
 171         { .id = "bus" },
 172         { .id = "bus_a" },
 173         { .id = "iface" },
 174 };
 175
 176 /**
 177  * struct qcom_icc_provider - Qualcomm specific interconnect provider
 178  * @provider: generic interconnect provider
 179  * @bus_clks: the clk_bulk_data table of bus clocks
 180  * @num_clks: the total number of clk_bulk_data entries
 181  * @is_bimc_node: indicates whether to use bimc specific setting
 182  * @regmap: regmap for QoS registers read/write access
 183  * @mmio: NoC base iospace
 184  */
 185 struct qcom_icc_provider {
 186         struct icc_provider provider;
 187         struct clk_bulk_data *bus_clks;
 188         int num_clks;
 189         bool is_bimc_node;
 190         struct regmap *regmap;
 191         void __iomem *mmio;
 192 };
 193
 194 #define SDM660_MAX_LINKS        34
 195
 196 /**
 197  * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters
 198  * @areq_prio: node requests priority
 199  * @prio_level: priority level for bus communication
 200  * @limit_commands: activate/deactivate limiter mode during runtime
 201  * @ap_owned: indicates if the node is owned by the AP or by the RPM
 202  * @qos_mode: default qos mode for this node
 203  * @qos_port: qos port number for finding qos registers of this node
 204  */
 205 struct qcom_icc_qos {
 206         u32 areq_prio;
 207         u32 prio_level;
 208         bool limit_commands;
 209         bool ap_owned;
 210         int qos_mode;
 211         int qos_port;
 212 };
 213
 214 /**
 215  * struct qcom_icc_node - Qualcomm specific interconnect nodes
 216  * @name: the node name used in debugfs
 217  * @id: a unique node identifier
 218  * @links: an array of nodes where we can go next while traversing
 219  * @num_links: the total number of @links
 220  * @buswidth: width of the interconnect between a node and the bus (bytes)
 221  * @mas_rpm_id: RPM id for devices that are bus masters
 222  * @slv_rpm_id: RPM id for devices that are bus slaves
 223  * @qos: NoC QoS setting parameters
 224  * @rate: current bus clock rate in Hz
 225  */
 226 struct qcom_icc_node {
 227         unsigned char *name;
 228         u16 id;
 229         u16 links[SDM660_MAX_LINKS];
 230         u16 num_links;
 231         u16 buswidth;
 232         int mas_rpm_id;
 233         int slv_rpm_id;
 234         struct qcom_icc_qos qos;
 235         u64 rate;
 236 };
 237
 238 struct qcom_icc_desc {
 239         struct qcom_icc_node **nodes;
 240         size_t num_nodes;
 241         const struct regmap_config *regmap_cfg;
 242 };
 243
 244 #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id,   \
 245                      _ap_owned, _qos_mode, _qos_prio, _qos_port, ...)   \
 246                 static struct qcom_icc_node _name = {                   \
 247                 .name = #_name,                                         \
 248                 .id = _id,                                              \
 249                 .buswidth = _buswidth,                                  \
 250                 .mas_rpm_id = _mas_rpm_id,                              \
 251                 .slv_rpm_id = _slv_rpm_id,                              \
 252                 .qos.ap_owned = _ap_owned,                              \
 253                 .qos.qos_mode = _qos_mode,                              \
 254                 .qos.areq_prio = _qos_prio,                             \
 255                 .qos.prio_level = _qos_prio,                            \
 256                 .qos.qos_port = _qos_port,                              \
 257                 .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),      \
 258                 .links = { __VA_ARGS__ },                               \
 259         }
 260
 261 DEFINE_QNODE(mas_ipa, SDM660_MASTER_IPA, 8, 59, -1, true, NOC_QOS_MODE_FIXED, 1, 3, SDM660_SLAVE_A2NOC_SNOC);
 262 DEFINE_QNODE(mas_cnoc_a2noc, SDM660_MASTER_CNOC_A2NOC, 8, 146, -1, true, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
 263 DEFINE_QNODE(mas_sdcc_1, SDM660_MASTER_SDCC_1, 8, 33, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
 264 DEFINE_QNODE(mas_sdcc_2, SDM660_MASTER_SDCC_2, 8, 35, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
 265 DEFINE_QNODE(mas_blsp_1, SDM660_MASTER_BLSP_1, 4, 41, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
 266 DEFINE_QNODE(mas_blsp_2, SDM660_MASTER_BLSP_2, 4, 39, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
 267 DEFINE_QNODE(mas_ufs, SDM660_MASTER_UFS, 8, 68, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_A2NOC_SNOC);
 268 DEFINE_QNODE(mas_usb_hs, SDM660_MASTER_USB_HS, 8, 42, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_A2NOC_SNOC);
 269 DEFINE_QNODE(mas_usb3, SDM660_MASTER_USB3, 8, 32, -1, true, NOC_QOS_MODE_FIXED, 1, 2, SDM660_SLAVE_A2NOC_SNOC);
 270 DEFINE_QNODE(mas_crypto, SDM660_MASTER_CRYPTO_C0, 8, 23, -1, true, NOC_QOS_MODE_FIXED, 1, 11, SDM660_SLAVE_A2NOC_SNOC);
 271 DEFINE_QNODE(mas_gnoc_bimc, SDM660_MASTER_GNOC_BIMC, 4, 144, -1, true, NOC_QOS_MODE_FIXED, 0, 0, SDM660_SLAVE_EBI);
 272 DEFINE_QNODE(mas_oxili, SDM660_MASTER_OXILI, 4, 6, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC);
 273 DEFINE_QNODE(mas_mnoc_bimc, SDM660_MASTER_MNOC_BIMC, 4, 2, -1, true, NOC_QOS_MODE_BYPASS, 0, 2, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC);
 274 DEFINE_QNODE(mas_snoc_bimc, SDM660_MASTER_SNOC_BIMC, 4, 3, -1, false, -1, 0, -1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI);
 275 DEFINE_QNODE(mas_pimem, SDM660_MASTER_PIMEM, 4, 113, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI);
 276 DEFINE_QNODE(mas_snoc_cnoc, SDM660_MASTER_SNOC_CNOC, 8, 52, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG);
 277 DEFINE_QNODE(mas_qdss_dap, SDM660_MASTER_QDSS_DAP, 8, 49, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_CNOC_A2NOC, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG);
 278 DEFINE_QNODE(mas_apss_proc, SDM660_MASTER_APPS_PROC, 16, 0, -1, true, -1, 0, -1, SDM660_SLAVE_GNOC_SNOC, SDM660_SLAVE_GNOC_BIMC);
 279 DEFINE_QNODE(mas_cnoc_mnoc_mmss_cfg, SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 8, 4, -1, true, -1, 0, -1, SDM660_SLAVE_VENUS_THROTTLE_CFG, SDM660_SLAVE_VENUS_CFG, SDM660_SLAVE_CAMERA_THROTTLE_CFG, SDM660_SLAVE_SMMU_CFG, SDM660_SLAVE_CAMERA_CFG, SDM660_SLAVE_CSI_PHY_CFG, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, SDM660_SLAVE_DISPLAY_CFG, SDM660_SLAVE_MMSS_CLK_CFG, SDM660_SLAVE_MNOC_MPU_CFG, SDM660_SLAVE_MISC_CFG, SDM660_SLAVE_MMSS_CLK_XPU_CFG);
 280 DEFINE_QNODE(mas_cnoc_mnoc_cfg, SDM660_MASTER_CNOC_MNOC_CFG, 4, 5, -1, true, -1, 0, -1, SDM660_SLAVE_SRVC_MNOC);
 281 DEFINE_QNODE(mas_cpp, SDM660_MASTER_CPP, 16, 115, -1, true, NOC_QOS_MODE_BYPASS, 0, 4, SDM660_SLAVE_MNOC_BIMC);
 282 DEFINE_QNODE(mas_jpeg, SDM660_MASTER_JPEG, 16, 7, -1, true, NOC_QOS_MODE_BYPASS, 0, 6, SDM660_SLAVE_MNOC_BIMC);
 283 DEFINE_QNODE(mas_mdp_p0, SDM660_MASTER_MDP_P0, 16, 8, -1, true, NOC_QOS_MODE_BYPASS, 0, 0, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp???? */
 284 DEFINE_QNODE(mas_mdp_p1, SDM660_MASTER_MDP_P1, 16, 61, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp??? */
 285 DEFINE_QNODE(mas_venus, SDM660_MASTER_VENUS, 16, 9, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC);
 286 DEFINE_QNODE(mas_vfe, SDM660_MASTER_VFE, 16, 11, -1, true, NOC_QOS_MODE_BYPASS, 0, 5, SDM660_SLAVE_MNOC_BIMC);
 287 DEFINE_QNODE(mas_qdss_etr, SDM660_MASTER_QDSS_ETR, 8, 31, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC);
 288 DEFINE_QNODE(mas_qdss_bam, SDM660_MASTER_QDSS_BAM, 4, 19, -1, true, NOC_QOS_MODE_FIXED, 1, 0, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC);
 289 DEFINE_QNODE(mas_snoc_cfg, SDM660_MASTER_SNOC_CFG, 4, 20, -1, false, -1, 0, -1, SDM660_SLAVE_SRVC_SNOC);
 290 DEFINE_QNODE(mas_bimc_snoc, SDM660_MASTER_BIMC_SNOC, 8, 21, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
 291 DEFINE_QNODE(mas_gnoc_snoc, SDM660_MASTER_GNOC_SNOC, 8, 150, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
 292 DEFINE_QNODE(mas_a2noc_snoc, SDM660_MASTER_A2NOC_SNOC, 16, 112, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_SNOC_BIMC, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
 293 DEFINE_QNODE(slv_a2noc_snoc, SDM660_SLAVE_A2NOC_SNOC, 16, -1, 143, false, -1, 0, -1, SDM660_MASTER_A2NOC_SNOC);
 294 DEFINE_QNODE(slv_ebi, SDM660_SLAVE_EBI, 4, -1, 0, false, -1, 0, -1, 0);
 295 DEFINE_QNODE(slv_hmss_l3, SDM660_SLAVE_HMSS_L3, 4, -1, 160, false, -1, 0, -1, 0);
 296 DEFINE_QNODE(slv_bimc_snoc, SDM660_SLAVE_BIMC_SNOC, 4, -1, 2, false, -1, 0, -1, SDM660_MASTER_BIMC_SNOC);
 297 DEFINE_QNODE(slv_cnoc_a2noc, SDM660_SLAVE_CNOC_A2NOC, 8, -1, 208, true, -1, 0, -1, SDM660_MASTER_CNOC_A2NOC);
 298 DEFINE_QNODE(slv_mpm, SDM660_SLAVE_MPM, 4, -1, 62, true, -1, 0, -1, 0);
 299 DEFINE_QNODE(slv_pmic_arb, SDM660_SLAVE_PMIC_ARB, 4, -1, 59, true, -1, 0, -1, 0);
 300 DEFINE_QNODE(slv_tlmm_north, SDM660_SLAVE_TLMM_NORTH, 8, -1, 214, true, -1, 0, -1, 0);
 301 DEFINE_QNODE(slv_tcsr, SDM660_SLAVE_TCSR, 4, -1, 50, true, -1, 0, -1, 0);
 302 DEFINE_QNODE(slv_pimem_cfg, SDM660_SLAVE_PIMEM_CFG, 4, -1, 167, true, -1, 0, -1, 0);
 303 DEFINE_QNODE(slv_imem_cfg, SDM660_SLAVE_IMEM_CFG, 4, -1, 54, true, -1, 0, -1, 0);
 304 DEFINE_QNODE(slv_message_ram, SDM660_SLAVE_MESSAGE_RAM, 4, -1, 55, true, -1, 0, -1, 0);
 305 DEFINE_QNODE(slv_glm, SDM660_SLAVE_GLM, 4, -1, 209, true, -1, 0, -1, 0);
 306 DEFINE_QNODE(slv_bimc_cfg, SDM660_SLAVE_BIMC_CFG, 4, -1, 56, true, -1, 0, -1, 0);
 307 DEFINE_QNODE(slv_prng, SDM660_SLAVE_PRNG, 4, -1, 44, true, -1, 0, -1, 0);
 308 DEFINE_QNODE(slv_spdm, SDM660_SLAVE_SPDM, 4, -1, 60, true, -1, 0, -1, 0);
 309 DEFINE_QNODE(slv_qdss_cfg, SDM660_SLAVE_QDSS_CFG, 4, -1, 63, true, -1, 0, -1, 0);
 310 DEFINE_QNODE(slv_cnoc_mnoc_cfg, SDM660_SLAVE_BLSP_1, 4, -1, 66, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_CFG);
 311 DEFINE_QNODE(slv_snoc_cfg, SDM660_SLAVE_SNOC_CFG, 4, -1, 70, true, -1, 0, -1, 0);
 312 DEFINE_QNODE(slv_qm_cfg, SDM660_SLAVE_QM_CFG, 4, -1, 212, true, -1, 0, -1, 0);
 313 DEFINE_QNODE(slv_clk_ctl, SDM660_SLAVE_CLK_CTL, 4, -1, 47, true, -1, 0, -1, 0);
 314 DEFINE_QNODE(slv_mss_cfg, SDM660_SLAVE_MSS_CFG, 4, -1, 48, true, -1, 0, -1, 0);
 315 DEFINE_QNODE(slv_tlmm_south, SDM660_SLAVE_TLMM_SOUTH, 4, -1, 217, true, -1, 0, -1, 0);
 316 DEFINE_QNODE(slv_ufs_cfg, SDM660_SLAVE_UFS_CFG, 4, -1, 92, true, -1, 0, -1, 0);
 317 DEFINE_QNODE(slv_a2noc_cfg, SDM660_SLAVE_A2NOC_CFG, 4, -1, 150, true, -1, 0, -1, 0);
 318 DEFINE_QNODE(slv_a2noc_smmu_cfg, SDM660_SLAVE_A2NOC_SMMU_CFG, 8, -1, 152, true, -1, 0, -1, 0);
 319 DEFINE_QNODE(slv_gpuss_cfg, SDM660_SLAVE_GPUSS_CFG, 8, -1, 11, true, -1, 0, -1, 0);
 320 DEFINE_QNODE(slv_ahb2phy, SDM660_SLAVE_AHB2PHY, 4, -1, 163, true, -1, 0, -1, 0);
 321 DEFINE_QNODE(slv_blsp_1, SDM660_SLAVE_BLSP_1, 4, -1, 39, true, -1, 0, -1, 0);
 322 DEFINE_QNODE(slv_sdcc_1, SDM660_SLAVE_SDCC_1, 4, -1, 31, true, -1, 0, -1, 0);
 323 DEFINE_QNODE(slv_sdcc_2, SDM660_SLAVE_SDCC_2, 4, -1, 33, true, -1, 0, -1, 0);
 324 DEFINE_QNODE(slv_tlmm_center, SDM660_SLAVE_TLMM_CENTER, 4, -1, 218, true, -1, 0, -1, 0);
 325 DEFINE_QNODE(slv_blsp_2, SDM660_SLAVE_BLSP_2, 4, -1, 37, true, -1, 0, -1, 0);
 326 DEFINE_QNODE(slv_pdm, SDM660_SLAVE_PDM, 4, -1, 41, true, -1, 0, -1, 0);
 327 DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 8, -1, 58, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_MMSS_CFG);
 328 DEFINE_QNODE(slv_usb_hs, SDM660_SLAVE_USB_HS, 4, -1, 40, true, -1, 0, -1, 0);
 329 DEFINE_QNODE(slv_usb3_0, SDM660_SLAVE_USB3_0, 4, -1, 22, true, -1, 0, -1, 0);
 330 DEFINE_QNODE(slv_srvc_cnoc, SDM660_SLAVE_SRVC_CNOC, 4, -1, 76, true, -1, 0, -1, 0);
 331 DEFINE_QNODE(slv_gnoc_bimc, SDM660_SLAVE_GNOC_BIMC, 16, -1, 210, true, -1, 0, -1, SDM660_MASTER_GNOC_BIMC);
 332 DEFINE_QNODE(slv_gnoc_snoc, SDM660_SLAVE_GNOC_SNOC, 8, -1, 211, true, -1, 0, -1, SDM660_MASTER_GNOC_SNOC);
 333 DEFINE_QNODE(slv_camera_cfg, SDM660_SLAVE_CAMERA_CFG, 4, -1, 3, true, -1, 0, -1, 0);
 334 DEFINE_QNODE(slv_camera_throttle_cfg, SDM660_SLAVE_CAMERA_THROTTLE_CFG, 4, -1, 154, true, -1, 0, -1, 0);
 335 DEFINE_QNODE(slv_misc_cfg, SDM660_SLAVE_MISC_CFG, 4, -1, 8, true, -1, 0, -1, 0);
 336 DEFINE_QNODE(slv_venus_throttle_cfg, SDM660_SLAVE_VENUS_THROTTLE_CFG, 4, -1, 178, true, -1, 0, -1, 0);
 337 DEFINE_QNODE(slv_venus_cfg, SDM660_SLAVE_VENUS_CFG, 4, -1, 10, true, -1, 0, -1, 0);
 338 DEFINE_QNODE(slv_mmss_clk_xpu_cfg, SDM660_SLAVE_MMSS_CLK_XPU_CFG, 4, -1, 13, true, -1, 0, -1, 0);
 339 DEFINE_QNODE(slv_mmss_clk_cfg, SDM660_SLAVE_MMSS_CLK_CFG, 4, -1, 12, true, -1, 0, -1, 0);
 340 DEFINE_QNODE(slv_mnoc_mpu_cfg, SDM660_SLAVE_MNOC_MPU_CFG, 4, -1, 14, true, -1, 0, -1, 0);
 341 DEFINE_QNODE(slv_display_cfg, SDM660_SLAVE_DISPLAY_CFG, 4, -1, 4, true, -1, 0, -1, 0);
 342 DEFINE_QNODE(slv_csi_phy_cfg, SDM660_SLAVE_CSI_PHY_CFG, 4, -1, 224, true, -1, 0, -1, 0);
 343 DEFINE_QNODE(slv_display_throttle_cfg, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 4, -1, 156, true, -1, 0, -1, 0);
 344 DEFINE_QNODE(slv_smmu_cfg, SDM660_SLAVE_SMMU_CFG, 8, -1, 205, true, -1, 0, -1, 0);
 345 DEFINE_QNODE(slv_mnoc_bimc, SDM660_SLAVE_MNOC_BIMC, 16, -1, 16, true, -1, 0, -1, SDM660_MASTER_MNOC_BIMC);
 346 DEFINE_QNODE(slv_srvc_mnoc, SDM660_SLAVE_SRVC_MNOC, 8, -1, 17, true, -1, 0, -1, 0);
 347 DEFINE_QNODE(slv_hmss, SDM660_SLAVE_HMSS, 8, -1, 20, true, -1, 0, -1, 0);
 348 DEFINE_QNODE(slv_lpass, SDM660_SLAVE_LPASS, 4, -1, 21, true, -1, 0, -1, 0);
 349 DEFINE_QNODE(slv_wlan, SDM660_SLAVE_WLAN, 4, -1, 206, false, -1, 0, -1, 0);
 350 DEFINE_QNODE(slv_cdsp, SDM660_SLAVE_CDSP, 4, -1, 221, true, -1, 0, -1, 0);
 351 DEFINE_QNODE(slv_ipa, SDM660_SLAVE_IPA, 4, -1, 183, true, -1, 0, -1, 0);
 352 DEFINE_QNODE(slv_snoc_bimc, SDM660_SLAVE_SNOC_BIMC, 16, -1, 24, false, -1, 0, -1, SDM660_MASTER_SNOC_BIMC);
 353 DEFINE_QNODE(slv_snoc_cnoc, SDM660_SLAVE_SNOC_CNOC, 8, -1, 25, false, -1, 0, -1, SDM660_MASTER_SNOC_CNOC);
 354 DEFINE_QNODE(slv_imem, SDM660_SLAVE_IMEM, 8, -1, 26, false, -1, 0, -1, 0);
 355 DEFINE_QNODE(slv_pimem, SDM660_SLAVE_PIMEM, 8, -1, 166, false, -1, 0, -1, 0);
 356 DEFINE_QNODE(slv_qdss_stm, SDM660_SLAVE_QDSS_STM, 4, -1, 30, false, -1, 0, -1, 0);
 357 DEFINE_QNODE(slv_srvc_snoc, SDM660_SLAVE_SRVC_SNOC, 16, -1, 29, false, -1, 0, -1, 0);
 358
 359 static struct qcom_icc_node *sdm660_a2noc_nodes[] = {
 360         [MASTER_IPA] = &mas_ipa,
 361         [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
 362         [MASTER_SDCC_1] = &mas_sdcc_1,
 363         [MASTER_SDCC_2] = &mas_sdcc_2,
 364         [MASTER_BLSP_1] = &mas_blsp_1,
 365         [MASTER_BLSP_2] = &mas_blsp_2,
 366         [MASTER_UFS] = &mas_ufs,
 367         [MASTER_USB_HS] = &mas_usb_hs,
 368         [MASTER_USB3] = &mas_usb3,
 369         [MASTER_CRYPTO_C0] = &mas_crypto,
 370         [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
 371 };
 372
 373 static const struct regmap_config sdm660_a2noc_regmap_config = {
 374         .reg_bits       = 32,
 375         .reg_stride     = 4,
 376         .val_bits       = 32,
 377         .max_register   = 0x20000,
 378         .fast_io        = true,
 379 };
 380
 381 static struct qcom_icc_desc sdm660_a2noc = {
 382         .nodes = sdm660_a2noc_nodes,
 383         .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
 384         .regmap_cfg = &sdm660_a2noc_regmap_config,
 385 };
 386
 387 static struct qcom_icc_node *sdm660_bimc_nodes[] = {
 388         [MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
 389         [MASTER_OXILI] = &mas_oxili,
 390         [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
 391         [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
 392         [MASTER_PIMEM] = &mas_pimem,
 393         [SLAVE_EBI] = &slv_ebi,
 394         [SLAVE_HMSS_L3] = &slv_hmss_l3,
 395         [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
 396 };
 397
 398 static const struct regmap_config sdm660_bimc_regmap_config = {
 399         .reg_bits       = 32,
 400         .reg_stride     = 4,
 401         .val_bits       = 32,
 402         .max_register   = 0x80000,
 403         .fast_io        = true,
 404 };
 405
 406 static struct qcom_icc_desc sdm660_bimc = {
 407         .nodes = sdm660_bimc_nodes,
 408         .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
 409         .regmap_cfg = &sdm660_bimc_regmap_config,
 410 };
 411
 412 static struct qcom_icc_node *sdm660_cnoc_nodes[] = {
 413         [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
 414         [MASTER_QDSS_DAP] = &mas_qdss_dap,
 415         [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
 416         [SLAVE_MPM] = &slv_mpm,
 417         [SLAVE_PMIC_ARB] = &slv_pmic_arb,
 418         [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
 419         [SLAVE_TCSR] = &slv_tcsr,
 420         [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
 421         [SLAVE_IMEM_CFG] = &slv_imem_cfg,
 422         [SLAVE_MESSAGE_RAM] = &slv_message_ram,
 423         [SLAVE_GLM] = &slv_glm,
 424         [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
 425         [SLAVE_PRNG] = &slv_prng,
 426         [SLAVE_SPDM] = &slv_spdm,
 427         [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
 428         [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
 429         [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
 430         [SLAVE_QM_CFG] = &slv_qm_cfg,
 431         [SLAVE_CLK_CTL] = &slv_clk_ctl,
 432         [SLAVE_MSS_CFG] = &slv_mss_cfg,
 433         [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
 434         [SLAVE_UFS_CFG] = &slv_ufs_cfg,
 435         [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
 436         [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
 437         [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
 438         [SLAVE_AHB2PHY] = &slv_ahb2phy,
 439         [SLAVE_BLSP_1] = &slv_blsp_1,
 440         [SLAVE_SDCC_1] = &slv_sdcc_1,
 441         [SLAVE_SDCC_2] = &slv_sdcc_2,
 442         [SLAVE_TLMM_CENTER] = &slv_tlmm_center,
 443         [SLAVE_BLSP_2] = &slv_blsp_2,
 444         [SLAVE_PDM] = &slv_pdm,
 445         [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
 446         [SLAVE_USB_HS] = &slv_usb_hs,
 447         [SLAVE_USB3_0] = &slv_usb3_0,
 448         [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
 449 };
 450
 451 static const struct regmap_config sdm660_cnoc_regmap_config = {
 452         .reg_bits       = 32,
 453         .reg_stride     = 4,
 454         .val_bits       = 32,
 455         .max_register   = 0x10000,
 456         .fast_io        = true,
 457 };
 458
 459 static struct qcom_icc_desc sdm660_cnoc = {
 460         .nodes = sdm660_cnoc_nodes,
 461         .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
 462         .regmap_cfg = &sdm660_cnoc_regmap_config,
 463 };
 464
 465 static struct qcom_icc_node *sdm660_gnoc_nodes[] = {
 466         [MASTER_APSS_PROC] = &mas_apss_proc,
 467         [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
 468         [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
 469 };
 470
 471 static const struct regmap_config sdm660_gnoc_regmap_config = {
 472         .reg_bits       = 32,
 473         .reg_stride     = 4,
 474         .val_bits       = 32,
 475         .max_register   = 0xe000,
 476         .fast_io        = true,
 477 };
 478
 479 static struct qcom_icc_desc sdm660_gnoc = {
 480         .nodes = sdm660_gnoc_nodes,
 481         .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
 482         .regmap_cfg = &sdm660_gnoc_regmap_config,
 483 };
 484
 485 static struct qcom_icc_node *sdm660_mnoc_nodes[] = {
 486         [MASTER_CPP] = &mas_cpp,
 487         [MASTER_JPEG] = &mas_jpeg,
 488         [MASTER_MDP_P0] = &mas_mdp_p0,
 489         [MASTER_MDP_P1] = &mas_mdp_p1,
 490         [MASTER_VENUS] = &mas_venus,
 491         [MASTER_VFE] = &mas_vfe,
 492         [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
 493         [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
 494         [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
 495         [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
 496         [SLAVE_MISC_CFG] = &slv_misc_cfg,
 497         [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
 498         [SLAVE_VENUS_CFG] = &slv_venus_cfg,
 499         [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
 500         [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
 501         [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
 502         [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
 503         [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
 504         [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
 505         [SLAVE_SMMU_CFG] = &slv_smmu_cfg,
 506         [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
 507         [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
 508 };
 509
 510 static const struct regmap_config sdm660_mnoc_regmap_config = {
 511         .reg_bits       = 32,
 512         .reg_stride     = 4,
 513         .val_bits       = 32,
 514         .max_register   = 0x10000,
 515         .fast_io        = true,
 516 };
 517
 518 static struct qcom_icc_desc sdm660_mnoc = {
 519         .nodes = sdm660_mnoc_nodes,
 520         .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
 521         .regmap_cfg = &sdm660_mnoc_regmap_config,
 522 };
 523
 524 static struct qcom_icc_node *sdm660_snoc_nodes[] = {
 525         [MASTER_QDSS_ETR] = &mas_qdss_etr,
 526         [MASTER_QDSS_BAM] = &mas_qdss_bam,
 527         [MASTER_SNOC_CFG] = &mas_snoc_cfg,
 528         [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
 529         [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
 530         [MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
 531         [SLAVE_HMSS] = &slv_hmss,
 532         [SLAVE_LPASS] = &slv_lpass,
 533         [SLAVE_WLAN] = &slv_wlan,
 534         [SLAVE_CDSP] = &slv_cdsp,
 535         [SLAVE_IPA] = &slv_ipa,
 536         [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
 537         [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
 538         [SLAVE_IMEM] = &slv_imem,
 539         [SLAVE_PIMEM] = &slv_pimem,
 540         [SLAVE_QDSS_STM] = &slv_qdss_stm,
 541         [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
 542 };
 543
 544 static const struct regmap_config sdm660_snoc_regmap_config = {
 545         .reg_bits       = 32,
 546         .reg_stride     = 4,
 547         .val_bits       = 32,
 548         .max_register   = 0x20000,
 549         .fast_io        = true,
 550 };
 551
 552 static struct qcom_icc_desc sdm660_snoc = {
 553         .nodes = sdm660_snoc_nodes,
 554         .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
 555         .regmap_cfg = &sdm660_snoc_regmap_config,
 556 };
 557
 558 static int qcom_icc_bimc_set_qos_health(struct regmap *rmap,
 559                                         struct qcom_icc_qos *qos,
 560                                         int regnum)
 561 {
 562         u32 val;
 563         u32 mask;
 564
 565         val = qos->prio_level;
 566         mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK;
 567
 568         val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT;
 569         mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK;
 570
 571         /* LIMITCMDS is not present on M_BKE_HEALTH_3 */
 572         if (regnum != 3) {
 573                 val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT;
 574                 mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK;
 575         }
 576
 577         return regmap_update_bits(rmap,
 578                                   M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
 579                                   mask, val);
 580 }
 581
 582 static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw,
 583                                  bool bypass_mode)
 584 {
 585         struct qcom_icc_provider *qp;
 586         struct qcom_icc_node *qn;
 587         struct icc_provider *provider;
 588         u32 mode = NOC_QOS_MODE_BYPASS;
 589         u32 val = 0;
 590         int i, rc = 0;
 591
 592         qn = src->data;
 593         provider = src->provider;
 594         qp = to_qcom_provider(provider);
 595
 596         if (qn->qos.qos_mode != -1)
 597                 mode = qn->qos.qos_mode;
 598
 599         /* QoS Priority: The QoS Health parameters are getting considered
 600          * only if we are NOT in Bypass Mode.
 601          */
 602         if (mode != NOC_QOS_MODE_BYPASS) {
 603                 for (i = 3; i >= 0; i--) {
 604                         rc = qcom_icc_bimc_set_qos_health(qp->regmap,
 605                                                           &qn->qos, i);
 606                         if (rc)
 607                                 return rc;
 608                 }
 609
 610                 /* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */
 611                 val = 1;
 612         }
 613
 614         return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port),
 615                                   M_BKE_EN_EN_BMASK, val);
 616 }
 617
 618 static int qcom_icc_noc_set_qos_priority(struct regmap *rmap,
 619                                          struct qcom_icc_qos *qos)
 620 {
 621         u32 val;
 622         int rc;
 623
 624         /* Must be updated one at a time, P1 first, P0 last */
 625         val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
 626         rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
 627                                 NOC_QOS_PRIORITY_MASK, val);
 628         if (rc)
 629                 return rc;
 630
 631         val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT;
 632         return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
 633                                   NOC_QOS_PRIORITY_MASK, val);
 634 }
 635
 636 static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
 637 {
 638         struct qcom_icc_provider *qp;
 639         struct qcom_icc_node *qn;
 640         struct icc_provider *provider;
 641         u32 mode = NOC_QOS_MODE_BYPASS;
 642         int rc = 0;
 643
 644         qn = src->data;
 645         provider = src->provider;
 646         qp = to_qcom_provider(provider);
 647
 648         if (qn->qos.qos_port < 0) {
 649                 dev_dbg(src->provider->dev,
 650                         "NoC QoS: Skipping %s: vote aggregated on parent.\n",
 651                         qn->name);
 652                 return 0;
 653         }
 654
 655         if (qn->qos.qos_mode != -1)
 656                 mode = qn->qos.qos_mode;
 657
 658         if (mode == NOC_QOS_MODE_FIXED) {
 659                 dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n",
 660                         qn->name);
 661                 rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos);
 662                 if (rc)
 663                         return rc;
 664         } else if (mode == NOC_QOS_MODE_BYPASS) {
 665                 dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n",
 666                         qn->name);
 667         }
 668
 669         return regmap_update_bits(qp->regmap,
 670                                   NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
 671                                   NOC_QOS_MODEn_MASK, mode);
 672 }
 673
 674 static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw)
 675 {
 676         struct qcom_icc_provider *qp = to_qcom_provider(node->provider);
 677         struct qcom_icc_node *qn = node->data;
 678
 679         dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name);
 680
 681         if (qp->is_bimc_node)
 682                 return qcom_icc_set_bimc_qos(node, sum_bw,
 683                                 (qn->qos.qos_mode == NOC_QOS_MODE_BYPASS));
 684
 685         return qcom_icc_set_noc_qos(node, sum_bw);
 686 }
 687
 688 static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw)
 689 {
 690         int ret = 0;
 691
 692         if (mas_rpm_id != -1) {
 693                 ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
 694                                             RPM_BUS_MASTER_REQ,
 695                                             mas_rpm_id,
 696                                             sum_bw);
 697                 if (ret) {
 698                         pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
 699                                mas_rpm_id, ret);
 700                         return ret;
 701                 }
 702         }
 703
 704         if (slv_rpm_id != -1) {
 705                 ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
 706                                             RPM_BUS_SLAVE_REQ,
 707                                             slv_rpm_id,
 708                                             sum_bw);
 709                 if (ret) {
 710                         pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
 711                                slv_rpm_id, ret);
 712                         return ret;
 713                 }
 714         }
 715
 716         return ret;
 717 }
 718
 719 static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 720 {
 721         struct qcom_icc_provider *qp;
 722         struct qcom_icc_node *qn;
 723         struct icc_provider *provider;
 724         struct icc_node *n;
 725         u64 sum_bw;
 726         u64 max_peak_bw;
 727         u64 rate;
 728         u32 agg_avg = 0;
 729         u32 agg_peak = 0;
 730         int ret, i;
 731
 732         qn = src->data;
 733         provider = src->provider;
 734         qp = to_qcom_provider(provider);
 735
 736         list_for_each_entry(n, &provider->nodes, node_list)
 737                 provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
 738                                     &agg_avg, &agg_peak);
 739
 740         sum_bw = icc_units_to_bps(agg_avg);
 741         max_peak_bw = icc_units_to_bps(agg_peak);
 742
 743         if (!qn->qos.ap_owned) {
 744                 /* send bandwidth request message to the RPM processor */
 745                 ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw);
 746                 if (ret)
 747                         return ret;
 748         } else if (qn->qos.qos_mode != -1) {
 749                 /* set bandwidth directly from the AP */
 750                 ret = qcom_icc_qos_set(src, sum_bw);
 751                 if (ret)
 752                         return ret;
 753         }
 754
 755         rate = max(sum_bw, max_peak_bw);
 756
 757         do_div(rate, qn->buswidth);
 758
 759         if (qn->rate == rate)
 760                 return 0;
 761
 762         for (i = 0; i < qp->num_clks; i++) {
 763                 ret = clk_set_rate(qp->bus_clks[i].clk, rate);
 764                 if (ret) {
 765                         pr_err("%s clk_set_rate error: %d\n",
 766                                qp->bus_clks[i].id, ret);
 767                         return ret;
 768                 }
 769         }
 770
 771         qn->rate = rate;
 772
 773         return 0;
 774 }
 775
 776 static int qnoc_probe(struct platform_device *pdev)
 777 {
 778         struct device *dev = &pdev->dev;
 779         const struct qcom_icc_desc *desc;
 780         struct icc_onecell_data *data;
 781         struct icc_provider *provider;
 782         struct qcom_icc_node **qnodes;
 783         struct qcom_icc_provider *qp;
 784         struct icc_node *node;
 785         struct resource *res;
 786         size_t num_nodes, i;
 787         int ret;
 788
 789         /* wait for the RPM proxy */
 790         if (!qcom_icc_rpm_smd_available())
 791                 return -EPROBE_DEFER;
 792
 793         desc = of_device_get_match_data(dev);
 794         if (!desc)
 795                 return -EINVAL;
 796
 797         qnodes = desc->nodes;
 798         num_nodes = desc->num_nodes;
 799
 800         qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
 801         if (!qp)
 802                 return -ENOMEM;
 803
 804         data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
 805                             GFP_KERNEL);
 806         if (!data)
 807                 return -ENOMEM;
 808
 809         if (of_device_is_compatible(dev->of_node, "qcom,sdm660-mnoc")) {
 810                 qp->bus_clks = devm_kmemdup(dev, bus_mm_clocks,
 811                                             sizeof(bus_mm_clocks), GFP_KERNEL);
 812                 qp->num_clks = ARRAY_SIZE(bus_mm_clocks);
 813         } else {
 814                 if (of_device_is_compatible(dev->of_node, "qcom,sdm660-bimc"))
 815                         qp->is_bimc_node = true;
 816
 817                 qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks),
 818                                             GFP_KERNEL);
 819                 qp->num_clks = ARRAY_SIZE(bus_clocks);
 820         }
 821         if (!qp->bus_clks)
 822                 return -ENOMEM;
 823
 824         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 825         if (!res)
 826                 return -ENODEV;
 827
 828         qp->mmio = devm_ioremap_resource(dev, res);
 829         if (IS_ERR(qp->mmio)) {
 830                 dev_err(dev, "Cannot ioremap interconnect bus resource\n");
 831                 return PTR_ERR(qp->mmio);
 832         }
 833
 834         qp->regmap = devm_regmap_init_mmio(dev, qp->mmio, desc->regmap_cfg);
 835         if (IS_ERR(qp->regmap)) {
 836                 dev_err(dev, "Cannot regmap interconnect bus resource\n");
 837                 return PTR_ERR(qp->regmap);
 838         }
 839
 840         ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
 841         if (ret)
 842                 return ret;
 843
 844         ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
 845         if (ret)
 846                 return ret;
 847
 848         provider = &qp->provider;
 849         INIT_LIST_HEAD(&provider->nodes);
 850         provider->dev = dev;
 851         provider->set = qcom_icc_set;
 852         provider->aggregate = icc_std_aggregate;
 853         provider->xlate = of_icc_xlate_onecell;
 854         provider->data = data;
 855
 856         ret = icc_provider_add(provider);
 857         if (ret) {
 858                 dev_err(dev, "error adding interconnect provider: %d\n", ret);
 859                 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
 860                 return ret;
 861         }
 862
 863         for (i = 0; i < num_nodes; i++) {
 864                 size_t j;
 865
 866                 node = icc_node_create(qnodes[i]->id);
 867                 if (IS_ERR(node)) {
 868                         ret = PTR_ERR(node);
 869                         goto err;
 870                 }
 871
 872                 node->name = qnodes[i]->name;
 873                 node->data = qnodes[i];
 874                 icc_node_add(node, provider);
 875
 876                 for (j = 0; j < qnodes[i]->num_links; j++)
 877                         icc_link_create(node, qnodes[i]->links[j]);
 878
 879                 data->nodes[i] = node;
 880         }
 881         data->num_nodes = num_nodes;
 882         platform_set_drvdata(pdev, qp);
 883
 884         return 0;
 885 err:
 886         icc_nodes_remove(provider);
 887         clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
 888         icc_provider_del(provider);
 889
 890         return ret;
 891 }
 892
 893 static int qnoc_remove(struct platform_device *pdev)
 894 {
 895         struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
 896
 897         icc_nodes_remove(&qp->provider);
 898         clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
 899         return icc_provider_del(&qp->provider);
 900 }
 901
 902 static const struct of_device_id sdm660_noc_of_match[] = {
 903         { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
 904         { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
 905         { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
 906         { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
 907         { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
 908         { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
 909         { },
 910 };
 911 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
 912
 913 static struct platform_driver sdm660_noc_driver = {
 914         .probe = qnoc_probe,
 915         .remove = qnoc_remove,
 916         .driver = {
 917                 .name = "qnoc-sdm660",
 918                 .of_match_table = sdm660_noc_of_match,
 919         },
 920 };
 921 module_platform_driver(sdm660_noc_driver);
 922 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
 923 MODULE_LICENSE("GPL v2");