1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Linaro Ltd
6 #include <dt-bindings/interconnect/qcom,qcs404.h>
8 #include <linux/device.h>
9 #include <linux/interconnect-provider.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/of_device.h>
20 QCS404_MASTER_AMPSS_M0 = 1,
21 QCS404_MASTER_GRAPHICS_3D,
22 QCS404_MASTER_MDP_PORT0,
23 QCS404_SNOC_BIMC_1_MAS,
28 QCS404_MASTER_XM_USB_HS1,
29 QCS404_MASTER_CRYPTO_CORE0,
34 QCS404_MASTER_QDSS_BAM,
37 QCS404_MASTER_QDSS_ETR,
61 QCS404_SLAVE_SPDM_WRAPPER,
65 QCS404_SLAVE_SNOC_CFG,
66 QCS404_SLAVE_MESSAGE_RAM,
67 QCS404_SLAVE_DISPLAY_CFG,
68 QCS404_SLAVE_GRAPHICS_3D_CFG,
70 QCS404_SLAVE_TLMM_NORTH,
72 QCS404_SLAVE_EMAC_CFG,
74 QCS404_SLAVE_TLMM_EAST,
76 QCS404_SLAVE_PMIC_ARB,
79 QCS404_SLAVE_TLMM_SOUTH,
82 QCS404_SLAVE_CRYPTO_0_CFG,
86 QCS404_SNOC_BIMC_1_SLV,
89 QCS404_SLAVE_QDSS_STM,
90 QCS404_SLAVE_CATS_128,
91 QCS404_SLAVE_OCMEM_64,
95 static const u16 mas_apps_proc_links[] = {
100 static struct qcom_icc_node mas_apps_proc = {
101 .name = "mas_apps_proc",
102 .id = QCS404_MASTER_AMPSS_M0,
106 .num_links = ARRAY_SIZE(mas_apps_proc_links),
107 .links = mas_apps_proc_links,
110 static const u16 mas_oxili_links[] = {
111 QCS404_SLAVE_EBI_CH0,
115 static struct qcom_icc_node mas_oxili = {
117 .id = QCS404_MASTER_GRAPHICS_3D,
121 .num_links = ARRAY_SIZE(mas_oxili_links),
122 .links = mas_oxili_links,
125 static const u16 mas_mdp_links[] = {
126 QCS404_SLAVE_EBI_CH0,
130 static struct qcom_icc_node mas_mdp = {
132 .id = QCS404_MASTER_MDP_PORT0,
136 .num_links = ARRAY_SIZE(mas_mdp_links),
137 .links = mas_mdp_links,
140 static const u16 mas_snoc_bimc_1_links[] = {
144 static struct qcom_icc_node mas_snoc_bimc_1 = {
145 .name = "mas_snoc_bimc_1",
146 .id = QCS404_SNOC_BIMC_1_MAS,
150 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
151 .links = mas_snoc_bimc_1_links,
154 static const u16 mas_tcu_0_links[] = {
155 QCS404_SLAVE_EBI_CH0,
159 static struct qcom_icc_node mas_tcu_0 = {
161 .id = QCS404_MASTER_TCU_0,
165 .num_links = ARRAY_SIZE(mas_tcu_0_links),
166 .links = mas_tcu_0_links,
169 static const u16 mas_spdm_links[] = {
173 static struct qcom_icc_node mas_spdm = {
175 .id = QCS404_MASTER_SPDM,
179 .num_links = ARRAY_SIZE(mas_spdm_links),
180 .links = mas_spdm_links,
183 static const u16 mas_blsp_1_links[] = {
187 static struct qcom_icc_node mas_blsp_1 = {
188 .name = "mas_blsp_1",
189 .id = QCS404_MASTER_BLSP_1,
193 .num_links = ARRAY_SIZE(mas_blsp_1_links),
194 .links = mas_blsp_1_links,
197 static const u16 mas_blsp_2_links[] = {
201 static struct qcom_icc_node mas_blsp_2 = {
202 .name = "mas_blsp_2",
203 .id = QCS404_MASTER_BLSP_2,
207 .num_links = ARRAY_SIZE(mas_blsp_2_links),
208 .links = mas_blsp_2_links,
211 static const u16 mas_xi_usb_hs1_links[] = {
215 static struct qcom_icc_node mas_xi_usb_hs1 = {
216 .name = "mas_xi_usb_hs1",
217 .id = QCS404_MASTER_XM_USB_HS1,
221 .num_links = ARRAY_SIZE(mas_xi_usb_hs1_links),
222 .links = mas_xi_usb_hs1_links,
225 static const u16 mas_crypto_links[] = {
226 QCS404_PNOC_SNOC_SLV,
230 static struct qcom_icc_node mas_crypto = {
231 .name = "mas_crypto",
232 .id = QCS404_MASTER_CRYPTO_CORE0,
236 .num_links = ARRAY_SIZE(mas_crypto_links),
237 .links = mas_crypto_links,
240 static const u16 mas_sdcc_1_links[] = {
244 static struct qcom_icc_node mas_sdcc_1 = {
245 .name = "mas_sdcc_1",
246 .id = QCS404_MASTER_SDCC_1,
250 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
251 .links = mas_sdcc_1_links,
254 static const u16 mas_sdcc_2_links[] = {
258 static struct qcom_icc_node mas_sdcc_2 = {
259 .name = "mas_sdcc_2",
260 .id = QCS404_MASTER_SDCC_2,
264 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
265 .links = mas_sdcc_2_links,
268 static const u16 mas_snoc_pcnoc_links[] = {
272 static struct qcom_icc_node mas_snoc_pcnoc = {
273 .name = "mas_snoc_pcnoc",
274 .id = QCS404_SNOC_PNOC_MAS,
278 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
279 .links = mas_snoc_pcnoc_links,
282 static const u16 mas_qpic_links[] = {
286 static struct qcom_icc_node mas_qpic = {
288 .id = QCS404_MASTER_QPIC,
292 .num_links = ARRAY_SIZE(mas_qpic_links),
293 .links = mas_qpic_links,
296 static const u16 mas_qdss_bam_links[] = {
300 static struct qcom_icc_node mas_qdss_bam = {
301 .name = "mas_qdss_bam",
302 .id = QCS404_MASTER_QDSS_BAM,
306 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
307 .links = mas_qdss_bam_links,
310 static const u16 mas_bimc_snoc_links[] = {
311 QCS404_SLAVE_OCMEM_64,
312 QCS404_SLAVE_CATS_128,
317 static struct qcom_icc_node mas_bimc_snoc = {
318 .name = "mas_bimc_snoc",
319 .id = QCS404_BIMC_SNOC_MAS,
323 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
324 .links = mas_bimc_snoc_links,
327 static const u16 mas_pcnoc_snoc_links[] = {
328 QCS404_SNOC_BIMC_1_SLV,
333 static struct qcom_icc_node mas_pcnoc_snoc = {
334 .name = "mas_pcnoc_snoc",
335 .id = QCS404_PNOC_SNOC_MAS,
339 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
340 .links = mas_pcnoc_snoc_links,
343 static const u16 mas_qdss_etr_links[] = {
347 static struct qcom_icc_node mas_qdss_etr = {
348 .name = "mas_qdss_etr",
349 .id = QCS404_MASTER_QDSS_ETR,
353 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
354 .links = mas_qdss_etr_links,
357 static const u16 mas_emac_links[] = {
358 QCS404_SNOC_BIMC_1_SLV,
362 static struct qcom_icc_node mas_emac = {
364 .id = QCS404_MASTER_EMAC,
368 .num_links = ARRAY_SIZE(mas_emac_links),
369 .links = mas_emac_links,
372 static const u16 mas_pcie_links[] = {
373 QCS404_SNOC_BIMC_1_SLV,
377 static struct qcom_icc_node mas_pcie = {
379 .id = QCS404_MASTER_PCIE,
383 .num_links = ARRAY_SIZE(mas_pcie_links),
384 .links = mas_pcie_links,
387 static const u16 mas_usb3_links[] = {
388 QCS404_SNOC_BIMC_1_SLV,
392 static struct qcom_icc_node mas_usb3 = {
394 .id = QCS404_MASTER_USB3,
398 .num_links = ARRAY_SIZE(mas_usb3_links),
399 .links = mas_usb3_links,
402 static const u16 pcnoc_int_0_links[] = {
403 QCS404_PNOC_SNOC_SLV,
407 static struct qcom_icc_node pcnoc_int_0 = {
408 .name = "pcnoc_int_0",
409 .id = QCS404_PNOC_INT_0,
413 .num_links = ARRAY_SIZE(pcnoc_int_0_links),
414 .links = pcnoc_int_0_links,
417 static const u16 pcnoc_int_2_links[] = {
432 static struct qcom_icc_node pcnoc_int_2 = {
433 .name = "pcnoc_int_2",
434 .id = QCS404_PNOC_INT_2,
438 .num_links = ARRAY_SIZE(pcnoc_int_2_links),
439 .links = pcnoc_int_2_links,
442 static const u16 pcnoc_int_3_links[] = {
446 static struct qcom_icc_node pcnoc_int_3 = {
447 .name = "pcnoc_int_3",
448 .id = QCS404_PNOC_INT_3,
452 .num_links = ARRAY_SIZE(pcnoc_int_3_links),
453 .links = pcnoc_int_3_links,
456 static const u16 pcnoc_s_0_links[] = {
458 QCS404_SLAVE_SPDM_WRAPPER,
462 static struct qcom_icc_node pcnoc_s_0 = {
464 .id = QCS404_PNOC_SLV_0,
468 .num_links = ARRAY_SIZE(pcnoc_s_0_links),
469 .links = pcnoc_s_0_links,
472 static const u16 pcnoc_s_1_links[] = {
476 static struct qcom_icc_node pcnoc_s_1 = {
478 .id = QCS404_PNOC_SLV_1,
482 .num_links = ARRAY_SIZE(pcnoc_s_1_links),
483 .links = pcnoc_s_1_links,
486 static const u16 pcnoc_s_2_links[] = {
487 QCS404_SLAVE_GRAPHICS_3D_CFG
490 static struct qcom_icc_node pcnoc_s_2 = {
492 .id = QCS404_PNOC_SLV_2,
496 .num_links = ARRAY_SIZE(pcnoc_s_2_links),
497 .links = pcnoc_s_2_links,
500 static const u16 pcnoc_s_3_links[] = {
501 QCS404_SLAVE_MESSAGE_RAM
504 static struct qcom_icc_node pcnoc_s_3 = {
506 .id = QCS404_PNOC_SLV_3,
510 .num_links = ARRAY_SIZE(pcnoc_s_3_links),
511 .links = pcnoc_s_3_links,
514 static const u16 pcnoc_s_4_links[] = {
515 QCS404_SLAVE_SNOC_CFG
518 static struct qcom_icc_node pcnoc_s_4 = {
520 .id = QCS404_PNOC_SLV_4,
524 .num_links = ARRAY_SIZE(pcnoc_s_4_links),
525 .links = pcnoc_s_4_links,
528 static const u16 pcnoc_s_6_links[] = {
530 QCS404_SLAVE_TLMM_NORTH,
531 QCS404_SLAVE_EMAC_CFG
534 static struct qcom_icc_node pcnoc_s_6 = {
536 .id = QCS404_PNOC_SLV_6,
540 .num_links = ARRAY_SIZE(pcnoc_s_6_links),
541 .links = pcnoc_s_6_links,
544 static const u16 pcnoc_s_7_links[] = {
545 QCS404_SLAVE_TLMM_SOUTH,
546 QCS404_SLAVE_DISPLAY_CFG,
552 static struct qcom_icc_node pcnoc_s_7 = {
554 .id = QCS404_PNOC_SLV_7,
558 .num_links = ARRAY_SIZE(pcnoc_s_7_links),
559 .links = pcnoc_s_7_links,
562 static const u16 pcnoc_s_8_links[] = {
563 QCS404_SLAVE_CRYPTO_0_CFG
566 static struct qcom_icc_node pcnoc_s_8 = {
568 .id = QCS404_PNOC_SLV_8,
572 .num_links = ARRAY_SIZE(pcnoc_s_8_links),
573 .links = pcnoc_s_8_links,
576 static const u16 pcnoc_s_9_links[] = {
578 QCS404_SLAVE_TLMM_EAST,
579 QCS404_SLAVE_PMIC_ARB
582 static struct qcom_icc_node pcnoc_s_9 = {
584 .id = QCS404_PNOC_SLV_9,
588 .num_links = ARRAY_SIZE(pcnoc_s_9_links),
589 .links = pcnoc_s_9_links,
592 static const u16 pcnoc_s_10_links[] = {
596 static struct qcom_icc_node pcnoc_s_10 = {
597 .name = "pcnoc_s_10",
598 .id = QCS404_PNOC_SLV_10,
602 .num_links = ARRAY_SIZE(pcnoc_s_10_links),
603 .links = pcnoc_s_10_links,
606 static const u16 pcnoc_s_11_links[] = {
610 static struct qcom_icc_node pcnoc_s_11 = {
611 .name = "pcnoc_s_11",
612 .id = QCS404_PNOC_SLV_11,
616 .num_links = ARRAY_SIZE(pcnoc_s_11_links),
617 .links = pcnoc_s_11_links,
620 static const u16 qdss_int_links[] = {
621 QCS404_SNOC_BIMC_1_SLV,
625 static struct qcom_icc_node qdss_int = {
627 .id = QCS404_SNOC_QDSS_INT,
631 .num_links = ARRAY_SIZE(qdss_int_links),
632 .links = qdss_int_links,
635 static const u16 snoc_int_0_links[] = {
641 static struct qcom_icc_node snoc_int_0 = {
642 .name = "snoc_int_0",
643 .id = QCS404_SNOC_INT_0,
647 .num_links = ARRAY_SIZE(snoc_int_0_links),
648 .links = snoc_int_0_links,
651 static const u16 snoc_int_1_links[] = {
652 QCS404_SNOC_PNOC_SLV,
656 static struct qcom_icc_node snoc_int_1 = {
657 .name = "snoc_int_1",
658 .id = QCS404_SNOC_INT_1,
662 .num_links = ARRAY_SIZE(snoc_int_1_links),
663 .links = snoc_int_1_links,
666 static const u16 snoc_int_2_links[] = {
667 QCS404_SLAVE_QDSS_STM,
671 static struct qcom_icc_node snoc_int_2 = {
672 .name = "snoc_int_2",
673 .id = QCS404_SNOC_INT_2,
677 .num_links = ARRAY_SIZE(snoc_int_2_links),
678 .links = snoc_int_2_links,
681 static struct qcom_icc_node slv_ebi = {
683 .id = QCS404_SLAVE_EBI_CH0,
689 static const u16 slv_bimc_snoc_links[] = {
693 static struct qcom_icc_node slv_bimc_snoc = {
694 .name = "slv_bimc_snoc",
695 .id = QCS404_BIMC_SNOC_SLV,
699 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
700 .links = slv_bimc_snoc_links,
703 static struct qcom_icc_node slv_spdm = {
705 .id = QCS404_SLAVE_SPDM_WRAPPER,
711 static struct qcom_icc_node slv_pdm = {
713 .id = QCS404_SLAVE_PDM,
719 static struct qcom_icc_node slv_prng = {
721 .id = QCS404_SLAVE_PRNG,
727 static struct qcom_icc_node slv_tcsr = {
729 .id = QCS404_SLAVE_TCSR,
735 static struct qcom_icc_node slv_snoc_cfg = {
736 .name = "slv_snoc_cfg",
737 .id = QCS404_SLAVE_SNOC_CFG,
743 static struct qcom_icc_node slv_message_ram = {
744 .name = "slv_message_ram",
745 .id = QCS404_SLAVE_MESSAGE_RAM,
751 static struct qcom_icc_node slv_disp_ss_cfg = {
752 .name = "slv_disp_ss_cfg",
753 .id = QCS404_SLAVE_DISPLAY_CFG,
759 static struct qcom_icc_node slv_gpu_cfg = {
760 .name = "slv_gpu_cfg",
761 .id = QCS404_SLAVE_GRAPHICS_3D_CFG,
767 static struct qcom_icc_node slv_blsp_1 = {
768 .name = "slv_blsp_1",
769 .id = QCS404_SLAVE_BLSP_1,
775 static struct qcom_icc_node slv_tlmm_north = {
776 .name = "slv_tlmm_north",
777 .id = QCS404_SLAVE_TLMM_NORTH,
783 static struct qcom_icc_node slv_pcie = {
785 .id = QCS404_SLAVE_PCIE_1,
791 static struct qcom_icc_node slv_ethernet = {
792 .name = "slv_ethernet",
793 .id = QCS404_SLAVE_EMAC_CFG,
799 static struct qcom_icc_node slv_blsp_2 = {
800 .name = "slv_blsp_2",
801 .id = QCS404_SLAVE_BLSP_2,
807 static struct qcom_icc_node slv_tlmm_east = {
808 .name = "slv_tlmm_east",
809 .id = QCS404_SLAVE_TLMM_EAST,
815 static struct qcom_icc_node slv_tcu = {
817 .id = QCS404_SLAVE_TCU,
823 static struct qcom_icc_node slv_pmic_arb = {
824 .name = "slv_pmic_arb",
825 .id = QCS404_SLAVE_PMIC_ARB,
831 static struct qcom_icc_node slv_sdcc_1 = {
832 .name = "slv_sdcc_1",
833 .id = QCS404_SLAVE_SDCC_1,
839 static struct qcom_icc_node slv_sdcc_2 = {
840 .name = "slv_sdcc_2",
841 .id = QCS404_SLAVE_SDCC_2,
847 static struct qcom_icc_node slv_tlmm_south = {
848 .name = "slv_tlmm_south",
849 .id = QCS404_SLAVE_TLMM_SOUTH,
855 static struct qcom_icc_node slv_usb_hs = {
856 .name = "slv_usb_hs",
857 .id = QCS404_SLAVE_USB_HS,
863 static struct qcom_icc_node slv_usb3 = {
865 .id = QCS404_SLAVE_USB3,
871 static struct qcom_icc_node slv_crypto_0_cfg = {
872 .name = "slv_crypto_0_cfg",
873 .id = QCS404_SLAVE_CRYPTO_0_CFG,
879 static const u16 slv_pcnoc_snoc_links[] = {
883 static struct qcom_icc_node slv_pcnoc_snoc = {
884 .name = "slv_pcnoc_snoc",
885 .id = QCS404_PNOC_SNOC_SLV,
889 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
890 .links = slv_pcnoc_snoc_links,
893 static struct qcom_icc_node slv_kpss_ahb = {
894 .name = "slv_kpss_ahb",
895 .id = QCS404_SLAVE_APPSS,
901 static struct qcom_icc_node slv_wcss = {
903 .id = QCS404_SLAVE_WCSS,
909 static const u16 slv_snoc_bimc_1_links[] = {
910 QCS404_SNOC_BIMC_1_MAS
913 static struct qcom_icc_node slv_snoc_bimc_1 = {
914 .name = "slv_snoc_bimc_1",
915 .id = QCS404_SNOC_BIMC_1_SLV,
919 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links),
920 .links = slv_snoc_bimc_1_links,
923 static struct qcom_icc_node slv_imem = {
925 .id = QCS404_SLAVE_OCIMEM,
931 static const u16 slv_snoc_pcnoc_links[] = {
935 static struct qcom_icc_node slv_snoc_pcnoc = {
936 .name = "slv_snoc_pcnoc",
937 .id = QCS404_SNOC_PNOC_SLV,
941 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
942 .links = slv_snoc_pcnoc_links,
945 static struct qcom_icc_node slv_qdss_stm = {
946 .name = "slv_qdss_stm",
947 .id = QCS404_SLAVE_QDSS_STM,
953 static struct qcom_icc_node slv_cats_0 = {
954 .name = "slv_cats_0",
955 .id = QCS404_SLAVE_CATS_128,
961 static struct qcom_icc_node slv_cats_1 = {
962 .name = "slv_cats_1",
963 .id = QCS404_SLAVE_OCMEM_64,
969 static struct qcom_icc_node slv_lpass = {
971 .id = QCS404_SLAVE_LPASS,
977 static struct qcom_icc_node *qcs404_bimc_nodes[] = {
978 [MASTER_AMPSS_M0] = &mas_apps_proc,
979 [MASTER_OXILI] = &mas_oxili,
980 [MASTER_MDP_PORT0] = &mas_mdp,
981 [MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
982 [MASTER_TCU_0] = &mas_tcu_0,
983 [SLAVE_EBI_CH0] = &slv_ebi,
984 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
987 static struct qcom_icc_desc qcs404_bimc = {
988 .nodes = qcs404_bimc_nodes,
989 .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
992 static struct qcom_icc_node *qcs404_pcnoc_nodes[] = {
993 [MASTER_SPDM] = &mas_spdm,
994 [MASTER_BLSP_1] = &mas_blsp_1,
995 [MASTER_BLSP_2] = &mas_blsp_2,
996 [MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
997 [MASTER_CRYPT0] = &mas_crypto,
998 [MASTER_SDCC_1] = &mas_sdcc_1,
999 [MASTER_SDCC_2] = &mas_sdcc_2,
1000 [MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
1001 [MASTER_QPIC] = &mas_qpic,
1002 [PCNOC_INT_0] = &pcnoc_int_0,
1003 [PCNOC_INT_2] = &pcnoc_int_2,
1004 [PCNOC_INT_3] = &pcnoc_int_3,
1005 [PCNOC_S_0] = &pcnoc_s_0,
1006 [PCNOC_S_1] = &pcnoc_s_1,
1007 [PCNOC_S_2] = &pcnoc_s_2,
1008 [PCNOC_S_3] = &pcnoc_s_3,
1009 [PCNOC_S_4] = &pcnoc_s_4,
1010 [PCNOC_S_6] = &pcnoc_s_6,
1011 [PCNOC_S_7] = &pcnoc_s_7,
1012 [PCNOC_S_8] = &pcnoc_s_8,
1013 [PCNOC_S_9] = &pcnoc_s_9,
1014 [PCNOC_S_10] = &pcnoc_s_10,
1015 [PCNOC_S_11] = &pcnoc_s_11,
1016 [SLAVE_SPDM] = &slv_spdm,
1017 [SLAVE_PDM] = &slv_pdm,
1018 [SLAVE_PRNG] = &slv_prng,
1019 [SLAVE_TCSR] = &slv_tcsr,
1020 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1021 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1022 [SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
1023 [SLAVE_GPU_CFG] = &slv_gpu_cfg,
1024 [SLAVE_BLSP_1] = &slv_blsp_1,
1025 [SLAVE_BLSP_2] = &slv_blsp_2,
1026 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1027 [SLAVE_PCIE] = &slv_pcie,
1028 [SLAVE_ETHERNET] = &slv_ethernet,
1029 [SLAVE_TLMM_EAST] = &slv_tlmm_east,
1030 [SLAVE_TCU] = &slv_tcu,
1031 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1032 [SLAVE_SDCC_1] = &slv_sdcc_1,
1033 [SLAVE_SDCC_2] = &slv_sdcc_2,
1034 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1035 [SLAVE_USB_HS] = &slv_usb_hs,
1036 [SLAVE_USB3] = &slv_usb3,
1037 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1038 [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
1041 static struct qcom_icc_desc qcs404_pcnoc = {
1042 .nodes = qcs404_pcnoc_nodes,
1043 .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
1046 static struct qcom_icc_node *qcs404_snoc_nodes[] = {
1047 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1048 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1049 [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
1050 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1051 [MASTER_EMAC] = &mas_emac,
1052 [MASTER_PCIE] = &mas_pcie,
1053 [MASTER_USB3] = &mas_usb3,
1054 [QDSS_INT] = &qdss_int,
1055 [SNOC_INT_0] = &snoc_int_0,
1056 [SNOC_INT_1] = &snoc_int_1,
1057 [SNOC_INT_2] = &snoc_int_2,
1058 [SLAVE_KPSS_AHB] = &slv_kpss_ahb,
1059 [SLAVE_WCSS] = &slv_wcss,
1060 [SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
1061 [SLAVE_IMEM] = &slv_imem,
1062 [SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
1063 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1064 [SLAVE_CATS_0] = &slv_cats_0,
1065 [SLAVE_CATS_1] = &slv_cats_1,
1066 [SLAVE_LPASS] = &slv_lpass,
1069 static struct qcom_icc_desc qcs404_snoc = {
1070 .nodes = qcs404_snoc_nodes,
1071 .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
1075 static const struct of_device_id qcs404_noc_of_match[] = {
1076 { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
1077 { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
1078 { .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
1081 MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
1083 static struct platform_driver qcs404_noc_driver = {
1084 .probe = qnoc_probe,
1085 .remove = qnoc_remove,
1087 .name = "qnoc-qcs404",
1088 .of_match_table = qcs404_noc_of_match,
1091 module_platform_driver(qcs404_noc_driver);
1092 MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
1093 MODULE_LICENSE("GPL v2");