drivers/interconnect/qcom/osm-l3.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/interconnect-provider.h>
   9 #include <linux/io.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16
  17 #include "sc7180.h"
  18 #include "sc8180x.h"
  19 #include "sdm845.h"
  20 #include "sm8150.h"
  21 #include "sm8250.h"
  22
  23 #define LUT_MAX_ENTRIES                 40U
  24 #define LUT_SRC                         GENMASK(31, 30)
  25 #define LUT_L_VAL                       GENMASK(7, 0)
  26 #define CLK_HW_DIV                      2
  27
  28 /* OSM Register offsets */
  29 #define REG_ENABLE                      0x0
  30 #define OSM_LUT_ROW_SIZE                32
  31 #define OSM_REG_FREQ_LUT                0x110
  32 #define OSM_REG_PERF_STATE              0x920
  33
  34 /* EPSS Register offsets */
  35 #define EPSS_LUT_ROW_SIZE               4
  36 #define EPSS_REG_FREQ_LUT               0x100
  37 #define EPSS_REG_PERF_STATE             0x320
  38
  39 #define OSM_L3_MAX_LINKS                1
  40
  41 #define to_osm_l3_provider(_provider) \
  42         container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
  43
  44 struct qcom_osm_l3_icc_provider {
  45         void __iomem *base;
  46         unsigned int max_state;
  47         unsigned int reg_perf_state;
  48         unsigned long lut_tables[LUT_MAX_ENTRIES];
  49         struct icc_provider provider;
  50 };
  51
  52 /**
  53  * struct qcom_osm_l3_node - Qualcomm specific interconnect nodes
  54  * @name: the node name used in debugfs
  55  * @links: an array of nodes where we can go next while traversing
  56  * @id: a unique node identifier
  57  * @num_links: the total number of @links
  58  * @buswidth: width of the interconnect between a node and the bus
  59  */
  60 struct qcom_osm_l3_node {
  61         const char *name;
  62         u16 links[OSM_L3_MAX_LINKS];
  63         u16 id;
  64         u16 num_links;
  65         u16 buswidth;
  66 };
  67
  68 struct qcom_osm_l3_desc {
  69         const struct qcom_osm_l3_node **nodes;
  70         size_t num_nodes;
  71         unsigned int lut_row_size;
  72         unsigned int reg_freq_lut;
  73         unsigned int reg_perf_state;
  74 };
  75
  76 #define DEFINE_QNODE(_name, _id, _buswidth, ...)                        \
  77         static const struct qcom_osm_l3_node _name = {                  \
  78                 .name = #_name,                                         \
  79                 .id = _id,                                              \
  80                 .buswidth = _buswidth,                                  \
  81                 .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),      \
  82                 .links = { __VA_ARGS__ },                               \
  83         }
  84
  85 DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
  86 DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
  87
  88 static const struct qcom_osm_l3_node *sdm845_osm_l3_nodes[] = {
  89         [MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
  90         [SLAVE_OSM_L3] = &sdm845_osm_l3,
  91 };
  92
  93 static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
  94         .nodes = sdm845_osm_l3_nodes,
  95         .num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
  96         .lut_row_size = OSM_LUT_ROW_SIZE,
  97         .reg_freq_lut = OSM_REG_FREQ_LUT,
  98         .reg_perf_state = OSM_REG_PERF_STATE,
  99 };
 100
 101 DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
 102 DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
 103
 104 static const struct qcom_osm_l3_node *sc7180_osm_l3_nodes[] = {
 105         [MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
 106         [SLAVE_OSM_L3] = &sc7180_osm_l3,
 107 };
 108
 109 static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
 110         .nodes = sc7180_osm_l3_nodes,
 111         .num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
 112         .lut_row_size = OSM_LUT_ROW_SIZE,
 113         .reg_freq_lut = OSM_REG_FREQ_LUT,
 114         .reg_perf_state = OSM_REG_PERF_STATE,
 115 };
 116
 117 DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
 118 DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
 119
 120 static const struct qcom_osm_l3_node *sc8180x_osm_l3_nodes[] = {
 121         [MASTER_OSM_L3_APPS] = &sc8180x_osm_apps_l3,
 122         [SLAVE_OSM_L3] = &sc8180x_osm_l3,
 123 };
 124
 125 static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = {
 126         .nodes = sc8180x_osm_l3_nodes,
 127         .num_nodes = ARRAY_SIZE(sc8180x_osm_l3_nodes),
 128         .lut_row_size = OSM_LUT_ROW_SIZE,
 129         .reg_freq_lut = OSM_REG_FREQ_LUT,
 130         .reg_perf_state = OSM_REG_PERF_STATE,
 131 };
 132
 133 DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
 134 DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
 135
 136 static const struct qcom_osm_l3_node *sm8150_osm_l3_nodes[] = {
 137         [MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
 138         [SLAVE_OSM_L3] = &sm8150_osm_l3,
 139 };
 140
 141 static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = {
 142         .nodes = sm8150_osm_l3_nodes,
 143         .num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
 144         .lut_row_size = OSM_LUT_ROW_SIZE,
 145         .reg_freq_lut = OSM_REG_FREQ_LUT,
 146         .reg_perf_state = OSM_REG_PERF_STATE,
 147 };
 148
 149 DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
 150 DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
 151
 152 static const struct qcom_osm_l3_node *sm8250_epss_l3_nodes[] = {
 153         [MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
 154         [SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
 155 };
 156
 157 static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
 158         .nodes = sm8250_epss_l3_nodes,
 159         .num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
 160         .lut_row_size = EPSS_LUT_ROW_SIZE,
 161         .reg_freq_lut = EPSS_REG_FREQ_LUT,
 162         .reg_perf_state = EPSS_REG_PERF_STATE,
 163 };
 164
 165 static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 166 {
 167         struct qcom_osm_l3_icc_provider *qp;
 168         struct icc_provider *provider;
 169         const struct qcom_osm_l3_node *qn;
 170         struct icc_node *n;
 171         unsigned int index;
 172         u32 agg_peak = 0;
 173         u32 agg_avg = 0;
 174         u64 rate;
 175
 176         qn = src->data;
 177         provider = src->provider;
 178         qp = to_osm_l3_provider(provider);
 179
 180         list_for_each_entry(n, &provider->nodes, node_list)
 181                 provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
 182                                     &agg_avg, &agg_peak);
 183
 184         rate = max(agg_avg, agg_peak);
 185         rate = icc_units_to_bps(rate);
 186         do_div(rate, qn->buswidth);
 187
 188         for (index = 0; index < qp->max_state - 1; index++) {
 189                 if (qp->lut_tables[index] >= rate)
 190                         break;
 191         }
 192
 193         writel_relaxed(index, qp->base + qp->reg_perf_state);
 194
 195         return 0;
 196 }
 197
 198 static int qcom_osm_l3_remove(struct platform_device *pdev)
 199 {
 200         struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);
 201
 202         icc_nodes_remove(&qp->provider);
 203         return icc_provider_del(&qp->provider);
 204 }
 205
 206 static int qcom_osm_l3_probe(struct platform_device *pdev)
 207 {
 208         u32 info, src, lval, i, prev_freq = 0, freq;
 209         static unsigned long hw_rate, xo_rate;
 210         struct qcom_osm_l3_icc_provider *qp;
 211         const struct qcom_osm_l3_desc *desc;
 212         struct icc_onecell_data *data;
 213         struct icc_provider *provider;
 214         const struct qcom_osm_l3_node **qnodes;
 215         struct icc_node *node;
 216         size_t num_nodes;
 217         struct clk *clk;
 218         int ret;
 219
 220         clk = clk_get(&pdev->dev, "xo");
 221         if (IS_ERR(clk))
 222                 return PTR_ERR(clk);
 223
 224         xo_rate = clk_get_rate(clk);
 225         clk_put(clk);
 226
 227         clk = clk_get(&pdev->dev, "alternate");
 228         if (IS_ERR(clk))
 229                 return PTR_ERR(clk);
 230
 231         hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 232         clk_put(clk);
 233
 234         qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
 235         if (!qp)
 236                 return -ENOMEM;
 237
 238         qp->base = devm_platform_ioremap_resource(pdev, 0);
 239         if (IS_ERR(qp->base))
 240                 return PTR_ERR(qp->base);
 241
 242         /* HW should be in enabled state to proceed */
 243         if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
 244                 dev_err(&pdev->dev, "error hardware not enabled\n");
 245                 return -ENODEV;
 246         }
 247
 248         desc = device_get_match_data(&pdev->dev);
 249         if (!desc)
 250                 return -EINVAL;
 251
 252         qp->reg_perf_state = desc->reg_perf_state;
 253
 254         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 255                 info = readl_relaxed(qp->base + desc->reg_freq_lut +
 256                                      i * desc->lut_row_size);
 257                 src = FIELD_GET(LUT_SRC, info);
 258                 lval = FIELD_GET(LUT_L_VAL, info);
 259                 if (src)
 260                         freq = xo_rate * lval;
 261                 else
 262                         freq = hw_rate;
 263
 264                 /* Two of the same frequencies signify end of table */
 265                 if (i > 0 && prev_freq == freq)
 266                         break;
 267
 268                 dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq);
 269
 270                 qp->lut_tables[i] = freq;
 271                 prev_freq = freq;
 272         }
 273         qp->max_state = i;
 274
 275         qnodes = desc->nodes;
 276         num_nodes = desc->num_nodes;
 277
 278         data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
 279         if (!data)
 280                 return -ENOMEM;
 281
 282         provider = &qp->provider;
 283         provider->dev = &pdev->dev;
 284         provider->set = qcom_osm_l3_set;
 285         provider->aggregate = icc_std_aggregate;
 286         provider->xlate = of_icc_xlate_onecell;
 287         INIT_LIST_HEAD(&provider->nodes);
 288         provider->data = data;
 289
 290         ret = icc_provider_add(provider);
 291         if (ret) {
 292                 dev_err(&pdev->dev, "error adding interconnect provider\n");
 293                 return ret;
 294         }
 295
 296         for (i = 0; i < num_nodes; i++) {
 297                 size_t j;
 298
 299                 node = icc_node_create(qnodes[i]->id);
 300                 if (IS_ERR(node)) {
 301                         ret = PTR_ERR(node);
 302                         goto err;
 303                 }
 304
 305                 node->name = qnodes[i]->name;
 306                 /* Cast away const and add it back in qcom_osm_l3_set() */
 307                 node->data = (void *)qnodes[i];
 308                 icc_node_add(node, provider);
 309
 310                 for (j = 0; j < qnodes[i]->num_links; j++)
 311                         icc_link_create(node, qnodes[i]->links[j]);
 312
 313                 data->nodes[i] = node;
 314         }
 315         data->num_nodes = num_nodes;
 316
 317         platform_set_drvdata(pdev, qp);
 318
 319         return 0;
 320 err:
 321         icc_nodes_remove(provider);
 322         icc_provider_del(provider);
 323
 324         return ret;
 325 }
 326
 327 static const struct of_device_id osm_l3_of_match[] = {
 328         { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
 329         { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
 330         { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
 331         { .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
 332         { .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
 333         { }
 334 };
 335 MODULE_DEVICE_TABLE(of, osm_l3_of_match);
 336
 337 static struct platform_driver osm_l3_driver = {
 338         .probe = qcom_osm_l3_probe,
 339         .remove = qcom_osm_l3_remove,
 340         .driver = {
 341                 .name = "osm-l3",
 342                 .of_match_table = osm_l3_of_match,
 343                 .sync_state = icc_sync_state,
 344         },
 345 };
 346 module_platform_driver(osm_l3_driver);
 347
 348 MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver");
 349 MODULE_LICENSE("GPL v2");