1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm MSM8996 Network-on-Chip (NoC) QoS driver
5 * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
9 #include <linux/device.h>
10 #include <linux/interconnect-provider.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
18 #include <dt-bindings/interconnect/qcom,msm8996.h>
24 static const char * const bus_mm_clocks[] = {
30 static const char * const bus_a0noc_clocks[] = {
36 static const u16 mas_a0noc_common_links[] = {
37 MSM8996_SLAVE_A0NOC_SNOC
40 static struct qcom_icc_node mas_pcie_0 = {
42 .id = MSM8996_MASTER_PCIE_0,
47 .qos.qos_mode = NOC_QOS_MODE_FIXED,
51 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
52 .links = mas_a0noc_common_links
55 static struct qcom_icc_node mas_pcie_1 = {
57 .id = MSM8996_MASTER_PCIE_1,
62 .qos.qos_mode = NOC_QOS_MODE_FIXED,
66 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
67 .links = mas_a0noc_common_links
70 static struct qcom_icc_node mas_pcie_2 = {
72 .id = MSM8996_MASTER_PCIE_2,
77 .qos.qos_mode = NOC_QOS_MODE_FIXED,
81 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
82 .links = mas_a0noc_common_links
85 static const u16 mas_a1noc_common_links[] = {
86 MSM8996_SLAVE_A1NOC_SNOC
89 static struct qcom_icc_node mas_cnoc_a1noc = {
90 .name = "mas_cnoc_a1noc",
91 .id = MSM8996_MASTER_CNOC_A1NOC,
96 .qos.qos_mode = NOC_QOS_MODE_INVALID,
97 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
98 .links = mas_a1noc_common_links
101 static struct qcom_icc_node mas_crypto_c0 = {
102 .name = "mas_crypto_c0",
103 .id = MSM8996_MASTER_CRYPTO_CORE0,
107 .qos.ap_owned = true,
108 .qos.qos_mode = NOC_QOS_MODE_FIXED,
112 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
113 .links = mas_a1noc_common_links
116 static struct qcom_icc_node mas_pnoc_a1noc = {
117 .name = "mas_pnoc_a1noc",
118 .id = MSM8996_MASTER_PNOC_A1NOC,
122 .qos.ap_owned = false,
123 .qos.qos_mode = NOC_QOS_MODE_FIXED,
127 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
128 .links = mas_a1noc_common_links
131 static const u16 mas_a2noc_common_links[] = {
132 MSM8996_SLAVE_A2NOC_SNOC
135 static struct qcom_icc_node mas_usb3 = {
137 .id = MSM8996_MASTER_USB3,
141 .qos.ap_owned = true,
142 .qos.qos_mode = NOC_QOS_MODE_FIXED,
146 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
147 .links = mas_a2noc_common_links
150 static struct qcom_icc_node mas_ipa = {
152 .id = MSM8996_MASTER_IPA,
156 .qos.ap_owned = true,
157 .qos.qos_mode = NOC_QOS_MODE_FIXED,
161 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
162 .links = mas_a2noc_common_links
165 static struct qcom_icc_node mas_ufs = {
167 .id = MSM8996_MASTER_UFS,
171 .qos.ap_owned = true,
172 .qos.qos_mode = NOC_QOS_MODE_FIXED,
176 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
177 .links = mas_a2noc_common_links
180 static const u16 mas_apps_proc_links[] = {
181 MSM8996_SLAVE_BIMC_SNOC_1,
182 MSM8996_SLAVE_EBI_CH0,
183 MSM8996_SLAVE_BIMC_SNOC_0
186 static struct qcom_icc_node mas_apps_proc = {
187 .name = "mas_apps_proc",
188 .id = MSM8996_MASTER_AMPSS_M0,
192 .qos.ap_owned = true,
193 .qos.qos_mode = NOC_QOS_MODE_FIXED,
197 .num_links = ARRAY_SIZE(mas_apps_proc_links),
198 .links = mas_apps_proc_links
201 static const u16 mas_oxili_common_links[] = {
202 MSM8996_SLAVE_BIMC_SNOC_1,
203 MSM8996_SLAVE_HMSS_L3,
204 MSM8996_SLAVE_EBI_CH0,
205 MSM8996_SLAVE_BIMC_SNOC_0
208 static struct qcom_icc_node mas_oxili = {
210 .id = MSM8996_MASTER_GRAPHICS_3D,
214 .qos.ap_owned = true,
215 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
219 .num_links = ARRAY_SIZE(mas_oxili_common_links),
220 .links = mas_oxili_common_links
223 static struct qcom_icc_node mas_mnoc_bimc = {
224 .name = "mas_mnoc_bimc",
225 .id = MSM8996_MASTER_MNOC_BIMC,
229 .qos.ap_owned = true,
230 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
234 .num_links = ARRAY_SIZE(mas_oxili_common_links),
235 .links = mas_oxili_common_links
238 static const u16 mas_snoc_bimc_links[] = {
239 MSM8996_SLAVE_HMSS_L3,
240 MSM8996_SLAVE_EBI_CH0
243 static struct qcom_icc_node mas_snoc_bimc = {
244 .name = "mas_snoc_bimc",
245 .id = MSM8996_MASTER_SNOC_BIMC,
249 .qos.ap_owned = false,
250 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
254 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
255 .links = mas_snoc_bimc_links
258 static const u16 mas_snoc_cnoc_links[] = {
259 MSM8996_SLAVE_CLK_CTL,
260 MSM8996_SLAVE_RBCPR_CX,
261 MSM8996_SLAVE_A2NOC_SMMU_CFG,
262 MSM8996_SLAVE_A0NOC_MPU_CFG,
263 MSM8996_SLAVE_MESSAGE_RAM,
264 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
265 MSM8996_SLAVE_PCIE_0_CFG,
268 MSM8996_SLAVE_A0NOC_SMMU_CFG,
269 MSM8996_SLAVE_EBI1_PHY_CFG,
270 MSM8996_SLAVE_BIMC_CFG,
271 MSM8996_SLAVE_PIMEM_CFG,
272 MSM8996_SLAVE_RBCPR_MX,
274 MSM8996_SLAVE_PCIE20_AHB2PHY,
275 MSM8996_SLAVE_A2NOC_MPU_CFG,
276 MSM8996_SLAVE_QDSS_CFG,
277 MSM8996_SLAVE_A2NOC_CFG,
278 MSM8996_SLAVE_A0NOC_CFG,
279 MSM8996_SLAVE_UFS_CFG,
280 MSM8996_SLAVE_CRYPTO_0_CFG,
281 MSM8996_SLAVE_PCIE_1_CFG,
282 MSM8996_SLAVE_SNOC_CFG,
283 MSM8996_SLAVE_SNOC_MPU_CFG,
284 MSM8996_SLAVE_A1NOC_MPU_CFG,
285 MSM8996_SLAVE_A1NOC_SMMU_CFG,
286 MSM8996_SLAVE_PCIE_2_CFG,
287 MSM8996_SLAVE_CNOC_MNOC_CFG,
288 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
289 MSM8996_SLAVE_PMIC_ARB,
290 MSM8996_SLAVE_IMEM_CFG,
291 MSM8996_SLAVE_A1NOC_CFG,
292 MSM8996_SLAVE_SSC_CFG,
294 MSM8996_SLAVE_LPASS_SMMU_CFG,
295 MSM8996_SLAVE_DCC_CFG
298 static struct qcom_icc_node mas_snoc_cnoc = {
299 .name = "mas_snoc_cnoc",
300 .id = MSM8996_MASTER_SNOC_CNOC,
304 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
305 .links = mas_snoc_cnoc_links
308 static const u16 mas_qdss_dap_links[] = {
309 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
310 MSM8996_SLAVE_RBCPR_CX,
311 MSM8996_SLAVE_A2NOC_SMMU_CFG,
312 MSM8996_SLAVE_A0NOC_MPU_CFG,
313 MSM8996_SLAVE_MESSAGE_RAM,
314 MSM8996_SLAVE_PCIE_0_CFG,
317 MSM8996_SLAVE_A0NOC_SMMU_CFG,
318 MSM8996_SLAVE_EBI1_PHY_CFG,
319 MSM8996_SLAVE_BIMC_CFG,
320 MSM8996_SLAVE_PIMEM_CFG,
321 MSM8996_SLAVE_RBCPR_MX,
322 MSM8996_SLAVE_CLK_CTL,
324 MSM8996_SLAVE_PCIE20_AHB2PHY,
325 MSM8996_SLAVE_A2NOC_MPU_CFG,
326 MSM8996_SLAVE_QDSS_CFG,
327 MSM8996_SLAVE_A2NOC_CFG,
328 MSM8996_SLAVE_A0NOC_CFG,
329 MSM8996_SLAVE_UFS_CFG,
330 MSM8996_SLAVE_CRYPTO_0_CFG,
331 MSM8996_SLAVE_CNOC_A1NOC,
332 MSM8996_SLAVE_PCIE_1_CFG,
333 MSM8996_SLAVE_SNOC_CFG,
334 MSM8996_SLAVE_SNOC_MPU_CFG,
335 MSM8996_SLAVE_A1NOC_MPU_CFG,
336 MSM8996_SLAVE_A1NOC_SMMU_CFG,
337 MSM8996_SLAVE_PCIE_2_CFG,
338 MSM8996_SLAVE_CNOC_MNOC_CFG,
339 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
340 MSM8996_SLAVE_PMIC_ARB,
341 MSM8996_SLAVE_IMEM_CFG,
342 MSM8996_SLAVE_A1NOC_CFG,
343 MSM8996_SLAVE_SSC_CFG,
345 MSM8996_SLAVE_LPASS_SMMU_CFG,
346 MSM8996_SLAVE_DCC_CFG
349 static struct qcom_icc_node mas_qdss_dap = {
350 .name = "mas_qdss_dap",
351 .id = MSM8996_MASTER_QDSS_DAP,
355 .qos.ap_owned = true,
356 .qos.qos_mode = NOC_QOS_MODE_INVALID,
357 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
358 .links = mas_qdss_dap_links
361 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
362 MSM8996_SLAVE_MMAGIC_CFG,
363 MSM8996_SLAVE_DSA_MPU_CFG,
364 MSM8996_SLAVE_MMSS_CLK_CFG,
365 MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
366 MSM8996_SLAVE_VENUS_CFG,
367 MSM8996_SLAVE_SMMU_VFE_CFG,
368 MSM8996_SLAVE_MISC_CFG,
369 MSM8996_SLAVE_SMMU_CPP_CFG,
370 MSM8996_SLAVE_GRAPHICS_3D_CFG,
371 MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
372 MSM8996_SLAVE_VENUS_THROTTLE_CFG,
373 MSM8996_SLAVE_CAMERA_CFG,
374 MSM8996_SLAVE_DISPLAY_CFG,
375 MSM8996_SLAVE_CPR_CFG,
376 MSM8996_SLAVE_SMMU_ROTATOR_CFG,
377 MSM8996_SLAVE_DSA_CFG,
378 MSM8996_SLAVE_SMMU_VENUS_CFG,
379 MSM8996_SLAVE_VMEM_CFG,
380 MSM8996_SLAVE_SMMU_JPEG_CFG,
381 MSM8996_SLAVE_SMMU_MDP_CFG,
382 MSM8996_SLAVE_MNOC_MPU_CFG
385 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
386 .name = "mas_cnoc_mnoc_mmss_cfg",
387 .id = MSM8996_MASTER_CNOC_MNOC_MMSS_CFG,
391 .qos.ap_owned = true,
392 .qos.qos_mode = NOC_QOS_MODE_INVALID,
393 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
394 .links = mas_cnoc_mnoc_mmss_cfg_links
397 static const u16 mas_cnoc_mnoc_cfg_links[] = {
398 MSM8996_SLAVE_SERVICE_MNOC
401 static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
402 .name = "mas_cnoc_mnoc_cfg",
403 .id = MSM8996_MASTER_CNOC_MNOC_CFG,
407 .qos.ap_owned = true,
408 .qos.qos_mode = NOC_QOS_MODE_INVALID,
409 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
410 .links = mas_cnoc_mnoc_cfg_links
413 static const u16 mas_mnoc_bimc_common_links[] = {
414 MSM8996_SLAVE_MNOC_BIMC
417 static struct qcom_icc_node mas_cpp = {
419 .id = MSM8996_MASTER_CPP,
423 .qos.ap_owned = true,
424 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
428 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
429 .links = mas_mnoc_bimc_common_links
432 static struct qcom_icc_node mas_jpeg = {
434 .id = MSM8996_MASTER_JPEG,
438 .qos.ap_owned = true,
439 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
443 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
444 .links = mas_mnoc_bimc_common_links
447 static struct qcom_icc_node mas_mdp_p0 = {
448 .name = "mas_mdp_p0",
449 .id = MSM8996_MASTER_MDP_PORT0,
453 .qos.ap_owned = true,
454 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
458 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
459 .links = mas_mnoc_bimc_common_links
462 static struct qcom_icc_node mas_mdp_p1 = {
463 .name = "mas_mdp_p1",
464 .id = MSM8996_MASTER_MDP_PORT1,
468 .qos.ap_owned = true,
469 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
473 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
474 .links = mas_mnoc_bimc_common_links
477 static struct qcom_icc_node mas_rotator = {
478 .name = "mas_rotator",
479 .id = MSM8996_MASTER_ROTATOR,
483 .qos.ap_owned = true,
484 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
488 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
489 .links = mas_mnoc_bimc_common_links
492 static struct qcom_icc_node mas_venus = {
494 .id = MSM8996_MASTER_VIDEO_P0,
498 .qos.ap_owned = true,
499 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
503 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
504 .links = mas_mnoc_bimc_common_links
507 static struct qcom_icc_node mas_vfe = {
509 .id = MSM8996_MASTER_VFE,
513 .qos.ap_owned = true,
514 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
518 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
519 .links = mas_mnoc_bimc_common_links
522 static const u16 mas_vmem_common_links[] = {
526 static struct qcom_icc_node mas_snoc_vmem = {
527 .name = "mas_snoc_vmem",
528 .id = MSM8996_MASTER_SNOC_VMEM,
532 .qos.ap_owned = true,
533 .qos.qos_mode = NOC_QOS_MODE_INVALID,
534 .num_links = ARRAY_SIZE(mas_vmem_common_links),
535 .links = mas_vmem_common_links
538 static struct qcom_icc_node mas_venus_vmem = {
539 .name = "mas_venus_vmem",
540 .id = MSM8996_MASTER_VIDEO_P0_OCMEM,
544 .qos.ap_owned = true,
545 .qos.qos_mode = NOC_QOS_MODE_INVALID,
546 .num_links = ARRAY_SIZE(mas_vmem_common_links),
547 .links = mas_vmem_common_links
550 static const u16 mas_snoc_pnoc_links[] = {
551 MSM8996_SLAVE_BLSP_1,
552 MSM8996_SLAVE_BLSP_2,
553 MSM8996_SLAVE_SDCC_1,
554 MSM8996_SLAVE_SDCC_2,
555 MSM8996_SLAVE_SDCC_4,
558 MSM8996_SLAVE_AHB2PHY
561 static struct qcom_icc_node mas_snoc_pnoc = {
562 .name = "mas_snoc_pnoc",
563 .id = MSM8996_MASTER_SNOC_PNOC,
567 .num_links = ARRAY_SIZE(mas_snoc_pnoc_links),
568 .links = mas_snoc_pnoc_links
571 static const u16 mas_pnoc_a1noc_common_links[] = {
572 MSM8996_SLAVE_PNOC_A1NOC
575 static struct qcom_icc_node mas_sdcc_1 = {
576 .name = "mas_sdcc_1",
577 .id = MSM8996_MASTER_SDCC_1,
581 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
582 .links = mas_pnoc_a1noc_common_links
585 static struct qcom_icc_node mas_sdcc_2 = {
586 .name = "mas_sdcc_2",
587 .id = MSM8996_MASTER_SDCC_2,
591 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
592 .links = mas_pnoc_a1noc_common_links
595 static struct qcom_icc_node mas_sdcc_4 = {
596 .name = "mas_sdcc_4",
597 .id = MSM8996_MASTER_SDCC_4,
601 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
602 .links = mas_pnoc_a1noc_common_links
605 static struct qcom_icc_node mas_usb_hs = {
606 .name = "mas_usb_hs",
607 .id = MSM8996_MASTER_USB_HS,
611 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
612 .links = mas_pnoc_a1noc_common_links
615 static struct qcom_icc_node mas_blsp_1 = {
616 .name = "mas_blsp_1",
617 .id = MSM8996_MASTER_BLSP_1,
621 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
622 .links = mas_pnoc_a1noc_common_links
625 static struct qcom_icc_node mas_blsp_2 = {
626 .name = "mas_blsp_2",
627 .id = MSM8996_MASTER_BLSP_2,
631 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
632 .links = mas_pnoc_a1noc_common_links
635 static struct qcom_icc_node mas_tsif = {
637 .id = MSM8996_MASTER_TSIF,
641 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
642 .links = mas_pnoc_a1noc_common_links
645 static const u16 mas_hmss_links[] = {
647 MSM8996_SLAVE_OCIMEM,
648 MSM8996_SLAVE_SNOC_BIMC
651 static struct qcom_icc_node mas_hmss = {
653 .id = MSM8996_MASTER_HMSS,
657 .qos.ap_owned = true,
658 .qos.qos_mode = NOC_QOS_MODE_FIXED,
662 .num_links = ARRAY_SIZE(mas_hmss_links),
663 .links = mas_hmss_links
666 static const u16 mas_qdss_common_links[] = {
669 MSM8996_SLAVE_OCIMEM,
670 MSM8996_SLAVE_SNOC_BIMC,
671 MSM8996_SLAVE_SNOC_PNOC
674 static struct qcom_icc_node mas_qdss_bam = {
675 .name = "mas_qdss_bam",
676 .id = MSM8996_MASTER_QDSS_BAM,
680 .qos.ap_owned = true,
681 .qos.qos_mode = NOC_QOS_MODE_FIXED,
685 .num_links = ARRAY_SIZE(mas_qdss_common_links),
686 .links = mas_qdss_common_links
689 static const u16 mas_snoc_cfg_links[] = {
690 MSM8996_SLAVE_SERVICE_SNOC
693 static struct qcom_icc_node mas_snoc_cfg = {
694 .name = "mas_snoc_cfg",
695 .id = MSM8996_MASTER_SNOC_CFG,
699 .qos.ap_owned = true,
700 .qos.qos_mode = NOC_QOS_MODE_INVALID,
701 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
702 .links = mas_snoc_cfg_links
705 static const u16 mas_bimc_snoc_0_links[] = {
706 MSM8996_SLAVE_SNOC_VMEM,
711 MSM8996_SLAVE_SNOC_CNOC,
712 MSM8996_SLAVE_SNOC_PNOC,
713 MSM8996_SLAVE_OCIMEM,
714 MSM8996_SLAVE_QDSS_STM
717 static struct qcom_icc_node mas_bimc_snoc_0 = {
718 .name = "mas_bimc_snoc_0",
719 .id = MSM8996_MASTER_BIMC_SNOC_0,
723 .qos.ap_owned = true,
724 .qos.qos_mode = NOC_QOS_MODE_INVALID,
725 .num_links = ARRAY_SIZE(mas_bimc_snoc_0_links),
726 .links = mas_bimc_snoc_0_links
729 static const u16 mas_bimc_snoc_1_links[] = {
730 MSM8996_SLAVE_PCIE_2,
731 MSM8996_SLAVE_PCIE_1,
735 static struct qcom_icc_node mas_bimc_snoc_1 = {
736 .name = "mas_bimc_snoc_1",
737 .id = MSM8996_MASTER_BIMC_SNOC_1,
741 .qos.ap_owned = true,
742 .qos.qos_mode = NOC_QOS_MODE_INVALID,
743 .num_links = ARRAY_SIZE(mas_bimc_snoc_1_links),
744 .links = mas_bimc_snoc_1_links
747 static const u16 mas_a0noc_snoc_links[] = {
748 MSM8996_SLAVE_SNOC_PNOC,
749 MSM8996_SLAVE_OCIMEM,
751 MSM8996_SLAVE_SNOC_BIMC,
755 static struct qcom_icc_node mas_a0noc_snoc = {
756 .name = "mas_a0noc_snoc",
757 .id = MSM8996_MASTER_A0NOC_SNOC,
761 .qos.ap_owned = true,
762 .qos.qos_mode = NOC_QOS_MODE_INVALID,
763 .num_links = ARRAY_SIZE(mas_a0noc_snoc_links),
764 .links = mas_a0noc_snoc_links
767 static const u16 mas_a1noc_snoc_links[] = {
768 MSM8996_SLAVE_SNOC_VMEM,
770 MSM8996_SLAVE_PCIE_0,
772 MSM8996_SLAVE_PCIE_2,
774 MSM8996_SLAVE_PCIE_1,
776 MSM8996_SLAVE_SNOC_BIMC,
777 MSM8996_SLAVE_SNOC_CNOC,
778 MSM8996_SLAVE_SNOC_PNOC,
779 MSM8996_SLAVE_OCIMEM,
780 MSM8996_SLAVE_QDSS_STM
783 static struct qcom_icc_node mas_a1noc_snoc = {
784 .name = "mas_a1noc_snoc",
785 .id = MSM8996_MASTER_A1NOC_SNOC,
789 .num_links = ARRAY_SIZE(mas_a1noc_snoc_links),
790 .links = mas_a1noc_snoc_links
793 static const u16 mas_a2noc_snoc_links[] = {
794 MSM8996_SLAVE_SNOC_VMEM,
796 MSM8996_SLAVE_PCIE_1,
798 MSM8996_SLAVE_PCIE_2,
799 MSM8996_SLAVE_QDSS_STM,
801 MSM8996_SLAVE_SNOC_BIMC,
802 MSM8996_SLAVE_SNOC_CNOC,
803 MSM8996_SLAVE_SNOC_PNOC,
804 MSM8996_SLAVE_OCIMEM,
808 static struct qcom_icc_node mas_a2noc_snoc = {
809 .name = "mas_a2noc_snoc",
810 .id = MSM8996_MASTER_A2NOC_SNOC,
814 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
815 .links = mas_a2noc_snoc_links
818 static struct qcom_icc_node mas_qdss_etr = {
819 .name = "mas_qdss_etr",
820 .id = MSM8996_MASTER_QDSS_ETR,
824 .qos.ap_owned = true,
825 .qos.qos_mode = NOC_QOS_MODE_FIXED,
829 .num_links = ARRAY_SIZE(mas_qdss_common_links),
830 .links = mas_qdss_common_links
833 static const u16 slv_a0noc_snoc_links[] = {
834 MSM8996_MASTER_A0NOC_SNOC
837 static struct qcom_icc_node slv_a0noc_snoc = {
838 .name = "slv_a0noc_snoc",
839 .id = MSM8996_SLAVE_A0NOC_SNOC,
843 .qos.ap_owned = true,
844 .qos.qos_mode = NOC_QOS_MODE_INVALID,
845 .num_links = ARRAY_SIZE(slv_a0noc_snoc_links),
846 .links = slv_a0noc_snoc_links
849 static const u16 slv_a1noc_snoc_links[] = {
850 MSM8996_MASTER_A1NOC_SNOC
853 static struct qcom_icc_node slv_a1noc_snoc = {
854 .name = "slv_a1noc_snoc",
855 .id = MSM8996_SLAVE_A1NOC_SNOC,
859 .num_links = ARRAY_SIZE(slv_a1noc_snoc_links),
860 .links = slv_a1noc_snoc_links
863 static const u16 slv_a2noc_snoc_links[] = {
864 MSM8996_MASTER_A2NOC_SNOC
867 static struct qcom_icc_node slv_a2noc_snoc = {
868 .name = "slv_a2noc_snoc",
869 .id = MSM8996_SLAVE_A2NOC_SNOC,
873 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
874 .links = slv_a2noc_snoc_links
877 static struct qcom_icc_node slv_ebi = {
879 .id = MSM8996_SLAVE_EBI_CH0,
885 static struct qcom_icc_node slv_hmss_l3 = {
886 .name = "slv_hmss_l3",
887 .id = MSM8996_SLAVE_HMSS_L3,
893 static const u16 slv_bimc_snoc_0_links[] = {
894 MSM8996_MASTER_BIMC_SNOC_0
897 static struct qcom_icc_node slv_bimc_snoc_0 = {
898 .name = "slv_bimc_snoc_0",
899 .id = MSM8996_SLAVE_BIMC_SNOC_0,
903 .qos.ap_owned = true,
904 .qos.qos_mode = NOC_QOS_MODE_INVALID,
905 .num_links = ARRAY_SIZE(slv_bimc_snoc_0_links),
906 .links = slv_bimc_snoc_0_links
909 static const u16 slv_bimc_snoc_1_links[] = {
910 MSM8996_MASTER_BIMC_SNOC_1
913 static struct qcom_icc_node slv_bimc_snoc_1 = {
914 .name = "slv_bimc_snoc_1",
915 .id = MSM8996_SLAVE_BIMC_SNOC_1,
919 .qos.ap_owned = true,
920 .qos.qos_mode = NOC_QOS_MODE_INVALID,
921 .num_links = ARRAY_SIZE(slv_bimc_snoc_1_links),
922 .links = slv_bimc_snoc_1_links
925 static const u16 slv_cnoc_a1noc_links[] = {
926 MSM8996_MASTER_CNOC_A1NOC
929 static struct qcom_icc_node slv_cnoc_a1noc = {
930 .name = "slv_cnoc_a1noc",
931 .id = MSM8996_SLAVE_CNOC_A1NOC,
935 .qos.ap_owned = true,
936 .qos.qos_mode = NOC_QOS_MODE_INVALID,
937 .num_links = ARRAY_SIZE(slv_cnoc_a1noc_links),
938 .links = slv_cnoc_a1noc_links
941 static struct qcom_icc_node slv_clk_ctl = {
942 .name = "slv_clk_ctl",
943 .id = MSM8996_SLAVE_CLK_CTL,
949 static struct qcom_icc_node slv_tcsr = {
951 .id = MSM8996_SLAVE_TCSR,
957 static struct qcom_icc_node slv_tlmm = {
959 .id = MSM8996_SLAVE_TLMM,
965 static struct qcom_icc_node slv_crypto0_cfg = {
966 .name = "slv_crypto0_cfg",
967 .id = MSM8996_SLAVE_CRYPTO_0_CFG,
971 .qos.ap_owned = true,
972 .qos.qos_mode = NOC_QOS_MODE_INVALID
975 static struct qcom_icc_node slv_mpm = {
977 .id = MSM8996_SLAVE_MPM,
981 .qos.ap_owned = true,
982 .qos.qos_mode = NOC_QOS_MODE_INVALID
985 static struct qcom_icc_node slv_pimem_cfg = {
986 .name = "slv_pimem_cfg",
987 .id = MSM8996_SLAVE_PIMEM_CFG,
991 .qos.ap_owned = true,
992 .qos.qos_mode = NOC_QOS_MODE_INVALID
995 static struct qcom_icc_node slv_imem_cfg = {
996 .name = "slv_imem_cfg",
997 .id = MSM8996_SLAVE_IMEM_CFG,
1001 .qos.ap_owned = true,
1002 .qos.qos_mode = NOC_QOS_MODE_INVALID
1005 static struct qcom_icc_node slv_message_ram = {
1006 .name = "slv_message_ram",
1007 .id = MSM8996_SLAVE_MESSAGE_RAM,
1013 static struct qcom_icc_node slv_bimc_cfg = {
1014 .name = "slv_bimc_cfg",
1015 .id = MSM8996_SLAVE_BIMC_CFG,
1019 .qos.ap_owned = true,
1020 .qos.qos_mode = NOC_QOS_MODE_INVALID
1023 static struct qcom_icc_node slv_pmic_arb = {
1024 .name = "slv_pmic_arb",
1025 .id = MSM8996_SLAVE_PMIC_ARB,
1031 static struct qcom_icc_node slv_prng = {
1033 .id = MSM8996_SLAVE_PRNG,
1037 .qos.ap_owned = true,
1038 .qos.qos_mode = NOC_QOS_MODE_INVALID
1041 static struct qcom_icc_node slv_dcc_cfg = {
1042 .name = "slv_dcc_cfg",
1043 .id = MSM8996_SLAVE_DCC_CFG,
1047 .qos.ap_owned = true,
1048 .qos.qos_mode = NOC_QOS_MODE_INVALID
1051 static struct qcom_icc_node slv_rbcpr_mx = {
1052 .name = "slv_rbcpr_mx",
1053 .id = MSM8996_SLAVE_RBCPR_MX,
1057 .qos.ap_owned = true,
1058 .qos.qos_mode = NOC_QOS_MODE_INVALID
1061 static struct qcom_icc_node slv_qdss_cfg = {
1062 .name = "slv_qdss_cfg",
1063 .id = MSM8996_SLAVE_QDSS_CFG,
1067 .qos.ap_owned = true,
1068 .qos.qos_mode = NOC_QOS_MODE_INVALID
1071 static struct qcom_icc_node slv_rbcpr_cx = {
1072 .name = "slv_rbcpr_cx",
1073 .id = MSM8996_SLAVE_RBCPR_CX,
1077 .qos.ap_owned = true,
1078 .qos.qos_mode = NOC_QOS_MODE_INVALID
1081 static struct qcom_icc_node slv_cpu_apu_cfg = {
1082 .name = "slv_cpu_apu_cfg",
1083 .id = MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
1087 .qos.ap_owned = true,
1088 .qos.qos_mode = NOC_QOS_MODE_INVALID
1091 static const u16 slv_cnoc_mnoc_cfg_links[] = {
1092 MSM8996_MASTER_CNOC_MNOC_CFG
1095 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
1096 .name = "slv_cnoc_mnoc_cfg",
1097 .id = MSM8996_SLAVE_CNOC_MNOC_CFG,
1101 .qos.ap_owned = true,
1102 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1103 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
1104 .links = slv_cnoc_mnoc_cfg_links
1107 static struct qcom_icc_node slv_snoc_cfg = {
1108 .name = "slv_snoc_cfg",
1109 .id = MSM8996_SLAVE_SNOC_CFG,
1113 .qos.ap_owned = true,
1114 .qos.qos_mode = NOC_QOS_MODE_INVALID
1117 static struct qcom_icc_node slv_snoc_mpu_cfg = {
1118 .name = "slv_snoc_mpu_cfg",
1119 .id = MSM8996_SLAVE_SNOC_MPU_CFG,
1123 .qos.ap_owned = true,
1124 .qos.qos_mode = NOC_QOS_MODE_INVALID
1127 static struct qcom_icc_node slv_ebi1_phy_cfg = {
1128 .name = "slv_ebi1_phy_cfg",
1129 .id = MSM8996_SLAVE_EBI1_PHY_CFG,
1133 .qos.ap_owned = true,
1134 .qos.qos_mode = NOC_QOS_MODE_INVALID
1137 static struct qcom_icc_node slv_a0noc_cfg = {
1138 .name = "slv_a0noc_cfg",
1139 .id = MSM8996_SLAVE_A0NOC_CFG,
1143 .qos.ap_owned = true,
1144 .qos.qos_mode = NOC_QOS_MODE_INVALID
1147 static struct qcom_icc_node slv_pcie_1_cfg = {
1148 .name = "slv_pcie_1_cfg",
1149 .id = MSM8996_SLAVE_PCIE_1_CFG,
1153 .qos.ap_owned = true,
1154 .qos.qos_mode = NOC_QOS_MODE_INVALID
1157 static struct qcom_icc_node slv_pcie_2_cfg = {
1158 .name = "slv_pcie_2_cfg",
1159 .id = MSM8996_SLAVE_PCIE_2_CFG,
1163 .qos.ap_owned = true,
1164 .qos.qos_mode = NOC_QOS_MODE_INVALID
1167 static struct qcom_icc_node slv_pcie_0_cfg = {
1168 .name = "slv_pcie_0_cfg",
1169 .id = MSM8996_SLAVE_PCIE_0_CFG,
1173 .qos.ap_owned = true,
1174 .qos.qos_mode = NOC_QOS_MODE_INVALID
1177 static struct qcom_icc_node slv_pcie20_ahb2phy = {
1178 .name = "slv_pcie20_ahb2phy",
1179 .id = MSM8996_SLAVE_PCIE20_AHB2PHY,
1183 .qos.ap_owned = true,
1184 .qos.qos_mode = NOC_QOS_MODE_INVALID
1187 static struct qcom_icc_node slv_a0noc_mpu_cfg = {
1188 .name = "slv_a0noc_mpu_cfg",
1189 .id = MSM8996_SLAVE_A0NOC_MPU_CFG,
1193 .qos.ap_owned = true,
1194 .qos.qos_mode = NOC_QOS_MODE_INVALID
1197 static struct qcom_icc_node slv_ufs_cfg = {
1198 .name = "slv_ufs_cfg",
1199 .id = MSM8996_SLAVE_UFS_CFG,
1203 .qos.ap_owned = true,
1204 .qos.qos_mode = NOC_QOS_MODE_INVALID
1207 static struct qcom_icc_node slv_a1noc_cfg = {
1208 .name = "slv_a1noc_cfg",
1209 .id = MSM8996_SLAVE_A1NOC_CFG,
1213 .qos.ap_owned = true,
1214 .qos.qos_mode = NOC_QOS_MODE_INVALID
1217 static struct qcom_icc_node slv_a1noc_mpu_cfg = {
1218 .name = "slv_a1noc_mpu_cfg",
1219 .id = MSM8996_SLAVE_A1NOC_MPU_CFG,
1223 .qos.ap_owned = true,
1224 .qos.qos_mode = NOC_QOS_MODE_INVALID
1227 static struct qcom_icc_node slv_a2noc_cfg = {
1228 .name = "slv_a2noc_cfg",
1229 .id = MSM8996_SLAVE_A2NOC_CFG,
1233 .qos.ap_owned = true,
1234 .qos.qos_mode = NOC_QOS_MODE_INVALID
1237 static struct qcom_icc_node slv_a2noc_mpu_cfg = {
1238 .name = "slv_a2noc_mpu_cfg",
1239 .id = MSM8996_SLAVE_A2NOC_MPU_CFG,
1243 .qos.ap_owned = true,
1244 .qos.qos_mode = NOC_QOS_MODE_INVALID
1247 static struct qcom_icc_node slv_ssc_cfg = {
1248 .name = "slv_ssc_cfg",
1249 .id = MSM8996_SLAVE_SSC_CFG,
1253 .qos.ap_owned = true,
1254 .qos.qos_mode = NOC_QOS_MODE_INVALID
1257 static struct qcom_icc_node slv_a0noc_smmu_cfg = {
1258 .name = "slv_a0noc_smmu_cfg",
1259 .id = MSM8996_SLAVE_A0NOC_SMMU_CFG,
1263 .qos.ap_owned = true,
1264 .qos.qos_mode = NOC_QOS_MODE_INVALID
1267 static struct qcom_icc_node slv_a1noc_smmu_cfg = {
1268 .name = "slv_a1noc_smmu_cfg",
1269 .id = MSM8996_SLAVE_A1NOC_SMMU_CFG,
1273 .qos.ap_owned = true,
1274 .qos.qos_mode = NOC_QOS_MODE_INVALID
1277 static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1278 .name = "slv_a2noc_smmu_cfg",
1279 .id = MSM8996_SLAVE_A2NOC_SMMU_CFG,
1283 .qos.ap_owned = true,
1284 .qos.qos_mode = NOC_QOS_MODE_INVALID
1287 static struct qcom_icc_node slv_lpass_smmu_cfg = {
1288 .name = "slv_lpass_smmu_cfg",
1289 .id = MSM8996_SLAVE_LPASS_SMMU_CFG,
1293 .qos.ap_owned = true,
1294 .qos.qos_mode = NOC_QOS_MODE_INVALID
1297 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1298 MSM8996_MASTER_CNOC_MNOC_MMSS_CFG
1301 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1302 .name = "slv_cnoc_mnoc_mmss_cfg",
1303 .id = MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
1307 .qos.ap_owned = true,
1308 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1309 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1310 .links = slv_cnoc_mnoc_mmss_cfg_links
1313 static struct qcom_icc_node slv_mmagic_cfg = {
1314 .name = "slv_mmagic_cfg",
1315 .id = MSM8996_SLAVE_MMAGIC_CFG,
1319 .qos.ap_owned = true,
1320 .qos.qos_mode = NOC_QOS_MODE_INVALID
1323 static struct qcom_icc_node slv_cpr_cfg = {
1324 .name = "slv_cpr_cfg",
1325 .id = MSM8996_SLAVE_CPR_CFG,
1329 .qos.ap_owned = true,
1330 .qos.qos_mode = NOC_QOS_MODE_INVALID
1333 static struct qcom_icc_node slv_misc_cfg = {
1334 .name = "slv_misc_cfg",
1335 .id = MSM8996_SLAVE_MISC_CFG,
1339 .qos.ap_owned = true,
1340 .qos.qos_mode = NOC_QOS_MODE_INVALID
1343 static struct qcom_icc_node slv_venus_throttle_cfg = {
1344 .name = "slv_venus_throttle_cfg",
1345 .id = MSM8996_SLAVE_VENUS_THROTTLE_CFG,
1349 .qos.ap_owned = true,
1350 .qos.qos_mode = NOC_QOS_MODE_INVALID
1353 static struct qcom_icc_node slv_venus_cfg = {
1354 .name = "slv_venus_cfg",
1355 .id = MSM8996_SLAVE_VENUS_CFG,
1359 .qos.ap_owned = true,
1360 .qos.qos_mode = NOC_QOS_MODE_INVALID
1363 static struct qcom_icc_node slv_vmem_cfg = {
1364 .name = "slv_vmem_cfg",
1365 .id = MSM8996_SLAVE_VMEM_CFG,
1369 .qos.ap_owned = true,
1370 .qos.qos_mode = NOC_QOS_MODE_INVALID
1373 static struct qcom_icc_node slv_dsa_cfg = {
1374 .name = "slv_dsa_cfg",
1375 .id = MSM8996_SLAVE_DSA_CFG,
1379 .qos.ap_owned = true,
1380 .qos.qos_mode = NOC_QOS_MODE_INVALID
1383 static struct qcom_icc_node slv_mnoc_clocks_cfg = {
1384 .name = "slv_mnoc_clocks_cfg",
1385 .id = MSM8996_SLAVE_MMSS_CLK_CFG,
1389 .qos.ap_owned = true,
1390 .qos.qos_mode = NOC_QOS_MODE_INVALID
1393 static struct qcom_icc_node slv_dsa_mpu_cfg = {
1394 .name = "slv_dsa_mpu_cfg",
1395 .id = MSM8996_SLAVE_DSA_MPU_CFG,
1399 .qos.ap_owned = true,
1400 .qos.qos_mode = NOC_QOS_MODE_INVALID
1403 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1404 .name = "slv_mnoc_mpu_cfg",
1405 .id = MSM8996_SLAVE_MNOC_MPU_CFG,
1409 .qos.ap_owned = true,
1410 .qos.qos_mode = NOC_QOS_MODE_INVALID
1413 static struct qcom_icc_node slv_display_cfg = {
1414 .name = "slv_display_cfg",
1415 .id = MSM8996_SLAVE_DISPLAY_CFG,
1419 .qos.ap_owned = true,
1420 .qos.qos_mode = NOC_QOS_MODE_INVALID
1423 static struct qcom_icc_node slv_display_throttle_cfg = {
1424 .name = "slv_display_throttle_cfg",
1425 .id = MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
1429 .qos.ap_owned = true,
1430 .qos.qos_mode = NOC_QOS_MODE_INVALID
1433 static struct qcom_icc_node slv_camera_cfg = {
1434 .name = "slv_camera_cfg",
1435 .id = MSM8996_SLAVE_CAMERA_CFG,
1439 .qos.ap_owned = true,
1440 .qos.qos_mode = NOC_QOS_MODE_INVALID
1443 static struct qcom_icc_node slv_camera_throttle_cfg = {
1444 .name = "slv_camera_throttle_cfg",
1445 .id = MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
1449 .qos.ap_owned = true,
1450 .qos.qos_mode = NOC_QOS_MODE_INVALID
1453 static struct qcom_icc_node slv_oxili_cfg = {
1454 .name = "slv_oxili_cfg",
1455 .id = MSM8996_SLAVE_GRAPHICS_3D_CFG,
1459 .qos.ap_owned = true,
1460 .qos.qos_mode = NOC_QOS_MODE_INVALID
1463 static struct qcom_icc_node slv_smmu_mdp_cfg = {
1464 .name = "slv_smmu_mdp_cfg",
1465 .id = MSM8996_SLAVE_SMMU_MDP_CFG,
1469 .qos.ap_owned = true,
1470 .qos.qos_mode = NOC_QOS_MODE_INVALID
1473 static struct qcom_icc_node slv_smmu_rot_cfg = {
1474 .name = "slv_smmu_rot_cfg",
1475 .id = MSM8996_SLAVE_SMMU_ROTATOR_CFG,
1479 .qos.ap_owned = true,
1480 .qos.qos_mode = NOC_QOS_MODE_INVALID
1483 static struct qcom_icc_node slv_smmu_venus_cfg = {
1484 .name = "slv_smmu_venus_cfg",
1485 .id = MSM8996_SLAVE_SMMU_VENUS_CFG,
1489 .qos.ap_owned = true,
1490 .qos.qos_mode = NOC_QOS_MODE_INVALID
1493 static struct qcom_icc_node slv_smmu_cpp_cfg = {
1494 .name = "slv_smmu_cpp_cfg",
1495 .id = MSM8996_SLAVE_SMMU_CPP_CFG,
1499 .qos.ap_owned = true,
1500 .qos.qos_mode = NOC_QOS_MODE_INVALID
1503 static struct qcom_icc_node slv_smmu_jpeg_cfg = {
1504 .name = "slv_smmu_jpeg_cfg",
1505 .id = MSM8996_SLAVE_SMMU_JPEG_CFG,
1509 .qos.ap_owned = true,
1510 .qos.qos_mode = NOC_QOS_MODE_INVALID
1513 static struct qcom_icc_node slv_smmu_vfe_cfg = {
1514 .name = "slv_smmu_vfe_cfg",
1515 .id = MSM8996_SLAVE_SMMU_VFE_CFG,
1519 .qos.ap_owned = true,
1520 .qos.qos_mode = NOC_QOS_MODE_INVALID
1523 static const u16 slv_mnoc_bimc_links[] = {
1524 MSM8996_MASTER_MNOC_BIMC
1527 static struct qcom_icc_node slv_mnoc_bimc = {
1528 .name = "slv_mnoc_bimc",
1529 .id = MSM8996_SLAVE_MNOC_BIMC,
1533 .qos.ap_owned = true,
1534 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1535 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1536 .links = slv_mnoc_bimc_links
1539 static struct qcom_icc_node slv_vmem = {
1541 .id = MSM8996_SLAVE_VMEM,
1545 .qos.ap_owned = true,
1546 .qos.qos_mode = NOC_QOS_MODE_INVALID
1549 static struct qcom_icc_node slv_srvc_mnoc = {
1550 .name = "slv_srvc_mnoc",
1551 .id = MSM8996_SLAVE_SERVICE_MNOC,
1555 .qos.ap_owned = true,
1556 .qos.qos_mode = NOC_QOS_MODE_INVALID
1559 static const u16 slv_pnoc_a1noc_links[] = {
1560 MSM8996_MASTER_PNOC_A1NOC
1563 static struct qcom_icc_node slv_pnoc_a1noc = {
1564 .name = "slv_pnoc_a1noc",
1565 .id = MSM8996_SLAVE_PNOC_A1NOC,
1569 .num_links = ARRAY_SIZE(slv_pnoc_a1noc_links),
1570 .links = slv_pnoc_a1noc_links
1573 static struct qcom_icc_node slv_usb_hs = {
1574 .name = "slv_usb_hs",
1575 .id = MSM8996_SLAVE_USB_HS,
1581 static struct qcom_icc_node slv_sdcc_2 = {
1582 .name = "slv_sdcc_2",
1583 .id = MSM8996_SLAVE_SDCC_2,
1589 static struct qcom_icc_node slv_sdcc_4 = {
1590 .name = "slv_sdcc_4",
1591 .id = MSM8996_SLAVE_SDCC_4,
1597 static struct qcom_icc_node slv_tsif = {
1599 .id = MSM8996_SLAVE_TSIF,
1605 static struct qcom_icc_node slv_blsp_2 = {
1606 .name = "slv_blsp_2",
1607 .id = MSM8996_SLAVE_BLSP_2,
1613 static struct qcom_icc_node slv_sdcc_1 = {
1614 .name = "slv_sdcc_1",
1615 .id = MSM8996_SLAVE_SDCC_1,
1621 static struct qcom_icc_node slv_blsp_1 = {
1622 .name = "slv_blsp_1",
1623 .id = MSM8996_SLAVE_BLSP_1,
1629 static struct qcom_icc_node slv_pdm = {
1631 .id = MSM8996_SLAVE_PDM,
1637 static struct qcom_icc_node slv_ahb2phy = {
1638 .name = "slv_ahb2phy",
1639 .id = MSM8996_SLAVE_AHB2PHY,
1643 .qos.ap_owned = true,
1644 .qos.qos_mode = NOC_QOS_MODE_INVALID
1647 static struct qcom_icc_node slv_hmss = {
1649 .id = MSM8996_SLAVE_APPSS,
1653 .qos.ap_owned = true,
1654 .qos.qos_mode = NOC_QOS_MODE_INVALID
1657 static struct qcom_icc_node slv_lpass = {
1658 .name = "slv_lpass",
1659 .id = MSM8996_SLAVE_LPASS,
1663 .qos.ap_owned = true,
1664 .qos.qos_mode = NOC_QOS_MODE_INVALID
1667 static struct qcom_icc_node slv_usb3 = {
1669 .id = MSM8996_SLAVE_USB3,
1673 .qos.ap_owned = true,
1674 .qos.qos_mode = NOC_QOS_MODE_INVALID
1677 static const u16 slv_snoc_bimc_links[] = {
1678 MSM8996_MASTER_SNOC_BIMC
1681 static struct qcom_icc_node slv_snoc_bimc = {
1682 .name = "slv_snoc_bimc",
1683 .id = MSM8996_SLAVE_SNOC_BIMC,
1687 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1688 .links = slv_snoc_bimc_links
1691 static const u16 slv_snoc_cnoc_links[] = {
1692 MSM8996_MASTER_SNOC_CNOC
1695 static struct qcom_icc_node slv_snoc_cnoc = {
1696 .name = "slv_snoc_cnoc",
1697 .id = MSM8996_SLAVE_SNOC_CNOC,
1701 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1702 .links = slv_snoc_cnoc_links
1705 static struct qcom_icc_node slv_imem = {
1707 .id = MSM8996_SLAVE_OCIMEM,
1713 static struct qcom_icc_node slv_pimem = {
1714 .name = "slv_pimem",
1715 .id = MSM8996_SLAVE_PIMEM,
1721 static const u16 slv_snoc_vmem_links[] = {
1722 MSM8996_MASTER_SNOC_VMEM
1725 static struct qcom_icc_node slv_snoc_vmem = {
1726 .name = "slv_snoc_vmem",
1727 .id = MSM8996_SLAVE_SNOC_VMEM,
1731 .qos.ap_owned = true,
1732 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1733 .num_links = ARRAY_SIZE(slv_snoc_vmem_links),
1734 .links = slv_snoc_vmem_links
1737 static const u16 slv_snoc_pnoc_links[] = {
1738 MSM8996_MASTER_SNOC_PNOC
1741 static struct qcom_icc_node slv_snoc_pnoc = {
1742 .name = "slv_snoc_pnoc",
1743 .id = MSM8996_SLAVE_SNOC_PNOC,
1747 .num_links = ARRAY_SIZE(slv_snoc_pnoc_links),
1748 .links = slv_snoc_pnoc_links
1751 static struct qcom_icc_node slv_qdss_stm = {
1752 .name = "slv_qdss_stm",
1753 .id = MSM8996_SLAVE_QDSS_STM,
1759 static struct qcom_icc_node slv_pcie_0 = {
1760 .name = "slv_pcie_0",
1761 .id = MSM8996_SLAVE_PCIE_0,
1765 .qos.ap_owned = true,
1766 .qos.qos_mode = NOC_QOS_MODE_INVALID
1769 static struct qcom_icc_node slv_pcie_1 = {
1770 .name = "slv_pcie_1",
1771 .id = MSM8996_SLAVE_PCIE_1,
1775 .qos.ap_owned = true,
1776 .qos.qos_mode = NOC_QOS_MODE_INVALID
1779 static struct qcom_icc_node slv_pcie_2 = {
1780 .name = "slv_pcie_2",
1781 .id = MSM8996_SLAVE_PCIE_2,
1785 .qos.ap_owned = true,
1786 .qos.qos_mode = NOC_QOS_MODE_INVALID
1789 static struct qcom_icc_node slv_srvc_snoc = {
1790 .name = "slv_srvc_snoc",
1791 .id = MSM8996_SLAVE_SERVICE_SNOC,
1795 .qos.ap_owned = true,
1796 .qos.qos_mode = NOC_QOS_MODE_INVALID
1799 static struct qcom_icc_node *a0noc_nodes[] = {
1800 [MASTER_PCIE_0] = &mas_pcie_0,
1801 [MASTER_PCIE_1] = &mas_pcie_1,
1802 [MASTER_PCIE_2] = &mas_pcie_2
1805 static const struct regmap_config msm8996_a0noc_regmap_config = {
1809 .max_register = 0x9000,
1813 static const struct qcom_icc_desc msm8996_a0noc = {
1814 .type = QCOM_ICC_NOC,
1815 .nodes = a0noc_nodes,
1816 .num_nodes = ARRAY_SIZE(a0noc_nodes),
1817 .clocks = bus_a0noc_clocks,
1818 .num_clocks = ARRAY_SIZE(bus_a0noc_clocks),
1820 .regmap_cfg = &msm8996_a0noc_regmap_config
1823 static struct qcom_icc_node *a1noc_nodes[] = {
1824 [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc,
1825 [MASTER_CRYPTO_CORE0] = &mas_crypto_c0,
1826 [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc
1829 static const struct regmap_config msm8996_a1noc_regmap_config = {
1833 .max_register = 0x7000,
1837 static const struct qcom_icc_desc msm8996_a1noc = {
1838 .type = QCOM_ICC_NOC,
1839 .nodes = a1noc_nodes,
1840 .num_nodes = ARRAY_SIZE(a1noc_nodes),
1841 .regmap_cfg = &msm8996_a1noc_regmap_config
1844 static struct qcom_icc_node *a2noc_nodes[] = {
1845 [MASTER_USB3] = &mas_usb3,
1846 [MASTER_IPA] = &mas_ipa,
1847 [MASTER_UFS] = &mas_ufs
1850 static const struct regmap_config msm8996_a2noc_regmap_config = {
1854 .max_register = 0xa000,
1858 static const struct qcom_icc_desc msm8996_a2noc = {
1859 .type = QCOM_ICC_NOC,
1860 .nodes = a2noc_nodes,
1861 .num_nodes = ARRAY_SIZE(a2noc_nodes),
1862 .regmap_cfg = &msm8996_a2noc_regmap_config
1865 static struct qcom_icc_node *bimc_nodes[] = {
1866 [MASTER_AMPSS_M0] = &mas_apps_proc,
1867 [MASTER_GRAPHICS_3D] = &mas_oxili,
1868 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1869 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1870 [SLAVE_EBI_CH0] = &slv_ebi,
1871 [SLAVE_HMSS_L3] = &slv_hmss_l3,
1872 [SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0,
1873 [SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1
1876 static const struct regmap_config msm8996_bimc_regmap_config = {
1880 .max_register = 0x62000,
1884 static const struct qcom_icc_desc msm8996_bimc = {
1885 .type = QCOM_ICC_BIMC,
1886 .nodes = bimc_nodes,
1887 .num_nodes = ARRAY_SIZE(bimc_nodes),
1888 .regmap_cfg = &msm8996_bimc_regmap_config
1891 static struct qcom_icc_node *cnoc_nodes[] = {
1892 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1893 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1894 [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc,
1895 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1896 [SLAVE_TCSR] = &slv_tcsr,
1897 [SLAVE_TLMM] = &slv_tlmm,
1898 [SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg,
1899 [SLAVE_MPM] = &slv_mpm,
1900 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1901 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1902 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1903 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1904 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1905 [SLAVE_PRNG] = &slv_prng,
1906 [SLAVE_DCC_CFG] = &slv_dcc_cfg,
1907 [SLAVE_RBCPR_MX] = &slv_rbcpr_mx,
1908 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1909 [SLAVE_RBCPR_CX] = &slv_rbcpr_cx,
1910 [SLAVE_QDSS_RBCPR_APU] = &slv_cpu_apu_cfg,
1911 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1912 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1913 [SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg,
1914 [SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg,
1915 [SLAVE_A0NOC_CFG] = &slv_a0noc_cfg,
1916 [SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg,
1917 [SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg,
1918 [SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg,
1919 [SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy,
1920 [SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg,
1921 [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1922 [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg,
1923 [SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg,
1924 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1925 [SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg,
1926 [SLAVE_SSC_CFG] = &slv_ssc_cfg,
1927 [SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg,
1928 [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg,
1929 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1930 [SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg,
1931 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg
1934 static const struct regmap_config msm8996_cnoc_regmap_config = {
1938 .max_register = 0x1000,
1942 static const struct qcom_icc_desc msm8996_cnoc = {
1943 .type = QCOM_ICC_NOC,
1944 .nodes = cnoc_nodes,
1945 .num_nodes = ARRAY_SIZE(cnoc_nodes),
1946 .regmap_cfg = &msm8996_cnoc_regmap_config
1949 static struct qcom_icc_node *mnoc_nodes[] = {
1950 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1951 [MASTER_CPP] = &mas_cpp,
1952 [MASTER_JPEG] = &mas_jpeg,
1953 [MASTER_MDP_PORT0] = &mas_mdp_p0,
1954 [MASTER_MDP_PORT1] = &mas_mdp_p1,
1955 [MASTER_ROTATOR] = &mas_rotator,
1956 [MASTER_VIDEO_P0] = &mas_venus,
1957 [MASTER_VFE] = &mas_vfe,
1958 [MASTER_SNOC_VMEM] = &mas_snoc_vmem,
1959 [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem,
1960 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1961 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1962 [SLAVE_VMEM] = &slv_vmem,
1963 [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc,
1964 [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg,
1965 [SLAVE_CPR_CFG] = &slv_cpr_cfg,
1966 [SLAVE_MISC_CFG] = &slv_misc_cfg,
1967 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1968 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1969 [SLAVE_VMEM_CFG] = &slv_vmem_cfg,
1970 [SLAVE_DSA_CFG] = &slv_dsa_cfg,
1971 [SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg,
1972 [SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg,
1973 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1974 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1975 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1976 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1977 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1978 [SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg,
1979 [SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg,
1980 [SLAVE_SMMU_ROT_CFG] = &slv_smmu_rot_cfg,
1981 [SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg,
1982 [SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg,
1983 [SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg,
1984 [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg
1987 static const struct regmap_config msm8996_mnoc_regmap_config = {
1991 .max_register = 0x20000,
1995 static const struct qcom_icc_desc msm8996_mnoc = {
1996 .type = QCOM_ICC_NOC,
1997 .nodes = mnoc_nodes,
1998 .num_nodes = ARRAY_SIZE(mnoc_nodes),
1999 .clocks = bus_mm_clocks,
2000 .num_clocks = ARRAY_SIZE(bus_mm_clocks),
2001 .regmap_cfg = &msm8996_mnoc_regmap_config
2004 static struct qcom_icc_node *pnoc_nodes[] = {
2005 [MASTER_SNOC_PNOC] = &mas_snoc_pnoc,
2006 [MASTER_SDCC_1] = &mas_sdcc_1,
2007 [MASTER_SDCC_2] = &mas_sdcc_2,
2008 [MASTER_SDCC_4] = &mas_sdcc_4,
2009 [MASTER_USB_HS] = &mas_usb_hs,
2010 [MASTER_BLSP_1] = &mas_blsp_1,
2011 [MASTER_BLSP_2] = &mas_blsp_2,
2012 [MASTER_TSIF] = &mas_tsif,
2013 [SLAVE_PNOC_A1NOC] = &slv_pnoc_a1noc,
2014 [SLAVE_USB_HS] = &slv_usb_hs,
2015 [SLAVE_SDCC_2] = &slv_sdcc_2,
2016 [SLAVE_SDCC_4] = &slv_sdcc_4,
2017 [SLAVE_TSIF] = &slv_tsif,
2018 [SLAVE_BLSP_2] = &slv_blsp_2,
2019 [SLAVE_SDCC_1] = &slv_sdcc_1,
2020 [SLAVE_BLSP_1] = &slv_blsp_1,
2021 [SLAVE_PDM] = &slv_pdm,
2022 [SLAVE_AHB2PHY] = &slv_ahb2phy
2025 static const struct regmap_config msm8996_pnoc_regmap_config = {
2029 .max_register = 0x3000,
2033 static const struct qcom_icc_desc msm8996_pnoc = {
2034 .type = QCOM_ICC_NOC,
2035 .nodes = pnoc_nodes,
2036 .num_nodes = ARRAY_SIZE(pnoc_nodes),
2037 .regmap_cfg = &msm8996_pnoc_regmap_config
2040 static struct qcom_icc_node *snoc_nodes[] = {
2041 [MASTER_HMSS] = &mas_hmss,
2042 [MASTER_QDSS_BAM] = &mas_qdss_bam,
2043 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
2044 [MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0,
2045 [MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1,
2046 [MASTER_A0NOC_SNOC] = &mas_a0noc_snoc,
2047 [MASTER_A1NOC_SNOC] = &mas_a1noc_snoc,
2048 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
2049 [MASTER_QDSS_ETR] = &mas_qdss_etr,
2050 [SLAVE_A0NOC_SNOC] = &slv_a0noc_snoc,
2051 [SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc,
2052 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
2053 [SLAVE_HMSS] = &slv_hmss,
2054 [SLAVE_LPASS] = &slv_lpass,
2055 [SLAVE_USB3] = &slv_usb3,
2056 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
2057 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
2058 [SLAVE_IMEM] = &slv_imem,
2059 [SLAVE_PIMEM] = &slv_pimem,
2060 [SLAVE_SNOC_VMEM] = &slv_snoc_vmem,
2061 [SLAVE_SNOC_PNOC] = &slv_snoc_pnoc,
2062 [SLAVE_QDSS_STM] = &slv_qdss_stm,
2063 [SLAVE_PCIE_0] = &slv_pcie_0,
2064 [SLAVE_PCIE_1] = &slv_pcie_1,
2065 [SLAVE_PCIE_2] = &slv_pcie_2,
2066 [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc
2069 static const struct regmap_config msm8996_snoc_regmap_config = {
2073 .max_register = 0x20000,
2077 static const struct qcom_icc_desc msm8996_snoc = {
2078 .type = QCOM_ICC_NOC,
2079 .nodes = snoc_nodes,
2080 .num_nodes = ARRAY_SIZE(snoc_nodes),
2081 .regmap_cfg = &msm8996_snoc_regmap_config
2084 static const struct of_device_id qnoc_of_match[] = {
2085 { .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc},
2086 { .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc},
2087 { .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc},
2088 { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc},
2089 { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc},
2090 { .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc},
2091 { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc},
2092 { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc},
2095 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2097 static struct platform_driver qnoc_driver = {
2098 .probe = qnoc_probe,
2099 .remove = qnoc_remove,
2101 .name = "qnoc-msm8996",
2102 .of_match_table = qnoc_of_match,
2103 .sync_state = icc_sync_state,
2106 module_platform_driver(qnoc_driver);
2108 MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
2109 MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver");
2110 MODULE_LICENSE("GPL v2");