drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <rdma/iw_cm.h>
  37 #include <rdma/ib_mad.h>
  38 #include <linux/netdevice.h>
  39 #include <linux/iommu.h>
  40 #include <linux/pci.h>
  41 #include <net/addrconf.h>
  42
  43 #include <linux/qed/qed_chain.h>
  44 #include <linux/qed/qed_if.h>
  45 #include "qedr.h"
  46 #include "verbs.h"
  47 #include <rdma/qedr-abi.h>
  48 #include "qedr_iw_cm.h"
  49
  50 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  51 MODULE_AUTHOR("QLogic Corporation");
  52 MODULE_LICENSE("Dual BSD/GPL");
  53
  54 #define QEDR_WQ_MULTIPLIER_DFT  (3)
  55
  56 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  57                                    enum ib_event_type type)
  58 {
  59         struct ib_event ibev;
  60
  61         ibev.device = &dev->ibdev;
  62         ibev.element.port_num = port_num;
  63         ibev.event = type;
  64
  65         ib_dispatch_event(&ibev);
  66 }
  67
  68 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  69                                             u8 port_num)
  70 {
  71         return IB_LINK_LAYER_ETHERNET;
  72 }
  73
  74 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
  75 {
  76         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  77         u32 fw_ver = (u32)qedr->attr.fw_ver;
  78
  79         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
  80                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  81                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  82 }
  83
  84 static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
  85                                     struct ib_port_immutable *immutable)
  86 {
  87         struct ib_port_attr attr;
  88         int err;
  89
  90         err = qedr_query_port(ibdev, port_num, &attr);
  91         if (err)
  92                 return err;
  93
  94         immutable->pkey_tbl_len = attr.pkey_tbl_len;
  95         immutable->gid_tbl_len = attr.gid_tbl_len;
  96         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
  97             RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  98         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  99
 100         return 0;
 101 }
 102
 103 static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
 104                                   struct ib_port_immutable *immutable)
 105 {
 106         struct ib_port_attr attr;
 107         int err;
 108
 109         err = qedr_query_port(ibdev, port_num, &attr);
 110         if (err)
 111                 return err;
 112
 113         immutable->gid_tbl_len = 1;
 114         immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
 115         immutable->max_mad_size = 0;
 116
 117         return 0;
 118 }
 119
 120 /* QEDR sysfs interface */
 121 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
 122                            char *buf)
 123 {
 124         struct qedr_dev *dev =
 125                 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
 126
 127         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->attr.hw_ver);
 128 }
 129 static DEVICE_ATTR_RO(hw_rev);
 130
 131 static ssize_t hca_type_show(struct device *device,
 132                              struct device_attribute *attr, char *buf)
 133 {
 134         struct qedr_dev *dev =
 135                 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
 136
 137         return scnprintf(buf, PAGE_SIZE, "FastLinQ QL%x %s\n",
 138                          dev->pdev->device,
 139                          rdma_protocol_iwarp(&dev->ibdev, 1) ?
 140                          "iWARP" : "RoCE");
 141 }
 142 static DEVICE_ATTR_RO(hca_type);
 143
 144 static struct attribute *qedr_attributes[] = {
 145         &dev_attr_hw_rev.attr,
 146         &dev_attr_hca_type.attr,
 147         NULL
 148 };
 149
 150 static const struct attribute_group qedr_attr_group = {
 151         .attrs = qedr_attributes,
 152 };
 153
 154 static const struct ib_device_ops qedr_iw_dev_ops = {
 155         .get_port_immutable = qedr_iw_port_immutable,
 156         .iw_accept = qedr_iw_accept,
 157         .iw_add_ref = qedr_iw_qp_add_ref,
 158         .iw_connect = qedr_iw_connect,
 159         .iw_create_listen = qedr_iw_create_listen,
 160         .iw_destroy_listen = qedr_iw_destroy_listen,
 161         .iw_get_qp = qedr_iw_get_qp,
 162         .iw_reject = qedr_iw_reject,
 163         .iw_rem_ref = qedr_iw_qp_rem_ref,
 164         .query_gid = qedr_iw_query_gid,
 165 };
 166
 167 static int qedr_iw_register_device(struct qedr_dev *dev)
 168 {
 169         dev->ibdev.node_type = RDMA_NODE_RNIC;
 170
 171         ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops);
 172
 173         memcpy(dev->ibdev.iw_ifname,
 174                dev->ndev->name, sizeof(dev->ibdev.iw_ifname));
 175
 176         return 0;
 177 }
 178
 179 static const struct ib_device_ops qedr_roce_dev_ops = {
 180         .get_port_immutable = qedr_roce_port_immutable,
 181         .query_pkey = qedr_query_pkey,
 182 };
 183
 184 static void qedr_roce_register_device(struct qedr_dev *dev)
 185 {
 186         dev->ibdev.node_type = RDMA_NODE_IB_CA;
 187
 188         ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops);
 189 }
 190
 191 static const struct ib_device_ops qedr_dev_ops = {
 192         .owner = THIS_MODULE,
 193         .driver_id = RDMA_DRIVER_QEDR,
 194         .uverbs_abi_ver = QEDR_ABI_VERSION,
 195
 196         .alloc_mr = qedr_alloc_mr,
 197         .alloc_pd = qedr_alloc_pd,
 198         .alloc_ucontext = qedr_alloc_ucontext,
 199         .create_ah = qedr_create_ah,
 200         .create_cq = qedr_create_cq,
 201         .create_qp = qedr_create_qp,
 202         .create_srq = qedr_create_srq,
 203         .dealloc_pd = qedr_dealloc_pd,
 204         .dealloc_ucontext = qedr_dealloc_ucontext,
 205         .dereg_mr = qedr_dereg_mr,
 206         .destroy_ah = qedr_destroy_ah,
 207         .destroy_cq = qedr_destroy_cq,
 208         .destroy_qp = qedr_destroy_qp,
 209         .destroy_srq = qedr_destroy_srq,
 210         .get_dev_fw_str = qedr_get_dev_fw_str,
 211         .get_dma_mr = qedr_get_dma_mr,
 212         .get_link_layer = qedr_link_layer,
 213         .map_mr_sg = qedr_map_mr_sg,
 214         .mmap = qedr_mmap,
 215         .mmap_free = qedr_mmap_free,
 216         .modify_qp = qedr_modify_qp,
 217         .modify_srq = qedr_modify_srq,
 218         .poll_cq = qedr_poll_cq,
 219         .post_recv = qedr_post_recv,
 220         .post_send = qedr_post_send,
 221         .post_srq_recv = qedr_post_srq_recv,
 222         .process_mad = qedr_process_mad,
 223         .query_device = qedr_query_device,
 224         .query_port = qedr_query_port,
 225         .query_qp = qedr_query_qp,
 226         .query_srq = qedr_query_srq,
 227         .reg_user_mr = qedr_reg_user_mr,
 228         .req_notify_cq = qedr_arm_cq,
 229         .resize_cq = qedr_resize_cq,
 230
 231         INIT_RDMA_OBJ_SIZE(ib_ah, qedr_ah, ibah),
 232         INIT_RDMA_OBJ_SIZE(ib_cq, qedr_cq, ibcq),
 233         INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd),
 234         INIT_RDMA_OBJ_SIZE(ib_srq, qedr_srq, ibsrq),
 235         INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext),
 236 };
 237
 238 static int qedr_register_device(struct qedr_dev *dev)
 239 {
 240         int rc;
 241
 242         dev->ibdev.node_guid = dev->attr.node_guid;
 243         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
 244
 245         dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
 246                                      QEDR_UVERBS(QUERY_DEVICE) |
 247                                      QEDR_UVERBS(QUERY_PORT) |
 248                                      QEDR_UVERBS(ALLOC_PD) |
 249                                      QEDR_UVERBS(DEALLOC_PD) |
 250                                      QEDR_UVERBS(CREATE_COMP_CHANNEL) |
 251                                      QEDR_UVERBS(CREATE_CQ) |
 252                                      QEDR_UVERBS(RESIZE_CQ) |
 253                                      QEDR_UVERBS(DESTROY_CQ) |
 254                                      QEDR_UVERBS(REQ_NOTIFY_CQ) |
 255                                      QEDR_UVERBS(CREATE_QP) |
 256                                      QEDR_UVERBS(MODIFY_QP) |
 257                                      QEDR_UVERBS(QUERY_QP) |
 258                                      QEDR_UVERBS(DESTROY_QP) |
 259                                      QEDR_UVERBS(CREATE_SRQ) |
 260                                      QEDR_UVERBS(DESTROY_SRQ) |
 261                                      QEDR_UVERBS(QUERY_SRQ) |
 262                                      QEDR_UVERBS(MODIFY_SRQ) |
 263                                      QEDR_UVERBS(POST_SRQ_RECV) |
 264                                      QEDR_UVERBS(REG_MR) |
 265                                      QEDR_UVERBS(DEREG_MR) |
 266                                      QEDR_UVERBS(POLL_CQ) |
 267                                      QEDR_UVERBS(POST_SEND) |
 268                                      QEDR_UVERBS(POST_RECV);
 269
 270         if (IS_IWARP(dev)) {
 271                 rc = qedr_iw_register_device(dev);
 272                 if (rc)
 273                         return rc;
 274         } else {
 275                 qedr_roce_register_device(dev);
 276         }
 277
 278         dev->ibdev.phys_port_cnt = 1;
 279         dev->ibdev.num_comp_vectors = dev->num_cnq;
 280         dev->ibdev.dev.parent = &dev->pdev->dev;
 281
 282         rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group);
 283         ib_set_device_ops(&dev->ibdev, &qedr_dev_ops);
 284
 285         rc = ib_device_set_netdev(&dev->ibdev, dev->ndev, 1);
 286         if (rc)
 287                 return rc;
 288
 289         return ib_register_device(&dev->ibdev, "qedr%d");
 290 }
 291
 292 /* This function allocates fast-path status block memory */
 293 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
 294                              struct qed_sb_info *sb_info, u16 sb_id)
 295 {
 296         struct status_block_e4 *sb_virt;
 297         dma_addr_t sb_phys;
 298         int rc;
 299
 300         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
 301                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 302         if (!sb_virt)
 303                 return -ENOMEM;
 304
 305         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 306                                        sb_virt, sb_phys, sb_id,
 307                                        QED_SB_TYPE_CNQ);
 308         if (rc) {
 309                 pr_err("Status block initialization failed\n");
 310                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 311                                   sb_virt, sb_phys);
 312                 return rc;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static void qedr_free_mem_sb(struct qedr_dev *dev,
 319                              struct qed_sb_info *sb_info, int sb_id)
 320 {
 321         if (sb_info->sb_virt) {
 322                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id,
 323                                              QED_SB_TYPE_CNQ);
 324                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 325                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 326         }
 327 }
 328
 329 static void qedr_free_resources(struct qedr_dev *dev)
 330 {
 331         int i;
 332
 333         if (IS_IWARP(dev))
 334                 destroy_workqueue(dev->iwarp_wq);
 335
 336         for (i = 0; i < dev->num_cnq; i++) {
 337                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 338                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 339         }
 340
 341         kfree(dev->cnq_array);
 342         kfree(dev->sb_array);
 343         kfree(dev->sgid_tbl);
 344 }
 345
 346 static int qedr_alloc_resources(struct qedr_dev *dev)
 347 {
 348         struct qedr_cnq *cnq;
 349         __le16 *cons_pi;
 350         u16 n_entries;
 351         int i, rc;
 352
 353         dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid),
 354                                 GFP_KERNEL);
 355         if (!dev->sgid_tbl)
 356                 return -ENOMEM;
 357
 358         spin_lock_init(&dev->sgid_lock);
 359         xa_init_flags(&dev->srqs, XA_FLAGS_LOCK_IRQ);
 360
 361         if (IS_IWARP(dev)) {
 362                 xa_init(&dev->qps);
 363                 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
 364         }
 365
 366         /* Allocate Status blocks for CNQ */
 367         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 368                                 GFP_KERNEL);
 369         if (!dev->sb_array) {
 370                 rc = -ENOMEM;
 371                 goto err1;
 372         }
 373
 374         dev->cnq_array = kcalloc(dev->num_cnq,
 375                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 376         if (!dev->cnq_array) {
 377                 rc = -ENOMEM;
 378                 goto err2;
 379         }
 380
 381         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 382
 383         /* Allocate CNQ PBLs */
 384         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 385         for (i = 0; i < dev->num_cnq; i++) {
 386                 cnq = &dev->cnq_array[i];
 387
 388                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 389                                        dev->sb_start + i);
 390                 if (rc)
 391                         goto err3;
 392
 393                 rc = dev->ops->common->chain_alloc(dev->cdev,
 394                                                    QED_CHAIN_USE_TO_CONSUME,
 395                                                    QED_CHAIN_MODE_PBL,
 396                                                    QED_CHAIN_CNT_TYPE_U16,
 397                                                    n_entries,
 398                                                    sizeof(struct regpair *),
 399                                                    &cnq->pbl, NULL);
 400                 if (rc)
 401                         goto err4;
 402
 403                 cnq->dev = dev;
 404                 cnq->sb = &dev->sb_array[i];
 405                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 406                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 407                 cnq->index = i;
 408                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 409
 410                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 411                          i, qed_chain_get_cons_idx(&cnq->pbl));
 412         }
 413
 414         return 0;
 415 err4:
 416         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 417 err3:
 418         for (--i; i >= 0; i--) {
 419                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 420                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 421         }
 422         kfree(dev->cnq_array);
 423 err2:
 424         kfree(dev->sb_array);
 425 err1:
 426         kfree(dev->sgid_tbl);
 427         return rc;
 428 }
 429
 430 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 431 {
 432         int rc = pci_enable_atomic_ops_to_root(pdev,
 433                                                PCI_EXP_DEVCAP2_ATOMIC_COMP64);
 434
 435         if (rc) {
 436                 dev->atomic_cap = IB_ATOMIC_NONE;
 437                 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
 438         } else {
 439                 dev->atomic_cap = IB_ATOMIC_GLOB;
 440                 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
 441         }
 442 }
 443
 444 static const struct qed_rdma_ops *qed_ops;
 445
 446 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 447
 448 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 449 {
 450         u16 hw_comp_cons, sw_comp_cons;
 451         struct qedr_cnq *cnq = handle;
 452         struct regpair *cq_handle;
 453         struct qedr_cq *cq;
 454
 455         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 456
 457         qed_sb_update_sb_idx(cnq->sb);
 458
 459         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 460         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 461
 462         /* Align protocol-index and chain reads */
 463         rmb();
 464
 465         while (sw_comp_cons != hw_comp_cons) {
 466                 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
 467                 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
 468                                 cq_handle->lo);
 469
 470                 if (cq == NULL) {
 471                         DP_ERR(cnq->dev,
 472                                "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
 473                                cq_handle->hi, cq_handle->lo, sw_comp_cons,
 474                                hw_comp_cons);
 475
 476                         break;
 477                 }
 478
 479                 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
 480                         DP_ERR(cnq->dev,
 481                                "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
 482                                cq_handle->hi, cq_handle->lo, cq);
 483                         break;
 484                 }
 485
 486                 cq->arm_flags = 0;
 487
 488                 if (!cq->destroyed && cq->ibcq.comp_handler)
 489                         (*cq->ibcq.comp_handler)
 490                                 (&cq->ibcq, cq->ibcq.cq_context);
 491
 492                 /* The CQ's CNQ notification counter is checked before
 493                  * destroying the CQ in a busy-wait loop that waits for all of
 494                  * the CQ's CNQ interrupts to be processed. It is increased
 495                  * here, only after the completion handler, to ensure that the
 496                  * the handler is not running when the CQ is destroyed.
 497                  */
 498                 cq->cnq_notif++;
 499
 500                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 501
 502                 cnq->n_comp++;
 503         }
 504
 505         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 506                                       sw_comp_cons);
 507
 508         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 509
 510         return IRQ_HANDLED;
 511 }
 512
 513 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 514 {
 515         u32 vector;
 516         u16 idx;
 517         int i;
 518
 519         for (i = 0; i < dev->int_info.used_cnt; i++) {
 520                 if (dev->int_info.msix_cnt) {
 521                         idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
 522                         vector = dev->int_info.msix[idx].vector;
 523                         synchronize_irq(vector);
 524                         free_irq(vector, &dev->cnq_array[i]);
 525                 }
 526         }
 527
 528         dev->int_info.used_cnt = 0;
 529 }
 530
 531 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 532 {
 533         int i, rc = 0;
 534         u16 idx;
 535
 536         if (dev->num_cnq > dev->int_info.msix_cnt) {
 537                 DP_ERR(dev,
 538                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 539                        dev->num_cnq, dev->int_info.msix_cnt);
 540                 return -EINVAL;
 541         }
 542
 543         for (i = 0; i < dev->num_cnq; i++) {
 544                 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
 545                 rc = request_irq(dev->int_info.msix[idx].vector,
 546                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 547                                  &dev->cnq_array[i]);
 548                 if (rc) {
 549                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 550                         qedr_sync_free_irqs(dev);
 551                 } else {
 552                         DP_DEBUG(dev, QEDR_MSG_INIT,
 553                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 554                                  dev->cnq_array[i].name, i,
 555                                  &dev->cnq_array[i]);
 556                         dev->int_info.used_cnt++;
 557                 }
 558         }
 559
 560         return rc;
 561 }
 562
 563 static int qedr_setup_irqs(struct qedr_dev *dev)
 564 {
 565         int rc;
 566
 567         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 568
 569         /* Learn Interrupt configuration */
 570         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 571         if (rc < 0)
 572                 return rc;
 573
 574         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 575         if (rc) {
 576                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 577                 return rc;
 578         }
 579
 580         if (dev->int_info.msix_cnt) {
 581                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 582                          dev->int_info.msix_cnt);
 583                 rc = qedr_req_msix_irqs(dev);
 584                 if (rc)
 585                         return rc;
 586         }
 587
 588         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 589
 590         return 0;
 591 }
 592
 593 static int qedr_set_device_attr(struct qedr_dev *dev)
 594 {
 595         struct qed_rdma_device *qed_attr;
 596         struct qedr_device_attr *attr;
 597         u32 page_size;
 598
 599         /* Part 1 - query core capabilities */
 600         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 601
 602         /* Part 2 - check capabilities */
 603         page_size = ~dev->attr.page_size_caps + 1;
 604         if (page_size > PAGE_SIZE) {
 605                 DP_ERR(dev,
 606                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 607                        PAGE_SIZE, page_size);
 608                 return -ENODEV;
 609         }
 610
 611         /* Part 3 - copy and update capabilities */
 612         attr = &dev->attr;
 613         attr->vendor_id = qed_attr->vendor_id;
 614         attr->vendor_part_id = qed_attr->vendor_part_id;
 615         attr->hw_ver = qed_attr->hw_ver;
 616         attr->fw_ver = qed_attr->fw_ver;
 617         attr->node_guid = qed_attr->node_guid;
 618         attr->sys_image_guid = qed_attr->sys_image_guid;
 619         attr->max_cnq = qed_attr->max_cnq;
 620         attr->max_sge = qed_attr->max_sge;
 621         attr->max_inline = qed_attr->max_inline;
 622         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 623         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 624         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 625         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 626         attr->max_dev_resp_rd_atomic_resc =
 627             qed_attr->max_dev_resp_rd_atomic_resc;
 628         attr->max_cq = qed_attr->max_cq;
 629         attr->max_qp = qed_attr->max_qp;
 630         attr->max_mr = qed_attr->max_mr;
 631         attr->max_mr_size = qed_attr->max_mr_size;
 632         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 633         attr->max_mw = qed_attr->max_mw;
 634         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 635         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 636         attr->max_pd = qed_attr->max_pd;
 637         attr->max_ah = qed_attr->max_ah;
 638         attr->max_pkey = qed_attr->max_pkey;
 639         attr->max_srq = qed_attr->max_srq;
 640         attr->max_srq_wr = qed_attr->max_srq_wr;
 641         attr->dev_caps = qed_attr->dev_caps;
 642         attr->page_size_caps = qed_attr->page_size_caps;
 643         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 644         attr->reserved_lkey = qed_attr->reserved_lkey;
 645         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 646         attr->max_stats_queues = qed_attr->max_stats_queues;
 647
 648         return 0;
 649 }
 650
 651 static void qedr_unaffiliated_event(void *context, u8 event_code)
 652 {
 653         pr_err("unaffiliated event not implemented yet\n");
 654 }
 655
 656 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
 657 {
 658 #define EVENT_TYPE_NOT_DEFINED  0
 659 #define EVENT_TYPE_CQ           1
 660 #define EVENT_TYPE_QP           2
 661 #define EVENT_TYPE_SRQ          3
 662         struct qedr_dev *dev = (struct qedr_dev *)context;
 663         struct regpair *async_handle = (struct regpair *)fw_handle;
 664         u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
 665         u8 event_type = EVENT_TYPE_NOT_DEFINED;
 666         struct ib_event event;
 667         struct ib_srq *ibsrq;
 668         struct qedr_srq *srq;
 669         unsigned long flags;
 670         struct ib_cq *ibcq;
 671         struct ib_qp *ibqp;
 672         struct qedr_cq *cq;
 673         struct qedr_qp *qp;
 674         u16 srq_id;
 675
 676         if (IS_ROCE(dev)) {
 677                 switch (e_code) {
 678                 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
 679                         event.event = IB_EVENT_CQ_ERR;
 680                         event_type = EVENT_TYPE_CQ;
 681                         break;
 682                 case ROCE_ASYNC_EVENT_SQ_DRAINED:
 683                         event.event = IB_EVENT_SQ_DRAINED;
 684                         event_type = EVENT_TYPE_QP;
 685                         break;
 686                 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
 687                         event.event = IB_EVENT_QP_FATAL;
 688                         event_type = EVENT_TYPE_QP;
 689                         break;
 690                 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
 691                         event.event = IB_EVENT_QP_REQ_ERR;
 692                         event_type = EVENT_TYPE_QP;
 693                         break;
 694                 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
 695                         event.event = IB_EVENT_QP_ACCESS_ERR;
 696                         event_type = EVENT_TYPE_QP;
 697                         break;
 698                 case ROCE_ASYNC_EVENT_SRQ_LIMIT:
 699                         event.event = IB_EVENT_SRQ_LIMIT_REACHED;
 700                         event_type = EVENT_TYPE_SRQ;
 701                         break;
 702                 case ROCE_ASYNC_EVENT_SRQ_EMPTY:
 703                         event.event = IB_EVENT_SRQ_ERR;
 704                         event_type = EVENT_TYPE_SRQ;
 705                         break;
 706                 default:
 707                         DP_ERR(dev, "unsupported event %d on handle=%llx\n",
 708                                e_code, roce_handle64);
 709                 }
 710         } else {
 711                 switch (e_code) {
 712                 case QED_IWARP_EVENT_SRQ_LIMIT:
 713                         event.event = IB_EVENT_SRQ_LIMIT_REACHED;
 714                         event_type = EVENT_TYPE_SRQ;
 715                         break;
 716                 case QED_IWARP_EVENT_SRQ_EMPTY:
 717                         event.event = IB_EVENT_SRQ_ERR;
 718                         event_type = EVENT_TYPE_SRQ;
 719                         break;
 720                 default:
 721                 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
 722                        roce_handle64);
 723                 }
 724         }
 725         switch (event_type) {
 726         case EVENT_TYPE_CQ:
 727                 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
 728                 if (cq) {
 729                         ibcq = &cq->ibcq;
 730                         if (ibcq->event_handler) {
 731                                 event.device = ibcq->device;
 732                                 event.element.cq = ibcq;
 733                                 ibcq->event_handler(&event, ibcq->cq_context);
 734                         }
 735                 } else {
 736                         WARN(1,
 737                              "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
 738                              roce_handle64);
 739                 }
 740                 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
 741                 break;
 742         case EVENT_TYPE_QP:
 743                 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
 744                 if (qp) {
 745                         ibqp = &qp->ibqp;
 746                         if (ibqp->event_handler) {
 747                                 event.device = ibqp->device;
 748                                 event.element.qp = ibqp;
 749                                 ibqp->event_handler(&event, ibqp->qp_context);
 750                         }
 751                 } else {
 752                         WARN(1,
 753                              "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
 754                              roce_handle64);
 755                 }
 756                 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
 757                 break;
 758         case EVENT_TYPE_SRQ:
 759                 srq_id = (u16)roce_handle64;
 760                 xa_lock_irqsave(&dev->srqs, flags);
 761                 srq = xa_load(&dev->srqs, srq_id);
 762                 if (srq) {
 763                         ibsrq = &srq->ibsrq;
 764                         if (ibsrq->event_handler) {
 765                                 event.device = ibsrq->device;
 766                                 event.element.srq = ibsrq;
 767                                 ibsrq->event_handler(&event,
 768                                                      ibsrq->srq_context);
 769                         }
 770                 } else {
 771                         DP_NOTICE(dev,
 772                                   "SRQ event with NULL pointer ibsrq. Handle=%llx\n",
 773                                   roce_handle64);
 774                 }
 775                 xa_unlock_irqrestore(&dev->srqs, flags);
 776                 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq);
 777         default:
 778                 break;
 779         }
 780 }
 781
 782 static int qedr_init_hw(struct qedr_dev *dev)
 783 {
 784         struct qed_rdma_add_user_out_params out_params;
 785         struct qed_rdma_start_in_params *in_params;
 786         struct qed_rdma_cnq_params *cur_pbl;
 787         struct qed_rdma_events events;
 788         dma_addr_t p_phys_table;
 789         u32 page_cnt;
 790         int rc = 0;
 791         int i;
 792
 793         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 794         if (!in_params) {
 795                 rc = -ENOMEM;
 796                 goto out;
 797         }
 798
 799         in_params->desired_cnq = dev->num_cnq;
 800         for (i = 0; i < dev->num_cnq; i++) {
 801                 cur_pbl = &in_params->cnq_pbl_list[i];
 802
 803                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 804                 cur_pbl->num_pbl_pages = page_cnt;
 805
 806                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 807                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 808         }
 809
 810         events.affiliated_event = qedr_affiliated_event;
 811         events.unaffiliated_event = qedr_unaffiliated_event;
 812         events.context = dev;
 813
 814         in_params->events = &events;
 815         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 816         in_params->max_mtu = dev->ndev->mtu;
 817         dev->iwarp_max_mtu = dev->ndev->mtu;
 818         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 819
 820         rc = dev->ops->rdma_init(dev->cdev, in_params);
 821         if (rc)
 822                 goto out;
 823
 824         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 825         if (rc)
 826                 goto out;
 827
 828         dev->db_addr = out_params.dpi_addr;
 829         dev->db_phys_addr = out_params.dpi_phys_addr;
 830         dev->db_size = out_params.dpi_size;
 831         dev->dpi = out_params.dpi;
 832
 833         rc = qedr_set_device_attr(dev);
 834 out:
 835         kfree(in_params);
 836         if (rc)
 837                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 838
 839         return rc;
 840 }
 841
 842 static void qedr_stop_hw(struct qedr_dev *dev)
 843 {
 844         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 845         dev->ops->rdma_stop(dev->rdma_ctx);
 846 }
 847
 848 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 849                                  struct net_device *ndev)
 850 {
 851         struct qed_dev_rdma_info dev_info;
 852         struct qedr_dev *dev;
 853         int rc = 0;
 854
 855         dev = ib_alloc_device(qedr_dev, ibdev);
 856         if (!dev) {
 857                 pr_err("Unable to allocate ib device\n");
 858                 return NULL;
 859         }
 860
 861         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 862
 863         dev->pdev = pdev;
 864         dev->ndev = ndev;
 865         dev->cdev = cdev;
 866
 867         qed_ops = qed_get_rdma_ops();
 868         if (!qed_ops) {
 869                 DP_ERR(dev, "Failed to get qed roce operations\n");
 870                 goto init_err;
 871         }
 872
 873         dev->ops = qed_ops;
 874         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 875         if (rc)
 876                 goto init_err;
 877
 878         dev->user_dpm_enabled = dev_info.user_dpm_enabled;
 879         dev->rdma_type = dev_info.rdma_type;
 880         dev->num_hwfns = dev_info.common.num_hwfns;
 881
 882         if (IS_IWARP(dev) && QEDR_IS_CMT(dev)) {
 883                 rc = dev->ops->iwarp_set_engine_affin(cdev, false);
 884                 if (rc) {
 885                         DP_ERR(dev, "iWARP is disabled over a 100g device Enabling it may impact L2 performance. To enable it run devlink dev param set <dev> name iwarp_cmt value true cmode runtime\n");
 886                         goto init_err;
 887                 }
 888         }
 889         dev->affin_hwfn_idx = dev->ops->common->get_affin_hwfn_idx(cdev);
 890
 891         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 892
 893         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 894         if (!dev->num_cnq) {
 895                 DP_ERR(dev, "Failed. At least one CNQ is required.\n");
 896                 rc = -ENOMEM;
 897                 goto init_err;
 898         }
 899
 900         dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
 901
 902         qedr_pci_set_atomic(dev, pdev);
 903
 904         rc = qedr_alloc_resources(dev);
 905         if (rc)
 906                 goto init_err;
 907
 908         rc = qedr_init_hw(dev);
 909         if (rc)
 910                 goto alloc_err;
 911
 912         rc = qedr_setup_irqs(dev);
 913         if (rc)
 914                 goto irq_err;
 915
 916         rc = qedr_register_device(dev);
 917         if (rc) {
 918                 DP_ERR(dev, "Unable to allocate register device\n");
 919                 goto reg_err;
 920         }
 921
 922         if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 923                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
 924
 925         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 926         return dev;
 927
 928 reg_err:
 929         qedr_sync_free_irqs(dev);
 930 irq_err:
 931         qedr_stop_hw(dev);
 932 alloc_err:
 933         qedr_free_resources(dev);
 934 init_err:
 935         ib_dealloc_device(&dev->ibdev);
 936         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 937
 938         return NULL;
 939 }
 940
 941 static void qedr_remove(struct qedr_dev *dev)
 942 {
 943         /* First unregister with stack to stop all the active traffic
 944          * of the registered clients.
 945          */
 946         ib_unregister_device(&dev->ibdev);
 947
 948         qedr_stop_hw(dev);
 949         qedr_sync_free_irqs(dev);
 950         qedr_free_resources(dev);
 951
 952         if (IS_IWARP(dev) && QEDR_IS_CMT(dev))
 953                 dev->ops->iwarp_set_engine_affin(dev->cdev, true);
 954
 955         ib_dealloc_device(&dev->ibdev);
 956 }
 957
 958 static void qedr_close(struct qedr_dev *dev)
 959 {
 960         if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 961                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
 962 }
 963
 964 static void qedr_shutdown(struct qedr_dev *dev)
 965 {
 966         qedr_close(dev);
 967         qedr_remove(dev);
 968 }
 969
 970 static void qedr_open(struct qedr_dev *dev)
 971 {
 972         if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 973                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
 974 }
 975
 976 static void qedr_mac_address_change(struct qedr_dev *dev)
 977 {
 978         union ib_gid *sgid = &dev->sgid_tbl[0];
 979         u8 guid[8], mac_addr[6];
 980         int rc;
 981
 982         /* Update SGID */
 983         ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
 984         guid[0] = mac_addr[0] ^ 2;
 985         guid[1] = mac_addr[1];
 986         guid[2] = mac_addr[2];
 987         guid[3] = 0xff;
 988         guid[4] = 0xfe;
 989         guid[5] = mac_addr[3];
 990         guid[6] = mac_addr[4];
 991         guid[7] = mac_addr[5];
 992         sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 993         memcpy(&sgid->raw[8], guid, sizeof(guid));
 994
 995         /* Update LL2 */
 996         rc = dev->ops->ll2_set_mac_filter(dev->cdev,
 997                                           dev->gsi_ll2_mac_address,
 998                                           dev->ndev->dev_addr);
 999
1000         ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
1001
1002         qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
1003
1004         if (rc)
1005                 DP_ERR(dev, "Error updating mac filter\n");
1006 }
1007
1008 /* event handling via NIC driver ensures that all the NIC specific
1009  * initialization done before RoCE driver notifies
1010  * event to stack.
1011  */
1012 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
1013 {
1014         switch (event) {
1015         case QEDE_UP:
1016                 qedr_open(dev);
1017                 break;
1018         case QEDE_DOWN:
1019                 qedr_close(dev);
1020                 break;
1021         case QEDE_CLOSE:
1022                 qedr_shutdown(dev);
1023                 break;
1024         case QEDE_CHANGE_ADDR:
1025                 qedr_mac_address_change(dev);
1026                 break;
1027         default:
1028                 pr_err("Event not supported\n");
1029         }
1030 }
1031
1032 static struct qedr_driver qedr_drv = {
1033         .name = "qedr_driver",
1034         .add = qedr_add,
1035         .remove = qedr_remove,
1036         .notify = qedr_notify,
1037 };
1038
1039 static int __init qedr_init_module(void)
1040 {
1041         return qede_rdma_register_driver(&qedr_drv);
1042 }
1043
1044 static void __exit qedr_exit_module(void)
1045 {
1046         qede_rdma_unregister_driver(&qedr_drv);
1047 }
1048
1049 module_init(qedr_init_module);
1050 module_exit(qedr_exit_module);