drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <rdma/rdma_counter.h>
  38 #include <linux/mlx5/fs.h>
  39 #include "mlx5_ib.h"
  40 #include "ib_rep.h"
  41 #include "cmd.h"
  42 #include "qp.h"
  43
  44 enum {
  45         MLX5_IB_ACK_REQ_FREQ    = 8,
  46 };
  47
  48 enum {
  49         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  50         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  51         MLX5_IB_LINK_TYPE_IB            = 0,
  52         MLX5_IB_LINK_TYPE_ETH           = 1
  53 };
  54
  55 enum {
  56         MLX5_IB_SQ_STRIDE       = 6,
  57         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  58 };
  59
  60 static const u32 mlx5_ib_opcode[] = {
  61         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  62         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  63         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  64         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  65         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  66         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  67         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  68         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  69         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  70         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  71         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  72         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  73         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  74         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  75 };
  76
  77 struct mlx5_wqe_eth_pad {
  78         u8 rsvd0[16];
  79 };
  80
  81 enum raw_qp_set_mask_map {
  82         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  83         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  84 };
  85
  86 struct mlx5_modify_raw_qp_param {
  87         u16 operation;
  88
  89         u32 set_mask; /* raw_qp_set_mask_map */
  90
  91         struct mlx5_rate_limit rl;
  92
  93         u8 rq_q_ctr_id;
  94         u16 port;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 /**
 112  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
 113  * to kernel buffer
 114  *
 115  * @umem: User space memory where the WQ is
 116  * @buffer: buffer to copy to
 117  * @buflen: buffer length
 118  * @wqe_index: index of WQE to copy from
 119  * @wq_offset: offset to start of WQ
 120  * @wq_wqe_cnt: number of WQEs in WQ
 121  * @wq_wqe_shift: log2 of WQE size
 122  * @bcnt: number of bytes to copy
 123  * @bytes_copied: number of bytes to copy (return value)
 124  *
 125  * Copies from start of WQE bcnt or less bytes.
 126  * Does not gurantee to copy the entire WQE.
 127  *
 128  * Return: zero on success, or an error code.
 129  */
 130 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
 131                                         size_t buflen, int wqe_index,
 132                                         int wq_offset, int wq_wqe_cnt,
 133                                         int wq_wqe_shift, int bcnt,
 134                                         size_t *bytes_copied)
 135 {
 136         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 137         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 138         size_t copy_length;
 139         int ret;
 140
 141         /* don't copy more than requested, more than buffer length or
 142          * beyond WQ end
 143          */
 144         copy_length = min_t(u32, buflen, wq_end - offset);
 145         copy_length = min_t(u32, copy_length, bcnt);
 146
 147         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 148         if (ret)
 149                 return ret;
 150
 151         if (!ret && bytes_copied)
 152                 *bytes_copied = copy_length;
 153
 154         return 0;
 155 }
 156
 157 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 158                                       void *buffer, size_t buflen, size_t *bc)
 159 {
 160         struct mlx5_wqe_ctrl_seg *ctrl;
 161         size_t bytes_copied = 0;
 162         size_t wqe_length;
 163         void *p;
 164         int ds;
 165
 166         wqe_index = wqe_index & qp->sq.fbc.sz_m1;
 167
 168         /* read the control segment first */
 169         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 170         ctrl = p;
 171         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 172         wqe_length = ds * MLX5_WQE_DS_UNITS;
 173
 174         /* read rest of WQE if it spreads over more than one stride */
 175         while (bytes_copied < wqe_length) {
 176                 size_t copy_length =
 177                         min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
 178
 179                 if (!copy_length)
 180                         break;
 181
 182                 memcpy(buffer + bytes_copied, p, copy_length);
 183                 bytes_copied += copy_length;
 184
 185                 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
 186                 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 187         }
 188         *bc = bytes_copied;
 189         return 0;
 190 }
 191
 192 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 193                                     void *buffer, size_t buflen, size_t *bc)
 194 {
 195         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 196         struct ib_umem *umem = base->ubuffer.umem;
 197         struct mlx5_ib_wq *wq = &qp->sq;
 198         struct mlx5_wqe_ctrl_seg *ctrl;
 199         size_t bytes_copied;
 200         size_t bytes_copied2;
 201         size_t wqe_length;
 202         int ret;
 203         int ds;
 204
 205         /* at first read as much as possible */
 206         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 207                                            wq->offset, wq->wqe_cnt,
 208                                            wq->wqe_shift, buflen,
 209                                            &bytes_copied);
 210         if (ret)
 211                 return ret;
 212
 213         /* we need at least control segment size to proceed */
 214         if (bytes_copied < sizeof(*ctrl))
 215                 return -EINVAL;
 216
 217         ctrl = buffer;
 218         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 219         wqe_length = ds * MLX5_WQE_DS_UNITS;
 220
 221         /* if we copied enough then we are done */
 222         if (bytes_copied >= wqe_length) {
 223                 *bc = bytes_copied;
 224                 return 0;
 225         }
 226
 227         /* otherwise this a wrapped around wqe
 228          * so read the remaining bytes starting
 229          * from  wqe_index 0
 230          */
 231         ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
 232                                            buflen - bytes_copied, 0, wq->offset,
 233                                            wq->wqe_cnt, wq->wqe_shift,
 234                                            wqe_length - bytes_copied,
 235                                            &bytes_copied2);
 236
 237         if (ret)
 238                 return ret;
 239         *bc = bytes_copied + bytes_copied2;
 240         return 0;
 241 }
 242
 243 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 244                         size_t buflen, size_t *bc)
 245 {
 246         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 247         struct ib_umem *umem = base->ubuffer.umem;
 248
 249         if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
 250                 return -EINVAL;
 251
 252         if (!umem)
 253                 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
 254                                                   buflen, bc);
 255
 256         return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
 257 }
 258
 259 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
 260                                     void *buffer, size_t buflen, size_t *bc)
 261 {
 262         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 263         struct ib_umem *umem = base->ubuffer.umem;
 264         struct mlx5_ib_wq *wq = &qp->rq;
 265         size_t bytes_copied;
 266         int ret;
 267
 268         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 269                                            wq->offset, wq->wqe_cnt,
 270                                            wq->wqe_shift, buflen,
 271                                            &bytes_copied);
 272
 273         if (ret)
 274                 return ret;
 275         *bc = bytes_copied;
 276         return 0;
 277 }
 278
 279 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 280                         size_t buflen, size_t *bc)
 281 {
 282         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 283         struct ib_umem *umem = base->ubuffer.umem;
 284         struct mlx5_ib_wq *wq = &qp->rq;
 285         size_t wqe_size = 1 << wq->wqe_shift;
 286
 287         if (buflen < wqe_size)
 288                 return -EINVAL;
 289
 290         if (!umem)
 291                 return -EOPNOTSUPP;
 292
 293         return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
 294 }
 295
 296 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
 297                                      void *buffer, size_t buflen, size_t *bc)
 298 {
 299         struct ib_umem *umem = srq->umem;
 300         size_t bytes_copied;
 301         int ret;
 302
 303         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
 304                                            srq->msrq.max, srq->msrq.wqe_shift,
 305                                            buflen, &bytes_copied);
 306
 307         if (ret)
 308                 return ret;
 309         *bc = bytes_copied;
 310         return 0;
 311 }
 312
 313 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
 314                          size_t buflen, size_t *bc)
 315 {
 316         struct ib_umem *umem = srq->umem;
 317         size_t wqe_size = 1 << srq->msrq.wqe_shift;
 318
 319         if (buflen < wqe_size)
 320                 return -EINVAL;
 321
 322         if (!umem)
 323                 return -EOPNOTSUPP;
 324
 325         return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
 326 }
 327
 328 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 329 {
 330         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 331         struct ib_event event;
 332
 333         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 334                 /* This event is only valid for trans_qps */
 335                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 336         }
 337
 338         if (ibqp->event_handler) {
 339                 event.device     = ibqp->device;
 340                 event.element.qp = ibqp;
 341                 switch (type) {
 342                 case MLX5_EVENT_TYPE_PATH_MIG:
 343                         event.event = IB_EVENT_PATH_MIG;
 344                         break;
 345                 case MLX5_EVENT_TYPE_COMM_EST:
 346                         event.event = IB_EVENT_COMM_EST;
 347                         break;
 348                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 349                         event.event = IB_EVENT_SQ_DRAINED;
 350                         break;
 351                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 352                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 353                         break;
 354                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 355                         event.event = IB_EVENT_QP_FATAL;
 356                         break;
 357                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 358                         event.event = IB_EVENT_PATH_MIG_ERR;
 359                         break;
 360                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 361                         event.event = IB_EVENT_QP_REQ_ERR;
 362                         break;
 363                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 364                         event.event = IB_EVENT_QP_ACCESS_ERR;
 365                         break;
 366                 default:
 367                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 368                         return;
 369                 }
 370
 371                 ibqp->event_handler(&event, ibqp->qp_context);
 372         }
 373 }
 374
 375 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 376                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 377 {
 378         int wqe_size;
 379         int wq_size;
 380
 381         /* Sanity check RQ size before proceeding */
 382         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 383                 return -EINVAL;
 384
 385         if (!has_rq) {
 386                 qp->rq.max_gs = 0;
 387                 qp->rq.wqe_cnt = 0;
 388                 qp->rq.wqe_shift = 0;
 389                 cap->max_recv_wr = 0;
 390                 cap->max_recv_sge = 0;
 391         } else {
 392                 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
 393
 394                 if (ucmd) {
 395                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 396                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 397                                 return -EINVAL;
 398                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 399                         if ((1 << qp->rq.wqe_shift) /
 400                                     sizeof(struct mlx5_wqe_data_seg) <
 401                             wq_sig)
 402                                 return -EINVAL;
 403                         qp->rq.max_gs =
 404                                 (1 << qp->rq.wqe_shift) /
 405                                         sizeof(struct mlx5_wqe_data_seg) -
 406                                 wq_sig;
 407                         qp->rq.max_post = qp->rq.wqe_cnt;
 408                 } else {
 409                         wqe_size =
 410                                 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
 411                                          0;
 412                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 413                         wqe_size = roundup_pow_of_two(wqe_size);
 414                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 415                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 416                         qp->rq.wqe_cnt = wq_size / wqe_size;
 417                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 418                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 419                                             wqe_size,
 420                                             MLX5_CAP_GEN(dev->mdev,
 421                                                          max_wqe_sz_rq));
 422                                 return -EINVAL;
 423                         }
 424                         qp->rq.wqe_shift = ilog2(wqe_size);
 425                         qp->rq.max_gs =
 426                                 (1 << qp->rq.wqe_shift) /
 427                                         sizeof(struct mlx5_wqe_data_seg) -
 428                                 wq_sig;
 429                         qp->rq.max_post = qp->rq.wqe_cnt;
 430                 }
 431         }
 432
 433         return 0;
 434 }
 435
 436 static int sq_overhead(struct ib_qp_init_attr *attr)
 437 {
 438         int size = 0;
 439
 440         switch (attr->qp_type) {
 441         case IB_QPT_XRC_INI:
 442                 size += sizeof(struct mlx5_wqe_xrc_seg);
 443                 /* fall through */
 444         case IB_QPT_RC:
 445                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 446                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 447                             sizeof(struct mlx5_wqe_raddr_seg),
 448                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 449                             sizeof(struct mlx5_mkey_seg) +
 450                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 451                             MLX5_IB_UMR_OCTOWORD);
 452                 break;
 453
 454         case IB_QPT_XRC_TGT:
 455                 return 0;
 456
 457         case IB_QPT_UC:
 458                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 459                         max(sizeof(struct mlx5_wqe_raddr_seg),
 460                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 461                             sizeof(struct mlx5_mkey_seg));
 462                 break;
 463
 464         case IB_QPT_UD:
 465                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 466                         size += sizeof(struct mlx5_wqe_eth_pad) +
 467                                 sizeof(struct mlx5_wqe_eth_seg);
 468                 /* fall through */
 469         case IB_QPT_SMI:
 470         case MLX5_IB_QPT_HW_GSI:
 471                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 472                         sizeof(struct mlx5_wqe_datagram_seg);
 473                 break;
 474
 475         case MLX5_IB_QPT_REG_UMR:
 476                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 477                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 478                         sizeof(struct mlx5_mkey_seg);
 479                 break;
 480
 481         default:
 482                 return -EINVAL;
 483         }
 484
 485         return size;
 486 }
 487
 488 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 489 {
 490         int inl_size = 0;
 491         int size;
 492
 493         size = sq_overhead(attr);
 494         if (size < 0)
 495                 return size;
 496
 497         if (attr->cap.max_inline_data) {
 498                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 499                         attr->cap.max_inline_data;
 500         }
 501
 502         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 503         if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
 504             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 505                 return MLX5_SIG_WQE_SIZE;
 506         else
 507                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 508 }
 509
 510 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 511 {
 512         int max_sge;
 513
 514         if (attr->qp_type == IB_QPT_RC)
 515                 max_sge = (min_t(int, wqe_size, 512) -
 516                            sizeof(struct mlx5_wqe_ctrl_seg) -
 517                            sizeof(struct mlx5_wqe_raddr_seg)) /
 518                         sizeof(struct mlx5_wqe_data_seg);
 519         else if (attr->qp_type == IB_QPT_XRC_INI)
 520                 max_sge = (min_t(int, wqe_size, 512) -
 521                            sizeof(struct mlx5_wqe_ctrl_seg) -
 522                            sizeof(struct mlx5_wqe_xrc_seg) -
 523                            sizeof(struct mlx5_wqe_raddr_seg)) /
 524                         sizeof(struct mlx5_wqe_data_seg);
 525         else
 526                 max_sge = (wqe_size - sq_overhead(attr)) /
 527                         sizeof(struct mlx5_wqe_data_seg);
 528
 529         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 530                      sizeof(struct mlx5_wqe_data_seg));
 531 }
 532
 533 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 534                         struct mlx5_ib_qp *qp)
 535 {
 536         int wqe_size;
 537         int wq_size;
 538
 539         if (!attr->cap.max_send_wr)
 540                 return 0;
 541
 542         wqe_size = calc_send_wqe(attr);
 543         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 544         if (wqe_size < 0)
 545                 return wqe_size;
 546
 547         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 548                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 549                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 550                 return -EINVAL;
 551         }
 552
 553         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 554                               sizeof(struct mlx5_wqe_inline_seg);
 555         attr->cap.max_inline_data = qp->max_inline_data;
 556
 557         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 558         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 559         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 560                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 561                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 562                             qp->sq.wqe_cnt,
 563                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 564                 return -ENOMEM;
 565         }
 566         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 567         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 568         if (qp->sq.max_gs < attr->cap.max_send_sge)
 569                 return -ENOMEM;
 570
 571         attr->cap.max_send_sge = qp->sq.max_gs;
 572         qp->sq.max_post = wq_size / wqe_size;
 573         attr->cap.max_send_wr = qp->sq.max_post;
 574
 575         return wq_size;
 576 }
 577
 578 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 579                             struct mlx5_ib_qp *qp,
 580                             struct mlx5_ib_create_qp *ucmd,
 581                             struct mlx5_ib_qp_base *base,
 582                             struct ib_qp_init_attr *attr)
 583 {
 584         int desc_sz = 1 << qp->sq.wqe_shift;
 585
 586         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 587                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 588                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 589                 return -EINVAL;
 590         }
 591
 592         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 593                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 594                              ucmd->sq_wqe_count);
 595                 return -EINVAL;
 596         }
 597
 598         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 599
 600         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 601                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 602                              qp->sq.wqe_cnt,
 603                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 604                 return -EINVAL;
 605         }
 606
 607         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 608             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
 609                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 610                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 611         } else {
 612                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 613                                          (qp->sq.wqe_cnt << 6);
 614         }
 615
 616         return 0;
 617 }
 618
 619 static int qp_has_rq(struct ib_qp_init_attr *attr)
 620 {
 621         if (attr->qp_type == IB_QPT_XRC_INI ||
 622             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 623             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 624             !attr->cap.max_recv_wr)
 625                 return 0;
 626
 627         return 1;
 628 }
 629
 630 enum {
 631         /* this is the first blue flame register in the array of bfregs assigned
 632          * to a processes. Since we do not use it for blue flame but rather
 633          * regular 64 bit doorbells, we do not need a lock for maintaiing
 634          * "odd/even" order
 635          */
 636         NUM_NON_BLUE_FLAME_BFREGS = 1,
 637 };
 638
 639 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 640 {
 641         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 642 }
 643
 644 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 645                          struct mlx5_bfreg_info *bfregi)
 646 {
 647         int n;
 648
 649         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 650             NUM_NON_BLUE_FLAME_BFREGS;
 651
 652         return n >= 0 ? n : 0;
 653 }
 654
 655 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 656                            struct mlx5_bfreg_info *bfregi)
 657 {
 658         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 659 }
 660
 661 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 662                           struct mlx5_bfreg_info *bfregi)
 663 {
 664         int med;
 665
 666         med = num_med_bfreg(dev, bfregi);
 667         return ++med;
 668 }
 669
 670 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 671                                   struct mlx5_bfreg_info *bfregi)
 672 {
 673         int i;
 674
 675         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 676                 if (!bfregi->count[i]) {
 677                         bfregi->count[i]++;
 678                         return i;
 679                 }
 680         }
 681
 682         return -ENOMEM;
 683 }
 684
 685 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 686                                  struct mlx5_bfreg_info *bfregi)
 687 {
 688         int minidx = first_med_bfreg(dev, bfregi);
 689         int i;
 690
 691         if (minidx < 0)
 692                 return minidx;
 693
 694         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 695                 if (bfregi->count[i] < bfregi->count[minidx])
 696                         minidx = i;
 697                 if (!bfregi->count[minidx])
 698                         break;
 699         }
 700
 701         bfregi->count[minidx]++;
 702         return minidx;
 703 }
 704
 705 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 706                        struct mlx5_bfreg_info *bfregi)
 707 {
 708         int bfregn = -ENOMEM;
 709
 710         if (bfregi->lib_uar_dyn)
 711                 return -EINVAL;
 712
 713         mutex_lock(&bfregi->lock);
 714         if (bfregi->ver >= 2) {
 715                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 716                 if (bfregn < 0)
 717                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 718         }
 719
 720         if (bfregn < 0) {
 721                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 722                 bfregn = 0;
 723                 bfregi->count[bfregn]++;
 724         }
 725         mutex_unlock(&bfregi->lock);
 726
 727         return bfregn;
 728 }
 729
 730 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 731 {
 732         mutex_lock(&bfregi->lock);
 733         bfregi->count[bfregn]--;
 734         mutex_unlock(&bfregi->lock);
 735 }
 736
 737 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 738 {
 739         switch (state) {
 740         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 741         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 742         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 743         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 744         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 745         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 746         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 747         default:                return -1;
 748         }
 749 }
 750
 751 static int to_mlx5_st(enum ib_qp_type type)
 752 {
 753         switch (type) {
 754         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 755         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 756         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 757         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 758         case IB_QPT_XRC_INI:
 759         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 760         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 761         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 762         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 763         case IB_QPT_RAW_PACKET:         return MLX5_QP_ST_RAW_ETHERTYPE;
 764         default:                return -EINVAL;
 765         }
 766 }
 767
 768 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 769                              struct mlx5_ib_cq *recv_cq);
 770 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 771                                struct mlx5_ib_cq *recv_cq);
 772
 773 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 774                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 775                         bool dyn_bfreg)
 776 {
 777         unsigned int bfregs_per_sys_page;
 778         u32 index_of_sys_page;
 779         u32 offset;
 780
 781         if (bfregi->lib_uar_dyn)
 782                 return -EINVAL;
 783
 784         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 785                                 MLX5_NON_FP_BFREGS_PER_UAR;
 786         index_of_sys_page = bfregn / bfregs_per_sys_page;
 787
 788         if (dyn_bfreg) {
 789                 index_of_sys_page += bfregi->num_static_sys_pages;
 790
 791                 if (index_of_sys_page >= bfregi->num_sys_pages)
 792                         return -EINVAL;
 793
 794                 if (bfregn > bfregi->num_dyn_bfregs ||
 795                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 796                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 797                         return -EINVAL;
 798                 }
 799         }
 800
 801         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 802         return bfregi->sys_pages[index_of_sys_page] + offset;
 803 }
 804
 805 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 806                             unsigned long addr, size_t size,
 807                             struct ib_umem **umem, int *npages, int *page_shift,
 808                             int *ncont, u32 *offset)
 809 {
 810         int err;
 811
 812         *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
 813         if (IS_ERR(*umem)) {
 814                 mlx5_ib_dbg(dev, "umem_get failed\n");
 815                 return PTR_ERR(*umem);
 816         }
 817
 818         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 819
 820         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 821         if (err) {
 822                 mlx5_ib_warn(dev, "bad offset\n");
 823                 goto err_umem;
 824         }
 825
 826         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 827                     addr, size, *npages, *page_shift, *ncont, *offset);
 828
 829         return 0;
 830
 831 err_umem:
 832         ib_umem_release(*umem);
 833         *umem = NULL;
 834
 835         return err;
 836 }
 837
 838 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 839                             struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
 840 {
 841         struct mlx5_ib_ucontext *context =
 842                 rdma_udata_to_drv_context(
 843                         udata,
 844                         struct mlx5_ib_ucontext,
 845                         ibucontext);
 846
 847         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 848                 atomic_dec(&dev->delay_drop.rqs_cnt);
 849
 850         mlx5_ib_db_unmap_user(context, &rwq->db);
 851         ib_umem_release(rwq->umem);
 852 }
 853
 854 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 855                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 856                           struct mlx5_ib_create_wq *ucmd)
 857 {
 858         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
 859                 udata, struct mlx5_ib_ucontext, ibucontext);
 860         int page_shift = 0;
 861         int npages;
 862         u32 offset = 0;
 863         int ncont = 0;
 864         int err;
 865
 866         if (!ucmd->buf_addr)
 867                 return -EINVAL;
 868
 869         rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
 870         if (IS_ERR(rwq->umem)) {
 871                 mlx5_ib_dbg(dev, "umem_get failed\n");
 872                 err = PTR_ERR(rwq->umem);
 873                 return err;
 874         }
 875
 876         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 877                            &ncont, NULL);
 878         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 879                                      &rwq->rq_page_offset);
 880         if (err) {
 881                 mlx5_ib_warn(dev, "bad offset\n");
 882                 goto err_umem;
 883         }
 884
 885         rwq->rq_num_pas = ncont;
 886         rwq->page_shift = page_shift;
 887         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 888         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 889
 890         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 891                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 892                     npages, page_shift, ncont, offset);
 893
 894         err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
 895         if (err) {
 896                 mlx5_ib_dbg(dev, "map failed\n");
 897                 goto err_umem;
 898         }
 899
 900         return 0;
 901
 902 err_umem:
 903         ib_umem_release(rwq->umem);
 904         return err;
 905 }
 906
 907 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 908                          struct mlx5_bfreg_info *bfregi, int bfregn)
 909 {
 910         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 911                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 912 }
 913
 914 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 915                            struct mlx5_ib_qp *qp, struct ib_udata *udata,
 916                            struct ib_qp_init_attr *attr, u32 **in,
 917                            struct mlx5_ib_create_qp_resp *resp, int *inlen,
 918                            struct mlx5_ib_qp_base *base,
 919                            struct mlx5_ib_create_qp *ucmd)
 920 {
 921         struct mlx5_ib_ucontext *context;
 922         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 923         int page_shift = 0;
 924         int uar_index = 0;
 925         int npages;
 926         u32 offset = 0;
 927         int bfregn;
 928         int ncont = 0;
 929         __be64 *pas;
 930         void *qpc;
 931         int err;
 932         u16 uid;
 933         u32 uar_flags;
 934
 935         context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
 936                                             ibucontext);
 937         uar_flags = qp->flags_en &
 938                     (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
 939         switch (uar_flags) {
 940         case MLX5_QP_FLAG_UAR_PAGE_INDEX:
 941                 uar_index = ucmd->bfreg_index;
 942                 bfregn = MLX5_IB_INVALID_BFREG;
 943                 break;
 944         case MLX5_QP_FLAG_BFREG_INDEX:
 945                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 946                                                 ucmd->bfreg_index, true);
 947                 if (uar_index < 0)
 948                         return uar_index;
 949                 bfregn = MLX5_IB_INVALID_BFREG;
 950                 break;
 951         case 0:
 952                 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
 953                         return -EINVAL;
 954                 bfregn = alloc_bfreg(dev, &context->bfregi);
 955                 if (bfregn < 0)
 956                         return bfregn;
 957                 break;
 958         default:
 959                 return -EINVAL;
 960         }
 961
 962         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 963         if (bfregn != MLX5_IB_INVALID_BFREG)
 964                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 965                                                 false);
 966
 967         qp->rq.offset = 0;
 968         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 969         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 970
 971         err = set_user_buf_size(dev, qp, ucmd, base, attr);
 972         if (err)
 973                 goto err_bfreg;
 974
 975         if (ucmd->buf_addr && ubuffer->buf_size) {
 976                 ubuffer->buf_addr = ucmd->buf_addr;
 977                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 978                                        ubuffer->buf_size, &ubuffer->umem,
 979                                        &npages, &page_shift, &ncont, &offset);
 980                 if (err)
 981                         goto err_bfreg;
 982         } else {
 983                 ubuffer->umem = NULL;
 984         }
 985
 986         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 987                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 988         *in = kvzalloc(*inlen, GFP_KERNEL);
 989         if (!*in) {
 990                 err = -ENOMEM;
 991                 goto err_umem;
 992         }
 993
 994         uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
 995         MLX5_SET(create_qp_in, *in, uid, uid);
 996         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 997         if (ubuffer->umem)
 998                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 999
1000         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1001
1002         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1003         MLX5_SET(qpc, qpc, page_offset, offset);
1004
1005         MLX5_SET(qpc, qpc, uar_page, uar_index);
1006         if (bfregn != MLX5_IB_INVALID_BFREG)
1007                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
1008         else
1009                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
1010         qp->bfregn = bfregn;
1011
1012         err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
1013         if (err) {
1014                 mlx5_ib_dbg(dev, "map failed\n");
1015                 goto err_free;
1016         }
1017
1018         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1019         if (err) {
1020                 mlx5_ib_dbg(dev, "copy failed\n");
1021                 goto err_unmap;
1022         }
1023
1024         return 0;
1025
1026 err_unmap:
1027         mlx5_ib_db_unmap_user(context, &qp->db);
1028
1029 err_free:
1030         kvfree(*in);
1031
1032 err_umem:
1033         ib_umem_release(ubuffer->umem);
1034
1035 err_bfreg:
1036         if (bfregn != MLX5_IB_INVALID_BFREG)
1037                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
1038         return err;
1039 }
1040
1041 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1042                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base,
1043                             struct ib_udata *udata)
1044 {
1045         struct mlx5_ib_ucontext *context =
1046                 rdma_udata_to_drv_context(
1047                         udata,
1048                         struct mlx5_ib_ucontext,
1049                         ibucontext);
1050
1051         mlx5_ib_db_unmap_user(context, &qp->db);
1052         ib_umem_release(base->ubuffer.umem);
1053
1054         /*
1055          * Free only the BFREGs which are handled by the kernel.
1056          * BFREGs of UARs allocated dynamically are handled by user.
1057          */
1058         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1059                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1060 }
1061
1062 /* get_sq_edge - Get the next nearby edge.
1063  *
1064  * An 'edge' is defined as the first following address after the end
1065  * of the fragment or the SQ. Accordingly, during the WQE construction
1066  * which repetitively increases the pointer to write the next data, it
1067  * simply should check if it gets to an edge.
1068  *
1069  * @sq - SQ buffer.
1070  * @idx - Stride index in the SQ buffer.
1071  *
1072  * Return:
1073  *      The new edge.
1074  */
1075 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1076 {
1077         void *fragment_end;
1078
1079         fragment_end = mlx5_frag_buf_get_wqe
1080                 (&sq->fbc,
1081                  mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1082
1083         return fragment_end + MLX5_SEND_WQE_BB;
1084 }
1085
1086 static int _create_kernel_qp(struct mlx5_ib_dev *dev,
1087                              struct ib_qp_init_attr *init_attr,
1088                              struct mlx5_ib_qp *qp, u32 **in, int *inlen,
1089                              struct mlx5_ib_qp_base *base)
1090 {
1091         int uar_index;
1092         void *qpc;
1093         int err;
1094
1095         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1096                 qp->bf.bfreg = &dev->fp_bfreg;
1097         else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
1098                 qp->bf.bfreg = &dev->wc_bfreg;
1099         else
1100                 qp->bf.bfreg = &dev->bfreg;
1101
1102         /* We need to divide by two since each register is comprised of
1103          * two buffers of identical size, namely odd and even
1104          */
1105         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1106         uar_index = qp->bf.bfreg->index;
1107
1108         err = calc_sq_size(dev, init_attr, qp);
1109         if (err < 0) {
1110                 mlx5_ib_dbg(dev, "err %d\n", err);
1111                 return err;
1112         }
1113
1114         qp->rq.offset = 0;
1115         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1116         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1117
1118         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1119                                        &qp->buf, dev->mdev->priv.numa_node);
1120         if (err) {
1121                 mlx5_ib_dbg(dev, "err %d\n", err);
1122                 return err;
1123         }
1124
1125         if (qp->rq.wqe_cnt)
1126                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1127                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1128
1129         if (qp->sq.wqe_cnt) {
1130                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1131                                         MLX5_SEND_WQE_BB;
1132                 mlx5_init_fbc_offset(qp->buf.frags +
1133                                      (qp->sq.offset / PAGE_SIZE),
1134                                      ilog2(MLX5_SEND_WQE_BB),
1135                                      ilog2(qp->sq.wqe_cnt),
1136                                      sq_strides_offset, &qp->sq.fbc);
1137
1138                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1139         }
1140
1141         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1142                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1143         *in = kvzalloc(*inlen, GFP_KERNEL);
1144         if (!*in) {
1145                 err = -ENOMEM;
1146                 goto err_buf;
1147         }
1148
1149         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1150         MLX5_SET(qpc, qpc, uar_page, uar_index);
1151         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1152
1153         /* Set "fast registration enabled" for all kernel QPs */
1154         MLX5_SET(qpc, qpc, fre, 1);
1155         MLX5_SET(qpc, qpc, rlky, 1);
1156
1157         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
1158                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1159
1160         mlx5_fill_page_frag_array(&qp->buf,
1161                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1162                                                          *in, pas));
1163
1164         err = mlx5_db_alloc(dev->mdev, &qp->db);
1165         if (err) {
1166                 mlx5_ib_dbg(dev, "err %d\n", err);
1167                 goto err_free;
1168         }
1169
1170         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1171                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1172         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1173                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1174         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1175                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1176         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1177                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1178         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1179                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1180
1181         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1182             !qp->sq.w_list || !qp->sq.wqe_head) {
1183                 err = -ENOMEM;
1184                 goto err_wrid;
1185         }
1186
1187         return 0;
1188
1189 err_wrid:
1190         kvfree(qp->sq.wqe_head);
1191         kvfree(qp->sq.w_list);
1192         kvfree(qp->sq.wrid);
1193         kvfree(qp->sq.wr_data);
1194         kvfree(qp->rq.wrid);
1195         mlx5_db_free(dev->mdev, &qp->db);
1196
1197 err_free:
1198         kvfree(*in);
1199
1200 err_buf:
1201         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1202         return err;
1203 }
1204
1205 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1206 {
1207         kvfree(qp->sq.wqe_head);
1208         kvfree(qp->sq.w_list);
1209         kvfree(qp->sq.wrid);
1210         kvfree(qp->sq.wr_data);
1211         kvfree(qp->rq.wrid);
1212         if (qp->db.db)
1213                 mlx5_db_free(dev->mdev, &qp->db);
1214         if (qp->buf.frags)
1215                 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1216 }
1217
1218 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1219 {
1220         if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1221             (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
1222                 return MLX5_SRQ_RQ;
1223         else if (!qp->has_rq)
1224                 return MLX5_ZERO_LEN_RQ;
1225
1226         return MLX5_NON_ZERO_RQ;
1227 }
1228
1229 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1230                                     struct mlx5_ib_qp *qp,
1231                                     struct mlx5_ib_sq *sq, u32 tdn,
1232                                     struct ib_pd *pd)
1233 {
1234         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
1235         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1236
1237         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1238         MLX5_SET(tisc, tisc, transport_domain, tdn);
1239         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1240                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1241
1242         return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1243 }
1244
1245 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1246                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1247 {
1248         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1249 }
1250
1251 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1252 {
1253         if (sq->flow_rule)
1254                 mlx5_del_flow_rules(sq->flow_rule);
1255         sq->flow_rule = NULL;
1256 }
1257
1258 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1259                                    struct ib_udata *udata,
1260                                    struct mlx5_ib_sq *sq, void *qpin,
1261                                    struct ib_pd *pd)
1262 {
1263         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1264         __be64 *pas;
1265         void *in;
1266         void *sqc;
1267         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1268         void *wq;
1269         int inlen;
1270         int err;
1271         int page_shift = 0;
1272         int npages;
1273         int ncont = 0;
1274         u32 offset = 0;
1275
1276         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1277                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1278                                &offset);
1279         if (err)
1280                 return err;
1281
1282         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1283         in = kvzalloc(inlen, GFP_KERNEL);
1284         if (!in) {
1285                 err = -ENOMEM;
1286                 goto err_umem;
1287         }
1288
1289         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1290         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1291         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1292         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1293                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1294         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1295         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1296         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1297         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1298         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1299         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1300             MLX5_CAP_ETH(dev->mdev, swp))
1301                 MLX5_SET(sqc, sqc, allow_swp, 1);
1302
1303         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1304         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1305         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1306         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1307         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1308         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1309         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1310         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1311         MLX5_SET(wq, wq, page_offset, offset);
1312
1313         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1314         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1315
1316         err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
1317
1318         kvfree(in);
1319
1320         if (err)
1321                 goto err_umem;
1322
1323         return 0;
1324
1325 err_umem:
1326         ib_umem_release(sq->ubuffer.umem);
1327         sq->ubuffer.umem = NULL;
1328
1329         return err;
1330 }
1331
1332 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1333                                      struct mlx5_ib_sq *sq)
1334 {
1335         destroy_flow_rule_vport_sq(sq);
1336         mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
1337         ib_umem_release(sq->ubuffer.umem);
1338 }
1339
1340 static size_t get_rq_pas_size(void *qpc)
1341 {
1342         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1343         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1344         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1345         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1346         u32 po_quanta     = 1 << (log_page_size - 6);
1347         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1348         u32 page_size     = 1 << log_page_size;
1349         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1350         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1351
1352         return rq_num_pas * sizeof(u64);
1353 }
1354
1355 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1356                                    struct mlx5_ib_rq *rq, void *qpin,
1357                                    size_t qpinlen, struct ib_pd *pd)
1358 {
1359         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1360         __be64 *pas;
1361         __be64 *qp_pas;
1362         void *in;
1363         void *rqc;
1364         void *wq;
1365         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1366         size_t rq_pas_size = get_rq_pas_size(qpc);
1367         size_t inlen;
1368         int err;
1369
1370         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1371                 return -EINVAL;
1372
1373         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1374         in = kvzalloc(inlen, GFP_KERNEL);
1375         if (!in)
1376                 return -ENOMEM;
1377
1378         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1379         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1380         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1381                 MLX5_SET(rqc, rqc, vsd, 1);
1382         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1383         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1384         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1385         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1386         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1387
1388         if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
1389                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1390
1391         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1392         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1393         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1394                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1395         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1396         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1397         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1398         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1399         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1400         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1401
1402         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1403         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1404         memcpy(pas, qp_pas, rq_pas_size);
1405
1406         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
1407
1408         kvfree(in);
1409
1410         return err;
1411 }
1412
1413 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1414                                      struct mlx5_ib_rq *rq)
1415 {
1416         mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
1417 }
1418
1419 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1420                                       struct mlx5_ib_rq *rq,
1421                                       u32 qp_flags_en,
1422                                       struct ib_pd *pd)
1423 {
1424         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1425                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1426                 mlx5_ib_disable_lb(dev, false, true);
1427         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1428 }
1429
1430 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1431                                     struct mlx5_ib_rq *rq, u32 tdn,
1432                                     u32 *qp_flags_en, struct ib_pd *pd,
1433                                     u32 *out)
1434 {
1435         u8 lb_flag = 0;
1436         u32 *in;
1437         void *tirc;
1438         int inlen;
1439         int err;
1440
1441         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1442         in = kvzalloc(inlen, GFP_KERNEL);
1443         if (!in)
1444                 return -ENOMEM;
1445
1446         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1447         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1448         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1449         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1450         MLX5_SET(tirc, tirc, transport_domain, tdn);
1451         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1452                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1453
1454         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1455                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1456
1457         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1458                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1459
1460         if (dev->is_rep) {
1461                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1462                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1463         }
1464
1465         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1466         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1467         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1468         rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1469         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1470                 err = mlx5_ib_enable_lb(dev, false, true);
1471
1472                 if (err)
1473                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1474         }
1475         kvfree(in);
1476
1477         return err;
1478 }
1479
1480 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1481                                 u32 *in, size_t inlen,
1482                                 struct ib_pd *pd,
1483                                 struct ib_udata *udata,
1484                                 struct mlx5_ib_create_qp_resp *resp)
1485 {
1486         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1487         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1488         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1489         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1490                 udata, struct mlx5_ib_ucontext, ibucontext);
1491         int err;
1492         u32 tdn = mucontext->tdn;
1493         u16 uid = to_mpd(pd)->uid;
1494         u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1495
1496         if (qp->sq.wqe_cnt) {
1497                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1498                 if (err)
1499                         return err;
1500
1501                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1502                 if (err)
1503                         goto err_destroy_tis;
1504
1505                 if (uid) {
1506                         resp->tisn = sq->tisn;
1507                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1508                         resp->sqn = sq->base.mqp.qpn;
1509                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1510                 }
1511
1512                 sq->base.container_mibqp = qp;
1513                 sq->base.mqp.event = mlx5_ib_qp_event;
1514         }
1515
1516         if (qp->rq.wqe_cnt) {
1517                 rq->base.container_mibqp = qp;
1518
1519                 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
1520                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1521                 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
1522                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1523                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1524                 if (err)
1525                         goto err_destroy_sq;
1526
1527                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1528                                                out);
1529                 if (err)
1530                         goto err_destroy_rq;
1531
1532                 if (uid) {
1533                         resp->rqn = rq->base.mqp.qpn;
1534                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1535                         resp->tirn = rq->tirn;
1536                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1537                         if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1538                                 resp->tir_icm_addr = MLX5_GET(
1539                                         create_tir_out, out, icm_address_31_0);
1540                                 resp->tir_icm_addr |=
1541                                         (u64)MLX5_GET(create_tir_out, out,
1542                                                       icm_address_39_32)
1543                                         << 32;
1544                                 resp->tir_icm_addr |=
1545                                         (u64)MLX5_GET(create_tir_out, out,
1546                                                       icm_address_63_40)
1547                                         << 40;
1548                                 resp->comp_mask |=
1549                                         MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1550                         }
1551                 }
1552         }
1553
1554         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1555                                                      rq->base.mqp.qpn;
1556         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1557         if (err)
1558                 goto err_destroy_tir;
1559
1560         return 0;
1561
1562 err_destroy_tir:
1563         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1564 err_destroy_rq:
1565         destroy_raw_packet_qp_rq(dev, rq);
1566 err_destroy_sq:
1567         if (!qp->sq.wqe_cnt)
1568                 return err;
1569         destroy_raw_packet_qp_sq(dev, sq);
1570 err_destroy_tis:
1571         destroy_raw_packet_qp_tis(dev, sq, pd);
1572
1573         return err;
1574 }
1575
1576 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1577                                   struct mlx5_ib_qp *qp)
1578 {
1579         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1580         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1581         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1582
1583         if (qp->rq.wqe_cnt) {
1584                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1585                 destroy_raw_packet_qp_rq(dev, rq);
1586         }
1587
1588         if (qp->sq.wqe_cnt) {
1589                 destroy_raw_packet_qp_sq(dev, sq);
1590                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1591         }
1592 }
1593
1594 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1595                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1596 {
1597         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1598         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1599
1600         sq->sq = &qp->sq;
1601         rq->rq = &qp->rq;
1602         sq->doorbell = &qp->db;
1603         rq->doorbell = &qp->db;
1604 }
1605
1606 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1607 {
1608         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1609                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1610                 mlx5_ib_disable_lb(dev, false, true);
1611         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1612                              to_mpd(qp->ibqp.pd)->uid);
1613 }
1614
1615 static int create_rss_raw_qp_tir(struct ib_pd *pd, struct mlx5_ib_qp *qp,
1616                                  struct ib_qp_init_attr *init_attr,
1617                                  struct mlx5_ib_create_qp_rss *ucmd,
1618                                  struct ib_udata *udata)
1619 {
1620         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1621                 udata, struct mlx5_ib_ucontext, ibucontext);
1622         struct mlx5_ib_dev *dev = to_mdev(pd->device);
1623         struct mlx5_ib_create_qp_resp resp = {};
1624         int inlen;
1625         int outlen;
1626         int err;
1627         u32 *in;
1628         u32 *out;
1629         void *tirc;
1630         void *hfso;
1631         u32 selected_fields = 0;
1632         u32 outer_l4;
1633         size_t min_resp_len;
1634         u32 tdn = mucontext->tdn;
1635         u8 lb_flag = 0;
1636
1637         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1638         if (udata->outlen < min_resp_len)
1639                 return -EINVAL;
1640
1641         if (ucmd->comp_mask) {
1642                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1643                 return -EOPNOTSUPP;
1644         }
1645
1646         if (ucmd->flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1647                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1648                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1649                 mlx5_ib_dbg(dev, "invalid flags\n");
1650                 return -EOPNOTSUPP;
1651         }
1652
1653         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1654             !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1655                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1656                 return -EOPNOTSUPP;
1657         }
1658
1659         if (dev->is_rep)
1660                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1661
1662         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1663                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1664
1665         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1666                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1667
1668         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1669         if (err) {
1670                 mlx5_ib_dbg(dev, "copy failed\n");
1671                 return -EINVAL;
1672         }
1673
1674         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1675         outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1676         in = kvzalloc(inlen + outlen, GFP_KERNEL);
1677         if (!in)
1678                 return -ENOMEM;
1679
1680         out = in + MLX5_ST_SZ_DW(create_tir_in);
1681         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1682         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1683         MLX5_SET(tirc, tirc, disp_type,
1684                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1685         MLX5_SET(tirc, tirc, indirect_table,
1686                  init_attr->rwq_ind_tbl->ind_tbl_num);
1687         MLX5_SET(tirc, tirc, transport_domain, tdn);
1688
1689         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1690
1691         if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1692                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1693
1694         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1695
1696         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1697                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1698         else
1699                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1700
1701         switch (ucmd->rx_hash_function) {
1702         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1703         {
1704                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1705                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1706
1707                 if (len != ucmd->rx_key_len) {
1708                         err = -EINVAL;
1709                         goto err;
1710                 }
1711
1712                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1713                 memcpy(rss_key, ucmd->rx_hash_key, len);
1714                 break;
1715         }
1716         default:
1717                 err = -EOPNOTSUPP;
1718                 goto err;
1719         }
1720
1721         if (!ucmd->rx_hash_fields_mask) {
1722                 /* special case when this TIR serves as steering entry without hashing */
1723                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1724                         goto create_tir;
1725                 err = -EINVAL;
1726                 goto err;
1727         }
1728
1729         if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1730              (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1731              ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1732              (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1733                 err = -EINVAL;
1734                 goto err;
1735         }
1736
1737         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1738         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1739             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1740                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1741                          MLX5_L3_PROT_TYPE_IPV4);
1742         else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1743                  (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1744                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1745                          MLX5_L3_PROT_TYPE_IPV6);
1746
1747         outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1748                     (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1749                            << 0 |
1750                    ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1751                     (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1752                            << 1 |
1753                    (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1754
1755         /* Check that only one l4 protocol is set */
1756         if (outer_l4 & (outer_l4 - 1)) {
1757                 err = -EINVAL;
1758                 goto err;
1759         }
1760
1761         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1762         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1763             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1764                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1765                          MLX5_L4_PROT_TYPE_TCP);
1766         else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1767                  (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1768                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1769                          MLX5_L4_PROT_TYPE_UDP);
1770
1771         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1772             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1773                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1774
1775         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1776             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1777                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1778
1779         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1780             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1781                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1782
1783         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1784             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1785                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1786
1787         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1788                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1789
1790         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1791
1792 create_tir:
1793         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1794         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1795
1796         qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1797         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1798                 err = mlx5_ib_enable_lb(dev, false, true);
1799
1800                 if (err)
1801                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1802                                              to_mpd(pd)->uid);
1803         }
1804
1805         if (err)
1806                 goto err;
1807
1808         if (mucontext->devx_uid) {
1809                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1810                 resp.tirn = qp->rss_qp.tirn;
1811                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1812                         resp.tir_icm_addr =
1813                                 MLX5_GET(create_tir_out, out, icm_address_31_0);
1814                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1815                                                            icm_address_39_32)
1816                                              << 32;
1817                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1818                                                            icm_address_63_40)
1819                                              << 40;
1820                         resp.comp_mask |=
1821                                 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1822                 }
1823         }
1824
1825         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1826         if (err)
1827                 goto err_copy;
1828
1829         kvfree(in);
1830         /* qpn is reserved for that QP */
1831         qp->trans_qp.base.mqp.qpn = 0;
1832         qp->is_rss = true;
1833         return 0;
1834
1835 err_copy:
1836         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1837 err:
1838         kvfree(in);
1839         return err;
1840 }
1841
1842 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1843                                          struct ib_qp_init_attr *init_attr,
1844                                          struct mlx5_ib_create_qp *ucmd,
1845                                          void *qpc)
1846 {
1847         int scqe_sz;
1848         bool allow_scat_cqe = false;
1849
1850         if (ucmd)
1851                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1852
1853         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1854                 return;
1855
1856         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1857         if (scqe_sz == 128) {
1858                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1859                 return;
1860         }
1861
1862         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1863             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1864                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1865 }
1866
1867 static int atomic_size_to_mode(int size_mask)
1868 {
1869         /* driver does not support atomic_size > 256B
1870          * and does not know how to translate bigger sizes
1871          */
1872         int supported_size_mask = size_mask & 0x1ff;
1873         int log_max_size;
1874
1875         if (!supported_size_mask)
1876                 return -EOPNOTSUPP;
1877
1878         log_max_size = __fls(supported_size_mask);
1879
1880         if (log_max_size > 3)
1881                 return log_max_size;
1882
1883         return MLX5_ATOMIC_MODE_8B;
1884 }
1885
1886 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1887                            enum ib_qp_type qp_type)
1888 {
1889         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1890         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1891         int atomic_mode = -EOPNOTSUPP;
1892         int atomic_size_mask;
1893
1894         if (!atomic)
1895                 return -EOPNOTSUPP;
1896
1897         if (qp_type == MLX5_IB_QPT_DCT)
1898                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1899         else
1900                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1901
1902         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1903             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1904                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1905
1906         if (atomic_mode <= 0 &&
1907             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1908              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1909                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1910
1911         return atomic_mode;
1912 }
1913
1914 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev,
1915                              struct ib_qp_init_attr *attr,
1916                              struct mlx5_ib_qp *qp, struct ib_udata *udata,
1917                              u32 uidx)
1918 {
1919         struct mlx5_ib_resources *devr = &dev->devr;
1920         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1921         struct mlx5_core_dev *mdev = dev->mdev;
1922         struct mlx5_ib_qp_base *base;
1923         unsigned long flags;
1924         void *qpc;
1925         u32 *in;
1926         int err;
1927
1928         mutex_init(&qp->mutex);
1929
1930         if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1931                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1932
1933         in = kvzalloc(inlen, GFP_KERNEL);
1934         if (!in)
1935                 return -ENOMEM;
1936
1937         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1938
1939         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC);
1940         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1941         MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn);
1942
1943         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1944                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1945         if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1946                 MLX5_SET(qpc, qpc, cd_master, 1);
1947         if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1948                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1949         if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1950                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1951
1952         MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
1953         MLX5_SET(qpc, qpc, no_sq, 1);
1954         MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1955         MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1956         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1957         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn);
1958         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1959
1960         /* 0xffffff means we ask to work with cqe version 0 */
1961         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1962                 MLX5_SET(qpc, qpc, user_index, uidx);
1963
1964         if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1965                 MLX5_SET(qpc, qpc, end_padding_mode,
1966                          MLX5_WQ_END_PAD_MODE_ALIGN);
1967                 /* Special case to clean flag */
1968                 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
1969         }
1970
1971         base = &qp->trans_qp.base;
1972         err = mlx5_core_create_qp(dev, &base->mqp, in, inlen);
1973         kvfree(in);
1974         if (err) {
1975                 destroy_qp_user(dev, NULL, qp, base, udata);
1976                 return err;
1977         }
1978
1979         base->container_mibqp = qp;
1980         base->mqp.event = mlx5_ib_qp_event;
1981
1982         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1983         list_add_tail(&qp->qps_list, &dev->qp_list);
1984         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1985
1986         return 0;
1987 }
1988
1989 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1990                           struct ib_qp_init_attr *init_attr,
1991                           struct mlx5_ib_create_qp *ucmd,
1992                           struct ib_udata *udata, struct mlx5_ib_qp *qp,
1993                           u32 uidx)
1994 {
1995         struct mlx5_ib_resources *devr = &dev->devr;
1996         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1997         struct mlx5_core_dev *mdev = dev->mdev;
1998         struct mlx5_ib_create_qp_resp resp = {};
1999         struct mlx5_ib_cq *send_cq;
2000         struct mlx5_ib_cq *recv_cq;
2001         unsigned long flags;
2002         struct mlx5_ib_qp_base *base;
2003         int mlx5_st;
2004         void *qpc;
2005         u32 *in;
2006         int err;
2007
2008         mutex_init(&qp->mutex);
2009         spin_lock_init(&qp->sq.lock);
2010         spin_lock_init(&qp->rq.lock);
2011
2012         mlx5_st = to_mlx5_st(qp->type);
2013         if (mlx5_st < 0)
2014                 return -EINVAL;
2015
2016         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2017                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2018
2019         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
2020                 qp->underlay_qpn = init_attr->source_qpn;
2021
2022         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2023                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
2024                &qp->raw_packet_qp.rq.base :
2025                &qp->trans_qp.base;
2026
2027         qp->has_rq = qp_has_rq(init_attr);
2028         err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
2029         if (err) {
2030                 mlx5_ib_dbg(dev, "err %d\n", err);
2031                 return err;
2032         }
2033
2034         if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
2035             ucmd->rq_wqe_count != qp->rq.wqe_cnt)
2036                 return -EINVAL;
2037
2038         if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
2039                 return -EINVAL;
2040
2041         err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, &resp, &inlen,
2042                               base, ucmd);
2043         if (err)
2044                 return err;
2045
2046         if (is_sqp(init_attr->qp_type))
2047                 qp->port = init_attr->port_num;
2048
2049         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2050
2051         MLX5_SET(qpc, qpc, st, mlx5_st);
2052         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2053         MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
2054
2055         if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
2056                 MLX5_SET(qpc, qpc, wq_signature, 1);
2057
2058         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2059                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2060
2061         if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
2062                 MLX5_SET(qpc, qpc, cd_master, 1);
2063         if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
2064                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2065         if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
2066                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2067         if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
2068                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2069         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2070             (init_attr->qp_type == IB_QPT_RC ||
2071              init_attr->qp_type == IB_QPT_UC)) {
2072                 int rcqe_sz = rcqe_sz =
2073                         mlx5_ib_get_cqe_size(init_attr->recv_cq);
2074
2075                 MLX5_SET(qpc, qpc, cs_res,
2076                          rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2077                                           MLX5_RES_SCAT_DATA32_CQE);
2078         }
2079         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2080             (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
2081                 configure_requester_scat_cqe(dev, init_attr, ucmd, qpc);
2082
2083         if (qp->rq.wqe_cnt) {
2084                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2085                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2086         }
2087
2088         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2089
2090         if (qp->sq.wqe_cnt) {
2091                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2092         } else {
2093                 MLX5_SET(qpc, qpc, no_sq, 1);
2094                 if (init_attr->srq &&
2095                     init_attr->srq->srq_type == IB_SRQT_TM)
2096                         MLX5_SET(qpc, qpc, offload_type,
2097                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2098         }
2099
2100         /* Set default resources */
2101         switch (init_attr->qp_type) {
2102         case IB_QPT_XRC_INI:
2103                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2104                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2105                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2106                 break;
2107         default:
2108                 if (init_attr->srq) {
2109                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2110                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2111                 } else {
2112                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2113                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2114                 }
2115         }
2116
2117         if (init_attr->send_cq)
2118                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2119
2120         if (init_attr->recv_cq)
2121                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2122
2123         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2124
2125         /* 0xffffff means we ask to work with cqe version 0 */
2126         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2127                 MLX5_SET(qpc, qpc, user_index, uidx);
2128
2129         if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2130             init_attr->qp_type != IB_QPT_RAW_PACKET) {
2131                 MLX5_SET(qpc, qpc, end_padding_mode,
2132                          MLX5_WQ_END_PAD_MODE_ALIGN);
2133                 /* Special case to clean flag */
2134                 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
2135         }
2136
2137         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2138             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2139                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
2140                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2141                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2142                                            &resp);
2143         } else
2144                 err = mlx5_core_create_qp(dev, &base->mqp, in, inlen);
2145
2146         kvfree(in);
2147         if (err)
2148                 goto err_create;
2149
2150         base->container_mibqp = qp;
2151         base->mqp.event = mlx5_ib_qp_event;
2152
2153         get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
2154                 &send_cq, &recv_cq);
2155         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2156         mlx5_ib_lock_cqs(send_cq, recv_cq);
2157         /* Maintain device to QPs access, needed for further handling via reset
2158          * flow
2159          */
2160         list_add_tail(&qp->qps_list, &dev->qp_list);
2161         /* Maintain CQ to QPs access, needed for further handling via reset flow
2162          */
2163         if (send_cq)
2164                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2165         if (recv_cq)
2166                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2167         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2168         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2169
2170         return 0;
2171
2172 err_create:
2173         if (udata)
2174                 destroy_qp_user(dev, pd, qp, base, udata);
2175         else
2176                 destroy_qp_kernel(dev, qp);
2177         return err;
2178 }
2179
2180 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2181                             struct ib_qp_init_attr *attr, struct mlx5_ib_qp *qp,
2182                             u32 uidx)
2183 {
2184         struct mlx5_ib_resources *devr = &dev->devr;
2185         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2186         struct mlx5_core_dev *mdev = dev->mdev;
2187         struct mlx5_ib_cq *send_cq;
2188         struct mlx5_ib_cq *recv_cq;
2189         unsigned long flags;
2190         struct mlx5_ib_qp_base *base;
2191         int mlx5_st;
2192         void *qpc;
2193         u32 *in;
2194         int err;
2195
2196         mutex_init(&qp->mutex);
2197         spin_lock_init(&qp->sq.lock);
2198         spin_lock_init(&qp->rq.lock);
2199
2200         mlx5_st = to_mlx5_st(qp->type);
2201         if (mlx5_st < 0)
2202                 return -EINVAL;
2203
2204         if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2205                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2206
2207         base = &qp->trans_qp.base;
2208
2209         qp->has_rq = qp_has_rq(attr);
2210         err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL);
2211         if (err) {
2212                 mlx5_ib_dbg(dev, "err %d\n", err);
2213                 return err;
2214         }
2215
2216         err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base);
2217         if (err)
2218                 return err;
2219
2220         if (is_sqp(attr->qp_type))
2221                 qp->port = attr->port_num;
2222
2223         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2224
2225         MLX5_SET(qpc, qpc, st, mlx5_st);
2226         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2227
2228         if (attr->qp_type != MLX5_IB_QPT_REG_UMR)
2229                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2230         else
2231                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2232
2233
2234         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2235                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2236
2237         if (qp->rq.wqe_cnt) {
2238                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2239                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2240         }
2241
2242         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr));
2243
2244         if (qp->sq.wqe_cnt)
2245                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2246         else
2247                 MLX5_SET(qpc, qpc, no_sq, 1);
2248
2249         if (attr->srq) {
2250                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2251                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2252                          to_msrq(attr->srq)->msrq.srqn);
2253         } else {
2254                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2255                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2256                          to_msrq(devr->s1)->msrq.srqn);
2257         }
2258
2259         if (attr->send_cq)
2260                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn);
2261
2262         if (attr->recv_cq)
2263                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn);
2264
2265         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2266
2267         /* 0xffffff means we ask to work with cqe version 0 */
2268         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2269                 MLX5_SET(qpc, qpc, user_index, uidx);
2270
2271         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2272         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2273                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2274
2275         err = mlx5_core_create_qp(dev, &base->mqp, in, inlen);
2276         kvfree(in);
2277         if (err)
2278                 goto err_create;
2279
2280         base->container_mibqp = qp;
2281         base->mqp.event = mlx5_ib_qp_event;
2282
2283         get_cqs(qp->type, attr->send_cq, attr->recv_cq,
2284                 &send_cq, &recv_cq);
2285         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2286         mlx5_ib_lock_cqs(send_cq, recv_cq);
2287         /* Maintain device to QPs access, needed for further handling via reset
2288          * flow
2289          */
2290         list_add_tail(&qp->qps_list, &dev->qp_list);
2291         /* Maintain CQ to QPs access, needed for further handling via reset flow
2292          */
2293         if (send_cq)
2294                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2295         if (recv_cq)
2296                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2297         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2298         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2299
2300         return 0;
2301
2302 err_create:
2303         destroy_qp_kernel(dev, qp);
2304         return err;
2305 }
2306
2307 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2308         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2309 {
2310         if (send_cq) {
2311                 if (recv_cq) {
2312                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2313                                 spin_lock(&send_cq->lock);
2314                                 spin_lock_nested(&recv_cq->lock,
2315                                                  SINGLE_DEPTH_NESTING);
2316                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2317                                 spin_lock(&send_cq->lock);
2318                                 __acquire(&recv_cq->lock);
2319                         } else {
2320                                 spin_lock(&recv_cq->lock);
2321                                 spin_lock_nested(&send_cq->lock,
2322                                                  SINGLE_DEPTH_NESTING);
2323                         }
2324                 } else {
2325                         spin_lock(&send_cq->lock);
2326                         __acquire(&recv_cq->lock);
2327                 }
2328         } else if (recv_cq) {
2329                 spin_lock(&recv_cq->lock);
2330                 __acquire(&send_cq->lock);
2331         } else {
2332                 __acquire(&send_cq->lock);
2333                 __acquire(&recv_cq->lock);
2334         }
2335 }
2336
2337 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2338         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2339 {
2340         if (send_cq) {
2341                 if (recv_cq) {
2342                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2343                                 spin_unlock(&recv_cq->lock);
2344                                 spin_unlock(&send_cq->lock);
2345                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2346                                 __release(&recv_cq->lock);
2347                                 spin_unlock(&send_cq->lock);
2348                         } else {
2349                                 spin_unlock(&send_cq->lock);
2350                                 spin_unlock(&recv_cq->lock);
2351                         }
2352                 } else {
2353                         __release(&recv_cq->lock);
2354                         spin_unlock(&send_cq->lock);
2355                 }
2356         } else if (recv_cq) {
2357                 __release(&send_cq->lock);
2358                 spin_unlock(&recv_cq->lock);
2359         } else {
2360                 __release(&recv_cq->lock);
2361                 __release(&send_cq->lock);
2362         }
2363 }
2364
2365 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2366 {
2367         return to_mpd(qp->ibqp.pd);
2368 }
2369
2370 static void get_cqs(enum ib_qp_type qp_type,
2371                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2372                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2373 {
2374         switch (qp_type) {
2375         case IB_QPT_XRC_TGT:
2376                 *send_cq = NULL;
2377                 *recv_cq = NULL;
2378                 break;
2379         case MLX5_IB_QPT_REG_UMR:
2380         case IB_QPT_XRC_INI:
2381                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2382                 *recv_cq = NULL;
2383                 break;
2384
2385         case IB_QPT_SMI:
2386         case MLX5_IB_QPT_HW_GSI:
2387         case IB_QPT_RC:
2388         case IB_QPT_UC:
2389         case IB_QPT_UD:
2390         case IB_QPT_RAW_PACKET:
2391                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2392                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2393                 break;
2394         default:
2395                 *send_cq = NULL;
2396                 *recv_cq = NULL;
2397                 break;
2398         }
2399 }
2400
2401 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2402                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2403                                 u8 lag_tx_affinity);
2404
2405 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2406                               struct ib_udata *udata)
2407 {
2408         struct mlx5_ib_cq *send_cq, *recv_cq;
2409         struct mlx5_ib_qp_base *base;
2410         unsigned long flags;
2411         int err;
2412
2413         if (qp->ibqp.rwq_ind_tbl) {
2414                 destroy_rss_raw_qp_tir(dev, qp);
2415                 return;
2416         }
2417
2418         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2419                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
2420                &qp->raw_packet_qp.rq.base :
2421                &qp->trans_qp.base;
2422
2423         if (qp->state != IB_QPS_RESET) {
2424                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2425                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
2426                         err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
2427                                                   NULL, &base->mqp);
2428                 } else {
2429                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2430                                 .operation = MLX5_CMD_OP_2RST_QP
2431                         };
2432
2433                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2434                 }
2435                 if (err)
2436                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2437                                      base->mqp.qpn);
2438         }
2439
2440         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2441                 &send_cq, &recv_cq);
2442
2443         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2444         mlx5_ib_lock_cqs(send_cq, recv_cq);
2445         /* del from lists under both locks above to protect reset flow paths */
2446         list_del(&qp->qps_list);
2447         if (send_cq)
2448                 list_del(&qp->cq_send_list);
2449
2450         if (recv_cq)
2451                 list_del(&qp->cq_recv_list);
2452
2453         if (!udata) {
2454                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2455                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2456                 if (send_cq != recv_cq)
2457                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2458                                            NULL);
2459         }
2460         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2461         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2462
2463         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2464             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2465                 destroy_raw_packet_qp(dev, qp);
2466         } else {
2467                 err = mlx5_core_destroy_qp(dev, &base->mqp);
2468                 if (err)
2469                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2470                                      base->mqp.qpn);
2471         }
2472
2473         if (udata)
2474                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
2475         else
2476                 destroy_qp_kernel(dev, qp);
2477 }
2478
2479 static int create_dct(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2480                       struct ib_qp_init_attr *attr,
2481                       struct mlx5_ib_create_qp *ucmd, u32 uidx)
2482 {
2483         void *dctc;
2484
2485         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2486         if (!qp->dct.in)
2487                 return -ENOMEM;
2488
2489         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2490         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2491         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2492         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2493         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2494         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2495         MLX5_SET(dctc, dctc, user_index, uidx);
2496
2497         if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
2498                 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2499
2500                 if (rcqe_sz == 128)
2501                         MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2502         }
2503
2504         qp->state = IB_QPS_RESET;
2505
2506         return 0;
2507 }
2508
2509 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2510                          enum ib_qp_type *type)
2511 {
2512         if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2513                 goto out;
2514
2515         switch (attr->qp_type) {
2516         case IB_QPT_XRC_TGT:
2517         case IB_QPT_XRC_INI:
2518                 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2519                         goto out;
2520                 fallthrough;
2521         case IB_QPT_RAW_PACKET:
2522         case IB_QPT_RC:
2523         case IB_QPT_UC:
2524         case IB_QPT_UD:
2525         case IB_QPT_SMI:
2526         case MLX5_IB_QPT_HW_GSI:
2527         case MLX5_IB_QPT_REG_UMR:
2528         case IB_QPT_DRIVER:
2529         case IB_QPT_GSI:
2530                 break;
2531         default:
2532                 goto out;
2533         }
2534
2535         *type = attr->qp_type;
2536         return 0;
2537
2538 out:
2539         mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2540         return -EOPNOTSUPP;
2541 }
2542
2543 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2544                             struct ib_qp_init_attr *attr,
2545                             struct ib_udata *udata)
2546 {
2547         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2548                 udata, struct mlx5_ib_ucontext, ibucontext);
2549
2550         if (!udata) {
2551                 /* Kernel create_qp callers */
2552                 if (attr->rwq_ind_tbl)
2553                         return -EOPNOTSUPP;
2554
2555                 switch (attr->qp_type) {
2556                 case IB_QPT_RAW_PACKET:
2557                 case IB_QPT_DRIVER:
2558                         return -EOPNOTSUPP;
2559                 default:
2560                         return 0;
2561                 }
2562         }
2563
2564         /* Userspace create_qp callers */
2565         if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2566                 mlx5_ib_dbg(dev,
2567                         "Raw Packet QP is only supported for CQE version > 0\n");
2568                 return -EINVAL;
2569         }
2570
2571         if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2572                 mlx5_ib_dbg(dev,
2573                             "Wrong QP type %d for the RWQ indirect table\n",
2574                             attr->qp_type);
2575                 return -EINVAL;
2576         }
2577
2578         switch (attr->qp_type) {
2579         case IB_QPT_SMI:
2580         case MLX5_IB_QPT_HW_GSI:
2581         case MLX5_IB_QPT_REG_UMR:
2582         case IB_QPT_GSI:
2583                 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2584                             attr->qp_type);
2585                 return -EINVAL;
2586         default:
2587                 break;
2588         }
2589
2590         /*
2591          * We don't need to see this warning, it means that kernel code
2592          * missing ib_pd. Placed here to catch developer's mistakes.
2593          */
2594         WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2595                   "There is a missing PD pointer assignment\n");
2596         return 0;
2597 }
2598
2599 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2600                                 bool cond, struct mlx5_ib_qp *qp)
2601 {
2602         if (!(*flags & flag))
2603                 return;
2604
2605         if (cond) {
2606                 qp->flags_en |= flag;
2607                 *flags &= ~flag;
2608                 return;
2609         }
2610
2611         if (flag == MLX5_QP_FLAG_SCATTER_CQE) {
2612                 /*
2613                  * We don't return error if this flag was provided,
2614                  * and mlx5 doesn't have right capability.
2615                  */
2616                 *flags &= ~MLX5_QP_FLAG_SCATTER_CQE;
2617                 return;
2618         }
2619         mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2620 }
2621
2622 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2623                                 void *ucmd, struct ib_qp_init_attr *attr)
2624 {
2625         struct mlx5_core_dev *mdev = dev->mdev;
2626         bool cond;
2627         int flags;
2628
2629         if (attr->rwq_ind_tbl)
2630                 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2631         else
2632                 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
2633
2634         switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2635         case MLX5_QP_FLAG_TYPE_DCI:
2636                 qp->type = MLX5_IB_QPT_DCI;
2637                 break;
2638         case MLX5_QP_FLAG_TYPE_DCT:
2639                 qp->type = MLX5_IB_QPT_DCT;
2640                 break;
2641         default:
2642                 if (qp->type != IB_QPT_DRIVER)
2643                         break;
2644                 /*
2645                  * It is IB_QPT_DRIVER and or no subtype or
2646                  * wrong subtype were provided.
2647                  */
2648                 return -EINVAL;
2649         }
2650
2651         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2652         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2653
2654         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2655         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2656                             MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2657
2658         if (qp->type == IB_QPT_RAW_PACKET) {
2659                 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2660                        MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2661                        MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2662                 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2663                                     cond, qp);
2664                 process_vendor_flag(dev, &flags,
2665                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2666                                     qp);
2667                 process_vendor_flag(dev, &flags,
2668                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2669                                     qp);
2670         }
2671
2672         if (qp->type == IB_QPT_RC)
2673                 process_vendor_flag(dev, &flags,
2674                                     MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2675                                     MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2676
2677         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2678         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2679
2680         if (flags)
2681                 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2682
2683         return (flags) ? -EINVAL : 0;
2684 }
2685
2686 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2687                                 bool cond, struct mlx5_ib_qp *qp)
2688 {
2689         if (!(*flags & flag))
2690                 return;
2691
2692         if (cond) {
2693                 qp->flags |= flag;
2694                 *flags &= ~flag;
2695                 return;
2696         }
2697
2698         if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2699                 /*
2700                  * Special case, if condition didn't meet, it won't be error,
2701                  * just different in-kernel flow.
2702                  */
2703                 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2704                 return;
2705         }
2706         mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2707 }
2708
2709 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2710                                 struct ib_qp_init_attr *attr)
2711 {
2712         enum ib_qp_type qp_type = qp->type;
2713         struct mlx5_core_dev *mdev = dev->mdev;
2714         int create_flags = attr->create_flags;
2715         bool cond;
2716
2717         if (qp_type == MLX5_IB_QPT_DCT)
2718                 return (create_flags) ? -EINVAL : 0;
2719
2720         if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2721                 return (create_flags) ? -EINVAL : 0;
2722
2723         process_create_flag(dev, &create_flags,
2724                             IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2725                             MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2726         process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2727                             MLX5_CAP_GEN(mdev, cd), qp);
2728         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2729                             MLX5_CAP_GEN(mdev, cd), qp);
2730         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2731                             MLX5_CAP_GEN(mdev, cd), qp);
2732
2733         if (qp_type == IB_QPT_UD) {
2734                 process_create_flag(dev, &create_flags,
2735                                     IB_QP_CREATE_IPOIB_UD_LSO,
2736                                     MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2737                                     qp);
2738                 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2739                 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2740                                     cond, qp);
2741         }
2742
2743         if (qp_type == IB_QPT_RAW_PACKET) {
2744                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2745                        MLX5_CAP_ETH(mdev, scatter_fcs);
2746                 process_create_flag(dev, &create_flags,
2747                                     IB_QP_CREATE_SCATTER_FCS, cond, qp);
2748
2749                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2750                        MLX5_CAP_ETH(mdev, vlan_cap);
2751                 process_create_flag(dev, &create_flags,
2752                                     IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2753         }
2754
2755         process_create_flag(dev, &create_flags,
2756                             IB_QP_CREATE_PCI_WRITE_END_PADDING,
2757                             MLX5_CAP_GEN(mdev, end_pad), qp);
2758
2759         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2760                             qp_type != MLX5_IB_QPT_REG_UMR, qp);
2761         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2762                             true, qp);
2763
2764         if (create_flags)
2765                 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2766                             create_flags);
2767
2768         return (create_flags) ? -EINVAL : 0;
2769 }
2770
2771 static size_t process_udata_size(struct ib_qp_init_attr *attr,
2772                                  struct ib_udata *udata)
2773 {
2774         size_t ucmd = sizeof(struct mlx5_ib_create_qp);
2775         size_t inlen = udata->inlen;
2776
2777         if (attr->qp_type == IB_QPT_DRIVER)
2778                 return (inlen < ucmd) ? 0 : ucmd;
2779
2780         if (!attr->rwq_ind_tbl)
2781                 return ucmd;
2782
2783         if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
2784                 return 0;
2785
2786         ucmd = sizeof(struct mlx5_ib_create_qp_rss);
2787         if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
2788                 return 0;
2789
2790         return min(ucmd, inlen);
2791 }
2792
2793 static int create_raw_qp(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2794                          struct ib_qp_init_attr *attr, void *ucmd,
2795                          struct ib_udata *udata, u32 uidx)
2796 {
2797         struct mlx5_ib_dev *dev = to_mdev(pd->device);
2798
2799         if (attr->rwq_ind_tbl)
2800                 return create_rss_raw_qp_tir(pd, qp, attr, ucmd, udata);
2801
2802         return create_user_qp(dev, pd, attr, ucmd, udata, qp, uidx);
2803 }
2804
2805 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2806                          struct ib_qp_init_attr *attr)
2807 {
2808         int ret = 0;
2809
2810         switch (qp->type) {
2811         case MLX5_IB_QPT_DCT:
2812                 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2813                 break;
2814         case MLX5_IB_QPT_DCI:
2815                 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2816                               -EINVAL :
2817                               0;
2818                 break;
2819         case IB_QPT_RAW_PACKET:
2820                 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2821                 break;
2822         default:
2823                 break;
2824         }
2825
2826         if (ret)
2827                 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2828
2829         return ret;
2830 }
2831
2832 static int get_qp_uidx(struct mlx5_ib_qp *qp, struct ib_udata *udata,
2833                        struct mlx5_ib_create_qp *ucmd,
2834                        struct ib_qp_init_attr *attr, u32 *uidx)
2835 {
2836         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2837                 udata, struct mlx5_ib_ucontext, ibucontext);
2838
2839         if (attr->rwq_ind_tbl)
2840                 return 0;
2841
2842         return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), uidx);
2843 }
2844
2845 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2846                                 struct ib_qp_init_attr *init_attr,
2847                                 struct ib_udata *udata)
2848 {
2849         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2850         struct mlx5_ib_dev *dev;
2851         struct mlx5_ib_qp *qp;
2852         enum ib_qp_type type;
2853         void *ucmd = NULL;
2854         u16 xrcdn = 0;
2855         int err;
2856
2857         dev = pd ? to_mdev(pd->device) :
2858                    to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2859
2860         err = check_qp_type(dev, init_attr, &type);
2861         if (err) {
2862                 mlx5_ib_dbg(dev, "Unsupported QP type %d\n",
2863                             init_attr->qp_type);
2864                 return ERR_PTR(err);
2865         }
2866
2867         err = check_valid_flow(dev, pd, init_attr, udata);
2868         if (err)
2869                 return ERR_PTR(err);
2870
2871         if (init_attr->qp_type == IB_QPT_GSI)
2872                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2873
2874         if (udata) {
2875                 size_t inlen =
2876                         process_udata_size(init_attr, udata);
2877
2878                 if (!inlen)
2879                         return ERR_PTR(-EINVAL);
2880
2881                 ucmd = kzalloc(inlen, GFP_KERNEL);
2882                 if (!ucmd)
2883                         return ERR_PTR(-ENOMEM);
2884
2885                 err = ib_copy_from_udata(ucmd, udata, inlen);
2886                 if (err)
2887                         goto free_ucmd;
2888         }
2889
2890         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2891         if (!qp) {
2892                 err = -ENOMEM;
2893                 goto free_ucmd;
2894         }
2895
2896         qp->type = type;
2897         if (udata) {
2898                 err = process_vendor_flags(dev, qp, ucmd, init_attr);
2899                 if (err)
2900                         goto free_qp;
2901
2902                 err = get_qp_uidx(qp, udata, ucmd, init_attr, &uidx);
2903                 if (err)
2904                         goto free_qp;
2905         }
2906         err = process_create_flags(dev, qp, init_attr);
2907         if (err)
2908                 goto free_qp;
2909
2910         err = check_qp_attr(dev, qp, init_attr);
2911         if (err)
2912                 goto free_qp;
2913
2914         switch (qp->type) {
2915         case IB_QPT_RAW_PACKET:
2916                 err = create_raw_qp(pd, qp, init_attr, ucmd, udata, uidx);
2917                 break;
2918         case MLX5_IB_QPT_DCT:
2919                 err = create_dct(pd, qp, init_attr, ucmd, uidx);
2920                 break;
2921         case IB_QPT_XRC_TGT:
2922                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2923                 err = create_xrc_tgt_qp(dev, init_attr, qp, udata, uidx);
2924                 break;
2925         default:
2926                 if (udata)
2927                         err = create_user_qp(dev, pd, init_attr, ucmd, udata,
2928                                              qp, uidx);
2929                 else
2930                         err = create_kernel_qp(dev, pd, init_attr, qp, uidx);
2931         }
2932         if (err) {
2933                 mlx5_ib_dbg(dev, "create_qp failed %d\n", err);
2934                 goto free_qp;
2935         }
2936
2937         kfree(ucmd);
2938
2939         if (is_qp0(init_attr->qp_type))
2940                 qp->ibqp.qp_num = 0;
2941         else if (is_qp1(init_attr->qp_type))
2942                 qp->ibqp.qp_num = 1;
2943         else
2944                 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2945
2946         qp->trans_qp.xrcdn = xrcdn;
2947
2948         return &qp->ibqp;
2949
2950 free_qp:
2951         kfree(qp);
2952 free_ucmd:
2953         kfree(ucmd);
2954         return ERR_PTR(err);
2955 }
2956
2957 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2958 {
2959         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2960
2961         if (mqp->state == IB_QPS_RTR) {
2962                 int err;
2963
2964                 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2965                 if (err) {
2966                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2967                         return err;
2968                 }
2969         }
2970
2971         kfree(mqp->dct.in);
2972         kfree(mqp);
2973         return 0;
2974 }
2975
2976 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
2977 {
2978         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2979         struct mlx5_ib_qp *mqp = to_mqp(qp);
2980
2981         if (unlikely(qp->qp_type == IB_QPT_GSI))
2982                 return mlx5_ib_gsi_destroy_qp(qp);
2983
2984         if (mqp->type == MLX5_IB_QPT_DCT)
2985                 return mlx5_ib_destroy_dct(mqp);
2986
2987         destroy_qp_common(dev, mqp, udata);
2988
2989         kfree(mqp);
2990
2991         return 0;
2992 }
2993
2994 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2995                                 const struct ib_qp_attr *attr,
2996                                 int attr_mask, __be32 *hw_access_flags_be)
2997 {
2998         u8 dest_rd_atomic;
2999         u32 access_flags, hw_access_flags = 0;
3000
3001         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
3002
3003         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3004                 dest_rd_atomic = attr->max_dest_rd_atomic;
3005         else
3006                 dest_rd_atomic = qp->trans_qp.resp_depth;
3007
3008         if (attr_mask & IB_QP_ACCESS_FLAGS)
3009                 access_flags = attr->qp_access_flags;
3010         else
3011                 access_flags = qp->trans_qp.atomic_rd_en;
3012
3013         if (!dest_rd_atomic)
3014                 access_flags &= IB_ACCESS_REMOTE_WRITE;
3015
3016         if (access_flags & IB_ACCESS_REMOTE_READ)
3017                 hw_access_flags |= MLX5_QP_BIT_RRE;
3018         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3019                 int atomic_mode;
3020
3021                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
3022                 if (atomic_mode < 0)
3023                         return -EOPNOTSUPP;
3024
3025                 hw_access_flags |= MLX5_QP_BIT_RAE;
3026                 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
3027         }
3028
3029         if (access_flags & IB_ACCESS_REMOTE_WRITE)
3030                 hw_access_flags |= MLX5_QP_BIT_RWE;
3031
3032         *hw_access_flags_be = cpu_to_be32(hw_access_flags);
3033
3034         return 0;
3035 }
3036
3037 enum {
3038         MLX5_PATH_FLAG_FL       = 1 << 0,
3039         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
3040         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
3041 };
3042
3043 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
3044 {
3045         if (rate == IB_RATE_PORT_CURRENT)
3046                 return 0;
3047
3048         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
3049                 return -EINVAL;
3050
3051         while (rate != IB_RATE_PORT_CURRENT &&
3052                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
3053                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
3054                 --rate;
3055
3056         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
3057 }
3058
3059 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
3060                                       struct mlx5_ib_sq *sq, u8 sl,
3061                                       struct ib_pd *pd)
3062 {
3063         void *in;
3064         void *tisc;
3065         int inlen;
3066         int err;
3067
3068         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3069         in = kvzalloc(inlen, GFP_KERNEL);
3070         if (!in)
3071                 return -ENOMEM;
3072
3073         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
3074         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3075
3076         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3077         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
3078
3079         err = mlx5_core_modify_tis(dev, sq->tisn, in);
3080
3081         kvfree(in);
3082
3083         return err;
3084 }
3085
3086 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
3087                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
3088                                          struct ib_pd *pd)
3089 {
3090         void *in;
3091         void *tisc;
3092         int inlen;
3093         int err;
3094
3095         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3096         in = kvzalloc(inlen, GFP_KERNEL);
3097         if (!in)
3098                 return -ENOMEM;
3099
3100         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
3101         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3102
3103         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3104         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
3105
3106         err = mlx5_core_modify_tis(dev, sq->tisn, in);
3107
3108         kvfree(in);
3109
3110         return err;
3111 }
3112
3113 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3114                          const struct rdma_ah_attr *ah,
3115                          struct mlx5_qp_path *path, u8 port, int attr_mask,
3116                          u32 path_flags, const struct ib_qp_attr *attr,
3117                          bool alt)
3118 {
3119         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
3120         int err;
3121         enum ib_gid_type gid_type;
3122         u8 ah_flags = rdma_ah_get_ah_flags(ah);
3123         u8 sl = rdma_ah_get_sl(ah);
3124
3125         if (attr_mask & IB_QP_PKEY_INDEX)
3126                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
3127                                                      attr->pkey_index);
3128
3129         if (ah_flags & IB_AH_GRH) {
3130                 if (grh->sgid_index >=
3131                     dev->mdev->port_caps[port - 1].gid_table_len) {
3132                         pr_err("sgid_index (%u) too large. max is %d\n",
3133                                grh->sgid_index,
3134                                dev->mdev->port_caps[port - 1].gid_table_len);
3135                         return -EINVAL;
3136                 }
3137         }
3138
3139         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
3140                 if (!(ah_flags & IB_AH_GRH))
3141                         return -EINVAL;
3142
3143                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
3144                 if (qp->ibqp.qp_type == IB_QPT_RC ||
3145                     qp->ibqp.qp_type == IB_QPT_UC ||
3146                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3147                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
3148                         path->udp_sport =
3149                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
3150                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
3151                 gid_type = ah->grh.sgid_attr->gid_type;
3152                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3153                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
3154         } else {
3155                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
3156                 path->fl_free_ar |=
3157                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
3158                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
3159                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
3160                 if (ah_flags & IB_AH_GRH)
3161                         path->grh_mlid  |= 1 << 7;
3162                 path->dci_cfi_prio_sl = sl & 0xf;
3163         }
3164
3165         if (ah_flags & IB_AH_GRH) {
3166                 path->mgid_index = grh->sgid_index;
3167                 path->hop_limit  = grh->hop_limit;
3168                 path->tclass_flowlabel =
3169                         cpu_to_be32((grh->traffic_class << 20) |
3170                                     (grh->flow_label));
3171                 memcpy(path->rgid, grh->dgid.raw, 16);
3172         }
3173
3174         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
3175         if (err < 0)
3176                 return err;
3177         path->static_rate = err;
3178         path->port = port;
3179
3180         if (attr_mask & IB_QP_TIMEOUT)
3181                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
3182
3183         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3184                 return modify_raw_packet_eth_prio(dev->mdev,
3185                                                   &qp->raw_packet_qp.sq,
3186                                                   sl & 0xf, qp->ibqp.pd);
3187
3188         return 0;
3189 }
3190
3191 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3192         [MLX5_QP_STATE_INIT] = {
3193                 [MLX5_QP_STATE_INIT] = {
3194                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3195                                           MLX5_QP_OPTPAR_RAE            |
3196                                           MLX5_QP_OPTPAR_RWE            |
3197                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3198                                           MLX5_QP_OPTPAR_PRI_PORT,
3199                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3200                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3201                                           MLX5_QP_OPTPAR_PRI_PORT,
3202                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3203                                           MLX5_QP_OPTPAR_Q_KEY          |
3204                                           MLX5_QP_OPTPAR_PRI_PORT,
3205                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3206                                           MLX5_QP_OPTPAR_RAE            |
3207                                           MLX5_QP_OPTPAR_RWE            |
3208                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3209                                           MLX5_QP_OPTPAR_PRI_PORT,
3210                 },
3211                 [MLX5_QP_STATE_RTR] = {
3212                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3213                                           MLX5_QP_OPTPAR_RRE            |
3214                                           MLX5_QP_OPTPAR_RAE            |
3215                                           MLX5_QP_OPTPAR_RWE            |
3216                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3217                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3218                                           MLX5_QP_OPTPAR_RWE            |
3219                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3220                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3221                                           MLX5_QP_OPTPAR_Q_KEY,
3222                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
3223                                            MLX5_QP_OPTPAR_Q_KEY,
3224                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3225                                           MLX5_QP_OPTPAR_RRE            |
3226                                           MLX5_QP_OPTPAR_RAE            |
3227                                           MLX5_QP_OPTPAR_RWE            |
3228                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3229                 },
3230         },
3231         [MLX5_QP_STATE_RTR] = {
3232                 [MLX5_QP_STATE_RTS] = {
3233                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3234                                           MLX5_QP_OPTPAR_RRE            |
3235                                           MLX5_QP_OPTPAR_RAE            |
3236                                           MLX5_QP_OPTPAR_RWE            |
3237                                           MLX5_QP_OPTPAR_PM_STATE       |
3238                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3239                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3240                                           MLX5_QP_OPTPAR_RWE            |
3241                                           MLX5_QP_OPTPAR_PM_STATE,
3242                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3243                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3244                                           MLX5_QP_OPTPAR_RRE            |
3245                                           MLX5_QP_OPTPAR_RAE            |
3246                                           MLX5_QP_OPTPAR_RWE            |
3247                                           MLX5_QP_OPTPAR_PM_STATE       |
3248                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3249                 },
3250         },
3251         [MLX5_QP_STATE_RTS] = {
3252                 [MLX5_QP_STATE_RTS] = {
3253                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3254                                           MLX5_QP_OPTPAR_RAE            |
3255                                           MLX5_QP_OPTPAR_RWE            |
3256                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3257                                           MLX5_QP_OPTPAR_PM_STATE       |
3258                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3259                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3260                                           MLX5_QP_OPTPAR_PM_STATE       |
3261                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3262                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3263                                           MLX5_QP_OPTPAR_SRQN           |
3264                                           MLX5_QP_OPTPAR_CQN_RCV,
3265                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3266                                           MLX5_QP_OPTPAR_RAE            |
3267                                           MLX5_QP_OPTPAR_RWE            |
3268                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3269                                           MLX5_QP_OPTPAR_PM_STATE       |
3270                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3271                 },
3272         },
3273         [MLX5_QP_STATE_SQER] = {
3274                 [MLX5_QP_STATE_RTS] = {
3275                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3276                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3277                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3278                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3279                                            MLX5_QP_OPTPAR_RWE           |
3280                                            MLX5_QP_OPTPAR_RAE           |
3281                                            MLX5_QP_OPTPAR_RRE,
3282                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
3283                                            MLX5_QP_OPTPAR_RWE           |
3284                                            MLX5_QP_OPTPAR_RAE           |
3285                                            MLX5_QP_OPTPAR_RRE,
3286                 },
3287         },
3288 };
3289
3290 static int ib_nr_to_mlx5_nr(int ib_mask)
3291 {
3292         switch (ib_mask) {
3293         case IB_QP_STATE:
3294                 return 0;
3295         case IB_QP_CUR_STATE:
3296                 return 0;
3297         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3298                 return 0;
3299         case IB_QP_ACCESS_FLAGS:
3300                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3301                         MLX5_QP_OPTPAR_RAE;
3302         case IB_QP_PKEY_INDEX:
3303                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3304         case IB_QP_PORT:
3305                 return MLX5_QP_OPTPAR_PRI_PORT;
3306         case IB_QP_QKEY:
3307                 return MLX5_QP_OPTPAR_Q_KEY;
3308         case IB_QP_AV:
3309                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3310                         MLX5_QP_OPTPAR_PRI_PORT;
3311         case IB_QP_PATH_MTU:
3312                 return 0;
3313         case IB_QP_TIMEOUT:
3314                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3315         case IB_QP_RETRY_CNT:
3316                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3317         case IB_QP_RNR_RETRY:
3318                 return MLX5_QP_OPTPAR_RNR_RETRY;
3319         case IB_QP_RQ_PSN:
3320                 return 0;
3321         case IB_QP_MAX_QP_RD_ATOMIC:
3322                 return MLX5_QP_OPTPAR_SRA_MAX;
3323         case IB_QP_ALT_PATH:
3324                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3325         case IB_QP_MIN_RNR_TIMER:
3326                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3327         case IB_QP_SQ_PSN:
3328                 return 0;
3329         case IB_QP_MAX_DEST_RD_ATOMIC:
3330                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3331                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3332         case IB_QP_PATH_MIG_STATE:
3333                 return MLX5_QP_OPTPAR_PM_STATE;
3334         case IB_QP_CAP:
3335                 return 0;
3336         case IB_QP_DEST_QPN:
3337                 return 0;
3338         }
3339         return 0;
3340 }
3341
3342 static int ib_mask_to_mlx5_opt(int ib_mask)
3343 {
3344         int result = 0;
3345         int i;
3346
3347         for (i = 0; i < 8 * sizeof(int); i++) {
3348                 if ((1 << i) & ib_mask)
3349                         result |= ib_nr_to_mlx5_nr(1 << i);
3350         }
3351
3352         return result;
3353 }
3354
3355 static int modify_raw_packet_qp_rq(
3356         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3357         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3358 {
3359         void *in;
3360         void *rqc;
3361         int inlen;
3362         int err;
3363
3364         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3365         in = kvzalloc(inlen, GFP_KERNEL);
3366         if (!in)
3367                 return -ENOMEM;
3368
3369         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3370         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3371
3372         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3373         MLX5_SET(rqc, rqc, state, new_state);
3374
3375         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3376                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3377                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3378                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3379                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3380                 } else
3381                         dev_info_once(
3382                                 &dev->ib_dev.dev,
3383                                 "RAW PACKET QP counters are not supported on current FW\n");
3384         }
3385
3386         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3387         if (err)
3388                 goto out;
3389
3390         rq->state = new_state;
3391
3392 out:
3393         kvfree(in);
3394         return err;
3395 }
3396
3397 static int modify_raw_packet_qp_sq(
3398         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3399         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3400 {
3401         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3402         struct mlx5_rate_limit old_rl = ibqp->rl;
3403         struct mlx5_rate_limit new_rl = old_rl;
3404         bool new_rate_added = false;
3405         u16 rl_index = 0;
3406         void *in;
3407         void *sqc;
3408         int inlen;
3409         int err;
3410
3411         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3412         in = kvzalloc(inlen, GFP_KERNEL);
3413         if (!in)
3414                 return -ENOMEM;
3415
3416         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3417         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3418
3419         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3420         MLX5_SET(sqc, sqc, state, new_state);
3421
3422         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3423                 if (new_state != MLX5_SQC_STATE_RDY)
3424                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3425                                 __func__);
3426                 else
3427                         new_rl = raw_qp_param->rl;
3428         }
3429
3430         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3431                 if (new_rl.rate) {
3432                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3433                         if (err) {
3434                                 pr_err("Failed configuring rate limit(err %d): \
3435                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3436                                        err, new_rl.rate, new_rl.max_burst_sz,
3437                                        new_rl.typical_pkt_sz);
3438
3439                                 goto out;
3440                         }
3441                         new_rate_added = true;
3442                 }
3443
3444                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3445                 /* index 0 means no limit */
3446                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3447         }
3448
3449         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
3450         if (err) {
3451                 /* Remove new rate from table if failed */
3452                 if (new_rate_added)
3453                         mlx5_rl_remove_rate(dev, &new_rl);
3454                 goto out;
3455         }
3456
3457         /* Only remove the old rate after new rate was set */
3458         if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3459             (new_state != MLX5_SQC_STATE_RDY)) {
3460                 mlx5_rl_remove_rate(dev, &old_rl);
3461                 if (new_state != MLX5_SQC_STATE_RDY)
3462                         memset(&new_rl, 0, sizeof(new_rl));
3463         }
3464
3465         ibqp->rl = new_rl;
3466         sq->state = new_state;
3467
3468 out:
3469         kvfree(in);
3470         return err;
3471 }
3472
3473 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3474                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3475                                 u8 tx_affinity)
3476 {
3477         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3478         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3479         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3480         int modify_rq = !!qp->rq.wqe_cnt;
3481         int modify_sq = !!qp->sq.wqe_cnt;
3482         int rq_state;
3483         int sq_state;
3484         int err;
3485
3486         switch (raw_qp_param->operation) {
3487         case MLX5_CMD_OP_RST2INIT_QP:
3488                 rq_state = MLX5_RQC_STATE_RDY;
3489                 sq_state = MLX5_SQC_STATE_RDY;
3490                 break;
3491         case MLX5_CMD_OP_2ERR_QP:
3492                 rq_state = MLX5_RQC_STATE_ERR;
3493                 sq_state = MLX5_SQC_STATE_ERR;
3494                 break;
3495         case MLX5_CMD_OP_2RST_QP:
3496                 rq_state = MLX5_RQC_STATE_RST;
3497                 sq_state = MLX5_SQC_STATE_RST;
3498                 break;
3499         case MLX5_CMD_OP_RTR2RTS_QP:
3500         case MLX5_CMD_OP_RTS2RTS_QP:
3501                 if (raw_qp_param->set_mask ==
3502                     MLX5_RAW_QP_RATE_LIMIT) {
3503                         modify_rq = 0;
3504                         sq_state = sq->state;
3505                 } else {
3506                         return raw_qp_param->set_mask ? -EINVAL : 0;
3507                 }
3508                 break;
3509         case MLX5_CMD_OP_INIT2INIT_QP:
3510         case MLX5_CMD_OP_INIT2RTR_QP:
3511                 if (raw_qp_param->set_mask)
3512                         return -EINVAL;
3513                 else
3514                         return 0;
3515         default:
3516                 WARN_ON(1);
3517                 return -EINVAL;
3518         }
3519
3520         if (modify_rq) {
3521                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3522                                                qp->ibqp.pd);
3523                 if (err)
3524                         return err;
3525         }
3526
3527         if (modify_sq) {
3528                 struct mlx5_flow_handle *flow_rule;
3529
3530                 if (tx_affinity) {
3531                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3532                                                             tx_affinity,
3533                                                             qp->ibqp.pd);
3534                         if (err)
3535                                 return err;
3536                 }
3537
3538                 flow_rule = create_flow_rule_vport_sq(dev, sq,
3539                                                       raw_qp_param->port);
3540                 if (IS_ERR(flow_rule))
3541                         return PTR_ERR(flow_rule);
3542
3543                 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3544                                               raw_qp_param, qp->ibqp.pd);
3545                 if (err) {
3546                         if (flow_rule)
3547                                 mlx5_del_flow_rules(flow_rule);
3548                         return err;
3549                 }
3550
3551                 if (flow_rule) {
3552                         destroy_flow_rule_vport_sq(sq);
3553                         sq->flow_rule = flow_rule;
3554                 }
3555
3556                 return err;
3557         }
3558
3559         return 0;
3560 }
3561
3562 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3563                                     struct mlx5_ib_pd *pd,
3564                                     struct mlx5_ib_qp_base *qp_base,
3565                                     u8 port_num, struct ib_udata *udata)
3566 {
3567         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3568                 udata, struct mlx5_ib_ucontext, ibucontext);
3569         unsigned int tx_port_affinity;
3570
3571         if (ucontext) {
3572                 tx_port_affinity = (unsigned int)atomic_add_return(
3573                                            1, &ucontext->tx_port_affinity) %
3574                                            MLX5_MAX_PORTS +
3575                                    1;
3576                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3577                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3578         } else {
3579                 tx_port_affinity =
3580                         (unsigned int)atomic_add_return(
3581                                 1, &dev->port[port_num].roce.tx_port_affinity) %
3582                                 MLX5_MAX_PORTS +
3583                         1;
3584                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3585                                 tx_port_affinity, qp_base->mqp.qpn);
3586         }
3587
3588         return tx_port_affinity;
3589 }
3590
3591 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3592                                     struct rdma_counter *counter)
3593 {
3594         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3595         struct mlx5_ib_qp *mqp = to_mqp(qp);
3596         struct mlx5_qp_context context = {};
3597         struct mlx5_ib_qp_base *base;
3598         u32 set_id;
3599
3600         if (counter)
3601                 set_id = counter->id;
3602         else
3603                 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3604
3605         base = &mqp->trans_qp.base;
3606         context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff);
3607         context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24);
3608         return mlx5_core_qp_modify(dev, MLX5_CMD_OP_RTS2RTS_QP,
3609                                    MLX5_QP_OPTPAR_COUNTER_SET_ID, &context,
3610                                    &base->mqp);
3611 }
3612
3613 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3614                                const struct ib_qp_attr *attr, int attr_mask,
3615                                enum ib_qp_state cur_state,
3616                                enum ib_qp_state new_state,
3617                                const struct mlx5_ib_modify_qp *ucmd,
3618                                struct ib_udata *udata)
3619 {
3620         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3621                 [MLX5_QP_STATE_RST] = {
3622                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3623                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3624                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3625                 },
3626                 [MLX5_QP_STATE_INIT]  = {
3627                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3628                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3629                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3630                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3631                 },
3632                 [MLX5_QP_STATE_RTR]   = {
3633                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3634                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3635                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3636                 },
3637                 [MLX5_QP_STATE_RTS]   = {
3638                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3639                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3640                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3641                 },
3642                 [MLX5_QP_STATE_SQD] = {
3643                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3644                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3645                 },
3646                 [MLX5_QP_STATE_SQER] = {
3647                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3648                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3649                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3650                 },
3651                 [MLX5_QP_STATE_ERR] = {
3652                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3653                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3654                 }
3655         };
3656
3657         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3658         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3659         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3660         struct mlx5_ib_cq *send_cq, *recv_cq;
3661         struct mlx5_qp_context *context;
3662         struct mlx5_ib_pd *pd;
3663         enum mlx5_qp_state mlx5_cur, mlx5_new;
3664         enum mlx5_qp_optpar optpar;
3665         u32 set_id = 0;
3666         int mlx5_st;
3667         int err;
3668         u16 op;
3669         u8 tx_affinity = 0;
3670
3671         mlx5_st = to_mlx5_st(qp->type);
3672         if (mlx5_st < 0)
3673                 return -EINVAL;
3674
3675         context = kzalloc(sizeof(*context), GFP_KERNEL);
3676         if (!context)
3677                 return -ENOMEM;
3678
3679         pd = get_pd(qp);
3680         context->flags = cpu_to_be32(mlx5_st << 16);
3681
3682         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3683                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3684         } else {
3685                 switch (attr->path_mig_state) {
3686                 case IB_MIG_MIGRATED:
3687                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3688                         break;
3689                 case IB_MIG_REARM:
3690                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3691                         break;
3692                 case IB_MIG_ARMED:
3693                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3694                         break;
3695                 }
3696         }
3697
3698         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3699                 if ((ibqp->qp_type == IB_QPT_RC) ||
3700                     (ibqp->qp_type == IB_QPT_UD &&
3701                      !(qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)) ||
3702                     (ibqp->qp_type == IB_QPT_UC) ||
3703                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3704                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3705                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3706                         if (dev->lag_active) {
3707                                 u8 p = mlx5_core_native_port_num(dev->mdev) - 1;
3708                                 tx_affinity = get_tx_affinity(dev, pd, base, p,
3709                                                               udata);
3710                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3711                         }
3712                 }
3713         }
3714
3715         if (is_sqp(ibqp->qp_type)) {
3716                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3717         } else if ((ibqp->qp_type == IB_QPT_UD &&
3718                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
3719                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3720                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3721         } else if (attr_mask & IB_QP_PATH_MTU) {
3722                 if (attr->path_mtu < IB_MTU_256 ||
3723                     attr->path_mtu > IB_MTU_4096) {
3724                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3725                         err = -EINVAL;
3726                         goto out;
3727                 }
3728                 context->mtu_msgmax = (attr->path_mtu << 5) |
3729                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3730         }
3731
3732         if (attr_mask & IB_QP_DEST_QPN)
3733                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3734
3735         if (attr_mask & IB_QP_PKEY_INDEX)
3736                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3737
3738         /* todo implement counter_index functionality */
3739
3740         if (is_sqp(ibqp->qp_type))
3741                 context->pri_path.port = qp->port;
3742
3743         if (attr_mask & IB_QP_PORT)
3744                 context->pri_path.port = attr->port_num;
3745
3746         if (attr_mask & IB_QP_AV) {
3747                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3748                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3749                                     attr_mask, 0, attr, false);
3750                 if (err)
3751                         goto out;
3752         }
3753
3754         if (attr_mask & IB_QP_TIMEOUT)
3755                 context->pri_path.ackto_lt |= attr->timeout << 3;
3756
3757         if (attr_mask & IB_QP_ALT_PATH) {
3758                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3759                                     &context->alt_path,
3760                                     attr->alt_port_num,
3761                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3762                                     0, attr, true);
3763                 if (err)
3764                         goto out;
3765         }
3766
3767         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3768                 &send_cq, &recv_cq);
3769
3770         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3771         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3772         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3773         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3774
3775         if (attr_mask & IB_QP_RNR_RETRY)
3776                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3777
3778         if (attr_mask & IB_QP_RETRY_CNT)
3779                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3780
3781         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3782                 if (attr->max_rd_atomic)
3783                         context->params1 |=
3784                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3785         }
3786
3787         if (attr_mask & IB_QP_SQ_PSN)
3788                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3789
3790         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3791                 if (attr->max_dest_rd_atomic)
3792                         context->params2 |=
3793                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3794         }
3795
3796         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3797                 __be32 access_flags;
3798
3799                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3800                 if (err)
3801                         goto out;
3802
3803                 context->params2 |= access_flags;
3804         }
3805
3806         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3807                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3808
3809         if (attr_mask & IB_QP_RQ_PSN)
3810                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3811
3812         if (attr_mask & IB_QP_QKEY)
3813                 context->qkey = cpu_to_be32(attr->qkey);
3814
3815         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3816                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3817
3818         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3819                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3820                                qp->port) - 1;
3821
3822                 /* Underlay port should be used - index 0 function per port */
3823                 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
3824                         port_num = 0;
3825
3826                 if (ibqp->counter)
3827                         set_id = ibqp->counter->id;
3828                 else
3829                         set_id = mlx5_ib_get_counters_id(dev, port_num);
3830                 context->qp_counter_set_usr_page |=
3831                         cpu_to_be32(set_id << 24);
3832         }
3833
3834         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3835                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3836
3837         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3838                 context->deth_sqpn = cpu_to_be32(1);
3839
3840         mlx5_cur = to_mlx5_state(cur_state);
3841         mlx5_new = to_mlx5_state(new_state);
3842
3843         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3844             !optab[mlx5_cur][mlx5_new]) {
3845                 err = -EINVAL;
3846                 goto out;
3847         }
3848
3849         op = optab[mlx5_cur][mlx5_new];
3850         optpar = ib_mask_to_mlx5_opt(attr_mask);
3851         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3852
3853         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3854             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
3855                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3856
3857                 raw_qp_param.operation = op;
3858                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3859                         raw_qp_param.rq_q_ctr_id = set_id;
3860                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3861                 }
3862
3863                 if (attr_mask & IB_QP_PORT)
3864                         raw_qp_param.port = attr->port_num;
3865
3866                 if (attr_mask & IB_QP_RATE_LIMIT) {
3867                         raw_qp_param.rl.rate = attr->rate_limit;
3868
3869                         if (ucmd->burst_info.max_burst_sz) {
3870                                 if (attr->rate_limit &&
3871                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3872                                         raw_qp_param.rl.max_burst_sz =
3873                                                 ucmd->burst_info.max_burst_sz;
3874                                 } else {
3875                                         err = -EINVAL;
3876                                         goto out;
3877                                 }
3878                         }
3879
3880                         if (ucmd->burst_info.typical_pkt_sz) {
3881                                 if (attr->rate_limit &&
3882                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3883                                         raw_qp_param.rl.typical_pkt_sz =
3884                                                 ucmd->burst_info.typical_pkt_sz;
3885                                 } else {
3886                                         err = -EINVAL;
3887                                         goto out;
3888                                 }
3889                         }
3890
3891                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3892                 }
3893
3894                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3895         } else {
3896                 err = mlx5_core_qp_modify(dev, op, optpar, context, &base->mqp);
3897         }
3898
3899         if (err)
3900                 goto out;
3901
3902         qp->state = new_state;
3903
3904         if (attr_mask & IB_QP_ACCESS_FLAGS)
3905                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3906         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3907                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3908         if (attr_mask & IB_QP_PORT)
3909                 qp->port = attr->port_num;
3910         if (attr_mask & IB_QP_ALT_PATH)
3911                 qp->trans_qp.alt_port = attr->alt_port_num;
3912
3913         /*
3914          * If we moved a kernel QP to RESET, clean up all old CQ
3915          * entries and reinitialize the QP.
3916          */
3917         if (new_state == IB_QPS_RESET &&
3918             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3919                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3920                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3921                 if (send_cq != recv_cq)
3922                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3923
3924                 qp->rq.head = 0;
3925                 qp->rq.tail = 0;
3926                 qp->sq.head = 0;
3927                 qp->sq.tail = 0;
3928                 qp->sq.cur_post = 0;
3929                 if (qp->sq.wqe_cnt)
3930                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3931                 qp->sq.last_poll = 0;
3932                 qp->db.db[MLX5_RCV_DBR] = 0;
3933                 qp->db.db[MLX5_SND_DBR] = 0;
3934         }
3935
3936         if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
3937                 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
3938                 if (!err)
3939                         qp->counter_pending = 0;
3940         }
3941
3942 out:
3943         kfree(context);
3944         return err;
3945 }
3946
3947 static inline bool is_valid_mask(int mask, int req, int opt)
3948 {
3949         if ((mask & req) != req)
3950                 return false;
3951
3952         if (mask & ~(req | opt))
3953                 return false;
3954
3955         return true;
3956 }
3957
3958 /* check valid transition for driver QP types
3959  * for now the only QP type that this function supports is DCI
3960  */
3961 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3962                                 enum ib_qp_attr_mask attr_mask)
3963 {
3964         int req = IB_QP_STATE;
3965         int opt = 0;
3966
3967         if (new_state == IB_QPS_RESET) {
3968                 return is_valid_mask(attr_mask, req, opt);
3969         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3970                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3971                 return is_valid_mask(attr_mask, req, opt);
3972         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3973                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3974                 return is_valid_mask(attr_mask, req, opt);
3975         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3976                 req |= IB_QP_PATH_MTU;
3977                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3978                 return is_valid_mask(attr_mask, req, opt);
3979         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3980                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3981                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3982                 opt = IB_QP_MIN_RNR_TIMER;
3983                 return is_valid_mask(attr_mask, req, opt);
3984         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3985                 opt = IB_QP_MIN_RNR_TIMER;
3986                 return is_valid_mask(attr_mask, req, opt);
3987         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3988                 return is_valid_mask(attr_mask, req, opt);
3989         }
3990         return false;
3991 }
3992
3993 /* mlx5_ib_modify_dct: modify a DCT QP
3994  * valid transitions are:
3995  * RESET to INIT: must set access_flags, pkey_index and port
3996  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3997  *                         mtu, gid_index and hop_limit
3998  * Other transitions and attributes are illegal
3999  */
4000 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4001                               int attr_mask, struct ib_udata *udata)
4002 {
4003         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4004         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4005         enum ib_qp_state cur_state, new_state;
4006         int err = 0;
4007         int required = IB_QP_STATE;
4008         void *dctc;
4009
4010         if (!(attr_mask & IB_QP_STATE))
4011                 return -EINVAL;
4012
4013         cur_state = qp->state;
4014         new_state = attr->qp_state;
4015
4016         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
4017         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4018                 u16 set_id;
4019
4020                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
4021                 if (!is_valid_mask(attr_mask, required, 0))
4022                         return -EINVAL;
4023
4024                 if (attr->port_num == 0 ||
4025                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
4026                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4027                                     attr->port_num, dev->num_ports);
4028                         return -EINVAL;
4029                 }
4030                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
4031                         MLX5_SET(dctc, dctc, rre, 1);
4032                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
4033                         MLX5_SET(dctc, dctc, rwe, 1);
4034                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
4035                         int atomic_mode;
4036
4037                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
4038                         if (atomic_mode < 0)
4039                                 return -EOPNOTSUPP;
4040
4041                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
4042                         MLX5_SET(dctc, dctc, rae, 1);
4043                 }
4044                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
4045                 MLX5_SET(dctc, dctc, port, attr->port_num);
4046
4047                 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
4048                 MLX5_SET(dctc, dctc, counter_set_id, set_id);
4049
4050         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4051                 struct mlx5_ib_modify_qp_resp resp = {};
4052                 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
4053                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
4054                                    sizeof(resp.dctn);
4055
4056                 if (udata->outlen < min_resp_len)
4057                         return -EINVAL;
4058                 resp.response_length = min_resp_len;
4059
4060                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
4061                 if (!is_valid_mask(attr_mask, required, 0))
4062                         return -EINVAL;
4063                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
4064                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
4065                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
4066                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
4067                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
4068                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
4069
4070                 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
4071                                            MLX5_ST_SZ_BYTES(create_dct_in), out,
4072                                            sizeof(out));
4073                 if (err)
4074                         return err;
4075                 resp.dctn = qp->dct.mdct.mqp.qpn;
4076                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4077                 if (err) {
4078                         mlx5_core_destroy_dct(dev, &qp->dct.mdct);
4079                         return err;
4080                 }
4081         } else {
4082                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
4083                 return -EINVAL;
4084         }
4085         if (err)
4086                 qp->state = IB_QPS_ERR;
4087         else
4088                 qp->state = new_state;
4089         return err;
4090 }
4091
4092 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4093                       int attr_mask, struct ib_udata *udata)
4094 {
4095         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4096         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4097         struct mlx5_ib_modify_qp ucmd = {};
4098         enum ib_qp_type qp_type;
4099         enum ib_qp_state cur_state, new_state;
4100         size_t required_cmd_sz;
4101         int err = -EINVAL;
4102         int port;
4103
4104         if (ibqp->rwq_ind_tbl)
4105                 return -ENOSYS;
4106
4107         if (udata && udata->inlen) {
4108                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4109                         sizeof(ucmd.reserved);
4110                 if (udata->inlen < required_cmd_sz)
4111                         return -EINVAL;
4112
4113                 if (udata->inlen > sizeof(ucmd) &&
4114                     !ib_is_udata_cleared(udata, sizeof(ucmd),
4115                                          udata->inlen - sizeof(ucmd)))
4116                         return -EOPNOTSUPP;
4117
4118                 if (ib_copy_from_udata(&ucmd, udata,
4119                                        min(udata->inlen, sizeof(ucmd))))
4120                         return -EFAULT;
4121
4122                 if (ucmd.comp_mask ||
4123                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
4124                     memchr_inv(&ucmd.burst_info.reserved, 0,
4125                                sizeof(ucmd.burst_info.reserved)))
4126                         return -EOPNOTSUPP;
4127         }
4128
4129         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4130                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
4131
4132         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
4133                                                                     qp->type;
4134
4135         if (qp_type == MLX5_IB_QPT_DCT)
4136                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
4137
4138         mutex_lock(&qp->mutex);
4139
4140         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
4141         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
4142
4143         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
4144                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4145         }
4146
4147         if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4148                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4149                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4150                                     attr_mask);
4151                         goto out;
4152                 }
4153         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
4154                    qp_type != MLX5_IB_QPT_DCI &&
4155                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4156                                        attr_mask)) {
4157                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4158                             cur_state, new_state, ibqp->qp_type, attr_mask);
4159                 goto out;
4160         } else if (qp_type == MLX5_IB_QPT_DCI &&
4161                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4162                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4163                             cur_state, new_state, qp_type, attr_mask);
4164                 goto out;
4165         }
4166
4167         if ((attr_mask & IB_QP_PORT) &&
4168             (attr->port_num == 0 ||
4169              attr->port_num > dev->num_ports)) {
4170                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4171                             attr->port_num, dev->num_ports);
4172                 goto out;
4173         }
4174
4175         if (attr_mask & IB_QP_PKEY_INDEX) {
4176                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4177                 if (attr->pkey_index >=
4178                     dev->mdev->port_caps[port - 1].pkey_table_len) {
4179                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4180                                     attr->pkey_index);
4181                         goto out;
4182                 }
4183         }
4184
4185         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
4186             attr->max_rd_atomic >
4187             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4188                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4189                             attr->max_rd_atomic);
4190                 goto out;
4191         }
4192
4193         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
4194             attr->max_dest_rd_atomic >
4195             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4196                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4197                             attr->max_dest_rd_atomic);
4198                 goto out;
4199         }
4200
4201         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4202                 err = 0;
4203                 goto out;
4204         }
4205
4206         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4207                                   new_state, &ucmd, udata);
4208
4209 out:
4210         mutex_unlock(&qp->mutex);
4211         return err;
4212 }
4213
4214 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4215                                    u32 wqe_sz, void **cur_edge)
4216 {
4217         u32 idx;
4218
4219         idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
4220         *cur_edge = get_sq_edge(sq, idx);
4221
4222         *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
4223 }
4224
4225 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
4226  * next nearby edge and get new address translation for current WQE position.
4227  * @sq - SQ buffer.
4228  * @seg: Current WQE position (16B aligned).
4229  * @wqe_sz: Total current WQE size [16B].
4230  * @cur_edge: Updated current edge.
4231  */
4232 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4233                                          u32 wqe_sz, void **cur_edge)
4234 {
4235         if (likely(*seg != *cur_edge))
4236                 return;
4237
4238         _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
4239 }
4240
4241 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
4242  * pointers. At the end @seg is aligned to 16B regardless the copied size.
4243  * @sq - SQ buffer.
4244  * @cur_edge: Updated current edge.
4245  * @seg: Current WQE position (16B aligned).
4246  * @wqe_sz: Total current WQE size [16B].
4247  * @src: Pointer to copy from.
4248  * @n: Number of bytes to copy.
4249  */
4250 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
4251                                    void **seg, u32 *wqe_sz, const void *src,
4252                                    size_t n)
4253 {
4254         while (likely(n)) {
4255                 size_t leftlen = *cur_edge - *seg;
4256                 size_t copysz = min_t(size_t, leftlen, n);
4257                 size_t stride;
4258
4259                 memcpy(*seg, src, copysz);
4260
4261                 n -= copysz;
4262                 src += copysz;
4263                 stride = !n ? ALIGN(copysz, 16) : copysz;
4264                 *seg += stride;
4265                 *wqe_sz += stride >> 4;
4266                 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
4267         }
4268 }
4269
4270 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
4271 {
4272         struct mlx5_ib_cq *cq;
4273         unsigned cur;
4274
4275         cur = wq->head - wq->tail;
4276         if (likely(cur + nreq < wq->max_post))
4277                 return 0;
4278
4279         cq = to_mcq(ib_cq);
4280         spin_lock(&cq->lock);
4281         cur = wq->head - wq->tail;
4282         spin_unlock(&cq->lock);
4283
4284         return cur + nreq >= wq->max_post;
4285 }
4286
4287 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
4288                                           u64 remote_addr, u32 rkey)
4289 {
4290         rseg->raddr    = cpu_to_be64(remote_addr);
4291         rseg->rkey     = cpu_to_be32(rkey);
4292         rseg->reserved = 0;
4293 }
4294
4295 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
4296                         void **seg, int *size, void **cur_edge)
4297 {
4298         struct mlx5_wqe_eth_seg *eseg = *seg;
4299
4300         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
4301
4302         if (wr->send_flags & IB_SEND_IP_CSUM)
4303                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
4304                                  MLX5_ETH_WQE_L4_CSUM;
4305
4306         if (wr->opcode == IB_WR_LSO) {
4307                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
4308                 size_t left, copysz;
4309                 void *pdata = ud_wr->header;
4310                 size_t stride;
4311
4312                 left = ud_wr->hlen;
4313                 eseg->mss = cpu_to_be16(ud_wr->mss);
4314                 eseg->inline_hdr.sz = cpu_to_be16(left);
4315
4316                 /* memcpy_send_wqe should get a 16B align address. Hence, we
4317                  * first copy up to the current edge and then, if needed,
4318                  * fall-through to memcpy_send_wqe.
4319                  */
4320                 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
4321                                left);
4322                 memcpy(eseg->inline_hdr.start, pdata, copysz);
4323                 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
4324                                sizeof(eseg->inline_hdr.start) + copysz, 16);
4325                 *size += stride / 16;
4326                 *seg += stride;
4327
4328                 if (copysz < left) {
4329                         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4330                         left -= copysz;
4331                         pdata += copysz;
4332                         memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4333                                         left);
4334                 }
4335
4336                 return;
4337         }
4338
4339         *seg += sizeof(struct mlx5_wqe_eth_seg);
4340         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
4341 }
4342
4343 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
4344                              const struct ib_send_wr *wr)
4345 {
4346         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4347         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4348         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
4349 }
4350
4351 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4352 {
4353         dseg->byte_count = cpu_to_be32(sg->length);
4354         dseg->lkey       = cpu_to_be32(sg->lkey);
4355         dseg->addr       = cpu_to_be64(sg->addr);
4356 }
4357
4358 static u64 get_xlt_octo(u64 bytes)
4359 {
4360         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4361                MLX5_IB_UMR_OCTOWORD;
4362 }
4363
4364 static __be64 frwr_mkey_mask(bool atomic)
4365 {
4366         u64 result;
4367
4368         result = MLX5_MKEY_MASK_LEN             |
4369                 MLX5_MKEY_MASK_PAGE_SIZE        |
4370                 MLX5_MKEY_MASK_START_ADDR       |
4371                 MLX5_MKEY_MASK_EN_RINVAL        |
4372                 MLX5_MKEY_MASK_KEY              |
4373                 MLX5_MKEY_MASK_LR               |
4374                 MLX5_MKEY_MASK_LW               |
4375                 MLX5_MKEY_MASK_RR               |
4376                 MLX5_MKEY_MASK_RW               |
4377                 MLX5_MKEY_MASK_SMALL_FENCE      |
4378                 MLX5_MKEY_MASK_FREE;
4379
4380         if (atomic)
4381                 result |= MLX5_MKEY_MASK_A;
4382
4383         return cpu_to_be64(result);
4384 }
4385
4386 static __be64 sig_mkey_mask(void)
4387 {
4388         u64 result;
4389
4390         result = MLX5_MKEY_MASK_LEN             |
4391                 MLX5_MKEY_MASK_PAGE_SIZE        |
4392                 MLX5_MKEY_MASK_START_ADDR       |
4393                 MLX5_MKEY_MASK_EN_SIGERR        |
4394                 MLX5_MKEY_MASK_EN_RINVAL        |
4395                 MLX5_MKEY_MASK_KEY              |
4396                 MLX5_MKEY_MASK_LR               |
4397                 MLX5_MKEY_MASK_LW               |
4398                 MLX5_MKEY_MASK_RR               |
4399                 MLX5_MKEY_MASK_RW               |
4400                 MLX5_MKEY_MASK_SMALL_FENCE      |
4401                 MLX5_MKEY_MASK_FREE             |
4402                 MLX5_MKEY_MASK_BSF_EN;
4403
4404         return cpu_to_be64(result);
4405 }
4406
4407 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
4408                             struct mlx5_ib_mr *mr, u8 flags, bool atomic)
4409 {
4410         int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4411
4412         memset(umr, 0, sizeof(*umr));
4413
4414         umr->flags = flags;
4415         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4416         umr->mkey_mask = frwr_mkey_mask(atomic);
4417 }
4418
4419 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4420 {
4421         memset(umr, 0, sizeof(*umr));
4422         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4423         umr->flags = MLX5_UMR_INLINE;
4424 }
4425
4426 static __be64 get_umr_enable_mr_mask(void)
4427 {
4428         u64 result;
4429
4430         result = MLX5_MKEY_MASK_KEY |
4431                  MLX5_MKEY_MASK_FREE;
4432
4433         return cpu_to_be64(result);
4434 }
4435
4436 static __be64 get_umr_disable_mr_mask(void)
4437 {
4438         u64 result;
4439
4440         result = MLX5_MKEY_MASK_FREE;
4441
4442         return cpu_to_be64(result);
4443 }
4444
4445 static __be64 get_umr_update_translation_mask(void)
4446 {
4447         u64 result;
4448
4449         result = MLX5_MKEY_MASK_LEN |
4450                  MLX5_MKEY_MASK_PAGE_SIZE |
4451                  MLX5_MKEY_MASK_START_ADDR;
4452
4453         return cpu_to_be64(result);
4454 }
4455
4456 static __be64 get_umr_update_access_mask(int atomic)
4457 {
4458         u64 result;
4459
4460         result = MLX5_MKEY_MASK_LR |
4461                  MLX5_MKEY_MASK_LW |
4462                  MLX5_MKEY_MASK_RR |
4463                  MLX5_MKEY_MASK_RW;
4464
4465         if (atomic)
4466                 result |= MLX5_MKEY_MASK_A;
4467
4468         return cpu_to_be64(result);
4469 }
4470
4471 static __be64 get_umr_update_pd_mask(void)
4472 {
4473         u64 result;
4474
4475         result = MLX5_MKEY_MASK_PD;
4476
4477         return cpu_to_be64(result);
4478 }
4479
4480 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4481 {
4482         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4483              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4484             (mask & MLX5_MKEY_MASK_A &&
4485              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4486                 return -EPERM;
4487         return 0;
4488 }
4489
4490 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4491                                struct mlx5_wqe_umr_ctrl_seg *umr,
4492                                const struct ib_send_wr *wr, int atomic)
4493 {
4494         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4495
4496         memset(umr, 0, sizeof(*umr));
4497
4498         if (!umrwr->ignore_free_state) {
4499                 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4500                          /* fail if free */
4501                         umr->flags = MLX5_UMR_CHECK_FREE;
4502                 else
4503                         /* fail if not free */
4504                         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
4505         }
4506
4507         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4508         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4509                 u64 offset = get_xlt_octo(umrwr->offset);
4510
4511                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4512                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4513                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4514         }
4515         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4516                 umr->mkey_mask |= get_umr_update_translation_mask();
4517         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4518                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4519                 umr->mkey_mask |= get_umr_update_pd_mask();
4520         }
4521         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4522                 umr->mkey_mask |= get_umr_enable_mr_mask();
4523         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4524                 umr->mkey_mask |= get_umr_disable_mr_mask();
4525
4526         if (!wr->num_sge)
4527                 umr->flags |= MLX5_UMR_INLINE;
4528
4529         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4530 }
4531
4532 static u8 get_umr_flags(int acc)
4533 {
4534         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4535                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4536                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4537                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4538                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4539 }
4540
4541 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4542                              struct mlx5_ib_mr *mr,
4543                              u32 key, int access)
4544 {
4545         int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1;
4546
4547         memset(seg, 0, sizeof(*seg));
4548
4549         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4550                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4551         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4552                 /* KLMs take twice the size of MTTs */
4553                 ndescs *= 2;
4554
4555         seg->flags = get_umr_flags(access) | mr->access_mode;
4556         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4557         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4558         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4559         seg->len = cpu_to_be64(mr->ibmr.length);
4560         seg->xlt_oct_size = cpu_to_be32(ndescs);
4561 }
4562
4563 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4564 {
4565         memset(seg, 0, sizeof(*seg));
4566         seg->status = MLX5_MKEY_STATUS_FREE;
4567 }
4568
4569 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4570                                  const struct ib_send_wr *wr)
4571 {
4572         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4573
4574         memset(seg, 0, sizeof(*seg));
4575         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4576                 seg->status = MLX5_MKEY_STATUS_FREE;
4577
4578         seg->flags = convert_access(umrwr->access_flags);
4579         if (umrwr->pd)
4580                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4581         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4582             !umrwr->length)
4583                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4584
4585         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4586         seg->len = cpu_to_be64(umrwr->length);
4587         seg->log2_page_size = umrwr->page_shift;
4588         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4589                                        mlx5_mkey_variant(umrwr->mkey));
4590 }
4591
4592 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4593                              struct mlx5_ib_mr *mr,
4594                              struct mlx5_ib_pd *pd)
4595 {
4596         int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs);
4597
4598         dseg->addr = cpu_to_be64(mr->desc_map);
4599         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4600         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4601 }
4602
4603 static __be32 send_ieth(const struct ib_send_wr *wr)
4604 {
4605         switch (wr->opcode) {
4606         case IB_WR_SEND_WITH_IMM:
4607         case IB_WR_RDMA_WRITE_WITH_IMM:
4608                 return wr->ex.imm_data;
4609
4610         case IB_WR_SEND_WITH_INV:
4611                 return cpu_to_be32(wr->ex.invalidate_rkey);
4612
4613         default:
4614                 return 0;
4615         }
4616 }
4617
4618 static u8 calc_sig(void *wqe, int size)
4619 {
4620         u8 *p = wqe;
4621         u8 res = 0;
4622         int i;
4623
4624         for (i = 0; i < size; i++)
4625                 res ^= p[i];
4626
4627         return ~res;
4628 }
4629
4630 static u8 wq_sig(void *wqe)
4631 {
4632         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4633 }
4634
4635 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4636                             void **wqe, int *wqe_sz, void **cur_edge)
4637 {
4638         struct mlx5_wqe_inline_seg *seg;
4639         size_t offset;
4640         int inl = 0;
4641         int i;
4642
4643         seg = *wqe;
4644         *wqe += sizeof(*seg);
4645         offset = sizeof(*seg);
4646
4647         for (i = 0; i < wr->num_sge; i++) {
4648                 size_t len  = wr->sg_list[i].length;
4649                 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4650
4651                 inl += len;
4652
4653                 if (unlikely(inl > qp->max_inline_data))
4654                         return -ENOMEM;
4655
4656                 while (likely(len)) {
4657                         size_t leftlen;
4658                         size_t copysz;
4659
4660                         handle_post_send_edge(&qp->sq, wqe,
4661                                               *wqe_sz + (offset >> 4),
4662                                               cur_edge);
4663
4664                         leftlen = *cur_edge - *wqe;
4665                         copysz = min_t(size_t, leftlen, len);
4666
4667                         memcpy(*wqe, addr, copysz);
4668                         len -= copysz;
4669                         addr += copysz;
4670                         *wqe += copysz;
4671                         offset += copysz;
4672                 }
4673         }
4674
4675         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4676
4677         *wqe_sz +=  ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4678
4679         return 0;
4680 }
4681
4682 static u16 prot_field_size(enum ib_signature_type type)
4683 {
4684         switch (type) {
4685         case IB_SIG_TYPE_T10_DIF:
4686                 return MLX5_DIF_SIZE;
4687         default:
4688                 return 0;
4689         }
4690 }
4691
4692 static u8 bs_selector(int block_size)
4693 {
4694         switch (block_size) {
4695         case 512:           return 0x1;
4696         case 520:           return 0x2;
4697         case 4096:          return 0x3;
4698         case 4160:          return 0x4;
4699         case 1073741824:    return 0x5;
4700         default:            return 0;
4701         }
4702 }
4703
4704 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4705                               struct mlx5_bsf_inl *inl)
4706 {
4707         /* Valid inline section and allow BSF refresh */
4708         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4709                                        MLX5_BSF_REFRESH_DIF);
4710         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4711         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4712         /* repeating block */
4713         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4714         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4715                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4716
4717         if (domain->sig.dif.ref_remap)
4718                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4719
4720         if (domain->sig.dif.app_escape) {
4721                 if (domain->sig.dif.ref_escape)
4722                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4723                 else
4724                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4725         }
4726
4727         inl->dif_app_bitmask_check =
4728                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4729 }
4730
4731 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4732                         struct ib_sig_attrs *sig_attrs,
4733                         struct mlx5_bsf *bsf, u32 data_size)
4734 {
4735         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4736         struct mlx5_bsf_basic *basic = &bsf->basic;
4737         struct ib_sig_domain *mem = &sig_attrs->mem;
4738         struct ib_sig_domain *wire = &sig_attrs->wire;
4739
4740         memset(bsf, 0, sizeof(*bsf));
4741
4742         /* Basic + Extended + Inline */
4743         basic->bsf_size_sbs = 1 << 7;
4744         /* Input domain check byte mask */
4745         basic->check_byte_mask = sig_attrs->check_mask;
4746         basic->raw_data_size = cpu_to_be32(data_size);
4747
4748         /* Memory domain */
4749         switch (sig_attrs->mem.sig_type) {
4750         case IB_SIG_TYPE_NONE:
4751                 break;
4752         case IB_SIG_TYPE_T10_DIF:
4753                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4754                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4755                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4756                 break;
4757         default:
4758                 return -EINVAL;
4759         }
4760
4761         /* Wire domain */
4762         switch (sig_attrs->wire.sig_type) {
4763         case IB_SIG_TYPE_NONE:
4764                 break;
4765         case IB_SIG_TYPE_T10_DIF:
4766                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4767                     mem->sig_type == wire->sig_type) {
4768                         /* Same block structure */
4769                         basic->bsf_size_sbs |= 1 << 4;
4770                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4771                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4772                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4773                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4774                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4775                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4776                 } else
4777                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4778
4779                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4780                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4781                 break;
4782         default:
4783                 return -EINVAL;
4784         }
4785
4786         return 0;
4787 }
4788
4789 static int set_sig_data_segment(const struct ib_send_wr *send_wr,
4790                                 struct ib_mr *sig_mr,
4791                                 struct ib_sig_attrs *sig_attrs,
4792                                 struct mlx5_ib_qp *qp, void **seg, int *size,
4793                                 void **cur_edge)
4794 {
4795         struct mlx5_bsf *bsf;
4796         u32 data_len;
4797         u32 data_key;
4798         u64 data_va;
4799         u32 prot_len = 0;
4800         u32 prot_key = 0;
4801         u64 prot_va = 0;
4802         bool prot = false;
4803         int ret;
4804         int wqe_size;
4805         struct mlx5_ib_mr *mr = to_mmr(sig_mr);
4806         struct mlx5_ib_mr *pi_mr = mr->pi_mr;
4807
4808         data_len = pi_mr->data_length;
4809         data_key = pi_mr->ibmr.lkey;
4810         data_va = pi_mr->data_iova;
4811         if (pi_mr->meta_ndescs) {
4812                 prot_len = pi_mr->meta_length;
4813                 prot_key = pi_mr->ibmr.lkey;
4814                 prot_va = pi_mr->pi_iova;
4815                 prot = true;
4816         }
4817
4818         if (!prot || (data_key == prot_key && data_va == prot_va &&
4819                       data_len == prot_len)) {
4820                 /**
4821                  * Source domain doesn't contain signature information
4822                  * or data and protection are interleaved in memory.
4823                  * So need construct:
4824                  *                  ------------------
4825                  *                 |     data_klm     |
4826                  *                  ------------------
4827                  *                 |       BSF        |
4828                  *                  ------------------
4829                  **/
4830                 struct mlx5_klm *data_klm = *seg;
4831
4832                 data_klm->bcount = cpu_to_be32(data_len);
4833                 data_klm->key = cpu_to_be32(data_key);
4834                 data_klm->va = cpu_to_be64(data_va);
4835                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4836         } else {
4837                 /**
4838                  * Source domain contains signature information
4839                  * So need construct a strided block format:
4840                  *               ---------------------------
4841                  *              |     stride_block_ctrl     |
4842                  *               ---------------------------
4843                  *              |          data_klm         |
4844                  *               ---------------------------
4845                  *              |          prot_klm         |
4846                  *               ---------------------------
4847                  *              |             BSF           |
4848                  *               ---------------------------
4849                  **/
4850                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4851                 struct mlx5_stride_block_entry *data_sentry;
4852                 struct mlx5_stride_block_entry *prot_sentry;
4853                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4854                 int prot_size;
4855
4856                 sblock_ctrl = *seg;
4857                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4858                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4859
4860                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4861                 if (!prot_size) {
4862                         pr_err("Bad block size given: %u\n", block_size);
4863                         return -EINVAL;
4864                 }
4865                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4866                                                             prot_size);
4867                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4868                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4869                 sblock_ctrl->num_entries = cpu_to_be16(2);
4870
4871                 data_sentry->bcount = cpu_to_be16(block_size);
4872                 data_sentry->key = cpu_to_be32(data_key);
4873                 data_sentry->va = cpu_to_be64(data_va);
4874                 data_sentry->stride = cpu_to_be16(block_size);
4875
4876                 prot_sentry->bcount = cpu_to_be16(prot_size);
4877                 prot_sentry->key = cpu_to_be32(prot_key);
4878                 prot_sentry->va = cpu_to_be64(prot_va);
4879                 prot_sentry->stride = cpu_to_be16(prot_size);
4880
4881                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4882                                  sizeof(*prot_sentry), 64);
4883         }
4884
4885         *seg += wqe_size;
4886         *size += wqe_size / 16;
4887         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4888
4889         bsf = *seg;
4890         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4891         if (ret)
4892                 return -EINVAL;
4893
4894         *seg += sizeof(*bsf);
4895         *size += sizeof(*bsf) / 16;
4896         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4897
4898         return 0;
4899 }
4900
4901 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4902                                  struct ib_mr *sig_mr, int access_flags,
4903                                  u32 size, u32 length, u32 pdn)
4904 {
4905         u32 sig_key = sig_mr->rkey;
4906         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4907
4908         memset(seg, 0, sizeof(*seg));
4909
4910         seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS;
4911         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4912         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4913                                     MLX5_MKEY_BSF_EN | pdn);
4914         seg->len = cpu_to_be64(length);
4915         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4916         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4917 }
4918
4919 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4920                                 u32 size)
4921 {
4922         memset(umr, 0, sizeof(*umr));
4923
4924         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4925         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4926         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4927         umr->mkey_mask = sig_mkey_mask();
4928 }
4929
4930 static int set_pi_umr_wr(const struct ib_send_wr *send_wr,
4931                          struct mlx5_ib_qp *qp, void **seg, int *size,
4932                          void **cur_edge)
4933 {
4934         const struct ib_reg_wr *wr = reg_wr(send_wr);
4935         struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr);
4936         struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr;
4937         struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs;
4938         u32 pdn = get_pd(qp)->pdn;
4939         u32 xlt_size;
4940         int region_len, ret;
4941
4942         if (unlikely(send_wr->num_sge != 0) ||
4943             unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) ||
4944             unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) ||
4945             unlikely(!sig_mr->sig->sig_status_checked))
4946                 return -EINVAL;
4947
4948         /* length of the protected region, data + protection */
4949         region_len = pi_mr->ibmr.length;
4950
4951         /**
4952          * KLM octoword size - if protection was provided
4953          * then we use strided block format (3 octowords),
4954          * else we use single KLM (1 octoword)
4955          **/
4956         if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE)
4957                 xlt_size = 0x30;
4958         else
4959                 xlt_size = sizeof(struct mlx5_klm);
4960
4961         set_sig_umr_segment(*seg, xlt_size);
4962         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4963         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4964         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4965
4966         set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len,
4967                              pdn);
4968         *seg += sizeof(struct mlx5_mkey_seg);
4969         *size += sizeof(struct mlx5_mkey_seg) / 16;
4970         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4971
4972         ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size,
4973                                    cur_edge);
4974         if (ret)
4975                 return ret;
4976
4977         sig_mr->sig->sig_status_checked = false;
4978         return 0;
4979 }
4980
4981 static int set_psv_wr(struct ib_sig_domain *domain,
4982                       u32 psv_idx, void **seg, int *size)
4983 {
4984         struct mlx5_seg_set_psv *psv_seg = *seg;
4985
4986         memset(psv_seg, 0, sizeof(*psv_seg));
4987         psv_seg->psv_num = cpu_to_be32(psv_idx);
4988         switch (domain->sig_type) {
4989         case IB_SIG_TYPE_NONE:
4990                 break;
4991         case IB_SIG_TYPE_T10_DIF:
4992                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4993                                                      domain->sig.dif.app_tag);
4994                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4995                 break;
4996         default:
4997                 pr_err("Bad signature type (%d) is given.\n",
4998                        domain->sig_type);
4999                 return -EINVAL;
5000         }
5001
5002         *seg += sizeof(*psv_seg);
5003         *size += sizeof(*psv_seg) / 16;
5004
5005         return 0;
5006 }
5007
5008 static int set_reg_wr(struct mlx5_ib_qp *qp,
5009                       const struct ib_reg_wr *wr,
5010                       void **seg, int *size, void **cur_edge,
5011                       bool check_not_free)
5012 {
5013         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
5014         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
5015         struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device);
5016         int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
5017         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
5018         bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC;
5019         u8 flags = 0;
5020
5021         if (!mlx5_ib_can_use_umr(dev, atomic, wr->access)) {
5022                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
5023                              "Fast update of %s for MR is disabled\n",
5024                              (MLX5_CAP_GEN(dev->mdev,
5025                                            umr_modify_entity_size_disabled)) ?
5026                                      "entity size" :
5027                                      "atomic access");
5028                 return -EINVAL;
5029         }
5030
5031         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
5032                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
5033                              "Invalid IB_SEND_INLINE send flag\n");
5034                 return -EINVAL;
5035         }
5036
5037         if (check_not_free)
5038                 flags |= MLX5_UMR_CHECK_NOT_FREE;
5039         if (umr_inline)
5040                 flags |= MLX5_UMR_INLINE;
5041
5042         set_reg_umr_seg(*seg, mr, flags, atomic);
5043         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5044         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5045         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
5046
5047         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
5048         *seg += sizeof(struct mlx5_mkey_seg);
5049         *size += sizeof(struct mlx5_mkey_seg) / 16;
5050         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
5051
5052         if (umr_inline) {
5053                 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
5054                                 mr_list_size);
5055                 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
5056         } else {
5057                 set_reg_data_seg(*seg, mr, pd);
5058                 *seg += sizeof(struct mlx5_wqe_data_seg);
5059                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
5060         }
5061         return 0;
5062 }
5063
5064 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
5065                         void **cur_edge)
5066 {
5067         set_linv_umr_seg(*seg);
5068         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5069         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5070         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
5071         set_linv_mkey_seg(*seg);
5072         *seg += sizeof(struct mlx5_mkey_seg);
5073         *size += sizeof(struct mlx5_mkey_seg) / 16;
5074         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
5075 }
5076
5077 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
5078 {
5079         __be32 *p = NULL;
5080         int i, j;
5081
5082         pr_debug("dump WQE index %u:\n", idx);
5083         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
5084                 if ((i & 0xf) == 0) {
5085                         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
5086                         pr_debug("WQBB at %p:\n", (void *)p);
5087                         j = 0;
5088                         idx = (idx + 1) & (qp->sq.wqe_cnt - 1);
5089                 }
5090                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
5091                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
5092                          be32_to_cpu(p[j + 3]));
5093         }
5094 }
5095
5096 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
5097                        struct mlx5_wqe_ctrl_seg **ctrl,
5098                        const struct ib_send_wr *wr, unsigned int *idx,
5099                        int *size, void **cur_edge, int nreq,
5100                        bool send_signaled, bool solicited)
5101 {
5102         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
5103                 return -ENOMEM;
5104
5105         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
5106         *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
5107         *ctrl = *seg;
5108         *(uint32_t *)(*seg + 8) = 0;
5109         (*ctrl)->imm = send_ieth(wr);
5110         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
5111                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
5112                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
5113
5114         *seg += sizeof(**ctrl);
5115         *size = sizeof(**ctrl) / 16;
5116         *cur_edge = qp->sq.cur_edge;
5117
5118         return 0;
5119 }
5120
5121 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
5122                      struct mlx5_wqe_ctrl_seg **ctrl,
5123                      const struct ib_send_wr *wr, unsigned *idx,
5124                      int *size, void **cur_edge, int nreq)
5125 {
5126         return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
5127                            wr->send_flags & IB_SEND_SIGNALED,
5128                            wr->send_flags & IB_SEND_SOLICITED);
5129 }
5130
5131 static void finish_wqe(struct mlx5_ib_qp *qp,
5132                        struct mlx5_wqe_ctrl_seg *ctrl,
5133                        void *seg, u8 size, void *cur_edge,
5134                        unsigned int idx, u64 wr_id, int nreq, u8 fence,
5135                        u32 mlx5_opcode)
5136 {
5137         u8 opmod = 0;
5138
5139         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
5140                                              mlx5_opcode | ((u32)opmod << 24));
5141         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
5142         ctrl->fm_ce_se |= fence;
5143         if (unlikely(qp->flags_en & MLX5_QP_FLAG_SIGNATURE))
5144                 ctrl->signature = wq_sig(ctrl);
5145
5146         qp->sq.wrid[idx] = wr_id;
5147         qp->sq.w_list[idx].opcode = mlx5_opcode;
5148         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
5149         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
5150         qp->sq.w_list[idx].next = qp->sq.cur_post;
5151
5152         /* We save the edge which was possibly updated during the WQE
5153          * construction, into SQ's cache.
5154          */
5155         seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
5156         qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
5157                           get_sq_edge(&qp->sq, qp->sq.cur_post &
5158                                       (qp->sq.wqe_cnt - 1)) :
5159                           cur_edge;
5160 }
5161
5162 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5163                               const struct ib_send_wr **bad_wr, bool drain)
5164 {
5165         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
5166         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5167         struct mlx5_core_dev *mdev = dev->mdev;
5168         struct ib_reg_wr reg_pi_wr;
5169         struct mlx5_ib_qp *qp;
5170         struct mlx5_ib_mr *mr;
5171         struct mlx5_ib_mr *pi_mr;
5172         struct mlx5_ib_mr pa_pi_mr;
5173         struct ib_sig_attrs *sig_attrs;
5174         struct mlx5_wqe_xrc_seg *xrc;
5175         struct mlx5_bf *bf;
5176         void *cur_edge;
5177         int uninitialized_var(size);
5178         unsigned long flags;
5179         unsigned idx;
5180         int err = 0;
5181         int num_sge;
5182         void *seg;
5183         int nreq;
5184         int i;
5185         u8 next_fence = 0;
5186         u8 fence;
5187
5188         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5189                      !drain)) {
5190                 *bad_wr = wr;
5191                 return -EIO;
5192         }
5193
5194         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5195                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
5196
5197         qp = to_mqp(ibqp);
5198         bf = &qp->bf;
5199
5200         spin_lock_irqsave(&qp->sq.lock, flags);
5201
5202         for (nreq = 0; wr; nreq++, wr = wr->next) {
5203                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
5204                         mlx5_ib_warn(dev, "\n");
5205                         err = -EINVAL;
5206                         *bad_wr = wr;
5207                         goto out;
5208                 }
5209
5210                 num_sge = wr->num_sge;
5211                 if (unlikely(num_sge > qp->sq.max_gs)) {
5212                         mlx5_ib_warn(dev, "\n");
5213                         err = -EINVAL;
5214                         *bad_wr = wr;
5215                         goto out;
5216                 }
5217
5218                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
5219                                 nreq);
5220                 if (err) {
5221                         mlx5_ib_warn(dev, "\n");
5222                         err = -ENOMEM;
5223                         *bad_wr = wr;
5224                         goto out;
5225                 }
5226
5227                 if (wr->opcode == IB_WR_REG_MR ||
5228                     wr->opcode == IB_WR_REG_MR_INTEGRITY) {
5229                         fence = dev->umr_fence;
5230                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
5231                 } else  {
5232                         if (wr->send_flags & IB_SEND_FENCE) {
5233                                 if (qp->next_fence)
5234                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
5235                                 else
5236                                         fence = MLX5_FENCE_MODE_FENCE;
5237                         } else {
5238                                 fence = qp->next_fence;
5239                         }
5240                 }
5241
5242                 switch (ibqp->qp_type) {
5243                 case IB_QPT_XRC_INI:
5244                         xrc = seg;
5245                         seg += sizeof(*xrc);
5246                         size += sizeof(*xrc) / 16;
5247                         /* fall through */
5248                 case IB_QPT_RC:
5249                         switch (wr->opcode) {
5250                         case IB_WR_RDMA_READ:
5251                         case IB_WR_RDMA_WRITE:
5252                         case IB_WR_RDMA_WRITE_WITH_IMM:
5253                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5254                                               rdma_wr(wr)->rkey);
5255                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
5256                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5257                                 break;
5258
5259                         case IB_WR_ATOMIC_CMP_AND_SWP:
5260                         case IB_WR_ATOMIC_FETCH_AND_ADD:
5261                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
5262                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
5263                                 err = -ENOSYS;
5264                                 *bad_wr = wr;
5265                                 goto out;
5266
5267                         case IB_WR_LOCAL_INV:
5268                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
5269                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
5270                                 set_linv_wr(qp, &seg, &size, &cur_edge);
5271                                 num_sge = 0;
5272                                 break;
5273
5274                         case IB_WR_REG_MR:
5275                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
5276                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
5277                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
5278                                                  &cur_edge, true);
5279                                 if (err) {
5280                                         *bad_wr = wr;
5281                                         goto out;
5282                                 }
5283                                 num_sge = 0;
5284                                 break;
5285
5286                         case IB_WR_REG_MR_INTEGRITY:
5287                                 qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY;
5288
5289                                 mr = to_mmr(reg_wr(wr)->mr);
5290                                 pi_mr = mr->pi_mr;
5291
5292                                 if (pi_mr) {
5293                                         memset(&reg_pi_wr, 0,
5294                                                sizeof(struct ib_reg_wr));
5295
5296                                         reg_pi_wr.mr = &pi_mr->ibmr;
5297                                         reg_pi_wr.access = reg_wr(wr)->access;
5298                                         reg_pi_wr.key = pi_mr->ibmr.rkey;
5299
5300                                         ctrl->imm = cpu_to_be32(reg_pi_wr.key);
5301                                         /* UMR for data + prot registration */
5302                                         err = set_reg_wr(qp, &reg_pi_wr, &seg,
5303                                                          &size, &cur_edge,
5304                                                          false);
5305                                         if (err) {
5306                                                 *bad_wr = wr;
5307                                                 goto out;
5308                                         }
5309                                         finish_wqe(qp, ctrl, seg, size,
5310                                                    cur_edge, idx, wr->wr_id,
5311                                                    nreq, fence,
5312                                                    MLX5_OPCODE_UMR);
5313
5314                                         err = begin_wqe(qp, &seg, &ctrl, wr,
5315                                                         &idx, &size, &cur_edge,
5316                                                         nreq);
5317                                         if (err) {
5318                                                 mlx5_ib_warn(dev, "\n");
5319                                                 err = -ENOMEM;
5320                                                 *bad_wr = wr;
5321                                                 goto out;
5322                                         }
5323                                 } else {
5324                                         memset(&pa_pi_mr, 0,
5325                                                sizeof(struct mlx5_ib_mr));
5326                                         /* No UMR, use local_dma_lkey */
5327                                         pa_pi_mr.ibmr.lkey =
5328                                                 mr->ibmr.pd->local_dma_lkey;
5329
5330                                         pa_pi_mr.ndescs = mr->ndescs;
5331                                         pa_pi_mr.data_length = mr->data_length;
5332                                         pa_pi_mr.data_iova = mr->data_iova;
5333                                         if (mr->meta_ndescs) {
5334                                                 pa_pi_mr.meta_ndescs =
5335                                                         mr->meta_ndescs;
5336                                                 pa_pi_mr.meta_length =
5337                                                         mr->meta_length;
5338                                                 pa_pi_mr.pi_iova = mr->pi_iova;
5339                                         }
5340
5341                                         pa_pi_mr.ibmr.length = mr->ibmr.length;
5342                                         mr->pi_mr = &pa_pi_mr;
5343                                 }
5344                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
5345                                 /* UMR for sig MR */
5346                                 err = set_pi_umr_wr(wr, qp, &seg, &size,
5347                                                     &cur_edge);
5348                                 if (err) {
5349                                         mlx5_ib_warn(dev, "\n");
5350                                         *bad_wr = wr;
5351                                         goto out;
5352                                 }
5353                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5354                                            wr->wr_id, nreq, fence,
5355                                            MLX5_OPCODE_UMR);
5356
5357                                 /*
5358                                  * SET_PSV WQEs are not signaled and solicited
5359                                  * on error
5360                                  */
5361                                 sig_attrs = mr->ibmr.sig_attrs;
5362                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5363                                                   &size, &cur_edge, nreq, false,
5364                                                   true);
5365                                 if (err) {
5366                                         mlx5_ib_warn(dev, "\n");
5367                                         err = -ENOMEM;
5368                                         *bad_wr = wr;
5369                                         goto out;
5370                                 }
5371                                 err = set_psv_wr(&sig_attrs->mem,
5372                                                  mr->sig->psv_memory.psv_idx,
5373                                                  &seg, &size);
5374                                 if (err) {
5375                                         mlx5_ib_warn(dev, "\n");
5376                                         *bad_wr = wr;
5377                                         goto out;
5378                                 }
5379                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5380                                            wr->wr_id, nreq, next_fence,
5381                                            MLX5_OPCODE_SET_PSV);
5382
5383                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5384                                                   &size, &cur_edge, nreq, false,
5385                                                   true);
5386                                 if (err) {
5387                                         mlx5_ib_warn(dev, "\n");
5388                                         err = -ENOMEM;
5389                                         *bad_wr = wr;
5390                                         goto out;
5391                                 }
5392                                 err = set_psv_wr(&sig_attrs->wire,
5393                                                  mr->sig->psv_wire.psv_idx,
5394                                                  &seg, &size);
5395                                 if (err) {
5396                                         mlx5_ib_warn(dev, "\n");
5397                                         *bad_wr = wr;
5398                                         goto out;
5399                                 }
5400                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5401                                            wr->wr_id, nreq, next_fence,
5402                                            MLX5_OPCODE_SET_PSV);
5403
5404                                 qp->next_fence =
5405                                         MLX5_FENCE_MODE_INITIATOR_SMALL;
5406                                 num_sge = 0;
5407                                 goto skip_psv;
5408
5409                         default:
5410                                 break;
5411                         }
5412                         break;
5413
5414                 case IB_QPT_UC:
5415                         switch (wr->opcode) {
5416                         case IB_WR_RDMA_WRITE:
5417                         case IB_WR_RDMA_WRITE_WITH_IMM:
5418                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5419                                               rdma_wr(wr)->rkey);
5420                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
5421                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5422                                 break;
5423
5424                         default:
5425                                 break;
5426                         }
5427                         break;
5428
5429                 case IB_QPT_SMI:
5430                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5431                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5432                                 err = -EPERM;
5433                                 *bad_wr = wr;
5434                                 goto out;
5435                         }
5436                         /* fall through */
5437                 case MLX5_IB_QPT_HW_GSI:
5438                         set_datagram_seg(seg, wr);
5439                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5440                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5441                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5442
5443                         break;
5444                 case IB_QPT_UD:
5445                         set_datagram_seg(seg, wr);
5446                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5447                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5448                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5449
5450                         /* handle qp that supports ud offload */
5451                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5452                                 struct mlx5_wqe_eth_pad *pad;
5453
5454                                 pad = seg;
5455                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5456                                 seg += sizeof(struct mlx5_wqe_eth_pad);
5457                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
5458                                 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5459                                 handle_post_send_edge(&qp->sq, &seg, size,
5460                                                       &cur_edge);
5461                         }
5462                         break;
5463                 case MLX5_IB_QPT_REG_UMR:
5464                         if (wr->opcode != MLX5_IB_WR_UMR) {
5465                                 err = -EINVAL;
5466                                 mlx5_ib_warn(dev, "bad opcode\n");
5467                                 goto out;
5468                         }
5469                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
5470                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
5471                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5472                         if (unlikely(err))
5473                                 goto out;
5474                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5475                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5476                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5477                         set_reg_mkey_segment(seg, wr);
5478                         seg += sizeof(struct mlx5_mkey_seg);
5479                         size += sizeof(struct mlx5_mkey_seg) / 16;
5480                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5481                         break;
5482
5483                 default:
5484                         break;
5485                 }
5486
5487                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
5488                         err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
5489                         if (unlikely(err)) {
5490                                 mlx5_ib_warn(dev, "\n");
5491                                 *bad_wr = wr;
5492                                 goto out;
5493                         }
5494                 } else {
5495                         for (i = 0; i < num_sge; i++) {
5496                                 handle_post_send_edge(&qp->sq, &seg, size,
5497                                                       &cur_edge);
5498                                 if (likely(wr->sg_list[i].length)) {
5499                                         set_data_ptr_seg
5500                                         ((struct mlx5_wqe_data_seg *)seg,
5501                                          wr->sg_list + i);
5502                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
5503                                         seg += sizeof(struct mlx5_wqe_data_seg);
5504                                 }
5505                         }
5506                 }
5507
5508                 qp->next_fence = next_fence;
5509                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5510                            fence, mlx5_ib_opcode[wr->opcode]);
5511 skip_psv:
5512                 if (0)
5513                         dump_wqe(qp, idx, size);
5514         }
5515
5516 out:
5517         if (likely(nreq)) {
5518                 qp->sq.head += nreq;
5519
5520                 /* Make sure that descriptors are written before
5521                  * updating doorbell record and ringing the doorbell
5522                  */
5523                 wmb();
5524
5525                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5526
5527                 /* Make sure doorbell record is visible to the HCA before
5528                  * we hit doorbell */
5529                 wmb();
5530
5531                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
5532                 /* Make sure doorbells don't leak out of SQ spinlock
5533                  * and reach the HCA out of order.
5534                  */
5535                 bf->offset ^= bf->buf_size;
5536         }
5537
5538         spin_unlock_irqrestore(&qp->sq.lock, flags);
5539
5540         return err;
5541 }
5542
5543 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5544                       const struct ib_send_wr **bad_wr)
5545 {
5546         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5547 }
5548
5549 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5550 {
5551         sig->signature = calc_sig(sig, size);
5552 }
5553
5554 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5555                       const struct ib_recv_wr **bad_wr, bool drain)
5556 {
5557         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5558         struct mlx5_wqe_data_seg *scat;
5559         struct mlx5_rwqe_sig *sig;
5560         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5561         struct mlx5_core_dev *mdev = dev->mdev;
5562         unsigned long flags;
5563         int err = 0;
5564         int nreq;
5565         int ind;
5566         int i;
5567
5568         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5569                      !drain)) {
5570                 *bad_wr = wr;
5571                 return -EIO;
5572         }
5573
5574         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5575                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5576
5577         spin_lock_irqsave(&qp->rq.lock, flags);
5578
5579         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5580
5581         for (nreq = 0; wr; nreq++, wr = wr->next) {
5582                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5583                         err = -ENOMEM;
5584                         *bad_wr = wr;
5585                         goto out;
5586                 }
5587
5588                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5589                         err = -EINVAL;
5590                         *bad_wr = wr;
5591                         goto out;
5592                 }
5593
5594                 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5595                 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
5596                         scat++;
5597
5598                 for (i = 0; i < wr->num_sge; i++)
5599                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5600
5601                 if (i < qp->rq.max_gs) {
5602                         scat[i].byte_count = 0;
5603                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5604                         scat[i].addr       = 0;
5605                 }
5606
5607                 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) {
5608                         sig = (struct mlx5_rwqe_sig *)scat;
5609                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5610                 }
5611
5612                 qp->rq.wrid[ind] = wr->wr_id;
5613
5614                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5615         }
5616
5617 out:
5618         if (likely(nreq)) {
5619                 qp->rq.head += nreq;
5620
5621                 /* Make sure that descriptors are written before
5622                  * doorbell record.
5623                  */
5624                 wmb();
5625
5626                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5627         }
5628
5629         spin_unlock_irqrestore(&qp->rq.lock, flags);
5630
5631         return err;
5632 }
5633
5634 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5635                       const struct ib_recv_wr **bad_wr)
5636 {
5637         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5638 }
5639
5640 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5641 {
5642         switch (mlx5_state) {
5643         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5644         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5645         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5646         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5647         case MLX5_QP_STATE_SQ_DRAINING:
5648         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5649         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5650         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5651         default:                     return -1;
5652         }
5653 }
5654
5655 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5656 {
5657         switch (mlx5_mig_state) {
5658         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5659         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5660         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5661         default: return -1;
5662         }
5663 }
5664
5665 static int to_ib_qp_access_flags(int mlx5_flags)
5666 {
5667         int ib_flags = 0;
5668
5669         if (mlx5_flags & MLX5_QP_BIT_RRE)
5670                 ib_flags |= IB_ACCESS_REMOTE_READ;
5671         if (mlx5_flags & MLX5_QP_BIT_RWE)
5672                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5673         if (mlx5_flags & MLX5_QP_BIT_RAE)
5674                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5675
5676         return ib_flags;
5677 }
5678
5679 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5680                             struct rdma_ah_attr *ah_attr,
5681                             struct mlx5_qp_path *path)
5682 {
5683
5684         memset(ah_attr, 0, sizeof(*ah_attr));
5685
5686         if (!path->port || path->port > ibdev->num_ports)
5687                 return;
5688
5689         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5690
5691         rdma_ah_set_port_num(ah_attr, path->port);
5692         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5693
5694         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5695         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5696         rdma_ah_set_static_rate(ah_attr,
5697                                 path->static_rate ? path->static_rate - 5 : 0);
5698         if (path->grh_mlid & (1 << 7)) {
5699                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5700
5701                 rdma_ah_set_grh(ah_attr, NULL,
5702                                 tc_fl & 0xfffff,
5703                                 path->mgid_index,
5704                                 path->hop_limit,
5705                                 (tc_fl >> 20) & 0xff);
5706                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5707         }
5708 }
5709
5710 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5711                                         struct mlx5_ib_sq *sq,
5712                                         u8 *sq_state)
5713 {
5714         int err;
5715
5716         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5717         if (err)
5718                 goto out;
5719         sq->state = *sq_state;
5720
5721 out:
5722         return err;
5723 }
5724
5725 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5726                                         struct mlx5_ib_rq *rq,
5727                                         u8 *rq_state)
5728 {
5729         void *out;
5730         void *rqc;
5731         int inlen;
5732         int err;
5733
5734         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5735         out = kvzalloc(inlen, GFP_KERNEL);
5736         if (!out)
5737                 return -ENOMEM;
5738
5739         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5740         if (err)
5741                 goto out;
5742
5743         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5744         *rq_state = MLX5_GET(rqc, rqc, state);
5745         rq->state = *rq_state;
5746
5747 out:
5748         kvfree(out);
5749         return err;
5750 }
5751
5752 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5753                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5754 {
5755         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5756                 [MLX5_RQC_STATE_RST] = {
5757                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5758                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5759                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5760                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5761                 },
5762                 [MLX5_RQC_STATE_RDY] = {
5763                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5764                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5765                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5766                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5767                 },
5768                 [MLX5_RQC_STATE_ERR] = {
5769                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5770                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5771                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5772                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5773                 },
5774                 [MLX5_RQ_STATE_NA] = {
5775                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5776                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5777                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5778                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5779                 },
5780         };
5781
5782         *qp_state = sqrq_trans[rq_state][sq_state];
5783
5784         if (*qp_state == MLX5_QP_STATE_BAD) {
5785                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5786                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5787                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5788                 return -EINVAL;
5789         }
5790
5791         if (*qp_state == MLX5_QP_STATE)
5792                 *qp_state = qp->state;
5793
5794         return 0;
5795 }
5796
5797 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5798                                      struct mlx5_ib_qp *qp,
5799                                      u8 *raw_packet_qp_state)
5800 {
5801         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5802         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5803         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5804         int err;
5805         u8 sq_state = MLX5_SQ_STATE_NA;
5806         u8 rq_state = MLX5_RQ_STATE_NA;
5807
5808         if (qp->sq.wqe_cnt) {
5809                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5810                 if (err)
5811                         return err;
5812         }
5813
5814         if (qp->rq.wqe_cnt) {
5815                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5816                 if (err)
5817                         return err;
5818         }
5819
5820         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5821                                       raw_packet_qp_state);
5822 }
5823
5824 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5825                          struct ib_qp_attr *qp_attr)
5826 {
5827         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5828         struct mlx5_qp_context *context;
5829         int mlx5_state;
5830         u32 *outb;
5831         int err = 0;
5832
5833         outb = kzalloc(outlen, GFP_KERNEL);
5834         if (!outb)
5835                 return -ENOMEM;
5836
5837         err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
5838         if (err)
5839                 goto out;
5840
5841         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5842         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5843
5844         mlx5_state = be32_to_cpu(context->flags) >> 28;
5845
5846         qp->state                    = to_ib_qp_state(mlx5_state);
5847         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5848         qp_attr->path_mig_state      =
5849                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5850         qp_attr->qkey                = be32_to_cpu(context->qkey);
5851         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5852         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5853         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5854         qp_attr->qp_access_flags     =
5855                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5856
5857         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5858                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5859                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5860                 qp_attr->alt_pkey_index =
5861                         be16_to_cpu(context->alt_path.pkey_index);
5862                 qp_attr->alt_port_num   =
5863                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5864         }
5865
5866         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5867         qp_attr->port_num = context->pri_path.port;
5868
5869         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5870         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5871
5872         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5873
5874         qp_attr->max_dest_rd_atomic =
5875                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5876         qp_attr->min_rnr_timer      =
5877                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5878         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5879         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5880         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5881         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5882
5883 out:
5884         kfree(outb);
5885         return err;
5886 }
5887
5888 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5889                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5890                                 struct ib_qp_init_attr *qp_init_attr)
5891 {
5892         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5893         u32 *out;
5894         u32 access_flags = 0;
5895         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5896         void *dctc;
5897         int err;
5898         int supported_mask = IB_QP_STATE |
5899                              IB_QP_ACCESS_FLAGS |
5900                              IB_QP_PORT |
5901                              IB_QP_MIN_RNR_TIMER |
5902                              IB_QP_AV |
5903                              IB_QP_PATH_MTU |
5904                              IB_QP_PKEY_INDEX;
5905
5906         if (qp_attr_mask & ~supported_mask)
5907                 return -EINVAL;
5908         if (mqp->state != IB_QPS_RTR)
5909                 return -EINVAL;
5910
5911         out = kzalloc(outlen, GFP_KERNEL);
5912         if (!out)
5913                 return -ENOMEM;
5914
5915         err = mlx5_core_dct_query(dev, dct, out, outlen);
5916         if (err)
5917                 goto out;
5918
5919         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5920
5921         if (qp_attr_mask & IB_QP_STATE)
5922                 qp_attr->qp_state = IB_QPS_RTR;
5923
5924         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5925                 if (MLX5_GET(dctc, dctc, rre))
5926                         access_flags |= IB_ACCESS_REMOTE_READ;
5927                 if (MLX5_GET(dctc, dctc, rwe))
5928                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5929                 if (MLX5_GET(dctc, dctc, rae))
5930                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5931                 qp_attr->qp_access_flags = access_flags;
5932         }
5933
5934         if (qp_attr_mask & IB_QP_PORT)
5935                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5936         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5937                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5938         if (qp_attr_mask & IB_QP_AV) {
5939                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5940                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5941                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5942                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5943         }
5944         if (qp_attr_mask & IB_QP_PATH_MTU)
5945                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5946         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5947                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5948 out:
5949         kfree(out);
5950         return err;
5951 }
5952
5953 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5954                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5955 {
5956         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5957         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5958         int err = 0;
5959         u8 raw_packet_qp_state;
5960
5961         if (ibqp->rwq_ind_tbl)
5962                 return -ENOSYS;
5963
5964         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5965                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5966                                             qp_init_attr);
5967
5968         /* Not all of output fields are applicable, make sure to zero them */
5969         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5970         memset(qp_attr, 0, sizeof(*qp_attr));
5971
5972         if (unlikely(qp->type == MLX5_IB_QPT_DCT))
5973                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5974                                             qp_attr_mask, qp_init_attr);
5975
5976         mutex_lock(&qp->mutex);
5977
5978         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5979             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
5980                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5981                 if (err)
5982                         goto out;
5983                 qp->state = raw_packet_qp_state;
5984                 qp_attr->port_num = 1;
5985         } else {
5986                 err = query_qp_attr(dev, qp, qp_attr);
5987                 if (err)
5988                         goto out;
5989         }
5990
5991         qp_attr->qp_state            = qp->state;
5992         qp_attr->cur_qp_state        = qp_attr->qp_state;
5993         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5994         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5995
5996         if (!ibqp->uobject) {
5997                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5998                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5999                 qp_init_attr->qp_context = ibqp->qp_context;
6000         } else {
6001                 qp_attr->cap.max_send_wr  = 0;
6002                 qp_attr->cap.max_send_sge = 0;
6003         }
6004
6005         qp_init_attr->qp_type = ibqp->qp_type;
6006         qp_init_attr->recv_cq = ibqp->recv_cq;
6007         qp_init_attr->send_cq = ibqp->send_cq;
6008         qp_init_attr->srq = ibqp->srq;
6009         qp_attr->cap.max_inline_data = qp->max_inline_data;
6010
6011         qp_init_attr->cap            = qp_attr->cap;
6012
6013         qp_init_attr->create_flags = qp->flags;
6014
6015         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
6016                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
6017
6018 out:
6019         mutex_unlock(&qp->mutex);
6020         return err;
6021 }
6022
6023 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
6024                                    struct ib_udata *udata)
6025 {
6026         struct mlx5_ib_dev *dev = to_mdev(ibdev);
6027         struct mlx5_ib_xrcd *xrcd;
6028         int err;
6029
6030         if (!MLX5_CAP_GEN(dev->mdev, xrc))
6031                 return ERR_PTR(-ENOSYS);
6032
6033         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
6034         if (!xrcd)
6035                 return ERR_PTR(-ENOMEM);
6036
6037         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
6038         if (err) {
6039                 kfree(xrcd);
6040                 return ERR_PTR(-ENOMEM);
6041         }
6042
6043         return &xrcd->ibxrcd;
6044 }
6045
6046 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
6047 {
6048         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
6049         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
6050         int err;
6051
6052         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
6053         if (err)
6054                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
6055
6056         kfree(xrcd);
6057         return 0;
6058 }
6059
6060 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
6061 {
6062         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
6063         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
6064         struct ib_event event;
6065
6066         if (rwq->ibwq.event_handler) {
6067                 event.device     = rwq->ibwq.device;
6068                 event.element.wq = &rwq->ibwq;
6069                 switch (type) {
6070                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
6071                         event.event = IB_EVENT_WQ_FATAL;
6072                         break;
6073                 default:
6074                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
6075                         return;
6076                 }
6077
6078                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
6079         }
6080 }
6081
6082 static int set_delay_drop(struct mlx5_ib_dev *dev)
6083 {
6084         int err = 0;
6085
6086         mutex_lock(&dev->delay_drop.lock);
6087         if (dev->delay_drop.activate)
6088                 goto out;
6089
6090         err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
6091         if (err)
6092                 goto out;
6093
6094         dev->delay_drop.activate = true;
6095 out:
6096         mutex_unlock(&dev->delay_drop.lock);
6097
6098         if (!err)
6099                 atomic_inc(&dev->delay_drop.rqs_cnt);
6100         return err;
6101 }
6102
6103 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
6104                       struct ib_wq_init_attr *init_attr)
6105 {
6106         struct mlx5_ib_dev *dev;
6107         int has_net_offloads;
6108         __be64 *rq_pas0;
6109         void *in;
6110         void *rqc;
6111         void *wq;
6112         int inlen;
6113         int err;
6114
6115         dev = to_mdev(pd->device);
6116
6117         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
6118         in = kvzalloc(inlen, GFP_KERNEL);
6119         if (!in)
6120                 return -ENOMEM;
6121
6122         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
6123         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
6124         MLX5_SET(rqc,  rqc, mem_rq_type,
6125                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
6126         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
6127         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
6128         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
6129         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
6130         wq = MLX5_ADDR_OF(rqc, rqc, wq);
6131         MLX5_SET(wq, wq, wq_type,
6132                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
6133                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
6134         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6135                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
6136                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
6137                         err = -EOPNOTSUPP;
6138                         goto out;
6139                 } else {
6140                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
6141                 }
6142         }
6143         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
6144         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
6145                 /*
6146                  * In Firmware number of strides in each WQE is:
6147                  *   "512 * 2^single_wqe_log_num_of_strides"
6148                  * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
6149                  * accepted as 0 to 9
6150                  */
6151                 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
6152                                              2,  3,  4,  5,  6,  7,  8, 9 };
6153                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
6154                 MLX5_SET(wq, wq, log_wqe_stride_size,
6155                          rwq->single_stride_log_num_of_bytes -
6156                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
6157                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
6158                          fw_map[rwq->log_num_strides -
6159                                 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
6160         }
6161         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
6162         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
6163         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
6164         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
6165         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
6166         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
6167         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
6168         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6169                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6170                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
6171                         err = -EOPNOTSUPP;
6172                         goto out;
6173                 }
6174         } else {
6175                 MLX5_SET(rqc, rqc, vsd, 1);
6176         }
6177         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
6178                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
6179                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
6180                         err = -EOPNOTSUPP;
6181                         goto out;
6182                 }
6183                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
6184         }
6185         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6186                 if (!(dev->ib_dev.attrs.raw_packet_caps &
6187                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
6188                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
6189                         err = -EOPNOTSUPP;
6190                         goto out;
6191                 }
6192                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
6193         }
6194         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
6195         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
6196         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
6197         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6198                 err = set_delay_drop(dev);
6199                 if (err) {
6200                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
6201                                      err);
6202                         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6203                 } else {
6204                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
6205                 }
6206         }
6207 out:
6208         kvfree(in);
6209         return err;
6210 }
6211
6212 static int set_user_rq_size(struct mlx5_ib_dev *dev,
6213                             struct ib_wq_init_attr *wq_init_attr,
6214                             struct mlx5_ib_create_wq *ucmd,
6215                             struct mlx5_ib_rwq *rwq)
6216 {
6217         /* Sanity check RQ size before proceeding */
6218         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
6219                 return -EINVAL;
6220
6221         if (!ucmd->rq_wqe_count)
6222                 return -EINVAL;
6223
6224         rwq->wqe_count = ucmd->rq_wqe_count;
6225         rwq->wqe_shift = ucmd->rq_wqe_shift;
6226         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
6227                 return -EINVAL;
6228
6229         rwq->log_rq_stride = rwq->wqe_shift;
6230         rwq->log_rq_size = ilog2(rwq->wqe_count);
6231         return 0;
6232 }
6233
6234 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
6235 {
6236         if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
6237             (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
6238                 return false;
6239
6240         if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
6241             (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
6242                 return false;
6243
6244         return true;
6245 }
6246
6247 static int prepare_user_rq(struct ib_pd *pd,
6248                            struct ib_wq_init_attr *init_attr,
6249                            struct ib_udata *udata,
6250                            struct mlx5_ib_rwq *rwq)
6251 {
6252         struct mlx5_ib_dev *dev = to_mdev(pd->device);
6253         struct mlx5_ib_create_wq ucmd = {};
6254         int err;
6255         size_t required_cmd_sz;
6256
6257         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
6258                 + sizeof(ucmd.single_stride_log_num_of_bytes);
6259         if (udata->inlen < required_cmd_sz) {
6260                 mlx5_ib_dbg(dev, "invalid inlen\n");
6261                 return -EINVAL;
6262         }
6263
6264         if (udata->inlen > sizeof(ucmd) &&
6265             !ib_is_udata_cleared(udata, sizeof(ucmd),
6266                                  udata->inlen - sizeof(ucmd))) {
6267                 mlx5_ib_dbg(dev, "inlen is not supported\n");
6268                 return -EOPNOTSUPP;
6269         }
6270
6271         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
6272                 mlx5_ib_dbg(dev, "copy failed\n");
6273                 return -EFAULT;
6274         }
6275
6276         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
6277                 mlx5_ib_dbg(dev, "invalid comp mask\n");
6278                 return -EOPNOTSUPP;
6279         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
6280                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
6281                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
6282                         return -EOPNOTSUPP;
6283                 }
6284                 if ((ucmd.single_stride_log_num_of_bytes <
6285                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
6286                     (ucmd.single_stride_log_num_of_bytes >
6287                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
6288                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
6289                                     ucmd.single_stride_log_num_of_bytes,
6290                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
6291                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
6292                         return -EINVAL;
6293                 }
6294                 if (!log_of_strides_valid(dev,
6295                                           ucmd.single_wqe_log_num_of_strides)) {
6296                         mlx5_ib_dbg(
6297                                 dev,
6298                                 "Invalid log num strides (%u. Range is %u - %u)\n",
6299                                 ucmd.single_wqe_log_num_of_strides,
6300                                 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
6301                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
6302                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
6303                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
6304                         return -EINVAL;
6305                 }
6306                 rwq->single_stride_log_num_of_bytes =
6307                         ucmd.single_stride_log_num_of_bytes;
6308                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
6309                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
6310                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
6311         }
6312
6313         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
6314         if (err) {
6315                 mlx5_ib_dbg(dev, "err %d\n", err);
6316                 return err;
6317         }
6318
6319         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
6320         if (err) {
6321                 mlx5_ib_dbg(dev, "err %d\n", err);
6322                 return err;
6323         }
6324
6325         rwq->user_index = ucmd.user_index;
6326         return 0;
6327 }
6328
6329 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
6330                                 struct ib_wq_init_attr *init_attr,
6331                                 struct ib_udata *udata)
6332 {
6333         struct mlx5_ib_dev *dev;
6334         struct mlx5_ib_rwq *rwq;
6335         struct mlx5_ib_create_wq_resp resp = {};
6336         size_t min_resp_len;
6337         int err;
6338
6339         if (!udata)
6340                 return ERR_PTR(-ENOSYS);
6341
6342         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6343         if (udata->outlen && udata->outlen < min_resp_len)
6344                 return ERR_PTR(-EINVAL);
6345
6346         if (!capable(CAP_SYS_RAWIO) &&
6347             init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
6348                 return ERR_PTR(-EPERM);
6349
6350         dev = to_mdev(pd->device);
6351         switch (init_attr->wq_type) {
6352         case IB_WQT_RQ:
6353                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
6354                 if (!rwq)
6355                         return ERR_PTR(-ENOMEM);
6356                 err = prepare_user_rq(pd, init_attr, udata, rwq);
6357                 if (err)
6358                         goto err;
6359                 err = create_rq(rwq, pd, init_attr);
6360                 if (err)
6361                         goto err_user_rq;
6362                 break;
6363         default:
6364                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
6365                             init_attr->wq_type);
6366                 return ERR_PTR(-EINVAL);
6367         }
6368
6369         rwq->ibwq.wq_num = rwq->core_qp.qpn;
6370         rwq->ibwq.state = IB_WQS_RESET;
6371         if (udata->outlen) {
6372                 resp.response_length = offsetof(typeof(resp), response_length) +
6373                                 sizeof(resp.response_length);
6374                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6375                 if (err)
6376                         goto err_copy;
6377         }
6378
6379         rwq->core_qp.event = mlx5_ib_wq_event;
6380         rwq->ibwq.event_handler = init_attr->event_handler;
6381         return &rwq->ibwq;
6382
6383 err_copy:
6384         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6385 err_user_rq:
6386         destroy_user_rq(dev, pd, rwq, udata);
6387 err:
6388         kfree(rwq);
6389         return ERR_PTR(err);
6390 }
6391
6392 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
6393 {
6394         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6395         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6396
6397         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6398         destroy_user_rq(dev, wq->pd, rwq, udata);
6399         kfree(rwq);
6400 }
6401
6402 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
6403                                                       struct ib_rwq_ind_table_init_attr *init_attr,
6404                                                       struct ib_udata *udata)
6405 {
6406         struct mlx5_ib_dev *dev = to_mdev(device);
6407         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
6408         int sz = 1 << init_attr->log_ind_tbl_size;
6409         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
6410         size_t min_resp_len;
6411         int inlen;
6412         int err;
6413         int i;
6414         u32 *in;
6415         void *rqtc;
6416
6417         if (udata->inlen > 0 &&
6418             !ib_is_udata_cleared(udata, 0,
6419                                  udata->inlen))
6420                 return ERR_PTR(-EOPNOTSUPP);
6421
6422         if (init_attr->log_ind_tbl_size >
6423             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
6424                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
6425                             init_attr->log_ind_tbl_size,
6426                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
6427                 return ERR_PTR(-EINVAL);
6428         }
6429
6430         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6431         if (udata->outlen && udata->outlen < min_resp_len)
6432                 return ERR_PTR(-EINVAL);
6433
6434         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6435         if (!rwq_ind_tbl)
6436                 return ERR_PTR(-ENOMEM);
6437
6438         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
6439         in = kvzalloc(inlen, GFP_KERNEL);
6440         if (!in) {
6441                 err = -ENOMEM;
6442                 goto err;
6443         }
6444
6445         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6446
6447         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6448         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6449
6450         for (i = 0; i < sz; i++)
6451                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6452
6453         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6454         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6455
6456         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6457         kvfree(in);
6458
6459         if (err)
6460                 goto err;
6461
6462         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6463         if (udata->outlen) {
6464                 resp.response_length = offsetof(typeof(resp), response_length) +
6465                                         sizeof(resp.response_length);
6466                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6467                 if (err)
6468                         goto err_copy;
6469         }
6470
6471         return &rwq_ind_tbl->ib_rwq_ind_tbl;
6472
6473 err_copy:
6474         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6475 err:
6476         kfree(rwq_ind_tbl);
6477         return ERR_PTR(err);
6478 }
6479
6480 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6481 {
6482         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6483         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6484
6485         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6486
6487         kfree(rwq_ind_tbl);
6488         return 0;
6489 }
6490
6491 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6492                       u32 wq_attr_mask, struct ib_udata *udata)
6493 {
6494         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6495         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6496         struct mlx5_ib_modify_wq ucmd = {};
6497         size_t required_cmd_sz;
6498         int curr_wq_state;
6499         int wq_state;
6500         int inlen;
6501         int err;
6502         void *rqc;
6503         void *in;
6504
6505         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6506         if (udata->inlen < required_cmd_sz)
6507                 return -EINVAL;
6508
6509         if (udata->inlen > sizeof(ucmd) &&
6510             !ib_is_udata_cleared(udata, sizeof(ucmd),
6511                                  udata->inlen - sizeof(ucmd)))
6512                 return -EOPNOTSUPP;
6513
6514         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6515                 return -EFAULT;
6516
6517         if (ucmd.comp_mask || ucmd.reserved)
6518                 return -EOPNOTSUPP;
6519
6520         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
6521         in = kvzalloc(inlen, GFP_KERNEL);
6522         if (!in)
6523                 return -ENOMEM;
6524
6525         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6526
6527         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6528                 wq_attr->curr_wq_state : wq->state;
6529         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6530                 wq_attr->wq_state : curr_wq_state;
6531         if (curr_wq_state == IB_WQS_ERR)
6532                 curr_wq_state = MLX5_RQC_STATE_ERR;
6533         if (wq_state == IB_WQS_ERR)
6534                 wq_state = MLX5_RQC_STATE_ERR;
6535         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6536         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6537         MLX5_SET(rqc, rqc, state, wq_state);
6538
6539         if (wq_attr_mask & IB_WQ_FLAGS) {
6540                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6541                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6542                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6543                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
6544                                             "supported\n");
6545                                 err = -EOPNOTSUPP;
6546                                 goto out;
6547                         }
6548                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6549                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6550                         MLX5_SET(rqc, rqc, vsd,
6551                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6552                 }
6553
6554                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6555                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6556                         err = -EOPNOTSUPP;
6557                         goto out;
6558                 }
6559         }
6560
6561         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6562                 u16 set_id;
6563
6564                 set_id = mlx5_ib_get_counters_id(dev, 0);
6565                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6566                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6567                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6568                         MLX5_SET(rqc, rqc, counter_set_id, set_id);
6569                 } else
6570                         dev_info_once(
6571                                 &dev->ib_dev.dev,
6572                                 "Receive WQ counters are not supported on current FW\n");
6573         }
6574
6575         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
6576         if (!err)
6577                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6578
6579 out:
6580         kvfree(in);
6581         return err;
6582 }
6583
6584 struct mlx5_ib_drain_cqe {
6585         struct ib_cqe cqe;
6586         struct completion done;
6587 };
6588
6589 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6590 {
6591         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6592                                                      struct mlx5_ib_drain_cqe,
6593                                                      cqe);
6594
6595         complete(&cqe->done);
6596 }
6597
6598 /* This function returns only once the drained WR was completed */
6599 static void handle_drain_completion(struct ib_cq *cq,
6600                                     struct mlx5_ib_drain_cqe *sdrain,
6601                                     struct mlx5_ib_dev *dev)
6602 {
6603         struct mlx5_core_dev *mdev = dev->mdev;
6604
6605         if (cq->poll_ctx == IB_POLL_DIRECT) {
6606                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6607                         ib_process_cq_direct(cq, -1);
6608                 return;
6609         }
6610
6611         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6612                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6613                 bool triggered = false;
6614                 unsigned long flags;
6615
6616                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6617                 /* Make sure that the CQ handler won't run if wasn't run yet */
6618                 if (!mcq->mcq.reset_notify_added)
6619                         mcq->mcq.reset_notify_added = 1;
6620                 else
6621                         triggered = true;
6622                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6623
6624                 if (triggered) {
6625                         /* Wait for any scheduled/running task to be ended */
6626                         switch (cq->poll_ctx) {
6627                         case IB_POLL_SOFTIRQ:
6628                                 irq_poll_disable(&cq->iop);
6629                                 irq_poll_enable(&cq->iop);
6630                                 break;
6631                         case IB_POLL_WORKQUEUE:
6632                                 cancel_work_sync(&cq->work);
6633                                 break;
6634                         default:
6635                                 WARN_ON_ONCE(1);
6636                         }
6637                 }
6638
6639                 /* Run the CQ handler - this makes sure that the drain WR will
6640                  * be processed if wasn't processed yet.
6641                  */
6642                 mcq->mcq.comp(&mcq->mcq, NULL);
6643         }
6644
6645         wait_for_completion(&sdrain->done);
6646 }
6647
6648 void mlx5_ib_drain_sq(struct ib_qp *qp)
6649 {
6650         struct ib_cq *cq = qp->send_cq;
6651         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6652         struct mlx5_ib_drain_cqe sdrain;
6653         const struct ib_send_wr *bad_swr;
6654         struct ib_rdma_wr swr = {
6655                 .wr = {
6656                         .next = NULL,
6657                         { .wr_cqe       = &sdrain.cqe, },
6658                         .opcode = IB_WR_RDMA_WRITE,
6659                 },
6660         };
6661         int ret;
6662         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6663         struct mlx5_core_dev *mdev = dev->mdev;
6664
6665         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6666         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6667                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6668                 return;
6669         }
6670
6671         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6672         init_completion(&sdrain.done);
6673
6674         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6675         if (ret) {
6676                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6677                 return;
6678         }
6679
6680         handle_drain_completion(cq, &sdrain, dev);
6681 }
6682
6683 void mlx5_ib_drain_rq(struct ib_qp *qp)
6684 {
6685         struct ib_cq *cq = qp->recv_cq;
6686         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6687         struct mlx5_ib_drain_cqe rdrain;
6688         struct ib_recv_wr rwr = {};
6689         const struct ib_recv_wr *bad_rwr;
6690         int ret;
6691         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6692         struct mlx5_core_dev *mdev = dev->mdev;
6693
6694         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6695         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6696                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6697                 return;
6698         }
6699
6700         rwr.wr_cqe = &rdrain.cqe;
6701         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6702         init_completion(&rdrain.done);
6703
6704         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6705         if (ret) {
6706                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6707                 return;
6708         }
6709
6710         handle_drain_completion(cq, &rdrain, dev);
6711 }
6712
6713 /**
6714  * Bind a qp to a counter. If @counter is NULL then bind the qp to
6715  * the default counter
6716  */
6717 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
6718 {
6719         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6720         struct mlx5_ib_qp *mqp = to_mqp(qp);
6721         int err = 0;
6722
6723         mutex_lock(&mqp->mutex);
6724         if (mqp->state == IB_QPS_RESET) {
6725                 qp->counter = counter;
6726                 goto out;
6727         }
6728
6729         if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
6730                 err = -EOPNOTSUPP;
6731                 goto out;
6732         }
6733
6734         if (mqp->state == IB_QPS_RTS) {
6735                 err = __mlx5_ib_qp_set_counter(qp, counter);
6736                 if (!err)
6737                         qp->counter = counter;
6738
6739                 goto out;
6740         }
6741
6742         mqp->counter_pending = 1;
6743         qp->counter = counter;
6744
6745 out:
6746         mutex_unlock(&mqp->mutex);
6747         return err;
6748 }