drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <rdma/rdma_counter.h>
  38 #include <linux/mlx5/fs.h>
  39 #include "mlx5_ib.h"
  40 #include "ib_rep.h"
  41 #include "cmd.h"
  42 #include "qp.h"
  43 #include "wr.h"
  44
  45 enum {
  46         MLX5_IB_ACK_REQ_FREQ    = 8,
  47 };
  48
  49 enum {
  50         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  51         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  52         MLX5_IB_LINK_TYPE_IB            = 0,
  53         MLX5_IB_LINK_TYPE_ETH           = 1
  54 };
  55
  56 enum raw_qp_set_mask_map {
  57         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  58         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  59 };
  60
  61 struct mlx5_modify_raw_qp_param {
  62         u16 operation;
  63
  64         u32 set_mask; /* raw_qp_set_mask_map */
  65
  66         struct mlx5_rate_limit rl;
  67
  68         u8 rq_q_ctr_id;
  69         u16 port;
  70 };
  71
  72 static void get_cqs(enum ib_qp_type qp_type,
  73                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  74                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  75
  76 static int is_qp0(enum ib_qp_type qp_type)
  77 {
  78         return qp_type == IB_QPT_SMI;
  79 }
  80
  81 static int is_sqp(enum ib_qp_type qp_type)
  82 {
  83         return is_qp0(qp_type) || is_qp1(qp_type);
  84 }
  85
  86 /**
  87  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
  88  * to kernel buffer
  89  *
  90  * @umem: User space memory where the WQ is
  91  * @buffer: buffer to copy to
  92  * @buflen: buffer length
  93  * @wqe_index: index of WQE to copy from
  94  * @wq_offset: offset to start of WQ
  95  * @wq_wqe_cnt: number of WQEs in WQ
  96  * @wq_wqe_shift: log2 of WQE size
  97  * @bcnt: number of bytes to copy
  98  * @bytes_copied: number of bytes to copy (return value)
  99  *
 100  * Copies from start of WQE bcnt or less bytes.
 101  * Does not gurantee to copy the entire WQE.
 102  *
 103  * Return: zero on success, or an error code.
 104  */
 105 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
 106                                         size_t buflen, int wqe_index,
 107                                         int wq_offset, int wq_wqe_cnt,
 108                                         int wq_wqe_shift, int bcnt,
 109                                         size_t *bytes_copied)
 110 {
 111         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 112         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 113         size_t copy_length;
 114         int ret;
 115
 116         /* don't copy more than requested, more than buffer length or
 117          * beyond WQ end
 118          */
 119         copy_length = min_t(u32, buflen, wq_end - offset);
 120         copy_length = min_t(u32, copy_length, bcnt);
 121
 122         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 123         if (ret)
 124                 return ret;
 125
 126         if (!ret && bytes_copied)
 127                 *bytes_copied = copy_length;
 128
 129         return 0;
 130 }
 131
 132 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 133                                       void *buffer, size_t buflen, size_t *bc)
 134 {
 135         struct mlx5_wqe_ctrl_seg *ctrl;
 136         size_t bytes_copied = 0;
 137         size_t wqe_length;
 138         void *p;
 139         int ds;
 140
 141         wqe_index = wqe_index & qp->sq.fbc.sz_m1;
 142
 143         /* read the control segment first */
 144         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 145         ctrl = p;
 146         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 147         wqe_length = ds * MLX5_WQE_DS_UNITS;
 148
 149         /* read rest of WQE if it spreads over more than one stride */
 150         while (bytes_copied < wqe_length) {
 151                 size_t copy_length =
 152                         min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
 153
 154                 if (!copy_length)
 155                         break;
 156
 157                 memcpy(buffer + bytes_copied, p, copy_length);
 158                 bytes_copied += copy_length;
 159
 160                 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
 161                 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 162         }
 163         *bc = bytes_copied;
 164         return 0;
 165 }
 166
 167 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 168                                     void *buffer, size_t buflen, size_t *bc)
 169 {
 170         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 171         struct ib_umem *umem = base->ubuffer.umem;
 172         struct mlx5_ib_wq *wq = &qp->sq;
 173         struct mlx5_wqe_ctrl_seg *ctrl;
 174         size_t bytes_copied;
 175         size_t bytes_copied2;
 176         size_t wqe_length;
 177         int ret;
 178         int ds;
 179
 180         /* at first read as much as possible */
 181         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 182                                            wq->offset, wq->wqe_cnt,
 183                                            wq->wqe_shift, buflen,
 184                                            &bytes_copied);
 185         if (ret)
 186                 return ret;
 187
 188         /* we need at least control segment size to proceed */
 189         if (bytes_copied < sizeof(*ctrl))
 190                 return -EINVAL;
 191
 192         ctrl = buffer;
 193         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 194         wqe_length = ds * MLX5_WQE_DS_UNITS;
 195
 196         /* if we copied enough then we are done */
 197         if (bytes_copied >= wqe_length) {
 198                 *bc = bytes_copied;
 199                 return 0;
 200         }
 201
 202         /* otherwise this a wrapped around wqe
 203          * so read the remaining bytes starting
 204          * from  wqe_index 0
 205          */
 206         ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
 207                                            buflen - bytes_copied, 0, wq->offset,
 208                                            wq->wqe_cnt, wq->wqe_shift,
 209                                            wqe_length - bytes_copied,
 210                                            &bytes_copied2);
 211
 212         if (ret)
 213                 return ret;
 214         *bc = bytes_copied + bytes_copied2;
 215         return 0;
 216 }
 217
 218 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 219                         size_t buflen, size_t *bc)
 220 {
 221         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 222         struct ib_umem *umem = base->ubuffer.umem;
 223
 224         if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
 225                 return -EINVAL;
 226
 227         if (!umem)
 228                 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
 229                                                   buflen, bc);
 230
 231         return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
 232 }
 233
 234 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
 235                                     void *buffer, size_t buflen, size_t *bc)
 236 {
 237         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 238         struct ib_umem *umem = base->ubuffer.umem;
 239         struct mlx5_ib_wq *wq = &qp->rq;
 240         size_t bytes_copied;
 241         int ret;
 242
 243         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 244                                            wq->offset, wq->wqe_cnt,
 245                                            wq->wqe_shift, buflen,
 246                                            &bytes_copied);
 247
 248         if (ret)
 249                 return ret;
 250         *bc = bytes_copied;
 251         return 0;
 252 }
 253
 254 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 255                         size_t buflen, size_t *bc)
 256 {
 257         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 258         struct ib_umem *umem = base->ubuffer.umem;
 259         struct mlx5_ib_wq *wq = &qp->rq;
 260         size_t wqe_size = 1 << wq->wqe_shift;
 261
 262         if (buflen < wqe_size)
 263                 return -EINVAL;
 264
 265         if (!umem)
 266                 return -EOPNOTSUPP;
 267
 268         return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
 269 }
 270
 271 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
 272                                      void *buffer, size_t buflen, size_t *bc)
 273 {
 274         struct ib_umem *umem = srq->umem;
 275         size_t bytes_copied;
 276         int ret;
 277
 278         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
 279                                            srq->msrq.max, srq->msrq.wqe_shift,
 280                                            buflen, &bytes_copied);
 281
 282         if (ret)
 283                 return ret;
 284         *bc = bytes_copied;
 285         return 0;
 286 }
 287
 288 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
 289                          size_t buflen, size_t *bc)
 290 {
 291         struct ib_umem *umem = srq->umem;
 292         size_t wqe_size = 1 << srq->msrq.wqe_shift;
 293
 294         if (buflen < wqe_size)
 295                 return -EINVAL;
 296
 297         if (!umem)
 298                 return -EOPNOTSUPP;
 299
 300         return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
 301 }
 302
 303 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 304 {
 305         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 306         struct ib_event event;
 307
 308         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 309                 /* This event is only valid for trans_qps */
 310                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 311         }
 312
 313         if (ibqp->event_handler) {
 314                 event.device     = ibqp->device;
 315                 event.element.qp = ibqp;
 316                 switch (type) {
 317                 case MLX5_EVENT_TYPE_PATH_MIG:
 318                         event.event = IB_EVENT_PATH_MIG;
 319                         break;
 320                 case MLX5_EVENT_TYPE_COMM_EST:
 321                         event.event = IB_EVENT_COMM_EST;
 322                         break;
 323                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 324                         event.event = IB_EVENT_SQ_DRAINED;
 325                         break;
 326                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 327                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 328                         break;
 329                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 330                         event.event = IB_EVENT_QP_FATAL;
 331                         break;
 332                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 333                         event.event = IB_EVENT_PATH_MIG_ERR;
 334                         break;
 335                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 336                         event.event = IB_EVENT_QP_REQ_ERR;
 337                         break;
 338                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 339                         event.event = IB_EVENT_QP_ACCESS_ERR;
 340                         break;
 341                 default:
 342                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 343                         return;
 344                 }
 345
 346                 ibqp->event_handler(&event, ibqp->qp_context);
 347         }
 348 }
 349
 350 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 351                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 352 {
 353         int wqe_size;
 354         int wq_size;
 355
 356         /* Sanity check RQ size before proceeding */
 357         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 358                 return -EINVAL;
 359
 360         if (!has_rq) {
 361                 qp->rq.max_gs = 0;
 362                 qp->rq.wqe_cnt = 0;
 363                 qp->rq.wqe_shift = 0;
 364                 cap->max_recv_wr = 0;
 365                 cap->max_recv_sge = 0;
 366         } else {
 367                 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
 368
 369                 if (ucmd) {
 370                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 371                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 372                                 return -EINVAL;
 373                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 374                         if ((1 << qp->rq.wqe_shift) /
 375                                     sizeof(struct mlx5_wqe_data_seg) <
 376                             wq_sig)
 377                                 return -EINVAL;
 378                         qp->rq.max_gs =
 379                                 (1 << qp->rq.wqe_shift) /
 380                                         sizeof(struct mlx5_wqe_data_seg) -
 381                                 wq_sig;
 382                         qp->rq.max_post = qp->rq.wqe_cnt;
 383                 } else {
 384                         wqe_size =
 385                                 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
 386                                          0;
 387                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 388                         wqe_size = roundup_pow_of_two(wqe_size);
 389                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 390                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 391                         qp->rq.wqe_cnt = wq_size / wqe_size;
 392                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 393                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 394                                             wqe_size,
 395                                             MLX5_CAP_GEN(dev->mdev,
 396                                                          max_wqe_sz_rq));
 397                                 return -EINVAL;
 398                         }
 399                         qp->rq.wqe_shift = ilog2(wqe_size);
 400                         qp->rq.max_gs =
 401                                 (1 << qp->rq.wqe_shift) /
 402                                         sizeof(struct mlx5_wqe_data_seg) -
 403                                 wq_sig;
 404                         qp->rq.max_post = qp->rq.wqe_cnt;
 405                 }
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int sq_overhead(struct ib_qp_init_attr *attr)
 412 {
 413         int size = 0;
 414
 415         switch (attr->qp_type) {
 416         case IB_QPT_XRC_INI:
 417                 size += sizeof(struct mlx5_wqe_xrc_seg);
 418                 /* fall through */
 419         case IB_QPT_RC:
 420                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 421                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 422                             sizeof(struct mlx5_wqe_raddr_seg),
 423                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 424                             sizeof(struct mlx5_mkey_seg) +
 425                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 426                             MLX5_IB_UMR_OCTOWORD);
 427                 break;
 428
 429         case IB_QPT_XRC_TGT:
 430                 return 0;
 431
 432         case IB_QPT_UC:
 433                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 434                         max(sizeof(struct mlx5_wqe_raddr_seg),
 435                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 436                             sizeof(struct mlx5_mkey_seg));
 437                 break;
 438
 439         case IB_QPT_UD:
 440                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 441                         size += sizeof(struct mlx5_wqe_eth_pad) +
 442                                 sizeof(struct mlx5_wqe_eth_seg);
 443                 /* fall through */
 444         case IB_QPT_SMI:
 445         case MLX5_IB_QPT_HW_GSI:
 446                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 447                         sizeof(struct mlx5_wqe_datagram_seg);
 448                 break;
 449
 450         case MLX5_IB_QPT_REG_UMR:
 451                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 452                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 453                         sizeof(struct mlx5_mkey_seg);
 454                 break;
 455
 456         default:
 457                 return -EINVAL;
 458         }
 459
 460         return size;
 461 }
 462
 463 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 464 {
 465         int inl_size = 0;
 466         int size;
 467
 468         size = sq_overhead(attr);
 469         if (size < 0)
 470                 return size;
 471
 472         if (attr->cap.max_inline_data) {
 473                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 474                         attr->cap.max_inline_data;
 475         }
 476
 477         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 478         if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
 479             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 480                 return MLX5_SIG_WQE_SIZE;
 481         else
 482                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 483 }
 484
 485 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 486 {
 487         int max_sge;
 488
 489         if (attr->qp_type == IB_QPT_RC)
 490                 max_sge = (min_t(int, wqe_size, 512) -
 491                            sizeof(struct mlx5_wqe_ctrl_seg) -
 492                            sizeof(struct mlx5_wqe_raddr_seg)) /
 493                         sizeof(struct mlx5_wqe_data_seg);
 494         else if (attr->qp_type == IB_QPT_XRC_INI)
 495                 max_sge = (min_t(int, wqe_size, 512) -
 496                            sizeof(struct mlx5_wqe_ctrl_seg) -
 497                            sizeof(struct mlx5_wqe_xrc_seg) -
 498                            sizeof(struct mlx5_wqe_raddr_seg)) /
 499                         sizeof(struct mlx5_wqe_data_seg);
 500         else
 501                 max_sge = (wqe_size - sq_overhead(attr)) /
 502                         sizeof(struct mlx5_wqe_data_seg);
 503
 504         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 505                      sizeof(struct mlx5_wqe_data_seg));
 506 }
 507
 508 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 509                         struct mlx5_ib_qp *qp)
 510 {
 511         int wqe_size;
 512         int wq_size;
 513
 514         if (!attr->cap.max_send_wr)
 515                 return 0;
 516
 517         wqe_size = calc_send_wqe(attr);
 518         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 519         if (wqe_size < 0)
 520                 return wqe_size;
 521
 522         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 523                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 524                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 525                 return -EINVAL;
 526         }
 527
 528         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 529                               sizeof(struct mlx5_wqe_inline_seg);
 530         attr->cap.max_inline_data = qp->max_inline_data;
 531
 532         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 533         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 534         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 535                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 536                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 537                             qp->sq.wqe_cnt,
 538                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 539                 return -ENOMEM;
 540         }
 541         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 542         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 543         if (qp->sq.max_gs < attr->cap.max_send_sge)
 544                 return -ENOMEM;
 545
 546         attr->cap.max_send_sge = qp->sq.max_gs;
 547         qp->sq.max_post = wq_size / wqe_size;
 548         attr->cap.max_send_wr = qp->sq.max_post;
 549
 550         return wq_size;
 551 }
 552
 553 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 554                             struct mlx5_ib_qp *qp,
 555                             struct mlx5_ib_create_qp *ucmd,
 556                             struct mlx5_ib_qp_base *base,
 557                             struct ib_qp_init_attr *attr)
 558 {
 559         int desc_sz = 1 << qp->sq.wqe_shift;
 560
 561         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 562                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 563                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 564                 return -EINVAL;
 565         }
 566
 567         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 568                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 569                              ucmd->sq_wqe_count);
 570                 return -EINVAL;
 571         }
 572
 573         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 574
 575         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 576                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 577                              qp->sq.wqe_cnt,
 578                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 579                 return -EINVAL;
 580         }
 581
 582         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 583             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
 584                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 585                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 586         } else {
 587                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 588                                          (qp->sq.wqe_cnt << 6);
 589         }
 590
 591         return 0;
 592 }
 593
 594 static int qp_has_rq(struct ib_qp_init_attr *attr)
 595 {
 596         if (attr->qp_type == IB_QPT_XRC_INI ||
 597             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 598             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 599             !attr->cap.max_recv_wr)
 600                 return 0;
 601
 602         return 1;
 603 }
 604
 605 enum {
 606         /* this is the first blue flame register in the array of bfregs assigned
 607          * to a processes. Since we do not use it for blue flame but rather
 608          * regular 64 bit doorbells, we do not need a lock for maintaiing
 609          * "odd/even" order
 610          */
 611         NUM_NON_BLUE_FLAME_BFREGS = 1,
 612 };
 613
 614 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 615 {
 616         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 617 }
 618
 619 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 620                          struct mlx5_bfreg_info *bfregi)
 621 {
 622         int n;
 623
 624         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 625             NUM_NON_BLUE_FLAME_BFREGS;
 626
 627         return n >= 0 ? n : 0;
 628 }
 629
 630 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 631                            struct mlx5_bfreg_info *bfregi)
 632 {
 633         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 634 }
 635
 636 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 637                           struct mlx5_bfreg_info *bfregi)
 638 {
 639         int med;
 640
 641         med = num_med_bfreg(dev, bfregi);
 642         return ++med;
 643 }
 644
 645 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 646                                   struct mlx5_bfreg_info *bfregi)
 647 {
 648         int i;
 649
 650         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 651                 if (!bfregi->count[i]) {
 652                         bfregi->count[i]++;
 653                         return i;
 654                 }
 655         }
 656
 657         return -ENOMEM;
 658 }
 659
 660 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 661                                  struct mlx5_bfreg_info *bfregi)
 662 {
 663         int minidx = first_med_bfreg(dev, bfregi);
 664         int i;
 665
 666         if (minidx < 0)
 667                 return minidx;
 668
 669         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 670                 if (bfregi->count[i] < bfregi->count[minidx])
 671                         minidx = i;
 672                 if (!bfregi->count[minidx])
 673                         break;
 674         }
 675
 676         bfregi->count[minidx]++;
 677         return minidx;
 678 }
 679
 680 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 681                        struct mlx5_bfreg_info *bfregi)
 682 {
 683         int bfregn = -ENOMEM;
 684
 685         if (bfregi->lib_uar_dyn)
 686                 return -EINVAL;
 687
 688         mutex_lock(&bfregi->lock);
 689         if (bfregi->ver >= 2) {
 690                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 691                 if (bfregn < 0)
 692                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 693         }
 694
 695         if (bfregn < 0) {
 696                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 697                 bfregn = 0;
 698                 bfregi->count[bfregn]++;
 699         }
 700         mutex_unlock(&bfregi->lock);
 701
 702         return bfregn;
 703 }
 704
 705 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 706 {
 707         mutex_lock(&bfregi->lock);
 708         bfregi->count[bfregn]--;
 709         mutex_unlock(&bfregi->lock);
 710 }
 711
 712 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 713 {
 714         switch (state) {
 715         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 716         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 717         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 718         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 719         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 720         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 721         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 722         default:                return -1;
 723         }
 724 }
 725
 726 static int to_mlx5_st(enum ib_qp_type type)
 727 {
 728         switch (type) {
 729         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 730         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 731         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 732         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 733         case IB_QPT_XRC_INI:
 734         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 735         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 736         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 737         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 738         case IB_QPT_RAW_PACKET:         return MLX5_QP_ST_RAW_ETHERTYPE;
 739         default:                return -EINVAL;
 740         }
 741 }
 742
 743 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 744                              struct mlx5_ib_cq *recv_cq);
 745 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 746                                struct mlx5_ib_cq *recv_cq);
 747
 748 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 749                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 750                         bool dyn_bfreg)
 751 {
 752         unsigned int bfregs_per_sys_page;
 753         u32 index_of_sys_page;
 754         u32 offset;
 755
 756         if (bfregi->lib_uar_dyn)
 757                 return -EINVAL;
 758
 759         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 760                                 MLX5_NON_FP_BFREGS_PER_UAR;
 761         index_of_sys_page = bfregn / bfregs_per_sys_page;
 762
 763         if (dyn_bfreg) {
 764                 index_of_sys_page += bfregi->num_static_sys_pages;
 765
 766                 if (index_of_sys_page >= bfregi->num_sys_pages)
 767                         return -EINVAL;
 768
 769                 if (bfregn > bfregi->num_dyn_bfregs ||
 770                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 771                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 772                         return -EINVAL;
 773                 }
 774         }
 775
 776         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 777         return bfregi->sys_pages[index_of_sys_page] + offset;
 778 }
 779
 780 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 781                             unsigned long addr, size_t size,
 782                             struct ib_umem **umem, int *npages, int *page_shift,
 783                             int *ncont, u32 *offset)
 784 {
 785         int err;
 786
 787         *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
 788         if (IS_ERR(*umem)) {
 789                 mlx5_ib_dbg(dev, "umem_get failed\n");
 790                 return PTR_ERR(*umem);
 791         }
 792
 793         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 794
 795         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 796         if (err) {
 797                 mlx5_ib_warn(dev, "bad offset\n");
 798                 goto err_umem;
 799         }
 800
 801         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 802                     addr, size, *npages, *page_shift, *ncont, *offset);
 803
 804         return 0;
 805
 806 err_umem:
 807         ib_umem_release(*umem);
 808         *umem = NULL;
 809
 810         return err;
 811 }
 812
 813 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 814                             struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
 815 {
 816         struct mlx5_ib_ucontext *context =
 817                 rdma_udata_to_drv_context(
 818                         udata,
 819                         struct mlx5_ib_ucontext,
 820                         ibucontext);
 821
 822         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 823                 atomic_dec(&dev->delay_drop.rqs_cnt);
 824
 825         mlx5_ib_db_unmap_user(context, &rwq->db);
 826         ib_umem_release(rwq->umem);
 827 }
 828
 829 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 830                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 831                           struct mlx5_ib_create_wq *ucmd)
 832 {
 833         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
 834                 udata, struct mlx5_ib_ucontext, ibucontext);
 835         int page_shift = 0;
 836         int npages;
 837         u32 offset = 0;
 838         int ncont = 0;
 839         int err;
 840
 841         if (!ucmd->buf_addr)
 842                 return -EINVAL;
 843
 844         rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
 845         if (IS_ERR(rwq->umem)) {
 846                 mlx5_ib_dbg(dev, "umem_get failed\n");
 847                 err = PTR_ERR(rwq->umem);
 848                 return err;
 849         }
 850
 851         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 852                            &ncont, NULL);
 853         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 854                                      &rwq->rq_page_offset);
 855         if (err) {
 856                 mlx5_ib_warn(dev, "bad offset\n");
 857                 goto err_umem;
 858         }
 859
 860         rwq->rq_num_pas = ncont;
 861         rwq->page_shift = page_shift;
 862         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 863         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 864
 865         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 866                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 867                     npages, page_shift, ncont, offset);
 868
 869         err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
 870         if (err) {
 871                 mlx5_ib_dbg(dev, "map failed\n");
 872                 goto err_umem;
 873         }
 874
 875         return 0;
 876
 877 err_umem:
 878         ib_umem_release(rwq->umem);
 879         return err;
 880 }
 881
 882 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 883                          struct mlx5_bfreg_info *bfregi, int bfregn)
 884 {
 885         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 886                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 887 }
 888
 889 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 890                            struct mlx5_ib_qp *qp, struct ib_udata *udata,
 891                            struct ib_qp_init_attr *attr, u32 **in,
 892                            struct mlx5_ib_create_qp_resp *resp, int *inlen,
 893                            struct mlx5_ib_qp_base *base,
 894                            struct mlx5_ib_create_qp *ucmd)
 895 {
 896         struct mlx5_ib_ucontext *context;
 897         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 898         int page_shift = 0;
 899         int uar_index = 0;
 900         int npages;
 901         u32 offset = 0;
 902         int bfregn;
 903         int ncont = 0;
 904         __be64 *pas;
 905         void *qpc;
 906         int err;
 907         u16 uid;
 908         u32 uar_flags;
 909
 910         context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
 911                                             ibucontext);
 912         uar_flags = qp->flags_en &
 913                     (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
 914         switch (uar_flags) {
 915         case MLX5_QP_FLAG_UAR_PAGE_INDEX:
 916                 uar_index = ucmd->bfreg_index;
 917                 bfregn = MLX5_IB_INVALID_BFREG;
 918                 break;
 919         case MLX5_QP_FLAG_BFREG_INDEX:
 920                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 921                                                 ucmd->bfreg_index, true);
 922                 if (uar_index < 0)
 923                         return uar_index;
 924                 bfregn = MLX5_IB_INVALID_BFREG;
 925                 break;
 926         case 0:
 927                 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
 928                         return -EINVAL;
 929                 bfregn = alloc_bfreg(dev, &context->bfregi);
 930                 if (bfregn < 0)
 931                         return bfregn;
 932                 break;
 933         default:
 934                 return -EINVAL;
 935         }
 936
 937         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 938         if (bfregn != MLX5_IB_INVALID_BFREG)
 939                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 940                                                 false);
 941
 942         qp->rq.offset = 0;
 943         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 944         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 945
 946         err = set_user_buf_size(dev, qp, ucmd, base, attr);
 947         if (err)
 948                 goto err_bfreg;
 949
 950         if (ucmd->buf_addr && ubuffer->buf_size) {
 951                 ubuffer->buf_addr = ucmd->buf_addr;
 952                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 953                                        ubuffer->buf_size, &ubuffer->umem,
 954                                        &npages, &page_shift, &ncont, &offset);
 955                 if (err)
 956                         goto err_bfreg;
 957         } else {
 958                 ubuffer->umem = NULL;
 959         }
 960
 961         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 962                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 963         *in = kvzalloc(*inlen, GFP_KERNEL);
 964         if (!*in) {
 965                 err = -ENOMEM;
 966                 goto err_umem;
 967         }
 968
 969         uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
 970         MLX5_SET(create_qp_in, *in, uid, uid);
 971         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 972         if (ubuffer->umem)
 973                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 974
 975         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 976
 977         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 978         MLX5_SET(qpc, qpc, page_offset, offset);
 979
 980         MLX5_SET(qpc, qpc, uar_page, uar_index);
 981         if (bfregn != MLX5_IB_INVALID_BFREG)
 982                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 983         else
 984                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 985         qp->bfregn = bfregn;
 986
 987         err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
 988         if (err) {
 989                 mlx5_ib_dbg(dev, "map failed\n");
 990                 goto err_free;
 991         }
 992
 993         return 0;
 994
 995 err_free:
 996         kvfree(*in);
 997
 998 err_umem:
 999         ib_umem_release(ubuffer->umem);
1000
1001 err_bfreg:
1002         if (bfregn != MLX5_IB_INVALID_BFREG)
1003                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
1004         return err;
1005 }
1006
1007 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1008                        struct mlx5_ib_qp_base *base, struct ib_udata *udata)
1009 {
1010         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1011                 udata, struct mlx5_ib_ucontext, ibucontext);
1012
1013         if (udata) {
1014                 /* User QP */
1015                 mlx5_ib_db_unmap_user(context, &qp->db);
1016                 ib_umem_release(base->ubuffer.umem);
1017
1018                 /*
1019                  * Free only the BFREGs which are handled by the kernel.
1020                  * BFREGs of UARs allocated dynamically are handled by user.
1021                  */
1022                 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1023                         mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1024                 return;
1025         }
1026
1027         /* Kernel QP */
1028         kvfree(qp->sq.wqe_head);
1029         kvfree(qp->sq.w_list);
1030         kvfree(qp->sq.wrid);
1031         kvfree(qp->sq.wr_data);
1032         kvfree(qp->rq.wrid);
1033         if (qp->db.db)
1034                 mlx5_db_free(dev->mdev, &qp->db);
1035         if (qp->buf.frags)
1036                 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1037 }
1038
1039 static int _create_kernel_qp(struct mlx5_ib_dev *dev,
1040                              struct ib_qp_init_attr *init_attr,
1041                              struct mlx5_ib_qp *qp, u32 **in, int *inlen,
1042                              struct mlx5_ib_qp_base *base)
1043 {
1044         int uar_index;
1045         void *qpc;
1046         int err;
1047
1048         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1049                 qp->bf.bfreg = &dev->fp_bfreg;
1050         else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
1051                 qp->bf.bfreg = &dev->wc_bfreg;
1052         else
1053                 qp->bf.bfreg = &dev->bfreg;
1054
1055         /* We need to divide by two since each register is comprised of
1056          * two buffers of identical size, namely odd and even
1057          */
1058         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1059         uar_index = qp->bf.bfreg->index;
1060
1061         err = calc_sq_size(dev, init_attr, qp);
1062         if (err < 0) {
1063                 mlx5_ib_dbg(dev, "err %d\n", err);
1064                 return err;
1065         }
1066
1067         qp->rq.offset = 0;
1068         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1069         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1070
1071         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1072                                        &qp->buf, dev->mdev->priv.numa_node);
1073         if (err) {
1074                 mlx5_ib_dbg(dev, "err %d\n", err);
1075                 return err;
1076         }
1077
1078         if (qp->rq.wqe_cnt)
1079                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1080                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1081
1082         if (qp->sq.wqe_cnt) {
1083                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1084                                         MLX5_SEND_WQE_BB;
1085                 mlx5_init_fbc_offset(qp->buf.frags +
1086                                      (qp->sq.offset / PAGE_SIZE),
1087                                      ilog2(MLX5_SEND_WQE_BB),
1088                                      ilog2(qp->sq.wqe_cnt),
1089                                      sq_strides_offset, &qp->sq.fbc);
1090
1091                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1092         }
1093
1094         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1095                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1096         *in = kvzalloc(*inlen, GFP_KERNEL);
1097         if (!*in) {
1098                 err = -ENOMEM;
1099                 goto err_buf;
1100         }
1101
1102         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1103         MLX5_SET(qpc, qpc, uar_page, uar_index);
1104         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1105
1106         /* Set "fast registration enabled" for all kernel QPs */
1107         MLX5_SET(qpc, qpc, fre, 1);
1108         MLX5_SET(qpc, qpc, rlky, 1);
1109
1110         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
1111                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1112
1113         mlx5_fill_page_frag_array(&qp->buf,
1114                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1115                                                          *in, pas));
1116
1117         err = mlx5_db_alloc(dev->mdev, &qp->db);
1118         if (err) {
1119                 mlx5_ib_dbg(dev, "err %d\n", err);
1120                 goto err_free;
1121         }
1122
1123         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1124                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1125         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1126                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1127         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1128                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1129         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1130                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1131         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1132                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1133
1134         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1135             !qp->sq.w_list || !qp->sq.wqe_head) {
1136                 err = -ENOMEM;
1137                 goto err_wrid;
1138         }
1139
1140         return 0;
1141
1142 err_wrid:
1143         kvfree(qp->sq.wqe_head);
1144         kvfree(qp->sq.w_list);
1145         kvfree(qp->sq.wrid);
1146         kvfree(qp->sq.wr_data);
1147         kvfree(qp->rq.wrid);
1148         mlx5_db_free(dev->mdev, &qp->db);
1149
1150 err_free:
1151         kvfree(*in);
1152
1153 err_buf:
1154         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1155         return err;
1156 }
1157
1158 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1159 {
1160         if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1161             (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
1162                 return MLX5_SRQ_RQ;
1163         else if (!qp->has_rq)
1164                 return MLX5_ZERO_LEN_RQ;
1165
1166         return MLX5_NON_ZERO_RQ;
1167 }
1168
1169 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1170                                     struct mlx5_ib_qp *qp,
1171                                     struct mlx5_ib_sq *sq, u32 tdn,
1172                                     struct ib_pd *pd)
1173 {
1174         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
1175         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1176
1177         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1178         MLX5_SET(tisc, tisc, transport_domain, tdn);
1179         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1180                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1181
1182         return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1183 }
1184
1185 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1186                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1187 {
1188         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1189 }
1190
1191 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1192 {
1193         if (sq->flow_rule)
1194                 mlx5_del_flow_rules(sq->flow_rule);
1195         sq->flow_rule = NULL;
1196 }
1197
1198 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1199                                    struct ib_udata *udata,
1200                                    struct mlx5_ib_sq *sq, void *qpin,
1201                                    struct ib_pd *pd)
1202 {
1203         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1204         __be64 *pas;
1205         void *in;
1206         void *sqc;
1207         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1208         void *wq;
1209         int inlen;
1210         int err;
1211         int page_shift = 0;
1212         int npages;
1213         int ncont = 0;
1214         u32 offset = 0;
1215
1216         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1217                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1218                                &offset);
1219         if (err)
1220                 return err;
1221
1222         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1223         in = kvzalloc(inlen, GFP_KERNEL);
1224         if (!in) {
1225                 err = -ENOMEM;
1226                 goto err_umem;
1227         }
1228
1229         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1230         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1231         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1232         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1233                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1234         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1235         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1236         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1237         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1238         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1239         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1240             MLX5_CAP_ETH(dev->mdev, swp))
1241                 MLX5_SET(sqc, sqc, allow_swp, 1);
1242
1243         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1244         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1245         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1246         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1247         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1248         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1249         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1250         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1251         MLX5_SET(wq, wq, page_offset, offset);
1252
1253         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1254         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1255
1256         err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
1257
1258         kvfree(in);
1259
1260         if (err)
1261                 goto err_umem;
1262
1263         return 0;
1264
1265 err_umem:
1266         ib_umem_release(sq->ubuffer.umem);
1267         sq->ubuffer.umem = NULL;
1268
1269         return err;
1270 }
1271
1272 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1273                                      struct mlx5_ib_sq *sq)
1274 {
1275         destroy_flow_rule_vport_sq(sq);
1276         mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
1277         ib_umem_release(sq->ubuffer.umem);
1278 }
1279
1280 static size_t get_rq_pas_size(void *qpc)
1281 {
1282         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1283         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1284         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1285         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1286         u32 po_quanta     = 1 << (log_page_size - 6);
1287         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1288         u32 page_size     = 1 << log_page_size;
1289         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1290         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1291
1292         return rq_num_pas * sizeof(u64);
1293 }
1294
1295 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1296                                    struct mlx5_ib_rq *rq, void *qpin,
1297                                    size_t qpinlen, struct ib_pd *pd)
1298 {
1299         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1300         __be64 *pas;
1301         __be64 *qp_pas;
1302         void *in;
1303         void *rqc;
1304         void *wq;
1305         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1306         size_t rq_pas_size = get_rq_pas_size(qpc);
1307         size_t inlen;
1308         int err;
1309
1310         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1311                 return -EINVAL;
1312
1313         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1314         in = kvzalloc(inlen, GFP_KERNEL);
1315         if (!in)
1316                 return -ENOMEM;
1317
1318         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1319         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1320         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1321                 MLX5_SET(rqc, rqc, vsd, 1);
1322         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1323         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1324         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1325         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1326         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1327
1328         if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
1329                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1330
1331         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1332         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1333         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1334                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1335         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1336         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1337         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1338         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1339         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1340         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1341
1342         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1343         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1344         memcpy(pas, qp_pas, rq_pas_size);
1345
1346         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
1347
1348         kvfree(in);
1349
1350         return err;
1351 }
1352
1353 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1354                                      struct mlx5_ib_rq *rq)
1355 {
1356         mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
1357 }
1358
1359 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1360                                       struct mlx5_ib_rq *rq,
1361                                       u32 qp_flags_en,
1362                                       struct ib_pd *pd)
1363 {
1364         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1365                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1366                 mlx5_ib_disable_lb(dev, false, true);
1367         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1368 }
1369
1370 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1371                                     struct mlx5_ib_rq *rq, u32 tdn,
1372                                     u32 *qp_flags_en, struct ib_pd *pd,
1373                                     u32 *out)
1374 {
1375         u8 lb_flag = 0;
1376         u32 *in;
1377         void *tirc;
1378         int inlen;
1379         int err;
1380
1381         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1382         in = kvzalloc(inlen, GFP_KERNEL);
1383         if (!in)
1384                 return -ENOMEM;
1385
1386         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1387         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1388         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1389         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1390         MLX5_SET(tirc, tirc, transport_domain, tdn);
1391         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1392                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1393
1394         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1395                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1396
1397         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1398                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1399
1400         if (dev->is_rep) {
1401                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1402                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1403         }
1404
1405         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1406         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1407         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1408         rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1409         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1410                 err = mlx5_ib_enable_lb(dev, false, true);
1411
1412                 if (err)
1413                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1414         }
1415         kvfree(in);
1416
1417         return err;
1418 }
1419
1420 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1421                                 u32 *in, size_t inlen,
1422                                 struct ib_pd *pd,
1423                                 struct ib_udata *udata,
1424                                 struct mlx5_ib_create_qp_resp *resp)
1425 {
1426         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1427         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1428         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1429         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1430                 udata, struct mlx5_ib_ucontext, ibucontext);
1431         int err;
1432         u32 tdn = mucontext->tdn;
1433         u16 uid = to_mpd(pd)->uid;
1434         u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1435
1436         if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt)
1437                 return -EINVAL;
1438         if (qp->sq.wqe_cnt) {
1439                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1440                 if (err)
1441                         return err;
1442
1443                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1444                 if (err)
1445                         goto err_destroy_tis;
1446
1447                 if (uid) {
1448                         resp->tisn = sq->tisn;
1449                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1450                         resp->sqn = sq->base.mqp.qpn;
1451                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1452                 }
1453
1454                 sq->base.container_mibqp = qp;
1455                 sq->base.mqp.event = mlx5_ib_qp_event;
1456         }
1457
1458         if (qp->rq.wqe_cnt) {
1459                 rq->base.container_mibqp = qp;
1460
1461                 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
1462                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1463                 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
1464                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1465                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1466                 if (err)
1467                         goto err_destroy_sq;
1468
1469                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1470                                                out);
1471                 if (err)
1472                         goto err_destroy_rq;
1473
1474                 if (uid) {
1475                         resp->rqn = rq->base.mqp.qpn;
1476                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1477                         resp->tirn = rq->tirn;
1478                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1479                         if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1480                                 resp->tir_icm_addr = MLX5_GET(
1481                                         create_tir_out, out, icm_address_31_0);
1482                                 resp->tir_icm_addr |=
1483                                         (u64)MLX5_GET(create_tir_out, out,
1484                                                       icm_address_39_32)
1485                                         << 32;
1486                                 resp->tir_icm_addr |=
1487                                         (u64)MLX5_GET(create_tir_out, out,
1488                                                       icm_address_63_40)
1489                                         << 40;
1490                                 resp->comp_mask |=
1491                                         MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1492                         }
1493                 }
1494         }
1495
1496         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1497                                                      rq->base.mqp.qpn;
1498         return 0;
1499
1500 err_destroy_rq:
1501         destroy_raw_packet_qp_rq(dev, rq);
1502 err_destroy_sq:
1503         if (!qp->sq.wqe_cnt)
1504                 return err;
1505         destroy_raw_packet_qp_sq(dev, sq);
1506 err_destroy_tis:
1507         destroy_raw_packet_qp_tis(dev, sq, pd);
1508
1509         return err;
1510 }
1511
1512 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1513                                   struct mlx5_ib_qp *qp)
1514 {
1515         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1516         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1517         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1518
1519         if (qp->rq.wqe_cnt) {
1520                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1521                 destroy_raw_packet_qp_rq(dev, rq);
1522         }
1523
1524         if (qp->sq.wqe_cnt) {
1525                 destroy_raw_packet_qp_sq(dev, sq);
1526                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1527         }
1528 }
1529
1530 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1531                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1532 {
1533         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1534         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1535
1536         sq->sq = &qp->sq;
1537         rq->rq = &qp->rq;
1538         sq->doorbell = &qp->db;
1539         rq->doorbell = &qp->db;
1540 }
1541
1542 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1543 {
1544         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1545                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1546                 mlx5_ib_disable_lb(dev, false, true);
1547         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1548                              to_mpd(qp->ibqp.pd)->uid);
1549 }
1550
1551 struct mlx5_create_qp_params {
1552         struct ib_udata *udata;
1553         size_t inlen;
1554         size_t outlen;
1555         size_t ucmd_size;
1556         void *ucmd;
1557         u8 is_rss_raw : 1;
1558         struct ib_qp_init_attr *attr;
1559         u32 uidx;
1560         struct mlx5_ib_create_qp_resp resp;
1561 };
1562
1563 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1564                                  struct mlx5_ib_qp *qp,
1565                                  struct mlx5_create_qp_params *params)
1566 {
1567         struct ib_qp_init_attr *init_attr = params->attr;
1568         struct mlx5_ib_create_qp_rss *ucmd = params->ucmd;
1569         struct ib_udata *udata = params->udata;
1570         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1571                 udata, struct mlx5_ib_ucontext, ibucontext);
1572         int inlen;
1573         int outlen;
1574         int err;
1575         u32 *in;
1576         u32 *out;
1577         void *tirc;
1578         void *hfso;
1579         u32 selected_fields = 0;
1580         u32 outer_l4;
1581         u32 tdn = mucontext->tdn;
1582         u8 lb_flag = 0;
1583
1584         if (ucmd->comp_mask) {
1585                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1586                 return -EOPNOTSUPP;
1587         }
1588
1589         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1590             !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1591                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1592                 return -EOPNOTSUPP;
1593         }
1594
1595         if (dev->is_rep)
1596                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1597
1598         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1599                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1600
1601         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1602                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1603
1604         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1605         outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1606         in = kvzalloc(inlen + outlen, GFP_KERNEL);
1607         if (!in)
1608                 return -ENOMEM;
1609
1610         out = in + MLX5_ST_SZ_DW(create_tir_in);
1611         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1612         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1613         MLX5_SET(tirc, tirc, disp_type,
1614                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1615         MLX5_SET(tirc, tirc, indirect_table,
1616                  init_attr->rwq_ind_tbl->ind_tbl_num);
1617         MLX5_SET(tirc, tirc, transport_domain, tdn);
1618
1619         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1620
1621         if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1622                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1623
1624         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1625
1626         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1627                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1628         else
1629                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1630
1631         switch (ucmd->rx_hash_function) {
1632         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1633         {
1634                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1635                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1636
1637                 if (len != ucmd->rx_key_len) {
1638                         err = -EINVAL;
1639                         goto err;
1640                 }
1641
1642                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1643                 memcpy(rss_key, ucmd->rx_hash_key, len);
1644                 break;
1645         }
1646         default:
1647                 err = -EOPNOTSUPP;
1648                 goto err;
1649         }
1650
1651         if (!ucmd->rx_hash_fields_mask) {
1652                 /* special case when this TIR serves as steering entry without hashing */
1653                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1654                         goto create_tir;
1655                 err = -EINVAL;
1656                 goto err;
1657         }
1658
1659         if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1660              (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1661              ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1662              (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1663                 err = -EINVAL;
1664                 goto err;
1665         }
1666
1667         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1668         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1669             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1670                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1671                          MLX5_L3_PROT_TYPE_IPV4);
1672         else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1673                  (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1674                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1675                          MLX5_L3_PROT_TYPE_IPV6);
1676
1677         outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1678                     (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1679                            << 0 |
1680                    ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1681                     (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1682                            << 1 |
1683                    (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1684
1685         /* Check that only one l4 protocol is set */
1686         if (outer_l4 & (outer_l4 - 1)) {
1687                 err = -EINVAL;
1688                 goto err;
1689         }
1690
1691         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1692         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1693             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1694                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1695                          MLX5_L4_PROT_TYPE_TCP);
1696         else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1697                  (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1698                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1699                          MLX5_L4_PROT_TYPE_UDP);
1700
1701         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1702             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1703                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1704
1705         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1706             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1707                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1708
1709         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1710             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1711                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1712
1713         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1714             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1715                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1716
1717         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1718                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1719
1720         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1721
1722 create_tir:
1723         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1724         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1725
1726         qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1727         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1728                 err = mlx5_ib_enable_lb(dev, false, true);
1729
1730                 if (err)
1731                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1732                                              to_mpd(pd)->uid);
1733         }
1734
1735         if (err)
1736                 goto err;
1737
1738         if (mucontext->devx_uid) {
1739                 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1740                 params->resp.tirn = qp->rss_qp.tirn;
1741                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1742                         params->resp.tir_icm_addr =
1743                                 MLX5_GET(create_tir_out, out, icm_address_31_0);
1744                         params->resp.tir_icm_addr |=
1745                                 (u64)MLX5_GET(create_tir_out, out,
1746                                               icm_address_39_32)
1747                                 << 32;
1748                         params->resp.tir_icm_addr |=
1749                                 (u64)MLX5_GET(create_tir_out, out,
1750                                               icm_address_63_40)
1751                                 << 40;
1752                         params->resp.comp_mask |=
1753                                 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1754                 }
1755         }
1756
1757         kvfree(in);
1758         /* qpn is reserved for that QP */
1759         qp->trans_qp.base.mqp.qpn = 0;
1760         qp->is_rss = true;
1761         return 0;
1762
1763 err:
1764         kvfree(in);
1765         return err;
1766 }
1767
1768 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1769                                          struct ib_qp_init_attr *init_attr,
1770                                          struct mlx5_ib_create_qp *ucmd,
1771                                          void *qpc)
1772 {
1773         int scqe_sz;
1774         bool allow_scat_cqe = false;
1775
1776         if (ucmd)
1777                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1778
1779         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1780                 return;
1781
1782         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1783         if (scqe_sz == 128) {
1784                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1785                 return;
1786         }
1787
1788         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1789             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1790                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1791 }
1792
1793 static int atomic_size_to_mode(int size_mask)
1794 {
1795         /* driver does not support atomic_size > 256B
1796          * and does not know how to translate bigger sizes
1797          */
1798         int supported_size_mask = size_mask & 0x1ff;
1799         int log_max_size;
1800
1801         if (!supported_size_mask)
1802                 return -EOPNOTSUPP;
1803
1804         log_max_size = __fls(supported_size_mask);
1805
1806         if (log_max_size > 3)
1807                 return log_max_size;
1808
1809         return MLX5_ATOMIC_MODE_8B;
1810 }
1811
1812 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1813                            enum ib_qp_type qp_type)
1814 {
1815         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1816         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1817         int atomic_mode = -EOPNOTSUPP;
1818         int atomic_size_mask;
1819
1820         if (!atomic)
1821                 return -EOPNOTSUPP;
1822
1823         if (qp_type == MLX5_IB_QPT_DCT)
1824                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1825         else
1826                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1827
1828         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1829             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1830                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1831
1832         if (atomic_mode <= 0 &&
1833             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1834              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1835                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1836
1837         return atomic_mode;
1838 }
1839
1840 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1841                              struct mlx5_create_qp_params *params)
1842 {
1843         struct mlx5_ib_create_qp *ucmd = params->ucmd;
1844         struct ib_qp_init_attr *attr = params->attr;
1845         u32 uidx = params->uidx;
1846         struct mlx5_ib_resources *devr = &dev->devr;
1847         u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
1848         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1849         struct mlx5_core_dev *mdev = dev->mdev;
1850         struct mlx5_ib_qp_base *base;
1851         unsigned long flags;
1852         void *qpc;
1853         u32 *in;
1854         int err;
1855
1856         mutex_init(&qp->mutex);
1857
1858         if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1859                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1860
1861         in = kvzalloc(inlen, GFP_KERNEL);
1862         if (!in)
1863                 return -ENOMEM;
1864
1865         if (MLX5_CAP_GEN(mdev, ece_support))
1866                 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
1867         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1868
1869         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC);
1870         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1871         MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn);
1872
1873         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1874                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1875         if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1876                 MLX5_SET(qpc, qpc, cd_master, 1);
1877         if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1878                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1879         if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1880                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1881
1882         MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
1883         MLX5_SET(qpc, qpc, no_sq, 1);
1884         MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1885         MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1886         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1887         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn);
1888         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1889
1890         /* 0xffffff means we ask to work with cqe version 0 */
1891         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1892                 MLX5_SET(qpc, qpc, user_index, uidx);
1893
1894         if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1895                 MLX5_SET(qpc, qpc, end_padding_mode,
1896                          MLX5_WQ_END_PAD_MODE_ALIGN);
1897                 /* Special case to clean flag */
1898                 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
1899         }
1900
1901         base = &qp->trans_qp.base;
1902         err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
1903         kvfree(in);
1904         if (err)
1905                 return err;
1906
1907         base->container_mibqp = qp;
1908         base->mqp.event = mlx5_ib_qp_event;
1909         params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
1910
1911         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1912         list_add_tail(&qp->qps_list, &dev->qp_list);
1913         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1914
1915         qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn;
1916         return 0;
1917 }
1918
1919 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1920                           struct mlx5_ib_qp *qp,
1921                           struct mlx5_create_qp_params *params)
1922 {
1923         struct ib_qp_init_attr *init_attr = params->attr;
1924         struct mlx5_ib_create_qp *ucmd = params->ucmd;
1925         u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
1926         struct ib_udata *udata = params->udata;
1927         u32 uidx = params->uidx;
1928         struct mlx5_ib_resources *devr = &dev->devr;
1929         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1930         struct mlx5_core_dev *mdev = dev->mdev;
1931         struct mlx5_ib_cq *send_cq;
1932         struct mlx5_ib_cq *recv_cq;
1933         unsigned long flags;
1934         struct mlx5_ib_qp_base *base;
1935         int mlx5_st;
1936         void *qpc;
1937         u32 *in;
1938         int err;
1939
1940         mutex_init(&qp->mutex);
1941         spin_lock_init(&qp->sq.lock);
1942         spin_lock_init(&qp->rq.lock);
1943
1944         mlx5_st = to_mlx5_st(qp->type);
1945         if (mlx5_st < 0)
1946                 return -EINVAL;
1947
1948         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1949                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1950
1951         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1952                 qp->underlay_qpn = init_attr->source_qpn;
1953
1954         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1955                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
1956                &qp->raw_packet_qp.rq.base :
1957                &qp->trans_qp.base;
1958
1959         qp->has_rq = qp_has_rq(init_attr);
1960         err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
1961         if (err) {
1962                 mlx5_ib_dbg(dev, "err %d\n", err);
1963                 return err;
1964         }
1965
1966         if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
1967             ucmd->rq_wqe_count != qp->rq.wqe_cnt)
1968                 return -EINVAL;
1969
1970         if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
1971                 return -EINVAL;
1972
1973         err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, &params->resp,
1974                               &inlen, base, ucmd);
1975         if (err)
1976                 return err;
1977
1978         if (is_sqp(init_attr->qp_type))
1979                 qp->port = init_attr->port_num;
1980
1981         if (MLX5_CAP_GEN(mdev, ece_support))
1982                 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
1983         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1984
1985         MLX5_SET(qpc, qpc, st, mlx5_st);
1986         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1987         MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
1988
1989         if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
1990                 MLX5_SET(qpc, qpc, wq_signature, 1);
1991
1992         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1993                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1994
1995         if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1996                 MLX5_SET(qpc, qpc, cd_master, 1);
1997         if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1998                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1999         if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
2000                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2001         if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
2002                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2003         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2004             (init_attr->qp_type == IB_QPT_RC ||
2005              init_attr->qp_type == IB_QPT_UC)) {
2006                 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
2007
2008                 MLX5_SET(qpc, qpc, cs_res,
2009                          rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2010                                           MLX5_RES_SCAT_DATA32_CQE);
2011         }
2012         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2013             (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
2014                 configure_requester_scat_cqe(dev, init_attr, ucmd, qpc);
2015
2016         if (qp->rq.wqe_cnt) {
2017                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2018                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2019         }
2020
2021         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2022
2023         if (qp->sq.wqe_cnt) {
2024                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2025         } else {
2026                 MLX5_SET(qpc, qpc, no_sq, 1);
2027                 if (init_attr->srq &&
2028                     init_attr->srq->srq_type == IB_SRQT_TM)
2029                         MLX5_SET(qpc, qpc, offload_type,
2030                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2031         }
2032
2033         /* Set default resources */
2034         switch (init_attr->qp_type) {
2035         case IB_QPT_XRC_INI:
2036                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2037                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2038                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2039                 break;
2040         default:
2041                 if (init_attr->srq) {
2042                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2043                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2044                 } else {
2045                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2046                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2047                 }
2048         }
2049
2050         if (init_attr->send_cq)
2051                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2052
2053         if (init_attr->recv_cq)
2054                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2055
2056         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2057
2058         /* 0xffffff means we ask to work with cqe version 0 */
2059         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2060                 MLX5_SET(qpc, qpc, user_index, uidx);
2061
2062         if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2063             init_attr->qp_type != IB_QPT_RAW_PACKET) {
2064                 MLX5_SET(qpc, qpc, end_padding_mode,
2065                          MLX5_WQ_END_PAD_MODE_ALIGN);
2066                 /* Special case to clean flag */
2067                 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
2068         }
2069
2070         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2071             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2072                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
2073                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2074                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2075                                            &params->resp);
2076         } else
2077                 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
2078
2079         kvfree(in);
2080         if (err)
2081                 goto err_create;
2082
2083         base->container_mibqp = qp;
2084         base->mqp.event = mlx5_ib_qp_event;
2085         params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
2086
2087         get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
2088                 &send_cq, &recv_cq);
2089         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2090         mlx5_ib_lock_cqs(send_cq, recv_cq);
2091         /* Maintain device to QPs access, needed for further handling via reset
2092          * flow
2093          */
2094         list_add_tail(&qp->qps_list, &dev->qp_list);
2095         /* Maintain CQ to QPs access, needed for further handling via reset flow
2096          */
2097         if (send_cq)
2098                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2099         if (recv_cq)
2100                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2101         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2102         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2103
2104         return 0;
2105
2106 err_create:
2107         destroy_qp(dev, qp, base, udata);
2108         return err;
2109 }
2110
2111 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2112                             struct mlx5_ib_qp *qp,
2113                             struct mlx5_create_qp_params *params)
2114 {
2115         struct ib_qp_init_attr *attr = params->attr;
2116         u32 uidx = params->uidx;
2117         struct mlx5_ib_resources *devr = &dev->devr;
2118         u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
2119         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2120         struct mlx5_core_dev *mdev = dev->mdev;
2121         struct mlx5_ib_cq *send_cq;
2122         struct mlx5_ib_cq *recv_cq;
2123         unsigned long flags;
2124         struct mlx5_ib_qp_base *base;
2125         int mlx5_st;
2126         void *qpc;
2127         u32 *in;
2128         int err;
2129
2130         mutex_init(&qp->mutex);
2131         spin_lock_init(&qp->sq.lock);
2132         spin_lock_init(&qp->rq.lock);
2133
2134         mlx5_st = to_mlx5_st(qp->type);
2135         if (mlx5_st < 0)
2136                 return -EINVAL;
2137
2138         if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2139                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2140
2141         base = &qp->trans_qp.base;
2142
2143         qp->has_rq = qp_has_rq(attr);
2144         err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL);
2145         if (err) {
2146                 mlx5_ib_dbg(dev, "err %d\n", err);
2147                 return err;
2148         }
2149
2150         err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base);
2151         if (err)
2152                 return err;
2153
2154         if (is_sqp(attr->qp_type))
2155                 qp->port = attr->port_num;
2156
2157         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2158
2159         MLX5_SET(qpc, qpc, st, mlx5_st);
2160         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2161
2162         if (attr->qp_type != MLX5_IB_QPT_REG_UMR)
2163                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2164         else
2165                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2166
2167
2168         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2169                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2170
2171         if (qp->rq.wqe_cnt) {
2172                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2173                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2174         }
2175
2176         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr));
2177
2178         if (qp->sq.wqe_cnt)
2179                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2180         else
2181                 MLX5_SET(qpc, qpc, no_sq, 1);
2182
2183         if (attr->srq) {
2184                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2185                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2186                          to_msrq(attr->srq)->msrq.srqn);
2187         } else {
2188                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2189                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2190                          to_msrq(devr->s1)->msrq.srqn);
2191         }
2192
2193         if (attr->send_cq)
2194                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn);
2195
2196         if (attr->recv_cq)
2197                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn);
2198
2199         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2200
2201         /* 0xffffff means we ask to work with cqe version 0 */
2202         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2203                 MLX5_SET(qpc, qpc, user_index, uidx);
2204
2205         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2206         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2207                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2208
2209         err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
2210         kvfree(in);
2211         if (err)
2212                 goto err_create;
2213
2214         base->container_mibqp = qp;
2215         base->mqp.event = mlx5_ib_qp_event;
2216
2217         get_cqs(qp->type, attr->send_cq, attr->recv_cq,
2218                 &send_cq, &recv_cq);
2219         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2220         mlx5_ib_lock_cqs(send_cq, recv_cq);
2221         /* Maintain device to QPs access, needed for further handling via reset
2222          * flow
2223          */
2224         list_add_tail(&qp->qps_list, &dev->qp_list);
2225         /* Maintain CQ to QPs access, needed for further handling via reset flow
2226          */
2227         if (send_cq)
2228                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2229         if (recv_cq)
2230                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2231         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2232         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2233
2234         return 0;
2235
2236 err_create:
2237         destroy_qp(dev, qp, base, NULL);
2238         return err;
2239 }
2240
2241 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2242         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2243 {
2244         if (send_cq) {
2245                 if (recv_cq) {
2246                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2247                                 spin_lock(&send_cq->lock);
2248                                 spin_lock_nested(&recv_cq->lock,
2249                                                  SINGLE_DEPTH_NESTING);
2250                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2251                                 spin_lock(&send_cq->lock);
2252                                 __acquire(&recv_cq->lock);
2253                         } else {
2254                                 spin_lock(&recv_cq->lock);
2255                                 spin_lock_nested(&send_cq->lock,
2256                                                  SINGLE_DEPTH_NESTING);
2257                         }
2258                 } else {
2259                         spin_lock(&send_cq->lock);
2260                         __acquire(&recv_cq->lock);
2261                 }
2262         } else if (recv_cq) {
2263                 spin_lock(&recv_cq->lock);
2264                 __acquire(&send_cq->lock);
2265         } else {
2266                 __acquire(&send_cq->lock);
2267                 __acquire(&recv_cq->lock);
2268         }
2269 }
2270
2271 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2272         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2273 {
2274         if (send_cq) {
2275                 if (recv_cq) {
2276                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2277                                 spin_unlock(&recv_cq->lock);
2278                                 spin_unlock(&send_cq->lock);
2279                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2280                                 __release(&recv_cq->lock);
2281                                 spin_unlock(&send_cq->lock);
2282                         } else {
2283                                 spin_unlock(&send_cq->lock);
2284                                 spin_unlock(&recv_cq->lock);
2285                         }
2286                 } else {
2287                         __release(&recv_cq->lock);
2288                         spin_unlock(&send_cq->lock);
2289                 }
2290         } else if (recv_cq) {
2291                 __release(&send_cq->lock);
2292                 spin_unlock(&recv_cq->lock);
2293         } else {
2294                 __release(&recv_cq->lock);
2295                 __release(&send_cq->lock);
2296         }
2297 }
2298
2299 static void get_cqs(enum ib_qp_type qp_type,
2300                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2301                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2302 {
2303         switch (qp_type) {
2304         case IB_QPT_XRC_TGT:
2305                 *send_cq = NULL;
2306                 *recv_cq = NULL;
2307                 break;
2308         case MLX5_IB_QPT_REG_UMR:
2309         case IB_QPT_XRC_INI:
2310                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2311                 *recv_cq = NULL;
2312                 break;
2313
2314         case IB_QPT_SMI:
2315         case MLX5_IB_QPT_HW_GSI:
2316         case IB_QPT_RC:
2317         case IB_QPT_UC:
2318         case IB_QPT_UD:
2319         case IB_QPT_RAW_PACKET:
2320                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2321                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2322                 break;
2323         default:
2324                 *send_cq = NULL;
2325                 *recv_cq = NULL;
2326                 break;
2327         }
2328 }
2329
2330 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2331                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2332                                 u8 lag_tx_affinity);
2333
2334 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2335                               struct ib_udata *udata)
2336 {
2337         struct mlx5_ib_cq *send_cq, *recv_cq;
2338         struct mlx5_ib_qp_base *base;
2339         unsigned long flags;
2340         int err;
2341
2342         if (qp->ibqp.rwq_ind_tbl) {
2343                 destroy_rss_raw_qp_tir(dev, qp);
2344                 return;
2345         }
2346
2347         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2348                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
2349                &qp->raw_packet_qp.rq.base :
2350                &qp->trans_qp.base;
2351
2352         if (qp->state != IB_QPS_RESET) {
2353                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2354                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
2355                         err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
2356                                                   NULL, &base->mqp);
2357                 } else {
2358                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2359                                 .operation = MLX5_CMD_OP_2RST_QP
2360                         };
2361
2362                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2363                 }
2364                 if (err)
2365                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2366                                      base->mqp.qpn);
2367         }
2368
2369         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2370                 &send_cq, &recv_cq);
2371
2372         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2373         mlx5_ib_lock_cqs(send_cq, recv_cq);
2374         /* del from lists under both locks above to protect reset flow paths */
2375         list_del(&qp->qps_list);
2376         if (send_cq)
2377                 list_del(&qp->cq_send_list);
2378
2379         if (recv_cq)
2380                 list_del(&qp->cq_recv_list);
2381
2382         if (!udata) {
2383                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2384                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2385                 if (send_cq != recv_cq)
2386                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2387                                            NULL);
2388         }
2389         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2390         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2391
2392         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2393             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2394                 destroy_raw_packet_qp(dev, qp);
2395         } else {
2396                 err = mlx5_core_destroy_qp(dev, &base->mqp);
2397                 if (err)
2398                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2399                                      base->mqp.qpn);
2400         }
2401
2402         destroy_qp(dev, qp, base, udata);
2403 }
2404
2405 static int create_dct(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2406                       struct mlx5_create_qp_params *params)
2407 {
2408         struct ib_qp_init_attr *attr = params->attr;
2409         struct mlx5_ib_create_qp *ucmd = params->ucmd;
2410         u32 uidx = params->uidx;
2411         void *dctc;
2412
2413         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2414         if (!qp->dct.in)
2415                 return -ENOMEM;
2416
2417         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2418         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2419         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2420         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2421         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2422         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2423         MLX5_SET(dctc, dctc, user_index, uidx);
2424
2425         if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
2426                 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2427
2428                 if (rcqe_sz == 128)
2429                         MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2430         }
2431
2432         qp->state = IB_QPS_RESET;
2433
2434         return 0;
2435 }
2436
2437 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2438                          enum ib_qp_type *type)
2439 {
2440         if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2441                 goto out;
2442
2443         switch (attr->qp_type) {
2444         case IB_QPT_XRC_TGT:
2445         case IB_QPT_XRC_INI:
2446                 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2447                         goto out;
2448                 fallthrough;
2449         case IB_QPT_RC:
2450         case IB_QPT_UC:
2451         case IB_QPT_SMI:
2452         case MLX5_IB_QPT_HW_GSI:
2453         case IB_QPT_DRIVER:
2454         case IB_QPT_GSI:
2455                 if (dev->profile == &raw_eth_profile)
2456                         goto out;
2457         case IB_QPT_RAW_PACKET:
2458         case IB_QPT_UD:
2459         case MLX5_IB_QPT_REG_UMR:
2460                 break;
2461         default:
2462                 goto out;
2463         }
2464
2465         *type = attr->qp_type;
2466         return 0;
2467
2468 out:
2469         mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2470         return -EOPNOTSUPP;
2471 }
2472
2473 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2474                             struct ib_qp_init_attr *attr,
2475                             struct ib_udata *udata)
2476 {
2477         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2478                 udata, struct mlx5_ib_ucontext, ibucontext);
2479
2480         if (!udata) {
2481                 /* Kernel create_qp callers */
2482                 if (attr->rwq_ind_tbl)
2483                         return -EOPNOTSUPP;
2484
2485                 switch (attr->qp_type) {
2486                 case IB_QPT_RAW_PACKET:
2487                 case IB_QPT_DRIVER:
2488                         return -EOPNOTSUPP;
2489                 default:
2490                         return 0;
2491                 }
2492         }
2493
2494         /* Userspace create_qp callers */
2495         if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2496                 mlx5_ib_dbg(dev,
2497                         "Raw Packet QP is only supported for CQE version > 0\n");
2498                 return -EINVAL;
2499         }
2500
2501         if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2502                 mlx5_ib_dbg(dev,
2503                             "Wrong QP type %d for the RWQ indirect table\n",
2504                             attr->qp_type);
2505                 return -EINVAL;
2506         }
2507
2508         switch (attr->qp_type) {
2509         case IB_QPT_SMI:
2510         case MLX5_IB_QPT_HW_GSI:
2511         case MLX5_IB_QPT_REG_UMR:
2512         case IB_QPT_GSI:
2513                 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2514                             attr->qp_type);
2515                 return -EINVAL;
2516         default:
2517                 break;
2518         }
2519
2520         /*
2521          * We don't need to see this warning, it means that kernel code
2522          * missing ib_pd. Placed here to catch developer's mistakes.
2523          */
2524         WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2525                   "There is a missing PD pointer assignment\n");
2526         return 0;
2527 }
2528
2529 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2530                                 bool cond, struct mlx5_ib_qp *qp)
2531 {
2532         if (!(*flags & flag))
2533                 return;
2534
2535         if (cond) {
2536                 qp->flags_en |= flag;
2537                 *flags &= ~flag;
2538                 return;
2539         }
2540
2541         if (flag == MLX5_QP_FLAG_SCATTER_CQE) {
2542                 /*
2543                  * We don't return error if this flag was provided,
2544                  * and mlx5 doesn't have right capability.
2545                  */
2546                 *flags &= ~MLX5_QP_FLAG_SCATTER_CQE;
2547                 return;
2548         }
2549         mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2550 }
2551
2552 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2553                                 void *ucmd, struct ib_qp_init_attr *attr)
2554 {
2555         struct mlx5_core_dev *mdev = dev->mdev;
2556         bool cond;
2557         int flags;
2558
2559         if (attr->rwq_ind_tbl)
2560                 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2561         else
2562                 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
2563
2564         switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2565         case MLX5_QP_FLAG_TYPE_DCI:
2566                 qp->type = MLX5_IB_QPT_DCI;
2567                 break;
2568         case MLX5_QP_FLAG_TYPE_DCT:
2569                 qp->type = MLX5_IB_QPT_DCT;
2570                 break;
2571         default:
2572                 if (qp->type != IB_QPT_DRIVER)
2573                         break;
2574                 /*
2575                  * It is IB_QPT_DRIVER and or no subtype or
2576                  * wrong subtype were provided.
2577                  */
2578                 return -EINVAL;
2579         }
2580
2581         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2582         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2583
2584         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2585         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2586                             MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2587
2588         if (qp->type == IB_QPT_RAW_PACKET) {
2589                 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2590                        MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2591                        MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2592                 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2593                                     cond, qp);
2594                 process_vendor_flag(dev, &flags,
2595                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2596                                     qp);
2597                 process_vendor_flag(dev, &flags,
2598                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2599                                     qp);
2600         }
2601
2602         if (qp->type == IB_QPT_RC)
2603                 process_vendor_flag(dev, &flags,
2604                                     MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2605                                     MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2606
2607         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2608         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2609
2610         cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2611                                 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2612                                 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC);
2613         if (attr->rwq_ind_tbl && cond) {
2614                 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n",
2615                             cond);
2616                 return -EINVAL;
2617         }
2618
2619         if (flags)
2620                 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2621
2622         return (flags) ? -EINVAL : 0;
2623         }
2624
2625 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2626                                 bool cond, struct mlx5_ib_qp *qp)
2627 {
2628         if (!(*flags & flag))
2629                 return;
2630
2631         if (cond) {
2632                 qp->flags |= flag;
2633                 *flags &= ~flag;
2634                 return;
2635         }
2636
2637         if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2638                 /*
2639                  * Special case, if condition didn't meet, it won't be error,
2640                  * just different in-kernel flow.
2641                  */
2642                 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2643                 return;
2644         }
2645         mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2646 }
2647
2648 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2649                                 struct ib_qp_init_attr *attr)
2650 {
2651         enum ib_qp_type qp_type = qp->type;
2652         struct mlx5_core_dev *mdev = dev->mdev;
2653         int create_flags = attr->create_flags;
2654         bool cond;
2655
2656         if (qp->type == IB_QPT_UD && dev->profile == &raw_eth_profile)
2657                 if (create_flags & ~MLX5_IB_QP_CREATE_WC_TEST)
2658                         return -EINVAL;
2659
2660         if (qp_type == MLX5_IB_QPT_DCT)
2661                 return (create_flags) ? -EINVAL : 0;
2662
2663         if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2664                 return (create_flags) ? -EINVAL : 0;
2665
2666         process_create_flag(dev, &create_flags,
2667                             IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2668                             MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2669         process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2670                             MLX5_CAP_GEN(mdev, cd), qp);
2671         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2672                             MLX5_CAP_GEN(mdev, cd), qp);
2673         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2674                             MLX5_CAP_GEN(mdev, cd), qp);
2675
2676         if (qp_type == IB_QPT_UD) {
2677                 process_create_flag(dev, &create_flags,
2678                                     IB_QP_CREATE_IPOIB_UD_LSO,
2679                                     MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2680                                     qp);
2681                 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2682                 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2683                                     cond, qp);
2684         }
2685
2686         if (qp_type == IB_QPT_RAW_PACKET) {
2687                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2688                        MLX5_CAP_ETH(mdev, scatter_fcs);
2689                 process_create_flag(dev, &create_flags,
2690                                     IB_QP_CREATE_SCATTER_FCS, cond, qp);
2691
2692                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2693                        MLX5_CAP_ETH(mdev, vlan_cap);
2694                 process_create_flag(dev, &create_flags,
2695                                     IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2696         }
2697
2698         process_create_flag(dev, &create_flags,
2699                             IB_QP_CREATE_PCI_WRITE_END_PADDING,
2700                             MLX5_CAP_GEN(mdev, end_pad), qp);
2701
2702         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2703                             qp_type != MLX5_IB_QPT_REG_UMR, qp);
2704         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2705                             true, qp);
2706
2707         if (create_flags)
2708                 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2709                             create_flags);
2710
2711         return (create_flags) ? -EINVAL : 0;
2712 }
2713
2714 static int process_udata_size(struct mlx5_ib_dev *dev,
2715                               struct mlx5_create_qp_params *params)
2716 {
2717         size_t ucmd = sizeof(struct mlx5_ib_create_qp);
2718         struct ib_udata *udata = params->udata;
2719         size_t outlen = udata->outlen;
2720         size_t inlen = udata->inlen;
2721
2722         params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp));
2723         params->ucmd_size = ucmd;
2724         if (!params->is_rss_raw) {
2725                 /* User has old rdma-core, which doesn't support ECE */
2726                 size_t min_inlen =
2727                         offsetof(struct mlx5_ib_create_qp, ece_options);
2728
2729                 /*
2730                  * We will check in check_ucmd_data() that user
2731                  * cleared everything after inlen.
2732                  */
2733                 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd);
2734                 goto out;
2735         }
2736
2737         /* RSS RAW QP */
2738         if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
2739                 return -EINVAL;
2740
2741         if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index))
2742                 return -EINVAL;
2743
2744         ucmd = sizeof(struct mlx5_ib_create_qp_rss);
2745         params->ucmd_size = ucmd;
2746         if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
2747                 return -EINVAL;
2748
2749         params->inlen = min(ucmd, inlen);
2750 out:
2751         if (!params->inlen)
2752                 mlx5_ib_dbg(dev, "udata is too small\n");
2753
2754         return (params->inlen) ? 0 : -EINVAL;
2755 }
2756
2757 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2758                      struct mlx5_ib_qp *qp,
2759                      struct mlx5_create_qp_params *params)
2760 {
2761         int err;
2762
2763         if (params->is_rss_raw) {
2764                 err = create_rss_raw_qp_tir(dev, pd, qp, params);
2765                 goto out;
2766         }
2767
2768         if (qp->type == MLX5_IB_QPT_DCT) {
2769                 err = create_dct(pd, qp, params);
2770                 goto out;
2771         }
2772
2773         if (qp->type == IB_QPT_XRC_TGT) {
2774                 err = create_xrc_tgt_qp(dev, qp, params);
2775                 goto out;
2776         }
2777
2778         if (params->udata)
2779                 err = create_user_qp(dev, pd, qp, params);
2780         else
2781                 err = create_kernel_qp(dev, pd, qp, params);
2782
2783 out:
2784         if (err) {
2785                 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type);
2786                 return err;
2787         }
2788
2789         if (is_qp0(qp->type))
2790                 qp->ibqp.qp_num = 0;
2791         else if (is_qp1(qp->type))
2792                 qp->ibqp.qp_num = 1;
2793         else
2794                 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2795
2796         mlx5_ib_dbg(dev,
2797                 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n",
2798                 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2799                 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn :
2800                                         -1,
2801                 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn :
2802                                         -1,
2803                 params->resp.ece_options);
2804
2805         return 0;
2806 }
2807
2808 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2809                          struct ib_qp_init_attr *attr)
2810 {
2811         int ret = 0;
2812
2813         switch (qp->type) {
2814         case MLX5_IB_QPT_DCT:
2815                 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2816                 break;
2817         case MLX5_IB_QPT_DCI:
2818                 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2819                               -EINVAL :
2820                               0;
2821                 break;
2822         case IB_QPT_RAW_PACKET:
2823                 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2824                 break;
2825         default:
2826                 break;
2827         }
2828
2829         if (ret)
2830                 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2831
2832         return ret;
2833 }
2834
2835 static int get_qp_uidx(struct mlx5_ib_qp *qp,
2836                        struct mlx5_create_qp_params *params)
2837 {
2838         struct mlx5_ib_create_qp *ucmd = params->ucmd;
2839         struct ib_udata *udata = params->udata;
2840         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2841                 udata, struct mlx5_ib_ucontext, ibucontext);
2842
2843         if (params->is_rss_raw)
2844                 return 0;
2845
2846         return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &params->uidx);
2847 }
2848
2849 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2850 {
2851         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2852
2853         if (mqp->state == IB_QPS_RTR) {
2854                 int err;
2855
2856                 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2857                 if (err) {
2858                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2859                         return err;
2860                 }
2861         }
2862
2863         kfree(mqp->dct.in);
2864         kfree(mqp);
2865         return 0;
2866 }
2867
2868 static int check_ucmd_data(struct mlx5_ib_dev *dev,
2869                            struct mlx5_create_qp_params *params)
2870 {
2871         struct ib_qp_init_attr *attr = params->attr;
2872         struct ib_udata *udata = params->udata;
2873         size_t size, last;
2874         int ret;
2875
2876         if (params->is_rss_raw)
2877                 /*
2878                  * These QPs don't have "reserved" field in their
2879                  * create_qp input struct, so their data is always valid.
2880                  */
2881                 last = sizeof(struct mlx5_ib_create_qp_rss);
2882         else
2883                 /* IB_QPT_RAW_PACKET and IB_QPT_DRIVER don't have ECE data */
2884                 switch (attr->qp_type) {
2885                 case IB_QPT_DRIVER:
2886                 case IB_QPT_RAW_PACKET:
2887                         last = offsetof(struct mlx5_ib_create_qp, ece_options);
2888                         break;
2889                 default:
2890                         last = offsetof(struct mlx5_ib_create_qp, reserved);
2891                 }
2892
2893         if (udata->inlen <= last)
2894                 return 0;
2895
2896         /*
2897          * User provides different create_qp structures based on the
2898          * flow and we need to know if he cleared memory after our
2899          * struct create_qp ends.
2900          */
2901         size = udata->inlen - last;
2902         ret = ib_is_udata_cleared(params->udata, last, size);
2903         if (!ret)
2904                 mlx5_ib_dbg(
2905                         dev,
2906                         "udata is not cleared, inlen = %lu, ucmd = %lu, last = %lu, size = %lu\n",
2907                         udata->inlen, params->ucmd_size, last, size);
2908         return ret ? 0 : -EINVAL;
2909 }
2910
2911 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr,
2912                                 struct ib_udata *udata)
2913 {
2914         struct mlx5_create_qp_params params = {};
2915         struct mlx5_ib_dev *dev;
2916         struct mlx5_ib_qp *qp;
2917         enum ib_qp_type type;
2918         int err;
2919
2920         dev = pd ? to_mdev(pd->device) :
2921                    to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device);
2922
2923         err = check_qp_type(dev, attr, &type);
2924         if (err)
2925                 return ERR_PTR(err);
2926
2927         err = check_valid_flow(dev, pd, attr, udata);
2928         if (err)
2929                 return ERR_PTR(err);
2930
2931         if (attr->qp_type == IB_QPT_GSI)
2932                 return mlx5_ib_gsi_create_qp(pd, attr);
2933
2934         params.udata = udata;
2935         params.uidx = MLX5_IB_DEFAULT_UIDX;
2936         params.attr = attr;
2937         params.is_rss_raw = !!attr->rwq_ind_tbl;
2938
2939         if (udata) {
2940                 err = process_udata_size(dev, &params);
2941                 if (err)
2942                         return ERR_PTR(err);
2943
2944                 err = check_ucmd_data(dev, &params);
2945                 if (err)
2946                         return ERR_PTR(err);
2947
2948                 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL);
2949                 if (!params.ucmd)
2950                         return ERR_PTR(-ENOMEM);
2951
2952                 err = ib_copy_from_udata(params.ucmd, udata, params.inlen);
2953                 if (err)
2954                         goto free_ucmd;
2955         }
2956
2957         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2958         if (!qp) {
2959                 err = -ENOMEM;
2960                 goto free_ucmd;
2961         }
2962
2963         qp->type = type;
2964         if (udata) {
2965                 err = process_vendor_flags(dev, qp, params.ucmd, attr);
2966                 if (err)
2967                         goto free_qp;
2968
2969                 err = get_qp_uidx(qp, &params);
2970                 if (err)
2971                         goto free_qp;
2972         }
2973         err = process_create_flags(dev, qp, attr);
2974         if (err)
2975                 goto free_qp;
2976
2977         err = check_qp_attr(dev, qp, attr);
2978         if (err)
2979                 goto free_qp;
2980
2981         err = create_qp(dev, pd, qp, &params);
2982         if (err)
2983                 goto free_qp;
2984
2985         kfree(params.ucmd);
2986         params.ucmd = NULL;
2987
2988         if (udata)
2989                 /*
2990                  * It is safe to copy response for all user create QP flows,
2991                  * including MLX5_IB_QPT_DCT, which doesn't need it.
2992                  * In that case, resp will be filled with zeros.
2993                  */
2994                 err = ib_copy_to_udata(udata, &params.resp, params.outlen);
2995         if (err)
2996                 goto destroy_qp;
2997
2998         return &qp->ibqp;
2999
3000 destroy_qp:
3001         if (qp->type == MLX5_IB_QPT_DCT)
3002                 mlx5_ib_destroy_dct(qp);
3003         else
3004                 destroy_qp_common(dev, qp, udata);
3005         qp = NULL;
3006 free_qp:
3007         kfree(qp);
3008 free_ucmd:
3009         kfree(params.ucmd);
3010         return ERR_PTR(err);
3011 }
3012
3013 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
3014 {
3015         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3016         struct mlx5_ib_qp *mqp = to_mqp(qp);
3017
3018         if (unlikely(qp->qp_type == IB_QPT_GSI))
3019                 return mlx5_ib_gsi_destroy_qp(qp);
3020
3021         if (mqp->type == MLX5_IB_QPT_DCT)
3022                 return mlx5_ib_destroy_dct(mqp);
3023
3024         destroy_qp_common(dev, mqp, udata);
3025
3026         kfree(mqp);
3027
3028         return 0;
3029 }
3030
3031 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp,
3032                                 const struct ib_qp_attr *attr, int attr_mask,
3033                                 void *qpc)
3034 {
3035         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
3036         u8 dest_rd_atomic;
3037         u32 access_flags;
3038
3039         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3040                 dest_rd_atomic = attr->max_dest_rd_atomic;
3041         else
3042                 dest_rd_atomic = qp->trans_qp.resp_depth;
3043
3044         if (attr_mask & IB_QP_ACCESS_FLAGS)
3045                 access_flags = attr->qp_access_flags;
3046         else
3047                 access_flags = qp->trans_qp.atomic_rd_en;
3048
3049         if (!dest_rd_atomic)
3050                 access_flags &= IB_ACCESS_REMOTE_WRITE;
3051
3052         MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ));
3053
3054         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3055                 int atomic_mode;
3056
3057                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
3058                 if (atomic_mode < 0)
3059                         return -EOPNOTSUPP;
3060
3061                 MLX5_SET(qpc, qpc, rae, 1);
3062                 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode);
3063         }
3064
3065         MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3066         return 0;
3067 }
3068
3069 enum {
3070         MLX5_PATH_FLAG_FL       = 1 << 0,
3071         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
3072         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
3073 };
3074
3075 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
3076 {
3077         if (rate == IB_RATE_PORT_CURRENT)
3078                 return 0;
3079
3080         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
3081                 return -EINVAL;
3082
3083         while (rate != IB_RATE_PORT_CURRENT &&
3084                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
3085                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
3086                 --rate;
3087
3088         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
3089 }
3090
3091 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
3092                                       struct mlx5_ib_sq *sq, u8 sl,
3093                                       struct ib_pd *pd)
3094 {
3095         void *in;
3096         void *tisc;
3097         int inlen;
3098         int err;
3099
3100         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3101         in = kvzalloc(inlen, GFP_KERNEL);
3102         if (!in)
3103                 return -ENOMEM;
3104
3105         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
3106         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3107
3108         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3109         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
3110
3111         err = mlx5_core_modify_tis(dev, sq->tisn, in);
3112
3113         kvfree(in);
3114
3115         return err;
3116 }
3117
3118 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
3119                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
3120                                          struct ib_pd *pd)
3121 {
3122         void *in;
3123         void *tisc;
3124         int inlen;
3125         int err;
3126
3127         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3128         in = kvzalloc(inlen, GFP_KERNEL);
3129         if (!in)
3130                 return -ENOMEM;
3131
3132         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
3133         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3134
3135         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3136         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
3137
3138         err = mlx5_core_modify_tis(dev, sq->tisn, in);
3139
3140         kvfree(in);
3141
3142         return err;
3143 }
3144
3145 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah,
3146                                     u32 lqpn, u32 rqpn)
3147
3148 {
3149         u32 fl = ah->grh.flow_label;
3150
3151         if (!fl)
3152                 fl = rdma_calc_flow_label(lqpn, rqpn);
3153
3154         MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl));
3155 }
3156
3157 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3158                          const struct rdma_ah_attr *ah, void *path, u8 port,
3159                          int attr_mask, u32 path_flags,
3160                          const struct ib_qp_attr *attr, bool alt)
3161 {
3162         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
3163         int err;
3164         enum ib_gid_type gid_type;
3165         u8 ah_flags = rdma_ah_get_ah_flags(ah);
3166         u8 sl = rdma_ah_get_sl(ah);
3167
3168         if (attr_mask & IB_QP_PKEY_INDEX)
3169                 MLX5_SET(ads, path, pkey_index,
3170                          alt ? attr->alt_pkey_index : attr->pkey_index);
3171
3172         if (ah_flags & IB_AH_GRH) {
3173                 if (grh->sgid_index >=
3174                     dev->mdev->port_caps[port - 1].gid_table_len) {
3175                         pr_err("sgid_index (%u) too large. max is %d\n",
3176                                grh->sgid_index,
3177                                dev->mdev->port_caps[port - 1].gid_table_len);
3178                         return -EINVAL;
3179                 }
3180         }
3181
3182         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
3183                 if (!(ah_flags & IB_AH_GRH))
3184                         return -EINVAL;
3185
3186                 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32),
3187                                 ah->roce.dmac);
3188                 if ((qp->ibqp.qp_type == IB_QPT_RC ||
3189                      qp->ibqp.qp_type == IB_QPT_UC ||
3190                      qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3191                      qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
3192                     (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) &&
3193                     (attr_mask & IB_QP_DEST_QPN))
3194                         mlx5_set_path_udp_sport(path, ah,
3195                                                 qp->ibqp.qp_num,
3196                                                 attr->dest_qp_num);
3197                 MLX5_SET(ads, path, eth_prio, sl & 0x7);
3198                 gid_type = ah->grh.sgid_attr->gid_type;
3199                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3200                         MLX5_SET(ads, path, dscp, grh->traffic_class >> 2);
3201         } else {
3202                 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL));
3203                 MLX5_SET(ads, path, free_ar,
3204                          !!(path_flags & MLX5_PATH_FLAG_FREE_AR));
3205                 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah));
3206                 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah));
3207                 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH));
3208                 MLX5_SET(ads, path, sl, sl);
3209         }
3210
3211         if (ah_flags & IB_AH_GRH) {
3212                 MLX5_SET(ads, path, src_addr_index, grh->sgid_index);
3213                 MLX5_SET(ads, path, hop_limit, grh->hop_limit);
3214                 MLX5_SET(ads, path, tclass, grh->traffic_class);
3215                 MLX5_SET(ads, path, flow_label, grh->flow_label);
3216                 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw,
3217                        sizeof(grh->dgid.raw));
3218         }
3219
3220         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
3221         if (err < 0)
3222                 return err;
3223         MLX5_SET(ads, path, stat_rate, err);
3224         MLX5_SET(ads, path, vhca_port_num, port);
3225
3226         if (attr_mask & IB_QP_TIMEOUT)
3227                 MLX5_SET(ads, path, ack_timeout,
3228                          alt ? attr->alt_timeout : attr->timeout);
3229
3230         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3231                 return modify_raw_packet_eth_prio(dev->mdev,
3232                                                   &qp->raw_packet_qp.sq,
3233                                                   sl & 0xf, qp->ibqp.pd);
3234
3235         return 0;
3236 }
3237
3238 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3239         [MLX5_QP_STATE_INIT] = {
3240                 [MLX5_QP_STATE_INIT] = {
3241                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3242                                           MLX5_QP_OPTPAR_RAE            |
3243                                           MLX5_QP_OPTPAR_RWE            |
3244                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3245                                           MLX5_QP_OPTPAR_PRI_PORT       |
3246                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3247                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3248                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3249                                           MLX5_QP_OPTPAR_PRI_PORT       |
3250                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3251                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3252                                           MLX5_QP_OPTPAR_Q_KEY          |
3253                                           MLX5_QP_OPTPAR_PRI_PORT,
3254                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3255                                           MLX5_QP_OPTPAR_RAE            |
3256                                           MLX5_QP_OPTPAR_RWE            |
3257                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3258                                           MLX5_QP_OPTPAR_PRI_PORT       |
3259                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3260                 },
3261                 [MLX5_QP_STATE_RTR] = {
3262                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3263                                           MLX5_QP_OPTPAR_RRE            |
3264                                           MLX5_QP_OPTPAR_RAE            |
3265                                           MLX5_QP_OPTPAR_RWE            |
3266                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3267                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3268                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3269                                           MLX5_QP_OPTPAR_RWE            |
3270                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3271                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3272                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3273                                           MLX5_QP_OPTPAR_Q_KEY,
3274                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
3275                                            MLX5_QP_OPTPAR_Q_KEY,
3276                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3277                                           MLX5_QP_OPTPAR_RRE            |
3278                                           MLX5_QP_OPTPAR_RAE            |
3279                                           MLX5_QP_OPTPAR_RWE            |
3280                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3281                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3282                 },
3283         },
3284         [MLX5_QP_STATE_RTR] = {
3285                 [MLX5_QP_STATE_RTS] = {
3286                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3287                                           MLX5_QP_OPTPAR_RRE            |
3288                                           MLX5_QP_OPTPAR_RAE            |
3289                                           MLX5_QP_OPTPAR_RWE            |
3290                                           MLX5_QP_OPTPAR_PM_STATE       |
3291                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3292                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3293                                           MLX5_QP_OPTPAR_RWE            |
3294                                           MLX5_QP_OPTPAR_PM_STATE,
3295                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3296                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3297                                           MLX5_QP_OPTPAR_RRE            |
3298                                           MLX5_QP_OPTPAR_RAE            |
3299                                           MLX5_QP_OPTPAR_RWE            |
3300                                           MLX5_QP_OPTPAR_PM_STATE       |
3301                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3302                 },
3303         },
3304         [MLX5_QP_STATE_RTS] = {
3305                 [MLX5_QP_STATE_RTS] = {
3306                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3307                                           MLX5_QP_OPTPAR_RAE            |
3308                                           MLX5_QP_OPTPAR_RWE            |
3309                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3310                                           MLX5_QP_OPTPAR_PM_STATE       |
3311                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3312                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3313                                           MLX5_QP_OPTPAR_PM_STATE       |
3314                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3315                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3316                                           MLX5_QP_OPTPAR_SRQN           |
3317                                           MLX5_QP_OPTPAR_CQN_RCV,
3318                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3319                                           MLX5_QP_OPTPAR_RAE            |
3320                                           MLX5_QP_OPTPAR_RWE            |
3321                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3322                                           MLX5_QP_OPTPAR_PM_STATE       |
3323                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3324                 },
3325         },
3326         [MLX5_QP_STATE_SQER] = {
3327                 [MLX5_QP_STATE_RTS] = {
3328                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3329                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3330                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3331                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3332                                            MLX5_QP_OPTPAR_RWE           |
3333                                            MLX5_QP_OPTPAR_RAE           |
3334                                            MLX5_QP_OPTPAR_RRE,
3335                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
3336                                            MLX5_QP_OPTPAR_RWE           |
3337                                            MLX5_QP_OPTPAR_RAE           |
3338                                            MLX5_QP_OPTPAR_RRE,
3339                 },
3340         },
3341 };
3342
3343 static int ib_nr_to_mlx5_nr(int ib_mask)
3344 {
3345         switch (ib_mask) {
3346         case IB_QP_STATE:
3347                 return 0;
3348         case IB_QP_CUR_STATE:
3349                 return 0;
3350         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3351                 return 0;
3352         case IB_QP_ACCESS_FLAGS:
3353                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3354                         MLX5_QP_OPTPAR_RAE;
3355         case IB_QP_PKEY_INDEX:
3356                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3357         case IB_QP_PORT:
3358                 return MLX5_QP_OPTPAR_PRI_PORT;
3359         case IB_QP_QKEY:
3360                 return MLX5_QP_OPTPAR_Q_KEY;
3361         case IB_QP_AV:
3362                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3363                         MLX5_QP_OPTPAR_PRI_PORT;
3364         case IB_QP_PATH_MTU:
3365                 return 0;
3366         case IB_QP_TIMEOUT:
3367                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3368         case IB_QP_RETRY_CNT:
3369                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3370         case IB_QP_RNR_RETRY:
3371                 return MLX5_QP_OPTPAR_RNR_RETRY;
3372         case IB_QP_RQ_PSN:
3373                 return 0;
3374         case IB_QP_MAX_QP_RD_ATOMIC:
3375                 return MLX5_QP_OPTPAR_SRA_MAX;
3376         case IB_QP_ALT_PATH:
3377                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3378         case IB_QP_MIN_RNR_TIMER:
3379                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3380         case IB_QP_SQ_PSN:
3381                 return 0;
3382         case IB_QP_MAX_DEST_RD_ATOMIC:
3383                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3384                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3385         case IB_QP_PATH_MIG_STATE:
3386                 return MLX5_QP_OPTPAR_PM_STATE;
3387         case IB_QP_CAP:
3388                 return 0;
3389         case IB_QP_DEST_QPN:
3390                 return 0;
3391         }
3392         return 0;
3393 }
3394
3395 static int ib_mask_to_mlx5_opt(int ib_mask)
3396 {
3397         int result = 0;
3398         int i;
3399
3400         for (i = 0; i < 8 * sizeof(int); i++) {
3401                 if ((1 << i) & ib_mask)
3402                         result |= ib_nr_to_mlx5_nr(1 << i);
3403         }
3404
3405         return result;
3406 }
3407
3408 static int modify_raw_packet_qp_rq(
3409         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3410         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3411 {
3412         void *in;
3413         void *rqc;
3414         int inlen;
3415         int err;
3416
3417         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3418         in = kvzalloc(inlen, GFP_KERNEL);
3419         if (!in)
3420                 return -ENOMEM;
3421
3422         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3423         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3424
3425         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3426         MLX5_SET(rqc, rqc, state, new_state);
3427
3428         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3429                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3430                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3431                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3432                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3433                 } else
3434                         dev_info_once(
3435                                 &dev->ib_dev.dev,
3436                                 "RAW PACKET QP counters are not supported on current FW\n");
3437         }
3438
3439         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3440         if (err)
3441                 goto out;
3442
3443         rq->state = new_state;
3444
3445 out:
3446         kvfree(in);
3447         return err;
3448 }
3449
3450 static int modify_raw_packet_qp_sq(
3451         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3452         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3453 {
3454         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3455         struct mlx5_rate_limit old_rl = ibqp->rl;
3456         struct mlx5_rate_limit new_rl = old_rl;
3457         bool new_rate_added = false;
3458         u16 rl_index = 0;
3459         void *in;
3460         void *sqc;
3461         int inlen;
3462         int err;
3463
3464         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3465         in = kvzalloc(inlen, GFP_KERNEL);
3466         if (!in)
3467                 return -ENOMEM;
3468
3469         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3470         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3471
3472         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3473         MLX5_SET(sqc, sqc, state, new_state);
3474
3475         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3476                 if (new_state != MLX5_SQC_STATE_RDY)
3477                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3478                                 __func__);
3479                 else
3480                         new_rl = raw_qp_param->rl;
3481         }
3482
3483         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3484                 if (new_rl.rate) {
3485                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3486                         if (err) {
3487                                 pr_err("Failed configuring rate limit(err %d): \
3488                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3489                                        err, new_rl.rate, new_rl.max_burst_sz,
3490                                        new_rl.typical_pkt_sz);
3491
3492                                 goto out;
3493                         }
3494                         new_rate_added = true;
3495                 }
3496
3497                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3498                 /* index 0 means no limit */
3499                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3500         }
3501
3502         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
3503         if (err) {
3504                 /* Remove new rate from table if failed */
3505                 if (new_rate_added)
3506                         mlx5_rl_remove_rate(dev, &new_rl);
3507                 goto out;
3508         }
3509
3510         /* Only remove the old rate after new rate was set */
3511         if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3512             (new_state != MLX5_SQC_STATE_RDY)) {
3513                 mlx5_rl_remove_rate(dev, &old_rl);
3514                 if (new_state != MLX5_SQC_STATE_RDY)
3515                         memset(&new_rl, 0, sizeof(new_rl));
3516         }
3517
3518         ibqp->rl = new_rl;
3519         sq->state = new_state;
3520
3521 out:
3522         kvfree(in);
3523         return err;
3524 }
3525
3526 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3527                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3528                                 u8 tx_affinity)
3529 {
3530         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3531         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3532         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3533         int modify_rq = !!qp->rq.wqe_cnt;
3534         int modify_sq = !!qp->sq.wqe_cnt;
3535         int rq_state;
3536         int sq_state;
3537         int err;
3538
3539         switch (raw_qp_param->operation) {
3540         case MLX5_CMD_OP_RST2INIT_QP:
3541                 rq_state = MLX5_RQC_STATE_RDY;
3542                 sq_state = MLX5_SQC_STATE_RDY;
3543                 break;
3544         case MLX5_CMD_OP_2ERR_QP:
3545                 rq_state = MLX5_RQC_STATE_ERR;
3546                 sq_state = MLX5_SQC_STATE_ERR;
3547                 break;
3548         case MLX5_CMD_OP_2RST_QP:
3549                 rq_state = MLX5_RQC_STATE_RST;
3550                 sq_state = MLX5_SQC_STATE_RST;
3551                 break;
3552         case MLX5_CMD_OP_RTR2RTS_QP:
3553         case MLX5_CMD_OP_RTS2RTS_QP:
3554                 if (raw_qp_param->set_mask ==
3555                     MLX5_RAW_QP_RATE_LIMIT) {
3556                         modify_rq = 0;
3557                         sq_state = sq->state;
3558                 } else {
3559                         return raw_qp_param->set_mask ? -EINVAL : 0;
3560                 }
3561                 break;
3562         case MLX5_CMD_OP_INIT2INIT_QP:
3563         case MLX5_CMD_OP_INIT2RTR_QP:
3564                 if (raw_qp_param->set_mask)
3565                         return -EINVAL;
3566                 else
3567                         return 0;
3568         default:
3569                 WARN_ON(1);
3570                 return -EINVAL;
3571         }
3572
3573         if (modify_rq) {
3574                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3575                                                qp->ibqp.pd);
3576                 if (err)
3577                         return err;
3578         }
3579
3580         if (modify_sq) {
3581                 struct mlx5_flow_handle *flow_rule;
3582
3583                 if (tx_affinity) {
3584                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3585                                                             tx_affinity,
3586                                                             qp->ibqp.pd);
3587                         if (err)
3588                                 return err;
3589                 }
3590
3591                 flow_rule = create_flow_rule_vport_sq(dev, sq,
3592                                                       raw_qp_param->port);
3593                 if (IS_ERR(flow_rule))
3594                         return PTR_ERR(flow_rule);
3595
3596                 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3597                                               raw_qp_param, qp->ibqp.pd);
3598                 if (err) {
3599                         if (flow_rule)
3600                                 mlx5_del_flow_rules(flow_rule);
3601                         return err;
3602                 }
3603
3604                 if (flow_rule) {
3605                         destroy_flow_rule_vport_sq(sq);
3606                         sq->flow_rule = flow_rule;
3607                 }
3608
3609                 return err;
3610         }
3611
3612         return 0;
3613 }
3614
3615 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev,
3616                                        struct ib_udata *udata)
3617 {
3618         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3619                 udata, struct mlx5_ib_ucontext, ibucontext);
3620         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3621         atomic_t *tx_port_affinity;
3622
3623         if (ucontext)
3624                 tx_port_affinity = &ucontext->tx_port_affinity;
3625         else
3626                 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity;
3627
3628         return (unsigned int)atomic_add_return(1, tx_port_affinity) %
3629                 MLX5_MAX_PORTS + 1;
3630 }
3631
3632 static bool qp_supports_affinity(struct ib_qp *qp)
3633 {
3634         if ((qp->qp_type == IB_QPT_RC) ||
3635             (qp->qp_type == IB_QPT_UD) ||
3636             (qp->qp_type == IB_QPT_UC) ||
3637             (qp->qp_type == IB_QPT_RAW_PACKET) ||
3638             (qp->qp_type == IB_QPT_XRC_INI) ||
3639             (qp->qp_type == IB_QPT_XRC_TGT))
3640                 return true;
3641         return false;
3642 }
3643
3644 static unsigned int get_tx_affinity(struct ib_qp *qp,
3645                                     const struct ib_qp_attr *attr,
3646                                     int attr_mask, u8 init,
3647                                     struct ib_udata *udata)
3648 {
3649         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3650                 udata, struct mlx5_ib_ucontext, ibucontext);
3651         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3652         struct mlx5_ib_qp *mqp = to_mqp(qp);
3653         struct mlx5_ib_qp_base *qp_base;
3654         unsigned int tx_affinity;
3655
3656         if (!(dev->lag_active && qp_supports_affinity(qp)))
3657                 return 0;
3658
3659         if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3660                 tx_affinity = mqp->gsi_lag_port;
3661         else if (init)
3662                 tx_affinity = get_tx_affinity_rr(dev, udata);
3663         else if ((attr_mask & IB_QP_AV) && attr->xmit_slave)
3664                 tx_affinity =
3665                         mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave);
3666         else
3667                 return 0;
3668
3669         qp_base = &mqp->trans_qp.base;
3670         if (ucontext)
3671                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3672                             tx_affinity, qp_base->mqp.qpn, ucontext);
3673         else
3674                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3675                             tx_affinity, qp_base->mqp.qpn);
3676         return tx_affinity;
3677 }
3678
3679 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3680                                     struct rdma_counter *counter)
3681 {
3682         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3683         u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {};
3684         struct mlx5_ib_qp *mqp = to_mqp(qp);
3685         struct mlx5_ib_qp_base *base;
3686         u32 set_id;
3687         u32 *qpc;
3688
3689         if (counter)
3690                 set_id = counter->id;
3691         else
3692                 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3693
3694         base = &mqp->trans_qp.base;
3695         MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);
3696         MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn);
3697         MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid);
3698         MLX5_SET(rts2rts_qp_in, in, opt_param_mask,
3699                  MLX5_QP_OPTPAR_COUNTER_SET_ID);
3700
3701         qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc);
3702         MLX5_SET(qpc, qpc, counter_set_id, set_id);
3703         return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in);
3704 }
3705
3706 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3707                                const struct ib_qp_attr *attr, int attr_mask,
3708                                enum ib_qp_state cur_state,
3709                                enum ib_qp_state new_state,
3710                                const struct mlx5_ib_modify_qp *ucmd,
3711                                struct ib_udata *udata)
3712 {
3713         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3714                 [MLX5_QP_STATE_RST] = {
3715                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3716                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3717                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3718                 },
3719                 [MLX5_QP_STATE_INIT]  = {
3720                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3721                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3722                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3723                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3724                 },
3725                 [MLX5_QP_STATE_RTR]   = {
3726                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3727                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3728                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3729                 },
3730                 [MLX5_QP_STATE_RTS]   = {
3731                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3732                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3733                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3734                 },
3735                 [MLX5_QP_STATE_SQD] = {
3736                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3737                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3738                 },
3739                 [MLX5_QP_STATE_SQER] = {
3740                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3741                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3742                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3743                 },
3744                 [MLX5_QP_STATE_ERR] = {
3745                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3746                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3747                 }
3748         };
3749
3750         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3751         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3752         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3753         struct mlx5_ib_cq *send_cq, *recv_cq;
3754         struct mlx5_ib_pd *pd;
3755         enum mlx5_qp_state mlx5_cur, mlx5_new;
3756         void *qpc, *pri_path, *alt_path;
3757         enum mlx5_qp_optpar optpar = 0;
3758         u32 set_id = 0;
3759         int mlx5_st;
3760         int err;
3761         u16 op;
3762         u8 tx_affinity = 0;
3763
3764         mlx5_st = to_mlx5_st(qp->type);
3765         if (mlx5_st < 0)
3766                 return -EINVAL;
3767
3768         qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
3769         if (!qpc)
3770                 return -ENOMEM;
3771
3772         pd = to_mpd(qp->ibqp.pd);
3773         MLX5_SET(qpc, qpc, st, mlx5_st);
3774
3775         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3776                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
3777         } else {
3778                 switch (attr->path_mig_state) {
3779                 case IB_MIG_MIGRATED:
3780                         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
3781                         break;
3782                 case IB_MIG_REARM:
3783                         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM);
3784                         break;
3785                 case IB_MIG_ARMED:
3786                         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED);
3787                         break;
3788                 }
3789         }
3790
3791         tx_affinity = get_tx_affinity(ibqp, attr, attr_mask,
3792                                       cur_state == IB_QPS_RESET &&
3793                                       new_state == IB_QPS_INIT, udata);
3794
3795         MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity);
3796         if (tx_affinity && new_state == IB_QPS_RTR &&
3797             MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
3798                 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
3799
3800         if (is_sqp(ibqp->qp_type)) {
3801                 MLX5_SET(qpc, qpc, mtu, IB_MTU_256);
3802                 MLX5_SET(qpc, qpc, log_msg_max, 8);
3803         } else if ((ibqp->qp_type == IB_QPT_UD &&
3804                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
3805                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3806                 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096);
3807                 MLX5_SET(qpc, qpc, log_msg_max, 12);
3808         } else if (attr_mask & IB_QP_PATH_MTU) {
3809                 if (attr->path_mtu < IB_MTU_256 ||
3810                     attr->path_mtu > IB_MTU_4096) {
3811                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3812                         err = -EINVAL;
3813                         goto out;
3814                 }
3815                 MLX5_SET(qpc, qpc, mtu, attr->path_mtu);
3816                 MLX5_SET(qpc, qpc, log_msg_max,
3817                          MLX5_CAP_GEN(dev->mdev, log_max_msg));
3818         }
3819
3820         if (attr_mask & IB_QP_DEST_QPN)
3821                 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num);
3822
3823         pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
3824         alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
3825
3826         if (attr_mask & IB_QP_PKEY_INDEX)
3827                 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index);
3828
3829         /* todo implement counter_index functionality */
3830
3831         if (is_sqp(ibqp->qp_type))
3832                 MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
3833
3834         if (attr_mask & IB_QP_PORT)
3835                 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num);
3836
3837         if (attr_mask & IB_QP_AV) {
3838                 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path,
3839                                     attr_mask & IB_QP_PORT ? attr->port_num :
3840                                                              qp->port,
3841                                     attr_mask, 0, attr, false);
3842                 if (err)
3843                         goto out;
3844         }
3845
3846         if (attr_mask & IB_QP_TIMEOUT)
3847                 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout);
3848
3849         if (attr_mask & IB_QP_ALT_PATH) {
3850                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path,
3851                                     attr->alt_port_num,
3852                                     attr_mask | IB_QP_PKEY_INDEX |
3853                                             IB_QP_TIMEOUT,
3854                                     0, attr, true);
3855                 if (err)
3856                         goto out;
3857         }
3858
3859         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3860                 &send_cq, &recv_cq);
3861
3862         MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3863         if (send_cq)
3864                 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn);
3865         if (recv_cq)
3866                 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn);
3867
3868         MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ);
3869
3870         if (attr_mask & IB_QP_RNR_RETRY)
3871                 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
3872
3873         if (attr_mask & IB_QP_RETRY_CNT)
3874                 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
3875
3876         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)
3877                 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));
3878
3879         if (attr_mask & IB_QP_SQ_PSN)
3880                 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);
3881
3882         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)
3883                 MLX5_SET(qpc, qpc, log_rra_max,
3884                          ilog2(attr->max_dest_rd_atomic));
3885
3886         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3887                 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);
3888                 if (err)
3889                         goto out;
3890         }
3891
3892         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3893                 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer);
3894
3895         if (attr_mask & IB_QP_RQ_PSN)
3896                 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn);
3897
3898         if (attr_mask & IB_QP_QKEY)
3899                 MLX5_SET(qpc, qpc, q_key, attr->qkey);
3900
3901         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3902                 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
3903
3904         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3905                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3906                                qp->port) - 1;
3907
3908                 /* Underlay port should be used - index 0 function per port */
3909                 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
3910                         port_num = 0;
3911
3912                 if (ibqp->counter)
3913                         set_id = ibqp->counter->id;
3914                 else
3915                         set_id = mlx5_ib_get_counters_id(dev, port_num);
3916                 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3917         }
3918
3919         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3920                 MLX5_SET(qpc, qpc, rlky, 1);
3921
3922         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3923                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
3924
3925         mlx5_cur = to_mlx5_state(cur_state);
3926         mlx5_new = to_mlx5_state(new_state);
3927
3928         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3929             !optab[mlx5_cur][mlx5_new]) {
3930                 err = -EINVAL;
3931                 goto out;
3932         }
3933
3934         op = optab[mlx5_cur][mlx5_new];
3935         optpar |= ib_mask_to_mlx5_opt(attr_mask);
3936         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3937
3938         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3939             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
3940                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3941
3942                 raw_qp_param.operation = op;
3943                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3944                         raw_qp_param.rq_q_ctr_id = set_id;
3945                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3946                 }
3947
3948                 if (attr_mask & IB_QP_PORT)
3949                         raw_qp_param.port = attr->port_num;
3950
3951                 if (attr_mask & IB_QP_RATE_LIMIT) {
3952                         raw_qp_param.rl.rate = attr->rate_limit;
3953
3954                         if (ucmd->burst_info.max_burst_sz) {
3955                                 if (attr->rate_limit &&
3956                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3957                                         raw_qp_param.rl.max_burst_sz =
3958                                                 ucmd->burst_info.max_burst_sz;
3959                                 } else {
3960                                         err = -EINVAL;
3961                                         goto out;
3962                                 }
3963                         }
3964
3965                         if (ucmd->burst_info.typical_pkt_sz) {
3966                                 if (attr->rate_limit &&
3967                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3968                                         raw_qp_param.rl.typical_pkt_sz =
3969                                                 ucmd->burst_info.typical_pkt_sz;
3970                                 } else {
3971                                         err = -EINVAL;
3972                                         goto out;
3973                                 }
3974                         }
3975
3976                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3977                 }
3978
3979                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3980         } else {
3981                 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp);
3982         }
3983
3984         if (err)
3985                 goto out;
3986
3987         qp->state = new_state;
3988
3989         if (attr_mask & IB_QP_ACCESS_FLAGS)
3990                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3991         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3992                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3993         if (attr_mask & IB_QP_PORT)
3994                 qp->port = attr->port_num;
3995         if (attr_mask & IB_QP_ALT_PATH)
3996                 qp->trans_qp.alt_port = attr->alt_port_num;
3997
3998         /*
3999          * If we moved a kernel QP to RESET, clean up all old CQ
4000          * entries and reinitialize the QP.
4001          */
4002         if (new_state == IB_QPS_RESET &&
4003             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
4004                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
4005                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
4006                 if (send_cq != recv_cq)
4007                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
4008
4009                 qp->rq.head = 0;
4010                 qp->rq.tail = 0;
4011                 qp->sq.head = 0;
4012                 qp->sq.tail = 0;
4013                 qp->sq.cur_post = 0;
4014                 if (qp->sq.wqe_cnt)
4015                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
4016                 qp->sq.last_poll = 0;
4017                 qp->db.db[MLX5_RCV_DBR] = 0;
4018                 qp->db.db[MLX5_SND_DBR] = 0;
4019         }
4020
4021         if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
4022                 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
4023                 if (!err)
4024                         qp->counter_pending = 0;
4025         }
4026
4027 out:
4028         kfree(qpc);
4029         return err;
4030 }
4031
4032 static inline bool is_valid_mask(int mask, int req, int opt)
4033 {
4034         if ((mask & req) != req)
4035                 return false;
4036
4037         if (mask & ~(req | opt))
4038                 return false;
4039
4040         return true;
4041 }
4042
4043 /* check valid transition for driver QP types
4044  * for now the only QP type that this function supports is DCI
4045  */
4046 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
4047                                 enum ib_qp_attr_mask attr_mask)
4048 {
4049         int req = IB_QP_STATE;
4050         int opt = 0;
4051
4052         if (new_state == IB_QPS_RESET) {
4053                 return is_valid_mask(attr_mask, req, opt);
4054         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4055                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
4056                 return is_valid_mask(attr_mask, req, opt);
4057         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4058                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
4059                 return is_valid_mask(attr_mask, req, opt);
4060         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4061                 req |= IB_QP_PATH_MTU;
4062                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
4063                 return is_valid_mask(attr_mask, req, opt);
4064         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4065                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
4066                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
4067                 opt = IB_QP_MIN_RNR_TIMER;
4068                 return is_valid_mask(attr_mask, req, opt);
4069         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
4070                 opt = IB_QP_MIN_RNR_TIMER;
4071                 return is_valid_mask(attr_mask, req, opt);
4072         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
4073                 return is_valid_mask(attr_mask, req, opt);
4074         }
4075         return false;
4076 }
4077
4078 /* mlx5_ib_modify_dct: modify a DCT QP
4079  * valid transitions are:
4080  * RESET to INIT: must set access_flags, pkey_index and port
4081  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
4082  *                         mtu, gid_index and hop_limit
4083  * Other transitions and attributes are illegal
4084  */
4085 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4086                               int attr_mask, struct ib_udata *udata)
4087 {
4088         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4089         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4090         enum ib_qp_state cur_state, new_state;
4091         int err = 0;
4092         int required = IB_QP_STATE;
4093         void *dctc;
4094
4095         if (!(attr_mask & IB_QP_STATE))
4096                 return -EINVAL;
4097
4098         cur_state = qp->state;
4099         new_state = attr->qp_state;
4100
4101         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
4102         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4103                 u16 set_id;
4104
4105                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
4106                 if (!is_valid_mask(attr_mask, required, 0))
4107                         return -EINVAL;
4108
4109                 if (attr->port_num == 0 ||
4110                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
4111                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4112                                     attr->port_num, dev->num_ports);
4113                         return -EINVAL;
4114                 }
4115                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
4116                         MLX5_SET(dctc, dctc, rre, 1);
4117                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
4118                         MLX5_SET(dctc, dctc, rwe, 1);
4119                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
4120                         int atomic_mode;
4121
4122                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
4123                         if (atomic_mode < 0)
4124                                 return -EOPNOTSUPP;
4125
4126                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
4127                         MLX5_SET(dctc, dctc, rae, 1);
4128                 }
4129                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
4130                 MLX5_SET(dctc, dctc, port, attr->port_num);
4131
4132                 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
4133                 MLX5_SET(dctc, dctc, counter_set_id, set_id);
4134
4135         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4136                 struct mlx5_ib_modify_qp_resp resp = {};
4137                 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
4138                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
4139                                    sizeof(resp.dctn);
4140
4141                 if (udata->outlen < min_resp_len)
4142                         return -EINVAL;
4143                 resp.response_length = min_resp_len;
4144
4145                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
4146                 if (!is_valid_mask(attr_mask, required, 0))
4147                         return -EINVAL;
4148                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
4149                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
4150                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
4151                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
4152                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
4153                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
4154
4155                 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
4156                                            MLX5_ST_SZ_BYTES(create_dct_in), out,
4157                                            sizeof(out));
4158                 if (err)
4159                         return err;
4160                 resp.dctn = qp->dct.mdct.mqp.qpn;
4161                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4162                 if (err) {
4163                         mlx5_core_destroy_dct(dev, &qp->dct.mdct);
4164                         return err;
4165                 }
4166         } else {
4167                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
4168                 return -EINVAL;
4169         }
4170         if (err)
4171                 qp->state = IB_QPS_ERR;
4172         else
4173                 qp->state = new_state;
4174         return err;
4175 }
4176
4177 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4178                       int attr_mask, struct ib_udata *udata)
4179 {
4180         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4181         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4182         struct mlx5_ib_modify_qp ucmd = {};
4183         enum ib_qp_type qp_type;
4184         enum ib_qp_state cur_state, new_state;
4185         size_t required_cmd_sz;
4186         int err = -EINVAL;
4187         int port;
4188
4189         if (ibqp->rwq_ind_tbl)
4190                 return -ENOSYS;
4191
4192         if (udata && udata->inlen) {
4193                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4194                         sizeof(ucmd.reserved);
4195                 if (udata->inlen < required_cmd_sz)
4196                         return -EINVAL;
4197
4198                 if (udata->inlen > sizeof(ucmd) &&
4199                     !ib_is_udata_cleared(udata, sizeof(ucmd),
4200                                          udata->inlen - sizeof(ucmd)))
4201                         return -EOPNOTSUPP;
4202
4203                 if (ib_copy_from_udata(&ucmd, udata,
4204                                        min(udata->inlen, sizeof(ucmd))))
4205                         return -EFAULT;
4206
4207                 if (ucmd.comp_mask ||
4208                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
4209                     memchr_inv(&ucmd.burst_info.reserved, 0,
4210                                sizeof(ucmd.burst_info.reserved)))
4211                         return -EOPNOTSUPP;
4212         }
4213
4214         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4215                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
4216
4217         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
4218                                                                     qp->type;
4219
4220         if (qp_type == MLX5_IB_QPT_DCT)
4221                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
4222
4223         mutex_lock(&qp->mutex);
4224
4225         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
4226         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
4227
4228         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
4229                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4230         }
4231
4232         if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4233                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4234                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4235                                     attr_mask);
4236                         goto out;
4237                 }
4238         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
4239                    qp_type != MLX5_IB_QPT_DCI &&
4240                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4241                                        attr_mask)) {
4242                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4243                             cur_state, new_state, ibqp->qp_type, attr_mask);
4244                 goto out;
4245         } else if (qp_type == MLX5_IB_QPT_DCI &&
4246                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4247                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4248                             cur_state, new_state, qp_type, attr_mask);
4249                 goto out;
4250         }
4251
4252         if ((attr_mask & IB_QP_PORT) &&
4253             (attr->port_num == 0 ||
4254              attr->port_num > dev->num_ports)) {
4255                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4256                             attr->port_num, dev->num_ports);
4257                 goto out;
4258         }
4259
4260         if (attr_mask & IB_QP_PKEY_INDEX) {
4261                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4262                 if (attr->pkey_index >=
4263                     dev->mdev->port_caps[port - 1].pkey_table_len) {
4264                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4265                                     attr->pkey_index);
4266                         goto out;
4267                 }
4268         }
4269
4270         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
4271             attr->max_rd_atomic >
4272             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4273                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4274                             attr->max_rd_atomic);
4275                 goto out;
4276         }
4277
4278         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
4279             attr->max_dest_rd_atomic >
4280             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4281                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4282                             attr->max_dest_rd_atomic);
4283                 goto out;
4284         }
4285
4286         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4287                 err = 0;
4288                 goto out;
4289         }
4290
4291         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4292                                   new_state, &ucmd, udata);
4293
4294 out:
4295         mutex_unlock(&qp->mutex);
4296         return err;
4297 }
4298
4299 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4300 {
4301         switch (mlx5_state) {
4302         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4303         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4304         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4305         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4306         case MLX5_QP_STATE_SQ_DRAINING:
4307         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4308         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4309         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4310         default:                     return -1;
4311         }
4312 }
4313
4314 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4315 {
4316         switch (mlx5_mig_state) {
4317         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4318         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4319         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4320         default: return -1;
4321         }
4322 }
4323
4324 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4325                             struct rdma_ah_attr *ah_attr, void *path)
4326 {
4327         int port = MLX5_GET(ads, path, vhca_port_num);
4328         int static_rate;
4329
4330         memset(ah_attr, 0, sizeof(*ah_attr));
4331
4332         if (!port || port > ibdev->num_ports)
4333                 return;
4334
4335         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port);
4336
4337         rdma_ah_set_port_num(ah_attr, port);
4338         rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl));
4339
4340         rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid));
4341         rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid));
4342
4343         static_rate = MLX5_GET(ads, path, stat_rate);
4344         rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0);
4345         if (MLX5_GET(ads, path, grh) ||
4346             ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
4347                 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label),
4348                                 MLX5_GET(ads, path, src_addr_index),
4349                                 MLX5_GET(ads, path, hop_limit),
4350                                 MLX5_GET(ads, path, tclass));
4351                 memcpy(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip),
4352                        MLX5_FLD_SZ_BYTES(ads, rgid_rip));
4353         }
4354 }
4355
4356 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4357                                         struct mlx5_ib_sq *sq,
4358                                         u8 *sq_state)
4359 {
4360         int err;
4361
4362         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4363         if (err)
4364                 goto out;
4365         sq->state = *sq_state;
4366
4367 out:
4368         return err;
4369 }
4370
4371 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4372                                         struct mlx5_ib_rq *rq,
4373                                         u8 *rq_state)
4374 {
4375         void *out;
4376         void *rqc;
4377         int inlen;
4378         int err;
4379
4380         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4381         out = kvzalloc(inlen, GFP_KERNEL);
4382         if (!out)
4383                 return -ENOMEM;
4384
4385         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4386         if (err)
4387                 goto out;
4388
4389         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4390         *rq_state = MLX5_GET(rqc, rqc, state);
4391         rq->state = *rq_state;
4392
4393 out:
4394         kvfree(out);
4395         return err;
4396 }
4397
4398 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4399                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4400 {
4401         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4402                 [MLX5_RQC_STATE_RST] = {
4403                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4404                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4405                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4406                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4407                 },
4408                 [MLX5_RQC_STATE_RDY] = {
4409                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4410                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4411                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4412                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4413                 },
4414                 [MLX5_RQC_STATE_ERR] = {
4415                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4416                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4417                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4418                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4419                 },
4420                 [MLX5_RQ_STATE_NA] = {
4421                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4422                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4423                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4424                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4425                 },
4426         };
4427
4428         *qp_state = sqrq_trans[rq_state][sq_state];
4429
4430         if (*qp_state == MLX5_QP_STATE_BAD) {
4431                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4432                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4433                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4434                 return -EINVAL;
4435         }
4436
4437         if (*qp_state == MLX5_QP_STATE)
4438                 *qp_state = qp->state;
4439
4440         return 0;
4441 }
4442
4443 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4444                                      struct mlx5_ib_qp *qp,
4445                                      u8 *raw_packet_qp_state)
4446 {
4447         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4448         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4449         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4450         int err;
4451         u8 sq_state = MLX5_SQ_STATE_NA;
4452         u8 rq_state = MLX5_RQ_STATE_NA;
4453
4454         if (qp->sq.wqe_cnt) {
4455                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4456                 if (err)
4457                         return err;
4458         }
4459
4460         if (qp->rq.wqe_cnt) {
4461                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4462                 if (err)
4463                         return err;
4464         }
4465
4466         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4467                                       raw_packet_qp_state);
4468 }
4469
4470 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4471                          struct ib_qp_attr *qp_attr)
4472 {
4473         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4474         void *qpc, *pri_path, *alt_path;
4475         u32 *outb;
4476         int err;
4477
4478         outb = kzalloc(outlen, GFP_KERNEL);
4479         if (!outb)
4480                 return -ENOMEM;
4481
4482         err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
4483         if (err)
4484                 goto out;
4485
4486         qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc);
4487
4488         qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state));
4489         if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING)
4490                 qp_attr->sq_draining = 1;
4491
4492         qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu);
4493         qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state));
4494         qp_attr->qkey = MLX5_GET(qpc, qpc, q_key);
4495         qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn);
4496         qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn);
4497         qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn);
4498
4499         if (MLX5_GET(qpc, qpc, rre))
4500                 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ;
4501         if (MLX5_GET(qpc, qpc, rwe))
4502                 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE;
4503         if (MLX5_GET(qpc, qpc, rae))
4504                 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4505
4506         qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max);
4507         qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max);
4508         qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak);
4509         qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count);
4510         qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry);
4511
4512         pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
4513         alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
4514
4515         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4516                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path);
4517                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path);
4518                 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index);
4519                 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num);
4520         }
4521
4522         qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index);
4523         qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num);
4524         qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout);
4525         qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout);
4526
4527 out:
4528         kfree(outb);
4529         return err;
4530 }
4531
4532 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4533                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4534                                 struct ib_qp_init_attr *qp_init_attr)
4535 {
4536         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
4537         u32 *out;
4538         u32 access_flags = 0;
4539         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4540         void *dctc;
4541         int err;
4542         int supported_mask = IB_QP_STATE |
4543                              IB_QP_ACCESS_FLAGS |
4544                              IB_QP_PORT |
4545                              IB_QP_MIN_RNR_TIMER |
4546                              IB_QP_AV |
4547                              IB_QP_PATH_MTU |
4548                              IB_QP_PKEY_INDEX;
4549
4550         if (qp_attr_mask & ~supported_mask)
4551                 return -EINVAL;
4552         if (mqp->state != IB_QPS_RTR)
4553                 return -EINVAL;
4554
4555         out = kzalloc(outlen, GFP_KERNEL);
4556         if (!out)
4557                 return -ENOMEM;
4558
4559         err = mlx5_core_dct_query(dev, dct, out, outlen);
4560         if (err)
4561                 goto out;
4562
4563         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4564
4565         if (qp_attr_mask & IB_QP_STATE)
4566                 qp_attr->qp_state = IB_QPS_RTR;
4567
4568         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4569                 if (MLX5_GET(dctc, dctc, rre))
4570                         access_flags |= IB_ACCESS_REMOTE_READ;
4571                 if (MLX5_GET(dctc, dctc, rwe))
4572                         access_flags |= IB_ACCESS_REMOTE_WRITE;
4573                 if (MLX5_GET(dctc, dctc, rae))
4574                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4575                 qp_attr->qp_access_flags = access_flags;
4576         }
4577
4578         if (qp_attr_mask & IB_QP_PORT)
4579                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4580         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4581                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4582         if (qp_attr_mask & IB_QP_AV) {
4583                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4584                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4585                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4586                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4587         }
4588         if (qp_attr_mask & IB_QP_PATH_MTU)
4589                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4590         if (qp_attr_mask & IB_QP_PKEY_INDEX)
4591                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4592 out:
4593         kfree(out);
4594         return err;
4595 }
4596
4597 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4598                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4599 {
4600         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4601         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4602         int err = 0;
4603         u8 raw_packet_qp_state;
4604
4605         if (ibqp->rwq_ind_tbl)
4606                 return -ENOSYS;
4607
4608         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4609                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4610                                             qp_init_attr);
4611
4612         /* Not all of output fields are applicable, make sure to zero them */
4613         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4614         memset(qp_attr, 0, sizeof(*qp_attr));
4615
4616         if (unlikely(qp->type == MLX5_IB_QPT_DCT))
4617                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4618                                             qp_attr_mask, qp_init_attr);
4619
4620         mutex_lock(&qp->mutex);
4621
4622         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4623             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4624                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4625                 if (err)
4626                         goto out;
4627                 qp->state = raw_packet_qp_state;
4628                 qp_attr->port_num = 1;
4629         } else {
4630                 err = query_qp_attr(dev, qp, qp_attr);
4631                 if (err)
4632                         goto out;
4633         }
4634
4635         qp_attr->qp_state            = qp->state;
4636         qp_attr->cur_qp_state        = qp_attr->qp_state;
4637         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4638         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4639
4640         if (!ibqp->uobject) {
4641                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4642                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4643                 qp_init_attr->qp_context = ibqp->qp_context;
4644         } else {
4645                 qp_attr->cap.max_send_wr  = 0;
4646                 qp_attr->cap.max_send_sge = 0;
4647         }
4648
4649         qp_init_attr->qp_type = ibqp->qp_type;
4650         qp_init_attr->recv_cq = ibqp->recv_cq;
4651         qp_init_attr->send_cq = ibqp->send_cq;
4652         qp_init_attr->srq = ibqp->srq;
4653         qp_attr->cap.max_inline_data = qp->max_inline_data;
4654
4655         qp_init_attr->cap            = qp_attr->cap;
4656
4657         qp_init_attr->create_flags = qp->flags;
4658
4659         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4660                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4661
4662 out:
4663         mutex_unlock(&qp->mutex);
4664         return err;
4665 }
4666
4667 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4668                                    struct ib_udata *udata)
4669 {
4670         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4671         struct mlx5_ib_xrcd *xrcd;
4672         int err;
4673
4674         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4675                 return ERR_PTR(-ENOSYS);
4676
4677         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4678         if (!xrcd)
4679                 return ERR_PTR(-ENOMEM);
4680
4681         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
4682         if (err) {
4683                 kfree(xrcd);
4684                 return ERR_PTR(-ENOMEM);
4685         }
4686
4687         return &xrcd->ibxrcd;
4688 }
4689
4690 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
4691 {
4692         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4693         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4694         int err;
4695
4696         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
4697         if (err)
4698                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4699
4700         kfree(xrcd);
4701         return 0;
4702 }
4703
4704 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4705 {
4706         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4707         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4708         struct ib_event event;
4709
4710         if (rwq->ibwq.event_handler) {
4711                 event.device     = rwq->ibwq.device;
4712                 event.element.wq = &rwq->ibwq;
4713                 switch (type) {
4714                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4715                         event.event = IB_EVENT_WQ_FATAL;
4716                         break;
4717                 default:
4718                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4719                         return;
4720                 }
4721
4722                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4723         }
4724 }
4725
4726 static int set_delay_drop(struct mlx5_ib_dev *dev)
4727 {
4728         int err = 0;
4729
4730         mutex_lock(&dev->delay_drop.lock);
4731         if (dev->delay_drop.activate)
4732                 goto out;
4733
4734         err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
4735         if (err)
4736                 goto out;
4737
4738         dev->delay_drop.activate = true;
4739 out:
4740         mutex_unlock(&dev->delay_drop.lock);
4741
4742         if (!err)
4743                 atomic_inc(&dev->delay_drop.rqs_cnt);
4744         return err;
4745 }
4746
4747 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4748                       struct ib_wq_init_attr *init_attr)
4749 {
4750         struct mlx5_ib_dev *dev;
4751         int has_net_offloads;
4752         __be64 *rq_pas0;
4753         void *in;
4754         void *rqc;
4755         void *wq;
4756         int inlen;
4757         int err;
4758
4759         dev = to_mdev(pd->device);
4760
4761         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4762         in = kvzalloc(inlen, GFP_KERNEL);
4763         if (!in)
4764                 return -ENOMEM;
4765
4766         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
4767         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4768         MLX5_SET(rqc,  rqc, mem_rq_type,
4769                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4770         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4771         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4772         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4773         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4774         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4775         MLX5_SET(wq, wq, wq_type,
4776                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4777                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4778         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4779                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4780                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4781                         err = -EOPNOTSUPP;
4782                         goto out;
4783                 } else {
4784                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4785                 }
4786         }
4787         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4788         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4789                 /*
4790                  * In Firmware number of strides in each WQE is:
4791                  *   "512 * 2^single_wqe_log_num_of_strides"
4792                  * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
4793                  * accepted as 0 to 9
4794                  */
4795                 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
4796                                              2,  3,  4,  5,  6,  7,  8, 9 };
4797                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4798                 MLX5_SET(wq, wq, log_wqe_stride_size,
4799                          rwq->single_stride_log_num_of_bytes -
4800                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4801                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
4802                          fw_map[rwq->log_num_strides -
4803                                 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
4804         }
4805         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4806         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4807         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4808         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4809         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4810         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4811         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4812         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4813                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4814                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4815                         err = -EOPNOTSUPP;
4816                         goto out;
4817                 }
4818         } else {
4819                 MLX5_SET(rqc, rqc, vsd, 1);
4820         }
4821         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4822                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4823                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4824                         err = -EOPNOTSUPP;
4825                         goto out;
4826                 }
4827                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4828         }
4829         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4830                 if (!(dev->ib_dev.attrs.raw_packet_caps &
4831                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
4832                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4833                         err = -EOPNOTSUPP;
4834                         goto out;
4835                 }
4836                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4837         }
4838         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4839         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4840         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
4841         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4842                 err = set_delay_drop(dev);
4843                 if (err) {
4844                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4845                                      err);
4846                         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
4847                 } else {
4848                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4849                 }
4850         }
4851 out:
4852         kvfree(in);
4853         return err;
4854 }
4855
4856 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4857                             struct ib_wq_init_attr *wq_init_attr,
4858                             struct mlx5_ib_create_wq *ucmd,
4859                             struct mlx5_ib_rwq *rwq)
4860 {
4861         /* Sanity check RQ size before proceeding */
4862         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4863                 return -EINVAL;
4864
4865         if (!ucmd->rq_wqe_count)
4866                 return -EINVAL;
4867
4868         rwq->wqe_count = ucmd->rq_wqe_count;
4869         rwq->wqe_shift = ucmd->rq_wqe_shift;
4870         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
4871                 return -EINVAL;
4872
4873         rwq->log_rq_stride = rwq->wqe_shift;
4874         rwq->log_rq_size = ilog2(rwq->wqe_count);
4875         return 0;
4876 }
4877
4878 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
4879 {
4880         if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4881             (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4882                 return false;
4883
4884         if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
4885             (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4886                 return false;
4887
4888         return true;
4889 }
4890
4891 static int prepare_user_rq(struct ib_pd *pd,
4892                            struct ib_wq_init_attr *init_attr,
4893                            struct ib_udata *udata,
4894                            struct mlx5_ib_rwq *rwq)
4895 {
4896         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4897         struct mlx5_ib_create_wq ucmd = {};
4898         int err;
4899         size_t required_cmd_sz;
4900
4901         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4902                 + sizeof(ucmd.single_stride_log_num_of_bytes);
4903         if (udata->inlen < required_cmd_sz) {
4904                 mlx5_ib_dbg(dev, "invalid inlen\n");
4905                 return -EINVAL;
4906         }
4907
4908         if (udata->inlen > sizeof(ucmd) &&
4909             !ib_is_udata_cleared(udata, sizeof(ucmd),
4910                                  udata->inlen - sizeof(ucmd))) {
4911                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4912                 return -EOPNOTSUPP;
4913         }
4914
4915         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4916                 mlx5_ib_dbg(dev, "copy failed\n");
4917                 return -EFAULT;
4918         }
4919
4920         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
4921                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4922                 return -EOPNOTSUPP;
4923         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4924                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4925                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4926                         return -EOPNOTSUPP;
4927                 }
4928                 if ((ucmd.single_stride_log_num_of_bytes <
4929                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4930                     (ucmd.single_stride_log_num_of_bytes >
4931                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4932                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4933                                     ucmd.single_stride_log_num_of_bytes,
4934                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4935                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4936                         return -EINVAL;
4937                 }
4938                 if (!log_of_strides_valid(dev,
4939                                           ucmd.single_wqe_log_num_of_strides)) {
4940                         mlx5_ib_dbg(
4941                                 dev,
4942                                 "Invalid log num strides (%u. Range is %u - %u)\n",
4943                                 ucmd.single_wqe_log_num_of_strides,
4944                                 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
4945                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
4946                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4947                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
4948                         return -EINVAL;
4949                 }
4950                 rwq->single_stride_log_num_of_bytes =
4951                         ucmd.single_stride_log_num_of_bytes;
4952                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4953                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4954                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
4955         }
4956
4957         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4958         if (err) {
4959                 mlx5_ib_dbg(dev, "err %d\n", err);
4960                 return err;
4961         }
4962
4963         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
4964         if (err) {
4965                 mlx5_ib_dbg(dev, "err %d\n", err);
4966                 return err;
4967         }
4968
4969         rwq->user_index = ucmd.user_index;
4970         return 0;
4971 }
4972
4973 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4974                                 struct ib_wq_init_attr *init_attr,
4975                                 struct ib_udata *udata)
4976 {
4977         struct mlx5_ib_dev *dev;
4978         struct mlx5_ib_rwq *rwq;
4979         struct mlx5_ib_create_wq_resp resp = {};
4980         size_t min_resp_len;
4981         int err;
4982
4983         if (!udata)
4984                 return ERR_PTR(-ENOSYS);
4985
4986         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4987         if (udata->outlen && udata->outlen < min_resp_len)
4988                 return ERR_PTR(-EINVAL);
4989
4990         if (!capable(CAP_SYS_RAWIO) &&
4991             init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
4992                 return ERR_PTR(-EPERM);
4993
4994         dev = to_mdev(pd->device);
4995         switch (init_attr->wq_type) {
4996         case IB_WQT_RQ:
4997                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4998                 if (!rwq)
4999                         return ERR_PTR(-ENOMEM);
5000                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5001                 if (err)
5002                         goto err;
5003                 err = create_rq(rwq, pd, init_attr);
5004                 if (err)
5005                         goto err_user_rq;
5006                 break;
5007         default:
5008                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5009                             init_attr->wq_type);
5010                 return ERR_PTR(-EINVAL);
5011         }
5012
5013         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5014         rwq->ibwq.state = IB_WQS_RESET;
5015         if (udata->outlen) {
5016                 resp.response_length = offsetof(typeof(resp), response_length) +
5017                                 sizeof(resp.response_length);
5018                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5019                 if (err)
5020                         goto err_copy;
5021         }
5022
5023         rwq->core_qp.event = mlx5_ib_wq_event;
5024         rwq->ibwq.event_handler = init_attr->event_handler;
5025         return &rwq->ibwq;
5026
5027 err_copy:
5028         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5029 err_user_rq:
5030         destroy_user_rq(dev, pd, rwq, udata);
5031 err:
5032         kfree(rwq);
5033         return ERR_PTR(err);
5034 }
5035
5036 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
5037 {
5038         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5039         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5040
5041         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5042         destroy_user_rq(dev, wq->pd, rwq, udata);
5043         kfree(rwq);
5044 }
5045
5046 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5047                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5048                                                       struct ib_udata *udata)
5049 {
5050         struct mlx5_ib_dev *dev = to_mdev(device);
5051         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5052         int sz = 1 << init_attr->log_ind_tbl_size;
5053         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5054         size_t min_resp_len;
5055         int inlen;
5056         int err;
5057         int i;
5058         u32 *in;
5059         void *rqtc;
5060
5061         if (udata->inlen > 0 &&
5062             !ib_is_udata_cleared(udata, 0,
5063                                  udata->inlen))
5064                 return ERR_PTR(-EOPNOTSUPP);
5065
5066         if (init_attr->log_ind_tbl_size >
5067             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5068                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5069                             init_attr->log_ind_tbl_size,
5070                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5071                 return ERR_PTR(-EINVAL);
5072         }
5073
5074         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5075         if (udata->outlen && udata->outlen < min_resp_len)
5076                 return ERR_PTR(-EINVAL);
5077
5078         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5079         if (!rwq_ind_tbl)
5080                 return ERR_PTR(-ENOMEM);
5081
5082         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5083         in = kvzalloc(inlen, GFP_KERNEL);
5084         if (!in) {
5085                 err = -ENOMEM;
5086                 goto err;
5087         }
5088
5089         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5090
5091         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5092         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5093
5094         for (i = 0; i < sz; i++)
5095                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5096
5097         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5098         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5099
5100         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5101         kvfree(in);
5102
5103         if (err)
5104                 goto err;
5105
5106         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5107         if (udata->outlen) {
5108                 resp.response_length = offsetof(typeof(resp), response_length) +
5109                                         sizeof(resp.response_length);
5110                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5111                 if (err)
5112                         goto err_copy;
5113         }
5114
5115         return &rwq_ind_tbl->ib_rwq_ind_tbl;
5116
5117 err_copy:
5118         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5119 err:
5120         kfree(rwq_ind_tbl);
5121         return ERR_PTR(err);
5122 }
5123
5124 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5125 {
5126         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5127         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5128
5129         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5130
5131         kfree(rwq_ind_tbl);
5132         return 0;
5133 }
5134
5135 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5136                       u32 wq_attr_mask, struct ib_udata *udata)
5137 {
5138         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5139         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5140         struct mlx5_ib_modify_wq ucmd = {};
5141         size_t required_cmd_sz;
5142         int curr_wq_state;
5143         int wq_state;
5144         int inlen;
5145         int err;
5146         void *rqc;
5147         void *in;
5148
5149         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5150         if (udata->inlen < required_cmd_sz)
5151                 return -EINVAL;
5152
5153         if (udata->inlen > sizeof(ucmd) &&
5154             !ib_is_udata_cleared(udata, sizeof(ucmd),
5155                                  udata->inlen - sizeof(ucmd)))
5156                 return -EOPNOTSUPP;
5157
5158         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5159                 return -EFAULT;
5160
5161         if (ucmd.comp_mask || ucmd.reserved)
5162                 return -EOPNOTSUPP;
5163
5164         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5165         in = kvzalloc(inlen, GFP_KERNEL);
5166         if (!in)
5167                 return -ENOMEM;
5168
5169         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5170
5171         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5172                 wq_attr->curr_wq_state : wq->state;
5173         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5174                 wq_attr->wq_state : curr_wq_state;
5175         if (curr_wq_state == IB_WQS_ERR)
5176                 curr_wq_state = MLX5_RQC_STATE_ERR;
5177         if (wq_state == IB_WQS_ERR)
5178                 wq_state = MLX5_RQC_STATE_ERR;
5179         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5180         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
5181         MLX5_SET(rqc, rqc, state, wq_state);
5182
5183         if (wq_attr_mask & IB_WQ_FLAGS) {
5184                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5185                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5186                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5187                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
5188                                             "supported\n");
5189                                 err = -EOPNOTSUPP;
5190                                 goto out;
5191                         }
5192                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5193                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5194                         MLX5_SET(rqc, rqc, vsd,
5195                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5196                 }
5197
5198                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5199                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5200                         err = -EOPNOTSUPP;
5201                         goto out;
5202                 }
5203         }
5204
5205         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5206                 u16 set_id;
5207
5208                 set_id = mlx5_ib_get_counters_id(dev, 0);
5209                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5210                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5211                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5212                         MLX5_SET(rqc, rqc, counter_set_id, set_id);
5213                 } else
5214                         dev_info_once(
5215                                 &dev->ib_dev.dev,
5216                                 "Receive WQ counters are not supported on current FW\n");
5217         }
5218
5219         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
5220         if (!err)
5221                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5222
5223 out:
5224         kvfree(in);
5225         return err;
5226 }
5227
5228 struct mlx5_ib_drain_cqe {
5229         struct ib_cqe cqe;
5230         struct completion done;
5231 };
5232
5233 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5234 {
5235         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5236                                                      struct mlx5_ib_drain_cqe,
5237                                                      cqe);
5238
5239         complete(&cqe->done);
5240 }
5241
5242 /* This function returns only once the drained WR was completed */
5243 static void handle_drain_completion(struct ib_cq *cq,
5244                                     struct mlx5_ib_drain_cqe *sdrain,
5245                                     struct mlx5_ib_dev *dev)
5246 {
5247         struct mlx5_core_dev *mdev = dev->mdev;
5248
5249         if (cq->poll_ctx == IB_POLL_DIRECT) {
5250                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5251                         ib_process_cq_direct(cq, -1);
5252                 return;
5253         }
5254
5255         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5256                 struct mlx5_ib_cq *mcq = to_mcq(cq);
5257                 bool triggered = false;
5258                 unsigned long flags;
5259
5260                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5261                 /* Make sure that the CQ handler won't run if wasn't run yet */
5262                 if (!mcq->mcq.reset_notify_added)
5263                         mcq->mcq.reset_notify_added = 1;
5264                 else
5265                         triggered = true;
5266                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5267
5268                 if (triggered) {
5269                         /* Wait for any scheduled/running task to be ended */
5270                         switch (cq->poll_ctx) {
5271                         case IB_POLL_SOFTIRQ:
5272                                 irq_poll_disable(&cq->iop);
5273                                 irq_poll_enable(&cq->iop);
5274                                 break;
5275                         case IB_POLL_WORKQUEUE:
5276                                 cancel_work_sync(&cq->work);
5277                                 break;
5278                         default:
5279                                 WARN_ON_ONCE(1);
5280                         }
5281                 }
5282
5283                 /* Run the CQ handler - this makes sure that the drain WR will
5284                  * be processed if wasn't processed yet.
5285                  */
5286                 mcq->mcq.comp(&mcq->mcq, NULL);
5287         }
5288
5289         wait_for_completion(&sdrain->done);
5290 }
5291
5292 void mlx5_ib_drain_sq(struct ib_qp *qp)
5293 {
5294         struct ib_cq *cq = qp->send_cq;
5295         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5296         struct mlx5_ib_drain_cqe sdrain;
5297         const struct ib_send_wr *bad_swr;
5298         struct ib_rdma_wr swr = {
5299                 .wr = {
5300                         .next = NULL,
5301                         { .wr_cqe       = &sdrain.cqe, },
5302                         .opcode = IB_WR_RDMA_WRITE,
5303                 },
5304         };
5305         int ret;
5306         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5307         struct mlx5_core_dev *mdev = dev->mdev;
5308
5309         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5310         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5311                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5312                 return;
5313         }
5314
5315         sdrain.cqe.done = mlx5_ib_drain_qp_done;
5316         init_completion(&sdrain.done);
5317
5318         ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr);
5319         if (ret) {
5320                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5321                 return;
5322         }
5323
5324         handle_drain_completion(cq, &sdrain, dev);
5325 }
5326
5327 void mlx5_ib_drain_rq(struct ib_qp *qp)
5328 {
5329         struct ib_cq *cq = qp->recv_cq;
5330         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5331         struct mlx5_ib_drain_cqe rdrain;
5332         struct ib_recv_wr rwr = {};
5333         const struct ib_recv_wr *bad_rwr;
5334         int ret;
5335         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5336         struct mlx5_core_dev *mdev = dev->mdev;
5337
5338         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5339         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5340                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5341                 return;
5342         }
5343
5344         rwr.wr_cqe = &rdrain.cqe;
5345         rdrain.cqe.done = mlx5_ib_drain_qp_done;
5346         init_completion(&rdrain.done);
5347
5348         ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr);
5349         if (ret) {
5350                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5351                 return;
5352         }
5353
5354         handle_drain_completion(cq, &rdrain, dev);
5355 }
5356
5357 /**
5358  * Bind a qp to a counter. If @counter is NULL then bind the qp to
5359  * the default counter
5360  */
5361 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
5362 {
5363         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5364         struct mlx5_ib_qp *mqp = to_mqp(qp);
5365         int err = 0;
5366
5367         mutex_lock(&mqp->mutex);
5368         if (mqp->state == IB_QPS_RESET) {
5369                 qp->counter = counter;
5370                 goto out;
5371         }
5372
5373         if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
5374                 err = -EOPNOTSUPP;
5375                 goto out;
5376         }
5377
5378         if (mqp->state == IB_QPS_RTS) {
5379                 err = __mlx5_ib_qp_set_counter(qp, counter);
5380                 if (!err)
5381                         qp->counter = counter;
5382
5383                 goto out;
5384         }
5385
5386         mqp->counter_pending = 1;
5387         qp->counter = counter;
5388
5389 out:
5390         mutex_unlock(&mqp->mutex);
5391         return err;
5392 }