drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/mlx5/fs.h>
  38 #include "mlx5_ib.h"
  39 #include "ib_rep.h"
  40 #include "cmd.h"
  41
  42 /* not supported currently */
  43 static int wq_signature;
  44
  45 enum {
  46         MLX5_IB_ACK_REQ_FREQ    = 8,
  47 };
  48
  49 enum {
  50         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  51         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  52         MLX5_IB_LINK_TYPE_IB            = 0,
  53         MLX5_IB_LINK_TYPE_ETH           = 1
  54 };
  55
  56 enum {
  57         MLX5_IB_SQ_STRIDE       = 6,
  58         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  59 };
  60
  61 static const u32 mlx5_ib_opcode[] = {
  62         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  63         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  64         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  65         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  66         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  67         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  68         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  69         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  70         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  71         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  72         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  73         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  74         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  75         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  76 };
  77
  78 struct mlx5_wqe_eth_pad {
  79         u8 rsvd0[16];
  80 };
  81
  82 enum raw_qp_set_mask_map {
  83         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  84         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  85 };
  86
  87 struct mlx5_modify_raw_qp_param {
  88         u16 operation;
  89
  90         u32 set_mask; /* raw_qp_set_mask_map */
  91
  92         struct mlx5_rate_limit rl;
  93
  94         u8 rq_q_ctr_id;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 112 {
 113         return mlx5_buf_offset(&qp->buf, offset);
 114 }
 115
 116 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 117 {
 118         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 119 }
 120
 121 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 122 {
 123         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 124 }
 125
 126 /**
 127  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 128  *
 129  * @qp: QP to copy from.
 130  * @send: copy from the send queue when non-zero, use the receive queue
 131  *        otherwise.
 132  * @wqe_index:  index to start copying from. For send work queues, the
 133  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 134  *              For receive work queue, it is the number of work queue
 135  *              element in the queue.
 136  * @buffer: destination buffer.
 137  * @length: maximum number of bytes to copy.
 138  *
 139  * Copies at least a single WQE, but may copy more data.
 140  *
 141  * Return: the number of bytes copied, or an error code.
 142  */
 143 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 144                           void *buffer, u32 length,
 145                           struct mlx5_ib_qp_base *base)
 146 {
 147         struct ib_device *ibdev = qp->ibqp.device;
 148         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 149         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 150         size_t offset;
 151         size_t wq_end;
 152         struct ib_umem *umem = base->ubuffer.umem;
 153         u32 first_copy_length;
 154         int wqe_length;
 155         int ret;
 156
 157         if (wq->wqe_cnt == 0) {
 158                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 159                             qp->ibqp.qp_type);
 160                 return -EINVAL;
 161         }
 162
 163         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 164         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 165
 166         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 167                 return -EINVAL;
 168
 169         if (offset > umem->length ||
 170             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 171                 return -EINVAL;
 172
 173         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 174         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 175         if (ret)
 176                 return ret;
 177
 178         if (send) {
 179                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 180                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 181
 182                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 183         } else {
 184                 wqe_length = 1 << wq->wqe_shift;
 185         }
 186
 187         if (wqe_length <= first_copy_length)
 188                 return first_copy_length;
 189
 190         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 191                                 wqe_length - first_copy_length);
 192         if (ret)
 193                 return ret;
 194
 195         return wqe_length;
 196 }
 197
 198 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 199 {
 200         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 201         struct ib_event event;
 202
 203         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 204                 /* This event is only valid for trans_qps */
 205                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 206         }
 207
 208         if (ibqp->event_handler) {
 209                 event.device     = ibqp->device;
 210                 event.element.qp = ibqp;
 211                 switch (type) {
 212                 case MLX5_EVENT_TYPE_PATH_MIG:
 213                         event.event = IB_EVENT_PATH_MIG;
 214                         break;
 215                 case MLX5_EVENT_TYPE_COMM_EST:
 216                         event.event = IB_EVENT_COMM_EST;
 217                         break;
 218                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 219                         event.event = IB_EVENT_SQ_DRAINED;
 220                         break;
 221                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 222                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 223                         break;
 224                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 225                         event.event = IB_EVENT_QP_FATAL;
 226                         break;
 227                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 228                         event.event = IB_EVENT_PATH_MIG_ERR;
 229                         break;
 230                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 231                         event.event = IB_EVENT_QP_REQ_ERR;
 232                         break;
 233                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 234                         event.event = IB_EVENT_QP_ACCESS_ERR;
 235                         break;
 236                 default:
 237                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 238                         return;
 239                 }
 240
 241                 ibqp->event_handler(&event, ibqp->qp_context);
 242         }
 243 }
 244
 245 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 246                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 247 {
 248         int wqe_size;
 249         int wq_size;
 250
 251         /* Sanity check RQ size before proceeding */
 252         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 253                 return -EINVAL;
 254
 255         if (!has_rq) {
 256                 qp->rq.max_gs = 0;
 257                 qp->rq.wqe_cnt = 0;
 258                 qp->rq.wqe_shift = 0;
 259                 cap->max_recv_wr = 0;
 260                 cap->max_recv_sge = 0;
 261         } else {
 262                 if (ucmd) {
 263                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 264                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 265                                 return -EINVAL;
 266                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 267                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 268                                 return -EINVAL;
 269                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 270                         qp->rq.max_post = qp->rq.wqe_cnt;
 271                 } else {
 272                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 273                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 274                         wqe_size = roundup_pow_of_two(wqe_size);
 275                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 276                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 277                         qp->rq.wqe_cnt = wq_size / wqe_size;
 278                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 279                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 280                                             wqe_size,
 281                                             MLX5_CAP_GEN(dev->mdev,
 282                                                          max_wqe_sz_rq));
 283                                 return -EINVAL;
 284                         }
 285                         qp->rq.wqe_shift = ilog2(wqe_size);
 286                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 287                         qp->rq.max_post = qp->rq.wqe_cnt;
 288                 }
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int sq_overhead(struct ib_qp_init_attr *attr)
 295 {
 296         int size = 0;
 297
 298         switch (attr->qp_type) {
 299         case IB_QPT_XRC_INI:
 300                 size += sizeof(struct mlx5_wqe_xrc_seg);
 301                 /* fall through */
 302         case IB_QPT_RC:
 303                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 304                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 305                             sizeof(struct mlx5_wqe_raddr_seg),
 306                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 307                             sizeof(struct mlx5_mkey_seg) +
 308                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 309                             MLX5_IB_UMR_OCTOWORD);
 310                 break;
 311
 312         case IB_QPT_XRC_TGT:
 313                 return 0;
 314
 315         case IB_QPT_UC:
 316                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 317                         max(sizeof(struct mlx5_wqe_raddr_seg),
 318                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 319                             sizeof(struct mlx5_mkey_seg));
 320                 break;
 321
 322         case IB_QPT_UD:
 323                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 324                         size += sizeof(struct mlx5_wqe_eth_pad) +
 325                                 sizeof(struct mlx5_wqe_eth_seg);
 326                 /* fall through */
 327         case IB_QPT_SMI:
 328         case MLX5_IB_QPT_HW_GSI:
 329                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 330                         sizeof(struct mlx5_wqe_datagram_seg);
 331                 break;
 332
 333         case MLX5_IB_QPT_REG_UMR:
 334                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 335                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 336                         sizeof(struct mlx5_mkey_seg);
 337                 break;
 338
 339         default:
 340                 return -EINVAL;
 341         }
 342
 343         return size;
 344 }
 345
 346 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 347 {
 348         int inl_size = 0;
 349         int size;
 350
 351         size = sq_overhead(attr);
 352         if (size < 0)
 353                 return size;
 354
 355         if (attr->cap.max_inline_data) {
 356                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 357                         attr->cap.max_inline_data;
 358         }
 359
 360         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 361         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 362             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 363                         return MLX5_SIG_WQE_SIZE;
 364         else
 365                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 366 }
 367
 368 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 369 {
 370         int max_sge;
 371
 372         if (attr->qp_type == IB_QPT_RC)
 373                 max_sge = (min_t(int, wqe_size, 512) -
 374                            sizeof(struct mlx5_wqe_ctrl_seg) -
 375                            sizeof(struct mlx5_wqe_raddr_seg)) /
 376                         sizeof(struct mlx5_wqe_data_seg);
 377         else if (attr->qp_type == IB_QPT_XRC_INI)
 378                 max_sge = (min_t(int, wqe_size, 512) -
 379                            sizeof(struct mlx5_wqe_ctrl_seg) -
 380                            sizeof(struct mlx5_wqe_xrc_seg) -
 381                            sizeof(struct mlx5_wqe_raddr_seg)) /
 382                         sizeof(struct mlx5_wqe_data_seg);
 383         else
 384                 max_sge = (wqe_size - sq_overhead(attr)) /
 385                         sizeof(struct mlx5_wqe_data_seg);
 386
 387         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 388                      sizeof(struct mlx5_wqe_data_seg));
 389 }
 390
 391 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 392                         struct mlx5_ib_qp *qp)
 393 {
 394         int wqe_size;
 395         int wq_size;
 396
 397         if (!attr->cap.max_send_wr)
 398                 return 0;
 399
 400         wqe_size = calc_send_wqe(attr);
 401         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 402         if (wqe_size < 0)
 403                 return wqe_size;
 404
 405         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 406                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 407                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 408                 return -EINVAL;
 409         }
 410
 411         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 412                               sizeof(struct mlx5_wqe_inline_seg);
 413         attr->cap.max_inline_data = qp->max_inline_data;
 414
 415         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 416                 qp->signature_en = true;
 417
 418         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 419         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 420         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 421                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 422                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 423                             qp->sq.wqe_cnt,
 424                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 425                 return -ENOMEM;
 426         }
 427         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 428         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 429         if (qp->sq.max_gs < attr->cap.max_send_sge)
 430                 return -ENOMEM;
 431
 432         attr->cap.max_send_sge = qp->sq.max_gs;
 433         qp->sq.max_post = wq_size / wqe_size;
 434         attr->cap.max_send_wr = qp->sq.max_post;
 435
 436         return wq_size;
 437 }
 438
 439 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 440                             struct mlx5_ib_qp *qp,
 441                             struct mlx5_ib_create_qp *ucmd,
 442                             struct mlx5_ib_qp_base *base,
 443                             struct ib_qp_init_attr *attr)
 444 {
 445         int desc_sz = 1 << qp->sq.wqe_shift;
 446
 447         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 448                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 449                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 450                 return -EINVAL;
 451         }
 452
 453         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 454                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 455                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 456                 return -EINVAL;
 457         }
 458
 459         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 460
 461         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 462                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 463                              qp->sq.wqe_cnt,
 464                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 465                 return -EINVAL;
 466         }
 467
 468         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 469             qp->flags & MLX5_IB_QP_UNDERLAY) {
 470                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 471                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 472         } else {
 473                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 474                                          (qp->sq.wqe_cnt << 6);
 475         }
 476
 477         return 0;
 478 }
 479
 480 static int qp_has_rq(struct ib_qp_init_attr *attr)
 481 {
 482         if (attr->qp_type == IB_QPT_XRC_INI ||
 483             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 484             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 485             !attr->cap.max_recv_wr)
 486                 return 0;
 487
 488         return 1;
 489 }
 490
 491 enum {
 492         /* this is the first blue flame register in the array of bfregs assigned
 493          * to a processes. Since we do not use it for blue flame but rather
 494          * regular 64 bit doorbells, we do not need a lock for maintaiing
 495          * "odd/even" order
 496          */
 497         NUM_NON_BLUE_FLAME_BFREGS = 1,
 498 };
 499
 500 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 501 {
 502         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 503 }
 504
 505 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 506                          struct mlx5_bfreg_info *bfregi)
 507 {
 508         int n;
 509
 510         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 511             NUM_NON_BLUE_FLAME_BFREGS;
 512
 513         return n >= 0 ? n : 0;
 514 }
 515
 516 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 517                            struct mlx5_bfreg_info *bfregi)
 518 {
 519         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 520 }
 521
 522 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 523                           struct mlx5_bfreg_info *bfregi)
 524 {
 525         int med;
 526
 527         med = num_med_bfreg(dev, bfregi);
 528         return ++med;
 529 }
 530
 531 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 532                                   struct mlx5_bfreg_info *bfregi)
 533 {
 534         int i;
 535
 536         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 537                 if (!bfregi->count[i]) {
 538                         bfregi->count[i]++;
 539                         return i;
 540                 }
 541         }
 542
 543         return -ENOMEM;
 544 }
 545
 546 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 547                                  struct mlx5_bfreg_info *bfregi)
 548 {
 549         int minidx = first_med_bfreg(dev, bfregi);
 550         int i;
 551
 552         if (minidx < 0)
 553                 return minidx;
 554
 555         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 556                 if (bfregi->count[i] < bfregi->count[minidx])
 557                         minidx = i;
 558                 if (!bfregi->count[minidx])
 559                         break;
 560         }
 561
 562         bfregi->count[minidx]++;
 563         return minidx;
 564 }
 565
 566 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 567                        struct mlx5_bfreg_info *bfregi)
 568 {
 569         int bfregn = -ENOMEM;
 570
 571         mutex_lock(&bfregi->lock);
 572         if (bfregi->ver >= 2) {
 573                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 574                 if (bfregn < 0)
 575                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 576         }
 577
 578         if (bfregn < 0) {
 579                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 580                 bfregn = 0;
 581                 bfregi->count[bfregn]++;
 582         }
 583         mutex_unlock(&bfregi->lock);
 584
 585         return bfregn;
 586 }
 587
 588 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 589 {
 590         mutex_lock(&bfregi->lock);
 591         bfregi->count[bfregn]--;
 592         mutex_unlock(&bfregi->lock);
 593 }
 594
 595 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 596 {
 597         switch (state) {
 598         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 599         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 600         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 601         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 602         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 603         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 604         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 605         default:                return -1;
 606         }
 607 }
 608
 609 static int to_mlx5_st(enum ib_qp_type type)
 610 {
 611         switch (type) {
 612         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 613         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 614         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 615         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 616         case IB_QPT_XRC_INI:
 617         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 618         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 619         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 620         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 621         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 622         case IB_QPT_RAW_PACKET:
 623         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 624         case IB_QPT_MAX:
 625         default:                return -EINVAL;
 626         }
 627 }
 628
 629 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 630                              struct mlx5_ib_cq *recv_cq);
 631 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 632                                struct mlx5_ib_cq *recv_cq);
 633
 634 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 635                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 636                         bool dyn_bfreg)
 637 {
 638         unsigned int bfregs_per_sys_page;
 639         u32 index_of_sys_page;
 640         u32 offset;
 641
 642         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 643                                 MLX5_NON_FP_BFREGS_PER_UAR;
 644         index_of_sys_page = bfregn / bfregs_per_sys_page;
 645
 646         if (dyn_bfreg) {
 647                 index_of_sys_page += bfregi->num_static_sys_pages;
 648
 649                 if (index_of_sys_page >= bfregi->num_sys_pages)
 650                         return -EINVAL;
 651
 652                 if (bfregn > bfregi->num_dyn_bfregs ||
 653                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 654                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 655                         return -EINVAL;
 656                 }
 657         }
 658
 659         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 660         return bfregi->sys_pages[index_of_sys_page] + offset;
 661 }
 662
 663 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 664                             struct ib_pd *pd,
 665                             unsigned long addr, size_t size,
 666                             struct ib_umem **umem,
 667                             int *npages, int *page_shift, int *ncont,
 668                             u32 *offset)
 669 {
 670         int err;
 671
 672         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 673         if (IS_ERR(*umem)) {
 674                 mlx5_ib_dbg(dev, "umem_get failed\n");
 675                 return PTR_ERR(*umem);
 676         }
 677
 678         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 679
 680         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 681         if (err) {
 682                 mlx5_ib_warn(dev, "bad offset\n");
 683                 goto err_umem;
 684         }
 685
 686         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 687                     addr, size, *npages, *page_shift, *ncont, *offset);
 688
 689         return 0;
 690
 691 err_umem:
 692         ib_umem_release(*umem);
 693         *umem = NULL;
 694
 695         return err;
 696 }
 697
 698 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 699                             struct mlx5_ib_rwq *rwq)
 700 {
 701         struct mlx5_ib_ucontext *context;
 702
 703         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 704                 atomic_dec(&dev->delay_drop.rqs_cnt);
 705
 706         context = to_mucontext(pd->uobject->context);
 707         mlx5_ib_db_unmap_user(context, &rwq->db);
 708         if (rwq->umem)
 709                 ib_umem_release(rwq->umem);
 710 }
 711
 712 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 713                           struct mlx5_ib_rwq *rwq,
 714                           struct mlx5_ib_create_wq *ucmd)
 715 {
 716         struct mlx5_ib_ucontext *context;
 717         int page_shift = 0;
 718         int npages;
 719         u32 offset = 0;
 720         int ncont = 0;
 721         int err;
 722
 723         if (!ucmd->buf_addr)
 724                 return -EINVAL;
 725
 726         context = to_mucontext(pd->uobject->context);
 727         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 728                                rwq->buf_size, 0, 0);
 729         if (IS_ERR(rwq->umem)) {
 730                 mlx5_ib_dbg(dev, "umem_get failed\n");
 731                 err = PTR_ERR(rwq->umem);
 732                 return err;
 733         }
 734
 735         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 736                            &ncont, NULL);
 737         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 738                                      &rwq->rq_page_offset);
 739         if (err) {
 740                 mlx5_ib_warn(dev, "bad offset\n");
 741                 goto err_umem;
 742         }
 743
 744         rwq->rq_num_pas = ncont;
 745         rwq->page_shift = page_shift;
 746         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 747         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 748
 749         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 750                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 751                     npages, page_shift, ncont, offset);
 752
 753         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 754         if (err) {
 755                 mlx5_ib_dbg(dev, "map failed\n");
 756                 goto err_umem;
 757         }
 758
 759         rwq->create_type = MLX5_WQ_USER;
 760         return 0;
 761
 762 err_umem:
 763         ib_umem_release(rwq->umem);
 764         return err;
 765 }
 766
 767 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 768                          struct mlx5_bfreg_info *bfregi, int bfregn)
 769 {
 770         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 771                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 772 }
 773
 774 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 775                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 776                           struct ib_qp_init_attr *attr,
 777                           u32 **in,
 778                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 779                           struct mlx5_ib_qp_base *base)
 780 {
 781         struct mlx5_ib_ucontext *context;
 782         struct mlx5_ib_create_qp ucmd;
 783         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 784         int page_shift = 0;
 785         int uar_index = 0;
 786         int npages;
 787         u32 offset = 0;
 788         int bfregn;
 789         int ncont = 0;
 790         __be64 *pas;
 791         void *qpc;
 792         int err;
 793
 794         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 795         if (err) {
 796                 mlx5_ib_dbg(dev, "copy failed\n");
 797                 return err;
 798         }
 799
 800         context = to_mucontext(pd->uobject->context);
 801         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
 802                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 803                                                 ucmd.bfreg_index, true);
 804                 if (uar_index < 0)
 805                         return uar_index;
 806
 807                 bfregn = MLX5_IB_INVALID_BFREG;
 808         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
 809                 /*
 810                  * TBD: should come from the verbs when we have the API
 811                  */
 812                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 813                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 814         }
 815         else {
 816                 bfregn = alloc_bfreg(dev, &context->bfregi);
 817                 if (bfregn < 0)
 818                         return bfregn;
 819         }
 820
 821         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 822         if (bfregn != MLX5_IB_INVALID_BFREG)
 823                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 824                                                 false);
 825
 826         qp->rq.offset = 0;
 827         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 828         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 829
 830         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 831         if (err)
 832                 goto err_bfreg;
 833
 834         if (ucmd.buf_addr && ubuffer->buf_size) {
 835                 ubuffer->buf_addr = ucmd.buf_addr;
 836                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 837                                        ubuffer->buf_size,
 838                                        &ubuffer->umem, &npages, &page_shift,
 839                                        &ncont, &offset);
 840                 if (err)
 841                         goto err_bfreg;
 842         } else {
 843                 ubuffer->umem = NULL;
 844         }
 845
 846         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 847                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 848         *in = kvzalloc(*inlen, GFP_KERNEL);
 849         if (!*in) {
 850                 err = -ENOMEM;
 851                 goto err_umem;
 852         }
 853
 854         MLX5_SET(create_qp_in, *in, uid, to_mpd(pd)->uid);
 855         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 856         if (ubuffer->umem)
 857                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 858
 859         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 860
 861         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 862         MLX5_SET(qpc, qpc, page_offset, offset);
 863
 864         MLX5_SET(qpc, qpc, uar_page, uar_index);
 865         if (bfregn != MLX5_IB_INVALID_BFREG)
 866                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 867         else
 868                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 869         qp->bfregn = bfregn;
 870
 871         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 872         if (err) {
 873                 mlx5_ib_dbg(dev, "map failed\n");
 874                 goto err_free;
 875         }
 876
 877         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
 878         if (err) {
 879                 mlx5_ib_dbg(dev, "copy failed\n");
 880                 goto err_unmap;
 881         }
 882         qp->create_type = MLX5_QP_USER;
 883
 884         return 0;
 885
 886 err_unmap:
 887         mlx5_ib_db_unmap_user(context, &qp->db);
 888
 889 err_free:
 890         kvfree(*in);
 891
 892 err_umem:
 893         if (ubuffer->umem)
 894                 ib_umem_release(ubuffer->umem);
 895
 896 err_bfreg:
 897         if (bfregn != MLX5_IB_INVALID_BFREG)
 898                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
 899         return err;
 900 }
 901
 902 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 903                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
 904 {
 905         struct mlx5_ib_ucontext *context;
 906
 907         context = to_mucontext(pd->uobject->context);
 908         mlx5_ib_db_unmap_user(context, &qp->db);
 909         if (base->ubuffer.umem)
 910                 ib_umem_release(base->ubuffer.umem);
 911
 912         /*
 913          * Free only the BFREGs which are handled by the kernel.
 914          * BFREGs of UARs allocated dynamically are handled by user.
 915          */
 916         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
 917                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
 918 }
 919
 920 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 921                             struct ib_qp_init_attr *init_attr,
 922                             struct mlx5_ib_qp *qp,
 923                             u32 **in, int *inlen,
 924                             struct mlx5_ib_qp_base *base)
 925 {
 926         int uar_index;
 927         void *qpc;
 928         int err;
 929
 930         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 931                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 932                                         IB_QP_CREATE_IPOIB_UD_LSO |
 933                                         IB_QP_CREATE_NETIF_QP |
 934                                         mlx5_ib_create_qp_sqpn_qp1()))
 935                 return -EINVAL;
 936
 937         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 938                 qp->bf.bfreg = &dev->fp_bfreg;
 939         else
 940                 qp->bf.bfreg = &dev->bfreg;
 941
 942         /* We need to divide by two since each register is comprised of
 943          * two buffers of identical size, namely odd and even
 944          */
 945         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
 946         uar_index = qp->bf.bfreg->index;
 947
 948         err = calc_sq_size(dev, init_attr, qp);
 949         if (err < 0) {
 950                 mlx5_ib_dbg(dev, "err %d\n", err);
 951                 return err;
 952         }
 953
 954         qp->rq.offset = 0;
 955         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 956         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 957
 958         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 959         if (err) {
 960                 mlx5_ib_dbg(dev, "err %d\n", err);
 961                 return err;
 962         }
 963
 964         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 965         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 966                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 967         *in = kvzalloc(*inlen, GFP_KERNEL);
 968         if (!*in) {
 969                 err = -ENOMEM;
 970                 goto err_buf;
 971         }
 972
 973         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 974         MLX5_SET(qpc, qpc, uar_page, uar_index);
 975         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 976
 977         /* Set "fast registration enabled" for all kernel QPs */
 978         MLX5_SET(qpc, qpc, fre, 1);
 979         MLX5_SET(qpc, qpc, rlky, 1);
 980
 981         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 982                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 983                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 984         }
 985
 986         mlx5_fill_page_array(&qp->buf,
 987                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 988
 989         err = mlx5_db_alloc(dev->mdev, &qp->db);
 990         if (err) {
 991                 mlx5_ib_dbg(dev, "err %d\n", err);
 992                 goto err_free;
 993         }
 994
 995         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
 996                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
 997         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
 998                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
 999         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1000                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1001         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1002                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1003         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1004                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1005
1006         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1007             !qp->sq.w_list || !qp->sq.wqe_head) {
1008                 err = -ENOMEM;
1009                 goto err_wrid;
1010         }
1011         qp->create_type = MLX5_QP_KERNEL;
1012
1013         return 0;
1014
1015 err_wrid:
1016         kvfree(qp->sq.wqe_head);
1017         kvfree(qp->sq.w_list);
1018         kvfree(qp->sq.wrid);
1019         kvfree(qp->sq.wr_data);
1020         kvfree(qp->rq.wrid);
1021         mlx5_db_free(dev->mdev, &qp->db);
1022
1023 err_free:
1024         kvfree(*in);
1025
1026 err_buf:
1027         mlx5_buf_free(dev->mdev, &qp->buf);
1028         return err;
1029 }
1030
1031 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1032 {
1033         kvfree(qp->sq.wqe_head);
1034         kvfree(qp->sq.w_list);
1035         kvfree(qp->sq.wrid);
1036         kvfree(qp->sq.wr_data);
1037         kvfree(qp->rq.wrid);
1038         mlx5_db_free(dev->mdev, &qp->db);
1039         mlx5_buf_free(dev->mdev, &qp->buf);
1040 }
1041
1042 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1043 {
1044         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1045             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1046             (attr->qp_type == IB_QPT_XRC_INI))
1047                 return MLX5_SRQ_RQ;
1048         else if (!qp->has_rq)
1049                 return MLX5_ZERO_LEN_RQ;
1050         else
1051                 return MLX5_NON_ZERO_RQ;
1052 }
1053
1054 static int is_connected(enum ib_qp_type qp_type)
1055 {
1056         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1057             qp_type == MLX5_IB_QPT_DCI)
1058                 return 1;
1059
1060         return 0;
1061 }
1062
1063 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1064                                     struct mlx5_ib_qp *qp,
1065                                     struct mlx5_ib_sq *sq, u32 tdn,
1066                                     struct ib_pd *pd)
1067 {
1068         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1069         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1070
1071         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1072         MLX5_SET(tisc, tisc, transport_domain, tdn);
1073         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1074                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1075
1076         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1077 }
1078
1079 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1080                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1081 {
1082         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1083 }
1084
1085 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1086                                        struct mlx5_ib_sq *sq)
1087 {
1088         if (sq->flow_rule)
1089                 mlx5_del_flow_rules(sq->flow_rule);
1090 }
1091
1092 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1093                                    struct mlx5_ib_sq *sq, void *qpin,
1094                                    struct ib_pd *pd)
1095 {
1096         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1097         __be64 *pas;
1098         void *in;
1099         void *sqc;
1100         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1101         void *wq;
1102         int inlen;
1103         int err;
1104         int page_shift = 0;
1105         int npages;
1106         int ncont = 0;
1107         u32 offset = 0;
1108
1109         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1110                                &sq->ubuffer.umem, &npages, &page_shift,
1111                                &ncont, &offset);
1112         if (err)
1113                 return err;
1114
1115         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1116         in = kvzalloc(inlen, GFP_KERNEL);
1117         if (!in) {
1118                 err = -ENOMEM;
1119                 goto err_umem;
1120         }
1121
1122         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1123         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1124         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1125         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1126                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1127         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1128         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1129         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1130         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1131         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1132         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1133             MLX5_CAP_ETH(dev->mdev, swp))
1134                 MLX5_SET(sqc, sqc, allow_swp, 1);
1135
1136         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1137         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1138         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1139         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1140         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1141         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1142         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1143         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1144         MLX5_SET(wq, wq, page_offset, offset);
1145
1146         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1147         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1148
1149         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1150
1151         kvfree(in);
1152
1153         if (err)
1154                 goto err_umem;
1155
1156         err = create_flow_rule_vport_sq(dev, sq);
1157         if (err)
1158                 goto err_flow;
1159
1160         return 0;
1161
1162 err_flow:
1163         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1164
1165 err_umem:
1166         ib_umem_release(sq->ubuffer.umem);
1167         sq->ubuffer.umem = NULL;
1168
1169         return err;
1170 }
1171
1172 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1173                                      struct mlx5_ib_sq *sq)
1174 {
1175         destroy_flow_rule_vport_sq(dev, sq);
1176         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1177         ib_umem_release(sq->ubuffer.umem);
1178 }
1179
1180 static size_t get_rq_pas_size(void *qpc)
1181 {
1182         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1183         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1184         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1185         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1186         u32 po_quanta     = 1 << (log_page_size - 6);
1187         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1188         u32 page_size     = 1 << log_page_size;
1189         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1190         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1191
1192         return rq_num_pas * sizeof(u64);
1193 }
1194
1195 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1196                                    struct mlx5_ib_rq *rq, void *qpin,
1197                                    size_t qpinlen, struct ib_pd *pd)
1198 {
1199         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1200         __be64 *pas;
1201         __be64 *qp_pas;
1202         void *in;
1203         void *rqc;
1204         void *wq;
1205         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1206         size_t rq_pas_size = get_rq_pas_size(qpc);
1207         size_t inlen;
1208         int err;
1209
1210         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1211                 return -EINVAL;
1212
1213         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1214         in = kvzalloc(inlen, GFP_KERNEL);
1215         if (!in)
1216                 return -ENOMEM;
1217
1218         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1219         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1220         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1221                 MLX5_SET(rqc, rqc, vsd, 1);
1222         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1223         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1224         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1225         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1226         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1227
1228         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1229                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1230
1231         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1232         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1233         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1234                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1235         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1236         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1237         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1238         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1239         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1240         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1241
1242         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1243         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1244         memcpy(pas, qp_pas, rq_pas_size);
1245
1246         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1247
1248         kvfree(in);
1249
1250         return err;
1251 }
1252
1253 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1254                                      struct mlx5_ib_rq *rq)
1255 {
1256         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1257 }
1258
1259 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1260 {
1261         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1262                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1263                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1264 }
1265
1266 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1267                                       struct mlx5_ib_rq *rq,
1268                                       u32 qp_flags_en,
1269                                       struct ib_pd *pd)
1270 {
1271         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1272                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1273                 mlx5_ib_disable_lb(dev, false, true);
1274         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1275 }
1276
1277 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1278                                     struct mlx5_ib_rq *rq, u32 tdn,
1279                                     u32 *qp_flags_en,
1280                                     struct ib_pd *pd)
1281 {
1282         u8 lb_flag = 0;
1283         u32 *in;
1284         void *tirc;
1285         int inlen;
1286         int err;
1287
1288         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1289         in = kvzalloc(inlen, GFP_KERNEL);
1290         if (!in)
1291                 return -ENOMEM;
1292
1293         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1294         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1295         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1296         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1297         MLX5_SET(tirc, tirc, transport_domain, tdn);
1298         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1299                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1300
1301         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1302                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1303
1304         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1305                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1306
1307         if (dev->rep) {
1308                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1309                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1310         }
1311
1312         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1313
1314         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1315
1316         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1317                 err = mlx5_ib_enable_lb(dev, false, true);
1318
1319                 if (err)
1320                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1321         }
1322         kvfree(in);
1323
1324         return err;
1325 }
1326
1327 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1328                                 u32 *in, size_t inlen,
1329                                 struct ib_pd *pd,
1330                                 struct ib_udata *udata,
1331                                 struct mlx5_ib_create_qp_resp *resp)
1332 {
1333         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1334         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1335         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1336         struct ib_uobject *uobj = pd->uobject;
1337         struct ib_ucontext *ucontext = uobj->context;
1338         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1339         int err;
1340         u32 tdn = mucontext->tdn;
1341         u16 uid = to_mpd(pd)->uid;
1342
1343         if (qp->sq.wqe_cnt) {
1344                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1345                 if (err)
1346                         return err;
1347
1348                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1349                 if (err)
1350                         goto err_destroy_tis;
1351
1352                 if (uid) {
1353                         resp->tisn = sq->tisn;
1354                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1355                         resp->sqn = sq->base.mqp.qpn;
1356                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1357                 }
1358
1359                 sq->base.container_mibqp = qp;
1360                 sq->base.mqp.event = mlx5_ib_qp_event;
1361         }
1362
1363         if (qp->rq.wqe_cnt) {
1364                 rq->base.container_mibqp = qp;
1365
1366                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1367                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1368                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1369                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1370                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1371                 if (err)
1372                         goto err_destroy_sq;
1373
1374                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
1375                 if (err)
1376                         goto err_destroy_rq;
1377
1378                 if (uid) {
1379                         resp->rqn = rq->base.mqp.qpn;
1380                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1381                         resp->tirn = rq->tirn;
1382                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1383                 }
1384         }
1385
1386         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1387                                                      rq->base.mqp.qpn;
1388         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1389         if (err)
1390                 goto err_destroy_tir;
1391
1392         return 0;
1393
1394 err_destroy_tir:
1395         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1396 err_destroy_rq:
1397         destroy_raw_packet_qp_rq(dev, rq);
1398 err_destroy_sq:
1399         if (!qp->sq.wqe_cnt)
1400                 return err;
1401         destroy_raw_packet_qp_sq(dev, sq);
1402 err_destroy_tis:
1403         destroy_raw_packet_qp_tis(dev, sq, pd);
1404
1405         return err;
1406 }
1407
1408 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1409                                   struct mlx5_ib_qp *qp)
1410 {
1411         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1412         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1413         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1414
1415         if (qp->rq.wqe_cnt) {
1416                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1417                 destroy_raw_packet_qp_rq(dev, rq);
1418         }
1419
1420         if (qp->sq.wqe_cnt) {
1421                 destroy_raw_packet_qp_sq(dev, sq);
1422                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1423         }
1424 }
1425
1426 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1427                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1428 {
1429         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1430         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1431
1432         sq->sq = &qp->sq;
1433         rq->rq = &qp->rq;
1434         sq->doorbell = &qp->db;
1435         rq->doorbell = &qp->db;
1436 }
1437
1438 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1439 {
1440         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1441                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1442                 mlx5_ib_disable_lb(dev, false, true);
1443         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1444                              to_mpd(qp->ibqp.pd)->uid);
1445 }
1446
1447 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1448                                  struct ib_pd *pd,
1449                                  struct ib_qp_init_attr *init_attr,
1450                                  struct ib_udata *udata)
1451 {
1452         struct ib_uobject *uobj = pd->uobject;
1453         struct ib_ucontext *ucontext = uobj->context;
1454         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1455         struct mlx5_ib_create_qp_resp resp = {};
1456         int inlen;
1457         int err;
1458         u32 *in;
1459         void *tirc;
1460         void *hfso;
1461         u32 selected_fields = 0;
1462         u32 outer_l4;
1463         size_t min_resp_len;
1464         u32 tdn = mucontext->tdn;
1465         struct mlx5_ib_create_qp_rss ucmd = {};
1466         size_t required_cmd_sz;
1467         u8 lb_flag = 0;
1468
1469         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1470                 return -EOPNOTSUPP;
1471
1472         if (init_attr->create_flags || init_attr->send_cq)
1473                 return -EINVAL;
1474
1475         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1476         if (udata->outlen < min_resp_len)
1477                 return -EINVAL;
1478
1479         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1480         if (udata->inlen < required_cmd_sz) {
1481                 mlx5_ib_dbg(dev, "invalid inlen\n");
1482                 return -EINVAL;
1483         }
1484
1485         if (udata->inlen > sizeof(ucmd) &&
1486             !ib_is_udata_cleared(udata, sizeof(ucmd),
1487                                  udata->inlen - sizeof(ucmd))) {
1488                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1489                 return -EOPNOTSUPP;
1490         }
1491
1492         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1493                 mlx5_ib_dbg(dev, "copy failed\n");
1494                 return -EFAULT;
1495         }
1496
1497         if (ucmd.comp_mask) {
1498                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1499                 return -EOPNOTSUPP;
1500         }
1501
1502         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1503                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1504                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1505                 mlx5_ib_dbg(dev, "invalid flags\n");
1506                 return -EOPNOTSUPP;
1507         }
1508
1509         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1510             !tunnel_offload_supported(dev->mdev)) {
1511                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1512                 return -EOPNOTSUPP;
1513         }
1514
1515         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1516             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1517                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1518                 return -EOPNOTSUPP;
1519         }
1520
1521         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1522                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1523                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1524         }
1525
1526         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1527                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1528                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1529         }
1530
1531         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1532         if (err) {
1533                 mlx5_ib_dbg(dev, "copy failed\n");
1534                 return -EINVAL;
1535         }
1536
1537         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1538         in = kvzalloc(inlen, GFP_KERNEL);
1539         if (!in)
1540                 return -ENOMEM;
1541
1542         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1543         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1544         MLX5_SET(tirc, tirc, disp_type,
1545                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1546         MLX5_SET(tirc, tirc, indirect_table,
1547                  init_attr->rwq_ind_tbl->ind_tbl_num);
1548         MLX5_SET(tirc, tirc, transport_domain, tdn);
1549
1550         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1551
1552         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1553                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1554
1555         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1556
1557         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1558                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1559         else
1560                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1561
1562         switch (ucmd.rx_hash_function) {
1563         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1564         {
1565                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1566                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1567
1568                 if (len != ucmd.rx_key_len) {
1569                         err = -EINVAL;
1570                         goto err;
1571                 }
1572
1573                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1574                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1575                 memcpy(rss_key, ucmd.rx_hash_key, len);
1576                 break;
1577         }
1578         default:
1579                 err = -EOPNOTSUPP;
1580                 goto err;
1581         }
1582
1583         if (!ucmd.rx_hash_fields_mask) {
1584                 /* special case when this TIR serves as steering entry without hashing */
1585                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1586                         goto create_tir;
1587                 err = -EINVAL;
1588                 goto err;
1589         }
1590
1591         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1592              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1593              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1594              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1595                 err = -EINVAL;
1596                 goto err;
1597         }
1598
1599         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1600         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1601             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1602                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1603                          MLX5_L3_PROT_TYPE_IPV4);
1604         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1605                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1606                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1607                          MLX5_L3_PROT_TYPE_IPV6);
1608
1609         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1610                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1611                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1612                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1613                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1614
1615         /* Check that only one l4 protocol is set */
1616         if (outer_l4 & (outer_l4 - 1)) {
1617                 err = -EINVAL;
1618                 goto err;
1619         }
1620
1621         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1622         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1623             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1624                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1625                          MLX5_L4_PROT_TYPE_TCP);
1626         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1627                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1628                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1629                          MLX5_L4_PROT_TYPE_UDP);
1630
1631         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1632             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1633                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1634
1635         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1636             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1637                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1638
1639         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1640             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1641                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1642
1643         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1644             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1645                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1646
1647         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1648                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1649
1650         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1651
1652 create_tir:
1653         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1654
1655         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1656                 err = mlx5_ib_enable_lb(dev, false, true);
1657
1658                 if (err)
1659                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1660                                              to_mpd(pd)->uid);
1661         }
1662
1663         if (err)
1664                 goto err;
1665
1666         if (mucontext->devx_uid) {
1667                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1668                 resp.tirn = qp->rss_qp.tirn;
1669         }
1670
1671         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1672         if (err)
1673                 goto err_copy;
1674
1675         kvfree(in);
1676         /* qpn is reserved for that QP */
1677         qp->trans_qp.base.mqp.qpn = 0;
1678         qp->flags |= MLX5_IB_QP_RSS;
1679         return 0;
1680
1681 err_copy:
1682         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1683 err:
1684         kvfree(in);
1685         return err;
1686 }
1687
1688 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1689                                          void *qpc)
1690 {
1691         int rcqe_sz;
1692
1693         if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1694                 return;
1695
1696         rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1697
1698         if (rcqe_sz == 128) {
1699                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1700                 return;
1701         }
1702
1703         if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1704                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1705 }
1706
1707 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1708                                          struct ib_qp_init_attr *init_attr,
1709                                          struct mlx5_ib_create_qp *ucmd,
1710                                          void *qpc)
1711 {
1712         enum ib_qp_type qpt = init_attr->qp_type;
1713         int scqe_sz;
1714         bool allow_scat_cqe = 0;
1715
1716         if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1717                 return;
1718
1719         if (ucmd)
1720                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1721
1722         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1723                 return;
1724
1725         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1726         if (scqe_sz == 128) {
1727                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1728                 return;
1729         }
1730
1731         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1732             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1733                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1734 }
1735
1736 static int atomic_size_to_mode(int size_mask)
1737 {
1738         /* driver does not support atomic_size > 256B
1739          * and does not know how to translate bigger sizes
1740          */
1741         int supported_size_mask = size_mask & 0x1ff;
1742         int log_max_size;
1743
1744         if (!supported_size_mask)
1745                 return -EOPNOTSUPP;
1746
1747         log_max_size = __fls(supported_size_mask);
1748
1749         if (log_max_size > 3)
1750                 return log_max_size;
1751
1752         return MLX5_ATOMIC_MODE_8B;
1753 }
1754
1755 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1756                            enum ib_qp_type qp_type)
1757 {
1758         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1759         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1760         int atomic_mode = -EOPNOTSUPP;
1761         int atomic_size_mask;
1762
1763         if (!atomic)
1764                 return -EOPNOTSUPP;
1765
1766         if (qp_type == MLX5_IB_QPT_DCT)
1767                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1768         else
1769                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1770
1771         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1772             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1773                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1774
1775         if (atomic_mode <= 0 &&
1776             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1777              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1778                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1779
1780         return atomic_mode;
1781 }
1782
1783 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1784 {
1785         return (input & ~supported) == 0;
1786 }
1787
1788 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1789                             struct ib_qp_init_attr *init_attr,
1790                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1791 {
1792         struct mlx5_ib_resources *devr = &dev->devr;
1793         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1794         struct mlx5_core_dev *mdev = dev->mdev;
1795         struct mlx5_ib_create_qp_resp resp = {};
1796         struct mlx5_ib_cq *send_cq;
1797         struct mlx5_ib_cq *recv_cq;
1798         unsigned long flags;
1799         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1800         struct mlx5_ib_create_qp ucmd;
1801         struct mlx5_ib_qp_base *base;
1802         int mlx5_st;
1803         void *qpc;
1804         u32 *in;
1805         int err;
1806
1807         mutex_init(&qp->mutex);
1808         spin_lock_init(&qp->sq.lock);
1809         spin_lock_init(&qp->rq.lock);
1810
1811         mlx5_st = to_mlx5_st(init_attr->qp_type);
1812         if (mlx5_st < 0)
1813                 return -EINVAL;
1814
1815         if (init_attr->rwq_ind_tbl) {
1816                 if (!udata)
1817                         return -ENOSYS;
1818
1819                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1820                 return err;
1821         }
1822
1823         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1824                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1825                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1826                         return -EINVAL;
1827                 } else {
1828                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1829                 }
1830         }
1831
1832         if (init_attr->create_flags &
1833                         (IB_QP_CREATE_CROSS_CHANNEL |
1834                          IB_QP_CREATE_MANAGED_SEND |
1835                          IB_QP_CREATE_MANAGED_RECV)) {
1836                 if (!MLX5_CAP_GEN(mdev, cd)) {
1837                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1838                         return -EINVAL;
1839                 }
1840                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1841                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1842                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1843                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1844                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1845                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1846         }
1847
1848         if (init_attr->qp_type == IB_QPT_UD &&
1849             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1850                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1851                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1852                         return -EOPNOTSUPP;
1853                 }
1854
1855         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1856                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1857                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1858                         return -EOPNOTSUPP;
1859                 }
1860                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1861                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1862                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1863                         return -EOPNOTSUPP;
1864                 }
1865                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1866         }
1867
1868         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1869                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1870
1871         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1872                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1873                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1874                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1875                         return -EOPNOTSUPP;
1876                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1877         }
1878
1879         if (pd && pd->uobject) {
1880                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1881                         mlx5_ib_dbg(dev, "copy failed\n");
1882                         return -EFAULT;
1883                 }
1884
1885                 if (!check_flags_mask(ucmd.flags,
1886                                       MLX5_QP_FLAG_SIGNATURE |
1887                                               MLX5_QP_FLAG_SCATTER_CQE |
1888                                               MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1889                                               MLX5_QP_FLAG_BFREG_INDEX |
1890                                               MLX5_QP_FLAG_TYPE_DCT |
1891                                               MLX5_QP_FLAG_TYPE_DCI |
1892                                               MLX5_QP_FLAG_ALLOW_SCATTER_CQE))
1893                         return -EINVAL;
1894
1895                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1896                                         &ucmd, udata->inlen, &uidx);
1897                 if (err)
1898                         return err;
1899
1900                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1901                 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
1902                         qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1903                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1904                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1905                             !tunnel_offload_supported(mdev)) {
1906                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1907                                 return -EOPNOTSUPP;
1908                         }
1909                         qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1910                 }
1911
1912                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1913                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1914                                 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1915                                 return -EOPNOTSUPP;
1916                         }
1917                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1918                 }
1919
1920                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1921                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1922                                 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1923                                 return -EOPNOTSUPP;
1924                         }
1925                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1926                 }
1927
1928                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1929                         if (init_attr->qp_type != IB_QPT_UD ||
1930                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
1931                              MLX5_CAP_PORT_TYPE_IB) ||
1932                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1933                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1934                                 return -EOPNOTSUPP;
1935                         }
1936
1937                         qp->flags |= MLX5_IB_QP_UNDERLAY;
1938                         qp->underlay_qpn = init_attr->source_qpn;
1939                 }
1940         } else {
1941                 qp->wq_sig = !!wq_signature;
1942         }
1943
1944         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1945                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1946                &qp->raw_packet_qp.rq.base :
1947                &qp->trans_qp.base;
1948
1949         qp->has_rq = qp_has_rq(init_attr);
1950         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1951                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1952         if (err) {
1953                 mlx5_ib_dbg(dev, "err %d\n", err);
1954                 return err;
1955         }
1956
1957         if (pd) {
1958                 if (pd->uobject) {
1959                         __u32 max_wqes =
1960                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1961                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1962                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1963                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1964                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1965                                 return -EINVAL;
1966                         }
1967                         if (ucmd.sq_wqe_count > max_wqes) {
1968                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1969                                             ucmd.sq_wqe_count, max_wqes);
1970                                 return -EINVAL;
1971                         }
1972                         if (init_attr->create_flags &
1973                             mlx5_ib_create_qp_sqpn_qp1()) {
1974                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1975                                 return -EINVAL;
1976                         }
1977                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1978                                              &resp, &inlen, base);
1979                         if (err)
1980                                 mlx5_ib_dbg(dev, "err %d\n", err);
1981                 } else {
1982                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1983                                                base);
1984                         if (err)
1985                                 mlx5_ib_dbg(dev, "err %d\n", err);
1986                 }
1987
1988                 if (err)
1989                         return err;
1990         } else {
1991                 in = kvzalloc(inlen, GFP_KERNEL);
1992                 if (!in)
1993                         return -ENOMEM;
1994
1995                 qp->create_type = MLX5_QP_EMPTY;
1996         }
1997
1998         if (is_sqp(init_attr->qp_type))
1999                 qp->port = init_attr->port_num;
2000
2001         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2002
2003         MLX5_SET(qpc, qpc, st, mlx5_st);
2004         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2005
2006         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2007                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2008         else
2009                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2010
2011
2012         if (qp->wq_sig)
2013                 MLX5_SET(qpc, qpc, wq_signature, 1);
2014
2015         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2016                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2017
2018         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
2019                 MLX5_SET(qpc, qpc, cd_master, 1);
2020         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
2021                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2022         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
2023                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2024
2025         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
2026                 configure_responder_scat_cqe(init_attr, qpc);
2027                 configure_requester_scat_cqe(dev, init_attr,
2028                                              (pd && pd->uobject) ? &ucmd : NULL,
2029                                              qpc);
2030         }
2031
2032         if (qp->rq.wqe_cnt) {
2033                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2034                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2035         }
2036
2037         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2038
2039         if (qp->sq.wqe_cnt) {
2040                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2041         } else {
2042                 MLX5_SET(qpc, qpc, no_sq, 1);
2043                 if (init_attr->srq &&
2044                     init_attr->srq->srq_type == IB_SRQT_TM)
2045                         MLX5_SET(qpc, qpc, offload_type,
2046                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2047         }
2048
2049         /* Set default resources */
2050         switch (init_attr->qp_type) {
2051         case IB_QPT_XRC_TGT:
2052                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2053                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2054                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2055                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2056                 break;
2057         case IB_QPT_XRC_INI:
2058                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2059                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2060                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2061                 break;
2062         default:
2063                 if (init_attr->srq) {
2064                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2065                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2066                 } else {
2067                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2068                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2069                 }
2070         }
2071
2072         if (init_attr->send_cq)
2073                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2074
2075         if (init_attr->recv_cq)
2076                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2077
2078         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2079
2080         /* 0xffffff means we ask to work with cqe version 0 */
2081         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2082                 MLX5_SET(qpc, qpc, user_index, uidx);
2083
2084         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2085         if (init_attr->qp_type == IB_QPT_UD &&
2086             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2087                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2088                 qp->flags |= MLX5_IB_QP_LSO;
2089         }
2090
2091         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2092                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2093                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2094                         err = -EOPNOTSUPP;
2095                         goto err;
2096                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2097                         MLX5_SET(qpc, qpc, end_padding_mode,
2098                                  MLX5_WQ_END_PAD_MODE_ALIGN);
2099                 } else {
2100                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2101                 }
2102         }
2103
2104         if (inlen < 0) {
2105                 err = -EINVAL;
2106                 goto err;
2107         }
2108
2109         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2110             qp->flags & MLX5_IB_QP_UNDERLAY) {
2111                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2112                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2113                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2114                                            &resp);
2115         } else {
2116                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2117         }
2118
2119         if (err) {
2120                 mlx5_ib_dbg(dev, "create qp failed\n");
2121                 goto err_create;
2122         }
2123
2124         kvfree(in);
2125
2126         base->container_mibqp = qp;
2127         base->mqp.event = mlx5_ib_qp_event;
2128
2129         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2130                 &send_cq, &recv_cq);
2131         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2132         mlx5_ib_lock_cqs(send_cq, recv_cq);
2133         /* Maintain device to QPs access, needed for further handling via reset
2134          * flow
2135          */
2136         list_add_tail(&qp->qps_list, &dev->qp_list);
2137         /* Maintain CQ to QPs access, needed for further handling via reset flow
2138          */
2139         if (send_cq)
2140                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2141         if (recv_cq)
2142                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2143         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2144         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2145
2146         return 0;
2147
2148 err_create:
2149         if (qp->create_type == MLX5_QP_USER)
2150                 destroy_qp_user(dev, pd, qp, base);
2151         else if (qp->create_type == MLX5_QP_KERNEL)
2152                 destroy_qp_kernel(dev, qp);
2153
2154 err:
2155         kvfree(in);
2156         return err;
2157 }
2158
2159 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2160         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2161 {
2162         if (send_cq) {
2163                 if (recv_cq) {
2164                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2165                                 spin_lock(&send_cq->lock);
2166                                 spin_lock_nested(&recv_cq->lock,
2167                                                  SINGLE_DEPTH_NESTING);
2168                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2169                                 spin_lock(&send_cq->lock);
2170                                 __acquire(&recv_cq->lock);
2171                         } else {
2172                                 spin_lock(&recv_cq->lock);
2173                                 spin_lock_nested(&send_cq->lock,
2174                                                  SINGLE_DEPTH_NESTING);
2175                         }
2176                 } else {
2177                         spin_lock(&send_cq->lock);
2178                         __acquire(&recv_cq->lock);
2179                 }
2180         } else if (recv_cq) {
2181                 spin_lock(&recv_cq->lock);
2182                 __acquire(&send_cq->lock);
2183         } else {
2184                 __acquire(&send_cq->lock);
2185                 __acquire(&recv_cq->lock);
2186         }
2187 }
2188
2189 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2190         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2191 {
2192         if (send_cq) {
2193                 if (recv_cq) {
2194                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2195                                 spin_unlock(&recv_cq->lock);
2196                                 spin_unlock(&send_cq->lock);
2197                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2198                                 __release(&recv_cq->lock);
2199                                 spin_unlock(&send_cq->lock);
2200                         } else {
2201                                 spin_unlock(&send_cq->lock);
2202                                 spin_unlock(&recv_cq->lock);
2203                         }
2204                 } else {
2205                         __release(&recv_cq->lock);
2206                         spin_unlock(&send_cq->lock);
2207                 }
2208         } else if (recv_cq) {
2209                 __release(&send_cq->lock);
2210                 spin_unlock(&recv_cq->lock);
2211         } else {
2212                 __release(&recv_cq->lock);
2213                 __release(&send_cq->lock);
2214         }
2215 }
2216
2217 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2218 {
2219         return to_mpd(qp->ibqp.pd);
2220 }
2221
2222 static void get_cqs(enum ib_qp_type qp_type,
2223                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2224                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2225 {
2226         switch (qp_type) {
2227         case IB_QPT_XRC_TGT:
2228                 *send_cq = NULL;
2229                 *recv_cq = NULL;
2230                 break;
2231         case MLX5_IB_QPT_REG_UMR:
2232         case IB_QPT_XRC_INI:
2233                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2234                 *recv_cq = NULL;
2235                 break;
2236
2237         case IB_QPT_SMI:
2238         case MLX5_IB_QPT_HW_GSI:
2239         case IB_QPT_RC:
2240         case IB_QPT_UC:
2241         case IB_QPT_UD:
2242         case IB_QPT_RAW_IPV6:
2243         case IB_QPT_RAW_ETHERTYPE:
2244         case IB_QPT_RAW_PACKET:
2245                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2246                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2247                 break;
2248
2249         case IB_QPT_MAX:
2250         default:
2251                 *send_cq = NULL;
2252                 *recv_cq = NULL;
2253                 break;
2254         }
2255 }
2256
2257 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2258                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2259                                 u8 lag_tx_affinity);
2260
2261 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2262 {
2263         struct mlx5_ib_cq *send_cq, *recv_cq;
2264         struct mlx5_ib_qp_base *base;
2265         unsigned long flags;
2266         int err;
2267
2268         if (qp->ibqp.rwq_ind_tbl) {
2269                 destroy_rss_raw_qp_tir(dev, qp);
2270                 return;
2271         }
2272
2273         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2274                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2275                &qp->raw_packet_qp.rq.base :
2276                &qp->trans_qp.base;
2277
2278         if (qp->state != IB_QPS_RESET) {
2279                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2280                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2281                         err = mlx5_core_qp_modify(dev->mdev,
2282                                                   MLX5_CMD_OP_2RST_QP, 0,
2283                                                   NULL, &base->mqp);
2284                 } else {
2285                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2286                                 .operation = MLX5_CMD_OP_2RST_QP
2287                         };
2288
2289                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2290                 }
2291                 if (err)
2292                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2293                                      base->mqp.qpn);
2294         }
2295
2296         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2297                 &send_cq, &recv_cq);
2298
2299         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2300         mlx5_ib_lock_cqs(send_cq, recv_cq);
2301         /* del from lists under both locks above to protect reset flow paths */
2302         list_del(&qp->qps_list);
2303         if (send_cq)
2304                 list_del(&qp->cq_send_list);
2305
2306         if (recv_cq)
2307                 list_del(&qp->cq_recv_list);
2308
2309         if (qp->create_type == MLX5_QP_KERNEL) {
2310                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2311                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2312                 if (send_cq != recv_cq)
2313                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2314                                            NULL);
2315         }
2316         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2317         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2318
2319         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2320             qp->flags & MLX5_IB_QP_UNDERLAY) {
2321                 destroy_raw_packet_qp(dev, qp);
2322         } else {
2323                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2324                 if (err)
2325                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2326                                      base->mqp.qpn);
2327         }
2328
2329         if (qp->create_type == MLX5_QP_KERNEL)
2330                 destroy_qp_kernel(dev, qp);
2331         else if (qp->create_type == MLX5_QP_USER)
2332                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2333 }
2334
2335 static const char *ib_qp_type_str(enum ib_qp_type type)
2336 {
2337         switch (type) {
2338         case IB_QPT_SMI:
2339                 return "IB_QPT_SMI";
2340         case IB_QPT_GSI:
2341                 return "IB_QPT_GSI";
2342         case IB_QPT_RC:
2343                 return "IB_QPT_RC";
2344         case IB_QPT_UC:
2345                 return "IB_QPT_UC";
2346         case IB_QPT_UD:
2347                 return "IB_QPT_UD";
2348         case IB_QPT_RAW_IPV6:
2349                 return "IB_QPT_RAW_IPV6";
2350         case IB_QPT_RAW_ETHERTYPE:
2351                 return "IB_QPT_RAW_ETHERTYPE";
2352         case IB_QPT_XRC_INI:
2353                 return "IB_QPT_XRC_INI";
2354         case IB_QPT_XRC_TGT:
2355                 return "IB_QPT_XRC_TGT";
2356         case IB_QPT_RAW_PACKET:
2357                 return "IB_QPT_RAW_PACKET";
2358         case MLX5_IB_QPT_REG_UMR:
2359                 return "MLX5_IB_QPT_REG_UMR";
2360         case IB_QPT_DRIVER:
2361                 return "IB_QPT_DRIVER";
2362         case IB_QPT_MAX:
2363         default:
2364                 return "Invalid QP type";
2365         }
2366 }
2367
2368 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2369                                         struct ib_qp_init_attr *attr,
2370                                         struct mlx5_ib_create_qp *ucmd)
2371 {
2372         struct mlx5_ib_qp *qp;
2373         int err = 0;
2374         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2375         void *dctc;
2376
2377         if (!attr->srq || !attr->recv_cq)
2378                 return ERR_PTR(-EINVAL);
2379
2380         err = get_qp_user_index(to_mucontext(pd->uobject->context),
2381                                 ucmd, sizeof(*ucmd), &uidx);
2382         if (err)
2383                 return ERR_PTR(err);
2384
2385         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2386         if (!qp)
2387                 return ERR_PTR(-ENOMEM);
2388
2389         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2390         if (!qp->dct.in) {
2391                 err = -ENOMEM;
2392                 goto err_free;
2393         }
2394
2395         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2396         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2397         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2398         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2399         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2400         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2401         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2402         MLX5_SET(dctc, dctc, user_index, uidx);
2403
2404         if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2405                 configure_responder_scat_cqe(attr, dctc);
2406
2407         qp->state = IB_QPS_RESET;
2408
2409         return &qp->ibqp;
2410 err_free:
2411         kfree(qp);
2412         return ERR_PTR(err);
2413 }
2414
2415 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2416                            struct ib_qp_init_attr *init_attr,
2417                            struct mlx5_ib_create_qp *ucmd,
2418                            struct ib_udata *udata)
2419 {
2420         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2421         int err;
2422
2423         if (!udata)
2424                 return -EINVAL;
2425
2426         if (udata->inlen < sizeof(*ucmd)) {
2427                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2428                 return -EINVAL;
2429         }
2430         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2431         if (err)
2432                 return err;
2433
2434         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2435                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2436         } else {
2437                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2438                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2439                 } else {
2440                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2441                         return -EINVAL;
2442                 }
2443         }
2444
2445         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2446                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2447                 return -EOPNOTSUPP;
2448         }
2449
2450         return 0;
2451 }
2452
2453 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2454                                 struct ib_qp_init_attr *verbs_init_attr,
2455                                 struct ib_udata *udata)
2456 {
2457         struct mlx5_ib_dev *dev;
2458         struct mlx5_ib_qp *qp;
2459         u16 xrcdn = 0;
2460         int err;
2461         struct ib_qp_init_attr mlx_init_attr;
2462         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2463
2464         if (pd) {
2465                 dev = to_mdev(pd->device);
2466
2467                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2468                         if (!pd->uobject) {
2469                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2470                                 return ERR_PTR(-EINVAL);
2471                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2472                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2473                                 return ERR_PTR(-EINVAL);
2474                         }
2475                 }
2476         } else {
2477                 /* being cautious here */
2478                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2479                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2480                         pr_warn("%s: no PD for transport %s\n", __func__,
2481                                 ib_qp_type_str(init_attr->qp_type));
2482                         return ERR_PTR(-EINVAL);
2483                 }
2484                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2485         }
2486
2487         if (init_attr->qp_type == IB_QPT_DRIVER) {
2488                 struct mlx5_ib_create_qp ucmd;
2489
2490                 init_attr = &mlx_init_attr;
2491                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2492                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2493                 if (err)
2494                         return ERR_PTR(err);
2495
2496                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2497                         if (init_attr->cap.max_recv_wr ||
2498                             init_attr->cap.max_recv_sge) {
2499                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2500                                 return ERR_PTR(-EINVAL);
2501                         }
2502                 } else {
2503                         return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2504                 }
2505         }
2506
2507         switch (init_attr->qp_type) {
2508         case IB_QPT_XRC_TGT:
2509         case IB_QPT_XRC_INI:
2510                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2511                         mlx5_ib_dbg(dev, "XRC not supported\n");
2512                         return ERR_PTR(-ENOSYS);
2513                 }
2514                 init_attr->recv_cq = NULL;
2515                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2516                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2517                         init_attr->send_cq = NULL;
2518                 }
2519
2520                 /* fall through */
2521         case IB_QPT_RAW_PACKET:
2522         case IB_QPT_RC:
2523         case IB_QPT_UC:
2524         case IB_QPT_UD:
2525         case IB_QPT_SMI:
2526         case MLX5_IB_QPT_HW_GSI:
2527         case MLX5_IB_QPT_REG_UMR:
2528         case MLX5_IB_QPT_DCI:
2529                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2530                 if (!qp)
2531                         return ERR_PTR(-ENOMEM);
2532
2533                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2534                 if (err) {
2535                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2536                         kfree(qp);
2537                         return ERR_PTR(err);
2538                 }
2539
2540                 if (is_qp0(init_attr->qp_type))
2541                         qp->ibqp.qp_num = 0;
2542                 else if (is_qp1(init_attr->qp_type))
2543                         qp->ibqp.qp_num = 1;
2544                 else
2545                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2546
2547                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2548                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2549                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2550                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2551
2552                 qp->trans_qp.xrcdn = xrcdn;
2553
2554                 break;
2555
2556         case IB_QPT_GSI:
2557                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2558
2559         case IB_QPT_RAW_IPV6:
2560         case IB_QPT_RAW_ETHERTYPE:
2561         case IB_QPT_MAX:
2562         default:
2563                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2564                             init_attr->qp_type);
2565                 /* Don't support raw QPs */
2566                 return ERR_PTR(-EINVAL);
2567         }
2568
2569         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2570                 qp->qp_sub_type = init_attr->qp_type;
2571
2572         return &qp->ibqp;
2573 }
2574
2575 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2576 {
2577         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2578
2579         if (mqp->state == IB_QPS_RTR) {
2580                 int err;
2581
2582                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2583                 if (err) {
2584                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2585                         return err;
2586                 }
2587         }
2588
2589         kfree(mqp->dct.in);
2590         kfree(mqp);
2591         return 0;
2592 }
2593
2594 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2595 {
2596         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2597         struct mlx5_ib_qp *mqp = to_mqp(qp);
2598
2599         if (unlikely(qp->qp_type == IB_QPT_GSI))
2600                 return mlx5_ib_gsi_destroy_qp(qp);
2601
2602         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2603                 return mlx5_ib_destroy_dct(mqp);
2604
2605         destroy_qp_common(dev, mqp);
2606
2607         kfree(mqp);
2608
2609         return 0;
2610 }
2611
2612 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2613                                 const struct ib_qp_attr *attr,
2614                                 int attr_mask, __be32 *hw_access_flags)
2615 {
2616         u8 dest_rd_atomic;
2617         u32 access_flags;
2618
2619         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2620
2621         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2622                 dest_rd_atomic = attr->max_dest_rd_atomic;
2623         else
2624                 dest_rd_atomic = qp->trans_qp.resp_depth;
2625
2626         if (attr_mask & IB_QP_ACCESS_FLAGS)
2627                 access_flags = attr->qp_access_flags;
2628         else
2629                 access_flags = qp->trans_qp.atomic_rd_en;
2630
2631         if (!dest_rd_atomic)
2632                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2633
2634         if (access_flags & IB_ACCESS_REMOTE_READ)
2635                 *hw_access_flags |= MLX5_QP_BIT_RRE;
2636         if ((access_flags & IB_ACCESS_REMOTE_ATOMIC) &&
2637             qp->ibqp.qp_type == IB_QPT_RC) {
2638                 int atomic_mode;
2639
2640                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2641                 if (atomic_mode < 0)
2642                         return -EOPNOTSUPP;
2643
2644                 *hw_access_flags |= MLX5_QP_BIT_RAE;
2645                 *hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2646         }
2647
2648         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2649                 *hw_access_flags |= MLX5_QP_BIT_RWE;
2650
2651         *hw_access_flags = cpu_to_be32(*hw_access_flags);
2652
2653         return 0;
2654 }
2655
2656 enum {
2657         MLX5_PATH_FLAG_FL       = 1 << 0,
2658         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2659         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2660 };
2661
2662 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2663 {
2664         if (rate == IB_RATE_PORT_CURRENT)
2665                 return 0;
2666
2667         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2668                 return -EINVAL;
2669
2670         while (rate != IB_RATE_PORT_CURRENT &&
2671                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2672                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2673                 --rate;
2674
2675         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2676 }
2677
2678 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2679                                       struct mlx5_ib_sq *sq, u8 sl,
2680                                       struct ib_pd *pd)
2681 {
2682         void *in;
2683         void *tisc;
2684         int inlen;
2685         int err;
2686
2687         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2688         in = kvzalloc(inlen, GFP_KERNEL);
2689         if (!in)
2690                 return -ENOMEM;
2691
2692         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2693         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2694
2695         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2696         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2697
2698         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2699
2700         kvfree(in);
2701
2702         return err;
2703 }
2704
2705 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2706                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2707                                          struct ib_pd *pd)
2708 {
2709         void *in;
2710         void *tisc;
2711         int inlen;
2712         int err;
2713
2714         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2715         in = kvzalloc(inlen, GFP_KERNEL);
2716         if (!in)
2717                 return -ENOMEM;
2718
2719         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2720         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2721
2722         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2723         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2724
2725         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2726
2727         kvfree(in);
2728
2729         return err;
2730 }
2731
2732 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2733                          const struct rdma_ah_attr *ah,
2734                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2735                          u32 path_flags, const struct ib_qp_attr *attr,
2736                          bool alt)
2737 {
2738         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2739         int err;
2740         enum ib_gid_type gid_type;
2741         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2742         u8 sl = rdma_ah_get_sl(ah);
2743
2744         if (attr_mask & IB_QP_PKEY_INDEX)
2745                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2746                                                      attr->pkey_index);
2747
2748         if (ah_flags & IB_AH_GRH) {
2749                 if (grh->sgid_index >=
2750                     dev->mdev->port_caps[port - 1].gid_table_len) {
2751                         pr_err("sgid_index (%u) too large. max is %d\n",
2752                                grh->sgid_index,
2753                                dev->mdev->port_caps[port - 1].gid_table_len);
2754                         return -EINVAL;
2755                 }
2756         }
2757
2758         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2759                 if (!(ah_flags & IB_AH_GRH))
2760                         return -EINVAL;
2761
2762                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2763                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2764                     qp->ibqp.qp_type == IB_QPT_UC ||
2765                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2766                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2767                         path->udp_sport =
2768                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2769                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2770                 gid_type = ah->grh.sgid_attr->gid_type;
2771                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2772                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2773         } else {
2774                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2775                 path->fl_free_ar |=
2776                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2777                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2778                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2779                 if (ah_flags & IB_AH_GRH)
2780                         path->grh_mlid  |= 1 << 7;
2781                 path->dci_cfi_prio_sl = sl & 0xf;
2782         }
2783
2784         if (ah_flags & IB_AH_GRH) {
2785                 path->mgid_index = grh->sgid_index;
2786                 path->hop_limit  = grh->hop_limit;
2787                 path->tclass_flowlabel =
2788                         cpu_to_be32((grh->traffic_class << 20) |
2789                                     (grh->flow_label));
2790                 memcpy(path->rgid, grh->dgid.raw, 16);
2791         }
2792
2793         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2794         if (err < 0)
2795                 return err;
2796         path->static_rate = err;
2797         path->port = port;
2798
2799         if (attr_mask & IB_QP_TIMEOUT)
2800                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2801
2802         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2803                 return modify_raw_packet_eth_prio(dev->mdev,
2804                                                   &qp->raw_packet_qp.sq,
2805                                                   sl & 0xf, qp->ibqp.pd);
2806
2807         return 0;
2808 }
2809
2810 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2811         [MLX5_QP_STATE_INIT] = {
2812                 [MLX5_QP_STATE_INIT] = {
2813                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2814                                           MLX5_QP_OPTPAR_RAE            |
2815                                           MLX5_QP_OPTPAR_RWE            |
2816                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2817                                           MLX5_QP_OPTPAR_PRI_PORT,
2818                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2819                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2820                                           MLX5_QP_OPTPAR_PRI_PORT,
2821                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2822                                           MLX5_QP_OPTPAR_Q_KEY          |
2823                                           MLX5_QP_OPTPAR_PRI_PORT,
2824                 },
2825                 [MLX5_QP_STATE_RTR] = {
2826                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2827                                           MLX5_QP_OPTPAR_RRE            |
2828                                           MLX5_QP_OPTPAR_RAE            |
2829                                           MLX5_QP_OPTPAR_RWE            |
2830                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2831                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2832                                           MLX5_QP_OPTPAR_RWE            |
2833                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2834                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2835                                           MLX5_QP_OPTPAR_Q_KEY,
2836                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2837                                            MLX5_QP_OPTPAR_Q_KEY,
2838                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2839                                           MLX5_QP_OPTPAR_RRE            |
2840                                           MLX5_QP_OPTPAR_RAE            |
2841                                           MLX5_QP_OPTPAR_RWE            |
2842                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2843                 },
2844         },
2845         [MLX5_QP_STATE_RTR] = {
2846                 [MLX5_QP_STATE_RTS] = {
2847                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2848                                           MLX5_QP_OPTPAR_RRE            |
2849                                           MLX5_QP_OPTPAR_RAE            |
2850                                           MLX5_QP_OPTPAR_RWE            |
2851                                           MLX5_QP_OPTPAR_PM_STATE       |
2852                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2853                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2854                                           MLX5_QP_OPTPAR_RWE            |
2855                                           MLX5_QP_OPTPAR_PM_STATE,
2856                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2857                 },
2858         },
2859         [MLX5_QP_STATE_RTS] = {
2860                 [MLX5_QP_STATE_RTS] = {
2861                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2862                                           MLX5_QP_OPTPAR_RAE            |
2863                                           MLX5_QP_OPTPAR_RWE            |
2864                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2865                                           MLX5_QP_OPTPAR_PM_STATE       |
2866                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2867                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2868                                           MLX5_QP_OPTPAR_PM_STATE       |
2869                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2870                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2871                                           MLX5_QP_OPTPAR_SRQN           |
2872                                           MLX5_QP_OPTPAR_CQN_RCV,
2873                 },
2874         },
2875         [MLX5_QP_STATE_SQER] = {
2876                 [MLX5_QP_STATE_RTS] = {
2877                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2878                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2879                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2880                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2881                                            MLX5_QP_OPTPAR_RWE           |
2882                                            MLX5_QP_OPTPAR_RAE           |
2883                                            MLX5_QP_OPTPAR_RRE,
2884                 },
2885         },
2886 };
2887
2888 static int ib_nr_to_mlx5_nr(int ib_mask)
2889 {
2890         switch (ib_mask) {
2891         case IB_QP_STATE:
2892                 return 0;
2893         case IB_QP_CUR_STATE:
2894                 return 0;
2895         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2896                 return 0;
2897         case IB_QP_ACCESS_FLAGS:
2898                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2899                         MLX5_QP_OPTPAR_RAE;
2900         case IB_QP_PKEY_INDEX:
2901                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2902         case IB_QP_PORT:
2903                 return MLX5_QP_OPTPAR_PRI_PORT;
2904         case IB_QP_QKEY:
2905                 return MLX5_QP_OPTPAR_Q_KEY;
2906         case IB_QP_AV:
2907                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2908                         MLX5_QP_OPTPAR_PRI_PORT;
2909         case IB_QP_PATH_MTU:
2910                 return 0;
2911         case IB_QP_TIMEOUT:
2912                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2913         case IB_QP_RETRY_CNT:
2914                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2915         case IB_QP_RNR_RETRY:
2916                 return MLX5_QP_OPTPAR_RNR_RETRY;
2917         case IB_QP_RQ_PSN:
2918                 return 0;
2919         case IB_QP_MAX_QP_RD_ATOMIC:
2920                 return MLX5_QP_OPTPAR_SRA_MAX;
2921         case IB_QP_ALT_PATH:
2922                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2923         case IB_QP_MIN_RNR_TIMER:
2924                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2925         case IB_QP_SQ_PSN:
2926                 return 0;
2927         case IB_QP_MAX_DEST_RD_ATOMIC:
2928                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2929                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2930         case IB_QP_PATH_MIG_STATE:
2931                 return MLX5_QP_OPTPAR_PM_STATE;
2932         case IB_QP_CAP:
2933                 return 0;
2934         case IB_QP_DEST_QPN:
2935                 return 0;
2936         }
2937         return 0;
2938 }
2939
2940 static int ib_mask_to_mlx5_opt(int ib_mask)
2941 {
2942         int result = 0;
2943         int i;
2944
2945         for (i = 0; i < 8 * sizeof(int); i++) {
2946                 if ((1 << i) & ib_mask)
2947                         result |= ib_nr_to_mlx5_nr(1 << i);
2948         }
2949
2950         return result;
2951 }
2952
2953 static int modify_raw_packet_qp_rq(
2954         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2955         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
2956 {
2957         void *in;
2958         void *rqc;
2959         int inlen;
2960         int err;
2961
2962         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2963         in = kvzalloc(inlen, GFP_KERNEL);
2964         if (!in)
2965                 return -ENOMEM;
2966
2967         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2968         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
2969
2970         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2971         MLX5_SET(rqc, rqc, state, new_state);
2972
2973         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2974                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2975                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2976                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2977                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2978                 } else
2979                         dev_info_once(
2980                                 &dev->ib_dev.dev,
2981                                 "RAW PACKET QP counters are not supported on current FW\n");
2982         }
2983
2984         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2985         if (err)
2986                 goto out;
2987
2988         rq->state = new_state;
2989
2990 out:
2991         kvfree(in);
2992         return err;
2993 }
2994
2995 static int modify_raw_packet_qp_sq(
2996         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
2997         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
2998 {
2999         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3000         struct mlx5_rate_limit old_rl = ibqp->rl;
3001         struct mlx5_rate_limit new_rl = old_rl;
3002         bool new_rate_added = false;
3003         u16 rl_index = 0;
3004         void *in;
3005         void *sqc;
3006         int inlen;
3007         int err;
3008
3009         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3010         in = kvzalloc(inlen, GFP_KERNEL);
3011         if (!in)
3012                 return -ENOMEM;
3013
3014         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3015         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3016
3017         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3018         MLX5_SET(sqc, sqc, state, new_state);
3019
3020         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3021                 if (new_state != MLX5_SQC_STATE_RDY)
3022                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3023                                 __func__);
3024                 else
3025                         new_rl = raw_qp_param->rl;
3026         }
3027
3028         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3029                 if (new_rl.rate) {
3030                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3031                         if (err) {
3032                                 pr_err("Failed configuring rate limit(err %d): \
3033                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3034                                        err, new_rl.rate, new_rl.max_burst_sz,
3035                                        new_rl.typical_pkt_sz);
3036
3037                                 goto out;
3038                         }
3039                         new_rate_added = true;
3040                 }
3041
3042                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3043                 /* index 0 means no limit */
3044                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3045         }
3046
3047         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
3048         if (err) {
3049                 /* Remove new rate from table if failed */
3050                 if (new_rate_added)
3051                         mlx5_rl_remove_rate(dev, &new_rl);
3052                 goto out;
3053         }
3054
3055         /* Only remove the old rate after new rate was set */
3056         if ((old_rl.rate &&
3057              !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3058             (new_state != MLX5_SQC_STATE_RDY))
3059                 mlx5_rl_remove_rate(dev, &old_rl);
3060
3061         ibqp->rl = new_rl;
3062         sq->state = new_state;
3063
3064 out:
3065         kvfree(in);
3066         return err;
3067 }
3068
3069 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3070                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3071                                 u8 tx_affinity)
3072 {
3073         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3074         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3075         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3076         int modify_rq = !!qp->rq.wqe_cnt;
3077         int modify_sq = !!qp->sq.wqe_cnt;
3078         int rq_state;
3079         int sq_state;
3080         int err;
3081
3082         switch (raw_qp_param->operation) {
3083         case MLX5_CMD_OP_RST2INIT_QP:
3084                 rq_state = MLX5_RQC_STATE_RDY;
3085                 sq_state = MLX5_SQC_STATE_RDY;
3086                 break;
3087         case MLX5_CMD_OP_2ERR_QP:
3088                 rq_state = MLX5_RQC_STATE_ERR;
3089                 sq_state = MLX5_SQC_STATE_ERR;
3090                 break;
3091         case MLX5_CMD_OP_2RST_QP:
3092                 rq_state = MLX5_RQC_STATE_RST;
3093                 sq_state = MLX5_SQC_STATE_RST;
3094                 break;
3095         case MLX5_CMD_OP_RTR2RTS_QP:
3096         case MLX5_CMD_OP_RTS2RTS_QP:
3097                 if (raw_qp_param->set_mask ==
3098                     MLX5_RAW_QP_RATE_LIMIT) {
3099                         modify_rq = 0;
3100                         sq_state = sq->state;
3101                 } else {
3102                         return raw_qp_param->set_mask ? -EINVAL : 0;
3103                 }
3104                 break;
3105         case MLX5_CMD_OP_INIT2INIT_QP:
3106         case MLX5_CMD_OP_INIT2RTR_QP:
3107                 if (raw_qp_param->set_mask)
3108                         return -EINVAL;
3109                 else
3110                         return 0;
3111         default:
3112                 WARN_ON(1);
3113                 return -EINVAL;
3114         }
3115
3116         if (modify_rq) {
3117                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3118                                                qp->ibqp.pd);
3119                 if (err)
3120                         return err;
3121         }
3122
3123         if (modify_sq) {
3124                 if (tx_affinity) {
3125                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3126                                                             tx_affinity,
3127                                                             qp->ibqp.pd);
3128                         if (err)
3129                                 return err;
3130                 }
3131
3132                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3133                                                raw_qp_param, qp->ibqp.pd);
3134         }
3135
3136         return 0;
3137 }
3138
3139 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3140                                     struct mlx5_ib_pd *pd,
3141                                     struct mlx5_ib_qp_base *qp_base,
3142                                     u8 port_num)
3143 {
3144         struct mlx5_ib_ucontext *ucontext = NULL;
3145         unsigned int tx_port_affinity;
3146
3147         if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3148                 ucontext = to_mucontext(pd->ibpd.uobject->context);
3149
3150         if (ucontext) {
3151                 tx_port_affinity = (unsigned int)atomic_add_return(
3152                                            1, &ucontext->tx_port_affinity) %
3153                                            MLX5_MAX_PORTS +
3154                                    1;
3155                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3156                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3157         } else {
3158                 tx_port_affinity =
3159                         (unsigned int)atomic_add_return(
3160                                 1, &dev->roce[port_num].tx_port_affinity) %
3161                                 MLX5_MAX_PORTS +
3162                         1;
3163                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3164                                 tx_port_affinity, qp_base->mqp.qpn);
3165         }
3166
3167         return tx_port_affinity;
3168 }
3169
3170 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3171                                const struct ib_qp_attr *attr, int attr_mask,
3172                                enum ib_qp_state cur_state, enum ib_qp_state new_state,
3173                                const struct mlx5_ib_modify_qp *ucmd)
3174 {
3175         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3176                 [MLX5_QP_STATE_RST] = {
3177                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3178                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3179                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3180                 },
3181                 [MLX5_QP_STATE_INIT]  = {
3182                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3183                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3184                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3185                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3186                 },
3187                 [MLX5_QP_STATE_RTR]   = {
3188                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3189                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3190                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3191                 },
3192                 [MLX5_QP_STATE_RTS]   = {
3193                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3194                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3195                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3196                 },
3197                 [MLX5_QP_STATE_SQD] = {
3198                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3199                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3200                 },
3201                 [MLX5_QP_STATE_SQER] = {
3202                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3203                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3204                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3205                 },
3206                 [MLX5_QP_STATE_ERR] = {
3207                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3208                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3209                 }
3210         };
3211
3212         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3213         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3214         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3215         struct mlx5_ib_cq *send_cq, *recv_cq;
3216         struct mlx5_qp_context *context;
3217         struct mlx5_ib_pd *pd;
3218         struct mlx5_ib_port *mibport = NULL;
3219         enum mlx5_qp_state mlx5_cur, mlx5_new;
3220         enum mlx5_qp_optpar optpar;
3221         int mlx5_st;
3222         int err;
3223         u16 op;
3224         u8 tx_affinity = 0;
3225
3226         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3227                              qp->qp_sub_type : ibqp->qp_type);
3228         if (mlx5_st < 0)
3229                 return -EINVAL;
3230
3231         context = kzalloc(sizeof(*context), GFP_KERNEL);
3232         if (!context)
3233                 return -ENOMEM;
3234
3235         pd = get_pd(qp);
3236         context->flags = cpu_to_be32(mlx5_st << 16);
3237
3238         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3239                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3240         } else {
3241                 switch (attr->path_mig_state) {
3242                 case IB_MIG_MIGRATED:
3243                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3244                         break;
3245                 case IB_MIG_REARM:
3246                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3247                         break;
3248                 case IB_MIG_ARMED:
3249                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3250                         break;
3251                 }
3252         }
3253
3254         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3255                 if ((ibqp->qp_type == IB_QPT_RC) ||
3256                     (ibqp->qp_type == IB_QPT_UD &&
3257                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3258                     (ibqp->qp_type == IB_QPT_UC) ||
3259                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3260                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3261                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3262                         if (mlx5_lag_is_active(dev->mdev)) {
3263                                 u8 p = mlx5_core_native_port_num(dev->mdev);
3264                                 tx_affinity = get_tx_affinity(dev, pd, base, p);
3265                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3266                         }
3267                 }
3268         }
3269
3270         if (is_sqp(ibqp->qp_type)) {
3271                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3272         } else if ((ibqp->qp_type == IB_QPT_UD &&
3273                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3274                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3275                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3276         } else if (attr_mask & IB_QP_PATH_MTU) {
3277                 if (attr->path_mtu < IB_MTU_256 ||
3278                     attr->path_mtu > IB_MTU_4096) {
3279                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3280                         err = -EINVAL;
3281                         goto out;
3282                 }
3283                 context->mtu_msgmax = (attr->path_mtu << 5) |
3284                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3285         }
3286
3287         if (attr_mask & IB_QP_DEST_QPN)
3288                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3289
3290         if (attr_mask & IB_QP_PKEY_INDEX)
3291                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3292
3293         /* todo implement counter_index functionality */
3294
3295         if (is_sqp(ibqp->qp_type))
3296                 context->pri_path.port = qp->port;
3297
3298         if (attr_mask & IB_QP_PORT)
3299                 context->pri_path.port = attr->port_num;
3300
3301         if (attr_mask & IB_QP_AV) {
3302                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3303                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3304                                     attr_mask, 0, attr, false);
3305                 if (err)
3306                         goto out;
3307         }
3308
3309         if (attr_mask & IB_QP_TIMEOUT)
3310                 context->pri_path.ackto_lt |= attr->timeout << 3;
3311
3312         if (attr_mask & IB_QP_ALT_PATH) {
3313                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3314                                     &context->alt_path,
3315                                     attr->alt_port_num,
3316                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3317                                     0, attr, true);
3318                 if (err)
3319                         goto out;
3320         }
3321
3322         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3323                 &send_cq, &recv_cq);
3324
3325         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3326         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3327         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3328         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3329
3330         if (attr_mask & IB_QP_RNR_RETRY)
3331                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3332
3333         if (attr_mask & IB_QP_RETRY_CNT)
3334                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3335
3336         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3337                 if (attr->max_rd_atomic)
3338                         context->params1 |=
3339                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3340         }
3341
3342         if (attr_mask & IB_QP_SQ_PSN)
3343                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3344
3345         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3346                 if (attr->max_dest_rd_atomic)
3347                         context->params2 |=
3348                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3349         }
3350
3351         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3352                 __be32 access_flags = 0;
3353
3354                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3355                 if (err)
3356                         goto out;
3357
3358                 context->params2 |= access_flags;
3359         }
3360
3361         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3362                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3363
3364         if (attr_mask & IB_QP_RQ_PSN)
3365                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3366
3367         if (attr_mask & IB_QP_QKEY)
3368                 context->qkey = cpu_to_be32(attr->qkey);
3369
3370         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3371                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3372
3373         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3374                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3375                                qp->port) - 1;
3376
3377                 /* Underlay port should be used - index 0 function per port */
3378                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3379                         port_num = 0;
3380
3381                 mibport = &dev->port[port_num];
3382                 context->qp_counter_set_usr_page |=
3383                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3384         }
3385
3386         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3387                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3388
3389         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3390                 context->deth_sqpn = cpu_to_be32(1);
3391
3392         mlx5_cur = to_mlx5_state(cur_state);
3393         mlx5_new = to_mlx5_state(new_state);
3394
3395         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3396             !optab[mlx5_cur][mlx5_new]) {
3397                 err = -EINVAL;
3398                 goto out;
3399         }
3400
3401         op = optab[mlx5_cur][mlx5_new];
3402         optpar = ib_mask_to_mlx5_opt(attr_mask);
3403         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3404
3405         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3406             qp->flags & MLX5_IB_QP_UNDERLAY) {
3407                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3408
3409                 raw_qp_param.operation = op;
3410                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3411                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3412                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3413                 }
3414
3415                 if (attr_mask & IB_QP_RATE_LIMIT) {
3416                         raw_qp_param.rl.rate = attr->rate_limit;
3417
3418                         if (ucmd->burst_info.max_burst_sz) {
3419                                 if (attr->rate_limit &&
3420                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3421                                         raw_qp_param.rl.max_burst_sz =
3422                                                 ucmd->burst_info.max_burst_sz;
3423                                 } else {
3424                                         err = -EINVAL;
3425                                         goto out;
3426                                 }
3427                         }
3428
3429                         if (ucmd->burst_info.typical_pkt_sz) {
3430                                 if (attr->rate_limit &&
3431                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3432                                         raw_qp_param.rl.typical_pkt_sz =
3433                                                 ucmd->burst_info.typical_pkt_sz;
3434                                 } else {
3435                                         err = -EINVAL;
3436                                         goto out;
3437                                 }
3438                         }
3439
3440                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3441                 }
3442
3443                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3444         } else {
3445                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3446                                           &base->mqp);
3447         }
3448
3449         if (err)
3450                 goto out;
3451
3452         qp->state = new_state;
3453
3454         if (attr_mask & IB_QP_ACCESS_FLAGS)
3455                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3456         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3457                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3458         if (attr_mask & IB_QP_PORT)
3459                 qp->port = attr->port_num;
3460         if (attr_mask & IB_QP_ALT_PATH)
3461                 qp->trans_qp.alt_port = attr->alt_port_num;
3462
3463         /*
3464          * If we moved a kernel QP to RESET, clean up all old CQ
3465          * entries and reinitialize the QP.
3466          */
3467         if (new_state == IB_QPS_RESET &&
3468             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3469                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3470                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3471                 if (send_cq != recv_cq)
3472                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3473
3474                 qp->rq.head = 0;
3475                 qp->rq.tail = 0;
3476                 qp->sq.head = 0;
3477                 qp->sq.tail = 0;
3478                 qp->sq.cur_post = 0;
3479                 qp->sq.last_poll = 0;
3480                 qp->db.db[MLX5_RCV_DBR] = 0;
3481                 qp->db.db[MLX5_SND_DBR] = 0;
3482         }
3483
3484 out:
3485         kfree(context);
3486         return err;
3487 }
3488
3489 static inline bool is_valid_mask(int mask, int req, int opt)
3490 {
3491         if ((mask & req) != req)
3492                 return false;
3493
3494         if (mask & ~(req | opt))
3495                 return false;
3496
3497         return true;
3498 }
3499
3500 /* check valid transition for driver QP types
3501  * for now the only QP type that this function supports is DCI
3502  */
3503 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3504                                 enum ib_qp_attr_mask attr_mask)
3505 {
3506         int req = IB_QP_STATE;
3507         int opt = 0;
3508
3509         if (new_state == IB_QPS_RESET) {
3510                 return is_valid_mask(attr_mask, req, opt);
3511         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3512                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3513                 return is_valid_mask(attr_mask, req, opt);
3514         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3515                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3516                 return is_valid_mask(attr_mask, req, opt);
3517         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3518                 req |= IB_QP_PATH_MTU;
3519                 opt = IB_QP_PKEY_INDEX;
3520                 return is_valid_mask(attr_mask, req, opt);
3521         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3522                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3523                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3524                 opt = IB_QP_MIN_RNR_TIMER;
3525                 return is_valid_mask(attr_mask, req, opt);
3526         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3527                 opt = IB_QP_MIN_RNR_TIMER;
3528                 return is_valid_mask(attr_mask, req, opt);
3529         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3530                 return is_valid_mask(attr_mask, req, opt);
3531         }
3532         return false;
3533 }
3534
3535 /* mlx5_ib_modify_dct: modify a DCT QP
3536  * valid transitions are:
3537  * RESET to INIT: must set access_flags, pkey_index and port
3538  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3539  *                         mtu, gid_index and hop_limit
3540  * Other transitions and attributes are illegal
3541  */
3542 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3543                               int attr_mask, struct ib_udata *udata)
3544 {
3545         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3546         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3547         enum ib_qp_state cur_state, new_state;
3548         int err = 0;
3549         int required = IB_QP_STATE;
3550         void *dctc;
3551
3552         if (!(attr_mask & IB_QP_STATE))
3553                 return -EINVAL;
3554
3555         cur_state = qp->state;
3556         new_state = attr->qp_state;
3557
3558         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3559         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3560                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3561                 if (!is_valid_mask(attr_mask, required, 0))
3562                         return -EINVAL;
3563
3564                 if (attr->port_num == 0 ||
3565                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3566                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3567                                     attr->port_num, dev->num_ports);
3568                         return -EINVAL;
3569                 }
3570                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3571                         MLX5_SET(dctc, dctc, rre, 1);
3572                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3573                         MLX5_SET(dctc, dctc, rwe, 1);
3574                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3575                         int atomic_mode;
3576
3577                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3578                         if (atomic_mode < 0)
3579                                 return -EOPNOTSUPP;
3580
3581                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3582                         MLX5_SET(dctc, dctc, rae, 1);
3583                 }
3584                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3585                 MLX5_SET(dctc, dctc, port, attr->port_num);
3586                 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3587
3588         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3589                 struct mlx5_ib_modify_qp_resp resp = {};
3590                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3591                                    sizeof(resp.dctn);
3592
3593                 if (udata->outlen < min_resp_len)
3594                         return -EINVAL;
3595                 resp.response_length = min_resp_len;
3596
3597                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3598                 if (!is_valid_mask(attr_mask, required, 0))
3599                         return -EINVAL;
3600                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3601                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3602                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3603                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3604                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3605                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3606
3607                 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3608                                            MLX5_ST_SZ_BYTES(create_dct_in));
3609                 if (err)
3610                         return err;
3611                 resp.dctn = qp->dct.mdct.mqp.qpn;
3612                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3613                 if (err) {
3614                         mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3615                         return err;
3616                 }
3617         } else {
3618                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3619                 return -EINVAL;
3620         }
3621         if (err)
3622                 qp->state = IB_QPS_ERR;
3623         else
3624                 qp->state = new_state;
3625         return err;
3626 }
3627
3628 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3629                       int attr_mask, struct ib_udata *udata)
3630 {
3631         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3632         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3633         struct mlx5_ib_modify_qp ucmd = {};
3634         enum ib_qp_type qp_type;
3635         enum ib_qp_state cur_state, new_state;
3636         size_t required_cmd_sz;
3637         int err = -EINVAL;
3638         int port;
3639
3640         if (ibqp->rwq_ind_tbl)
3641                 return -ENOSYS;
3642
3643         if (udata && udata->inlen) {
3644                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3645                         sizeof(ucmd.reserved);
3646                 if (udata->inlen < required_cmd_sz)
3647                         return -EINVAL;
3648
3649                 if (udata->inlen > sizeof(ucmd) &&
3650                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3651                                          udata->inlen - sizeof(ucmd)))
3652                         return -EOPNOTSUPP;
3653
3654                 if (ib_copy_from_udata(&ucmd, udata,
3655                                        min(udata->inlen, sizeof(ucmd))))
3656                         return -EFAULT;
3657
3658                 if (ucmd.comp_mask ||
3659                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3660                     memchr_inv(&ucmd.burst_info.reserved, 0,
3661                                sizeof(ucmd.burst_info.reserved)))
3662                         return -EOPNOTSUPP;
3663         }
3664
3665         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3666                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3667
3668         if (ibqp->qp_type == IB_QPT_DRIVER)
3669                 qp_type = qp->qp_sub_type;
3670         else
3671                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3672                         IB_QPT_GSI : ibqp->qp_type;
3673
3674         if (qp_type == MLX5_IB_QPT_DCT)
3675                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3676
3677         mutex_lock(&qp->mutex);
3678
3679         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3680         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3681
3682         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3683                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3684         }
3685
3686         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3687                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3688                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3689                                     attr_mask);
3690                         goto out;
3691                 }
3692         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3693                    qp_type != MLX5_IB_QPT_DCI &&
3694                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3695                                        attr_mask)) {
3696                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3697                             cur_state, new_state, ibqp->qp_type, attr_mask);
3698                 goto out;
3699         } else if (qp_type == MLX5_IB_QPT_DCI &&
3700                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3701                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3702                             cur_state, new_state, qp_type, attr_mask);
3703                 goto out;
3704         }
3705
3706         if ((attr_mask & IB_QP_PORT) &&
3707             (attr->port_num == 0 ||
3708              attr->port_num > dev->num_ports)) {
3709                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3710                             attr->port_num, dev->num_ports);
3711                 goto out;
3712         }
3713
3714         if (attr_mask & IB_QP_PKEY_INDEX) {
3715                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3716                 if (attr->pkey_index >=
3717                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3718                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3719                                     attr->pkey_index);
3720                         goto out;
3721                 }
3722         }
3723
3724         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3725             attr->max_rd_atomic >
3726             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3727                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3728                             attr->max_rd_atomic);
3729                 goto out;
3730         }
3731
3732         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3733             attr->max_dest_rd_atomic >
3734             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3735                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3736                             attr->max_dest_rd_atomic);
3737                 goto out;
3738         }
3739
3740         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3741                 err = 0;
3742                 goto out;
3743         }
3744
3745         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3746                                   new_state, &ucmd);
3747
3748 out:
3749         mutex_unlock(&qp->mutex);
3750         return err;
3751 }
3752
3753 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3754 {
3755         struct mlx5_ib_cq *cq;
3756         unsigned cur;
3757
3758         cur = wq->head - wq->tail;
3759         if (likely(cur + nreq < wq->max_post))
3760                 return 0;
3761
3762         cq = to_mcq(ib_cq);
3763         spin_lock(&cq->lock);
3764         cur = wq->head - wq->tail;
3765         spin_unlock(&cq->lock);
3766
3767         return cur + nreq >= wq->max_post;
3768 }
3769
3770 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3771                                           u64 remote_addr, u32 rkey)
3772 {
3773         rseg->raddr    = cpu_to_be64(remote_addr);
3774         rseg->rkey     = cpu_to_be32(rkey);
3775         rseg->reserved = 0;
3776 }
3777
3778 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3779                          const struct ib_send_wr *wr, void *qend,
3780                          struct mlx5_ib_qp *qp, int *size)
3781 {
3782         void *seg = eseg;
3783
3784         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3785
3786         if (wr->send_flags & IB_SEND_IP_CSUM)
3787                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3788                                  MLX5_ETH_WQE_L4_CSUM;
3789
3790         seg += sizeof(struct mlx5_wqe_eth_seg);
3791         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3792
3793         if (wr->opcode == IB_WR_LSO) {
3794                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3795                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3796                 u64 left, leftlen, copysz;
3797                 void *pdata = ud_wr->header;
3798
3799                 left = ud_wr->hlen;
3800                 eseg->mss = cpu_to_be16(ud_wr->mss);
3801                 eseg->inline_hdr.sz = cpu_to_be16(left);
3802
3803                 /*
3804                  * check if there is space till the end of queue, if yes,
3805                  * copy all in one shot, otherwise copy till the end of queue,
3806                  * rollback and than the copy the left
3807                  */
3808                 leftlen = qend - (void *)eseg->inline_hdr.start;
3809                 copysz = min_t(u64, leftlen, left);
3810
3811                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3812
3813                 if (likely(copysz > size_of_inl_hdr_start)) {
3814                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3815                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3816                 }
3817
3818                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3819                         seg = mlx5_get_send_wqe(qp, 0);
3820                         left -= copysz;
3821                         pdata += copysz;
3822                         memcpy(seg, pdata, left);
3823                         seg += ALIGN(left, 16);
3824                         *size += ALIGN(left, 16) / 16;
3825                 }
3826         }
3827
3828         return seg;
3829 }
3830
3831 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3832                              const struct ib_send_wr *wr)
3833 {
3834         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3835         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3836         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3837 }
3838
3839 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3840 {
3841         dseg->byte_count = cpu_to_be32(sg->length);
3842         dseg->lkey       = cpu_to_be32(sg->lkey);
3843         dseg->addr       = cpu_to_be64(sg->addr);
3844 }
3845
3846 static u64 get_xlt_octo(u64 bytes)
3847 {
3848         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3849                MLX5_IB_UMR_OCTOWORD;
3850 }
3851
3852 static __be64 frwr_mkey_mask(void)
3853 {
3854         u64 result;
3855
3856         result = MLX5_MKEY_MASK_LEN             |
3857                 MLX5_MKEY_MASK_PAGE_SIZE        |
3858                 MLX5_MKEY_MASK_START_ADDR       |
3859                 MLX5_MKEY_MASK_EN_RINVAL        |
3860                 MLX5_MKEY_MASK_KEY              |
3861                 MLX5_MKEY_MASK_LR               |
3862                 MLX5_MKEY_MASK_LW               |
3863                 MLX5_MKEY_MASK_RR               |
3864                 MLX5_MKEY_MASK_RW               |
3865                 MLX5_MKEY_MASK_A                |
3866                 MLX5_MKEY_MASK_SMALL_FENCE      |
3867                 MLX5_MKEY_MASK_FREE;
3868
3869         return cpu_to_be64(result);
3870 }
3871
3872 static __be64 sig_mkey_mask(void)
3873 {
3874         u64 result;
3875
3876         result = MLX5_MKEY_MASK_LEN             |
3877                 MLX5_MKEY_MASK_PAGE_SIZE        |
3878                 MLX5_MKEY_MASK_START_ADDR       |
3879                 MLX5_MKEY_MASK_EN_SIGERR        |
3880                 MLX5_MKEY_MASK_EN_RINVAL        |
3881                 MLX5_MKEY_MASK_KEY              |
3882                 MLX5_MKEY_MASK_LR               |
3883                 MLX5_MKEY_MASK_LW               |
3884                 MLX5_MKEY_MASK_RR               |
3885                 MLX5_MKEY_MASK_RW               |
3886                 MLX5_MKEY_MASK_SMALL_FENCE      |
3887                 MLX5_MKEY_MASK_FREE             |
3888                 MLX5_MKEY_MASK_BSF_EN;
3889
3890         return cpu_to_be64(result);
3891 }
3892
3893 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3894                             struct mlx5_ib_mr *mr, bool umr_inline)
3895 {
3896         int size = mr->ndescs * mr->desc_size;
3897
3898         memset(umr, 0, sizeof(*umr));
3899
3900         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3901         if (umr_inline)
3902                 umr->flags |= MLX5_UMR_INLINE;
3903         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3904         umr->mkey_mask = frwr_mkey_mask();
3905 }
3906
3907 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3908 {
3909         memset(umr, 0, sizeof(*umr));
3910         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3911         umr->flags = MLX5_UMR_INLINE;
3912 }
3913
3914 static __be64 get_umr_enable_mr_mask(void)
3915 {
3916         u64 result;
3917
3918         result = MLX5_MKEY_MASK_KEY |
3919                  MLX5_MKEY_MASK_FREE;
3920
3921         return cpu_to_be64(result);
3922 }
3923
3924 static __be64 get_umr_disable_mr_mask(void)
3925 {
3926         u64 result;
3927
3928         result = MLX5_MKEY_MASK_FREE;
3929
3930         return cpu_to_be64(result);
3931 }
3932
3933 static __be64 get_umr_update_translation_mask(void)
3934 {
3935         u64 result;
3936
3937         result = MLX5_MKEY_MASK_LEN |
3938                  MLX5_MKEY_MASK_PAGE_SIZE |
3939                  MLX5_MKEY_MASK_START_ADDR;
3940
3941         return cpu_to_be64(result);
3942 }
3943
3944 static __be64 get_umr_update_access_mask(int atomic)
3945 {
3946         u64 result;
3947
3948         result = MLX5_MKEY_MASK_LR |
3949                  MLX5_MKEY_MASK_LW |
3950                  MLX5_MKEY_MASK_RR |
3951                  MLX5_MKEY_MASK_RW;
3952
3953         if (atomic)
3954                 result |= MLX5_MKEY_MASK_A;
3955
3956         return cpu_to_be64(result);
3957 }
3958
3959 static __be64 get_umr_update_pd_mask(void)
3960 {
3961         u64 result;
3962
3963         result = MLX5_MKEY_MASK_PD;
3964
3965         return cpu_to_be64(result);
3966 }
3967
3968 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3969 {
3970         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3971              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3972             (mask & MLX5_MKEY_MASK_A &&
3973              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3974                 return -EPERM;
3975         return 0;
3976 }
3977
3978 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3979                                struct mlx5_wqe_umr_ctrl_seg *umr,
3980                                const struct ib_send_wr *wr, int atomic)
3981 {
3982         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3983
3984         memset(umr, 0, sizeof(*umr));
3985
3986         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3987                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3988         else
3989                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3990
3991         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3992         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3993                 u64 offset = get_xlt_octo(umrwr->offset);
3994
3995                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3996                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3997                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3998         }
3999         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4000                 umr->mkey_mask |= get_umr_update_translation_mask();
4001         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4002                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4003                 umr->mkey_mask |= get_umr_update_pd_mask();
4004         }
4005         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4006                 umr->mkey_mask |= get_umr_enable_mr_mask();
4007         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4008                 umr->mkey_mask |= get_umr_disable_mr_mask();
4009
4010         if (!wr->num_sge)
4011                 umr->flags |= MLX5_UMR_INLINE;
4012
4013         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4014 }
4015
4016 static u8 get_umr_flags(int acc)
4017 {
4018         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4019                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4020                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4021                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4022                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4023 }
4024
4025 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4026                              struct mlx5_ib_mr *mr,
4027                              u32 key, int access)
4028 {
4029         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
4030
4031         memset(seg, 0, sizeof(*seg));
4032
4033         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4034                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4035         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4036                 /* KLMs take twice the size of MTTs */
4037                 ndescs *= 2;
4038
4039         seg->flags = get_umr_flags(access) | mr->access_mode;
4040         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4041         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4042         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4043         seg->len = cpu_to_be64(mr->ibmr.length);
4044         seg->xlt_oct_size = cpu_to_be32(ndescs);
4045 }
4046
4047 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4048 {
4049         memset(seg, 0, sizeof(*seg));
4050         seg->status = MLX5_MKEY_STATUS_FREE;
4051 }
4052
4053 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4054                                  const struct ib_send_wr *wr)
4055 {
4056         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4057
4058         memset(seg, 0, sizeof(*seg));
4059         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4060                 seg->status = MLX5_MKEY_STATUS_FREE;
4061
4062         seg->flags = convert_access(umrwr->access_flags);
4063         if (umrwr->pd)
4064                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4065         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4066             !umrwr->length)
4067                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4068
4069         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4070         seg->len = cpu_to_be64(umrwr->length);
4071         seg->log2_page_size = umrwr->page_shift;
4072         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4073                                        mlx5_mkey_variant(umrwr->mkey));
4074 }
4075
4076 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4077                              struct mlx5_ib_mr *mr,
4078                              struct mlx5_ib_pd *pd)
4079 {
4080         int bcount = mr->desc_size * mr->ndescs;
4081
4082         dseg->addr = cpu_to_be64(mr->desc_map);
4083         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4084         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4085 }
4086
4087 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
4088                                    struct mlx5_ib_mr *mr, int mr_list_size)
4089 {
4090         void *qend = qp->sq.qend;
4091         void *addr = mr->descs;
4092         int copy;
4093
4094         if (unlikely(seg + mr_list_size > qend)) {
4095                 copy = qend - seg;
4096                 memcpy(seg, addr, copy);
4097                 addr += copy;
4098                 mr_list_size -= copy;
4099                 seg = mlx5_get_send_wqe(qp, 0);
4100         }
4101         memcpy(seg, addr, mr_list_size);
4102         seg += mr_list_size;
4103 }
4104
4105 static __be32 send_ieth(const struct ib_send_wr *wr)
4106 {
4107         switch (wr->opcode) {
4108         case IB_WR_SEND_WITH_IMM:
4109         case IB_WR_RDMA_WRITE_WITH_IMM:
4110                 return wr->ex.imm_data;
4111
4112         case IB_WR_SEND_WITH_INV:
4113                 return cpu_to_be32(wr->ex.invalidate_rkey);
4114
4115         default:
4116                 return 0;
4117         }
4118 }
4119
4120 static u8 calc_sig(void *wqe, int size)
4121 {
4122         u8 *p = wqe;
4123         u8 res = 0;
4124         int i;
4125
4126         for (i = 0; i < size; i++)
4127                 res ^= p[i];
4128
4129         return ~res;
4130 }
4131
4132 static u8 wq_sig(void *wqe)
4133 {
4134         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4135 }
4136
4137 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4138                             void *wqe, int *sz)
4139 {
4140         struct mlx5_wqe_inline_seg *seg;
4141         void *qend = qp->sq.qend;
4142         void *addr;
4143         int inl = 0;
4144         int copy;
4145         int len;
4146         int i;
4147
4148         seg = wqe;
4149         wqe += sizeof(*seg);
4150         for (i = 0; i < wr->num_sge; i++) {
4151                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4152                 len  = wr->sg_list[i].length;
4153                 inl += len;
4154
4155                 if (unlikely(inl > qp->max_inline_data))
4156                         return -ENOMEM;
4157
4158                 if (unlikely(wqe + len > qend)) {
4159                         copy = qend - wqe;
4160                         memcpy(wqe, addr, copy);
4161                         addr += copy;
4162                         len -= copy;
4163                         wqe = mlx5_get_send_wqe(qp, 0);
4164                 }
4165                 memcpy(wqe, addr, len);
4166                 wqe += len;
4167         }
4168
4169         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4170
4171         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4172
4173         return 0;
4174 }
4175
4176 static u16 prot_field_size(enum ib_signature_type type)
4177 {
4178         switch (type) {
4179         case IB_SIG_TYPE_T10_DIF:
4180                 return MLX5_DIF_SIZE;
4181         default:
4182                 return 0;
4183         }
4184 }
4185
4186 static u8 bs_selector(int block_size)
4187 {
4188         switch (block_size) {
4189         case 512:           return 0x1;
4190         case 520:           return 0x2;
4191         case 4096:          return 0x3;
4192         case 4160:          return 0x4;
4193         case 1073741824:    return 0x5;
4194         default:            return 0;
4195         }
4196 }
4197
4198 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4199                               struct mlx5_bsf_inl *inl)
4200 {
4201         /* Valid inline section and allow BSF refresh */
4202         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4203                                        MLX5_BSF_REFRESH_DIF);
4204         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4205         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4206         /* repeating block */
4207         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4208         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4209                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4210
4211         if (domain->sig.dif.ref_remap)
4212                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4213
4214         if (domain->sig.dif.app_escape) {
4215                 if (domain->sig.dif.ref_escape)
4216                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4217                 else
4218                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4219         }
4220
4221         inl->dif_app_bitmask_check =
4222                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4223 }
4224
4225 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4226                         struct ib_sig_attrs *sig_attrs,
4227                         struct mlx5_bsf *bsf, u32 data_size)
4228 {
4229         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4230         struct mlx5_bsf_basic *basic = &bsf->basic;
4231         struct ib_sig_domain *mem = &sig_attrs->mem;
4232         struct ib_sig_domain *wire = &sig_attrs->wire;
4233
4234         memset(bsf, 0, sizeof(*bsf));
4235
4236         /* Basic + Extended + Inline */
4237         basic->bsf_size_sbs = 1 << 7;
4238         /* Input domain check byte mask */
4239         basic->check_byte_mask = sig_attrs->check_mask;
4240         basic->raw_data_size = cpu_to_be32(data_size);
4241
4242         /* Memory domain */
4243         switch (sig_attrs->mem.sig_type) {
4244         case IB_SIG_TYPE_NONE:
4245                 break;
4246         case IB_SIG_TYPE_T10_DIF:
4247                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4248                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4249                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4250                 break;
4251         default:
4252                 return -EINVAL;
4253         }
4254
4255         /* Wire domain */
4256         switch (sig_attrs->wire.sig_type) {
4257         case IB_SIG_TYPE_NONE:
4258                 break;
4259         case IB_SIG_TYPE_T10_DIF:
4260                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4261                     mem->sig_type == wire->sig_type) {
4262                         /* Same block structure */
4263                         basic->bsf_size_sbs |= 1 << 4;
4264                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4265                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4266                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4267                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4268                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4269                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4270                 } else
4271                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4272
4273                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4274                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4275                 break;
4276         default:
4277                 return -EINVAL;
4278         }
4279
4280         return 0;
4281 }
4282
4283 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4284                                 struct mlx5_ib_qp *qp, void **seg, int *size)
4285 {
4286         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4287         struct ib_mr *sig_mr = wr->sig_mr;
4288         struct mlx5_bsf *bsf;
4289         u32 data_len = wr->wr.sg_list->length;
4290         u32 data_key = wr->wr.sg_list->lkey;
4291         u64 data_va = wr->wr.sg_list->addr;
4292         int ret;
4293         int wqe_size;
4294
4295         if (!wr->prot ||
4296             (data_key == wr->prot->lkey &&
4297              data_va == wr->prot->addr &&
4298              data_len == wr->prot->length)) {
4299                 /**
4300                  * Source domain doesn't contain signature information
4301                  * or data and protection are interleaved in memory.
4302                  * So need construct:
4303                  *                  ------------------
4304                  *                 |     data_klm     |
4305                  *                  ------------------
4306                  *                 |       BSF        |
4307                  *                  ------------------
4308                  **/
4309                 struct mlx5_klm *data_klm = *seg;
4310
4311                 data_klm->bcount = cpu_to_be32(data_len);
4312                 data_klm->key = cpu_to_be32(data_key);
4313                 data_klm->va = cpu_to_be64(data_va);
4314                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4315         } else {
4316                 /**
4317                  * Source domain contains signature information
4318                  * So need construct a strided block format:
4319                  *               ---------------------------
4320                  *              |     stride_block_ctrl     |
4321                  *               ---------------------------
4322                  *              |          data_klm         |
4323                  *               ---------------------------
4324                  *              |          prot_klm         |
4325                  *               ---------------------------
4326                  *              |             BSF           |
4327                  *               ---------------------------
4328                  **/
4329                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4330                 struct mlx5_stride_block_entry *data_sentry;
4331                 struct mlx5_stride_block_entry *prot_sentry;
4332                 u32 prot_key = wr->prot->lkey;
4333                 u64 prot_va = wr->prot->addr;
4334                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4335                 int prot_size;
4336
4337                 sblock_ctrl = *seg;
4338                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4339                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4340
4341                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4342                 if (!prot_size) {
4343                         pr_err("Bad block size given: %u\n", block_size);
4344                         return -EINVAL;
4345                 }
4346                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4347                                                             prot_size);
4348                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4349                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4350                 sblock_ctrl->num_entries = cpu_to_be16(2);
4351
4352                 data_sentry->bcount = cpu_to_be16(block_size);
4353                 data_sentry->key = cpu_to_be32(data_key);
4354                 data_sentry->va = cpu_to_be64(data_va);
4355                 data_sentry->stride = cpu_to_be16(block_size);
4356
4357                 prot_sentry->bcount = cpu_to_be16(prot_size);
4358                 prot_sentry->key = cpu_to_be32(prot_key);
4359                 prot_sentry->va = cpu_to_be64(prot_va);
4360                 prot_sentry->stride = cpu_to_be16(prot_size);
4361
4362                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4363                                  sizeof(*prot_sentry), 64);
4364         }
4365
4366         *seg += wqe_size;
4367         *size += wqe_size / 16;
4368         if (unlikely((*seg == qp->sq.qend)))
4369                 *seg = mlx5_get_send_wqe(qp, 0);
4370
4371         bsf = *seg;
4372         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4373         if (ret)
4374                 return -EINVAL;
4375
4376         *seg += sizeof(*bsf);
4377         *size += sizeof(*bsf) / 16;
4378         if (unlikely((*seg == qp->sq.qend)))
4379                 *seg = mlx5_get_send_wqe(qp, 0);
4380
4381         return 0;
4382 }
4383
4384 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4385                                  const struct ib_sig_handover_wr *wr, u32 size,
4386                                  u32 length, u32 pdn)
4387 {
4388         struct ib_mr *sig_mr = wr->sig_mr;
4389         u32 sig_key = sig_mr->rkey;
4390         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4391
4392         memset(seg, 0, sizeof(*seg));
4393
4394         seg->flags = get_umr_flags(wr->access_flags) |
4395                                    MLX5_MKC_ACCESS_MODE_KLMS;
4396         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4397         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4398                                     MLX5_MKEY_BSF_EN | pdn);
4399         seg->len = cpu_to_be64(length);
4400         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4401         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4402 }
4403
4404 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4405                                 u32 size)
4406 {
4407         memset(umr, 0, sizeof(*umr));
4408
4409         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4410         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4411         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4412         umr->mkey_mask = sig_mkey_mask();
4413 }
4414
4415
4416 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4417                           struct mlx5_ib_qp *qp, void **seg, int *size)
4418 {
4419         const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4420         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4421         u32 pdn = get_pd(qp)->pdn;
4422         u32 xlt_size;
4423         int region_len, ret;
4424
4425         if (unlikely(wr->wr.num_sge != 1) ||
4426             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4427             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4428             unlikely(!sig_mr->sig->sig_status_checked))
4429                 return -EINVAL;
4430
4431         /* length of the protected region, data + protection */
4432         region_len = wr->wr.sg_list->length;
4433         if (wr->prot &&
4434             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
4435              wr->prot->addr != wr->wr.sg_list->addr  ||
4436              wr->prot->length != wr->wr.sg_list->length))
4437                 region_len += wr->prot->length;
4438
4439         /**
4440          * KLM octoword size - if protection was provided
4441          * then we use strided block format (3 octowords),
4442          * else we use single KLM (1 octoword)
4443          **/
4444         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4445
4446         set_sig_umr_segment(*seg, xlt_size);
4447         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4448         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4449         if (unlikely((*seg == qp->sq.qend)))
4450                 *seg = mlx5_get_send_wqe(qp, 0);
4451
4452         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4453         *seg += sizeof(struct mlx5_mkey_seg);
4454         *size += sizeof(struct mlx5_mkey_seg) / 16;
4455         if (unlikely((*seg == qp->sq.qend)))
4456                 *seg = mlx5_get_send_wqe(qp, 0);
4457
4458         ret = set_sig_data_segment(wr, qp, seg, size);
4459         if (ret)
4460                 return ret;
4461
4462         sig_mr->sig->sig_status_checked = false;
4463         return 0;
4464 }
4465
4466 static int set_psv_wr(struct ib_sig_domain *domain,
4467                       u32 psv_idx, void **seg, int *size)
4468 {
4469         struct mlx5_seg_set_psv *psv_seg = *seg;
4470
4471         memset(psv_seg, 0, sizeof(*psv_seg));
4472         psv_seg->psv_num = cpu_to_be32(psv_idx);
4473         switch (domain->sig_type) {
4474         case IB_SIG_TYPE_NONE:
4475                 break;
4476         case IB_SIG_TYPE_T10_DIF:
4477                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4478                                                      domain->sig.dif.app_tag);
4479                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4480                 break;
4481         default:
4482                 pr_err("Bad signature type (%d) is given.\n",
4483                        domain->sig_type);
4484                 return -EINVAL;
4485         }
4486
4487         *seg += sizeof(*psv_seg);
4488         *size += sizeof(*psv_seg) / 16;
4489
4490         return 0;
4491 }
4492
4493 static int set_reg_wr(struct mlx5_ib_qp *qp,
4494                       const struct ib_reg_wr *wr,
4495                       void **seg, int *size)
4496 {
4497         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4498         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4499         int mr_list_size = mr->ndescs * mr->desc_size;
4500         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4501
4502         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4503                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4504                              "Invalid IB_SEND_INLINE send flag\n");
4505                 return -EINVAL;
4506         }
4507
4508         set_reg_umr_seg(*seg, mr, umr_inline);
4509         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4510         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4511         if (unlikely((*seg == qp->sq.qend)))
4512                 *seg = mlx5_get_send_wqe(qp, 0);
4513
4514         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4515         *seg += sizeof(struct mlx5_mkey_seg);
4516         *size += sizeof(struct mlx5_mkey_seg) / 16;
4517         if (unlikely((*seg == qp->sq.qend)))
4518                 *seg = mlx5_get_send_wqe(qp, 0);
4519
4520         if (umr_inline) {
4521                 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4522                 *size += get_xlt_octo(mr_list_size);
4523         } else {
4524                 set_reg_data_seg(*seg, mr, pd);
4525                 *seg += sizeof(struct mlx5_wqe_data_seg);
4526                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4527         }
4528         return 0;
4529 }
4530
4531 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4532 {
4533         set_linv_umr_seg(*seg);
4534         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4535         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4536         if (unlikely((*seg == qp->sq.qend)))
4537                 *seg = mlx5_get_send_wqe(qp, 0);
4538         set_linv_mkey_seg(*seg);
4539         *seg += sizeof(struct mlx5_mkey_seg);
4540         *size += sizeof(struct mlx5_mkey_seg) / 16;
4541         if (unlikely((*seg == qp->sq.qend)))
4542                 *seg = mlx5_get_send_wqe(qp, 0);
4543 }
4544
4545 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4546 {
4547         __be32 *p = NULL;
4548         int tidx = idx;
4549         int i, j;
4550
4551         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4552         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4553                 if ((i & 0xf) == 0) {
4554                         void *buf = mlx5_get_send_wqe(qp, tidx);
4555                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4556                         p = buf;
4557                         j = 0;
4558                 }
4559                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4560                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4561                          be32_to_cpu(p[j + 3]));
4562         }
4563 }
4564
4565 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4566                      struct mlx5_wqe_ctrl_seg **ctrl,
4567                      const struct ib_send_wr *wr, unsigned *idx,
4568                      int *size, int nreq, bool send_signaled, bool solicited)
4569 {
4570         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4571                 return -ENOMEM;
4572
4573         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4574         *seg = mlx5_get_send_wqe(qp, *idx);
4575         *ctrl = *seg;
4576         *(uint32_t *)(*seg + 8) = 0;
4577         (*ctrl)->imm = send_ieth(wr);
4578         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4579                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4580                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4581
4582         *seg += sizeof(**ctrl);
4583         *size = sizeof(**ctrl) / 16;
4584
4585         return 0;
4586 }
4587
4588 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4589                      struct mlx5_wqe_ctrl_seg **ctrl,
4590                      const struct ib_send_wr *wr, unsigned *idx,
4591                      int *size, int nreq)
4592 {
4593         return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq,
4594                            wr->send_flags & IB_SEND_SIGNALED,
4595                            wr->send_flags & IB_SEND_SOLICITED);
4596 }
4597
4598 static void finish_wqe(struct mlx5_ib_qp *qp,
4599                        struct mlx5_wqe_ctrl_seg *ctrl,
4600                        u8 size, unsigned idx, u64 wr_id,
4601                        int nreq, u8 fence, u32 mlx5_opcode)
4602 {
4603         u8 opmod = 0;
4604
4605         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4606                                              mlx5_opcode | ((u32)opmod << 24));
4607         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4608         ctrl->fm_ce_se |= fence;
4609         if (unlikely(qp->wq_sig))
4610                 ctrl->signature = wq_sig(ctrl);
4611
4612         qp->sq.wrid[idx] = wr_id;
4613         qp->sq.w_list[idx].opcode = mlx5_opcode;
4614         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4615         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4616         qp->sq.w_list[idx].next = qp->sq.cur_post;
4617 }
4618
4619 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4620                               const struct ib_send_wr **bad_wr, bool drain)
4621 {
4622         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
4623         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4624         struct mlx5_core_dev *mdev = dev->mdev;
4625         struct mlx5_ib_qp *qp;
4626         struct mlx5_ib_mr *mr;
4627         struct mlx5_wqe_data_seg *dpseg;
4628         struct mlx5_wqe_xrc_seg *xrc;
4629         struct mlx5_bf *bf;
4630         int uninitialized_var(size);
4631         void *qend;
4632         unsigned long flags;
4633         unsigned idx;
4634         int err = 0;
4635         int num_sge;
4636         void *seg;
4637         int nreq;
4638         int i;
4639         u8 next_fence = 0;
4640         u8 fence;
4641
4642         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4643                      !drain)) {
4644                 *bad_wr = wr;
4645                 return -EIO;
4646         }
4647
4648         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4649                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4650
4651         qp = to_mqp(ibqp);
4652         bf = &qp->bf;
4653         qend = qp->sq.qend;
4654
4655         spin_lock_irqsave(&qp->sq.lock, flags);
4656
4657         for (nreq = 0; wr; nreq++, wr = wr->next) {
4658                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4659                         mlx5_ib_warn(dev, "\n");
4660                         err = -EINVAL;
4661                         *bad_wr = wr;
4662                         goto out;
4663                 }
4664
4665                 num_sge = wr->num_sge;
4666                 if (unlikely(num_sge > qp->sq.max_gs)) {
4667                         mlx5_ib_warn(dev, "\n");
4668                         err = -EINVAL;
4669                         *bad_wr = wr;
4670                         goto out;
4671                 }
4672
4673                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4674                 if (err) {
4675                         mlx5_ib_warn(dev, "\n");
4676                         err = -ENOMEM;
4677                         *bad_wr = wr;
4678                         goto out;
4679                 }
4680
4681                 if (wr->opcode == IB_WR_LOCAL_INV ||
4682                     wr->opcode == IB_WR_REG_MR) {
4683                         fence = dev->umr_fence;
4684                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4685                 } else if (wr->send_flags & IB_SEND_FENCE) {
4686                         if (qp->next_fence)
4687                                 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4688                         else
4689                                 fence = MLX5_FENCE_MODE_FENCE;
4690                 } else {
4691                         fence = qp->next_fence;
4692                 }
4693
4694                 switch (ibqp->qp_type) {
4695                 case IB_QPT_XRC_INI:
4696                         xrc = seg;
4697                         seg += sizeof(*xrc);
4698                         size += sizeof(*xrc) / 16;
4699                         /* fall through */
4700                 case IB_QPT_RC:
4701                         switch (wr->opcode) {
4702                         case IB_WR_RDMA_READ:
4703                         case IB_WR_RDMA_WRITE:
4704                         case IB_WR_RDMA_WRITE_WITH_IMM:
4705                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4706                                               rdma_wr(wr)->rkey);
4707                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
4708                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4709                                 break;
4710
4711                         case IB_WR_ATOMIC_CMP_AND_SWP:
4712                         case IB_WR_ATOMIC_FETCH_AND_ADD:
4713                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4714                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4715                                 err = -ENOSYS;
4716                                 *bad_wr = wr;
4717                                 goto out;
4718
4719                         case IB_WR_LOCAL_INV:
4720                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4721                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4722                                 set_linv_wr(qp, &seg, &size);
4723                                 num_sge = 0;
4724                                 break;
4725
4726                         case IB_WR_REG_MR:
4727                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4728                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4729                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4730                                 if (err) {
4731                                         *bad_wr = wr;
4732                                         goto out;
4733                                 }
4734                                 num_sge = 0;
4735                                 break;
4736
4737                         case IB_WR_REG_SIG_MR:
4738                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4739                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4740
4741                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4742                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
4743                                 if (err) {
4744                                         mlx5_ib_warn(dev, "\n");
4745                                         *bad_wr = wr;
4746                                         goto out;
4747                                 }
4748
4749                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4750                                            fence, MLX5_OPCODE_UMR);
4751                                 /*
4752                                  * SET_PSV WQEs are not signaled and solicited
4753                                  * on error
4754                                  */
4755                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4756                                                   &size, nreq, false, true);
4757                                 if (err) {
4758                                         mlx5_ib_warn(dev, "\n");
4759                                         err = -ENOMEM;
4760                                         *bad_wr = wr;
4761                                         goto out;
4762                                 }
4763
4764                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4765                                                  mr->sig->psv_memory.psv_idx, &seg,
4766                                                  &size);
4767                                 if (err) {
4768                                         mlx5_ib_warn(dev, "\n");
4769                                         *bad_wr = wr;
4770                                         goto out;
4771                                 }
4772
4773                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4774                                            fence, MLX5_OPCODE_SET_PSV);
4775                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4776                                                   &size, nreq, false, true);
4777                                 if (err) {
4778                                         mlx5_ib_warn(dev, "\n");
4779                                         err = -ENOMEM;
4780                                         *bad_wr = wr;
4781                                         goto out;
4782                                 }
4783
4784                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4785                                                  mr->sig->psv_wire.psv_idx, &seg,
4786                                                  &size);
4787                                 if (err) {
4788                                         mlx5_ib_warn(dev, "\n");
4789                                         *bad_wr = wr;
4790                                         goto out;
4791                                 }
4792
4793                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4794                                            fence, MLX5_OPCODE_SET_PSV);
4795                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4796                                 num_sge = 0;
4797                                 goto skip_psv;
4798
4799                         default:
4800                                 break;
4801                         }
4802                         break;
4803
4804                 case IB_QPT_UC:
4805                         switch (wr->opcode) {
4806                         case IB_WR_RDMA_WRITE:
4807                         case IB_WR_RDMA_WRITE_WITH_IMM:
4808                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4809                                               rdma_wr(wr)->rkey);
4810                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
4811                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4812                                 break;
4813
4814                         default:
4815                                 break;
4816                         }
4817                         break;
4818
4819                 case IB_QPT_SMI:
4820                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4821                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4822                                 err = -EPERM;
4823                                 *bad_wr = wr;
4824                                 goto out;
4825                         }
4826                         /* fall through */
4827                 case MLX5_IB_QPT_HW_GSI:
4828                         set_datagram_seg(seg, wr);
4829                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4830                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4831                         if (unlikely((seg == qend)))
4832                                 seg = mlx5_get_send_wqe(qp, 0);
4833                         break;
4834                 case IB_QPT_UD:
4835                         set_datagram_seg(seg, wr);
4836                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4837                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4838
4839                         if (unlikely((seg == qend)))
4840                                 seg = mlx5_get_send_wqe(qp, 0);
4841
4842                         /* handle qp that supports ud offload */
4843                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4844                                 struct mlx5_wqe_eth_pad *pad;
4845
4846                                 pad = seg;
4847                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4848                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4849                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4850
4851                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4852
4853                                 if (unlikely((seg == qend)))
4854                                         seg = mlx5_get_send_wqe(qp, 0);
4855                         }
4856                         break;
4857                 case MLX5_IB_QPT_REG_UMR:
4858                         if (wr->opcode != MLX5_IB_WR_UMR) {
4859                                 err = -EINVAL;
4860                                 mlx5_ib_warn(dev, "bad opcode\n");
4861                                 goto out;
4862                         }
4863                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4864                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4865                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4866                         if (unlikely(err))
4867                                 goto out;
4868                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4869                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4870                         if (unlikely((seg == qend)))
4871                                 seg = mlx5_get_send_wqe(qp, 0);
4872                         set_reg_mkey_segment(seg, wr);
4873                         seg += sizeof(struct mlx5_mkey_seg);
4874                         size += sizeof(struct mlx5_mkey_seg) / 16;
4875                         if (unlikely((seg == qend)))
4876                                 seg = mlx5_get_send_wqe(qp, 0);
4877                         break;
4878
4879                 default:
4880                         break;
4881                 }
4882
4883                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4884                         int uninitialized_var(sz);
4885
4886                         err = set_data_inl_seg(qp, wr, seg, &sz);
4887                         if (unlikely(err)) {
4888                                 mlx5_ib_warn(dev, "\n");
4889                                 *bad_wr = wr;
4890                                 goto out;
4891                         }
4892                         size += sz;
4893                 } else {
4894                         dpseg = seg;
4895                         for (i = 0; i < num_sge; i++) {
4896                                 if (unlikely(dpseg == qend)) {
4897                                         seg = mlx5_get_send_wqe(qp, 0);
4898                                         dpseg = seg;
4899                                 }
4900                                 if (likely(wr->sg_list[i].length)) {
4901                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4902                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4903                                         dpseg++;
4904                                 }
4905                         }
4906                 }
4907
4908                 qp->next_fence = next_fence;
4909                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4910                            mlx5_ib_opcode[wr->opcode]);
4911 skip_psv:
4912                 if (0)
4913                         dump_wqe(qp, idx, size);
4914         }
4915
4916 out:
4917         if (likely(nreq)) {
4918                 qp->sq.head += nreq;
4919
4920                 /* Make sure that descriptors are written before
4921                  * updating doorbell record and ringing the doorbell
4922                  */
4923                 wmb();
4924
4925                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4926
4927                 /* Make sure doorbell record is visible to the HCA before
4928                  * we hit doorbell */
4929                 wmb();
4930
4931                 /* currently we support only regular doorbells */
4932                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4933                 /* Make sure doorbells don't leak out of SQ spinlock
4934                  * and reach the HCA out of order.
4935                  */
4936                 mmiowb();
4937                 bf->offset ^= bf->buf_size;
4938         }
4939
4940         spin_unlock_irqrestore(&qp->sq.lock, flags);
4941
4942         return err;
4943 }
4944
4945 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4946                       const struct ib_send_wr **bad_wr)
4947 {
4948         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
4949 }
4950
4951 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4952 {
4953         sig->signature = calc_sig(sig, size);
4954 }
4955
4956 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4957                       const struct ib_recv_wr **bad_wr, bool drain)
4958 {
4959         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4960         struct mlx5_wqe_data_seg *scat;
4961         struct mlx5_rwqe_sig *sig;
4962         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4963         struct mlx5_core_dev *mdev = dev->mdev;
4964         unsigned long flags;
4965         int err = 0;
4966         int nreq;
4967         int ind;
4968         int i;
4969
4970         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4971                      !drain)) {
4972                 *bad_wr = wr;
4973                 return -EIO;
4974         }
4975
4976         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4977                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4978
4979         spin_lock_irqsave(&qp->rq.lock, flags);
4980
4981         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4982
4983         for (nreq = 0; wr; nreq++, wr = wr->next) {
4984                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4985                         err = -ENOMEM;
4986                         *bad_wr = wr;
4987                         goto out;
4988                 }
4989
4990                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4991                         err = -EINVAL;
4992                         *bad_wr = wr;
4993                         goto out;
4994                 }
4995
4996                 scat = get_recv_wqe(qp, ind);
4997                 if (qp->wq_sig)
4998                         scat++;
4999
5000                 for (i = 0; i < wr->num_sge; i++)
5001                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5002
5003                 if (i < qp->rq.max_gs) {
5004                         scat[i].byte_count = 0;
5005                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5006                         scat[i].addr       = 0;
5007                 }
5008
5009                 if (qp->wq_sig) {
5010                         sig = (struct mlx5_rwqe_sig *)scat;
5011                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5012                 }
5013
5014                 qp->rq.wrid[ind] = wr->wr_id;
5015
5016                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5017         }
5018
5019 out:
5020         if (likely(nreq)) {
5021                 qp->rq.head += nreq;
5022
5023                 /* Make sure that descriptors are written before
5024                  * doorbell record.
5025                  */
5026                 wmb();
5027
5028                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5029         }
5030
5031         spin_unlock_irqrestore(&qp->rq.lock, flags);
5032
5033         return err;
5034 }
5035
5036 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5037                       const struct ib_recv_wr **bad_wr)
5038 {
5039         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5040 }
5041
5042 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5043 {
5044         switch (mlx5_state) {
5045         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5046         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5047         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5048         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5049         case MLX5_QP_STATE_SQ_DRAINING:
5050         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5051         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5052         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5053         default:                     return -1;
5054         }
5055 }
5056
5057 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5058 {
5059         switch (mlx5_mig_state) {
5060         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5061         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5062         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5063         default: return -1;
5064         }
5065 }
5066
5067 static int to_ib_qp_access_flags(int mlx5_flags)
5068 {
5069         int ib_flags = 0;
5070
5071         if (mlx5_flags & MLX5_QP_BIT_RRE)
5072                 ib_flags |= IB_ACCESS_REMOTE_READ;
5073         if (mlx5_flags & MLX5_QP_BIT_RWE)
5074                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5075         if (mlx5_flags & MLX5_QP_BIT_RAE)
5076                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5077
5078         return ib_flags;
5079 }
5080
5081 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5082                             struct rdma_ah_attr *ah_attr,
5083                             struct mlx5_qp_path *path)
5084 {
5085
5086         memset(ah_attr, 0, sizeof(*ah_attr));
5087
5088         if (!path->port || path->port > ibdev->num_ports)
5089                 return;
5090
5091         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5092
5093         rdma_ah_set_port_num(ah_attr, path->port);
5094         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5095
5096         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5097         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5098         rdma_ah_set_static_rate(ah_attr,
5099                                 path->static_rate ? path->static_rate - 5 : 0);
5100         if (path->grh_mlid & (1 << 7)) {
5101                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5102
5103                 rdma_ah_set_grh(ah_attr, NULL,
5104                                 tc_fl & 0xfffff,
5105                                 path->mgid_index,
5106                                 path->hop_limit,
5107                                 (tc_fl >> 20) & 0xff);
5108                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5109         }
5110 }
5111
5112 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5113                                         struct mlx5_ib_sq *sq,
5114                                         u8 *sq_state)
5115 {
5116         int err;
5117
5118         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5119         if (err)
5120                 goto out;
5121         sq->state = *sq_state;
5122
5123 out:
5124         return err;
5125 }
5126
5127 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5128                                         struct mlx5_ib_rq *rq,
5129                                         u8 *rq_state)
5130 {
5131         void *out;
5132         void *rqc;
5133         int inlen;
5134         int err;
5135
5136         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5137         out = kvzalloc(inlen, GFP_KERNEL);
5138         if (!out)
5139                 return -ENOMEM;
5140
5141         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5142         if (err)
5143                 goto out;
5144
5145         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5146         *rq_state = MLX5_GET(rqc, rqc, state);
5147         rq->state = *rq_state;
5148
5149 out:
5150         kvfree(out);
5151         return err;
5152 }
5153
5154 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5155                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5156 {
5157         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5158                 [MLX5_RQC_STATE_RST] = {
5159                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5160                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5161                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5162                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5163                 },
5164                 [MLX5_RQC_STATE_RDY] = {
5165                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5166                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5167                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5168                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5169                 },
5170                 [MLX5_RQC_STATE_ERR] = {
5171                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5172                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5173                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5174                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5175                 },
5176                 [MLX5_RQ_STATE_NA] = {
5177                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5178                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5179                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5180                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5181                 },
5182         };
5183
5184         *qp_state = sqrq_trans[rq_state][sq_state];
5185
5186         if (*qp_state == MLX5_QP_STATE_BAD) {
5187                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5188                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5189                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5190                 return -EINVAL;
5191         }
5192
5193         if (*qp_state == MLX5_QP_STATE)
5194                 *qp_state = qp->state;
5195
5196         return 0;
5197 }
5198
5199 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5200                                      struct mlx5_ib_qp *qp,
5201                                      u8 *raw_packet_qp_state)
5202 {
5203         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5204         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5205         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5206         int err;
5207         u8 sq_state = MLX5_SQ_STATE_NA;
5208         u8 rq_state = MLX5_RQ_STATE_NA;
5209
5210         if (qp->sq.wqe_cnt) {
5211                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5212                 if (err)
5213                         return err;
5214         }
5215
5216         if (qp->rq.wqe_cnt) {
5217                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5218                 if (err)
5219                         return err;
5220         }
5221
5222         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5223                                       raw_packet_qp_state);
5224 }
5225
5226 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5227                          struct ib_qp_attr *qp_attr)
5228 {
5229         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5230         struct mlx5_qp_context *context;
5231         int mlx5_state;
5232         u32 *outb;
5233         int err = 0;
5234
5235         outb = kzalloc(outlen, GFP_KERNEL);
5236         if (!outb)
5237                 return -ENOMEM;
5238
5239         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5240                                  outlen);
5241         if (err)
5242                 goto out;
5243
5244         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5245         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5246
5247         mlx5_state = be32_to_cpu(context->flags) >> 28;
5248
5249         qp->state                    = to_ib_qp_state(mlx5_state);
5250         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5251         qp_attr->path_mig_state      =
5252                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5253         qp_attr->qkey                = be32_to_cpu(context->qkey);
5254         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5255         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5256         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5257         qp_attr->qp_access_flags     =
5258                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5259
5260         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5261                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5262                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5263                 qp_attr->alt_pkey_index =
5264                         be16_to_cpu(context->alt_path.pkey_index);
5265                 qp_attr->alt_port_num   =
5266                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5267         }
5268
5269         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5270         qp_attr->port_num = context->pri_path.port;
5271
5272         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5273         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5274
5275         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5276
5277         qp_attr->max_dest_rd_atomic =
5278                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5279         qp_attr->min_rnr_timer      =
5280                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5281         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5282         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5283         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5284         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5285
5286 out:
5287         kfree(outb);
5288         return err;
5289 }
5290
5291 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5292                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5293                                 struct ib_qp_init_attr *qp_init_attr)
5294 {
5295         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5296         u32 *out;
5297         u32 access_flags = 0;
5298         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5299         void *dctc;
5300         int err;
5301         int supported_mask = IB_QP_STATE |
5302                              IB_QP_ACCESS_FLAGS |
5303                              IB_QP_PORT |
5304                              IB_QP_MIN_RNR_TIMER |
5305                              IB_QP_AV |
5306                              IB_QP_PATH_MTU |
5307                              IB_QP_PKEY_INDEX;
5308
5309         if (qp_attr_mask & ~supported_mask)
5310                 return -EINVAL;
5311         if (mqp->state != IB_QPS_RTR)
5312                 return -EINVAL;
5313
5314         out = kzalloc(outlen, GFP_KERNEL);
5315         if (!out)
5316                 return -ENOMEM;
5317
5318         err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5319         if (err)
5320                 goto out;
5321
5322         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5323
5324         if (qp_attr_mask & IB_QP_STATE)
5325                 qp_attr->qp_state = IB_QPS_RTR;
5326
5327         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5328                 if (MLX5_GET(dctc, dctc, rre))
5329                         access_flags |= IB_ACCESS_REMOTE_READ;
5330                 if (MLX5_GET(dctc, dctc, rwe))
5331                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5332                 if (MLX5_GET(dctc, dctc, rae))
5333                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5334                 qp_attr->qp_access_flags = access_flags;
5335         }
5336
5337         if (qp_attr_mask & IB_QP_PORT)
5338                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5339         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5340                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5341         if (qp_attr_mask & IB_QP_AV) {
5342                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5343                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5344                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5345                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5346         }
5347         if (qp_attr_mask & IB_QP_PATH_MTU)
5348                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5349         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5350                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5351 out:
5352         kfree(out);
5353         return err;
5354 }
5355
5356 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5357                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5358 {
5359         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5360         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5361         int err = 0;
5362         u8 raw_packet_qp_state;
5363
5364         if (ibqp->rwq_ind_tbl)
5365                 return -ENOSYS;
5366
5367         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5368                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5369                                             qp_init_attr);
5370
5371         /* Not all of output fields are applicable, make sure to zero them */
5372         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5373         memset(qp_attr, 0, sizeof(*qp_attr));
5374
5375         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5376                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5377                                             qp_attr_mask, qp_init_attr);
5378
5379         mutex_lock(&qp->mutex);
5380
5381         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5382             qp->flags & MLX5_IB_QP_UNDERLAY) {
5383                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5384                 if (err)
5385                         goto out;
5386                 qp->state = raw_packet_qp_state;
5387                 qp_attr->port_num = 1;
5388         } else {
5389                 err = query_qp_attr(dev, qp, qp_attr);
5390                 if (err)
5391                         goto out;
5392         }
5393
5394         qp_attr->qp_state            = qp->state;
5395         qp_attr->cur_qp_state        = qp_attr->qp_state;
5396         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5397         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5398
5399         if (!ibqp->uobject) {
5400                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5401                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5402                 qp_init_attr->qp_context = ibqp->qp_context;
5403         } else {
5404                 qp_attr->cap.max_send_wr  = 0;
5405                 qp_attr->cap.max_send_sge = 0;
5406         }
5407
5408         qp_init_attr->qp_type = ibqp->qp_type;
5409         qp_init_attr->recv_cq = ibqp->recv_cq;
5410         qp_init_attr->send_cq = ibqp->send_cq;
5411         qp_init_attr->srq = ibqp->srq;
5412         qp_attr->cap.max_inline_data = qp->max_inline_data;
5413
5414         qp_init_attr->cap            = qp_attr->cap;
5415
5416         qp_init_attr->create_flags = 0;
5417         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5418                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5419
5420         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5421                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5422         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5423                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5424         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5425                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5426         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5427                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5428
5429         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5430                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5431
5432 out:
5433         mutex_unlock(&qp->mutex);
5434         return err;
5435 }
5436
5437 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5438                                           struct ib_ucontext *context,
5439                                           struct ib_udata *udata)
5440 {
5441         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5442         struct mlx5_ib_xrcd *xrcd;
5443         int err;
5444         u16 uid;
5445
5446         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5447                 return ERR_PTR(-ENOSYS);
5448
5449         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5450         if (!xrcd)
5451                 return ERR_PTR(-ENOMEM);
5452
5453         uid = context ? to_mucontext(context)->devx_uid : 0;
5454         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, uid);
5455         if (err) {
5456                 kfree(xrcd);
5457                 return ERR_PTR(-ENOMEM);
5458         }
5459
5460         xrcd->uid = uid;
5461         return &xrcd->ibxrcd;
5462 }
5463
5464 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5465 {
5466         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5467         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5468         u16 uid =  to_mxrcd(xrcd)->uid;
5469         int err;
5470
5471         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, uid);
5472         if (err)
5473                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5474
5475         kfree(xrcd);
5476         return 0;
5477 }
5478
5479 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5480 {
5481         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5482         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5483         struct ib_event event;
5484
5485         if (rwq->ibwq.event_handler) {
5486                 event.device     = rwq->ibwq.device;
5487                 event.element.wq = &rwq->ibwq;
5488                 switch (type) {
5489                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5490                         event.event = IB_EVENT_WQ_FATAL;
5491                         break;
5492                 default:
5493                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5494                         return;
5495                 }
5496
5497                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5498         }
5499 }
5500
5501 static int set_delay_drop(struct mlx5_ib_dev *dev)
5502 {
5503         int err = 0;
5504
5505         mutex_lock(&dev->delay_drop.lock);
5506         if (dev->delay_drop.activate)
5507                 goto out;
5508
5509         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5510         if (err)
5511                 goto out;
5512
5513         dev->delay_drop.activate = true;
5514 out:
5515         mutex_unlock(&dev->delay_drop.lock);
5516
5517         if (!err)
5518                 atomic_inc(&dev->delay_drop.rqs_cnt);
5519         return err;
5520 }
5521
5522 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5523                       struct ib_wq_init_attr *init_attr)
5524 {
5525         struct mlx5_ib_dev *dev;
5526         int has_net_offloads;
5527         __be64 *rq_pas0;
5528         void *in;
5529         void *rqc;
5530         void *wq;
5531         int inlen;
5532         int err;
5533
5534         dev = to_mdev(pd->device);
5535
5536         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5537         in = kvzalloc(inlen, GFP_KERNEL);
5538         if (!in)
5539                 return -ENOMEM;
5540
5541         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5542         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5543         MLX5_SET(rqc,  rqc, mem_rq_type,
5544                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5545         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5546         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5547         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5548         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5549         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5550         MLX5_SET(wq, wq, wq_type,
5551                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5552                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5553         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5554                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5555                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5556                         err = -EOPNOTSUPP;
5557                         goto out;
5558                 } else {
5559                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5560                 }
5561         }
5562         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5563         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5564                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5565                 MLX5_SET(wq, wq, log_wqe_stride_size,
5566                          rwq->single_stride_log_num_of_bytes -
5567                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5568                 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5569                          MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5570         }
5571         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5572         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5573         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5574         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5575         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5576         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5577         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5578         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5579                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5580                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5581                         err = -EOPNOTSUPP;
5582                         goto out;
5583                 }
5584         } else {
5585                 MLX5_SET(rqc, rqc, vsd, 1);
5586         }
5587         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5588                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5589                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5590                         err = -EOPNOTSUPP;
5591                         goto out;
5592                 }
5593                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5594         }
5595         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5596                 if (!(dev->ib_dev.attrs.raw_packet_caps &
5597                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
5598                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5599                         err = -EOPNOTSUPP;
5600                         goto out;
5601                 }
5602                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5603         }
5604         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5605         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5606         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5607         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5608                 err = set_delay_drop(dev);
5609                 if (err) {
5610                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5611                                      err);
5612                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5613                 } else {
5614                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5615                 }
5616         }
5617 out:
5618         kvfree(in);
5619         return err;
5620 }
5621
5622 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5623                             struct ib_wq_init_attr *wq_init_attr,
5624                             struct mlx5_ib_create_wq *ucmd,
5625                             struct mlx5_ib_rwq *rwq)
5626 {
5627         /* Sanity check RQ size before proceeding */
5628         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5629                 return -EINVAL;
5630
5631         if (!ucmd->rq_wqe_count)
5632                 return -EINVAL;
5633
5634         rwq->wqe_count = ucmd->rq_wqe_count;
5635         rwq->wqe_shift = ucmd->rq_wqe_shift;
5636         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5637                 return -EINVAL;
5638
5639         rwq->log_rq_stride = rwq->wqe_shift;
5640         rwq->log_rq_size = ilog2(rwq->wqe_count);
5641         return 0;
5642 }
5643
5644 static int prepare_user_rq(struct ib_pd *pd,
5645                            struct ib_wq_init_attr *init_attr,
5646                            struct ib_udata *udata,
5647                            struct mlx5_ib_rwq *rwq)
5648 {
5649         struct mlx5_ib_dev *dev = to_mdev(pd->device);
5650         struct mlx5_ib_create_wq ucmd = {};
5651         int err;
5652         size_t required_cmd_sz;
5653
5654         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5655                 + sizeof(ucmd.single_stride_log_num_of_bytes);
5656         if (udata->inlen < required_cmd_sz) {
5657                 mlx5_ib_dbg(dev, "invalid inlen\n");
5658                 return -EINVAL;
5659         }
5660
5661         if (udata->inlen > sizeof(ucmd) &&
5662             !ib_is_udata_cleared(udata, sizeof(ucmd),
5663                                  udata->inlen - sizeof(ucmd))) {
5664                 mlx5_ib_dbg(dev, "inlen is not supported\n");
5665                 return -EOPNOTSUPP;
5666         }
5667
5668         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5669                 mlx5_ib_dbg(dev, "copy failed\n");
5670                 return -EFAULT;
5671         }
5672
5673         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5674                 mlx5_ib_dbg(dev, "invalid comp mask\n");
5675                 return -EOPNOTSUPP;
5676         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5677                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5678                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5679                         return -EOPNOTSUPP;
5680                 }
5681                 if ((ucmd.single_stride_log_num_of_bytes <
5682                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5683                     (ucmd.single_stride_log_num_of_bytes >
5684                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5685                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5686                                     ucmd.single_stride_log_num_of_bytes,
5687                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5688                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5689                         return -EINVAL;
5690                 }
5691                 if ((ucmd.single_wqe_log_num_of_strides >
5692                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5693                      (ucmd.single_wqe_log_num_of_strides <
5694                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5695                         mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5696                                     ucmd.single_wqe_log_num_of_strides,
5697                                     MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5698                                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5699                         return -EINVAL;
5700                 }
5701                 rwq->single_stride_log_num_of_bytes =
5702                         ucmd.single_stride_log_num_of_bytes;
5703                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5704                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5705                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5706         }
5707
5708         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5709         if (err) {
5710                 mlx5_ib_dbg(dev, "err %d\n", err);
5711                 return err;
5712         }
5713
5714         err = create_user_rq(dev, pd, rwq, &ucmd);
5715         if (err) {
5716                 mlx5_ib_dbg(dev, "err %d\n", err);
5717                 return err;
5718         }
5719
5720         rwq->user_index = ucmd.user_index;
5721         return 0;
5722 }
5723
5724 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5725                                 struct ib_wq_init_attr *init_attr,
5726                                 struct ib_udata *udata)
5727 {
5728         struct mlx5_ib_dev *dev;
5729         struct mlx5_ib_rwq *rwq;
5730         struct mlx5_ib_create_wq_resp resp = {};
5731         size_t min_resp_len;
5732         int err;
5733
5734         if (!udata)
5735                 return ERR_PTR(-ENOSYS);
5736
5737         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5738         if (udata->outlen && udata->outlen < min_resp_len)
5739                 return ERR_PTR(-EINVAL);
5740
5741         dev = to_mdev(pd->device);
5742         switch (init_attr->wq_type) {
5743         case IB_WQT_RQ:
5744                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5745                 if (!rwq)
5746                         return ERR_PTR(-ENOMEM);
5747                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5748                 if (err)
5749                         goto err;
5750                 err = create_rq(rwq, pd, init_attr);
5751                 if (err)
5752                         goto err_user_rq;
5753                 break;
5754         default:
5755                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5756                             init_attr->wq_type);
5757                 return ERR_PTR(-EINVAL);
5758         }
5759
5760         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5761         rwq->ibwq.state = IB_WQS_RESET;
5762         if (udata->outlen) {
5763                 resp.response_length = offsetof(typeof(resp), response_length) +
5764                                 sizeof(resp.response_length);
5765                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5766                 if (err)
5767                         goto err_copy;
5768         }
5769
5770         rwq->core_qp.event = mlx5_ib_wq_event;
5771         rwq->ibwq.event_handler = init_attr->event_handler;
5772         return &rwq->ibwq;
5773
5774 err_copy:
5775         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5776 err_user_rq:
5777         destroy_user_rq(dev, pd, rwq);
5778 err:
5779         kfree(rwq);
5780         return ERR_PTR(err);
5781 }
5782
5783 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5784 {
5785         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5786         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5787
5788         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5789         destroy_user_rq(dev, wq->pd, rwq);
5790         kfree(rwq);
5791
5792         return 0;
5793 }
5794
5795 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5796                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5797                                                       struct ib_udata *udata)
5798 {
5799         struct mlx5_ib_dev *dev = to_mdev(device);
5800         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5801         int sz = 1 << init_attr->log_ind_tbl_size;
5802         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5803         size_t min_resp_len;
5804         int inlen;
5805         int err;
5806         int i;
5807         u32 *in;
5808         void *rqtc;
5809
5810         if (udata->inlen > 0 &&
5811             !ib_is_udata_cleared(udata, 0,
5812                                  udata->inlen))
5813                 return ERR_PTR(-EOPNOTSUPP);
5814
5815         if (init_attr->log_ind_tbl_size >
5816             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5817                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5818                             init_attr->log_ind_tbl_size,
5819                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5820                 return ERR_PTR(-EINVAL);
5821         }
5822
5823         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5824         if (udata->outlen && udata->outlen < min_resp_len)
5825                 return ERR_PTR(-EINVAL);
5826
5827         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5828         if (!rwq_ind_tbl)
5829                 return ERR_PTR(-ENOMEM);
5830
5831         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5832         in = kvzalloc(inlen, GFP_KERNEL);
5833         if (!in) {
5834                 err = -ENOMEM;
5835                 goto err;
5836         }
5837
5838         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5839
5840         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5841         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5842
5843         for (i = 0; i < sz; i++)
5844                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5845
5846         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5847         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5848
5849         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5850         kvfree(in);
5851
5852         if (err)
5853                 goto err;
5854
5855         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5856         if (udata->outlen) {
5857                 resp.response_length = offsetof(typeof(resp), response_length) +
5858                                         sizeof(resp.response_length);
5859                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5860                 if (err)
5861                         goto err_copy;
5862         }
5863
5864         return &rwq_ind_tbl->ib_rwq_ind_tbl;
5865
5866 err_copy:
5867         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5868 err:
5869         kfree(rwq_ind_tbl);
5870         return ERR_PTR(err);
5871 }
5872
5873 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5874 {
5875         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5876         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5877
5878         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5879
5880         kfree(rwq_ind_tbl);
5881         return 0;
5882 }
5883
5884 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5885                       u32 wq_attr_mask, struct ib_udata *udata)
5886 {
5887         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5888         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5889         struct mlx5_ib_modify_wq ucmd = {};
5890         size_t required_cmd_sz;
5891         int curr_wq_state;
5892         int wq_state;
5893         int inlen;
5894         int err;
5895         void *rqc;
5896         void *in;
5897
5898         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5899         if (udata->inlen < required_cmd_sz)
5900                 return -EINVAL;
5901
5902         if (udata->inlen > sizeof(ucmd) &&
5903             !ib_is_udata_cleared(udata, sizeof(ucmd),
5904                                  udata->inlen - sizeof(ucmd)))
5905                 return -EOPNOTSUPP;
5906
5907         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5908                 return -EFAULT;
5909
5910         if (ucmd.comp_mask || ucmd.reserved)
5911                 return -EOPNOTSUPP;
5912
5913         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5914         in = kvzalloc(inlen, GFP_KERNEL);
5915         if (!in)
5916                 return -ENOMEM;
5917
5918         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5919
5920         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5921                 wq_attr->curr_wq_state : wq->state;
5922         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5923                 wq_attr->wq_state : curr_wq_state;
5924         if (curr_wq_state == IB_WQS_ERR)
5925                 curr_wq_state = MLX5_RQC_STATE_ERR;
5926         if (wq_state == IB_WQS_ERR)
5927                 wq_state = MLX5_RQC_STATE_ERR;
5928         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5929         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
5930         MLX5_SET(rqc, rqc, state, wq_state);
5931
5932         if (wq_attr_mask & IB_WQ_FLAGS) {
5933                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5934                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5935                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5936                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
5937                                             "supported\n");
5938                                 err = -EOPNOTSUPP;
5939                                 goto out;
5940                         }
5941                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5942                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5943                         MLX5_SET(rqc, rqc, vsd,
5944                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5945                 }
5946
5947                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5948                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5949                         err = -EOPNOTSUPP;
5950                         goto out;
5951                 }
5952         }
5953
5954         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5955                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5956                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5957                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5958                         MLX5_SET(rqc, rqc, counter_set_id,
5959                                  dev->port->cnts.set_id);
5960                 } else
5961                         dev_info_once(
5962                                 &dev->ib_dev.dev,
5963                                 "Receive WQ counters are not supported on current FW\n");
5964         }
5965
5966         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5967         if (!err)
5968                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5969
5970 out:
5971         kvfree(in);
5972         return err;
5973 }
5974
5975 struct mlx5_ib_drain_cqe {
5976         struct ib_cqe cqe;
5977         struct completion done;
5978 };
5979
5980 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5981 {
5982         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5983                                                      struct mlx5_ib_drain_cqe,
5984                                                      cqe);
5985
5986         complete(&cqe->done);
5987 }
5988
5989 /* This function returns only once the drained WR was completed */
5990 static void handle_drain_completion(struct ib_cq *cq,
5991                                     struct mlx5_ib_drain_cqe *sdrain,
5992                                     struct mlx5_ib_dev *dev)
5993 {
5994         struct mlx5_core_dev *mdev = dev->mdev;
5995
5996         if (cq->poll_ctx == IB_POLL_DIRECT) {
5997                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5998                         ib_process_cq_direct(cq, -1);
5999                 return;
6000         }
6001
6002         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6003                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6004                 bool triggered = false;
6005                 unsigned long flags;
6006
6007                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6008                 /* Make sure that the CQ handler won't run if wasn't run yet */
6009                 if (!mcq->mcq.reset_notify_added)
6010                         mcq->mcq.reset_notify_added = 1;
6011                 else
6012                         triggered = true;
6013                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6014
6015                 if (triggered) {
6016                         /* Wait for any scheduled/running task to be ended */
6017                         switch (cq->poll_ctx) {
6018                         case IB_POLL_SOFTIRQ:
6019                                 irq_poll_disable(&cq->iop);
6020                                 irq_poll_enable(&cq->iop);
6021                                 break;
6022                         case IB_POLL_WORKQUEUE:
6023                                 cancel_work_sync(&cq->work);
6024                                 break;
6025                         default:
6026                                 WARN_ON_ONCE(1);
6027                         }
6028                 }
6029
6030                 /* Run the CQ handler - this makes sure that the drain WR will
6031                  * be processed if wasn't processed yet.
6032                  */
6033                 mcq->mcq.comp(&mcq->mcq);
6034         }
6035
6036         wait_for_completion(&sdrain->done);
6037 }
6038
6039 void mlx5_ib_drain_sq(struct ib_qp *qp)
6040 {
6041         struct ib_cq *cq = qp->send_cq;
6042         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6043         struct mlx5_ib_drain_cqe sdrain;
6044         const struct ib_send_wr *bad_swr;
6045         struct ib_rdma_wr swr = {
6046                 .wr = {
6047                         .next = NULL,
6048                         { .wr_cqe       = &sdrain.cqe, },
6049                         .opcode = IB_WR_RDMA_WRITE,
6050                 },
6051         };
6052         int ret;
6053         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6054         struct mlx5_core_dev *mdev = dev->mdev;
6055
6056         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6057         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6058                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6059                 return;
6060         }
6061
6062         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6063         init_completion(&sdrain.done);
6064
6065         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6066         if (ret) {
6067                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6068                 return;
6069         }
6070
6071         handle_drain_completion(cq, &sdrain, dev);
6072 }
6073
6074 void mlx5_ib_drain_rq(struct ib_qp *qp)
6075 {
6076         struct ib_cq *cq = qp->recv_cq;
6077         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6078         struct mlx5_ib_drain_cqe rdrain;
6079         struct ib_recv_wr rwr = {};
6080         const struct ib_recv_wr *bad_rwr;
6081         int ret;
6082         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6083         struct mlx5_core_dev *mdev = dev->mdev;
6084
6085         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6086         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6087                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6088                 return;
6089         }
6090
6091         rwr.wr_cqe = &rdrain.cqe;
6092         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6093         init_completion(&rdrain.done);
6094
6095         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6096         if (ret) {
6097                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6098                 return;
6099         }
6100
6101         handle_drain_completion(cq, &rdrain, dev);
6102 }