drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <rdma/rdma_counter.h>
  38 #include <linux/mlx5/fs.h>
  39 #include "mlx5_ib.h"
  40 #include "ib_rep.h"
  41 #include "cmd.h"
  42 #include "qp.h"
  43
  44 enum {
  45         MLX5_IB_ACK_REQ_FREQ    = 8,
  46 };
  47
  48 enum {
  49         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  50         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  51         MLX5_IB_LINK_TYPE_IB            = 0,
  52         MLX5_IB_LINK_TYPE_ETH           = 1
  53 };
  54
  55 enum {
  56         MLX5_IB_SQ_STRIDE       = 6,
  57         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  58 };
  59
  60 static const u32 mlx5_ib_opcode[] = {
  61         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  62         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  63         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  64         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  65         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  66         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  67         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  68         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  69         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  70         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  71         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  72         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  73         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  74         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  75 };
  76
  77 struct mlx5_wqe_eth_pad {
  78         u8 rsvd0[16];
  79 };
  80
  81 enum raw_qp_set_mask_map {
  82         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  83         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  84 };
  85
  86 struct mlx5_modify_raw_qp_param {
  87         u16 operation;
  88
  89         u32 set_mask; /* raw_qp_set_mask_map */
  90
  91         struct mlx5_rate_limit rl;
  92
  93         u8 rq_q_ctr_id;
  94         u16 port;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 /**
 112  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
 113  * to kernel buffer
 114  *
 115  * @umem: User space memory where the WQ is
 116  * @buffer: buffer to copy to
 117  * @buflen: buffer length
 118  * @wqe_index: index of WQE to copy from
 119  * @wq_offset: offset to start of WQ
 120  * @wq_wqe_cnt: number of WQEs in WQ
 121  * @wq_wqe_shift: log2 of WQE size
 122  * @bcnt: number of bytes to copy
 123  * @bytes_copied: number of bytes to copy (return value)
 124  *
 125  * Copies from start of WQE bcnt or less bytes.
 126  * Does not gurantee to copy the entire WQE.
 127  *
 128  * Return: zero on success, or an error code.
 129  */
 130 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
 131                                         size_t buflen, int wqe_index,
 132                                         int wq_offset, int wq_wqe_cnt,
 133                                         int wq_wqe_shift, int bcnt,
 134                                         size_t *bytes_copied)
 135 {
 136         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 137         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 138         size_t copy_length;
 139         int ret;
 140
 141         /* don't copy more than requested, more than buffer length or
 142          * beyond WQ end
 143          */
 144         copy_length = min_t(u32, buflen, wq_end - offset);
 145         copy_length = min_t(u32, copy_length, bcnt);
 146
 147         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 148         if (ret)
 149                 return ret;
 150
 151         if (!ret && bytes_copied)
 152                 *bytes_copied = copy_length;
 153
 154         return 0;
 155 }
 156
 157 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 158                                       void *buffer, size_t buflen, size_t *bc)
 159 {
 160         struct mlx5_wqe_ctrl_seg *ctrl;
 161         size_t bytes_copied = 0;
 162         size_t wqe_length;
 163         void *p;
 164         int ds;
 165
 166         wqe_index = wqe_index & qp->sq.fbc.sz_m1;
 167
 168         /* read the control segment first */
 169         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 170         ctrl = p;
 171         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 172         wqe_length = ds * MLX5_WQE_DS_UNITS;
 173
 174         /* read rest of WQE if it spreads over more than one stride */
 175         while (bytes_copied < wqe_length) {
 176                 size_t copy_length =
 177                         min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
 178
 179                 if (!copy_length)
 180                         break;
 181
 182                 memcpy(buffer + bytes_copied, p, copy_length);
 183                 bytes_copied += copy_length;
 184
 185                 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
 186                 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 187         }
 188         *bc = bytes_copied;
 189         return 0;
 190 }
 191
 192 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 193                                     void *buffer, size_t buflen, size_t *bc)
 194 {
 195         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 196         struct ib_umem *umem = base->ubuffer.umem;
 197         struct mlx5_ib_wq *wq = &qp->sq;
 198         struct mlx5_wqe_ctrl_seg *ctrl;
 199         size_t bytes_copied;
 200         size_t bytes_copied2;
 201         size_t wqe_length;
 202         int ret;
 203         int ds;
 204
 205         /* at first read as much as possible */
 206         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 207                                            wq->offset, wq->wqe_cnt,
 208                                            wq->wqe_shift, buflen,
 209                                            &bytes_copied);
 210         if (ret)
 211                 return ret;
 212
 213         /* we need at least control segment size to proceed */
 214         if (bytes_copied < sizeof(*ctrl))
 215                 return -EINVAL;
 216
 217         ctrl = buffer;
 218         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 219         wqe_length = ds * MLX5_WQE_DS_UNITS;
 220
 221         /* if we copied enough then we are done */
 222         if (bytes_copied >= wqe_length) {
 223                 *bc = bytes_copied;
 224                 return 0;
 225         }
 226
 227         /* otherwise this a wrapped around wqe
 228          * so read the remaining bytes starting
 229          * from  wqe_index 0
 230          */
 231         ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
 232                                            buflen - bytes_copied, 0, wq->offset,
 233                                            wq->wqe_cnt, wq->wqe_shift,
 234                                            wqe_length - bytes_copied,
 235                                            &bytes_copied2);
 236
 237         if (ret)
 238                 return ret;
 239         *bc = bytes_copied + bytes_copied2;
 240         return 0;
 241 }
 242
 243 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 244                         size_t buflen, size_t *bc)
 245 {
 246         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 247         struct ib_umem *umem = base->ubuffer.umem;
 248
 249         if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
 250                 return -EINVAL;
 251
 252         if (!umem)
 253                 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
 254                                                   buflen, bc);
 255
 256         return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
 257 }
 258
 259 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
 260                                     void *buffer, size_t buflen, size_t *bc)
 261 {
 262         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 263         struct ib_umem *umem = base->ubuffer.umem;
 264         struct mlx5_ib_wq *wq = &qp->rq;
 265         size_t bytes_copied;
 266         int ret;
 267
 268         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 269                                            wq->offset, wq->wqe_cnt,
 270                                            wq->wqe_shift, buflen,
 271                                            &bytes_copied);
 272
 273         if (ret)
 274                 return ret;
 275         *bc = bytes_copied;
 276         return 0;
 277 }
 278
 279 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 280                         size_t buflen, size_t *bc)
 281 {
 282         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 283         struct ib_umem *umem = base->ubuffer.umem;
 284         struct mlx5_ib_wq *wq = &qp->rq;
 285         size_t wqe_size = 1 << wq->wqe_shift;
 286
 287         if (buflen < wqe_size)
 288                 return -EINVAL;
 289
 290         if (!umem)
 291                 return -EOPNOTSUPP;
 292
 293         return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
 294 }
 295
 296 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
 297                                      void *buffer, size_t buflen, size_t *bc)
 298 {
 299         struct ib_umem *umem = srq->umem;
 300         size_t bytes_copied;
 301         int ret;
 302
 303         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
 304                                            srq->msrq.max, srq->msrq.wqe_shift,
 305                                            buflen, &bytes_copied);
 306
 307         if (ret)
 308                 return ret;
 309         *bc = bytes_copied;
 310         return 0;
 311 }
 312
 313 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
 314                          size_t buflen, size_t *bc)
 315 {
 316         struct ib_umem *umem = srq->umem;
 317         size_t wqe_size = 1 << srq->msrq.wqe_shift;
 318
 319         if (buflen < wqe_size)
 320                 return -EINVAL;
 321
 322         if (!umem)
 323                 return -EOPNOTSUPP;
 324
 325         return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
 326 }
 327
 328 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 329 {
 330         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 331         struct ib_event event;
 332
 333         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 334                 /* This event is only valid for trans_qps */
 335                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 336         }
 337
 338         if (ibqp->event_handler) {
 339                 event.device     = ibqp->device;
 340                 event.element.qp = ibqp;
 341                 switch (type) {
 342                 case MLX5_EVENT_TYPE_PATH_MIG:
 343                         event.event = IB_EVENT_PATH_MIG;
 344                         break;
 345                 case MLX5_EVENT_TYPE_COMM_EST:
 346                         event.event = IB_EVENT_COMM_EST;
 347                         break;
 348                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 349                         event.event = IB_EVENT_SQ_DRAINED;
 350                         break;
 351                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 352                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 353                         break;
 354                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 355                         event.event = IB_EVENT_QP_FATAL;
 356                         break;
 357                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 358                         event.event = IB_EVENT_PATH_MIG_ERR;
 359                         break;
 360                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 361                         event.event = IB_EVENT_QP_REQ_ERR;
 362                         break;
 363                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 364                         event.event = IB_EVENT_QP_ACCESS_ERR;
 365                         break;
 366                 default:
 367                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 368                         return;
 369                 }
 370
 371                 ibqp->event_handler(&event, ibqp->qp_context);
 372         }
 373 }
 374
 375 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 376                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 377 {
 378         int wqe_size;
 379         int wq_size;
 380
 381         /* Sanity check RQ size before proceeding */
 382         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 383                 return -EINVAL;
 384
 385         if (!has_rq) {
 386                 qp->rq.max_gs = 0;
 387                 qp->rq.wqe_cnt = 0;
 388                 qp->rq.wqe_shift = 0;
 389                 cap->max_recv_wr = 0;
 390                 cap->max_recv_sge = 0;
 391         } else {
 392                 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
 393
 394                 if (ucmd) {
 395                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 396                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 397                                 return -EINVAL;
 398                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 399                         if ((1 << qp->rq.wqe_shift) /
 400                                     sizeof(struct mlx5_wqe_data_seg) <
 401                             wq_sig)
 402                                 return -EINVAL;
 403                         qp->rq.max_gs =
 404                                 (1 << qp->rq.wqe_shift) /
 405                                         sizeof(struct mlx5_wqe_data_seg) -
 406                                 wq_sig;
 407                         qp->rq.max_post = qp->rq.wqe_cnt;
 408                 } else {
 409                         wqe_size =
 410                                 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
 411                                          0;
 412                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 413                         wqe_size = roundup_pow_of_two(wqe_size);
 414                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 415                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 416                         qp->rq.wqe_cnt = wq_size / wqe_size;
 417                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 418                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 419                                             wqe_size,
 420                                             MLX5_CAP_GEN(dev->mdev,
 421                                                          max_wqe_sz_rq));
 422                                 return -EINVAL;
 423                         }
 424                         qp->rq.wqe_shift = ilog2(wqe_size);
 425                         qp->rq.max_gs =
 426                                 (1 << qp->rq.wqe_shift) /
 427                                         sizeof(struct mlx5_wqe_data_seg) -
 428                                 wq_sig;
 429                         qp->rq.max_post = qp->rq.wqe_cnt;
 430                 }
 431         }
 432
 433         return 0;
 434 }
 435
 436 static int sq_overhead(struct ib_qp_init_attr *attr)
 437 {
 438         int size = 0;
 439
 440         switch (attr->qp_type) {
 441         case IB_QPT_XRC_INI:
 442                 size += sizeof(struct mlx5_wqe_xrc_seg);
 443                 /* fall through */
 444         case IB_QPT_RC:
 445                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 446                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 447                             sizeof(struct mlx5_wqe_raddr_seg),
 448                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 449                             sizeof(struct mlx5_mkey_seg) +
 450                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 451                             MLX5_IB_UMR_OCTOWORD);
 452                 break;
 453
 454         case IB_QPT_XRC_TGT:
 455                 return 0;
 456
 457         case IB_QPT_UC:
 458                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 459                         max(sizeof(struct mlx5_wqe_raddr_seg),
 460                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 461                             sizeof(struct mlx5_mkey_seg));
 462                 break;
 463
 464         case IB_QPT_UD:
 465                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 466                         size += sizeof(struct mlx5_wqe_eth_pad) +
 467                                 sizeof(struct mlx5_wqe_eth_seg);
 468                 /* fall through */
 469         case IB_QPT_SMI:
 470         case MLX5_IB_QPT_HW_GSI:
 471                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 472                         sizeof(struct mlx5_wqe_datagram_seg);
 473                 break;
 474
 475         case MLX5_IB_QPT_REG_UMR:
 476                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 477                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 478                         sizeof(struct mlx5_mkey_seg);
 479                 break;
 480
 481         default:
 482                 return -EINVAL;
 483         }
 484
 485         return size;
 486 }
 487
 488 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 489 {
 490         int inl_size = 0;
 491         int size;
 492
 493         size = sq_overhead(attr);
 494         if (size < 0)
 495                 return size;
 496
 497         if (attr->cap.max_inline_data) {
 498                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 499                         attr->cap.max_inline_data;
 500         }
 501
 502         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 503         if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
 504             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 505                 return MLX5_SIG_WQE_SIZE;
 506         else
 507                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 508 }
 509
 510 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 511 {
 512         int max_sge;
 513
 514         if (attr->qp_type == IB_QPT_RC)
 515                 max_sge = (min_t(int, wqe_size, 512) -
 516                            sizeof(struct mlx5_wqe_ctrl_seg) -
 517                            sizeof(struct mlx5_wqe_raddr_seg)) /
 518                         sizeof(struct mlx5_wqe_data_seg);
 519         else if (attr->qp_type == IB_QPT_XRC_INI)
 520                 max_sge = (min_t(int, wqe_size, 512) -
 521                            sizeof(struct mlx5_wqe_ctrl_seg) -
 522                            sizeof(struct mlx5_wqe_xrc_seg) -
 523                            sizeof(struct mlx5_wqe_raddr_seg)) /
 524                         sizeof(struct mlx5_wqe_data_seg);
 525         else
 526                 max_sge = (wqe_size - sq_overhead(attr)) /
 527                         sizeof(struct mlx5_wqe_data_seg);
 528
 529         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 530                      sizeof(struct mlx5_wqe_data_seg));
 531 }
 532
 533 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 534                         struct mlx5_ib_qp *qp)
 535 {
 536         int wqe_size;
 537         int wq_size;
 538
 539         if (!attr->cap.max_send_wr)
 540                 return 0;
 541
 542         wqe_size = calc_send_wqe(attr);
 543         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 544         if (wqe_size < 0)
 545                 return wqe_size;
 546
 547         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 548                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 549                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 550                 return -EINVAL;
 551         }
 552
 553         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 554                               sizeof(struct mlx5_wqe_inline_seg);
 555         attr->cap.max_inline_data = qp->max_inline_data;
 556
 557         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 558         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 559         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 560                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 561                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 562                             qp->sq.wqe_cnt,
 563                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 564                 return -ENOMEM;
 565         }
 566         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 567         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 568         if (qp->sq.max_gs < attr->cap.max_send_sge)
 569                 return -ENOMEM;
 570
 571         attr->cap.max_send_sge = qp->sq.max_gs;
 572         qp->sq.max_post = wq_size / wqe_size;
 573         attr->cap.max_send_wr = qp->sq.max_post;
 574
 575         return wq_size;
 576 }
 577
 578 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 579                             struct mlx5_ib_qp *qp,
 580                             struct mlx5_ib_create_qp *ucmd,
 581                             struct mlx5_ib_qp_base *base,
 582                             struct ib_qp_init_attr *attr)
 583 {
 584         int desc_sz = 1 << qp->sq.wqe_shift;
 585
 586         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 587                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 588                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 589                 return -EINVAL;
 590         }
 591
 592         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 593                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 594                              ucmd->sq_wqe_count);
 595                 return -EINVAL;
 596         }
 597
 598         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 599
 600         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 601                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 602                              qp->sq.wqe_cnt,
 603                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 604                 return -EINVAL;
 605         }
 606
 607         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 608             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
 609                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 610                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 611         } else {
 612                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 613                                          (qp->sq.wqe_cnt << 6);
 614         }
 615
 616         return 0;
 617 }
 618
 619 static int qp_has_rq(struct ib_qp_init_attr *attr)
 620 {
 621         if (attr->qp_type == IB_QPT_XRC_INI ||
 622             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 623             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 624             !attr->cap.max_recv_wr)
 625                 return 0;
 626
 627         return 1;
 628 }
 629
 630 enum {
 631         /* this is the first blue flame register in the array of bfregs assigned
 632          * to a processes. Since we do not use it for blue flame but rather
 633          * regular 64 bit doorbells, we do not need a lock for maintaiing
 634          * "odd/even" order
 635          */
 636         NUM_NON_BLUE_FLAME_BFREGS = 1,
 637 };
 638
 639 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 640 {
 641         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 642 }
 643
 644 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 645                          struct mlx5_bfreg_info *bfregi)
 646 {
 647         int n;
 648
 649         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 650             NUM_NON_BLUE_FLAME_BFREGS;
 651
 652         return n >= 0 ? n : 0;
 653 }
 654
 655 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 656                            struct mlx5_bfreg_info *bfregi)
 657 {
 658         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 659 }
 660
 661 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 662                           struct mlx5_bfreg_info *bfregi)
 663 {
 664         int med;
 665
 666         med = num_med_bfreg(dev, bfregi);
 667         return ++med;
 668 }
 669
 670 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 671                                   struct mlx5_bfreg_info *bfregi)
 672 {
 673         int i;
 674
 675         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 676                 if (!bfregi->count[i]) {
 677                         bfregi->count[i]++;
 678                         return i;
 679                 }
 680         }
 681
 682         return -ENOMEM;
 683 }
 684
 685 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 686                                  struct mlx5_bfreg_info *bfregi)
 687 {
 688         int minidx = first_med_bfreg(dev, bfregi);
 689         int i;
 690
 691         if (minidx < 0)
 692                 return minidx;
 693
 694         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 695                 if (bfregi->count[i] < bfregi->count[minidx])
 696                         minidx = i;
 697                 if (!bfregi->count[minidx])
 698                         break;
 699         }
 700
 701         bfregi->count[minidx]++;
 702         return minidx;
 703 }
 704
 705 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 706                        struct mlx5_bfreg_info *bfregi)
 707 {
 708         int bfregn = -ENOMEM;
 709
 710         if (bfregi->lib_uar_dyn)
 711                 return -EINVAL;
 712
 713         mutex_lock(&bfregi->lock);
 714         if (bfregi->ver >= 2) {
 715                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 716                 if (bfregn < 0)
 717                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 718         }
 719
 720         if (bfregn < 0) {
 721                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 722                 bfregn = 0;
 723                 bfregi->count[bfregn]++;
 724         }
 725         mutex_unlock(&bfregi->lock);
 726
 727         return bfregn;
 728 }
 729
 730 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 731 {
 732         mutex_lock(&bfregi->lock);
 733         bfregi->count[bfregn]--;
 734         mutex_unlock(&bfregi->lock);
 735 }
 736
 737 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 738 {
 739         switch (state) {
 740         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 741         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 742         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 743         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 744         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 745         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 746         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 747         default:                return -1;
 748         }
 749 }
 750
 751 static int to_mlx5_st(enum ib_qp_type type)
 752 {
 753         switch (type) {
 754         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 755         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 756         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 757         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 758         case IB_QPT_XRC_INI:
 759         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 760         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 761         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 762         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 763         case IB_QPT_RAW_PACKET:         return MLX5_QP_ST_RAW_ETHERTYPE;
 764         default:                return -EINVAL;
 765         }
 766 }
 767
 768 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 769                              struct mlx5_ib_cq *recv_cq);
 770 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 771                                struct mlx5_ib_cq *recv_cq);
 772
 773 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 774                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 775                         bool dyn_bfreg)
 776 {
 777         unsigned int bfregs_per_sys_page;
 778         u32 index_of_sys_page;
 779         u32 offset;
 780
 781         if (bfregi->lib_uar_dyn)
 782                 return -EINVAL;
 783
 784         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 785                                 MLX5_NON_FP_BFREGS_PER_UAR;
 786         index_of_sys_page = bfregn / bfregs_per_sys_page;
 787
 788         if (dyn_bfreg) {
 789                 index_of_sys_page += bfregi->num_static_sys_pages;
 790
 791                 if (index_of_sys_page >= bfregi->num_sys_pages)
 792                         return -EINVAL;
 793
 794                 if (bfregn > bfregi->num_dyn_bfregs ||
 795                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 796                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 797                         return -EINVAL;
 798                 }
 799         }
 800
 801         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 802         return bfregi->sys_pages[index_of_sys_page] + offset;
 803 }
 804
 805 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 806                             unsigned long addr, size_t size,
 807                             struct ib_umem **umem, int *npages, int *page_shift,
 808                             int *ncont, u32 *offset)
 809 {
 810         int err;
 811
 812         *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
 813         if (IS_ERR(*umem)) {
 814                 mlx5_ib_dbg(dev, "umem_get failed\n");
 815                 return PTR_ERR(*umem);
 816         }
 817
 818         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 819
 820         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 821         if (err) {
 822                 mlx5_ib_warn(dev, "bad offset\n");
 823                 goto err_umem;
 824         }
 825
 826         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 827                     addr, size, *npages, *page_shift, *ncont, *offset);
 828
 829         return 0;
 830
 831 err_umem:
 832         ib_umem_release(*umem);
 833         *umem = NULL;
 834
 835         return err;
 836 }
 837
 838 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 839                             struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
 840 {
 841         struct mlx5_ib_ucontext *context =
 842                 rdma_udata_to_drv_context(
 843                         udata,
 844                         struct mlx5_ib_ucontext,
 845                         ibucontext);
 846
 847         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 848                 atomic_dec(&dev->delay_drop.rqs_cnt);
 849
 850         mlx5_ib_db_unmap_user(context, &rwq->db);
 851         ib_umem_release(rwq->umem);
 852 }
 853
 854 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 855                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 856                           struct mlx5_ib_create_wq *ucmd)
 857 {
 858         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
 859                 udata, struct mlx5_ib_ucontext, ibucontext);
 860         int page_shift = 0;
 861         int npages;
 862         u32 offset = 0;
 863         int ncont = 0;
 864         int err;
 865
 866         if (!ucmd->buf_addr)
 867                 return -EINVAL;
 868
 869         rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
 870         if (IS_ERR(rwq->umem)) {
 871                 mlx5_ib_dbg(dev, "umem_get failed\n");
 872                 err = PTR_ERR(rwq->umem);
 873                 return err;
 874         }
 875
 876         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 877                            &ncont, NULL);
 878         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 879                                      &rwq->rq_page_offset);
 880         if (err) {
 881                 mlx5_ib_warn(dev, "bad offset\n");
 882                 goto err_umem;
 883         }
 884
 885         rwq->rq_num_pas = ncont;
 886         rwq->page_shift = page_shift;
 887         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 888         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 889
 890         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 891                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 892                     npages, page_shift, ncont, offset);
 893
 894         err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
 895         if (err) {
 896                 mlx5_ib_dbg(dev, "map failed\n");
 897                 goto err_umem;
 898         }
 899
 900         rwq->create_type = MLX5_WQ_USER;
 901         return 0;
 902
 903 err_umem:
 904         ib_umem_release(rwq->umem);
 905         return err;
 906 }
 907
 908 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 909                          struct mlx5_bfreg_info *bfregi, int bfregn)
 910 {
 911         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 912                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 913 }
 914
 915 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 916                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 917                           struct ib_qp_init_attr *attr, u32 **in,
 918                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 919                           struct mlx5_ib_qp_base *base,
 920                           struct mlx5_ib_create_qp *ucmd)
 921 {
 922         struct mlx5_ib_ucontext *context;
 923         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 924         int page_shift = 0;
 925         int uar_index = 0;
 926         int npages;
 927         u32 offset = 0;
 928         int bfregn;
 929         int ncont = 0;
 930         __be64 *pas;
 931         void *qpc;
 932         int err;
 933         u16 uid;
 934         u32 uar_flags;
 935
 936         context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
 937                                             ibucontext);
 938         uar_flags = qp->flags_en &
 939                     (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
 940         switch (uar_flags) {
 941         case MLX5_QP_FLAG_UAR_PAGE_INDEX:
 942                 uar_index = ucmd->bfreg_index;
 943                 bfregn = MLX5_IB_INVALID_BFREG;
 944                 break;
 945         case MLX5_QP_FLAG_BFREG_INDEX:
 946                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 947                                                 ucmd->bfreg_index, true);
 948                 if (uar_index < 0)
 949                         return uar_index;
 950                 bfregn = MLX5_IB_INVALID_BFREG;
 951                 break;
 952         case 0:
 953                 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
 954                         return -EINVAL;
 955                 bfregn = alloc_bfreg(dev, &context->bfregi);
 956                 if (bfregn < 0)
 957                         return bfregn;
 958                 break;
 959         default:
 960                 return -EINVAL;
 961         }
 962
 963         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 964         if (bfregn != MLX5_IB_INVALID_BFREG)
 965                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 966                                                 false);
 967
 968         qp->rq.offset = 0;
 969         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 970         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 971
 972         err = set_user_buf_size(dev, qp, ucmd, base, attr);
 973         if (err)
 974                 goto err_bfreg;
 975
 976         if (ucmd->buf_addr && ubuffer->buf_size) {
 977                 ubuffer->buf_addr = ucmd->buf_addr;
 978                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 979                                        ubuffer->buf_size, &ubuffer->umem,
 980                                        &npages, &page_shift, &ncont, &offset);
 981                 if (err)
 982                         goto err_bfreg;
 983         } else {
 984                 ubuffer->umem = NULL;
 985         }
 986
 987         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 988                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 989         *in = kvzalloc(*inlen, GFP_KERNEL);
 990         if (!*in) {
 991                 err = -ENOMEM;
 992                 goto err_umem;
 993         }
 994
 995         uid = (attr->qp_type != IB_QPT_XRC_TGT &&
 996                attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
 997         MLX5_SET(create_qp_in, *in, uid, uid);
 998         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 999         if (ubuffer->umem)
1000                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
1001
1002         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1003
1004         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1005         MLX5_SET(qpc, qpc, page_offset, offset);
1006
1007         MLX5_SET(qpc, qpc, uar_page, uar_index);
1008         if (bfregn != MLX5_IB_INVALID_BFREG)
1009                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
1010         else
1011                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
1012         qp->bfregn = bfregn;
1013
1014         err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
1015         if (err) {
1016                 mlx5_ib_dbg(dev, "map failed\n");
1017                 goto err_free;
1018         }
1019
1020         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1021         if (err) {
1022                 mlx5_ib_dbg(dev, "copy failed\n");
1023                 goto err_unmap;
1024         }
1025         qp->create_type = MLX5_QP_USER;
1026
1027         return 0;
1028
1029 err_unmap:
1030         mlx5_ib_db_unmap_user(context, &qp->db);
1031
1032 err_free:
1033         kvfree(*in);
1034
1035 err_umem:
1036         ib_umem_release(ubuffer->umem);
1037
1038 err_bfreg:
1039         if (bfregn != MLX5_IB_INVALID_BFREG)
1040                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
1041         return err;
1042 }
1043
1044 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1045                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base,
1046                             struct ib_udata *udata)
1047 {
1048         struct mlx5_ib_ucontext *context =
1049                 rdma_udata_to_drv_context(
1050                         udata,
1051                         struct mlx5_ib_ucontext,
1052                         ibucontext);
1053
1054         mlx5_ib_db_unmap_user(context, &qp->db);
1055         ib_umem_release(base->ubuffer.umem);
1056
1057         /*
1058          * Free only the BFREGs which are handled by the kernel.
1059          * BFREGs of UARs allocated dynamically are handled by user.
1060          */
1061         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1062                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1063 }
1064
1065 /* get_sq_edge - Get the next nearby edge.
1066  *
1067  * An 'edge' is defined as the first following address after the end
1068  * of the fragment or the SQ. Accordingly, during the WQE construction
1069  * which repetitively increases the pointer to write the next data, it
1070  * simply should check if it gets to an edge.
1071  *
1072  * @sq - SQ buffer.
1073  * @idx - Stride index in the SQ buffer.
1074  *
1075  * Return:
1076  *      The new edge.
1077  */
1078 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1079 {
1080         void *fragment_end;
1081
1082         fragment_end = mlx5_frag_buf_get_wqe
1083                 (&sq->fbc,
1084                  mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1085
1086         return fragment_end + MLX5_SEND_WQE_BB;
1087 }
1088
1089 static int create_kernel_qp(struct mlx5_ib_dev *dev,
1090                             struct ib_qp_init_attr *init_attr,
1091                             struct mlx5_ib_qp *qp,
1092                             u32 **in, int *inlen,
1093                             struct mlx5_ib_qp_base *base)
1094 {
1095         int uar_index;
1096         void *qpc;
1097         int err;
1098
1099         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1100                 qp->bf.bfreg = &dev->fp_bfreg;
1101         else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
1102                 qp->bf.bfreg = &dev->wc_bfreg;
1103         else
1104                 qp->bf.bfreg = &dev->bfreg;
1105
1106         /* We need to divide by two since each register is comprised of
1107          * two buffers of identical size, namely odd and even
1108          */
1109         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1110         uar_index = qp->bf.bfreg->index;
1111
1112         err = calc_sq_size(dev, init_attr, qp);
1113         if (err < 0) {
1114                 mlx5_ib_dbg(dev, "err %d\n", err);
1115                 return err;
1116         }
1117
1118         qp->rq.offset = 0;
1119         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1120         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1121
1122         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1123                                        &qp->buf, dev->mdev->priv.numa_node);
1124         if (err) {
1125                 mlx5_ib_dbg(dev, "err %d\n", err);
1126                 return err;
1127         }
1128
1129         if (qp->rq.wqe_cnt)
1130                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1131                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1132
1133         if (qp->sq.wqe_cnt) {
1134                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1135                                         MLX5_SEND_WQE_BB;
1136                 mlx5_init_fbc_offset(qp->buf.frags +
1137                                      (qp->sq.offset / PAGE_SIZE),
1138                                      ilog2(MLX5_SEND_WQE_BB),
1139                                      ilog2(qp->sq.wqe_cnt),
1140                                      sq_strides_offset, &qp->sq.fbc);
1141
1142                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1143         }
1144
1145         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1146                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1147         *in = kvzalloc(*inlen, GFP_KERNEL);
1148         if (!*in) {
1149                 err = -ENOMEM;
1150                 goto err_buf;
1151         }
1152
1153         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1154         MLX5_SET(qpc, qpc, uar_page, uar_index);
1155         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1156
1157         /* Set "fast registration enabled" for all kernel QPs */
1158         MLX5_SET(qpc, qpc, fre, 1);
1159         MLX5_SET(qpc, qpc, rlky, 1);
1160
1161         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
1162                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1163
1164         mlx5_fill_page_frag_array(&qp->buf,
1165                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1166                                                          *in, pas));
1167
1168         err = mlx5_db_alloc(dev->mdev, &qp->db);
1169         if (err) {
1170                 mlx5_ib_dbg(dev, "err %d\n", err);
1171                 goto err_free;
1172         }
1173
1174         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1175                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1176         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1177                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1178         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1179                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1180         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1181                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1182         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1183                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1184
1185         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1186             !qp->sq.w_list || !qp->sq.wqe_head) {
1187                 err = -ENOMEM;
1188                 goto err_wrid;
1189         }
1190         qp->create_type = MLX5_QP_KERNEL;
1191
1192         return 0;
1193
1194 err_wrid:
1195         kvfree(qp->sq.wqe_head);
1196         kvfree(qp->sq.w_list);
1197         kvfree(qp->sq.wrid);
1198         kvfree(qp->sq.wr_data);
1199         kvfree(qp->rq.wrid);
1200         mlx5_db_free(dev->mdev, &qp->db);
1201
1202 err_free:
1203         kvfree(*in);
1204
1205 err_buf:
1206         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1207         return err;
1208 }
1209
1210 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1211 {
1212         kvfree(qp->sq.wqe_head);
1213         kvfree(qp->sq.w_list);
1214         kvfree(qp->sq.wrid);
1215         kvfree(qp->sq.wr_data);
1216         kvfree(qp->rq.wrid);
1217         mlx5_db_free(dev->mdev, &qp->db);
1218         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1219 }
1220
1221 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1222 {
1223         if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1224             (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
1225                 return MLX5_SRQ_RQ;
1226         else if (!qp->has_rq)
1227                 return MLX5_ZERO_LEN_RQ;
1228
1229         return MLX5_NON_ZERO_RQ;
1230 }
1231
1232 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1233                                     struct mlx5_ib_qp *qp,
1234                                     struct mlx5_ib_sq *sq, u32 tdn,
1235                                     struct ib_pd *pd)
1236 {
1237         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
1238         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1239
1240         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1241         MLX5_SET(tisc, tisc, transport_domain, tdn);
1242         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1243                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1244
1245         return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1246 }
1247
1248 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1249                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1250 {
1251         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1252 }
1253
1254 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1255 {
1256         if (sq->flow_rule)
1257                 mlx5_del_flow_rules(sq->flow_rule);
1258         sq->flow_rule = NULL;
1259 }
1260
1261 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1262                                    struct ib_udata *udata,
1263                                    struct mlx5_ib_sq *sq, void *qpin,
1264                                    struct ib_pd *pd)
1265 {
1266         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1267         __be64 *pas;
1268         void *in;
1269         void *sqc;
1270         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1271         void *wq;
1272         int inlen;
1273         int err;
1274         int page_shift = 0;
1275         int npages;
1276         int ncont = 0;
1277         u32 offset = 0;
1278
1279         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1280                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1281                                &offset);
1282         if (err)
1283                 return err;
1284
1285         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1286         in = kvzalloc(inlen, GFP_KERNEL);
1287         if (!in) {
1288                 err = -ENOMEM;
1289                 goto err_umem;
1290         }
1291
1292         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1293         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1294         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1295         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1296                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1297         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1298         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1299         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1300         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1301         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1302         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1303             MLX5_CAP_ETH(dev->mdev, swp))
1304                 MLX5_SET(sqc, sqc, allow_swp, 1);
1305
1306         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1307         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1308         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1309         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1310         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1311         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1312         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1313         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1314         MLX5_SET(wq, wq, page_offset, offset);
1315
1316         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1317         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1318
1319         err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
1320
1321         kvfree(in);
1322
1323         if (err)
1324                 goto err_umem;
1325
1326         return 0;
1327
1328 err_umem:
1329         ib_umem_release(sq->ubuffer.umem);
1330         sq->ubuffer.umem = NULL;
1331
1332         return err;
1333 }
1334
1335 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1336                                      struct mlx5_ib_sq *sq)
1337 {
1338         destroy_flow_rule_vport_sq(sq);
1339         mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
1340         ib_umem_release(sq->ubuffer.umem);
1341 }
1342
1343 static size_t get_rq_pas_size(void *qpc)
1344 {
1345         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1346         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1347         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1348         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1349         u32 po_quanta     = 1 << (log_page_size - 6);
1350         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1351         u32 page_size     = 1 << log_page_size;
1352         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1353         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1354
1355         return rq_num_pas * sizeof(u64);
1356 }
1357
1358 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1359                                    struct mlx5_ib_rq *rq, void *qpin,
1360                                    size_t qpinlen, struct ib_pd *pd)
1361 {
1362         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1363         __be64 *pas;
1364         __be64 *qp_pas;
1365         void *in;
1366         void *rqc;
1367         void *wq;
1368         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1369         size_t rq_pas_size = get_rq_pas_size(qpc);
1370         size_t inlen;
1371         int err;
1372
1373         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1374                 return -EINVAL;
1375
1376         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1377         in = kvzalloc(inlen, GFP_KERNEL);
1378         if (!in)
1379                 return -ENOMEM;
1380
1381         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1382         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1383         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1384                 MLX5_SET(rqc, rqc, vsd, 1);
1385         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1386         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1387         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1388         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1389         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1390
1391         if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
1392                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1393
1394         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1395         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1396         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1397                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1398         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1399         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1400         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1401         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1402         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1403         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1404
1405         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1406         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1407         memcpy(pas, qp_pas, rq_pas_size);
1408
1409         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
1410
1411         kvfree(in);
1412
1413         return err;
1414 }
1415
1416 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1417                                      struct mlx5_ib_rq *rq)
1418 {
1419         mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
1420 }
1421
1422 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1423                                       struct mlx5_ib_rq *rq,
1424                                       u32 qp_flags_en,
1425                                       struct ib_pd *pd)
1426 {
1427         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1428                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1429                 mlx5_ib_disable_lb(dev, false, true);
1430         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1431 }
1432
1433 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1434                                     struct mlx5_ib_rq *rq, u32 tdn,
1435                                     u32 *qp_flags_en, struct ib_pd *pd,
1436                                     u32 *out)
1437 {
1438         u8 lb_flag = 0;
1439         u32 *in;
1440         void *tirc;
1441         int inlen;
1442         int err;
1443
1444         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1445         in = kvzalloc(inlen, GFP_KERNEL);
1446         if (!in)
1447                 return -ENOMEM;
1448
1449         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1450         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1451         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1452         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1453         MLX5_SET(tirc, tirc, transport_domain, tdn);
1454         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1455                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1456
1457         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1458                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1459
1460         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1461                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1462
1463         if (dev->is_rep) {
1464                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1465                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1466         }
1467
1468         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1469         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1470         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1471         rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1472         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1473                 err = mlx5_ib_enable_lb(dev, false, true);
1474
1475                 if (err)
1476                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1477         }
1478         kvfree(in);
1479
1480         return err;
1481 }
1482
1483 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1484                                 u32 *in, size_t inlen,
1485                                 struct ib_pd *pd,
1486                                 struct ib_udata *udata,
1487                                 struct mlx5_ib_create_qp_resp *resp)
1488 {
1489         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1490         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1491         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1492         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1493                 udata, struct mlx5_ib_ucontext, ibucontext);
1494         int err;
1495         u32 tdn = mucontext->tdn;
1496         u16 uid = to_mpd(pd)->uid;
1497         u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1498
1499         if (qp->sq.wqe_cnt) {
1500                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1501                 if (err)
1502                         return err;
1503
1504                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1505                 if (err)
1506                         goto err_destroy_tis;
1507
1508                 if (uid) {
1509                         resp->tisn = sq->tisn;
1510                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1511                         resp->sqn = sq->base.mqp.qpn;
1512                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1513                 }
1514
1515                 sq->base.container_mibqp = qp;
1516                 sq->base.mqp.event = mlx5_ib_qp_event;
1517         }
1518
1519         if (qp->rq.wqe_cnt) {
1520                 rq->base.container_mibqp = qp;
1521
1522                 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
1523                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1524                 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
1525                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1526                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1527                 if (err)
1528                         goto err_destroy_sq;
1529
1530                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1531                                                out);
1532                 if (err)
1533                         goto err_destroy_rq;
1534
1535                 if (uid) {
1536                         resp->rqn = rq->base.mqp.qpn;
1537                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1538                         resp->tirn = rq->tirn;
1539                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1540                         if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1541                                 resp->tir_icm_addr = MLX5_GET(
1542                                         create_tir_out, out, icm_address_31_0);
1543                                 resp->tir_icm_addr |=
1544                                         (u64)MLX5_GET(create_tir_out, out,
1545                                                       icm_address_39_32)
1546                                         << 32;
1547                                 resp->tir_icm_addr |=
1548                                         (u64)MLX5_GET(create_tir_out, out,
1549                                                       icm_address_63_40)
1550                                         << 40;
1551                                 resp->comp_mask |=
1552                                         MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1553                         }
1554                 }
1555         }
1556
1557         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1558                                                      rq->base.mqp.qpn;
1559         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1560         if (err)
1561                 goto err_destroy_tir;
1562
1563         return 0;
1564
1565 err_destroy_tir:
1566         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1567 err_destroy_rq:
1568         destroy_raw_packet_qp_rq(dev, rq);
1569 err_destroy_sq:
1570         if (!qp->sq.wqe_cnt)
1571                 return err;
1572         destroy_raw_packet_qp_sq(dev, sq);
1573 err_destroy_tis:
1574         destroy_raw_packet_qp_tis(dev, sq, pd);
1575
1576         return err;
1577 }
1578
1579 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1580                                   struct mlx5_ib_qp *qp)
1581 {
1582         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1583         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1584         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1585
1586         if (qp->rq.wqe_cnt) {
1587                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1588                 destroy_raw_packet_qp_rq(dev, rq);
1589         }
1590
1591         if (qp->sq.wqe_cnt) {
1592                 destroy_raw_packet_qp_sq(dev, sq);
1593                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1594         }
1595 }
1596
1597 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1598                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1599 {
1600         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1601         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1602
1603         sq->sq = &qp->sq;
1604         rq->rq = &qp->rq;
1605         sq->doorbell = &qp->db;
1606         rq->doorbell = &qp->db;
1607 }
1608
1609 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1610 {
1611         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1612                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1613                 mlx5_ib_disable_lb(dev, false, true);
1614         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1615                              to_mpd(qp->ibqp.pd)->uid);
1616 }
1617
1618 static int create_rss_raw_qp_tir(struct ib_pd *pd, struct mlx5_ib_qp *qp,
1619                                  struct ib_qp_init_attr *init_attr,
1620                                  struct mlx5_ib_create_qp_rss *ucmd,
1621                                  struct ib_udata *udata)
1622 {
1623         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1624                 udata, struct mlx5_ib_ucontext, ibucontext);
1625         struct mlx5_ib_dev *dev = to_mdev(pd->device);
1626         struct mlx5_ib_create_qp_resp resp = {};
1627         int inlen;
1628         int outlen;
1629         int err;
1630         u32 *in;
1631         u32 *out;
1632         void *tirc;
1633         void *hfso;
1634         u32 selected_fields = 0;
1635         u32 outer_l4;
1636         size_t min_resp_len;
1637         u32 tdn = mucontext->tdn;
1638         u8 lb_flag = 0;
1639
1640         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1641         if (udata->outlen < min_resp_len)
1642                 return -EINVAL;
1643
1644         if (ucmd->comp_mask) {
1645                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1646                 return -EOPNOTSUPP;
1647         }
1648
1649         if (ucmd->flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1650                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1651                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1652                 mlx5_ib_dbg(dev, "invalid flags\n");
1653                 return -EOPNOTSUPP;
1654         }
1655
1656         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1657             !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1658                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1659                 return -EOPNOTSUPP;
1660         }
1661
1662         if (dev->is_rep)
1663                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1664
1665         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1666                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1667
1668         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1669                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1670
1671         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1672         if (err) {
1673                 mlx5_ib_dbg(dev, "copy failed\n");
1674                 return -EINVAL;
1675         }
1676
1677         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1678         outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1679         in = kvzalloc(inlen + outlen, GFP_KERNEL);
1680         if (!in)
1681                 return -ENOMEM;
1682
1683         out = in + MLX5_ST_SZ_DW(create_tir_in);
1684         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1685         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1686         MLX5_SET(tirc, tirc, disp_type,
1687                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1688         MLX5_SET(tirc, tirc, indirect_table,
1689                  init_attr->rwq_ind_tbl->ind_tbl_num);
1690         MLX5_SET(tirc, tirc, transport_domain, tdn);
1691
1692         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1693
1694         if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1695                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1696
1697         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1698
1699         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1700                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1701         else
1702                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1703
1704         switch (ucmd->rx_hash_function) {
1705         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1706         {
1707                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1708                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1709
1710                 if (len != ucmd->rx_key_len) {
1711                         err = -EINVAL;
1712                         goto err;
1713                 }
1714
1715                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1716                 memcpy(rss_key, ucmd->rx_hash_key, len);
1717                 break;
1718         }
1719         default:
1720                 err = -EOPNOTSUPP;
1721                 goto err;
1722         }
1723
1724         if (!ucmd->rx_hash_fields_mask) {
1725                 /* special case when this TIR serves as steering entry without hashing */
1726                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1727                         goto create_tir;
1728                 err = -EINVAL;
1729                 goto err;
1730         }
1731
1732         if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1733              (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1734              ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1735              (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1736                 err = -EINVAL;
1737                 goto err;
1738         }
1739
1740         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1741         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1742             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1743                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1744                          MLX5_L3_PROT_TYPE_IPV4);
1745         else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1746                  (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1747                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1748                          MLX5_L3_PROT_TYPE_IPV6);
1749
1750         outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1751                     (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1752                            << 0 |
1753                    ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1754                     (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1755                            << 1 |
1756                    (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1757
1758         /* Check that only one l4 protocol is set */
1759         if (outer_l4 & (outer_l4 - 1)) {
1760                 err = -EINVAL;
1761                 goto err;
1762         }
1763
1764         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1765         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1766             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1767                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1768                          MLX5_L4_PROT_TYPE_TCP);
1769         else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1770                  (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1771                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1772                          MLX5_L4_PROT_TYPE_UDP);
1773
1774         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1775             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1776                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1777
1778         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1779             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1780                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1781
1782         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1783             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1784                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1785
1786         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1787             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1788                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1789
1790         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1791                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1792
1793         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1794
1795 create_tir:
1796         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1797         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1798
1799         qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1800         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1801                 err = mlx5_ib_enable_lb(dev, false, true);
1802
1803                 if (err)
1804                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1805                                              to_mpd(pd)->uid);
1806         }
1807
1808         if (err)
1809                 goto err;
1810
1811         if (mucontext->devx_uid) {
1812                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1813                 resp.tirn = qp->rss_qp.tirn;
1814                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1815                         resp.tir_icm_addr =
1816                                 MLX5_GET(create_tir_out, out, icm_address_31_0);
1817                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1818                                                            icm_address_39_32)
1819                                              << 32;
1820                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1821                                                            icm_address_63_40)
1822                                              << 40;
1823                         resp.comp_mask |=
1824                                 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1825                 }
1826         }
1827
1828         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1829         if (err)
1830                 goto err_copy;
1831
1832         kvfree(in);
1833         /* qpn is reserved for that QP */
1834         qp->trans_qp.base.mqp.qpn = 0;
1835         qp->is_rss = true;
1836         return 0;
1837
1838 err_copy:
1839         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1840 err:
1841         kvfree(in);
1842         return err;
1843 }
1844
1845 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1846                                          struct ib_qp_init_attr *init_attr,
1847                                          struct mlx5_ib_create_qp *ucmd,
1848                                          void *qpc)
1849 {
1850         int scqe_sz;
1851         bool allow_scat_cqe = false;
1852
1853         if (ucmd)
1854                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1855
1856         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1857                 return;
1858
1859         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1860         if (scqe_sz == 128) {
1861                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1862                 return;
1863         }
1864
1865         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1866             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1867                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1868 }
1869
1870 static int atomic_size_to_mode(int size_mask)
1871 {
1872         /* driver does not support atomic_size > 256B
1873          * and does not know how to translate bigger sizes
1874          */
1875         int supported_size_mask = size_mask & 0x1ff;
1876         int log_max_size;
1877
1878         if (!supported_size_mask)
1879                 return -EOPNOTSUPP;
1880
1881         log_max_size = __fls(supported_size_mask);
1882
1883         if (log_max_size > 3)
1884                 return log_max_size;
1885
1886         return MLX5_ATOMIC_MODE_8B;
1887 }
1888
1889 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1890                            enum ib_qp_type qp_type)
1891 {
1892         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1893         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1894         int atomic_mode = -EOPNOTSUPP;
1895         int atomic_size_mask;
1896
1897         if (!atomic)
1898                 return -EOPNOTSUPP;
1899
1900         if (qp_type == MLX5_IB_QPT_DCT)
1901                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1902         else
1903                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1904
1905         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1906             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1907                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1908
1909         if (atomic_mode <= 0 &&
1910             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1911              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1912                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1913
1914         return atomic_mode;
1915 }
1916
1917 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1918                             struct ib_qp_init_attr *init_attr,
1919                             struct mlx5_ib_create_qp *ucmd,
1920                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1921 {
1922         struct mlx5_ib_resources *devr = &dev->devr;
1923         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1924         struct mlx5_core_dev *mdev = dev->mdev;
1925         struct mlx5_ib_create_qp_resp resp = {};
1926         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
1927                 udata, struct mlx5_ib_ucontext, ibucontext);
1928         struct mlx5_ib_cq *send_cq;
1929         struct mlx5_ib_cq *recv_cq;
1930         unsigned long flags;
1931         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1932         struct mlx5_ib_qp_base *base;
1933         int mlx5_st;
1934         void *qpc;
1935         u32 *in;
1936         int err;
1937
1938         mutex_init(&qp->mutex);
1939         spin_lock_init(&qp->sq.lock);
1940         spin_lock_init(&qp->rq.lock);
1941
1942         mlx5_st = to_mlx5_st(qp->type);
1943         if (mlx5_st < 0)
1944                 return -EINVAL;
1945
1946         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1947                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1948
1949         if (udata) {
1950                 err = get_qp_user_index(ucontext, ucmd, udata->inlen, &uidx);
1951                 if (err)
1952                         return err;
1953         }
1954
1955         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1956                 qp->underlay_qpn = init_attr->source_qpn;
1957
1958         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1959                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
1960                &qp->raw_packet_qp.rq.base :
1961                &qp->trans_qp.base;
1962
1963         qp->has_rq = qp_has_rq(init_attr);
1964         err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
1965         if (err) {
1966                 mlx5_ib_dbg(dev, "err %d\n", err);
1967                 return err;
1968         }
1969
1970         if (pd) {
1971                 if (udata) {
1972                         __u32 max_wqes =
1973                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1974                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n",
1975                                     ucmd->sq_wqe_count);
1976                         if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
1977                             ucmd->rq_wqe_count != qp->rq.wqe_cnt) {
1978                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1979                                 return -EINVAL;
1980                         }
1981                         if (ucmd->sq_wqe_count > max_wqes) {
1982                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1983                                             ucmd->sq_wqe_count, max_wqes);
1984                                 return -EINVAL;
1985                         }
1986                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1987                                              &resp, &inlen, base, ucmd);
1988                         if (err)
1989                                 mlx5_ib_dbg(dev, "err %d\n", err);
1990                 } else {
1991                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1992                                                base);
1993                         if (err)
1994                                 mlx5_ib_dbg(dev, "err %d\n", err);
1995                 }
1996
1997                 if (err)
1998                         return err;
1999         } else {
2000                 in = kvzalloc(inlen, GFP_KERNEL);
2001                 if (!in)
2002                         return -ENOMEM;
2003
2004                 qp->create_type = MLX5_QP_EMPTY;
2005         }
2006
2007         if (is_sqp(init_attr->qp_type))
2008                 qp->port = init_attr->port_num;
2009
2010         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2011
2012         MLX5_SET(qpc, qpc, st, mlx5_st);
2013         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2014
2015         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2016                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2017         else
2018                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2019
2020
2021         if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
2022                 MLX5_SET(qpc, qpc, wq_signature, 1);
2023
2024         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2025                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2026
2027         if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
2028                 MLX5_SET(qpc, qpc, cd_master, 1);
2029         if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
2030                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2031         if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
2032                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2033         if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
2034                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2035         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2036             (init_attr->qp_type == IB_QPT_RC ||
2037              init_attr->qp_type == IB_QPT_UC)) {
2038                 int rcqe_sz = rcqe_sz =
2039                         mlx5_ib_get_cqe_size(init_attr->recv_cq);
2040
2041                 MLX5_SET(qpc, qpc, cs_res,
2042                          rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2043                                           MLX5_RES_SCAT_DATA32_CQE);
2044         }
2045         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2046             (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
2047                 configure_requester_scat_cqe(dev, init_attr, ucmd, qpc);
2048
2049         if (qp->rq.wqe_cnt) {
2050                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2051                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2052         }
2053
2054         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2055
2056         if (qp->sq.wqe_cnt) {
2057                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2058         } else {
2059                 MLX5_SET(qpc, qpc, no_sq, 1);
2060                 if (init_attr->srq &&
2061                     init_attr->srq->srq_type == IB_SRQT_TM)
2062                         MLX5_SET(qpc, qpc, offload_type,
2063                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2064         }
2065
2066         /* Set default resources */
2067         switch (init_attr->qp_type) {
2068         case IB_QPT_XRC_TGT:
2069                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2070                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2071                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2072                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2073                 break;
2074         case IB_QPT_XRC_INI:
2075                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2076                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2077                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2078                 break;
2079         default:
2080                 if (init_attr->srq) {
2081                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2082                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2083                 } else {
2084                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2085                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2086                 }
2087         }
2088
2089         if (init_attr->send_cq)
2090                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2091
2092         if (init_attr->recv_cq)
2093                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2094
2095         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2096
2097         /* 0xffffff means we ask to work with cqe version 0 */
2098         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2099                 MLX5_SET(qpc, qpc, user_index, uidx);
2100
2101         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2102         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2103                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2104
2105         if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2106             init_attr->qp_type != IB_QPT_RAW_PACKET) {
2107                 MLX5_SET(qpc, qpc, end_padding_mode,
2108                          MLX5_WQ_END_PAD_MODE_ALIGN);
2109                 /* Special case to clean flag */
2110                 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
2111         }
2112
2113         if (inlen < 0) {
2114                 err = -EINVAL;
2115                 goto err;
2116         }
2117
2118         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2119             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2120                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
2121                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2122                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2123                                            &resp);
2124         } else {
2125                 err = mlx5_core_create_qp(dev, &base->mqp, in, inlen);
2126         }
2127
2128         if (err) {
2129                 mlx5_ib_dbg(dev, "create qp failed\n");
2130                 goto err_create;
2131         }
2132
2133         kvfree(in);
2134
2135         base->container_mibqp = qp;
2136         base->mqp.event = mlx5_ib_qp_event;
2137
2138         get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
2139                 &send_cq, &recv_cq);
2140         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2141         mlx5_ib_lock_cqs(send_cq, recv_cq);
2142         /* Maintain device to QPs access, needed for further handling via reset
2143          * flow
2144          */
2145         list_add_tail(&qp->qps_list, &dev->qp_list);
2146         /* Maintain CQ to QPs access, needed for further handling via reset flow
2147          */
2148         if (send_cq)
2149                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2150         if (recv_cq)
2151                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2152         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2153         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2154
2155         return 0;
2156
2157 err_create:
2158         if (qp->create_type == MLX5_QP_USER)
2159                 destroy_qp_user(dev, pd, qp, base, udata);
2160         else if (qp->create_type == MLX5_QP_KERNEL)
2161                 destroy_qp_kernel(dev, qp);
2162
2163 err:
2164         kvfree(in);
2165         return err;
2166 }
2167
2168 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2169         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2170 {
2171         if (send_cq) {
2172                 if (recv_cq) {
2173                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2174                                 spin_lock(&send_cq->lock);
2175                                 spin_lock_nested(&recv_cq->lock,
2176                                                  SINGLE_DEPTH_NESTING);
2177                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2178                                 spin_lock(&send_cq->lock);
2179                                 __acquire(&recv_cq->lock);
2180                         } else {
2181                                 spin_lock(&recv_cq->lock);
2182                                 spin_lock_nested(&send_cq->lock,
2183                                                  SINGLE_DEPTH_NESTING);
2184                         }
2185                 } else {
2186                         spin_lock(&send_cq->lock);
2187                         __acquire(&recv_cq->lock);
2188                 }
2189         } else if (recv_cq) {
2190                 spin_lock(&recv_cq->lock);
2191                 __acquire(&send_cq->lock);
2192         } else {
2193                 __acquire(&send_cq->lock);
2194                 __acquire(&recv_cq->lock);
2195         }
2196 }
2197
2198 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2199         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2200 {
2201         if (send_cq) {
2202                 if (recv_cq) {
2203                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2204                                 spin_unlock(&recv_cq->lock);
2205                                 spin_unlock(&send_cq->lock);
2206                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2207                                 __release(&recv_cq->lock);
2208                                 spin_unlock(&send_cq->lock);
2209                         } else {
2210                                 spin_unlock(&send_cq->lock);
2211                                 spin_unlock(&recv_cq->lock);
2212                         }
2213                 } else {
2214                         __release(&recv_cq->lock);
2215                         spin_unlock(&send_cq->lock);
2216                 }
2217         } else if (recv_cq) {
2218                 __release(&send_cq->lock);
2219                 spin_unlock(&recv_cq->lock);
2220         } else {
2221                 __release(&recv_cq->lock);
2222                 __release(&send_cq->lock);
2223         }
2224 }
2225
2226 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2227 {
2228         return to_mpd(qp->ibqp.pd);
2229 }
2230
2231 static void get_cqs(enum ib_qp_type qp_type,
2232                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2233                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2234 {
2235         switch (qp_type) {
2236         case IB_QPT_XRC_TGT:
2237                 *send_cq = NULL;
2238                 *recv_cq = NULL;
2239                 break;
2240         case MLX5_IB_QPT_REG_UMR:
2241         case IB_QPT_XRC_INI:
2242                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2243                 *recv_cq = NULL;
2244                 break;
2245
2246         case IB_QPT_SMI:
2247         case MLX5_IB_QPT_HW_GSI:
2248         case IB_QPT_RC:
2249         case IB_QPT_UC:
2250         case IB_QPT_UD:
2251         case IB_QPT_RAW_PACKET:
2252                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2253                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2254                 break;
2255         default:
2256                 *send_cq = NULL;
2257                 *recv_cq = NULL;
2258                 break;
2259         }
2260 }
2261
2262 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2263                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2264                                 u8 lag_tx_affinity);
2265
2266 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2267                               struct ib_udata *udata)
2268 {
2269         struct mlx5_ib_cq *send_cq, *recv_cq;
2270         struct mlx5_ib_qp_base *base;
2271         unsigned long flags;
2272         int err;
2273
2274         if (qp->ibqp.rwq_ind_tbl) {
2275                 destroy_rss_raw_qp_tir(dev, qp);
2276                 return;
2277         }
2278
2279         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2280                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
2281                &qp->raw_packet_qp.rq.base :
2282                &qp->trans_qp.base;
2283
2284         if (qp->state != IB_QPS_RESET) {
2285                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2286                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
2287                         err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
2288                                                   NULL, &base->mqp);
2289                 } else {
2290                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2291                                 .operation = MLX5_CMD_OP_2RST_QP
2292                         };
2293
2294                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2295                 }
2296                 if (err)
2297                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2298                                      base->mqp.qpn);
2299         }
2300
2301         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2302                 &send_cq, &recv_cq);
2303
2304         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2305         mlx5_ib_lock_cqs(send_cq, recv_cq);
2306         /* del from lists under both locks above to protect reset flow paths */
2307         list_del(&qp->qps_list);
2308         if (send_cq)
2309                 list_del(&qp->cq_send_list);
2310
2311         if (recv_cq)
2312                 list_del(&qp->cq_recv_list);
2313
2314         if (qp->create_type == MLX5_QP_KERNEL) {
2315                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2316                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2317                 if (send_cq != recv_cq)
2318                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2319                                            NULL);
2320         }
2321         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2322         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2323
2324         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2325             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2326                 destroy_raw_packet_qp(dev, qp);
2327         } else {
2328                 err = mlx5_core_destroy_qp(dev, &base->mqp);
2329                 if (err)
2330                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2331                                      base->mqp.qpn);
2332         }
2333
2334         if (qp->create_type == MLX5_QP_KERNEL)
2335                 destroy_qp_kernel(dev, qp);
2336         else if (qp->create_type == MLX5_QP_USER)
2337                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
2338 }
2339
2340 static int create_dct(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2341                       struct ib_qp_init_attr *attr,
2342                       struct mlx5_ib_create_qp *ucmd, struct ib_udata *udata)
2343 {
2344         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2345                 udata, struct mlx5_ib_ucontext, ibucontext);
2346         int err = 0;
2347         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2348         void *dctc;
2349
2350         err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx);
2351         if (err)
2352                 return err;
2353
2354         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2355         if (!qp->dct.in)
2356                 return -ENOMEM;
2357
2358         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2359         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2360         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2361         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2362         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2363         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2364         MLX5_SET(dctc, dctc, user_index, uidx);
2365
2366         if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
2367                 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2368
2369                 if (rcqe_sz == 128)
2370                         MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2371         }
2372
2373         qp->state = IB_QPS_RESET;
2374
2375         return 0;
2376 }
2377
2378 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2379                          enum ib_qp_type *type)
2380 {
2381         if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2382                 goto out;
2383
2384         switch (attr->qp_type) {
2385         case IB_QPT_XRC_TGT:
2386         case IB_QPT_XRC_INI:
2387                 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2388                         goto out;
2389                 fallthrough;
2390         case IB_QPT_RAW_PACKET:
2391         case IB_QPT_RC:
2392         case IB_QPT_UC:
2393         case IB_QPT_UD:
2394         case IB_QPT_SMI:
2395         case MLX5_IB_QPT_HW_GSI:
2396         case MLX5_IB_QPT_REG_UMR:
2397         case IB_QPT_DRIVER:
2398         case IB_QPT_GSI:
2399                 break;
2400         default:
2401                 goto out;
2402         }
2403
2404         *type = attr->qp_type;
2405         return 0;
2406
2407 out:
2408         mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2409         return -EOPNOTSUPP;
2410 }
2411
2412 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2413                             struct ib_qp_init_attr *attr,
2414                             struct ib_udata *udata)
2415 {
2416         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2417                 udata, struct mlx5_ib_ucontext, ibucontext);
2418
2419         if (!udata) {
2420                 /* Kernel create_qp callers */
2421                 if (attr->rwq_ind_tbl)
2422                         return -EOPNOTSUPP;
2423
2424                 switch (attr->qp_type) {
2425                 case IB_QPT_RAW_PACKET:
2426                 case IB_QPT_DRIVER:
2427                         return -EOPNOTSUPP;
2428                 default:
2429                         return 0;
2430                 }
2431         }
2432
2433         /* Userspace create_qp callers */
2434         if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2435                 mlx5_ib_dbg(dev,
2436                         "Raw Packet QP is only supported for CQE version > 0\n");
2437                 return -EINVAL;
2438         }
2439
2440         if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2441                 mlx5_ib_dbg(dev,
2442                             "Wrong QP type %d for the RWQ indirect table\n",
2443                             attr->qp_type);
2444                 return -EINVAL;
2445         }
2446
2447         switch (attr->qp_type) {
2448         case IB_QPT_SMI:
2449         case MLX5_IB_QPT_HW_GSI:
2450         case MLX5_IB_QPT_REG_UMR:
2451         case IB_QPT_GSI:
2452                 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2453                             attr->qp_type);
2454                 return -EINVAL;
2455         default:
2456                 break;
2457         }
2458
2459         /*
2460          * We don't need to see this warning, it means that kernel code
2461          * missing ib_pd. Placed here to catch developer's mistakes.
2462          */
2463         WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2464                   "There is a missing PD pointer assignment\n");
2465         return 0;
2466 }
2467
2468 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2469                                 bool cond, struct mlx5_ib_qp *qp)
2470 {
2471         if (!(*flags & flag))
2472                 return;
2473
2474         if (cond) {
2475                 qp->flags_en |= flag;
2476                 *flags &= ~flag;
2477                 return;
2478         }
2479
2480         if (flag == MLX5_QP_FLAG_SCATTER_CQE) {
2481                 /*
2482                  * We don't return error if this flag was provided,
2483                  * and mlx5 doesn't have right capability.
2484                  */
2485                 *flags &= ~MLX5_QP_FLAG_SCATTER_CQE;
2486                 return;
2487         }
2488         mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2489 }
2490
2491 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2492                                 void *ucmd, struct ib_qp_init_attr *attr)
2493 {
2494         struct mlx5_core_dev *mdev = dev->mdev;
2495         bool cond;
2496         int flags;
2497
2498         if (attr->rwq_ind_tbl)
2499                 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2500         else
2501                 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
2502
2503         switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2504         case MLX5_QP_FLAG_TYPE_DCI:
2505                 qp->type = MLX5_IB_QPT_DCI;
2506                 break;
2507         case MLX5_QP_FLAG_TYPE_DCT:
2508                 qp->type = MLX5_IB_QPT_DCT;
2509                 break;
2510         default:
2511                 if (qp->type != IB_QPT_DRIVER)
2512                         break;
2513                 /*
2514                  * It is IB_QPT_DRIVER and or no subtype or
2515                  * wrong subtype were provided.
2516                  */
2517                 return -EINVAL;
2518         }
2519
2520         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2521         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2522
2523         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2524         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2525                             MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2526
2527         if (qp->type == IB_QPT_RAW_PACKET) {
2528                 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2529                        MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2530                        MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2531                 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2532                                     cond, qp);
2533                 process_vendor_flag(dev, &flags,
2534                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2535                                     qp);
2536                 process_vendor_flag(dev, &flags,
2537                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2538                                     qp);
2539         }
2540
2541         if (qp->type == IB_QPT_RC)
2542                 process_vendor_flag(dev, &flags,
2543                                     MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2544                                     MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2545
2546         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2547         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2548
2549         if (flags)
2550                 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2551
2552         return (flags) ? -EINVAL : 0;
2553 }
2554
2555 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2556                                 bool cond, struct mlx5_ib_qp *qp)
2557 {
2558         if (!(*flags & flag))
2559                 return;
2560
2561         if (cond) {
2562                 qp->flags |= flag;
2563                 *flags &= ~flag;
2564                 return;
2565         }
2566
2567         if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2568                 /*
2569                  * Special case, if condition didn't meet, it won't be error,
2570                  * just different in-kernel flow.
2571                  */
2572                 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2573                 return;
2574         }
2575         mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2576 }
2577
2578 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2579                                 struct ib_qp_init_attr *attr)
2580 {
2581         enum ib_qp_type qp_type = qp->type;
2582         struct mlx5_core_dev *mdev = dev->mdev;
2583         int create_flags = attr->create_flags;
2584         bool cond;
2585
2586         if (qp_type == MLX5_IB_QPT_DCT)
2587                 return (create_flags) ? -EINVAL : 0;
2588
2589         if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2590                 return (create_flags) ? -EINVAL : 0;
2591
2592         process_create_flag(dev, &create_flags,
2593                             IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2594                             MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2595         process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2596                             MLX5_CAP_GEN(mdev, cd), qp);
2597         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2598                             MLX5_CAP_GEN(mdev, cd), qp);
2599         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2600                             MLX5_CAP_GEN(mdev, cd), qp);
2601
2602         if (qp_type == IB_QPT_UD) {
2603                 process_create_flag(dev, &create_flags,
2604                                     IB_QP_CREATE_IPOIB_UD_LSO,
2605                                     MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2606                                     qp);
2607                 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2608                 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2609                                     cond, qp);
2610         }
2611
2612         if (qp_type == IB_QPT_RAW_PACKET) {
2613                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2614                        MLX5_CAP_ETH(mdev, scatter_fcs);
2615                 process_create_flag(dev, &create_flags,
2616                                     IB_QP_CREATE_SCATTER_FCS, cond, qp);
2617
2618                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2619                        MLX5_CAP_ETH(mdev, vlan_cap);
2620                 process_create_flag(dev, &create_flags,
2621                                     IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2622         }
2623
2624         process_create_flag(dev, &create_flags,
2625                             IB_QP_CREATE_PCI_WRITE_END_PADDING,
2626                             MLX5_CAP_GEN(mdev, end_pad), qp);
2627
2628         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2629                             qp_type != MLX5_IB_QPT_REG_UMR, qp);
2630         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2631                             true, qp);
2632
2633         if (create_flags)
2634                 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2635                             create_flags);
2636
2637         return (create_flags) ? -EINVAL : 0;
2638 }
2639
2640 static size_t process_udata_size(struct ib_qp_init_attr *attr,
2641                                  struct ib_udata *udata)
2642 {
2643         size_t ucmd = sizeof(struct mlx5_ib_create_qp);
2644         size_t inlen = udata->inlen;
2645
2646         if (attr->qp_type == IB_QPT_DRIVER)
2647                 return (inlen < ucmd) ? 0 : ucmd;
2648
2649         if (!attr->rwq_ind_tbl)
2650                 return ucmd;
2651
2652         if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
2653                 return 0;
2654
2655         ucmd = sizeof(struct mlx5_ib_create_qp_rss);
2656         if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
2657                 return 0;
2658
2659         return min(ucmd, inlen);
2660 }
2661
2662 static int create_raw_qp(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2663                          struct ib_qp_init_attr *attr, void *ucmd,
2664                          struct ib_udata *udata)
2665 {
2666         struct mlx5_ib_dev *dev = to_mdev(pd->device);
2667
2668         if (attr->rwq_ind_tbl)
2669                 return create_rss_raw_qp_tir(pd, qp, attr, ucmd, udata);
2670
2671         return create_qp_common(dev, pd, attr, ucmd, udata, qp);
2672 }
2673
2674 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2675                          struct ib_qp_init_attr *attr)
2676 {
2677         int ret = 0;
2678
2679         switch (qp->type) {
2680         case MLX5_IB_QPT_DCT:
2681                 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2682                 break;
2683         case MLX5_IB_QPT_DCI:
2684                 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2685                               -EINVAL :
2686                               0;
2687                 break;
2688         case IB_QPT_RAW_PACKET:
2689                 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2690                 break;
2691         default:
2692                 break;
2693         }
2694
2695         if (ret)
2696                 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2697
2698         return ret;
2699 }
2700
2701 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2702                                 struct ib_qp_init_attr *init_attr,
2703                                 struct ib_udata *udata)
2704 {
2705         struct mlx5_ib_dev *dev;
2706         struct mlx5_ib_qp *qp;
2707         enum ib_qp_type type;
2708         void *ucmd = NULL;
2709         u16 xrcdn = 0;
2710         int err;
2711
2712         dev = pd ? to_mdev(pd->device) :
2713                    to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2714
2715         err = check_qp_type(dev, init_attr, &type);
2716         if (err) {
2717                 mlx5_ib_dbg(dev, "Unsupported QP type %d\n",
2718                             init_attr->qp_type);
2719                 return ERR_PTR(err);
2720         }
2721
2722         err = check_valid_flow(dev, pd, init_attr, udata);
2723         if (err)
2724                 return ERR_PTR(err);
2725
2726         if (init_attr->qp_type == IB_QPT_GSI)
2727                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2728
2729         if (udata) {
2730                 size_t inlen =
2731                         process_udata_size(init_attr, udata);
2732
2733                 if (!inlen)
2734                         return ERR_PTR(-EINVAL);
2735
2736                 ucmd = kzalloc(inlen, GFP_KERNEL);
2737                 if (!ucmd)
2738                         return ERR_PTR(-ENOMEM);
2739
2740                 err = ib_copy_from_udata(ucmd, udata, inlen);
2741                 if (err)
2742                         goto free_ucmd;
2743         }
2744
2745         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2746         if (!qp) {
2747                 err = -ENOMEM;
2748                 goto free_ucmd;
2749         }
2750
2751         qp->type = type;
2752         if (udata) {
2753                 err = process_vendor_flags(dev, qp, ucmd, init_attr);
2754                 if (err)
2755                         goto free_qp;
2756         }
2757         err = process_create_flags(dev, qp, init_attr);
2758         if (err)
2759                 goto free_qp;
2760
2761         if (qp->type == IB_QPT_XRC_TGT)
2762                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2763
2764         err = check_qp_attr(dev, qp, init_attr);
2765         if (err)
2766                 goto free_qp;
2767
2768         switch (qp->type) {
2769         case IB_QPT_RAW_PACKET:
2770                 err = create_raw_qp(pd, qp, init_attr, ucmd, udata);
2771                 break;
2772         case MLX5_IB_QPT_DCT:
2773                 err = create_dct(pd, qp, init_attr, ucmd, udata);
2774                 break;
2775         default:
2776                 err = create_qp_common(dev, pd, init_attr, ucmd, udata, qp);
2777         }
2778         if (err) {
2779                 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2780                 goto free_qp;
2781         }
2782
2783         kfree(ucmd);
2784
2785         if (is_qp0(init_attr->qp_type))
2786                 qp->ibqp.qp_num = 0;
2787         else if (is_qp1(init_attr->qp_type))
2788                 qp->ibqp.qp_num = 1;
2789         else
2790                 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2791
2792         qp->trans_qp.xrcdn = xrcdn;
2793
2794         return &qp->ibqp;
2795
2796 free_qp:
2797         kfree(qp);
2798 free_ucmd:
2799         kfree(ucmd);
2800         return ERR_PTR(err);
2801 }
2802
2803 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2804 {
2805         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2806
2807         if (mqp->state == IB_QPS_RTR) {
2808                 int err;
2809
2810                 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2811                 if (err) {
2812                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2813                         return err;
2814                 }
2815         }
2816
2817         kfree(mqp->dct.in);
2818         kfree(mqp);
2819         return 0;
2820 }
2821
2822 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
2823 {
2824         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2825         struct mlx5_ib_qp *mqp = to_mqp(qp);
2826
2827         if (unlikely(qp->qp_type == IB_QPT_GSI))
2828                 return mlx5_ib_gsi_destroy_qp(qp);
2829
2830         if (mqp->type == MLX5_IB_QPT_DCT)
2831                 return mlx5_ib_destroy_dct(mqp);
2832
2833         destroy_qp_common(dev, mqp, udata);
2834
2835         kfree(mqp);
2836
2837         return 0;
2838 }
2839
2840 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2841                                 const struct ib_qp_attr *attr,
2842                                 int attr_mask, __be32 *hw_access_flags_be)
2843 {
2844         u8 dest_rd_atomic;
2845         u32 access_flags, hw_access_flags = 0;
2846
2847         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2848
2849         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2850                 dest_rd_atomic = attr->max_dest_rd_atomic;
2851         else
2852                 dest_rd_atomic = qp->trans_qp.resp_depth;
2853
2854         if (attr_mask & IB_QP_ACCESS_FLAGS)
2855                 access_flags = attr->qp_access_flags;
2856         else
2857                 access_flags = qp->trans_qp.atomic_rd_en;
2858
2859         if (!dest_rd_atomic)
2860                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2861
2862         if (access_flags & IB_ACCESS_REMOTE_READ)
2863                 hw_access_flags |= MLX5_QP_BIT_RRE;
2864         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2865                 int atomic_mode;
2866
2867                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2868                 if (atomic_mode < 0)
2869                         return -EOPNOTSUPP;
2870
2871                 hw_access_flags |= MLX5_QP_BIT_RAE;
2872                 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2873         }
2874
2875         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2876                 hw_access_flags |= MLX5_QP_BIT_RWE;
2877
2878         *hw_access_flags_be = cpu_to_be32(hw_access_flags);
2879
2880         return 0;
2881 }
2882
2883 enum {
2884         MLX5_PATH_FLAG_FL       = 1 << 0,
2885         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2886         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2887 };
2888
2889 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2890 {
2891         if (rate == IB_RATE_PORT_CURRENT)
2892                 return 0;
2893
2894         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
2895                 return -EINVAL;
2896
2897         while (rate != IB_RATE_PORT_CURRENT &&
2898                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2899                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2900                 --rate;
2901
2902         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2903 }
2904
2905 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2906                                       struct mlx5_ib_sq *sq, u8 sl,
2907                                       struct ib_pd *pd)
2908 {
2909         void *in;
2910         void *tisc;
2911         int inlen;
2912         int err;
2913
2914         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2915         in = kvzalloc(inlen, GFP_KERNEL);
2916         if (!in)
2917                 return -ENOMEM;
2918
2919         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2920         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2921
2922         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2923         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2924
2925         err = mlx5_core_modify_tis(dev, sq->tisn, in);
2926
2927         kvfree(in);
2928
2929         return err;
2930 }
2931
2932 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2933                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2934                                          struct ib_pd *pd)
2935 {
2936         void *in;
2937         void *tisc;
2938         int inlen;
2939         int err;
2940
2941         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2942         in = kvzalloc(inlen, GFP_KERNEL);
2943         if (!in)
2944                 return -ENOMEM;
2945
2946         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2947         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2948
2949         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2950         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2951
2952         err = mlx5_core_modify_tis(dev, sq->tisn, in);
2953
2954         kvfree(in);
2955
2956         return err;
2957 }
2958
2959 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2960                          const struct rdma_ah_attr *ah,
2961                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2962                          u32 path_flags, const struct ib_qp_attr *attr,
2963                          bool alt)
2964 {
2965         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2966         int err;
2967         enum ib_gid_type gid_type;
2968         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2969         u8 sl = rdma_ah_get_sl(ah);
2970
2971         if (attr_mask & IB_QP_PKEY_INDEX)
2972                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2973                                                      attr->pkey_index);
2974
2975         if (ah_flags & IB_AH_GRH) {
2976                 if (grh->sgid_index >=
2977                     dev->mdev->port_caps[port - 1].gid_table_len) {
2978                         pr_err("sgid_index (%u) too large. max is %d\n",
2979                                grh->sgid_index,
2980                                dev->mdev->port_caps[port - 1].gid_table_len);
2981                         return -EINVAL;
2982                 }
2983         }
2984
2985         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2986                 if (!(ah_flags & IB_AH_GRH))
2987                         return -EINVAL;
2988
2989                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2990                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2991                     qp->ibqp.qp_type == IB_QPT_UC ||
2992                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2993                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2994                         path->udp_sport =
2995                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2996                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2997                 gid_type = ah->grh.sgid_attr->gid_type;
2998                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2999                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
3000         } else {
3001                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
3002                 path->fl_free_ar |=
3003                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
3004                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
3005                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
3006                 if (ah_flags & IB_AH_GRH)
3007                         path->grh_mlid  |= 1 << 7;
3008                 path->dci_cfi_prio_sl = sl & 0xf;
3009         }
3010
3011         if (ah_flags & IB_AH_GRH) {
3012                 path->mgid_index = grh->sgid_index;
3013                 path->hop_limit  = grh->hop_limit;
3014                 path->tclass_flowlabel =
3015                         cpu_to_be32((grh->traffic_class << 20) |
3016                                     (grh->flow_label));
3017                 memcpy(path->rgid, grh->dgid.raw, 16);
3018         }
3019
3020         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
3021         if (err < 0)
3022                 return err;
3023         path->static_rate = err;
3024         path->port = port;
3025
3026         if (attr_mask & IB_QP_TIMEOUT)
3027                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
3028
3029         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3030                 return modify_raw_packet_eth_prio(dev->mdev,
3031                                                   &qp->raw_packet_qp.sq,
3032                                                   sl & 0xf, qp->ibqp.pd);
3033
3034         return 0;
3035 }
3036
3037 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3038         [MLX5_QP_STATE_INIT] = {
3039                 [MLX5_QP_STATE_INIT] = {
3040                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3041                                           MLX5_QP_OPTPAR_RAE            |
3042                                           MLX5_QP_OPTPAR_RWE            |
3043                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3044                                           MLX5_QP_OPTPAR_PRI_PORT,
3045                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3046                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3047                                           MLX5_QP_OPTPAR_PRI_PORT,
3048                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3049                                           MLX5_QP_OPTPAR_Q_KEY          |
3050                                           MLX5_QP_OPTPAR_PRI_PORT,
3051                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3052                                           MLX5_QP_OPTPAR_RAE            |
3053                                           MLX5_QP_OPTPAR_RWE            |
3054                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3055                                           MLX5_QP_OPTPAR_PRI_PORT,
3056                 },
3057                 [MLX5_QP_STATE_RTR] = {
3058                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3059                                           MLX5_QP_OPTPAR_RRE            |
3060                                           MLX5_QP_OPTPAR_RAE            |
3061                                           MLX5_QP_OPTPAR_RWE            |
3062                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3063                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3064                                           MLX5_QP_OPTPAR_RWE            |
3065                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3066                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3067                                           MLX5_QP_OPTPAR_Q_KEY,
3068                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
3069                                            MLX5_QP_OPTPAR_Q_KEY,
3070                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3071                                           MLX5_QP_OPTPAR_RRE            |
3072                                           MLX5_QP_OPTPAR_RAE            |
3073                                           MLX5_QP_OPTPAR_RWE            |
3074                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3075                 },
3076         },
3077         [MLX5_QP_STATE_RTR] = {
3078                 [MLX5_QP_STATE_RTS] = {
3079                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3080                                           MLX5_QP_OPTPAR_RRE            |
3081                                           MLX5_QP_OPTPAR_RAE            |
3082                                           MLX5_QP_OPTPAR_RWE            |
3083                                           MLX5_QP_OPTPAR_PM_STATE       |
3084                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3085                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3086                                           MLX5_QP_OPTPAR_RWE            |
3087                                           MLX5_QP_OPTPAR_PM_STATE,
3088                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3089                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3090                                           MLX5_QP_OPTPAR_RRE            |
3091                                           MLX5_QP_OPTPAR_RAE            |
3092                                           MLX5_QP_OPTPAR_RWE            |
3093                                           MLX5_QP_OPTPAR_PM_STATE       |
3094                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3095                 },
3096         },
3097         [MLX5_QP_STATE_RTS] = {
3098                 [MLX5_QP_STATE_RTS] = {
3099                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3100                                           MLX5_QP_OPTPAR_RAE            |
3101                                           MLX5_QP_OPTPAR_RWE            |
3102                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3103                                           MLX5_QP_OPTPAR_PM_STATE       |
3104                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3105                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3106                                           MLX5_QP_OPTPAR_PM_STATE       |
3107                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3108                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3109                                           MLX5_QP_OPTPAR_SRQN           |
3110                                           MLX5_QP_OPTPAR_CQN_RCV,
3111                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3112                                           MLX5_QP_OPTPAR_RAE            |
3113                                           MLX5_QP_OPTPAR_RWE            |
3114                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3115                                           MLX5_QP_OPTPAR_PM_STATE       |
3116                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3117                 },
3118         },
3119         [MLX5_QP_STATE_SQER] = {
3120                 [MLX5_QP_STATE_RTS] = {
3121                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3122                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3123                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3124                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3125                                            MLX5_QP_OPTPAR_RWE           |
3126                                            MLX5_QP_OPTPAR_RAE           |
3127                                            MLX5_QP_OPTPAR_RRE,
3128                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
3129                                            MLX5_QP_OPTPAR_RWE           |
3130                                            MLX5_QP_OPTPAR_RAE           |
3131                                            MLX5_QP_OPTPAR_RRE,
3132                 },
3133         },
3134 };
3135
3136 static int ib_nr_to_mlx5_nr(int ib_mask)
3137 {
3138         switch (ib_mask) {
3139         case IB_QP_STATE:
3140                 return 0;
3141         case IB_QP_CUR_STATE:
3142                 return 0;
3143         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3144                 return 0;
3145         case IB_QP_ACCESS_FLAGS:
3146                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3147                         MLX5_QP_OPTPAR_RAE;
3148         case IB_QP_PKEY_INDEX:
3149                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3150         case IB_QP_PORT:
3151                 return MLX5_QP_OPTPAR_PRI_PORT;
3152         case IB_QP_QKEY:
3153                 return MLX5_QP_OPTPAR_Q_KEY;
3154         case IB_QP_AV:
3155                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3156                         MLX5_QP_OPTPAR_PRI_PORT;
3157         case IB_QP_PATH_MTU:
3158                 return 0;
3159         case IB_QP_TIMEOUT:
3160                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3161         case IB_QP_RETRY_CNT:
3162                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3163         case IB_QP_RNR_RETRY:
3164                 return MLX5_QP_OPTPAR_RNR_RETRY;
3165         case IB_QP_RQ_PSN:
3166                 return 0;
3167         case IB_QP_MAX_QP_RD_ATOMIC:
3168                 return MLX5_QP_OPTPAR_SRA_MAX;
3169         case IB_QP_ALT_PATH:
3170                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3171         case IB_QP_MIN_RNR_TIMER:
3172                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3173         case IB_QP_SQ_PSN:
3174                 return 0;
3175         case IB_QP_MAX_DEST_RD_ATOMIC:
3176                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3177                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3178         case IB_QP_PATH_MIG_STATE:
3179                 return MLX5_QP_OPTPAR_PM_STATE;
3180         case IB_QP_CAP:
3181                 return 0;
3182         case IB_QP_DEST_QPN:
3183                 return 0;
3184         }
3185         return 0;
3186 }
3187
3188 static int ib_mask_to_mlx5_opt(int ib_mask)
3189 {
3190         int result = 0;
3191         int i;
3192
3193         for (i = 0; i < 8 * sizeof(int); i++) {
3194                 if ((1 << i) & ib_mask)
3195                         result |= ib_nr_to_mlx5_nr(1 << i);
3196         }
3197
3198         return result;
3199 }
3200
3201 static int modify_raw_packet_qp_rq(
3202         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3203         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3204 {
3205         void *in;
3206         void *rqc;
3207         int inlen;
3208         int err;
3209
3210         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3211         in = kvzalloc(inlen, GFP_KERNEL);
3212         if (!in)
3213                 return -ENOMEM;
3214
3215         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3216         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3217
3218         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3219         MLX5_SET(rqc, rqc, state, new_state);
3220
3221         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3222                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3223                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3224                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3225                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3226                 } else
3227                         dev_info_once(
3228                                 &dev->ib_dev.dev,
3229                                 "RAW PACKET QP counters are not supported on current FW\n");
3230         }
3231
3232         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3233         if (err)
3234                 goto out;
3235
3236         rq->state = new_state;
3237
3238 out:
3239         kvfree(in);
3240         return err;
3241 }
3242
3243 static int modify_raw_packet_qp_sq(
3244         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3245         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3246 {
3247         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3248         struct mlx5_rate_limit old_rl = ibqp->rl;
3249         struct mlx5_rate_limit new_rl = old_rl;
3250         bool new_rate_added = false;
3251         u16 rl_index = 0;
3252         void *in;
3253         void *sqc;
3254         int inlen;
3255         int err;
3256
3257         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3258         in = kvzalloc(inlen, GFP_KERNEL);
3259         if (!in)
3260                 return -ENOMEM;
3261
3262         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3263         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3264
3265         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3266         MLX5_SET(sqc, sqc, state, new_state);
3267
3268         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3269                 if (new_state != MLX5_SQC_STATE_RDY)
3270                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3271                                 __func__);
3272                 else
3273                         new_rl = raw_qp_param->rl;
3274         }
3275
3276         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3277                 if (new_rl.rate) {
3278                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3279                         if (err) {
3280                                 pr_err("Failed configuring rate limit(err %d): \
3281                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3282                                        err, new_rl.rate, new_rl.max_burst_sz,
3283                                        new_rl.typical_pkt_sz);
3284
3285                                 goto out;
3286                         }
3287                         new_rate_added = true;
3288                 }
3289
3290                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3291                 /* index 0 means no limit */
3292                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3293         }
3294
3295         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
3296         if (err) {
3297                 /* Remove new rate from table if failed */
3298                 if (new_rate_added)
3299                         mlx5_rl_remove_rate(dev, &new_rl);
3300                 goto out;
3301         }
3302
3303         /* Only remove the old rate after new rate was set */
3304         if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3305             (new_state != MLX5_SQC_STATE_RDY)) {
3306                 mlx5_rl_remove_rate(dev, &old_rl);
3307                 if (new_state != MLX5_SQC_STATE_RDY)
3308                         memset(&new_rl, 0, sizeof(new_rl));
3309         }
3310
3311         ibqp->rl = new_rl;
3312         sq->state = new_state;
3313
3314 out:
3315         kvfree(in);
3316         return err;
3317 }
3318
3319 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3320                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3321                                 u8 tx_affinity)
3322 {
3323         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3324         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3325         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3326         int modify_rq = !!qp->rq.wqe_cnt;
3327         int modify_sq = !!qp->sq.wqe_cnt;
3328         int rq_state;
3329         int sq_state;
3330         int err;
3331
3332         switch (raw_qp_param->operation) {
3333         case MLX5_CMD_OP_RST2INIT_QP:
3334                 rq_state = MLX5_RQC_STATE_RDY;
3335                 sq_state = MLX5_SQC_STATE_RDY;
3336                 break;
3337         case MLX5_CMD_OP_2ERR_QP:
3338                 rq_state = MLX5_RQC_STATE_ERR;
3339                 sq_state = MLX5_SQC_STATE_ERR;
3340                 break;
3341         case MLX5_CMD_OP_2RST_QP:
3342                 rq_state = MLX5_RQC_STATE_RST;
3343                 sq_state = MLX5_SQC_STATE_RST;
3344                 break;
3345         case MLX5_CMD_OP_RTR2RTS_QP:
3346         case MLX5_CMD_OP_RTS2RTS_QP:
3347                 if (raw_qp_param->set_mask ==
3348                     MLX5_RAW_QP_RATE_LIMIT) {
3349                         modify_rq = 0;
3350                         sq_state = sq->state;
3351                 } else {
3352                         return raw_qp_param->set_mask ? -EINVAL : 0;
3353                 }
3354                 break;
3355         case MLX5_CMD_OP_INIT2INIT_QP:
3356         case MLX5_CMD_OP_INIT2RTR_QP:
3357                 if (raw_qp_param->set_mask)
3358                         return -EINVAL;
3359                 else
3360                         return 0;
3361         default:
3362                 WARN_ON(1);
3363                 return -EINVAL;
3364         }
3365
3366         if (modify_rq) {
3367                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3368                                                qp->ibqp.pd);
3369                 if (err)
3370                         return err;
3371         }
3372
3373         if (modify_sq) {
3374                 struct mlx5_flow_handle *flow_rule;
3375
3376                 if (tx_affinity) {
3377                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3378                                                             tx_affinity,
3379                                                             qp->ibqp.pd);
3380                         if (err)
3381                                 return err;
3382                 }
3383
3384                 flow_rule = create_flow_rule_vport_sq(dev, sq,
3385                                                       raw_qp_param->port);
3386                 if (IS_ERR(flow_rule))
3387                         return PTR_ERR(flow_rule);
3388
3389                 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3390                                               raw_qp_param, qp->ibqp.pd);
3391                 if (err) {
3392                         if (flow_rule)
3393                                 mlx5_del_flow_rules(flow_rule);
3394                         return err;
3395                 }
3396
3397                 if (flow_rule) {
3398                         destroy_flow_rule_vport_sq(sq);
3399                         sq->flow_rule = flow_rule;
3400                 }
3401
3402                 return err;
3403         }
3404
3405         return 0;
3406 }
3407
3408 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3409                                     struct mlx5_ib_pd *pd,
3410                                     struct mlx5_ib_qp_base *qp_base,
3411                                     u8 port_num, struct ib_udata *udata)
3412 {
3413         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3414                 udata, struct mlx5_ib_ucontext, ibucontext);
3415         unsigned int tx_port_affinity;
3416
3417         if (ucontext) {
3418                 tx_port_affinity = (unsigned int)atomic_add_return(
3419                                            1, &ucontext->tx_port_affinity) %
3420                                            MLX5_MAX_PORTS +
3421                                    1;
3422                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3423                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3424         } else {
3425                 tx_port_affinity =
3426                         (unsigned int)atomic_add_return(
3427                                 1, &dev->port[port_num].roce.tx_port_affinity) %
3428                                 MLX5_MAX_PORTS +
3429                         1;
3430                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3431                                 tx_port_affinity, qp_base->mqp.qpn);
3432         }
3433
3434         return tx_port_affinity;
3435 }
3436
3437 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3438                                     struct rdma_counter *counter)
3439 {
3440         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3441         struct mlx5_ib_qp *mqp = to_mqp(qp);
3442         struct mlx5_qp_context context = {};
3443         struct mlx5_ib_qp_base *base;
3444         u32 set_id;
3445
3446         if (counter)
3447                 set_id = counter->id;
3448         else
3449                 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3450
3451         base = &mqp->trans_qp.base;
3452         context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff);
3453         context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24);
3454         return mlx5_core_qp_modify(dev, MLX5_CMD_OP_RTS2RTS_QP,
3455                                    MLX5_QP_OPTPAR_COUNTER_SET_ID, &context,
3456                                    &base->mqp);
3457 }
3458
3459 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3460                                const struct ib_qp_attr *attr, int attr_mask,
3461                                enum ib_qp_state cur_state,
3462                                enum ib_qp_state new_state,
3463                                const struct mlx5_ib_modify_qp *ucmd,
3464                                struct ib_udata *udata)
3465 {
3466         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3467                 [MLX5_QP_STATE_RST] = {
3468                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3469                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3470                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3471                 },
3472                 [MLX5_QP_STATE_INIT]  = {
3473                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3474                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3475                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3476                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3477                 },
3478                 [MLX5_QP_STATE_RTR]   = {
3479                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3480                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3481                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3482                 },
3483                 [MLX5_QP_STATE_RTS]   = {
3484                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3485                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3486                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3487                 },
3488                 [MLX5_QP_STATE_SQD] = {
3489                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3490                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3491                 },
3492                 [MLX5_QP_STATE_SQER] = {
3493                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3494                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3495                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3496                 },
3497                 [MLX5_QP_STATE_ERR] = {
3498                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3499                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3500                 }
3501         };
3502
3503         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3504         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3505         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3506         struct mlx5_ib_cq *send_cq, *recv_cq;
3507         struct mlx5_qp_context *context;
3508         struct mlx5_ib_pd *pd;
3509         enum mlx5_qp_state mlx5_cur, mlx5_new;
3510         enum mlx5_qp_optpar optpar;
3511         u32 set_id = 0;
3512         int mlx5_st;
3513         int err;
3514         u16 op;
3515         u8 tx_affinity = 0;
3516
3517         mlx5_st = to_mlx5_st(qp->type);
3518         if (mlx5_st < 0)
3519                 return -EINVAL;
3520
3521         context = kzalloc(sizeof(*context), GFP_KERNEL);
3522         if (!context)
3523                 return -ENOMEM;
3524
3525         pd = get_pd(qp);
3526         context->flags = cpu_to_be32(mlx5_st << 16);
3527
3528         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3529                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3530         } else {
3531                 switch (attr->path_mig_state) {
3532                 case IB_MIG_MIGRATED:
3533                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3534                         break;
3535                 case IB_MIG_REARM:
3536                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3537                         break;
3538                 case IB_MIG_ARMED:
3539                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3540                         break;
3541                 }
3542         }
3543
3544         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3545                 if ((ibqp->qp_type == IB_QPT_RC) ||
3546                     (ibqp->qp_type == IB_QPT_UD &&
3547                      !(qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)) ||
3548                     (ibqp->qp_type == IB_QPT_UC) ||
3549                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3550                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3551                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3552                         if (dev->lag_active) {
3553                                 u8 p = mlx5_core_native_port_num(dev->mdev) - 1;
3554                                 tx_affinity = get_tx_affinity(dev, pd, base, p,
3555                                                               udata);
3556                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3557                         }
3558                 }
3559         }
3560
3561         if (is_sqp(ibqp->qp_type)) {
3562                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3563         } else if ((ibqp->qp_type == IB_QPT_UD &&
3564                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
3565                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3566                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3567         } else if (attr_mask & IB_QP_PATH_MTU) {
3568                 if (attr->path_mtu < IB_MTU_256 ||
3569                     attr->path_mtu > IB_MTU_4096) {
3570                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3571                         err = -EINVAL;
3572                         goto out;
3573                 }
3574                 context->mtu_msgmax = (attr->path_mtu << 5) |
3575                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3576         }
3577
3578         if (attr_mask & IB_QP_DEST_QPN)
3579                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3580
3581         if (attr_mask & IB_QP_PKEY_INDEX)
3582                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3583
3584         /* todo implement counter_index functionality */
3585
3586         if (is_sqp(ibqp->qp_type))
3587                 context->pri_path.port = qp->port;
3588
3589         if (attr_mask & IB_QP_PORT)
3590                 context->pri_path.port = attr->port_num;
3591
3592         if (attr_mask & IB_QP_AV) {
3593                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3594                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3595                                     attr_mask, 0, attr, false);
3596                 if (err)
3597                         goto out;
3598         }
3599
3600         if (attr_mask & IB_QP_TIMEOUT)
3601                 context->pri_path.ackto_lt |= attr->timeout << 3;
3602
3603         if (attr_mask & IB_QP_ALT_PATH) {
3604                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3605                                     &context->alt_path,
3606                                     attr->alt_port_num,
3607                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3608                                     0, attr, true);
3609                 if (err)
3610                         goto out;
3611         }
3612
3613         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3614                 &send_cq, &recv_cq);
3615
3616         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3617         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3618         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3619         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3620
3621         if (attr_mask & IB_QP_RNR_RETRY)
3622                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3623
3624         if (attr_mask & IB_QP_RETRY_CNT)
3625                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3626
3627         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3628                 if (attr->max_rd_atomic)
3629                         context->params1 |=
3630                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3631         }
3632
3633         if (attr_mask & IB_QP_SQ_PSN)
3634                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3635
3636         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3637                 if (attr->max_dest_rd_atomic)
3638                         context->params2 |=
3639                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3640         }
3641
3642         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3643                 __be32 access_flags;
3644
3645                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3646                 if (err)
3647                         goto out;
3648
3649                 context->params2 |= access_flags;
3650         }
3651
3652         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3653                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3654
3655         if (attr_mask & IB_QP_RQ_PSN)
3656                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3657
3658         if (attr_mask & IB_QP_QKEY)
3659                 context->qkey = cpu_to_be32(attr->qkey);
3660
3661         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3662                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3663
3664         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3665                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3666                                qp->port) - 1;
3667
3668                 /* Underlay port should be used - index 0 function per port */
3669                 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
3670                         port_num = 0;
3671
3672                 if (ibqp->counter)
3673                         set_id = ibqp->counter->id;
3674                 else
3675                         set_id = mlx5_ib_get_counters_id(dev, port_num);
3676                 context->qp_counter_set_usr_page |=
3677                         cpu_to_be32(set_id << 24);
3678         }
3679
3680         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3681                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3682
3683         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3684                 context->deth_sqpn = cpu_to_be32(1);
3685
3686         mlx5_cur = to_mlx5_state(cur_state);
3687         mlx5_new = to_mlx5_state(new_state);
3688
3689         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3690             !optab[mlx5_cur][mlx5_new]) {
3691                 err = -EINVAL;
3692                 goto out;
3693         }
3694
3695         op = optab[mlx5_cur][mlx5_new];
3696         optpar = ib_mask_to_mlx5_opt(attr_mask);
3697         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3698
3699         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3700             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
3701                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3702
3703                 raw_qp_param.operation = op;
3704                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3705                         raw_qp_param.rq_q_ctr_id = set_id;
3706                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3707                 }
3708
3709                 if (attr_mask & IB_QP_PORT)
3710                         raw_qp_param.port = attr->port_num;
3711
3712                 if (attr_mask & IB_QP_RATE_LIMIT) {
3713                         raw_qp_param.rl.rate = attr->rate_limit;
3714
3715                         if (ucmd->burst_info.max_burst_sz) {
3716                                 if (attr->rate_limit &&
3717                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3718                                         raw_qp_param.rl.max_burst_sz =
3719                                                 ucmd->burst_info.max_burst_sz;
3720                                 } else {
3721                                         err = -EINVAL;
3722                                         goto out;
3723                                 }
3724                         }
3725
3726                         if (ucmd->burst_info.typical_pkt_sz) {
3727                                 if (attr->rate_limit &&
3728                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3729                                         raw_qp_param.rl.typical_pkt_sz =
3730                                                 ucmd->burst_info.typical_pkt_sz;
3731                                 } else {
3732                                         err = -EINVAL;
3733                                         goto out;
3734                                 }
3735                         }
3736
3737                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3738                 }
3739
3740                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3741         } else {
3742                 err = mlx5_core_qp_modify(dev, op, optpar, context, &base->mqp);
3743         }
3744
3745         if (err)
3746                 goto out;
3747
3748         qp->state = new_state;
3749
3750         if (attr_mask & IB_QP_ACCESS_FLAGS)
3751                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3752         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3753                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3754         if (attr_mask & IB_QP_PORT)
3755                 qp->port = attr->port_num;
3756         if (attr_mask & IB_QP_ALT_PATH)
3757                 qp->trans_qp.alt_port = attr->alt_port_num;
3758
3759         /*
3760          * If we moved a kernel QP to RESET, clean up all old CQ
3761          * entries and reinitialize the QP.
3762          */
3763         if (new_state == IB_QPS_RESET &&
3764             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3765                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3766                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3767                 if (send_cq != recv_cq)
3768                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3769
3770                 qp->rq.head = 0;
3771                 qp->rq.tail = 0;
3772                 qp->sq.head = 0;
3773                 qp->sq.tail = 0;
3774                 qp->sq.cur_post = 0;
3775                 if (qp->sq.wqe_cnt)
3776                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3777                 qp->sq.last_poll = 0;
3778                 qp->db.db[MLX5_RCV_DBR] = 0;
3779                 qp->db.db[MLX5_SND_DBR] = 0;
3780         }
3781
3782         if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
3783                 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
3784                 if (!err)
3785                         qp->counter_pending = 0;
3786         }
3787
3788 out:
3789         kfree(context);
3790         return err;
3791 }
3792
3793 static inline bool is_valid_mask(int mask, int req, int opt)
3794 {
3795         if ((mask & req) != req)
3796                 return false;
3797
3798         if (mask & ~(req | opt))
3799                 return false;
3800
3801         return true;
3802 }
3803
3804 /* check valid transition for driver QP types
3805  * for now the only QP type that this function supports is DCI
3806  */
3807 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3808                                 enum ib_qp_attr_mask attr_mask)
3809 {
3810         int req = IB_QP_STATE;
3811         int opt = 0;
3812
3813         if (new_state == IB_QPS_RESET) {
3814                 return is_valid_mask(attr_mask, req, opt);
3815         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3816                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3817                 return is_valid_mask(attr_mask, req, opt);
3818         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3819                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3820                 return is_valid_mask(attr_mask, req, opt);
3821         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3822                 req |= IB_QP_PATH_MTU;
3823                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3824                 return is_valid_mask(attr_mask, req, opt);
3825         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3826                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3827                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3828                 opt = IB_QP_MIN_RNR_TIMER;
3829                 return is_valid_mask(attr_mask, req, opt);
3830         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3831                 opt = IB_QP_MIN_RNR_TIMER;
3832                 return is_valid_mask(attr_mask, req, opt);
3833         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3834                 return is_valid_mask(attr_mask, req, opt);
3835         }
3836         return false;
3837 }
3838
3839 /* mlx5_ib_modify_dct: modify a DCT QP
3840  * valid transitions are:
3841  * RESET to INIT: must set access_flags, pkey_index and port
3842  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3843  *                         mtu, gid_index and hop_limit
3844  * Other transitions and attributes are illegal
3845  */
3846 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3847                               int attr_mask, struct ib_udata *udata)
3848 {
3849         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3850         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3851         enum ib_qp_state cur_state, new_state;
3852         int err = 0;
3853         int required = IB_QP_STATE;
3854         void *dctc;
3855
3856         if (!(attr_mask & IB_QP_STATE))
3857                 return -EINVAL;
3858
3859         cur_state = qp->state;
3860         new_state = attr->qp_state;
3861
3862         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3863         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3864                 u16 set_id;
3865
3866                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3867                 if (!is_valid_mask(attr_mask, required, 0))
3868                         return -EINVAL;
3869
3870                 if (attr->port_num == 0 ||
3871                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3872                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3873                                     attr->port_num, dev->num_ports);
3874                         return -EINVAL;
3875                 }
3876                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3877                         MLX5_SET(dctc, dctc, rre, 1);
3878                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3879                         MLX5_SET(dctc, dctc, rwe, 1);
3880                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3881                         int atomic_mode;
3882
3883                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3884                         if (atomic_mode < 0)
3885                                 return -EOPNOTSUPP;
3886
3887                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3888                         MLX5_SET(dctc, dctc, rae, 1);
3889                 }
3890                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3891                 MLX5_SET(dctc, dctc, port, attr->port_num);
3892
3893                 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
3894                 MLX5_SET(dctc, dctc, counter_set_id, set_id);
3895
3896         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3897                 struct mlx5_ib_modify_qp_resp resp = {};
3898                 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
3899                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3900                                    sizeof(resp.dctn);
3901
3902                 if (udata->outlen < min_resp_len)
3903                         return -EINVAL;
3904                 resp.response_length = min_resp_len;
3905
3906                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3907                 if (!is_valid_mask(attr_mask, required, 0))
3908                         return -EINVAL;
3909                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3910                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3911                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3912                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3913                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3914                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3915
3916                 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
3917                                            MLX5_ST_SZ_BYTES(create_dct_in), out,
3918                                            sizeof(out));
3919                 if (err)
3920                         return err;
3921                 resp.dctn = qp->dct.mdct.mqp.qpn;
3922                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3923                 if (err) {
3924                         mlx5_core_destroy_dct(dev, &qp->dct.mdct);
3925                         return err;
3926                 }
3927         } else {
3928                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3929                 return -EINVAL;
3930         }
3931         if (err)
3932                 qp->state = IB_QPS_ERR;
3933         else
3934                 qp->state = new_state;
3935         return err;
3936 }
3937
3938 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3939                       int attr_mask, struct ib_udata *udata)
3940 {
3941         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3942         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3943         struct mlx5_ib_modify_qp ucmd = {};
3944         enum ib_qp_type qp_type;
3945         enum ib_qp_state cur_state, new_state;
3946         size_t required_cmd_sz;
3947         int err = -EINVAL;
3948         int port;
3949
3950         if (ibqp->rwq_ind_tbl)
3951                 return -ENOSYS;
3952
3953         if (udata && udata->inlen) {
3954                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3955                         sizeof(ucmd.reserved);
3956                 if (udata->inlen < required_cmd_sz)
3957                         return -EINVAL;
3958
3959                 if (udata->inlen > sizeof(ucmd) &&
3960                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3961                                          udata->inlen - sizeof(ucmd)))
3962                         return -EOPNOTSUPP;
3963
3964                 if (ib_copy_from_udata(&ucmd, udata,
3965                                        min(udata->inlen, sizeof(ucmd))))
3966                         return -EFAULT;
3967
3968                 if (ucmd.comp_mask ||
3969                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3970                     memchr_inv(&ucmd.burst_info.reserved, 0,
3971                                sizeof(ucmd.burst_info.reserved)))
3972                         return -EOPNOTSUPP;
3973         }
3974
3975         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3976                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3977
3978         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
3979                                                                     qp->type;
3980
3981         if (qp_type == MLX5_IB_QPT_DCT)
3982                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3983
3984         mutex_lock(&qp->mutex);
3985
3986         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3987         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3988
3989         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3990                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3991         }
3992
3993         if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
3994                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3995                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3996                                     attr_mask);
3997                         goto out;
3998                 }
3999         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
4000                    qp_type != MLX5_IB_QPT_DCI &&
4001                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4002                                        attr_mask)) {
4003                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4004                             cur_state, new_state, ibqp->qp_type, attr_mask);
4005                 goto out;
4006         } else if (qp_type == MLX5_IB_QPT_DCI &&
4007                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4008                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4009                             cur_state, new_state, qp_type, attr_mask);
4010                 goto out;
4011         }
4012
4013         if ((attr_mask & IB_QP_PORT) &&
4014             (attr->port_num == 0 ||
4015              attr->port_num > dev->num_ports)) {
4016                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4017                             attr->port_num, dev->num_ports);
4018                 goto out;
4019         }
4020
4021         if (attr_mask & IB_QP_PKEY_INDEX) {
4022                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4023                 if (attr->pkey_index >=
4024                     dev->mdev->port_caps[port - 1].pkey_table_len) {
4025                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4026                                     attr->pkey_index);
4027                         goto out;
4028                 }
4029         }
4030
4031         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
4032             attr->max_rd_atomic >
4033             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4034                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4035                             attr->max_rd_atomic);
4036                 goto out;
4037         }
4038
4039         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
4040             attr->max_dest_rd_atomic >
4041             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4042                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4043                             attr->max_dest_rd_atomic);
4044                 goto out;
4045         }
4046
4047         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4048                 err = 0;
4049                 goto out;
4050         }
4051
4052         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4053                                   new_state, &ucmd, udata);
4054
4055 out:
4056         mutex_unlock(&qp->mutex);
4057         return err;
4058 }
4059
4060 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4061                                    u32 wqe_sz, void **cur_edge)
4062 {
4063         u32 idx;
4064
4065         idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
4066         *cur_edge = get_sq_edge(sq, idx);
4067
4068         *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
4069 }
4070
4071 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
4072  * next nearby edge and get new address translation for current WQE position.
4073  * @sq - SQ buffer.
4074  * @seg: Current WQE position (16B aligned).
4075  * @wqe_sz: Total current WQE size [16B].
4076  * @cur_edge: Updated current edge.
4077  */
4078 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4079                                          u32 wqe_sz, void **cur_edge)
4080 {
4081         if (likely(*seg != *cur_edge))
4082                 return;
4083
4084         _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
4085 }
4086
4087 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
4088  * pointers. At the end @seg is aligned to 16B regardless the copied size.
4089  * @sq - SQ buffer.
4090  * @cur_edge: Updated current edge.
4091  * @seg: Current WQE position (16B aligned).
4092  * @wqe_sz: Total current WQE size [16B].
4093  * @src: Pointer to copy from.
4094  * @n: Number of bytes to copy.
4095  */
4096 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
4097                                    void **seg, u32 *wqe_sz, const void *src,
4098                                    size_t n)
4099 {
4100         while (likely(n)) {
4101                 size_t leftlen = *cur_edge - *seg;
4102                 size_t copysz = min_t(size_t, leftlen, n);
4103                 size_t stride;
4104
4105                 memcpy(*seg, src, copysz);
4106
4107                 n -= copysz;
4108                 src += copysz;
4109                 stride = !n ? ALIGN(copysz, 16) : copysz;
4110                 *seg += stride;
4111                 *wqe_sz += stride >> 4;
4112                 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
4113         }
4114 }
4115
4116 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
4117 {
4118         struct mlx5_ib_cq *cq;
4119         unsigned cur;
4120
4121         cur = wq->head - wq->tail;
4122         if (likely(cur + nreq < wq->max_post))
4123                 return 0;
4124
4125         cq = to_mcq(ib_cq);
4126         spin_lock(&cq->lock);
4127         cur = wq->head - wq->tail;
4128         spin_unlock(&cq->lock);
4129
4130         return cur + nreq >= wq->max_post;
4131 }
4132
4133 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
4134                                           u64 remote_addr, u32 rkey)
4135 {
4136         rseg->raddr    = cpu_to_be64(remote_addr);
4137         rseg->rkey     = cpu_to_be32(rkey);
4138         rseg->reserved = 0;
4139 }
4140
4141 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
4142                         void **seg, int *size, void **cur_edge)
4143 {
4144         struct mlx5_wqe_eth_seg *eseg = *seg;
4145
4146         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
4147
4148         if (wr->send_flags & IB_SEND_IP_CSUM)
4149                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
4150                                  MLX5_ETH_WQE_L4_CSUM;
4151
4152         if (wr->opcode == IB_WR_LSO) {
4153                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
4154                 size_t left, copysz;
4155                 void *pdata = ud_wr->header;
4156                 size_t stride;
4157
4158                 left = ud_wr->hlen;
4159                 eseg->mss = cpu_to_be16(ud_wr->mss);
4160                 eseg->inline_hdr.sz = cpu_to_be16(left);
4161
4162                 /* memcpy_send_wqe should get a 16B align address. Hence, we
4163                  * first copy up to the current edge and then, if needed,
4164                  * fall-through to memcpy_send_wqe.
4165                  */
4166                 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
4167                                left);
4168                 memcpy(eseg->inline_hdr.start, pdata, copysz);
4169                 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
4170                                sizeof(eseg->inline_hdr.start) + copysz, 16);
4171                 *size += stride / 16;
4172                 *seg += stride;
4173
4174                 if (copysz < left) {
4175                         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4176                         left -= copysz;
4177                         pdata += copysz;
4178                         memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4179                                         left);
4180                 }
4181
4182                 return;
4183         }
4184
4185         *seg += sizeof(struct mlx5_wqe_eth_seg);
4186         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
4187 }
4188
4189 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
4190                              const struct ib_send_wr *wr)
4191 {
4192         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4193         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4194         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
4195 }
4196
4197 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4198 {
4199         dseg->byte_count = cpu_to_be32(sg->length);
4200         dseg->lkey       = cpu_to_be32(sg->lkey);
4201         dseg->addr       = cpu_to_be64(sg->addr);
4202 }
4203
4204 static u64 get_xlt_octo(u64 bytes)
4205 {
4206         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4207                MLX5_IB_UMR_OCTOWORD;
4208 }
4209
4210 static __be64 frwr_mkey_mask(bool atomic)
4211 {
4212         u64 result;
4213
4214         result = MLX5_MKEY_MASK_LEN             |
4215                 MLX5_MKEY_MASK_PAGE_SIZE        |
4216                 MLX5_MKEY_MASK_START_ADDR       |
4217                 MLX5_MKEY_MASK_EN_RINVAL        |
4218                 MLX5_MKEY_MASK_KEY              |
4219                 MLX5_MKEY_MASK_LR               |
4220                 MLX5_MKEY_MASK_LW               |
4221                 MLX5_MKEY_MASK_RR               |
4222                 MLX5_MKEY_MASK_RW               |
4223                 MLX5_MKEY_MASK_SMALL_FENCE      |
4224                 MLX5_MKEY_MASK_FREE;
4225
4226         if (atomic)
4227                 result |= MLX5_MKEY_MASK_A;
4228
4229         return cpu_to_be64(result);
4230 }
4231
4232 static __be64 sig_mkey_mask(void)
4233 {
4234         u64 result;
4235
4236         result = MLX5_MKEY_MASK_LEN             |
4237                 MLX5_MKEY_MASK_PAGE_SIZE        |
4238                 MLX5_MKEY_MASK_START_ADDR       |
4239                 MLX5_MKEY_MASK_EN_SIGERR        |
4240                 MLX5_MKEY_MASK_EN_RINVAL        |
4241                 MLX5_MKEY_MASK_KEY              |
4242                 MLX5_MKEY_MASK_LR               |
4243                 MLX5_MKEY_MASK_LW               |
4244                 MLX5_MKEY_MASK_RR               |
4245                 MLX5_MKEY_MASK_RW               |
4246                 MLX5_MKEY_MASK_SMALL_FENCE      |
4247                 MLX5_MKEY_MASK_FREE             |
4248                 MLX5_MKEY_MASK_BSF_EN;
4249
4250         return cpu_to_be64(result);
4251 }
4252
4253 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
4254                             struct mlx5_ib_mr *mr, u8 flags, bool atomic)
4255 {
4256         int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4257
4258         memset(umr, 0, sizeof(*umr));
4259
4260         umr->flags = flags;
4261         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4262         umr->mkey_mask = frwr_mkey_mask(atomic);
4263 }
4264
4265 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4266 {
4267         memset(umr, 0, sizeof(*umr));
4268         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4269         umr->flags = MLX5_UMR_INLINE;
4270 }
4271
4272 static __be64 get_umr_enable_mr_mask(void)
4273 {
4274         u64 result;
4275
4276         result = MLX5_MKEY_MASK_KEY |
4277                  MLX5_MKEY_MASK_FREE;
4278
4279         return cpu_to_be64(result);
4280 }
4281
4282 static __be64 get_umr_disable_mr_mask(void)
4283 {
4284         u64 result;
4285
4286         result = MLX5_MKEY_MASK_FREE;
4287
4288         return cpu_to_be64(result);
4289 }
4290
4291 static __be64 get_umr_update_translation_mask(void)
4292 {
4293         u64 result;
4294
4295         result = MLX5_MKEY_MASK_LEN |
4296                  MLX5_MKEY_MASK_PAGE_SIZE |
4297                  MLX5_MKEY_MASK_START_ADDR;
4298
4299         return cpu_to_be64(result);
4300 }
4301
4302 static __be64 get_umr_update_access_mask(int atomic)
4303 {
4304         u64 result;
4305
4306         result = MLX5_MKEY_MASK_LR |
4307                  MLX5_MKEY_MASK_LW |
4308                  MLX5_MKEY_MASK_RR |
4309                  MLX5_MKEY_MASK_RW;
4310
4311         if (atomic)
4312                 result |= MLX5_MKEY_MASK_A;
4313
4314         return cpu_to_be64(result);
4315 }
4316
4317 static __be64 get_umr_update_pd_mask(void)
4318 {
4319         u64 result;
4320
4321         result = MLX5_MKEY_MASK_PD;
4322
4323         return cpu_to_be64(result);
4324 }
4325
4326 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4327 {
4328         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4329              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4330             (mask & MLX5_MKEY_MASK_A &&
4331              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4332                 return -EPERM;
4333         return 0;
4334 }
4335
4336 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4337                                struct mlx5_wqe_umr_ctrl_seg *umr,
4338                                const struct ib_send_wr *wr, int atomic)
4339 {
4340         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4341
4342         memset(umr, 0, sizeof(*umr));
4343
4344         if (!umrwr->ignore_free_state) {
4345                 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4346                          /* fail if free */
4347                         umr->flags = MLX5_UMR_CHECK_FREE;
4348                 else
4349                         /* fail if not free */
4350                         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
4351         }
4352
4353         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4354         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4355                 u64 offset = get_xlt_octo(umrwr->offset);
4356
4357                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4358                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4359                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4360         }
4361         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4362                 umr->mkey_mask |= get_umr_update_translation_mask();
4363         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4364                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4365                 umr->mkey_mask |= get_umr_update_pd_mask();
4366         }
4367         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4368                 umr->mkey_mask |= get_umr_enable_mr_mask();
4369         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4370                 umr->mkey_mask |= get_umr_disable_mr_mask();
4371
4372         if (!wr->num_sge)
4373                 umr->flags |= MLX5_UMR_INLINE;
4374
4375         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4376 }
4377
4378 static u8 get_umr_flags(int acc)
4379 {
4380         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4381                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4382                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4383                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4384                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4385 }
4386
4387 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4388                              struct mlx5_ib_mr *mr,
4389                              u32 key, int access)
4390 {
4391         int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1;
4392
4393         memset(seg, 0, sizeof(*seg));
4394
4395         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4396                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4397         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4398                 /* KLMs take twice the size of MTTs */
4399                 ndescs *= 2;
4400
4401         seg->flags = get_umr_flags(access) | mr->access_mode;
4402         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4403         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4404         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4405         seg->len = cpu_to_be64(mr->ibmr.length);
4406         seg->xlt_oct_size = cpu_to_be32(ndescs);
4407 }
4408
4409 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4410 {
4411         memset(seg, 0, sizeof(*seg));
4412         seg->status = MLX5_MKEY_STATUS_FREE;
4413 }
4414
4415 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4416                                  const struct ib_send_wr *wr)
4417 {
4418         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4419
4420         memset(seg, 0, sizeof(*seg));
4421         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4422                 seg->status = MLX5_MKEY_STATUS_FREE;
4423
4424         seg->flags = convert_access(umrwr->access_flags);
4425         if (umrwr->pd)
4426                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4427         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4428             !umrwr->length)
4429                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4430
4431         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4432         seg->len = cpu_to_be64(umrwr->length);
4433         seg->log2_page_size = umrwr->page_shift;
4434         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4435                                        mlx5_mkey_variant(umrwr->mkey));
4436 }
4437
4438 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4439                              struct mlx5_ib_mr *mr,
4440                              struct mlx5_ib_pd *pd)
4441 {
4442         int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs);
4443
4444         dseg->addr = cpu_to_be64(mr->desc_map);
4445         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4446         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4447 }
4448
4449 static __be32 send_ieth(const struct ib_send_wr *wr)
4450 {
4451         switch (wr->opcode) {
4452         case IB_WR_SEND_WITH_IMM:
4453         case IB_WR_RDMA_WRITE_WITH_IMM:
4454                 return wr->ex.imm_data;
4455
4456         case IB_WR_SEND_WITH_INV:
4457                 return cpu_to_be32(wr->ex.invalidate_rkey);
4458
4459         default:
4460                 return 0;
4461         }
4462 }
4463
4464 static u8 calc_sig(void *wqe, int size)
4465 {
4466         u8 *p = wqe;
4467         u8 res = 0;
4468         int i;
4469
4470         for (i = 0; i < size; i++)
4471                 res ^= p[i];
4472
4473         return ~res;
4474 }
4475
4476 static u8 wq_sig(void *wqe)
4477 {
4478         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4479 }
4480
4481 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4482                             void **wqe, int *wqe_sz, void **cur_edge)
4483 {
4484         struct mlx5_wqe_inline_seg *seg;
4485         size_t offset;
4486         int inl = 0;
4487         int i;
4488
4489         seg = *wqe;
4490         *wqe += sizeof(*seg);
4491         offset = sizeof(*seg);
4492
4493         for (i = 0; i < wr->num_sge; i++) {
4494                 size_t len  = wr->sg_list[i].length;
4495                 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4496
4497                 inl += len;
4498
4499                 if (unlikely(inl > qp->max_inline_data))
4500                         return -ENOMEM;
4501
4502                 while (likely(len)) {
4503                         size_t leftlen;
4504                         size_t copysz;
4505
4506                         handle_post_send_edge(&qp->sq, wqe,
4507                                               *wqe_sz + (offset >> 4),
4508                                               cur_edge);
4509
4510                         leftlen = *cur_edge - *wqe;
4511                         copysz = min_t(size_t, leftlen, len);
4512
4513                         memcpy(*wqe, addr, copysz);
4514                         len -= copysz;
4515                         addr += copysz;
4516                         *wqe += copysz;
4517                         offset += copysz;
4518                 }
4519         }
4520
4521         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4522
4523         *wqe_sz +=  ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4524
4525         return 0;
4526 }
4527
4528 static u16 prot_field_size(enum ib_signature_type type)
4529 {
4530         switch (type) {
4531         case IB_SIG_TYPE_T10_DIF:
4532                 return MLX5_DIF_SIZE;
4533         default:
4534                 return 0;
4535         }
4536 }
4537
4538 static u8 bs_selector(int block_size)
4539 {
4540         switch (block_size) {
4541         case 512:           return 0x1;
4542         case 520:           return 0x2;
4543         case 4096:          return 0x3;
4544         case 4160:          return 0x4;
4545         case 1073741824:    return 0x5;
4546         default:            return 0;
4547         }
4548 }
4549
4550 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4551                               struct mlx5_bsf_inl *inl)
4552 {
4553         /* Valid inline section and allow BSF refresh */
4554         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4555                                        MLX5_BSF_REFRESH_DIF);
4556         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4557         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4558         /* repeating block */
4559         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4560         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4561                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4562
4563         if (domain->sig.dif.ref_remap)
4564                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4565
4566         if (domain->sig.dif.app_escape) {
4567                 if (domain->sig.dif.ref_escape)
4568                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4569                 else
4570                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4571         }
4572
4573         inl->dif_app_bitmask_check =
4574                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4575 }
4576
4577 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4578                         struct ib_sig_attrs *sig_attrs,
4579                         struct mlx5_bsf *bsf, u32 data_size)
4580 {
4581         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4582         struct mlx5_bsf_basic *basic = &bsf->basic;
4583         struct ib_sig_domain *mem = &sig_attrs->mem;
4584         struct ib_sig_domain *wire = &sig_attrs->wire;
4585
4586         memset(bsf, 0, sizeof(*bsf));
4587
4588         /* Basic + Extended + Inline */
4589         basic->bsf_size_sbs = 1 << 7;
4590         /* Input domain check byte mask */
4591         basic->check_byte_mask = sig_attrs->check_mask;
4592         basic->raw_data_size = cpu_to_be32(data_size);
4593
4594         /* Memory domain */
4595         switch (sig_attrs->mem.sig_type) {
4596         case IB_SIG_TYPE_NONE:
4597                 break;
4598         case IB_SIG_TYPE_T10_DIF:
4599                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4600                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4601                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4602                 break;
4603         default:
4604                 return -EINVAL;
4605         }
4606
4607         /* Wire domain */
4608         switch (sig_attrs->wire.sig_type) {
4609         case IB_SIG_TYPE_NONE:
4610                 break;
4611         case IB_SIG_TYPE_T10_DIF:
4612                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4613                     mem->sig_type == wire->sig_type) {
4614                         /* Same block structure */
4615                         basic->bsf_size_sbs |= 1 << 4;
4616                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4617                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4618                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4619                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4620                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4621                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4622                 } else
4623                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4624
4625                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4626                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4627                 break;
4628         default:
4629                 return -EINVAL;
4630         }
4631
4632         return 0;
4633 }
4634
4635 static int set_sig_data_segment(const struct ib_send_wr *send_wr,
4636                                 struct ib_mr *sig_mr,
4637                                 struct ib_sig_attrs *sig_attrs,
4638                                 struct mlx5_ib_qp *qp, void **seg, int *size,
4639                                 void **cur_edge)
4640 {
4641         struct mlx5_bsf *bsf;
4642         u32 data_len;
4643         u32 data_key;
4644         u64 data_va;
4645         u32 prot_len = 0;
4646         u32 prot_key = 0;
4647         u64 prot_va = 0;
4648         bool prot = false;
4649         int ret;
4650         int wqe_size;
4651         struct mlx5_ib_mr *mr = to_mmr(sig_mr);
4652         struct mlx5_ib_mr *pi_mr = mr->pi_mr;
4653
4654         data_len = pi_mr->data_length;
4655         data_key = pi_mr->ibmr.lkey;
4656         data_va = pi_mr->data_iova;
4657         if (pi_mr->meta_ndescs) {
4658                 prot_len = pi_mr->meta_length;
4659                 prot_key = pi_mr->ibmr.lkey;
4660                 prot_va = pi_mr->pi_iova;
4661                 prot = true;
4662         }
4663
4664         if (!prot || (data_key == prot_key && data_va == prot_va &&
4665                       data_len == prot_len)) {
4666                 /**
4667                  * Source domain doesn't contain signature information
4668                  * or data and protection are interleaved in memory.
4669                  * So need construct:
4670                  *                  ------------------
4671                  *                 |     data_klm     |
4672                  *                  ------------------
4673                  *                 |       BSF        |
4674                  *                  ------------------
4675                  **/
4676                 struct mlx5_klm *data_klm = *seg;
4677
4678                 data_klm->bcount = cpu_to_be32(data_len);
4679                 data_klm->key = cpu_to_be32(data_key);
4680                 data_klm->va = cpu_to_be64(data_va);
4681                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4682         } else {
4683                 /**
4684                  * Source domain contains signature information
4685                  * So need construct a strided block format:
4686                  *               ---------------------------
4687                  *              |     stride_block_ctrl     |
4688                  *               ---------------------------
4689                  *              |          data_klm         |
4690                  *               ---------------------------
4691                  *              |          prot_klm         |
4692                  *               ---------------------------
4693                  *              |             BSF           |
4694                  *               ---------------------------
4695                  **/
4696                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4697                 struct mlx5_stride_block_entry *data_sentry;
4698                 struct mlx5_stride_block_entry *prot_sentry;
4699                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4700                 int prot_size;
4701
4702                 sblock_ctrl = *seg;
4703                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4704                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4705
4706                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4707                 if (!prot_size) {
4708                         pr_err("Bad block size given: %u\n", block_size);
4709                         return -EINVAL;
4710                 }
4711                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4712                                                             prot_size);
4713                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4714                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4715                 sblock_ctrl->num_entries = cpu_to_be16(2);
4716
4717                 data_sentry->bcount = cpu_to_be16(block_size);
4718                 data_sentry->key = cpu_to_be32(data_key);
4719                 data_sentry->va = cpu_to_be64(data_va);
4720                 data_sentry->stride = cpu_to_be16(block_size);
4721
4722                 prot_sentry->bcount = cpu_to_be16(prot_size);
4723                 prot_sentry->key = cpu_to_be32(prot_key);
4724                 prot_sentry->va = cpu_to_be64(prot_va);
4725                 prot_sentry->stride = cpu_to_be16(prot_size);
4726
4727                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4728                                  sizeof(*prot_sentry), 64);
4729         }
4730
4731         *seg += wqe_size;
4732         *size += wqe_size / 16;
4733         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4734
4735         bsf = *seg;
4736         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4737         if (ret)
4738                 return -EINVAL;
4739
4740         *seg += sizeof(*bsf);
4741         *size += sizeof(*bsf) / 16;
4742         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4743
4744         return 0;
4745 }
4746
4747 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4748                                  struct ib_mr *sig_mr, int access_flags,
4749                                  u32 size, u32 length, u32 pdn)
4750 {
4751         u32 sig_key = sig_mr->rkey;
4752         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4753
4754         memset(seg, 0, sizeof(*seg));
4755
4756         seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS;
4757         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4758         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4759                                     MLX5_MKEY_BSF_EN | pdn);
4760         seg->len = cpu_to_be64(length);
4761         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4762         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4763 }
4764
4765 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4766                                 u32 size)
4767 {
4768         memset(umr, 0, sizeof(*umr));
4769
4770         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4771         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4772         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4773         umr->mkey_mask = sig_mkey_mask();
4774 }
4775
4776 static int set_pi_umr_wr(const struct ib_send_wr *send_wr,
4777                          struct mlx5_ib_qp *qp, void **seg, int *size,
4778                          void **cur_edge)
4779 {
4780         const struct ib_reg_wr *wr = reg_wr(send_wr);
4781         struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr);
4782         struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr;
4783         struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs;
4784         u32 pdn = get_pd(qp)->pdn;
4785         u32 xlt_size;
4786         int region_len, ret;
4787
4788         if (unlikely(send_wr->num_sge != 0) ||
4789             unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) ||
4790             unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) ||
4791             unlikely(!sig_mr->sig->sig_status_checked))
4792                 return -EINVAL;
4793
4794         /* length of the protected region, data + protection */
4795         region_len = pi_mr->ibmr.length;
4796
4797         /**
4798          * KLM octoword size - if protection was provided
4799          * then we use strided block format (3 octowords),
4800          * else we use single KLM (1 octoword)
4801          **/
4802         if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE)
4803                 xlt_size = 0x30;
4804         else
4805                 xlt_size = sizeof(struct mlx5_klm);
4806
4807         set_sig_umr_segment(*seg, xlt_size);
4808         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4809         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4810         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4811
4812         set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len,
4813                              pdn);
4814         *seg += sizeof(struct mlx5_mkey_seg);
4815         *size += sizeof(struct mlx5_mkey_seg) / 16;
4816         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4817
4818         ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size,
4819                                    cur_edge);
4820         if (ret)
4821                 return ret;
4822
4823         sig_mr->sig->sig_status_checked = false;
4824         return 0;
4825 }
4826
4827 static int set_psv_wr(struct ib_sig_domain *domain,
4828                       u32 psv_idx, void **seg, int *size)
4829 {
4830         struct mlx5_seg_set_psv *psv_seg = *seg;
4831
4832         memset(psv_seg, 0, sizeof(*psv_seg));
4833         psv_seg->psv_num = cpu_to_be32(psv_idx);
4834         switch (domain->sig_type) {
4835         case IB_SIG_TYPE_NONE:
4836                 break;
4837         case IB_SIG_TYPE_T10_DIF:
4838                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4839                                                      domain->sig.dif.app_tag);
4840                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4841                 break;
4842         default:
4843                 pr_err("Bad signature type (%d) is given.\n",
4844                        domain->sig_type);
4845                 return -EINVAL;
4846         }
4847
4848         *seg += sizeof(*psv_seg);
4849         *size += sizeof(*psv_seg) / 16;
4850
4851         return 0;
4852 }
4853
4854 static int set_reg_wr(struct mlx5_ib_qp *qp,
4855                       const struct ib_reg_wr *wr,
4856                       void **seg, int *size, void **cur_edge,
4857                       bool check_not_free)
4858 {
4859         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4860         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4861         struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device);
4862         int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4863         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4864         bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC;
4865         u8 flags = 0;
4866
4867         if (!mlx5_ib_can_use_umr(dev, atomic, wr->access)) {
4868                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4869                              "Fast update of %s for MR is disabled\n",
4870                              (MLX5_CAP_GEN(dev->mdev,
4871                                            umr_modify_entity_size_disabled)) ?
4872                                      "entity size" :
4873                                      "atomic access");
4874                 return -EINVAL;
4875         }
4876
4877         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4878                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4879                              "Invalid IB_SEND_INLINE send flag\n");
4880                 return -EINVAL;
4881         }
4882
4883         if (check_not_free)
4884                 flags |= MLX5_UMR_CHECK_NOT_FREE;
4885         if (umr_inline)
4886                 flags |= MLX5_UMR_INLINE;
4887
4888         set_reg_umr_seg(*seg, mr, flags, atomic);
4889         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4890         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4891         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4892
4893         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4894         *seg += sizeof(struct mlx5_mkey_seg);
4895         *size += sizeof(struct mlx5_mkey_seg) / 16;
4896         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4897
4898         if (umr_inline) {
4899                 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4900                                 mr_list_size);
4901                 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4902         } else {
4903                 set_reg_data_seg(*seg, mr, pd);
4904                 *seg += sizeof(struct mlx5_wqe_data_seg);
4905                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4906         }
4907         return 0;
4908 }
4909
4910 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4911                         void **cur_edge)
4912 {
4913         set_linv_umr_seg(*seg);
4914         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4915         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4916         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4917         set_linv_mkey_seg(*seg);
4918         *seg += sizeof(struct mlx5_mkey_seg);
4919         *size += sizeof(struct mlx5_mkey_seg) / 16;
4920         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4921 }
4922
4923 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4924 {
4925         __be32 *p = NULL;
4926         int i, j;
4927
4928         pr_debug("dump WQE index %u:\n", idx);
4929         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4930                 if ((i & 0xf) == 0) {
4931                         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
4932                         pr_debug("WQBB at %p:\n", (void *)p);
4933                         j = 0;
4934                         idx = (idx + 1) & (qp->sq.wqe_cnt - 1);
4935                 }
4936                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4937                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4938                          be32_to_cpu(p[j + 3]));
4939         }
4940 }
4941
4942 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4943                        struct mlx5_wqe_ctrl_seg **ctrl,
4944                        const struct ib_send_wr *wr, unsigned int *idx,
4945                        int *size, void **cur_edge, int nreq,
4946                        bool send_signaled, bool solicited)
4947 {
4948         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4949                 return -ENOMEM;
4950
4951         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4952         *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4953         *ctrl = *seg;
4954         *(uint32_t *)(*seg + 8) = 0;
4955         (*ctrl)->imm = send_ieth(wr);
4956         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4957                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4958                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4959
4960         *seg += sizeof(**ctrl);
4961         *size = sizeof(**ctrl) / 16;
4962         *cur_edge = qp->sq.cur_edge;
4963
4964         return 0;
4965 }
4966
4967 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4968                      struct mlx5_wqe_ctrl_seg **ctrl,
4969                      const struct ib_send_wr *wr, unsigned *idx,
4970                      int *size, void **cur_edge, int nreq)
4971 {
4972         return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4973                            wr->send_flags & IB_SEND_SIGNALED,
4974                            wr->send_flags & IB_SEND_SOLICITED);
4975 }
4976
4977 static void finish_wqe(struct mlx5_ib_qp *qp,
4978                        struct mlx5_wqe_ctrl_seg *ctrl,
4979                        void *seg, u8 size, void *cur_edge,
4980                        unsigned int idx, u64 wr_id, int nreq, u8 fence,
4981                        u32 mlx5_opcode)
4982 {
4983         u8 opmod = 0;
4984
4985         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4986                                              mlx5_opcode | ((u32)opmod << 24));
4987         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4988         ctrl->fm_ce_se |= fence;
4989         if (unlikely(qp->flags_en & MLX5_QP_FLAG_SIGNATURE))
4990                 ctrl->signature = wq_sig(ctrl);
4991
4992         qp->sq.wrid[idx] = wr_id;
4993         qp->sq.w_list[idx].opcode = mlx5_opcode;
4994         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4995         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4996         qp->sq.w_list[idx].next = qp->sq.cur_post;
4997
4998         /* We save the edge which was possibly updated during the WQE
4999          * construction, into SQ's cache.
5000          */
5001         seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
5002         qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
5003                           get_sq_edge(&qp->sq, qp->sq.cur_post &
5004                                       (qp->sq.wqe_cnt - 1)) :
5005                           cur_edge;
5006 }
5007
5008 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5009                               const struct ib_send_wr **bad_wr, bool drain)
5010 {
5011         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
5012         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5013         struct mlx5_core_dev *mdev = dev->mdev;
5014         struct ib_reg_wr reg_pi_wr;
5015         struct mlx5_ib_qp *qp;
5016         struct mlx5_ib_mr *mr;
5017         struct mlx5_ib_mr *pi_mr;
5018         struct mlx5_ib_mr pa_pi_mr;
5019         struct ib_sig_attrs *sig_attrs;
5020         struct mlx5_wqe_xrc_seg *xrc;
5021         struct mlx5_bf *bf;
5022         void *cur_edge;
5023         int uninitialized_var(size);
5024         unsigned long flags;
5025         unsigned idx;
5026         int err = 0;
5027         int num_sge;
5028         void *seg;
5029         int nreq;
5030         int i;
5031         u8 next_fence = 0;
5032         u8 fence;
5033
5034         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5035                      !drain)) {
5036                 *bad_wr = wr;
5037                 return -EIO;
5038         }
5039
5040         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5041                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
5042
5043         qp = to_mqp(ibqp);
5044         bf = &qp->bf;
5045
5046         spin_lock_irqsave(&qp->sq.lock, flags);
5047
5048         for (nreq = 0; wr; nreq++, wr = wr->next) {
5049                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
5050                         mlx5_ib_warn(dev, "\n");
5051                         err = -EINVAL;
5052                         *bad_wr = wr;
5053                         goto out;
5054                 }
5055
5056                 num_sge = wr->num_sge;
5057                 if (unlikely(num_sge > qp->sq.max_gs)) {
5058                         mlx5_ib_warn(dev, "\n");
5059                         err = -EINVAL;
5060                         *bad_wr = wr;
5061                         goto out;
5062                 }
5063
5064                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
5065                                 nreq);
5066                 if (err) {
5067                         mlx5_ib_warn(dev, "\n");
5068                         err = -ENOMEM;
5069                         *bad_wr = wr;
5070                         goto out;
5071                 }
5072
5073                 if (wr->opcode == IB_WR_REG_MR ||
5074                     wr->opcode == IB_WR_REG_MR_INTEGRITY) {
5075                         fence = dev->umr_fence;
5076                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
5077                 } else  {
5078                         if (wr->send_flags & IB_SEND_FENCE) {
5079                                 if (qp->next_fence)
5080                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
5081                                 else
5082                                         fence = MLX5_FENCE_MODE_FENCE;
5083                         } else {
5084                                 fence = qp->next_fence;
5085                         }
5086                 }
5087
5088                 switch (ibqp->qp_type) {
5089                 case IB_QPT_XRC_INI:
5090                         xrc = seg;
5091                         seg += sizeof(*xrc);
5092                         size += sizeof(*xrc) / 16;
5093                         /* fall through */
5094                 case IB_QPT_RC:
5095                         switch (wr->opcode) {
5096                         case IB_WR_RDMA_READ:
5097                         case IB_WR_RDMA_WRITE:
5098                         case IB_WR_RDMA_WRITE_WITH_IMM:
5099                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5100                                               rdma_wr(wr)->rkey);
5101                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
5102                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5103                                 break;
5104
5105                         case IB_WR_ATOMIC_CMP_AND_SWP:
5106                         case IB_WR_ATOMIC_FETCH_AND_ADD:
5107                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
5108                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
5109                                 err = -ENOSYS;
5110                                 *bad_wr = wr;
5111                                 goto out;
5112
5113                         case IB_WR_LOCAL_INV:
5114                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
5115                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
5116                                 set_linv_wr(qp, &seg, &size, &cur_edge);
5117                                 num_sge = 0;
5118                                 break;
5119
5120                         case IB_WR_REG_MR:
5121                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
5122                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
5123                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
5124                                                  &cur_edge, true);
5125                                 if (err) {
5126                                         *bad_wr = wr;
5127                                         goto out;
5128                                 }
5129                                 num_sge = 0;
5130                                 break;
5131
5132                         case IB_WR_REG_MR_INTEGRITY:
5133                                 qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY;
5134
5135                                 mr = to_mmr(reg_wr(wr)->mr);
5136                                 pi_mr = mr->pi_mr;
5137
5138                                 if (pi_mr) {
5139                                         memset(&reg_pi_wr, 0,
5140                                                sizeof(struct ib_reg_wr));
5141
5142                                         reg_pi_wr.mr = &pi_mr->ibmr;
5143                                         reg_pi_wr.access = reg_wr(wr)->access;
5144                                         reg_pi_wr.key = pi_mr->ibmr.rkey;
5145
5146                                         ctrl->imm = cpu_to_be32(reg_pi_wr.key);
5147                                         /* UMR for data + prot registration */
5148                                         err = set_reg_wr(qp, &reg_pi_wr, &seg,
5149                                                          &size, &cur_edge,
5150                                                          false);
5151                                         if (err) {
5152                                                 *bad_wr = wr;
5153                                                 goto out;
5154                                         }
5155                                         finish_wqe(qp, ctrl, seg, size,
5156                                                    cur_edge, idx, wr->wr_id,
5157                                                    nreq, fence,
5158                                                    MLX5_OPCODE_UMR);
5159
5160                                         err = begin_wqe(qp, &seg, &ctrl, wr,
5161                                                         &idx, &size, &cur_edge,
5162                                                         nreq);
5163                                         if (err) {
5164                                                 mlx5_ib_warn(dev, "\n");
5165                                                 err = -ENOMEM;
5166                                                 *bad_wr = wr;
5167                                                 goto out;
5168                                         }
5169                                 } else {
5170                                         memset(&pa_pi_mr, 0,
5171                                                sizeof(struct mlx5_ib_mr));
5172                                         /* No UMR, use local_dma_lkey */
5173                                         pa_pi_mr.ibmr.lkey =
5174                                                 mr->ibmr.pd->local_dma_lkey;
5175
5176                                         pa_pi_mr.ndescs = mr->ndescs;
5177                                         pa_pi_mr.data_length = mr->data_length;
5178                                         pa_pi_mr.data_iova = mr->data_iova;
5179                                         if (mr->meta_ndescs) {
5180                                                 pa_pi_mr.meta_ndescs =
5181                                                         mr->meta_ndescs;
5182                                                 pa_pi_mr.meta_length =
5183                                                         mr->meta_length;
5184                                                 pa_pi_mr.pi_iova = mr->pi_iova;
5185                                         }
5186
5187                                         pa_pi_mr.ibmr.length = mr->ibmr.length;
5188                                         mr->pi_mr = &pa_pi_mr;
5189                                 }
5190                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
5191                                 /* UMR for sig MR */
5192                                 err = set_pi_umr_wr(wr, qp, &seg, &size,
5193                                                     &cur_edge);
5194                                 if (err) {
5195                                         mlx5_ib_warn(dev, "\n");
5196                                         *bad_wr = wr;
5197                                         goto out;
5198                                 }
5199                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5200                                            wr->wr_id, nreq, fence,
5201                                            MLX5_OPCODE_UMR);
5202
5203                                 /*
5204                                  * SET_PSV WQEs are not signaled and solicited
5205                                  * on error
5206                                  */
5207                                 sig_attrs = mr->ibmr.sig_attrs;
5208                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5209                                                   &size, &cur_edge, nreq, false,
5210                                                   true);
5211                                 if (err) {
5212                                         mlx5_ib_warn(dev, "\n");
5213                                         err = -ENOMEM;
5214                                         *bad_wr = wr;
5215                                         goto out;
5216                                 }
5217                                 err = set_psv_wr(&sig_attrs->mem,
5218                                                  mr->sig->psv_memory.psv_idx,
5219                                                  &seg, &size);
5220                                 if (err) {
5221                                         mlx5_ib_warn(dev, "\n");
5222                                         *bad_wr = wr;
5223                                         goto out;
5224                                 }
5225                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5226                                            wr->wr_id, nreq, next_fence,
5227                                            MLX5_OPCODE_SET_PSV);
5228
5229                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5230                                                   &size, &cur_edge, nreq, false,
5231                                                   true);
5232                                 if (err) {
5233                                         mlx5_ib_warn(dev, "\n");
5234                                         err = -ENOMEM;
5235                                         *bad_wr = wr;
5236                                         goto out;
5237                                 }
5238                                 err = set_psv_wr(&sig_attrs->wire,
5239                                                  mr->sig->psv_wire.psv_idx,
5240                                                  &seg, &size);
5241                                 if (err) {
5242                                         mlx5_ib_warn(dev, "\n");
5243                                         *bad_wr = wr;
5244                                         goto out;
5245                                 }
5246                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5247                                            wr->wr_id, nreq, next_fence,
5248                                            MLX5_OPCODE_SET_PSV);
5249
5250                                 qp->next_fence =
5251                                         MLX5_FENCE_MODE_INITIATOR_SMALL;
5252                                 num_sge = 0;
5253                                 goto skip_psv;
5254
5255                         default:
5256                                 break;
5257                         }
5258                         break;
5259
5260                 case IB_QPT_UC:
5261                         switch (wr->opcode) {
5262                         case IB_WR_RDMA_WRITE:
5263                         case IB_WR_RDMA_WRITE_WITH_IMM:
5264                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5265                                               rdma_wr(wr)->rkey);
5266                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
5267                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5268                                 break;
5269
5270                         default:
5271                                 break;
5272                         }
5273                         break;
5274
5275                 case IB_QPT_SMI:
5276                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5277                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5278                                 err = -EPERM;
5279                                 *bad_wr = wr;
5280                                 goto out;
5281                         }
5282                         /* fall through */
5283                 case MLX5_IB_QPT_HW_GSI:
5284                         set_datagram_seg(seg, wr);
5285                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5286                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5287                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5288
5289                         break;
5290                 case IB_QPT_UD:
5291                         set_datagram_seg(seg, wr);
5292                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5293                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5294                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5295
5296                         /* handle qp that supports ud offload */
5297                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5298                                 struct mlx5_wqe_eth_pad *pad;
5299
5300                                 pad = seg;
5301                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5302                                 seg += sizeof(struct mlx5_wqe_eth_pad);
5303                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
5304                                 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5305                                 handle_post_send_edge(&qp->sq, &seg, size,
5306                                                       &cur_edge);
5307                         }
5308                         break;
5309                 case MLX5_IB_QPT_REG_UMR:
5310                         if (wr->opcode != MLX5_IB_WR_UMR) {
5311                                 err = -EINVAL;
5312                                 mlx5_ib_warn(dev, "bad opcode\n");
5313                                 goto out;
5314                         }
5315                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
5316                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
5317                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5318                         if (unlikely(err))
5319                                 goto out;
5320                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5321                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5322                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5323                         set_reg_mkey_segment(seg, wr);
5324                         seg += sizeof(struct mlx5_mkey_seg);
5325                         size += sizeof(struct mlx5_mkey_seg) / 16;
5326                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5327                         break;
5328
5329                 default:
5330                         break;
5331                 }
5332
5333                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
5334                         err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
5335                         if (unlikely(err)) {
5336                                 mlx5_ib_warn(dev, "\n");
5337                                 *bad_wr = wr;
5338                                 goto out;
5339                         }
5340                 } else {
5341                         for (i = 0; i < num_sge; i++) {
5342                                 handle_post_send_edge(&qp->sq, &seg, size,
5343                                                       &cur_edge);
5344                                 if (likely(wr->sg_list[i].length)) {
5345                                         set_data_ptr_seg
5346                                         ((struct mlx5_wqe_data_seg *)seg,
5347                                          wr->sg_list + i);
5348                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
5349                                         seg += sizeof(struct mlx5_wqe_data_seg);
5350                                 }
5351                         }
5352                 }
5353
5354                 qp->next_fence = next_fence;
5355                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5356                            fence, mlx5_ib_opcode[wr->opcode]);
5357 skip_psv:
5358                 if (0)
5359                         dump_wqe(qp, idx, size);
5360         }
5361
5362 out:
5363         if (likely(nreq)) {
5364                 qp->sq.head += nreq;
5365
5366                 /* Make sure that descriptors are written before
5367                  * updating doorbell record and ringing the doorbell
5368                  */
5369                 wmb();
5370
5371                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5372
5373                 /* Make sure doorbell record is visible to the HCA before
5374                  * we hit doorbell */
5375                 wmb();
5376
5377                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
5378                 /* Make sure doorbells don't leak out of SQ spinlock
5379                  * and reach the HCA out of order.
5380                  */
5381                 bf->offset ^= bf->buf_size;
5382         }
5383
5384         spin_unlock_irqrestore(&qp->sq.lock, flags);
5385
5386         return err;
5387 }
5388
5389 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5390                       const struct ib_send_wr **bad_wr)
5391 {
5392         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5393 }
5394
5395 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5396 {
5397         sig->signature = calc_sig(sig, size);
5398 }
5399
5400 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5401                       const struct ib_recv_wr **bad_wr, bool drain)
5402 {
5403         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5404         struct mlx5_wqe_data_seg *scat;
5405         struct mlx5_rwqe_sig *sig;
5406         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5407         struct mlx5_core_dev *mdev = dev->mdev;
5408         unsigned long flags;
5409         int err = 0;
5410         int nreq;
5411         int ind;
5412         int i;
5413
5414         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5415                      !drain)) {
5416                 *bad_wr = wr;
5417                 return -EIO;
5418         }
5419
5420         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5421                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5422
5423         spin_lock_irqsave(&qp->rq.lock, flags);
5424
5425         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5426
5427         for (nreq = 0; wr; nreq++, wr = wr->next) {
5428                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5429                         err = -ENOMEM;
5430                         *bad_wr = wr;
5431                         goto out;
5432                 }
5433
5434                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5435                         err = -EINVAL;
5436                         *bad_wr = wr;
5437                         goto out;
5438                 }
5439
5440                 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5441                 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
5442                         scat++;
5443
5444                 for (i = 0; i < wr->num_sge; i++)
5445                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5446
5447                 if (i < qp->rq.max_gs) {
5448                         scat[i].byte_count = 0;
5449                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5450                         scat[i].addr       = 0;
5451                 }
5452
5453                 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) {
5454                         sig = (struct mlx5_rwqe_sig *)scat;
5455                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5456                 }
5457
5458                 qp->rq.wrid[ind] = wr->wr_id;
5459
5460                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5461         }
5462
5463 out:
5464         if (likely(nreq)) {
5465                 qp->rq.head += nreq;
5466
5467                 /* Make sure that descriptors are written before
5468                  * doorbell record.
5469                  */
5470                 wmb();
5471
5472                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5473         }
5474
5475         spin_unlock_irqrestore(&qp->rq.lock, flags);
5476
5477         return err;
5478 }
5479
5480 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5481                       const struct ib_recv_wr **bad_wr)
5482 {
5483         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5484 }
5485
5486 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5487 {
5488         switch (mlx5_state) {
5489         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5490         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5491         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5492         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5493         case MLX5_QP_STATE_SQ_DRAINING:
5494         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5495         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5496         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5497         default:                     return -1;
5498         }
5499 }
5500
5501 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5502 {
5503         switch (mlx5_mig_state) {
5504         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5505         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5506         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5507         default: return -1;
5508         }
5509 }
5510
5511 static int to_ib_qp_access_flags(int mlx5_flags)
5512 {
5513         int ib_flags = 0;
5514
5515         if (mlx5_flags & MLX5_QP_BIT_RRE)
5516                 ib_flags |= IB_ACCESS_REMOTE_READ;
5517         if (mlx5_flags & MLX5_QP_BIT_RWE)
5518                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5519         if (mlx5_flags & MLX5_QP_BIT_RAE)
5520                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5521
5522         return ib_flags;
5523 }
5524
5525 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5526                             struct rdma_ah_attr *ah_attr,
5527                             struct mlx5_qp_path *path)
5528 {
5529
5530         memset(ah_attr, 0, sizeof(*ah_attr));
5531
5532         if (!path->port || path->port > ibdev->num_ports)
5533                 return;
5534
5535         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5536
5537         rdma_ah_set_port_num(ah_attr, path->port);
5538         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5539
5540         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5541         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5542         rdma_ah_set_static_rate(ah_attr,
5543                                 path->static_rate ? path->static_rate - 5 : 0);
5544         if (path->grh_mlid & (1 << 7)) {
5545                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5546
5547                 rdma_ah_set_grh(ah_attr, NULL,
5548                                 tc_fl & 0xfffff,
5549                                 path->mgid_index,
5550                                 path->hop_limit,
5551                                 (tc_fl >> 20) & 0xff);
5552                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5553         }
5554 }
5555
5556 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5557                                         struct mlx5_ib_sq *sq,
5558                                         u8 *sq_state)
5559 {
5560         int err;
5561
5562         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5563         if (err)
5564                 goto out;
5565         sq->state = *sq_state;
5566
5567 out:
5568         return err;
5569 }
5570
5571 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5572                                         struct mlx5_ib_rq *rq,
5573                                         u8 *rq_state)
5574 {
5575         void *out;
5576         void *rqc;
5577         int inlen;
5578         int err;
5579
5580         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5581         out = kvzalloc(inlen, GFP_KERNEL);
5582         if (!out)
5583                 return -ENOMEM;
5584
5585         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5586         if (err)
5587                 goto out;
5588
5589         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5590         *rq_state = MLX5_GET(rqc, rqc, state);
5591         rq->state = *rq_state;
5592
5593 out:
5594         kvfree(out);
5595         return err;
5596 }
5597
5598 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5599                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5600 {
5601         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5602                 [MLX5_RQC_STATE_RST] = {
5603                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5604                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5605                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5606                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5607                 },
5608                 [MLX5_RQC_STATE_RDY] = {
5609                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5610                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5611                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5612                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5613                 },
5614                 [MLX5_RQC_STATE_ERR] = {
5615                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5616                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5617                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5618                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5619                 },
5620                 [MLX5_RQ_STATE_NA] = {
5621                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5622                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5623                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5624                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5625                 },
5626         };
5627
5628         *qp_state = sqrq_trans[rq_state][sq_state];
5629
5630         if (*qp_state == MLX5_QP_STATE_BAD) {
5631                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5632                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5633                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5634                 return -EINVAL;
5635         }
5636
5637         if (*qp_state == MLX5_QP_STATE)
5638                 *qp_state = qp->state;
5639
5640         return 0;
5641 }
5642
5643 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5644                                      struct mlx5_ib_qp *qp,
5645                                      u8 *raw_packet_qp_state)
5646 {
5647         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5648         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5649         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5650         int err;
5651         u8 sq_state = MLX5_SQ_STATE_NA;
5652         u8 rq_state = MLX5_RQ_STATE_NA;
5653
5654         if (qp->sq.wqe_cnt) {
5655                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5656                 if (err)
5657                         return err;
5658         }
5659
5660         if (qp->rq.wqe_cnt) {
5661                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5662                 if (err)
5663                         return err;
5664         }
5665
5666         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5667                                       raw_packet_qp_state);
5668 }
5669
5670 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5671                          struct ib_qp_attr *qp_attr)
5672 {
5673         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5674         struct mlx5_qp_context *context;
5675         int mlx5_state;
5676         u32 *outb;
5677         int err = 0;
5678
5679         outb = kzalloc(outlen, GFP_KERNEL);
5680         if (!outb)
5681                 return -ENOMEM;
5682
5683         err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
5684         if (err)
5685                 goto out;
5686
5687         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5688         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5689
5690         mlx5_state = be32_to_cpu(context->flags) >> 28;
5691
5692         qp->state                    = to_ib_qp_state(mlx5_state);
5693         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5694         qp_attr->path_mig_state      =
5695                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5696         qp_attr->qkey                = be32_to_cpu(context->qkey);
5697         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5698         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5699         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5700         qp_attr->qp_access_flags     =
5701                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5702
5703         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5704                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5705                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5706                 qp_attr->alt_pkey_index =
5707                         be16_to_cpu(context->alt_path.pkey_index);
5708                 qp_attr->alt_port_num   =
5709                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5710         }
5711
5712         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5713         qp_attr->port_num = context->pri_path.port;
5714
5715         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5716         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5717
5718         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5719
5720         qp_attr->max_dest_rd_atomic =
5721                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5722         qp_attr->min_rnr_timer      =
5723                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5724         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5725         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5726         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5727         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5728
5729 out:
5730         kfree(outb);
5731         return err;
5732 }
5733
5734 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5735                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5736                                 struct ib_qp_init_attr *qp_init_attr)
5737 {
5738         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5739         u32 *out;
5740         u32 access_flags = 0;
5741         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5742         void *dctc;
5743         int err;
5744         int supported_mask = IB_QP_STATE |
5745                              IB_QP_ACCESS_FLAGS |
5746                              IB_QP_PORT |
5747                              IB_QP_MIN_RNR_TIMER |
5748                              IB_QP_AV |
5749                              IB_QP_PATH_MTU |
5750                              IB_QP_PKEY_INDEX;
5751
5752         if (qp_attr_mask & ~supported_mask)
5753                 return -EINVAL;
5754         if (mqp->state != IB_QPS_RTR)
5755                 return -EINVAL;
5756
5757         out = kzalloc(outlen, GFP_KERNEL);
5758         if (!out)
5759                 return -ENOMEM;
5760
5761         err = mlx5_core_dct_query(dev, dct, out, outlen);
5762         if (err)
5763                 goto out;
5764
5765         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5766
5767         if (qp_attr_mask & IB_QP_STATE)
5768                 qp_attr->qp_state = IB_QPS_RTR;
5769
5770         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5771                 if (MLX5_GET(dctc, dctc, rre))
5772                         access_flags |= IB_ACCESS_REMOTE_READ;
5773                 if (MLX5_GET(dctc, dctc, rwe))
5774                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5775                 if (MLX5_GET(dctc, dctc, rae))
5776                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5777                 qp_attr->qp_access_flags = access_flags;
5778         }
5779
5780         if (qp_attr_mask & IB_QP_PORT)
5781                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5782         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5783                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5784         if (qp_attr_mask & IB_QP_AV) {
5785                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5786                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5787                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5788                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5789         }
5790         if (qp_attr_mask & IB_QP_PATH_MTU)
5791                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5792         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5793                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5794 out:
5795         kfree(out);
5796         return err;
5797 }
5798
5799 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5800                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5801 {
5802         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5803         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5804         int err = 0;
5805         u8 raw_packet_qp_state;
5806
5807         if (ibqp->rwq_ind_tbl)
5808                 return -ENOSYS;
5809
5810         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5811                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5812                                             qp_init_attr);
5813
5814         /* Not all of output fields are applicable, make sure to zero them */
5815         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5816         memset(qp_attr, 0, sizeof(*qp_attr));
5817
5818         if (unlikely(qp->type == MLX5_IB_QPT_DCT))
5819                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5820                                             qp_attr_mask, qp_init_attr);
5821
5822         mutex_lock(&qp->mutex);
5823
5824         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5825             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
5826                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5827                 if (err)
5828                         goto out;
5829                 qp->state = raw_packet_qp_state;
5830                 qp_attr->port_num = 1;
5831         } else {
5832                 err = query_qp_attr(dev, qp, qp_attr);
5833                 if (err)
5834                         goto out;
5835         }
5836
5837         qp_attr->qp_state            = qp->state;
5838         qp_attr->cur_qp_state        = qp_attr->qp_state;
5839         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5840         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5841
5842         if (!ibqp->uobject) {
5843                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5844                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5845                 qp_init_attr->qp_context = ibqp->qp_context;
5846         } else {
5847                 qp_attr->cap.max_send_wr  = 0;
5848                 qp_attr->cap.max_send_sge = 0;
5849         }
5850
5851         qp_init_attr->qp_type = ibqp->qp_type;
5852         qp_init_attr->recv_cq = ibqp->recv_cq;
5853         qp_init_attr->send_cq = ibqp->send_cq;
5854         qp_init_attr->srq = ibqp->srq;
5855         qp_attr->cap.max_inline_data = qp->max_inline_data;
5856
5857         qp_init_attr->cap            = qp_attr->cap;
5858
5859         qp_init_attr->create_flags = qp->flags;
5860
5861         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5862                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5863
5864 out:
5865         mutex_unlock(&qp->mutex);
5866         return err;
5867 }
5868
5869 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5870                                    struct ib_udata *udata)
5871 {
5872         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5873         struct mlx5_ib_xrcd *xrcd;
5874         int err;
5875
5876         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5877                 return ERR_PTR(-ENOSYS);
5878
5879         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5880         if (!xrcd)
5881                 return ERR_PTR(-ENOMEM);
5882
5883         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5884         if (err) {
5885                 kfree(xrcd);
5886                 return ERR_PTR(-ENOMEM);
5887         }
5888
5889         return &xrcd->ibxrcd;
5890 }
5891
5892 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
5893 {
5894         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5895         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5896         int err;
5897
5898         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5899         if (err)
5900                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5901
5902         kfree(xrcd);
5903         return 0;
5904 }
5905
5906 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5907 {
5908         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5909         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5910         struct ib_event event;
5911
5912         if (rwq->ibwq.event_handler) {
5913                 event.device     = rwq->ibwq.device;
5914                 event.element.wq = &rwq->ibwq;
5915                 switch (type) {
5916                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5917                         event.event = IB_EVENT_WQ_FATAL;
5918                         break;
5919                 default:
5920                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5921                         return;
5922                 }
5923
5924                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5925         }
5926 }
5927
5928 static int set_delay_drop(struct mlx5_ib_dev *dev)
5929 {
5930         int err = 0;
5931
5932         mutex_lock(&dev->delay_drop.lock);
5933         if (dev->delay_drop.activate)
5934                 goto out;
5935
5936         err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
5937         if (err)
5938                 goto out;
5939
5940         dev->delay_drop.activate = true;
5941 out:
5942         mutex_unlock(&dev->delay_drop.lock);
5943
5944         if (!err)
5945                 atomic_inc(&dev->delay_drop.rqs_cnt);
5946         return err;
5947 }
5948
5949 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5950                       struct ib_wq_init_attr *init_attr)
5951 {
5952         struct mlx5_ib_dev *dev;
5953         int has_net_offloads;
5954         __be64 *rq_pas0;
5955         void *in;
5956         void *rqc;
5957         void *wq;
5958         int inlen;
5959         int err;
5960
5961         dev = to_mdev(pd->device);
5962
5963         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5964         in = kvzalloc(inlen, GFP_KERNEL);
5965         if (!in)
5966                 return -ENOMEM;
5967
5968         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5969         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5970         MLX5_SET(rqc,  rqc, mem_rq_type,
5971                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5972         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5973         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5974         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5975         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5976         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5977         MLX5_SET(wq, wq, wq_type,
5978                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5979                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5980         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5981                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5982                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5983                         err = -EOPNOTSUPP;
5984                         goto out;
5985                 } else {
5986                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5987                 }
5988         }
5989         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5990         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5991                 /*
5992                  * In Firmware number of strides in each WQE is:
5993                  *   "512 * 2^single_wqe_log_num_of_strides"
5994                  * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
5995                  * accepted as 0 to 9
5996                  */
5997                 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
5998                                              2,  3,  4,  5,  6,  7,  8, 9 };
5999                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
6000                 MLX5_SET(wq, wq, log_wqe_stride_size,
6001                          rwq->single_stride_log_num_of_bytes -
6002                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
6003                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
6004                          fw_map[rwq->log_num_strides -
6005                                 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
6006         }
6007         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
6008         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
6009         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
6010         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
6011         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
6012         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
6013         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
6014         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6015                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6016                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
6017                         err = -EOPNOTSUPP;
6018                         goto out;
6019                 }
6020         } else {
6021                 MLX5_SET(rqc, rqc, vsd, 1);
6022         }
6023         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
6024                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
6025                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
6026                         err = -EOPNOTSUPP;
6027                         goto out;
6028                 }
6029                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
6030         }
6031         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6032                 if (!(dev->ib_dev.attrs.raw_packet_caps &
6033                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
6034                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
6035                         err = -EOPNOTSUPP;
6036                         goto out;
6037                 }
6038                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
6039         }
6040         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
6041         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
6042         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
6043         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6044                 err = set_delay_drop(dev);
6045                 if (err) {
6046                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
6047                                      err);
6048                         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6049                 } else {
6050                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
6051                 }
6052         }
6053 out:
6054         kvfree(in);
6055         return err;
6056 }
6057
6058 static int set_user_rq_size(struct mlx5_ib_dev *dev,
6059                             struct ib_wq_init_attr *wq_init_attr,
6060                             struct mlx5_ib_create_wq *ucmd,
6061                             struct mlx5_ib_rwq *rwq)
6062 {
6063         /* Sanity check RQ size before proceeding */
6064         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
6065                 return -EINVAL;
6066
6067         if (!ucmd->rq_wqe_count)
6068                 return -EINVAL;
6069
6070         rwq->wqe_count = ucmd->rq_wqe_count;
6071         rwq->wqe_shift = ucmd->rq_wqe_shift;
6072         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
6073                 return -EINVAL;
6074
6075         rwq->log_rq_stride = rwq->wqe_shift;
6076         rwq->log_rq_size = ilog2(rwq->wqe_count);
6077         return 0;
6078 }
6079
6080 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
6081 {
6082         if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
6083             (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
6084                 return false;
6085
6086         if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
6087             (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
6088                 return false;
6089
6090         return true;
6091 }
6092
6093 static int prepare_user_rq(struct ib_pd *pd,
6094                            struct ib_wq_init_attr *init_attr,
6095                            struct ib_udata *udata,
6096                            struct mlx5_ib_rwq *rwq)
6097 {
6098         struct mlx5_ib_dev *dev = to_mdev(pd->device);
6099         struct mlx5_ib_create_wq ucmd = {};
6100         int err;
6101         size_t required_cmd_sz;
6102
6103         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
6104                 + sizeof(ucmd.single_stride_log_num_of_bytes);
6105         if (udata->inlen < required_cmd_sz) {
6106                 mlx5_ib_dbg(dev, "invalid inlen\n");
6107                 return -EINVAL;
6108         }
6109
6110         if (udata->inlen > sizeof(ucmd) &&
6111             !ib_is_udata_cleared(udata, sizeof(ucmd),
6112                                  udata->inlen - sizeof(ucmd))) {
6113                 mlx5_ib_dbg(dev, "inlen is not supported\n");
6114                 return -EOPNOTSUPP;
6115         }
6116
6117         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
6118                 mlx5_ib_dbg(dev, "copy failed\n");
6119                 return -EFAULT;
6120         }
6121
6122         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
6123                 mlx5_ib_dbg(dev, "invalid comp mask\n");
6124                 return -EOPNOTSUPP;
6125         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
6126                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
6127                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
6128                         return -EOPNOTSUPP;
6129                 }
6130                 if ((ucmd.single_stride_log_num_of_bytes <
6131                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
6132                     (ucmd.single_stride_log_num_of_bytes >
6133                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
6134                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
6135                                     ucmd.single_stride_log_num_of_bytes,
6136                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
6137                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
6138                         return -EINVAL;
6139                 }
6140                 if (!log_of_strides_valid(dev,
6141                                           ucmd.single_wqe_log_num_of_strides)) {
6142                         mlx5_ib_dbg(
6143                                 dev,
6144                                 "Invalid log num strides (%u. Range is %u - %u)\n",
6145                                 ucmd.single_wqe_log_num_of_strides,
6146                                 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
6147                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
6148                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
6149                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
6150                         return -EINVAL;
6151                 }
6152                 rwq->single_stride_log_num_of_bytes =
6153                         ucmd.single_stride_log_num_of_bytes;
6154                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
6155                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
6156                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
6157         }
6158
6159         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
6160         if (err) {
6161                 mlx5_ib_dbg(dev, "err %d\n", err);
6162                 return err;
6163         }
6164
6165         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
6166         if (err) {
6167                 mlx5_ib_dbg(dev, "err %d\n", err);
6168                 return err;
6169         }
6170
6171         rwq->user_index = ucmd.user_index;
6172         return 0;
6173 }
6174
6175 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
6176                                 struct ib_wq_init_attr *init_attr,
6177                                 struct ib_udata *udata)
6178 {
6179         struct mlx5_ib_dev *dev;
6180         struct mlx5_ib_rwq *rwq;
6181         struct mlx5_ib_create_wq_resp resp = {};
6182         size_t min_resp_len;
6183         int err;
6184
6185         if (!udata)
6186                 return ERR_PTR(-ENOSYS);
6187
6188         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6189         if (udata->outlen && udata->outlen < min_resp_len)
6190                 return ERR_PTR(-EINVAL);
6191
6192         if (!capable(CAP_SYS_RAWIO) &&
6193             init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
6194                 return ERR_PTR(-EPERM);
6195
6196         dev = to_mdev(pd->device);
6197         switch (init_attr->wq_type) {
6198         case IB_WQT_RQ:
6199                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
6200                 if (!rwq)
6201                         return ERR_PTR(-ENOMEM);
6202                 err = prepare_user_rq(pd, init_attr, udata, rwq);
6203                 if (err)
6204                         goto err;
6205                 err = create_rq(rwq, pd, init_attr);
6206                 if (err)
6207                         goto err_user_rq;
6208                 break;
6209         default:
6210                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
6211                             init_attr->wq_type);
6212                 return ERR_PTR(-EINVAL);
6213         }
6214
6215         rwq->ibwq.wq_num = rwq->core_qp.qpn;
6216         rwq->ibwq.state = IB_WQS_RESET;
6217         if (udata->outlen) {
6218                 resp.response_length = offsetof(typeof(resp), response_length) +
6219                                 sizeof(resp.response_length);
6220                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6221                 if (err)
6222                         goto err_copy;
6223         }
6224
6225         rwq->core_qp.event = mlx5_ib_wq_event;
6226         rwq->ibwq.event_handler = init_attr->event_handler;
6227         return &rwq->ibwq;
6228
6229 err_copy:
6230         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6231 err_user_rq:
6232         destroy_user_rq(dev, pd, rwq, udata);
6233 err:
6234         kfree(rwq);
6235         return ERR_PTR(err);
6236 }
6237
6238 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
6239 {
6240         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6241         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6242
6243         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6244         destroy_user_rq(dev, wq->pd, rwq, udata);
6245         kfree(rwq);
6246 }
6247
6248 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
6249                                                       struct ib_rwq_ind_table_init_attr *init_attr,
6250                                                       struct ib_udata *udata)
6251 {
6252         struct mlx5_ib_dev *dev = to_mdev(device);
6253         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
6254         int sz = 1 << init_attr->log_ind_tbl_size;
6255         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
6256         size_t min_resp_len;
6257         int inlen;
6258         int err;
6259         int i;
6260         u32 *in;
6261         void *rqtc;
6262
6263         if (udata->inlen > 0 &&
6264             !ib_is_udata_cleared(udata, 0,
6265                                  udata->inlen))
6266                 return ERR_PTR(-EOPNOTSUPP);
6267
6268         if (init_attr->log_ind_tbl_size >
6269             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
6270                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
6271                             init_attr->log_ind_tbl_size,
6272                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
6273                 return ERR_PTR(-EINVAL);
6274         }
6275
6276         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6277         if (udata->outlen && udata->outlen < min_resp_len)
6278                 return ERR_PTR(-EINVAL);
6279
6280         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6281         if (!rwq_ind_tbl)
6282                 return ERR_PTR(-ENOMEM);
6283
6284         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
6285         in = kvzalloc(inlen, GFP_KERNEL);
6286         if (!in) {
6287                 err = -ENOMEM;
6288                 goto err;
6289         }
6290
6291         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6292
6293         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6294         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6295
6296         for (i = 0; i < sz; i++)
6297                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6298
6299         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6300         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6301
6302         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6303         kvfree(in);
6304
6305         if (err)
6306                 goto err;
6307
6308         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6309         if (udata->outlen) {
6310                 resp.response_length = offsetof(typeof(resp), response_length) +
6311                                         sizeof(resp.response_length);
6312                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6313                 if (err)
6314                         goto err_copy;
6315         }
6316
6317         return &rwq_ind_tbl->ib_rwq_ind_tbl;
6318
6319 err_copy:
6320         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6321 err:
6322         kfree(rwq_ind_tbl);
6323         return ERR_PTR(err);
6324 }
6325
6326 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6327 {
6328         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6329         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6330
6331         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6332
6333         kfree(rwq_ind_tbl);
6334         return 0;
6335 }
6336
6337 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6338                       u32 wq_attr_mask, struct ib_udata *udata)
6339 {
6340         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6341         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6342         struct mlx5_ib_modify_wq ucmd = {};
6343         size_t required_cmd_sz;
6344         int curr_wq_state;
6345         int wq_state;
6346         int inlen;
6347         int err;
6348         void *rqc;
6349         void *in;
6350
6351         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6352         if (udata->inlen < required_cmd_sz)
6353                 return -EINVAL;
6354
6355         if (udata->inlen > sizeof(ucmd) &&
6356             !ib_is_udata_cleared(udata, sizeof(ucmd),
6357                                  udata->inlen - sizeof(ucmd)))
6358                 return -EOPNOTSUPP;
6359
6360         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6361                 return -EFAULT;
6362
6363         if (ucmd.comp_mask || ucmd.reserved)
6364                 return -EOPNOTSUPP;
6365
6366         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
6367         in = kvzalloc(inlen, GFP_KERNEL);
6368         if (!in)
6369                 return -ENOMEM;
6370
6371         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6372
6373         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6374                 wq_attr->curr_wq_state : wq->state;
6375         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6376                 wq_attr->wq_state : curr_wq_state;
6377         if (curr_wq_state == IB_WQS_ERR)
6378                 curr_wq_state = MLX5_RQC_STATE_ERR;
6379         if (wq_state == IB_WQS_ERR)
6380                 wq_state = MLX5_RQC_STATE_ERR;
6381         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6382         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6383         MLX5_SET(rqc, rqc, state, wq_state);
6384
6385         if (wq_attr_mask & IB_WQ_FLAGS) {
6386                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6387                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6388                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6389                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
6390                                             "supported\n");
6391                                 err = -EOPNOTSUPP;
6392                                 goto out;
6393                         }
6394                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6395                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6396                         MLX5_SET(rqc, rqc, vsd,
6397                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6398                 }
6399
6400                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6401                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6402                         err = -EOPNOTSUPP;
6403                         goto out;
6404                 }
6405         }
6406
6407         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6408                 u16 set_id;
6409
6410                 set_id = mlx5_ib_get_counters_id(dev, 0);
6411                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6412                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6413                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6414                         MLX5_SET(rqc, rqc, counter_set_id, set_id);
6415                 } else
6416                         dev_info_once(
6417                                 &dev->ib_dev.dev,
6418                                 "Receive WQ counters are not supported on current FW\n");
6419         }
6420
6421         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
6422         if (!err)
6423                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6424
6425 out:
6426         kvfree(in);
6427         return err;
6428 }
6429
6430 struct mlx5_ib_drain_cqe {
6431         struct ib_cqe cqe;
6432         struct completion done;
6433 };
6434
6435 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6436 {
6437         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6438                                                      struct mlx5_ib_drain_cqe,
6439                                                      cqe);
6440
6441         complete(&cqe->done);
6442 }
6443
6444 /* This function returns only once the drained WR was completed */
6445 static void handle_drain_completion(struct ib_cq *cq,
6446                                     struct mlx5_ib_drain_cqe *sdrain,
6447                                     struct mlx5_ib_dev *dev)
6448 {
6449         struct mlx5_core_dev *mdev = dev->mdev;
6450
6451         if (cq->poll_ctx == IB_POLL_DIRECT) {
6452                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6453                         ib_process_cq_direct(cq, -1);
6454                 return;
6455         }
6456
6457         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6458                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6459                 bool triggered = false;
6460                 unsigned long flags;
6461
6462                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6463                 /* Make sure that the CQ handler won't run if wasn't run yet */
6464                 if (!mcq->mcq.reset_notify_added)
6465                         mcq->mcq.reset_notify_added = 1;
6466                 else
6467                         triggered = true;
6468                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6469
6470                 if (triggered) {
6471                         /* Wait for any scheduled/running task to be ended */
6472                         switch (cq->poll_ctx) {
6473                         case IB_POLL_SOFTIRQ:
6474                                 irq_poll_disable(&cq->iop);
6475                                 irq_poll_enable(&cq->iop);
6476                                 break;
6477                         case IB_POLL_WORKQUEUE:
6478                                 cancel_work_sync(&cq->work);
6479                                 break;
6480                         default:
6481                                 WARN_ON_ONCE(1);
6482                         }
6483                 }
6484
6485                 /* Run the CQ handler - this makes sure that the drain WR will
6486                  * be processed if wasn't processed yet.
6487                  */
6488                 mcq->mcq.comp(&mcq->mcq, NULL);
6489         }
6490
6491         wait_for_completion(&sdrain->done);
6492 }
6493
6494 void mlx5_ib_drain_sq(struct ib_qp *qp)
6495 {
6496         struct ib_cq *cq = qp->send_cq;
6497         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6498         struct mlx5_ib_drain_cqe sdrain;
6499         const struct ib_send_wr *bad_swr;
6500         struct ib_rdma_wr swr = {
6501                 .wr = {
6502                         .next = NULL,
6503                         { .wr_cqe       = &sdrain.cqe, },
6504                         .opcode = IB_WR_RDMA_WRITE,
6505                 },
6506         };
6507         int ret;
6508         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6509         struct mlx5_core_dev *mdev = dev->mdev;
6510
6511         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6512         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6513                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6514                 return;
6515         }
6516
6517         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6518         init_completion(&sdrain.done);
6519
6520         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6521         if (ret) {
6522                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6523                 return;
6524         }
6525
6526         handle_drain_completion(cq, &sdrain, dev);
6527 }
6528
6529 void mlx5_ib_drain_rq(struct ib_qp *qp)
6530 {
6531         struct ib_cq *cq = qp->recv_cq;
6532         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6533         struct mlx5_ib_drain_cqe rdrain;
6534         struct ib_recv_wr rwr = {};
6535         const struct ib_recv_wr *bad_rwr;
6536         int ret;
6537         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6538         struct mlx5_core_dev *mdev = dev->mdev;
6539
6540         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6541         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6542                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6543                 return;
6544         }
6545
6546         rwr.wr_cqe = &rdrain.cqe;
6547         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6548         init_completion(&rdrain.done);
6549
6550         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6551         if (ret) {
6552                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6553                 return;
6554         }
6555
6556         handle_drain_completion(cq, &rdrain, dev);
6557 }
6558
6559 /**
6560  * Bind a qp to a counter. If @counter is NULL then bind the qp to
6561  * the default counter
6562  */
6563 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
6564 {
6565         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6566         struct mlx5_ib_qp *mqp = to_mqp(qp);
6567         int err = 0;
6568
6569         mutex_lock(&mqp->mutex);
6570         if (mqp->state == IB_QPS_RESET) {
6571                 qp->counter = counter;
6572                 goto out;
6573         }
6574
6575         if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
6576                 err = -EOPNOTSUPP;
6577                 goto out;
6578         }
6579
6580         if (mqp->state == IB_QPS_RTS) {
6581                 err = __mlx5_ib_qp_set_counter(qp, counter);
6582                 if (!err)
6583                         qp->counter = counter;
6584
6585                 goto out;
6586         }
6587
6588         mqp->counter_pending = 1;
6589         qp->counter = counter;
6590
6591 out:
6592         mutex_unlock(&mqp->mutex);
6593         return err;
6594 }