drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <rdma/rdma_counter.h>
  38 #include <linux/mlx5/fs.h>
  39 #include "mlx5_ib.h"
  40 #include "ib_rep.h"
  41 #include "cmd.h"
  42 #include "qp.h"
  43
  44 enum {
  45         MLX5_IB_ACK_REQ_FREQ    = 8,
  46 };
  47
  48 enum {
  49         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  50         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  51         MLX5_IB_LINK_TYPE_IB            = 0,
  52         MLX5_IB_LINK_TYPE_ETH           = 1
  53 };
  54
  55 enum {
  56         MLX5_IB_SQ_STRIDE       = 6,
  57         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  58 };
  59
  60 static const u32 mlx5_ib_opcode[] = {
  61         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  62         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  63         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  64         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  65         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  66         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  67         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  68         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  69         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  70         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  71         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  72         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  73         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  74         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  75 };
  76
  77 struct mlx5_wqe_eth_pad {
  78         u8 rsvd0[16];
  79 };
  80
  81 enum raw_qp_set_mask_map {
  82         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  83         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  84 };
  85
  86 struct mlx5_modify_raw_qp_param {
  87         u16 operation;
  88
  89         u32 set_mask; /* raw_qp_set_mask_map */
  90
  91         struct mlx5_rate_limit rl;
  92
  93         u8 rq_q_ctr_id;
  94         u16 port;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 /**
 112  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
 113  * to kernel buffer
 114  *
 115  * @umem: User space memory where the WQ is
 116  * @buffer: buffer to copy to
 117  * @buflen: buffer length
 118  * @wqe_index: index of WQE to copy from
 119  * @wq_offset: offset to start of WQ
 120  * @wq_wqe_cnt: number of WQEs in WQ
 121  * @wq_wqe_shift: log2 of WQE size
 122  * @bcnt: number of bytes to copy
 123  * @bytes_copied: number of bytes to copy (return value)
 124  *
 125  * Copies from start of WQE bcnt or less bytes.
 126  * Does not gurantee to copy the entire WQE.
 127  *
 128  * Return: zero on success, or an error code.
 129  */
 130 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
 131                                         size_t buflen, int wqe_index,
 132                                         int wq_offset, int wq_wqe_cnt,
 133                                         int wq_wqe_shift, int bcnt,
 134                                         size_t *bytes_copied)
 135 {
 136         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 137         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 138         size_t copy_length;
 139         int ret;
 140
 141         /* don't copy more than requested, more than buffer length or
 142          * beyond WQ end
 143          */
 144         copy_length = min_t(u32, buflen, wq_end - offset);
 145         copy_length = min_t(u32, copy_length, bcnt);
 146
 147         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 148         if (ret)
 149                 return ret;
 150
 151         if (!ret && bytes_copied)
 152                 *bytes_copied = copy_length;
 153
 154         return 0;
 155 }
 156
 157 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 158                                       void *buffer, size_t buflen, size_t *bc)
 159 {
 160         struct mlx5_wqe_ctrl_seg *ctrl;
 161         size_t bytes_copied = 0;
 162         size_t wqe_length;
 163         void *p;
 164         int ds;
 165
 166         wqe_index = wqe_index & qp->sq.fbc.sz_m1;
 167
 168         /* read the control segment first */
 169         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 170         ctrl = p;
 171         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 172         wqe_length = ds * MLX5_WQE_DS_UNITS;
 173
 174         /* read rest of WQE if it spreads over more than one stride */
 175         while (bytes_copied < wqe_length) {
 176                 size_t copy_length =
 177                         min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
 178
 179                 if (!copy_length)
 180                         break;
 181
 182                 memcpy(buffer + bytes_copied, p, copy_length);
 183                 bytes_copied += copy_length;
 184
 185                 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
 186                 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 187         }
 188         *bc = bytes_copied;
 189         return 0;
 190 }
 191
 192 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 193                                     void *buffer, size_t buflen, size_t *bc)
 194 {
 195         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 196         struct ib_umem *umem = base->ubuffer.umem;
 197         struct mlx5_ib_wq *wq = &qp->sq;
 198         struct mlx5_wqe_ctrl_seg *ctrl;
 199         size_t bytes_copied;
 200         size_t bytes_copied2;
 201         size_t wqe_length;
 202         int ret;
 203         int ds;
 204
 205         /* at first read as much as possible */
 206         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 207                                            wq->offset, wq->wqe_cnt,
 208                                            wq->wqe_shift, buflen,
 209                                            &bytes_copied);
 210         if (ret)
 211                 return ret;
 212
 213         /* we need at least control segment size to proceed */
 214         if (bytes_copied < sizeof(*ctrl))
 215                 return -EINVAL;
 216
 217         ctrl = buffer;
 218         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 219         wqe_length = ds * MLX5_WQE_DS_UNITS;
 220
 221         /* if we copied enough then we are done */
 222         if (bytes_copied >= wqe_length) {
 223                 *bc = bytes_copied;
 224                 return 0;
 225         }
 226
 227         /* otherwise this a wrapped around wqe
 228          * so read the remaining bytes starting
 229          * from  wqe_index 0
 230          */
 231         ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
 232                                            buflen - bytes_copied, 0, wq->offset,
 233                                            wq->wqe_cnt, wq->wqe_shift,
 234                                            wqe_length - bytes_copied,
 235                                            &bytes_copied2);
 236
 237         if (ret)
 238                 return ret;
 239         *bc = bytes_copied + bytes_copied2;
 240         return 0;
 241 }
 242
 243 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 244                         size_t buflen, size_t *bc)
 245 {
 246         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 247         struct ib_umem *umem = base->ubuffer.umem;
 248
 249         if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
 250                 return -EINVAL;
 251
 252         if (!umem)
 253                 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
 254                                                   buflen, bc);
 255
 256         return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
 257 }
 258
 259 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
 260                                     void *buffer, size_t buflen, size_t *bc)
 261 {
 262         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 263         struct ib_umem *umem = base->ubuffer.umem;
 264         struct mlx5_ib_wq *wq = &qp->rq;
 265         size_t bytes_copied;
 266         int ret;
 267
 268         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 269                                            wq->offset, wq->wqe_cnt,
 270                                            wq->wqe_shift, buflen,
 271                                            &bytes_copied);
 272
 273         if (ret)
 274                 return ret;
 275         *bc = bytes_copied;
 276         return 0;
 277 }
 278
 279 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 280                         size_t buflen, size_t *bc)
 281 {
 282         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 283         struct ib_umem *umem = base->ubuffer.umem;
 284         struct mlx5_ib_wq *wq = &qp->rq;
 285         size_t wqe_size = 1 << wq->wqe_shift;
 286
 287         if (buflen < wqe_size)
 288                 return -EINVAL;
 289
 290         if (!umem)
 291                 return -EOPNOTSUPP;
 292
 293         return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
 294 }
 295
 296 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
 297                                      void *buffer, size_t buflen, size_t *bc)
 298 {
 299         struct ib_umem *umem = srq->umem;
 300         size_t bytes_copied;
 301         int ret;
 302
 303         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
 304                                            srq->msrq.max, srq->msrq.wqe_shift,
 305                                            buflen, &bytes_copied);
 306
 307         if (ret)
 308                 return ret;
 309         *bc = bytes_copied;
 310         return 0;
 311 }
 312
 313 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
 314                          size_t buflen, size_t *bc)
 315 {
 316         struct ib_umem *umem = srq->umem;
 317         size_t wqe_size = 1 << srq->msrq.wqe_shift;
 318
 319         if (buflen < wqe_size)
 320                 return -EINVAL;
 321
 322         if (!umem)
 323                 return -EOPNOTSUPP;
 324
 325         return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
 326 }
 327
 328 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 329 {
 330         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 331         struct ib_event event;
 332
 333         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 334                 /* This event is only valid for trans_qps */
 335                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 336         }
 337
 338         if (ibqp->event_handler) {
 339                 event.device     = ibqp->device;
 340                 event.element.qp = ibqp;
 341                 switch (type) {
 342                 case MLX5_EVENT_TYPE_PATH_MIG:
 343                         event.event = IB_EVENT_PATH_MIG;
 344                         break;
 345                 case MLX5_EVENT_TYPE_COMM_EST:
 346                         event.event = IB_EVENT_COMM_EST;
 347                         break;
 348                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 349                         event.event = IB_EVENT_SQ_DRAINED;
 350                         break;
 351                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 352                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 353                         break;
 354                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 355                         event.event = IB_EVENT_QP_FATAL;
 356                         break;
 357                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 358                         event.event = IB_EVENT_PATH_MIG_ERR;
 359                         break;
 360                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 361                         event.event = IB_EVENT_QP_REQ_ERR;
 362                         break;
 363                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 364                         event.event = IB_EVENT_QP_ACCESS_ERR;
 365                         break;
 366                 default:
 367                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 368                         return;
 369                 }
 370
 371                 ibqp->event_handler(&event, ibqp->qp_context);
 372         }
 373 }
 374
 375 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 376                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 377 {
 378         int wqe_size;
 379         int wq_size;
 380
 381         /* Sanity check RQ size before proceeding */
 382         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 383                 return -EINVAL;
 384
 385         if (!has_rq) {
 386                 qp->rq.max_gs = 0;
 387                 qp->rq.wqe_cnt = 0;
 388                 qp->rq.wqe_shift = 0;
 389                 cap->max_recv_wr = 0;
 390                 cap->max_recv_sge = 0;
 391         } else {
 392                 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
 393
 394                 if (ucmd) {
 395                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 396                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 397                                 return -EINVAL;
 398                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 399                         if ((1 << qp->rq.wqe_shift) /
 400                                     sizeof(struct mlx5_wqe_data_seg) <
 401                             wq_sig)
 402                                 return -EINVAL;
 403                         qp->rq.max_gs =
 404                                 (1 << qp->rq.wqe_shift) /
 405                                         sizeof(struct mlx5_wqe_data_seg) -
 406                                 wq_sig;
 407                         qp->rq.max_post = qp->rq.wqe_cnt;
 408                 } else {
 409                         wqe_size =
 410                                 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
 411                                          0;
 412                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 413                         wqe_size = roundup_pow_of_two(wqe_size);
 414                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 415                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 416                         qp->rq.wqe_cnt = wq_size / wqe_size;
 417                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 418                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 419                                             wqe_size,
 420                                             MLX5_CAP_GEN(dev->mdev,
 421                                                          max_wqe_sz_rq));
 422                                 return -EINVAL;
 423                         }
 424                         qp->rq.wqe_shift = ilog2(wqe_size);
 425                         qp->rq.max_gs =
 426                                 (1 << qp->rq.wqe_shift) /
 427                                         sizeof(struct mlx5_wqe_data_seg) -
 428                                 wq_sig;
 429                         qp->rq.max_post = qp->rq.wqe_cnt;
 430                 }
 431         }
 432
 433         return 0;
 434 }
 435
 436 static int sq_overhead(struct ib_qp_init_attr *attr)
 437 {
 438         int size = 0;
 439
 440         switch (attr->qp_type) {
 441         case IB_QPT_XRC_INI:
 442                 size += sizeof(struct mlx5_wqe_xrc_seg);
 443                 /* fall through */
 444         case IB_QPT_RC:
 445                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 446                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 447                             sizeof(struct mlx5_wqe_raddr_seg),
 448                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 449                             sizeof(struct mlx5_mkey_seg) +
 450                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 451                             MLX5_IB_UMR_OCTOWORD);
 452                 break;
 453
 454         case IB_QPT_XRC_TGT:
 455                 return 0;
 456
 457         case IB_QPT_UC:
 458                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 459                         max(sizeof(struct mlx5_wqe_raddr_seg),
 460                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 461                             sizeof(struct mlx5_mkey_seg));
 462                 break;
 463
 464         case IB_QPT_UD:
 465                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 466                         size += sizeof(struct mlx5_wqe_eth_pad) +
 467                                 sizeof(struct mlx5_wqe_eth_seg);
 468                 /* fall through */
 469         case IB_QPT_SMI:
 470         case MLX5_IB_QPT_HW_GSI:
 471                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 472                         sizeof(struct mlx5_wqe_datagram_seg);
 473                 break;
 474
 475         case MLX5_IB_QPT_REG_UMR:
 476                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 477                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 478                         sizeof(struct mlx5_mkey_seg);
 479                 break;
 480
 481         default:
 482                 return -EINVAL;
 483         }
 484
 485         return size;
 486 }
 487
 488 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 489 {
 490         int inl_size = 0;
 491         int size;
 492
 493         size = sq_overhead(attr);
 494         if (size < 0)
 495                 return size;
 496
 497         if (attr->cap.max_inline_data) {
 498                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 499                         attr->cap.max_inline_data;
 500         }
 501
 502         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 503         if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
 504             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 505                 return MLX5_SIG_WQE_SIZE;
 506         else
 507                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 508 }
 509
 510 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 511 {
 512         int max_sge;
 513
 514         if (attr->qp_type == IB_QPT_RC)
 515                 max_sge = (min_t(int, wqe_size, 512) -
 516                            sizeof(struct mlx5_wqe_ctrl_seg) -
 517                            sizeof(struct mlx5_wqe_raddr_seg)) /
 518                         sizeof(struct mlx5_wqe_data_seg);
 519         else if (attr->qp_type == IB_QPT_XRC_INI)
 520                 max_sge = (min_t(int, wqe_size, 512) -
 521                            sizeof(struct mlx5_wqe_ctrl_seg) -
 522                            sizeof(struct mlx5_wqe_xrc_seg) -
 523                            sizeof(struct mlx5_wqe_raddr_seg)) /
 524                         sizeof(struct mlx5_wqe_data_seg);
 525         else
 526                 max_sge = (wqe_size - sq_overhead(attr)) /
 527                         sizeof(struct mlx5_wqe_data_seg);
 528
 529         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 530                      sizeof(struct mlx5_wqe_data_seg));
 531 }
 532
 533 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 534                         struct mlx5_ib_qp *qp)
 535 {
 536         int wqe_size;
 537         int wq_size;
 538
 539         if (!attr->cap.max_send_wr)
 540                 return 0;
 541
 542         wqe_size = calc_send_wqe(attr);
 543         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 544         if (wqe_size < 0)
 545                 return wqe_size;
 546
 547         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 548                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 549                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 550                 return -EINVAL;
 551         }
 552
 553         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 554                               sizeof(struct mlx5_wqe_inline_seg);
 555         attr->cap.max_inline_data = qp->max_inline_data;
 556
 557         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 558         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 559         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 560                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 561                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 562                             qp->sq.wqe_cnt,
 563                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 564                 return -ENOMEM;
 565         }
 566         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 567         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 568         if (qp->sq.max_gs < attr->cap.max_send_sge)
 569                 return -ENOMEM;
 570
 571         attr->cap.max_send_sge = qp->sq.max_gs;
 572         qp->sq.max_post = wq_size / wqe_size;
 573         attr->cap.max_send_wr = qp->sq.max_post;
 574
 575         return wq_size;
 576 }
 577
 578 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 579                             struct mlx5_ib_qp *qp,
 580                             struct mlx5_ib_create_qp *ucmd,
 581                             struct mlx5_ib_qp_base *base,
 582                             struct ib_qp_init_attr *attr)
 583 {
 584         int desc_sz = 1 << qp->sq.wqe_shift;
 585
 586         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 587                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 588                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 589                 return -EINVAL;
 590         }
 591
 592         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 593                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 594                              ucmd->sq_wqe_count);
 595                 return -EINVAL;
 596         }
 597
 598         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 599
 600         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 601                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 602                              qp->sq.wqe_cnt,
 603                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 604                 return -EINVAL;
 605         }
 606
 607         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 608             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
 609                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 610                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 611         } else {
 612                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 613                                          (qp->sq.wqe_cnt << 6);
 614         }
 615
 616         return 0;
 617 }
 618
 619 static int qp_has_rq(struct ib_qp_init_attr *attr)
 620 {
 621         if (attr->qp_type == IB_QPT_XRC_INI ||
 622             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 623             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 624             !attr->cap.max_recv_wr)
 625                 return 0;
 626
 627         return 1;
 628 }
 629
 630 enum {
 631         /* this is the first blue flame register in the array of bfregs assigned
 632          * to a processes. Since we do not use it for blue flame but rather
 633          * regular 64 bit doorbells, we do not need a lock for maintaiing
 634          * "odd/even" order
 635          */
 636         NUM_NON_BLUE_FLAME_BFREGS = 1,
 637 };
 638
 639 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 640 {
 641         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 642 }
 643
 644 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 645                          struct mlx5_bfreg_info *bfregi)
 646 {
 647         int n;
 648
 649         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 650             NUM_NON_BLUE_FLAME_BFREGS;
 651
 652         return n >= 0 ? n : 0;
 653 }
 654
 655 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 656                            struct mlx5_bfreg_info *bfregi)
 657 {
 658         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 659 }
 660
 661 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 662                           struct mlx5_bfreg_info *bfregi)
 663 {
 664         int med;
 665
 666         med = num_med_bfreg(dev, bfregi);
 667         return ++med;
 668 }
 669
 670 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 671                                   struct mlx5_bfreg_info *bfregi)
 672 {
 673         int i;
 674
 675         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 676                 if (!bfregi->count[i]) {
 677                         bfregi->count[i]++;
 678                         return i;
 679                 }
 680         }
 681
 682         return -ENOMEM;
 683 }
 684
 685 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 686                                  struct mlx5_bfreg_info *bfregi)
 687 {
 688         int minidx = first_med_bfreg(dev, bfregi);
 689         int i;
 690
 691         if (minidx < 0)
 692                 return minidx;
 693
 694         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 695                 if (bfregi->count[i] < bfregi->count[minidx])
 696                         minidx = i;
 697                 if (!bfregi->count[minidx])
 698                         break;
 699         }
 700
 701         bfregi->count[minidx]++;
 702         return minidx;
 703 }
 704
 705 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 706                        struct mlx5_bfreg_info *bfregi)
 707 {
 708         int bfregn = -ENOMEM;
 709
 710         if (bfregi->lib_uar_dyn)
 711                 return -EINVAL;
 712
 713         mutex_lock(&bfregi->lock);
 714         if (bfregi->ver >= 2) {
 715                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 716                 if (bfregn < 0)
 717                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 718         }
 719
 720         if (bfregn < 0) {
 721                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 722                 bfregn = 0;
 723                 bfregi->count[bfregn]++;
 724         }
 725         mutex_unlock(&bfregi->lock);
 726
 727         return bfregn;
 728 }
 729
 730 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 731 {
 732         mutex_lock(&bfregi->lock);
 733         bfregi->count[bfregn]--;
 734         mutex_unlock(&bfregi->lock);
 735 }
 736
 737 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 738 {
 739         switch (state) {
 740         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 741         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 742         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 743         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 744         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 745         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 746         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 747         default:                return -1;
 748         }
 749 }
 750
 751 static int to_mlx5_st(enum ib_qp_type type)
 752 {
 753         switch (type) {
 754         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 755         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 756         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 757         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 758         case IB_QPT_XRC_INI:
 759         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 760         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 761         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 762         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 763         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 764         case IB_QPT_RAW_PACKET:
 765         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 766         case IB_QPT_MAX:
 767         default:                return -EINVAL;
 768         }
 769 }
 770
 771 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 772                              struct mlx5_ib_cq *recv_cq);
 773 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 774                                struct mlx5_ib_cq *recv_cq);
 775
 776 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 777                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 778                         bool dyn_bfreg)
 779 {
 780         unsigned int bfregs_per_sys_page;
 781         u32 index_of_sys_page;
 782         u32 offset;
 783
 784         if (bfregi->lib_uar_dyn)
 785                 return -EINVAL;
 786
 787         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 788                                 MLX5_NON_FP_BFREGS_PER_UAR;
 789         index_of_sys_page = bfregn / bfregs_per_sys_page;
 790
 791         if (dyn_bfreg) {
 792                 index_of_sys_page += bfregi->num_static_sys_pages;
 793
 794                 if (index_of_sys_page >= bfregi->num_sys_pages)
 795                         return -EINVAL;
 796
 797                 if (bfregn > bfregi->num_dyn_bfregs ||
 798                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 799                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 800                         return -EINVAL;
 801                 }
 802         }
 803
 804         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 805         return bfregi->sys_pages[index_of_sys_page] + offset;
 806 }
 807
 808 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 809                             unsigned long addr, size_t size,
 810                             struct ib_umem **umem, int *npages, int *page_shift,
 811                             int *ncont, u32 *offset)
 812 {
 813         int err;
 814
 815         *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
 816         if (IS_ERR(*umem)) {
 817                 mlx5_ib_dbg(dev, "umem_get failed\n");
 818                 return PTR_ERR(*umem);
 819         }
 820
 821         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 822
 823         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 824         if (err) {
 825                 mlx5_ib_warn(dev, "bad offset\n");
 826                 goto err_umem;
 827         }
 828
 829         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 830                     addr, size, *npages, *page_shift, *ncont, *offset);
 831
 832         return 0;
 833
 834 err_umem:
 835         ib_umem_release(*umem);
 836         *umem = NULL;
 837
 838         return err;
 839 }
 840
 841 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 842                             struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
 843 {
 844         struct mlx5_ib_ucontext *context =
 845                 rdma_udata_to_drv_context(
 846                         udata,
 847                         struct mlx5_ib_ucontext,
 848                         ibucontext);
 849
 850         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 851                 atomic_dec(&dev->delay_drop.rqs_cnt);
 852
 853         mlx5_ib_db_unmap_user(context, &rwq->db);
 854         ib_umem_release(rwq->umem);
 855 }
 856
 857 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 858                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 859                           struct mlx5_ib_create_wq *ucmd)
 860 {
 861         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
 862                 udata, struct mlx5_ib_ucontext, ibucontext);
 863         int page_shift = 0;
 864         int npages;
 865         u32 offset = 0;
 866         int ncont = 0;
 867         int err;
 868
 869         if (!ucmd->buf_addr)
 870                 return -EINVAL;
 871
 872         rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
 873         if (IS_ERR(rwq->umem)) {
 874                 mlx5_ib_dbg(dev, "umem_get failed\n");
 875                 err = PTR_ERR(rwq->umem);
 876                 return err;
 877         }
 878
 879         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 880                            &ncont, NULL);
 881         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 882                                      &rwq->rq_page_offset);
 883         if (err) {
 884                 mlx5_ib_warn(dev, "bad offset\n");
 885                 goto err_umem;
 886         }
 887
 888         rwq->rq_num_pas = ncont;
 889         rwq->page_shift = page_shift;
 890         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 891         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 892
 893         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 894                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 895                     npages, page_shift, ncont, offset);
 896
 897         err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
 898         if (err) {
 899                 mlx5_ib_dbg(dev, "map failed\n");
 900                 goto err_umem;
 901         }
 902
 903         rwq->create_type = MLX5_WQ_USER;
 904         return 0;
 905
 906 err_umem:
 907         ib_umem_release(rwq->umem);
 908         return err;
 909 }
 910
 911 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 912                          struct mlx5_bfreg_info *bfregi, int bfregn)
 913 {
 914         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 915                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 916 }
 917
 918 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 919                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 920                           struct ib_qp_init_attr *attr,
 921                           u32 **in,
 922                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 923                           struct mlx5_ib_qp_base *base)
 924 {
 925         struct mlx5_ib_ucontext *context;
 926         struct mlx5_ib_create_qp ucmd;
 927         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 928         int page_shift = 0;
 929         int uar_index = 0;
 930         int npages;
 931         u32 offset = 0;
 932         int bfregn;
 933         int ncont = 0;
 934         __be64 *pas;
 935         void *qpc;
 936         int err;
 937         u16 uid;
 938         u32 uar_flags;
 939
 940         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 941         if (err) {
 942                 mlx5_ib_dbg(dev, "copy failed\n");
 943                 return err;
 944         }
 945
 946         context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
 947                                             ibucontext);
 948         uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX |
 949                                   MLX5_QP_FLAG_BFREG_INDEX);
 950         switch (uar_flags) {
 951         case MLX5_QP_FLAG_UAR_PAGE_INDEX:
 952                 uar_index = ucmd.bfreg_index;
 953                 bfregn = MLX5_IB_INVALID_BFREG;
 954                 break;
 955         case MLX5_QP_FLAG_BFREG_INDEX:
 956                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 957                                                 ucmd.bfreg_index, true);
 958                 if (uar_index < 0)
 959                         return uar_index;
 960                 bfregn = MLX5_IB_INVALID_BFREG;
 961                 break;
 962         case 0:
 963                 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
 964                         return -EINVAL;
 965                 bfregn = alloc_bfreg(dev, &context->bfregi);
 966                 if (bfregn < 0)
 967                         return bfregn;
 968                 break;
 969         default:
 970                 return -EINVAL;
 971         }
 972
 973         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 974         if (bfregn != MLX5_IB_INVALID_BFREG)
 975                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 976                                                 false);
 977
 978         qp->rq.offset = 0;
 979         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 980         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 981
 982         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 983         if (err)
 984                 goto err_bfreg;
 985
 986         if (ucmd.buf_addr && ubuffer->buf_size) {
 987                 ubuffer->buf_addr = ucmd.buf_addr;
 988                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 989                                        ubuffer->buf_size, &ubuffer->umem,
 990                                        &npages, &page_shift, &ncont, &offset);
 991                 if (err)
 992                         goto err_bfreg;
 993         } else {
 994                 ubuffer->umem = NULL;
 995         }
 996
 997         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 998                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 999         *in = kvzalloc(*inlen, GFP_KERNEL);
1000         if (!*in) {
1001                 err = -ENOMEM;
1002                 goto err_umem;
1003         }
1004
1005         uid = (attr->qp_type != IB_QPT_XRC_TGT &&
1006                attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
1007         MLX5_SET(create_qp_in, *in, uid, uid);
1008         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
1009         if (ubuffer->umem)
1010                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
1011
1012         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1013
1014         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1015         MLX5_SET(qpc, qpc, page_offset, offset);
1016
1017         MLX5_SET(qpc, qpc, uar_page, uar_index);
1018         if (bfregn != MLX5_IB_INVALID_BFREG)
1019                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
1020         else
1021                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
1022         qp->bfregn = bfregn;
1023
1024         err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db);
1025         if (err) {
1026                 mlx5_ib_dbg(dev, "map failed\n");
1027                 goto err_free;
1028         }
1029
1030         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1031         if (err) {
1032                 mlx5_ib_dbg(dev, "copy failed\n");
1033                 goto err_unmap;
1034         }
1035         qp->create_type = MLX5_QP_USER;
1036
1037         return 0;
1038
1039 err_unmap:
1040         mlx5_ib_db_unmap_user(context, &qp->db);
1041
1042 err_free:
1043         kvfree(*in);
1044
1045 err_umem:
1046         ib_umem_release(ubuffer->umem);
1047
1048 err_bfreg:
1049         if (bfregn != MLX5_IB_INVALID_BFREG)
1050                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
1051         return err;
1052 }
1053
1054 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1055                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base,
1056                             struct ib_udata *udata)
1057 {
1058         struct mlx5_ib_ucontext *context =
1059                 rdma_udata_to_drv_context(
1060                         udata,
1061                         struct mlx5_ib_ucontext,
1062                         ibucontext);
1063
1064         mlx5_ib_db_unmap_user(context, &qp->db);
1065         ib_umem_release(base->ubuffer.umem);
1066
1067         /*
1068          * Free only the BFREGs which are handled by the kernel.
1069          * BFREGs of UARs allocated dynamically are handled by user.
1070          */
1071         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1072                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1073 }
1074
1075 /* get_sq_edge - Get the next nearby edge.
1076  *
1077  * An 'edge' is defined as the first following address after the end
1078  * of the fragment or the SQ. Accordingly, during the WQE construction
1079  * which repetitively increases the pointer to write the next data, it
1080  * simply should check if it gets to an edge.
1081  *
1082  * @sq - SQ buffer.
1083  * @idx - Stride index in the SQ buffer.
1084  *
1085  * Return:
1086  *      The new edge.
1087  */
1088 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1089 {
1090         void *fragment_end;
1091
1092         fragment_end = mlx5_frag_buf_get_wqe
1093                 (&sq->fbc,
1094                  mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1095
1096         return fragment_end + MLX5_SEND_WQE_BB;
1097 }
1098
1099 static int create_kernel_qp(struct mlx5_ib_dev *dev,
1100                             struct ib_qp_init_attr *init_attr,
1101                             struct mlx5_ib_qp *qp,
1102                             u32 **in, int *inlen,
1103                             struct mlx5_ib_qp_base *base)
1104 {
1105         int uar_index;
1106         void *qpc;
1107         int err;
1108
1109         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1110                 qp->bf.bfreg = &dev->fp_bfreg;
1111         else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
1112                 qp->bf.bfreg = &dev->wc_bfreg;
1113         else
1114                 qp->bf.bfreg = &dev->bfreg;
1115
1116         /* We need to divide by two since each register is comprised of
1117          * two buffers of identical size, namely odd and even
1118          */
1119         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1120         uar_index = qp->bf.bfreg->index;
1121
1122         err = calc_sq_size(dev, init_attr, qp);
1123         if (err < 0) {
1124                 mlx5_ib_dbg(dev, "err %d\n", err);
1125                 return err;
1126         }
1127
1128         qp->rq.offset = 0;
1129         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1130         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1131
1132         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1133                                        &qp->buf, dev->mdev->priv.numa_node);
1134         if (err) {
1135                 mlx5_ib_dbg(dev, "err %d\n", err);
1136                 return err;
1137         }
1138
1139         if (qp->rq.wqe_cnt)
1140                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1141                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1142
1143         if (qp->sq.wqe_cnt) {
1144                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1145                                         MLX5_SEND_WQE_BB;
1146                 mlx5_init_fbc_offset(qp->buf.frags +
1147                                      (qp->sq.offset / PAGE_SIZE),
1148                                      ilog2(MLX5_SEND_WQE_BB),
1149                                      ilog2(qp->sq.wqe_cnt),
1150                                      sq_strides_offset, &qp->sq.fbc);
1151
1152                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1153         }
1154
1155         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1156                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1157         *in = kvzalloc(*inlen, GFP_KERNEL);
1158         if (!*in) {
1159                 err = -ENOMEM;
1160                 goto err_buf;
1161         }
1162
1163         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1164         MLX5_SET(qpc, qpc, uar_page, uar_index);
1165         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1166
1167         /* Set "fast registration enabled" for all kernel QPs */
1168         MLX5_SET(qpc, qpc, fre, 1);
1169         MLX5_SET(qpc, qpc, rlky, 1);
1170
1171         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
1172                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1173
1174         mlx5_fill_page_frag_array(&qp->buf,
1175                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1176                                                          *in, pas));
1177
1178         err = mlx5_db_alloc(dev->mdev, &qp->db);
1179         if (err) {
1180                 mlx5_ib_dbg(dev, "err %d\n", err);
1181                 goto err_free;
1182         }
1183
1184         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1185                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1186         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1187                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1188         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1189                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1190         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1191                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1192         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1193                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1194
1195         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1196             !qp->sq.w_list || !qp->sq.wqe_head) {
1197                 err = -ENOMEM;
1198                 goto err_wrid;
1199         }
1200         qp->create_type = MLX5_QP_KERNEL;
1201
1202         return 0;
1203
1204 err_wrid:
1205         kvfree(qp->sq.wqe_head);
1206         kvfree(qp->sq.w_list);
1207         kvfree(qp->sq.wrid);
1208         kvfree(qp->sq.wr_data);
1209         kvfree(qp->rq.wrid);
1210         mlx5_db_free(dev->mdev, &qp->db);
1211
1212 err_free:
1213         kvfree(*in);
1214
1215 err_buf:
1216         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1217         return err;
1218 }
1219
1220 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1221 {
1222         kvfree(qp->sq.wqe_head);
1223         kvfree(qp->sq.w_list);
1224         kvfree(qp->sq.wrid);
1225         kvfree(qp->sq.wr_data);
1226         kvfree(qp->rq.wrid);
1227         mlx5_db_free(dev->mdev, &qp->db);
1228         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1229 }
1230
1231 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1232 {
1233         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1234             (qp->qp_sub_type == MLX5_IB_QPT_DCI) ||
1235             (attr->qp_type == IB_QPT_XRC_INI))
1236                 return MLX5_SRQ_RQ;
1237         else if (!qp->has_rq)
1238                 return MLX5_ZERO_LEN_RQ;
1239         else
1240                 return MLX5_NON_ZERO_RQ;
1241 }
1242
1243 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1244                                     struct mlx5_ib_qp *qp,
1245                                     struct mlx5_ib_sq *sq, u32 tdn,
1246                                     struct ib_pd *pd)
1247 {
1248         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
1249         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1250
1251         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1252         MLX5_SET(tisc, tisc, transport_domain, tdn);
1253         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1254                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1255
1256         return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1257 }
1258
1259 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1260                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1261 {
1262         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1263 }
1264
1265 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1266 {
1267         if (sq->flow_rule)
1268                 mlx5_del_flow_rules(sq->flow_rule);
1269         sq->flow_rule = NULL;
1270 }
1271
1272 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1273                                    struct ib_udata *udata,
1274                                    struct mlx5_ib_sq *sq, void *qpin,
1275                                    struct ib_pd *pd)
1276 {
1277         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1278         __be64 *pas;
1279         void *in;
1280         void *sqc;
1281         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1282         void *wq;
1283         int inlen;
1284         int err;
1285         int page_shift = 0;
1286         int npages;
1287         int ncont = 0;
1288         u32 offset = 0;
1289
1290         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1291                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1292                                &offset);
1293         if (err)
1294                 return err;
1295
1296         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1297         in = kvzalloc(inlen, GFP_KERNEL);
1298         if (!in) {
1299                 err = -ENOMEM;
1300                 goto err_umem;
1301         }
1302
1303         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1304         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1305         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1306         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1307                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1308         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1309         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1310         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1311         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1312         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1313         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1314             MLX5_CAP_ETH(dev->mdev, swp))
1315                 MLX5_SET(sqc, sqc, allow_swp, 1);
1316
1317         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1318         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1319         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1320         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1321         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1322         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1323         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1324         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1325         MLX5_SET(wq, wq, page_offset, offset);
1326
1327         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1328         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1329
1330         err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
1331
1332         kvfree(in);
1333
1334         if (err)
1335                 goto err_umem;
1336
1337         return 0;
1338
1339 err_umem:
1340         ib_umem_release(sq->ubuffer.umem);
1341         sq->ubuffer.umem = NULL;
1342
1343         return err;
1344 }
1345
1346 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1347                                      struct mlx5_ib_sq *sq)
1348 {
1349         destroy_flow_rule_vport_sq(sq);
1350         mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
1351         ib_umem_release(sq->ubuffer.umem);
1352 }
1353
1354 static size_t get_rq_pas_size(void *qpc)
1355 {
1356         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1357         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1358         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1359         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1360         u32 po_quanta     = 1 << (log_page_size - 6);
1361         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1362         u32 page_size     = 1 << log_page_size;
1363         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1364         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1365
1366         return rq_num_pas * sizeof(u64);
1367 }
1368
1369 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1370                                    struct mlx5_ib_rq *rq, void *qpin,
1371                                    size_t qpinlen, struct ib_pd *pd)
1372 {
1373         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1374         __be64 *pas;
1375         __be64 *qp_pas;
1376         void *in;
1377         void *rqc;
1378         void *wq;
1379         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1380         size_t rq_pas_size = get_rq_pas_size(qpc);
1381         size_t inlen;
1382         int err;
1383
1384         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1385                 return -EINVAL;
1386
1387         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1388         in = kvzalloc(inlen, GFP_KERNEL);
1389         if (!in)
1390                 return -ENOMEM;
1391
1392         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1393         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1394         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1395                 MLX5_SET(rqc, rqc, vsd, 1);
1396         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1397         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1398         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1399         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1400         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1401
1402         if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
1403                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1404
1405         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1406         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1407         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1408                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1409         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1410         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1411         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1412         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1413         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1414         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1415
1416         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1417         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1418         memcpy(pas, qp_pas, rq_pas_size);
1419
1420         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
1421
1422         kvfree(in);
1423
1424         return err;
1425 }
1426
1427 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1428                                      struct mlx5_ib_rq *rq)
1429 {
1430         mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
1431 }
1432
1433 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1434                                       struct mlx5_ib_rq *rq,
1435                                       u32 qp_flags_en,
1436                                       struct ib_pd *pd)
1437 {
1438         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1439                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1440                 mlx5_ib_disable_lb(dev, false, true);
1441         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1442 }
1443
1444 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1445                                     struct mlx5_ib_rq *rq, u32 tdn,
1446                                     u32 *qp_flags_en, struct ib_pd *pd,
1447                                     u32 *out)
1448 {
1449         u8 lb_flag = 0;
1450         u32 *in;
1451         void *tirc;
1452         int inlen;
1453         int err;
1454
1455         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1456         in = kvzalloc(inlen, GFP_KERNEL);
1457         if (!in)
1458                 return -ENOMEM;
1459
1460         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1461         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1462         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1463         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1464         MLX5_SET(tirc, tirc, transport_domain, tdn);
1465         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1466                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1467
1468         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1469                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1470
1471         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1472                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1473
1474         if (dev->is_rep) {
1475                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1476                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1477         }
1478
1479         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1480         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1481         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1482         rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1483         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1484                 err = mlx5_ib_enable_lb(dev, false, true);
1485
1486                 if (err)
1487                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1488         }
1489         kvfree(in);
1490
1491         return err;
1492 }
1493
1494 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1495                                 u32 *in, size_t inlen,
1496                                 struct ib_pd *pd,
1497                                 struct ib_udata *udata,
1498                                 struct mlx5_ib_create_qp_resp *resp)
1499 {
1500         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1501         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1502         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1503         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1504                 udata, struct mlx5_ib_ucontext, ibucontext);
1505         int err;
1506         u32 tdn = mucontext->tdn;
1507         u16 uid = to_mpd(pd)->uid;
1508         u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1509
1510         if (qp->sq.wqe_cnt) {
1511                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1512                 if (err)
1513                         return err;
1514
1515                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1516                 if (err)
1517                         goto err_destroy_tis;
1518
1519                 if (uid) {
1520                         resp->tisn = sq->tisn;
1521                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1522                         resp->sqn = sq->base.mqp.qpn;
1523                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1524                 }
1525
1526                 sq->base.container_mibqp = qp;
1527                 sq->base.mqp.event = mlx5_ib_qp_event;
1528         }
1529
1530         if (qp->rq.wqe_cnt) {
1531                 rq->base.container_mibqp = qp;
1532
1533                 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
1534                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1535                 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
1536                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1537                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1538                 if (err)
1539                         goto err_destroy_sq;
1540
1541                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1542                                                out);
1543                 if (err)
1544                         goto err_destroy_rq;
1545
1546                 if (uid) {
1547                         resp->rqn = rq->base.mqp.qpn;
1548                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1549                         resp->tirn = rq->tirn;
1550                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1551                         if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1552                                 resp->tir_icm_addr = MLX5_GET(
1553                                         create_tir_out, out, icm_address_31_0);
1554                                 resp->tir_icm_addr |=
1555                                         (u64)MLX5_GET(create_tir_out, out,
1556                                                       icm_address_39_32)
1557                                         << 32;
1558                                 resp->tir_icm_addr |=
1559                                         (u64)MLX5_GET(create_tir_out, out,
1560                                                       icm_address_63_40)
1561                                         << 40;
1562                                 resp->comp_mask |=
1563                                         MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1564                         }
1565                 }
1566         }
1567
1568         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1569                                                      rq->base.mqp.qpn;
1570         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1571         if (err)
1572                 goto err_destroy_tir;
1573
1574         return 0;
1575
1576 err_destroy_tir:
1577         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1578 err_destroy_rq:
1579         destroy_raw_packet_qp_rq(dev, rq);
1580 err_destroy_sq:
1581         if (!qp->sq.wqe_cnt)
1582                 return err;
1583         destroy_raw_packet_qp_sq(dev, sq);
1584 err_destroy_tis:
1585         destroy_raw_packet_qp_tis(dev, sq, pd);
1586
1587         return err;
1588 }
1589
1590 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1591                                   struct mlx5_ib_qp *qp)
1592 {
1593         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1594         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1595         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1596
1597         if (qp->rq.wqe_cnt) {
1598                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1599                 destroy_raw_packet_qp_rq(dev, rq);
1600         }
1601
1602         if (qp->sq.wqe_cnt) {
1603                 destroy_raw_packet_qp_sq(dev, sq);
1604                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1605         }
1606 }
1607
1608 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1609                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1610 {
1611         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1612         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1613
1614         sq->sq = &qp->sq;
1615         rq->rq = &qp->rq;
1616         sq->doorbell = &qp->db;
1617         rq->doorbell = &qp->db;
1618 }
1619
1620 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1621 {
1622         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1623                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1624                 mlx5_ib_disable_lb(dev, false, true);
1625         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1626                              to_mpd(qp->ibqp.pd)->uid);
1627 }
1628
1629 static int create_rss_raw_qp_tir(struct ib_pd *pd, struct mlx5_ib_qp *qp,
1630                                  struct ib_qp_init_attr *init_attr,
1631                                  struct ib_udata *udata)
1632 {
1633         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1634                 udata, struct mlx5_ib_ucontext, ibucontext);
1635         struct mlx5_ib_dev *dev = to_mdev(pd->device);
1636         struct mlx5_ib_create_qp_resp resp = {};
1637         int inlen;
1638         int outlen;
1639         int err;
1640         u32 *in;
1641         u32 *out;
1642         void *tirc;
1643         void *hfso;
1644         u32 selected_fields = 0;
1645         u32 outer_l4;
1646         size_t min_resp_len;
1647         u32 tdn = mucontext->tdn;
1648         struct mlx5_ib_create_qp_rss ucmd = {};
1649         size_t required_cmd_sz;
1650         u8 lb_flag = 0;
1651
1652         if (init_attr->send_cq)
1653                 return -EINVAL;
1654
1655         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1656         if (udata->outlen < min_resp_len)
1657                 return -EINVAL;
1658
1659         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1660         if (udata->inlen < required_cmd_sz) {
1661                 mlx5_ib_dbg(dev, "invalid inlen\n");
1662                 return -EINVAL;
1663         }
1664
1665         if (udata->inlen > sizeof(ucmd) &&
1666             !ib_is_udata_cleared(udata, sizeof(ucmd),
1667                                  udata->inlen - sizeof(ucmd))) {
1668                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1669                 return -EOPNOTSUPP;
1670         }
1671
1672         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1673                 mlx5_ib_dbg(dev, "copy failed\n");
1674                 return -EFAULT;
1675         }
1676
1677         if (ucmd.comp_mask) {
1678                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1679                 return -EOPNOTSUPP;
1680         }
1681
1682         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1683                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1684                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1685                 mlx5_ib_dbg(dev, "invalid flags\n");
1686                 return -EOPNOTSUPP;
1687         }
1688
1689         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1690             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1691                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1692                 return -EOPNOTSUPP;
1693         }
1694
1695         if (dev->is_rep)
1696                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1697
1698         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1699                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1700
1701         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1702                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1703
1704         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1705         if (err) {
1706                 mlx5_ib_dbg(dev, "copy failed\n");
1707                 return -EINVAL;
1708         }
1709
1710         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1711         outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1712         in = kvzalloc(inlen + outlen, GFP_KERNEL);
1713         if (!in)
1714                 return -ENOMEM;
1715
1716         out = in + MLX5_ST_SZ_DW(create_tir_in);
1717         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1718         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1719         MLX5_SET(tirc, tirc, disp_type,
1720                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1721         MLX5_SET(tirc, tirc, indirect_table,
1722                  init_attr->rwq_ind_tbl->ind_tbl_num);
1723         MLX5_SET(tirc, tirc, transport_domain, tdn);
1724
1725         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1726
1727         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1728                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1729
1730         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1731
1732         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1733                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1734         else
1735                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1736
1737         switch (ucmd.rx_hash_function) {
1738         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1739         {
1740                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1741                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1742
1743                 if (len != ucmd.rx_key_len) {
1744                         err = -EINVAL;
1745                         goto err;
1746                 }
1747
1748                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1749                 memcpy(rss_key, ucmd.rx_hash_key, len);
1750                 break;
1751         }
1752         default:
1753                 err = -EOPNOTSUPP;
1754                 goto err;
1755         }
1756
1757         if (!ucmd.rx_hash_fields_mask) {
1758                 /* special case when this TIR serves as steering entry without hashing */
1759                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1760                         goto create_tir;
1761                 err = -EINVAL;
1762                 goto err;
1763         }
1764
1765         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1766              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1767              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1768              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1769                 err = -EINVAL;
1770                 goto err;
1771         }
1772
1773         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1774         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1775             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1776                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1777                          MLX5_L3_PROT_TYPE_IPV4);
1778         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1779                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1780                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1781                          MLX5_L3_PROT_TYPE_IPV6);
1782
1783         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1784                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1785                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1786                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1787                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1788
1789         /* Check that only one l4 protocol is set */
1790         if (outer_l4 & (outer_l4 - 1)) {
1791                 err = -EINVAL;
1792                 goto err;
1793         }
1794
1795         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1796         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1797             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1798                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1799                          MLX5_L4_PROT_TYPE_TCP);
1800         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1801                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1802                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1803                          MLX5_L4_PROT_TYPE_UDP);
1804
1805         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1806             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1807                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1808
1809         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1810             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1811                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1812
1813         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1814             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1815                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1816
1817         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1818             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1819                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1820
1821         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1822                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1823
1824         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1825
1826 create_tir:
1827         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1828         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1829
1830         qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1831         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1832                 err = mlx5_ib_enable_lb(dev, false, true);
1833
1834                 if (err)
1835                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1836                                              to_mpd(pd)->uid);
1837         }
1838
1839         if (err)
1840                 goto err;
1841
1842         if (mucontext->devx_uid) {
1843                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1844                 resp.tirn = qp->rss_qp.tirn;
1845                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1846                         resp.tir_icm_addr =
1847                                 MLX5_GET(create_tir_out, out, icm_address_31_0);
1848                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1849                                                            icm_address_39_32)
1850                                              << 32;
1851                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1852                                                            icm_address_63_40)
1853                                              << 40;
1854                         resp.comp_mask |=
1855                                 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1856                 }
1857         }
1858
1859         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1860         if (err)
1861                 goto err_copy;
1862
1863         kvfree(in);
1864         /* qpn is reserved for that QP */
1865         qp->trans_qp.base.mqp.qpn = 0;
1866         qp->is_rss = true;
1867         return 0;
1868
1869 err_copy:
1870         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1871 err:
1872         kvfree(in);
1873         return err;
1874 }
1875
1876 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1877                                          struct ib_qp_init_attr *init_attr,
1878                                          struct mlx5_ib_create_qp *ucmd,
1879                                          void *qpc)
1880 {
1881         int scqe_sz;
1882         bool allow_scat_cqe = false;
1883
1884         if (ucmd)
1885                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1886
1887         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1888                 return;
1889
1890         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1891         if (scqe_sz == 128) {
1892                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1893                 return;
1894         }
1895
1896         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1897             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1898                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1899 }
1900
1901 static int atomic_size_to_mode(int size_mask)
1902 {
1903         /* driver does not support atomic_size > 256B
1904          * and does not know how to translate bigger sizes
1905          */
1906         int supported_size_mask = size_mask & 0x1ff;
1907         int log_max_size;
1908
1909         if (!supported_size_mask)
1910                 return -EOPNOTSUPP;
1911
1912         log_max_size = __fls(supported_size_mask);
1913
1914         if (log_max_size > 3)
1915                 return log_max_size;
1916
1917         return MLX5_ATOMIC_MODE_8B;
1918 }
1919
1920 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1921                            enum ib_qp_type qp_type)
1922 {
1923         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1924         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1925         int atomic_mode = -EOPNOTSUPP;
1926         int atomic_size_mask;
1927
1928         if (!atomic)
1929                 return -EOPNOTSUPP;
1930
1931         if (qp_type == MLX5_IB_QPT_DCT)
1932                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1933         else
1934                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1935
1936         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1937             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1938                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1939
1940         if (atomic_mode <= 0 &&
1941             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1942              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1943                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1944
1945         return atomic_mode;
1946 }
1947
1948 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1949                             struct ib_qp_init_attr *init_attr,
1950                             struct mlx5_ib_create_qp *ucmd,
1951                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1952 {
1953         struct mlx5_ib_resources *devr = &dev->devr;
1954         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1955         struct mlx5_core_dev *mdev = dev->mdev;
1956         struct mlx5_ib_create_qp_resp resp = {};
1957         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
1958                 udata, struct mlx5_ib_ucontext, ibucontext);
1959         struct mlx5_ib_cq *send_cq;
1960         struct mlx5_ib_cq *recv_cq;
1961         unsigned long flags;
1962         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1963         struct mlx5_ib_qp_base *base;
1964         int mlx5_st;
1965         void *qpc;
1966         u32 *in;
1967         int err;
1968
1969         mutex_init(&qp->mutex);
1970         spin_lock_init(&qp->sq.lock);
1971         spin_lock_init(&qp->rq.lock);
1972
1973         mlx5_st = to_mlx5_st((init_attr->qp_type != IB_QPT_DRIVER) ?
1974                                      init_attr->qp_type :
1975                                      qp->qp_sub_type);
1976         if (mlx5_st < 0)
1977                 return -EINVAL;
1978
1979         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1980                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1981
1982         if (udata) {
1983                 err = get_qp_user_index(ucontext, ucmd, udata->inlen, &uidx);
1984                 if (err)
1985                         return err;
1986         }
1987
1988         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1989                 qp->underlay_qpn = init_attr->source_qpn;
1990
1991         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1992                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
1993                &qp->raw_packet_qp.rq.base :
1994                &qp->trans_qp.base;
1995
1996         qp->has_rq = qp_has_rq(init_attr);
1997         err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
1998         if (err) {
1999                 mlx5_ib_dbg(dev, "err %d\n", err);
2000                 return err;
2001         }
2002
2003         if (pd) {
2004                 if (udata) {
2005                         __u32 max_wqes =
2006                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
2007                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n",
2008                                     ucmd->sq_wqe_count);
2009                         if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
2010                             ucmd->rq_wqe_count != qp->rq.wqe_cnt) {
2011                                 mlx5_ib_dbg(dev, "invalid rq params\n");
2012                                 return -EINVAL;
2013                         }
2014                         if (ucmd->sq_wqe_count > max_wqes) {
2015                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
2016                                             ucmd->sq_wqe_count, max_wqes);
2017                                 return -EINVAL;
2018                         }
2019                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2020                                              &resp, &inlen, base);
2021                         if (err)
2022                                 mlx5_ib_dbg(dev, "err %d\n", err);
2023                 } else {
2024                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2025                                                base);
2026                         if (err)
2027                                 mlx5_ib_dbg(dev, "err %d\n", err);
2028                 }
2029
2030                 if (err)
2031                         return err;
2032         } else {
2033                 in = kvzalloc(inlen, GFP_KERNEL);
2034                 if (!in)
2035                         return -ENOMEM;
2036
2037                 qp->create_type = MLX5_QP_EMPTY;
2038         }
2039
2040         if (is_sqp(init_attr->qp_type))
2041                 qp->port = init_attr->port_num;
2042
2043         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2044
2045         MLX5_SET(qpc, qpc, st, mlx5_st);
2046         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2047
2048         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2049                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2050         else
2051                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2052
2053
2054         if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
2055                 MLX5_SET(qpc, qpc, wq_signature, 1);
2056
2057         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2058                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2059
2060         if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
2061                 MLX5_SET(qpc, qpc, cd_master, 1);
2062         if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
2063                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2064         if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
2065                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2066         if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
2067                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2068         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2069             (init_attr->qp_type == IB_QPT_RC ||
2070              init_attr->qp_type == IB_QPT_UC)) {
2071                 int rcqe_sz = rcqe_sz =
2072                         mlx5_ib_get_cqe_size(init_attr->recv_cq);
2073
2074                 MLX5_SET(qpc, qpc, cs_res,
2075                          rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2076                                           MLX5_RES_SCAT_DATA32_CQE);
2077         }
2078         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2079             (qp->qp_sub_type == MLX5_IB_QPT_DCI ||
2080              init_attr->qp_type == IB_QPT_RC))
2081                 configure_requester_scat_cqe(dev, init_attr, ucmd, qpc);
2082
2083         if (qp->rq.wqe_cnt) {
2084                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2085                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2086         }
2087
2088         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2089
2090         if (qp->sq.wqe_cnt) {
2091                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2092         } else {
2093                 MLX5_SET(qpc, qpc, no_sq, 1);
2094                 if (init_attr->srq &&
2095                     init_attr->srq->srq_type == IB_SRQT_TM)
2096                         MLX5_SET(qpc, qpc, offload_type,
2097                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2098         }
2099
2100         /* Set default resources */
2101         switch (init_attr->qp_type) {
2102         case IB_QPT_XRC_TGT:
2103                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2104                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2105                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2106                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2107                 break;
2108         case IB_QPT_XRC_INI:
2109                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2110                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2111                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2112                 break;
2113         default:
2114                 if (init_attr->srq) {
2115                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2116                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2117                 } else {
2118                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2119                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2120                 }
2121         }
2122
2123         if (init_attr->send_cq)
2124                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2125
2126         if (init_attr->recv_cq)
2127                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2128
2129         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2130
2131         /* 0xffffff means we ask to work with cqe version 0 */
2132         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2133                 MLX5_SET(qpc, qpc, user_index, uidx);
2134
2135         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2136         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2137                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2138
2139         if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2140             init_attr->qp_type != IB_QPT_RAW_PACKET) {
2141                 MLX5_SET(qpc, qpc, end_padding_mode,
2142                          MLX5_WQ_END_PAD_MODE_ALIGN);
2143                 /* Special case to clean flag */
2144                 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
2145         }
2146
2147         if (inlen < 0) {
2148                 err = -EINVAL;
2149                 goto err;
2150         }
2151
2152         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2153             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2154                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
2155                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2156                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2157                                            &resp);
2158         } else {
2159                 err = mlx5_core_create_qp(dev, &base->mqp, in, inlen);
2160         }
2161
2162         if (err) {
2163                 mlx5_ib_dbg(dev, "create qp failed\n");
2164                 goto err_create;
2165         }
2166
2167         kvfree(in);
2168
2169         base->container_mibqp = qp;
2170         base->mqp.event = mlx5_ib_qp_event;
2171
2172         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2173                 &send_cq, &recv_cq);
2174         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2175         mlx5_ib_lock_cqs(send_cq, recv_cq);
2176         /* Maintain device to QPs access, needed for further handling via reset
2177          * flow
2178          */
2179         list_add_tail(&qp->qps_list, &dev->qp_list);
2180         /* Maintain CQ to QPs access, needed for further handling via reset flow
2181          */
2182         if (send_cq)
2183                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2184         if (recv_cq)
2185                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2186         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2187         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2188
2189         return 0;
2190
2191 err_create:
2192         if (qp->create_type == MLX5_QP_USER)
2193                 destroy_qp_user(dev, pd, qp, base, udata);
2194         else if (qp->create_type == MLX5_QP_KERNEL)
2195                 destroy_qp_kernel(dev, qp);
2196
2197 err:
2198         kvfree(in);
2199         return err;
2200 }
2201
2202 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2203         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2204 {
2205         if (send_cq) {
2206                 if (recv_cq) {
2207                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2208                                 spin_lock(&send_cq->lock);
2209                                 spin_lock_nested(&recv_cq->lock,
2210                                                  SINGLE_DEPTH_NESTING);
2211                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2212                                 spin_lock(&send_cq->lock);
2213                                 __acquire(&recv_cq->lock);
2214                         } else {
2215                                 spin_lock(&recv_cq->lock);
2216                                 spin_lock_nested(&send_cq->lock,
2217                                                  SINGLE_DEPTH_NESTING);
2218                         }
2219                 } else {
2220                         spin_lock(&send_cq->lock);
2221                         __acquire(&recv_cq->lock);
2222                 }
2223         } else if (recv_cq) {
2224                 spin_lock(&recv_cq->lock);
2225                 __acquire(&send_cq->lock);
2226         } else {
2227                 __acquire(&send_cq->lock);
2228                 __acquire(&recv_cq->lock);
2229         }
2230 }
2231
2232 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2233         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2234 {
2235         if (send_cq) {
2236                 if (recv_cq) {
2237                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2238                                 spin_unlock(&recv_cq->lock);
2239                                 spin_unlock(&send_cq->lock);
2240                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2241                                 __release(&recv_cq->lock);
2242                                 spin_unlock(&send_cq->lock);
2243                         } else {
2244                                 spin_unlock(&send_cq->lock);
2245                                 spin_unlock(&recv_cq->lock);
2246                         }
2247                 } else {
2248                         __release(&recv_cq->lock);
2249                         spin_unlock(&send_cq->lock);
2250                 }
2251         } else if (recv_cq) {
2252                 __release(&send_cq->lock);
2253                 spin_unlock(&recv_cq->lock);
2254         } else {
2255                 __release(&recv_cq->lock);
2256                 __release(&send_cq->lock);
2257         }
2258 }
2259
2260 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2261 {
2262         return to_mpd(qp->ibqp.pd);
2263 }
2264
2265 static void get_cqs(enum ib_qp_type qp_type,
2266                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2267                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2268 {
2269         switch (qp_type) {
2270         case IB_QPT_XRC_TGT:
2271                 *send_cq = NULL;
2272                 *recv_cq = NULL;
2273                 break;
2274         case MLX5_IB_QPT_REG_UMR:
2275         case IB_QPT_XRC_INI:
2276                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2277                 *recv_cq = NULL;
2278                 break;
2279
2280         case IB_QPT_SMI:
2281         case MLX5_IB_QPT_HW_GSI:
2282         case IB_QPT_RC:
2283         case IB_QPT_UC:
2284         case IB_QPT_UD:
2285         case IB_QPT_RAW_IPV6:
2286         case IB_QPT_RAW_ETHERTYPE:
2287         case IB_QPT_RAW_PACKET:
2288                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2289                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2290                 break;
2291
2292         case IB_QPT_MAX:
2293         default:
2294                 *send_cq = NULL;
2295                 *recv_cq = NULL;
2296                 break;
2297         }
2298 }
2299
2300 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2301                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2302                                 u8 lag_tx_affinity);
2303
2304 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2305                               struct ib_udata *udata)
2306 {
2307         struct mlx5_ib_cq *send_cq, *recv_cq;
2308         struct mlx5_ib_qp_base *base;
2309         unsigned long flags;
2310         int err;
2311
2312         if (qp->ibqp.rwq_ind_tbl) {
2313                 destroy_rss_raw_qp_tir(dev, qp);
2314                 return;
2315         }
2316
2317         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2318                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
2319                &qp->raw_packet_qp.rq.base :
2320                &qp->trans_qp.base;
2321
2322         if (qp->state != IB_QPS_RESET) {
2323                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2324                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
2325                         err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
2326                                                   NULL, &base->mqp);
2327                 } else {
2328                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2329                                 .operation = MLX5_CMD_OP_2RST_QP
2330                         };
2331
2332                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2333                 }
2334                 if (err)
2335                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2336                                      base->mqp.qpn);
2337         }
2338
2339         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2340                 &send_cq, &recv_cq);
2341
2342         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2343         mlx5_ib_lock_cqs(send_cq, recv_cq);
2344         /* del from lists under both locks above to protect reset flow paths */
2345         list_del(&qp->qps_list);
2346         if (send_cq)
2347                 list_del(&qp->cq_send_list);
2348
2349         if (recv_cq)
2350                 list_del(&qp->cq_recv_list);
2351
2352         if (qp->create_type == MLX5_QP_KERNEL) {
2353                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2354                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2355                 if (send_cq != recv_cq)
2356                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2357                                            NULL);
2358         }
2359         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2360         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2361
2362         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2363             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2364                 destroy_raw_packet_qp(dev, qp);
2365         } else {
2366                 err = mlx5_core_destroy_qp(dev, &base->mqp);
2367                 if (err)
2368                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2369                                      base->mqp.qpn);
2370         }
2371
2372         if (qp->create_type == MLX5_QP_KERNEL)
2373                 destroy_qp_kernel(dev, qp);
2374         else if (qp->create_type == MLX5_QP_USER)
2375                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
2376 }
2377
2378 static int create_dct(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2379                       struct ib_qp_init_attr *attr,
2380                       struct mlx5_ib_create_qp *ucmd, struct ib_udata *udata)
2381 {
2382         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2383                 udata, struct mlx5_ib_ucontext, ibucontext);
2384         int err = 0;
2385         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2386         void *dctc;
2387
2388         err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx);
2389         if (err)
2390                 return err;
2391
2392         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2393         if (!qp->dct.in)
2394                 return -ENOMEM;
2395
2396         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2397         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2398         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2399         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2400         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2401         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2402         MLX5_SET(dctc, dctc, user_index, uidx);
2403
2404         if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
2405                 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2406
2407                 if (rcqe_sz == 128)
2408                         MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2409         }
2410
2411         qp->state = IB_QPS_RESET;
2412
2413         return 0;
2414 }
2415
2416 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr)
2417 {
2418         if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2419                 goto out;
2420
2421         switch (attr->qp_type) {
2422         case IB_QPT_XRC_TGT:
2423         case IB_QPT_XRC_INI:
2424                 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2425                         goto out;
2426                 fallthrough;
2427         case IB_QPT_RAW_PACKET:
2428         case IB_QPT_RC:
2429         case IB_QPT_UC:
2430         case IB_QPT_UD:
2431         case IB_QPT_SMI:
2432         case MLX5_IB_QPT_HW_GSI:
2433         case MLX5_IB_QPT_REG_UMR:
2434         case IB_QPT_DRIVER:
2435         case IB_QPT_GSI:
2436                 return 0;
2437         case IB_QPT_RAW_IPV6:
2438         case IB_QPT_RAW_ETHERTYPE:
2439         case IB_QPT_MAX:
2440         default:
2441                 goto out;
2442         }
2443
2444         return 0;
2445
2446 out:
2447         mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2448         return -EOPNOTSUPP;
2449 }
2450
2451 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2452                             struct ib_qp_init_attr *attr,
2453                             struct ib_udata *udata)
2454 {
2455         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2456                 udata, struct mlx5_ib_ucontext, ibucontext);
2457
2458         if (!udata) {
2459                 /* Kernel create_qp callers */
2460                 if (attr->rwq_ind_tbl)
2461                         return -EOPNOTSUPP;
2462
2463                 switch (attr->qp_type) {
2464                 case IB_QPT_RAW_PACKET:
2465                 case IB_QPT_DRIVER:
2466                         return -EOPNOTSUPP;
2467                 default:
2468                         return 0;
2469                 }
2470         }
2471
2472         /* Userspace create_qp callers */
2473         if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2474                 mlx5_ib_dbg(dev,
2475                         "Raw Packet QP is only supported for CQE version > 0\n");
2476                 return -EINVAL;
2477         }
2478
2479         if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2480                 mlx5_ib_dbg(dev,
2481                             "Wrong QP type %d for the RWQ indirect table\n",
2482                             attr->qp_type);
2483                 return -EINVAL;
2484         }
2485
2486         switch (attr->qp_type) {
2487         case IB_QPT_SMI:
2488         case MLX5_IB_QPT_HW_GSI:
2489         case MLX5_IB_QPT_REG_UMR:
2490         case IB_QPT_GSI:
2491                 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2492                             attr->qp_type);
2493                 return -EINVAL;
2494         default:
2495                 break;
2496         }
2497
2498         /*
2499          * We don't need to see this warning, it means that kernel code
2500          * missing ib_pd. Placed here to catch developer's mistakes.
2501          */
2502         WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2503                   "There is a missing PD pointer assignment\n");
2504         return 0;
2505 }
2506
2507 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2508                                 bool cond, struct mlx5_ib_qp *qp)
2509 {
2510         if (!(*flags & flag))
2511                 return;
2512
2513         if (cond) {
2514                 qp->flags_en |= flag;
2515                 *flags &= ~flag;
2516                 return;
2517         }
2518
2519         if (flag == MLX5_QP_FLAG_SCATTER_CQE) {
2520                 /*
2521                  * We don't return error if this flag was provided,
2522                  * and mlx5 doesn't have right capability.
2523                  */
2524                 *flags &= ~MLX5_QP_FLAG_SCATTER_CQE;
2525                 return;
2526         }
2527         mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2528 }
2529
2530 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2531                                 struct ib_qp_init_attr *attr,
2532                                 struct mlx5_ib_create_qp *ucmd)
2533 {
2534         struct mlx5_core_dev *mdev = dev->mdev;
2535         int flags = ucmd->flags;
2536         bool cond;
2537
2538         switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2539         case MLX5_QP_FLAG_TYPE_DCI:
2540                 qp->qp_sub_type = MLX5_IB_QPT_DCI;
2541                 break;
2542         case MLX5_QP_FLAG_TYPE_DCT:
2543                 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2544                 fallthrough;
2545         default:
2546                 break;
2547         }
2548
2549         if (attr->qp_type == IB_QPT_DRIVER && !qp->qp_sub_type)
2550                 return -EINVAL;
2551
2552         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2553         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2554
2555         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2556         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2557                             MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2558
2559         if (attr->qp_type == IB_QPT_RAW_PACKET) {
2560                 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2561                        MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2562                        MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2563                 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2564                                     cond, qp);
2565                 process_vendor_flag(dev, &flags,
2566                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2567                                     qp);
2568                 process_vendor_flag(dev, &flags,
2569                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2570                                     qp);
2571         }
2572
2573         if (attr->qp_type == IB_QPT_RC)
2574                 process_vendor_flag(dev, &flags,
2575                                     MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2576                                     MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2577
2578         if (flags)
2579                 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2580
2581         return (flags) ? -EINVAL : 0;
2582 }
2583
2584 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2585                                 bool cond, struct mlx5_ib_qp *qp)
2586 {
2587         if (!(*flags & flag))
2588                 return;
2589
2590         if (cond) {
2591                 qp->flags |= flag;
2592                 *flags &= ~flag;
2593                 return;
2594         }
2595
2596         if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2597                 /*
2598                  * Special case, if condition didn't meet, it won't be error,
2599                  * just different in-kernel flow.
2600                  */
2601                 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2602                 return;
2603         }
2604         mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2605 }
2606
2607 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2608                                 struct ib_qp_init_attr *attr)
2609 {
2610         enum ib_qp_type qp_type = attr->qp_type;
2611         struct mlx5_core_dev *mdev = dev->mdev;
2612         int create_flags = attr->create_flags;
2613         bool cond;
2614
2615         if (qp->qp_sub_type == MLX5_IB_QPT_DCT)
2616                 return (create_flags) ? -EINVAL : 0;
2617
2618         if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2619                 return (create_flags) ? -EINVAL : 0;
2620
2621         process_create_flag(dev, &create_flags,
2622                             IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2623                             MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2624         process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2625                             MLX5_CAP_GEN(mdev, cd), qp);
2626         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2627                             MLX5_CAP_GEN(mdev, cd), qp);
2628         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2629                             MLX5_CAP_GEN(mdev, cd), qp);
2630
2631         if (qp_type == IB_QPT_UD) {
2632                 process_create_flag(dev, &create_flags,
2633                                     IB_QP_CREATE_IPOIB_UD_LSO,
2634                                     MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2635                                     qp);
2636                 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2637                 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2638                                     cond, qp);
2639         }
2640
2641         if (qp_type == IB_QPT_RAW_PACKET) {
2642                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2643                        MLX5_CAP_ETH(mdev, scatter_fcs);
2644                 process_create_flag(dev, &create_flags,
2645                                     IB_QP_CREATE_SCATTER_FCS, cond, qp);
2646
2647                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2648                        MLX5_CAP_ETH(mdev, vlan_cap);
2649                 process_create_flag(dev, &create_flags,
2650                                     IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2651         }
2652
2653         process_create_flag(dev, &create_flags,
2654                             IB_QP_CREATE_PCI_WRITE_END_PADDING,
2655                             MLX5_CAP_GEN(mdev, end_pad), qp);
2656
2657         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2658                             qp_type != MLX5_IB_QPT_REG_UMR, qp);
2659         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2660                             true, qp);
2661
2662         if (create_flags)
2663                 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2664                             create_flags);
2665
2666         return (create_flags) ? -EINVAL : 0;
2667 }
2668
2669 static int create_driver_qp(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2670                             struct ib_qp_init_attr *attr,
2671                             struct mlx5_ib_create_qp *ucmd,
2672                             struct ib_udata *udata)
2673 {
2674         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2675         int ret = -EINVAL;
2676
2677         switch (qp->qp_sub_type) {
2678         case MLX5_IB_QPT_DCT:
2679                 if (!attr->srq || !attr->recv_cq)
2680                         goto out;
2681
2682                 ret = create_dct(pd, qp, attr, ucmd, udata);
2683                 break;
2684         case MLX5_IB_QPT_DCI:
2685                 if (attr->cap.max_recv_wr || attr->cap.max_recv_sge)
2686                         goto out;
2687
2688                 ret = create_qp_common(mdev, pd, attr, ucmd, udata, qp);
2689                 break;
2690         default:
2691                 return -EINVAL;
2692         }
2693
2694 out:    return ret;
2695 }
2696
2697 static size_t process_udata_size(struct ib_qp_init_attr *attr,
2698                                  struct ib_udata *udata)
2699 {
2700         size_t ucmd = sizeof(struct mlx5_ib_create_qp);
2701
2702         if (attr->qp_type == IB_QPT_DRIVER)
2703                 return (udata->inlen < ucmd) ? 0 : ucmd;
2704
2705         return ucmd;
2706 }
2707
2708 static int create_raw_qp(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2709                          struct ib_qp_init_attr *attr,
2710                          struct mlx5_ib_create_qp *ucmd, struct ib_udata *udata)
2711 {
2712         struct mlx5_ib_dev *dev = to_mdev(pd->device);
2713
2714         if (attr->rwq_ind_tbl)
2715                 return create_rss_raw_qp_tir(pd, qp, attr, udata);
2716
2717         return create_qp_common(dev, pd, attr, ucmd, udata, qp);
2718 }
2719
2720 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2721                                 struct ib_qp_init_attr *init_attr,
2722                                 struct ib_udata *udata)
2723 {
2724         struct mlx5_ib_create_qp ucmd = {};
2725         struct mlx5_ib_dev *dev;
2726         struct mlx5_ib_qp *qp;
2727         u16 xrcdn = 0;
2728         int err;
2729
2730         dev = pd ? to_mdev(pd->device) :
2731                    to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2732
2733         err = check_qp_type(dev, init_attr);
2734         if (err) {
2735                 mlx5_ib_dbg(dev, "Unsupported QP type %d\n",
2736                             init_attr->qp_type);
2737                 return ERR_PTR(err);
2738         }
2739
2740         err = check_valid_flow(dev, pd, init_attr, udata);
2741         if (err)
2742                 return ERR_PTR(err);
2743
2744         if (init_attr->qp_type == IB_QPT_GSI)
2745                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2746
2747         if (udata && !init_attr->rwq_ind_tbl) {
2748                 size_t inlen =
2749                         process_udata_size(init_attr, udata);
2750
2751                 if (!inlen)
2752                         return ERR_PTR(-EINVAL);
2753
2754                 err = ib_copy_from_udata(&ucmd, udata, inlen);
2755                 if (err)
2756                         return ERR_PTR(err);
2757         }
2758
2759         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2760         if (!qp)
2761                 return ERR_PTR(-ENOMEM);
2762
2763         if (udata) {
2764                 err = process_vendor_flags(dev, qp, init_attr, &ucmd);
2765                 if (err)
2766                         goto free_qp;
2767         }
2768         err = process_create_flags(dev, qp, init_attr);
2769         if (err)
2770                 goto free_qp;
2771
2772         if (init_attr->qp_type == IB_QPT_XRC_TGT)
2773                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2774
2775         switch (init_attr->qp_type) {
2776         case IB_QPT_DRIVER:
2777                 err = create_driver_qp(pd, qp, init_attr, &ucmd, udata);
2778                 break;
2779         case IB_QPT_RAW_PACKET:
2780                 err = create_raw_qp(pd, qp, init_attr, &ucmd, udata);
2781                 break;
2782         default:
2783                 err = create_qp_common(dev, pd, init_attr,
2784                                        (udata) ? &ucmd : NULL, udata, qp);
2785         }
2786         if (err) {
2787                 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2788                 goto free_qp;
2789         }
2790
2791         if (is_qp0(init_attr->qp_type))
2792                 qp->ibqp.qp_num = 0;
2793         else if (is_qp1(init_attr->qp_type))
2794                 qp->ibqp.qp_num = 1;
2795         else
2796                 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2797
2798         qp->trans_qp.xrcdn = xrcdn;
2799
2800         return &qp->ibqp;
2801
2802 free_qp:
2803         kfree(qp);
2804         return ERR_PTR(err);
2805 }
2806
2807 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2808 {
2809         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2810
2811         if (mqp->state == IB_QPS_RTR) {
2812                 int err;
2813
2814                 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2815                 if (err) {
2816                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2817                         return err;
2818                 }
2819         }
2820
2821         kfree(mqp->dct.in);
2822         kfree(mqp);
2823         return 0;
2824 }
2825
2826 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
2827 {
2828         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2829         struct mlx5_ib_qp *mqp = to_mqp(qp);
2830
2831         if (unlikely(qp->qp_type == IB_QPT_GSI))
2832                 return mlx5_ib_gsi_destroy_qp(qp);
2833
2834         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2835                 return mlx5_ib_destroy_dct(mqp);
2836
2837         destroy_qp_common(dev, mqp, udata);
2838
2839         kfree(mqp);
2840
2841         return 0;
2842 }
2843
2844 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2845                                 const struct ib_qp_attr *attr,
2846                                 int attr_mask, __be32 *hw_access_flags_be)
2847 {
2848         u8 dest_rd_atomic;
2849         u32 access_flags, hw_access_flags = 0;
2850
2851         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2852
2853         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2854                 dest_rd_atomic = attr->max_dest_rd_atomic;
2855         else
2856                 dest_rd_atomic = qp->trans_qp.resp_depth;
2857
2858         if (attr_mask & IB_QP_ACCESS_FLAGS)
2859                 access_flags = attr->qp_access_flags;
2860         else
2861                 access_flags = qp->trans_qp.atomic_rd_en;
2862
2863         if (!dest_rd_atomic)
2864                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2865
2866         if (access_flags & IB_ACCESS_REMOTE_READ)
2867                 hw_access_flags |= MLX5_QP_BIT_RRE;
2868         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2869                 int atomic_mode;
2870
2871                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2872                 if (atomic_mode < 0)
2873                         return -EOPNOTSUPP;
2874
2875                 hw_access_flags |= MLX5_QP_BIT_RAE;
2876                 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2877         }
2878
2879         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2880                 hw_access_flags |= MLX5_QP_BIT_RWE;
2881
2882         *hw_access_flags_be = cpu_to_be32(hw_access_flags);
2883
2884         return 0;
2885 }
2886
2887 enum {
2888         MLX5_PATH_FLAG_FL       = 1 << 0,
2889         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2890         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2891 };
2892
2893 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2894 {
2895         if (rate == IB_RATE_PORT_CURRENT)
2896                 return 0;
2897
2898         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
2899                 return -EINVAL;
2900
2901         while (rate != IB_RATE_PORT_CURRENT &&
2902                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2903                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2904                 --rate;
2905
2906         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2907 }
2908
2909 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2910                                       struct mlx5_ib_sq *sq, u8 sl,
2911                                       struct ib_pd *pd)
2912 {
2913         void *in;
2914         void *tisc;
2915         int inlen;
2916         int err;
2917
2918         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2919         in = kvzalloc(inlen, GFP_KERNEL);
2920         if (!in)
2921                 return -ENOMEM;
2922
2923         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2924         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2925
2926         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2927         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2928
2929         err = mlx5_core_modify_tis(dev, sq->tisn, in);
2930
2931         kvfree(in);
2932
2933         return err;
2934 }
2935
2936 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2937                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2938                                          struct ib_pd *pd)
2939 {
2940         void *in;
2941         void *tisc;
2942         int inlen;
2943         int err;
2944
2945         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2946         in = kvzalloc(inlen, GFP_KERNEL);
2947         if (!in)
2948                 return -ENOMEM;
2949
2950         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2951         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2952
2953         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2954         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2955
2956         err = mlx5_core_modify_tis(dev, sq->tisn, in);
2957
2958         kvfree(in);
2959
2960         return err;
2961 }
2962
2963 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2964                          const struct rdma_ah_attr *ah,
2965                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2966                          u32 path_flags, const struct ib_qp_attr *attr,
2967                          bool alt)
2968 {
2969         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2970         int err;
2971         enum ib_gid_type gid_type;
2972         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2973         u8 sl = rdma_ah_get_sl(ah);
2974
2975         if (attr_mask & IB_QP_PKEY_INDEX)
2976                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2977                                                      attr->pkey_index);
2978
2979         if (ah_flags & IB_AH_GRH) {
2980                 if (grh->sgid_index >=
2981                     dev->mdev->port_caps[port - 1].gid_table_len) {
2982                         pr_err("sgid_index (%u) too large. max is %d\n",
2983                                grh->sgid_index,
2984                                dev->mdev->port_caps[port - 1].gid_table_len);
2985                         return -EINVAL;
2986                 }
2987         }
2988
2989         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2990                 if (!(ah_flags & IB_AH_GRH))
2991                         return -EINVAL;
2992
2993                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2994                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2995                     qp->ibqp.qp_type == IB_QPT_UC ||
2996                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2997                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2998                         path->udp_sport =
2999                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
3000                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
3001                 gid_type = ah->grh.sgid_attr->gid_type;
3002                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3003                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
3004         } else {
3005                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
3006                 path->fl_free_ar |=
3007                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
3008                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
3009                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
3010                 if (ah_flags & IB_AH_GRH)
3011                         path->grh_mlid  |= 1 << 7;
3012                 path->dci_cfi_prio_sl = sl & 0xf;
3013         }
3014
3015         if (ah_flags & IB_AH_GRH) {
3016                 path->mgid_index = grh->sgid_index;
3017                 path->hop_limit  = grh->hop_limit;
3018                 path->tclass_flowlabel =
3019                         cpu_to_be32((grh->traffic_class << 20) |
3020                                     (grh->flow_label));
3021                 memcpy(path->rgid, grh->dgid.raw, 16);
3022         }
3023
3024         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
3025         if (err < 0)
3026                 return err;
3027         path->static_rate = err;
3028         path->port = port;
3029
3030         if (attr_mask & IB_QP_TIMEOUT)
3031                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
3032
3033         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3034                 return modify_raw_packet_eth_prio(dev->mdev,
3035                                                   &qp->raw_packet_qp.sq,
3036                                                   sl & 0xf, qp->ibqp.pd);
3037
3038         return 0;
3039 }
3040
3041 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3042         [MLX5_QP_STATE_INIT] = {
3043                 [MLX5_QP_STATE_INIT] = {
3044                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3045                                           MLX5_QP_OPTPAR_RAE            |
3046                                           MLX5_QP_OPTPAR_RWE            |
3047                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3048                                           MLX5_QP_OPTPAR_PRI_PORT,
3049                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3050                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3051                                           MLX5_QP_OPTPAR_PRI_PORT,
3052                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3053                                           MLX5_QP_OPTPAR_Q_KEY          |
3054                                           MLX5_QP_OPTPAR_PRI_PORT,
3055                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3056                                           MLX5_QP_OPTPAR_RAE            |
3057                                           MLX5_QP_OPTPAR_RWE            |
3058                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3059                                           MLX5_QP_OPTPAR_PRI_PORT,
3060                 },
3061                 [MLX5_QP_STATE_RTR] = {
3062                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3063                                           MLX5_QP_OPTPAR_RRE            |
3064                                           MLX5_QP_OPTPAR_RAE            |
3065                                           MLX5_QP_OPTPAR_RWE            |
3066                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3067                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3068                                           MLX5_QP_OPTPAR_RWE            |
3069                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3070                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3071                                           MLX5_QP_OPTPAR_Q_KEY,
3072                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
3073                                            MLX5_QP_OPTPAR_Q_KEY,
3074                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3075                                           MLX5_QP_OPTPAR_RRE            |
3076                                           MLX5_QP_OPTPAR_RAE            |
3077                                           MLX5_QP_OPTPAR_RWE            |
3078                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3079                 },
3080         },
3081         [MLX5_QP_STATE_RTR] = {
3082                 [MLX5_QP_STATE_RTS] = {
3083                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3084                                           MLX5_QP_OPTPAR_RRE            |
3085                                           MLX5_QP_OPTPAR_RAE            |
3086                                           MLX5_QP_OPTPAR_RWE            |
3087                                           MLX5_QP_OPTPAR_PM_STATE       |
3088                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3089                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3090                                           MLX5_QP_OPTPAR_RWE            |
3091                                           MLX5_QP_OPTPAR_PM_STATE,
3092                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3093                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3094                                           MLX5_QP_OPTPAR_RRE            |
3095                                           MLX5_QP_OPTPAR_RAE            |
3096                                           MLX5_QP_OPTPAR_RWE            |
3097                                           MLX5_QP_OPTPAR_PM_STATE       |
3098                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3099                 },
3100         },
3101         [MLX5_QP_STATE_RTS] = {
3102                 [MLX5_QP_STATE_RTS] = {
3103                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3104                                           MLX5_QP_OPTPAR_RAE            |
3105                                           MLX5_QP_OPTPAR_RWE            |
3106                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3107                                           MLX5_QP_OPTPAR_PM_STATE       |
3108                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3109                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3110                                           MLX5_QP_OPTPAR_PM_STATE       |
3111                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3112                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3113                                           MLX5_QP_OPTPAR_SRQN           |
3114                                           MLX5_QP_OPTPAR_CQN_RCV,
3115                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3116                                           MLX5_QP_OPTPAR_RAE            |
3117                                           MLX5_QP_OPTPAR_RWE            |
3118                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3119                                           MLX5_QP_OPTPAR_PM_STATE       |
3120                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3121                 },
3122         },
3123         [MLX5_QP_STATE_SQER] = {
3124                 [MLX5_QP_STATE_RTS] = {
3125                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3126                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3127                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3128                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3129                                            MLX5_QP_OPTPAR_RWE           |
3130                                            MLX5_QP_OPTPAR_RAE           |
3131                                            MLX5_QP_OPTPAR_RRE,
3132                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
3133                                            MLX5_QP_OPTPAR_RWE           |
3134                                            MLX5_QP_OPTPAR_RAE           |
3135                                            MLX5_QP_OPTPAR_RRE,
3136                 },
3137         },
3138 };
3139
3140 static int ib_nr_to_mlx5_nr(int ib_mask)
3141 {
3142         switch (ib_mask) {
3143         case IB_QP_STATE:
3144                 return 0;
3145         case IB_QP_CUR_STATE:
3146                 return 0;
3147         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3148                 return 0;
3149         case IB_QP_ACCESS_FLAGS:
3150                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3151                         MLX5_QP_OPTPAR_RAE;
3152         case IB_QP_PKEY_INDEX:
3153                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3154         case IB_QP_PORT:
3155                 return MLX5_QP_OPTPAR_PRI_PORT;
3156         case IB_QP_QKEY:
3157                 return MLX5_QP_OPTPAR_Q_KEY;
3158         case IB_QP_AV:
3159                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3160                         MLX5_QP_OPTPAR_PRI_PORT;
3161         case IB_QP_PATH_MTU:
3162                 return 0;
3163         case IB_QP_TIMEOUT:
3164                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3165         case IB_QP_RETRY_CNT:
3166                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3167         case IB_QP_RNR_RETRY:
3168                 return MLX5_QP_OPTPAR_RNR_RETRY;
3169         case IB_QP_RQ_PSN:
3170                 return 0;
3171         case IB_QP_MAX_QP_RD_ATOMIC:
3172                 return MLX5_QP_OPTPAR_SRA_MAX;
3173         case IB_QP_ALT_PATH:
3174                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3175         case IB_QP_MIN_RNR_TIMER:
3176                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3177         case IB_QP_SQ_PSN:
3178                 return 0;
3179         case IB_QP_MAX_DEST_RD_ATOMIC:
3180                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3181                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3182         case IB_QP_PATH_MIG_STATE:
3183                 return MLX5_QP_OPTPAR_PM_STATE;
3184         case IB_QP_CAP:
3185                 return 0;
3186         case IB_QP_DEST_QPN:
3187                 return 0;
3188         }
3189         return 0;
3190 }
3191
3192 static int ib_mask_to_mlx5_opt(int ib_mask)
3193 {
3194         int result = 0;
3195         int i;
3196
3197         for (i = 0; i < 8 * sizeof(int); i++) {
3198                 if ((1 << i) & ib_mask)
3199                         result |= ib_nr_to_mlx5_nr(1 << i);
3200         }
3201
3202         return result;
3203 }
3204
3205 static int modify_raw_packet_qp_rq(
3206         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3207         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3208 {
3209         void *in;
3210         void *rqc;
3211         int inlen;
3212         int err;
3213
3214         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3215         in = kvzalloc(inlen, GFP_KERNEL);
3216         if (!in)
3217                 return -ENOMEM;
3218
3219         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3220         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3221
3222         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3223         MLX5_SET(rqc, rqc, state, new_state);
3224
3225         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3226                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3227                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3228                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3229                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3230                 } else
3231                         dev_info_once(
3232                                 &dev->ib_dev.dev,
3233                                 "RAW PACKET QP counters are not supported on current FW\n");
3234         }
3235
3236         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3237         if (err)
3238                 goto out;
3239
3240         rq->state = new_state;
3241
3242 out:
3243         kvfree(in);
3244         return err;
3245 }
3246
3247 static int modify_raw_packet_qp_sq(
3248         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3249         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3250 {
3251         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3252         struct mlx5_rate_limit old_rl = ibqp->rl;
3253         struct mlx5_rate_limit new_rl = old_rl;
3254         bool new_rate_added = false;
3255         u16 rl_index = 0;
3256         void *in;
3257         void *sqc;
3258         int inlen;
3259         int err;
3260
3261         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3262         in = kvzalloc(inlen, GFP_KERNEL);
3263         if (!in)
3264                 return -ENOMEM;
3265
3266         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3267         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3268
3269         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3270         MLX5_SET(sqc, sqc, state, new_state);
3271
3272         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3273                 if (new_state != MLX5_SQC_STATE_RDY)
3274                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3275                                 __func__);
3276                 else
3277                         new_rl = raw_qp_param->rl;
3278         }
3279
3280         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3281                 if (new_rl.rate) {
3282                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3283                         if (err) {
3284                                 pr_err("Failed configuring rate limit(err %d): \
3285                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3286                                        err, new_rl.rate, new_rl.max_burst_sz,
3287                                        new_rl.typical_pkt_sz);
3288
3289                                 goto out;
3290                         }
3291                         new_rate_added = true;
3292                 }
3293
3294                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3295                 /* index 0 means no limit */
3296                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3297         }
3298
3299         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
3300         if (err) {
3301                 /* Remove new rate from table if failed */
3302                 if (new_rate_added)
3303                         mlx5_rl_remove_rate(dev, &new_rl);
3304                 goto out;
3305         }
3306
3307         /* Only remove the old rate after new rate was set */
3308         if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3309             (new_state != MLX5_SQC_STATE_RDY)) {
3310                 mlx5_rl_remove_rate(dev, &old_rl);
3311                 if (new_state != MLX5_SQC_STATE_RDY)
3312                         memset(&new_rl, 0, sizeof(new_rl));
3313         }
3314
3315         ibqp->rl = new_rl;
3316         sq->state = new_state;
3317
3318 out:
3319         kvfree(in);
3320         return err;
3321 }
3322
3323 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3324                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3325                                 u8 tx_affinity)
3326 {
3327         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3328         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3329         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3330         int modify_rq = !!qp->rq.wqe_cnt;
3331         int modify_sq = !!qp->sq.wqe_cnt;
3332         int rq_state;
3333         int sq_state;
3334         int err;
3335
3336         switch (raw_qp_param->operation) {
3337         case MLX5_CMD_OP_RST2INIT_QP:
3338                 rq_state = MLX5_RQC_STATE_RDY;
3339                 sq_state = MLX5_SQC_STATE_RDY;
3340                 break;
3341         case MLX5_CMD_OP_2ERR_QP:
3342                 rq_state = MLX5_RQC_STATE_ERR;
3343                 sq_state = MLX5_SQC_STATE_ERR;
3344                 break;
3345         case MLX5_CMD_OP_2RST_QP:
3346                 rq_state = MLX5_RQC_STATE_RST;
3347                 sq_state = MLX5_SQC_STATE_RST;
3348                 break;
3349         case MLX5_CMD_OP_RTR2RTS_QP:
3350         case MLX5_CMD_OP_RTS2RTS_QP:
3351                 if (raw_qp_param->set_mask ==
3352                     MLX5_RAW_QP_RATE_LIMIT) {
3353                         modify_rq = 0;
3354                         sq_state = sq->state;
3355                 } else {
3356                         return raw_qp_param->set_mask ? -EINVAL : 0;
3357                 }
3358                 break;
3359         case MLX5_CMD_OP_INIT2INIT_QP:
3360         case MLX5_CMD_OP_INIT2RTR_QP:
3361                 if (raw_qp_param->set_mask)
3362                         return -EINVAL;
3363                 else
3364                         return 0;
3365         default:
3366                 WARN_ON(1);
3367                 return -EINVAL;
3368         }
3369
3370         if (modify_rq) {
3371                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3372                                                qp->ibqp.pd);
3373                 if (err)
3374                         return err;
3375         }
3376
3377         if (modify_sq) {
3378                 struct mlx5_flow_handle *flow_rule;
3379
3380                 if (tx_affinity) {
3381                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3382                                                             tx_affinity,
3383                                                             qp->ibqp.pd);
3384                         if (err)
3385                                 return err;
3386                 }
3387
3388                 flow_rule = create_flow_rule_vport_sq(dev, sq,
3389                                                       raw_qp_param->port);
3390                 if (IS_ERR(flow_rule))
3391                         return PTR_ERR(flow_rule);
3392
3393                 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3394                                               raw_qp_param, qp->ibqp.pd);
3395                 if (err) {
3396                         if (flow_rule)
3397                                 mlx5_del_flow_rules(flow_rule);
3398                         return err;
3399                 }
3400
3401                 if (flow_rule) {
3402                         destroy_flow_rule_vport_sq(sq);
3403                         sq->flow_rule = flow_rule;
3404                 }
3405
3406                 return err;
3407         }
3408
3409         return 0;
3410 }
3411
3412 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3413                                     struct mlx5_ib_pd *pd,
3414                                     struct mlx5_ib_qp_base *qp_base,
3415                                     u8 port_num, struct ib_udata *udata)
3416 {
3417         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3418                 udata, struct mlx5_ib_ucontext, ibucontext);
3419         unsigned int tx_port_affinity;
3420
3421         if (ucontext) {
3422                 tx_port_affinity = (unsigned int)atomic_add_return(
3423                                            1, &ucontext->tx_port_affinity) %
3424                                            MLX5_MAX_PORTS +
3425                                    1;
3426                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3427                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3428         } else {
3429                 tx_port_affinity =
3430                         (unsigned int)atomic_add_return(
3431                                 1, &dev->port[port_num].roce.tx_port_affinity) %
3432                                 MLX5_MAX_PORTS +
3433                         1;
3434                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3435                                 tx_port_affinity, qp_base->mqp.qpn);
3436         }
3437
3438         return tx_port_affinity;
3439 }
3440
3441 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3442                                     struct rdma_counter *counter)
3443 {
3444         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3445         struct mlx5_ib_qp *mqp = to_mqp(qp);
3446         struct mlx5_qp_context context = {};
3447         struct mlx5_ib_qp_base *base;
3448         u32 set_id;
3449
3450         if (counter)
3451                 set_id = counter->id;
3452         else
3453                 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3454
3455         base = &mqp->trans_qp.base;
3456         context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff);
3457         context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24);
3458         return mlx5_core_qp_modify(dev, MLX5_CMD_OP_RTS2RTS_QP,
3459                                    MLX5_QP_OPTPAR_COUNTER_SET_ID, &context,
3460                                    &base->mqp);
3461 }
3462
3463 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3464                                const struct ib_qp_attr *attr, int attr_mask,
3465                                enum ib_qp_state cur_state,
3466                                enum ib_qp_state new_state,
3467                                const struct mlx5_ib_modify_qp *ucmd,
3468                                struct ib_udata *udata)
3469 {
3470         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3471                 [MLX5_QP_STATE_RST] = {
3472                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3473                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3474                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3475                 },
3476                 [MLX5_QP_STATE_INIT]  = {
3477                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3478                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3479                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3480                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3481                 },
3482                 [MLX5_QP_STATE_RTR]   = {
3483                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3484                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3485                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3486                 },
3487                 [MLX5_QP_STATE_RTS]   = {
3488                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3489                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3490                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3491                 },
3492                 [MLX5_QP_STATE_SQD] = {
3493                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3494                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3495                 },
3496                 [MLX5_QP_STATE_SQER] = {
3497                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3498                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3499                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3500                 },
3501                 [MLX5_QP_STATE_ERR] = {
3502                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3503                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3504                 }
3505         };
3506
3507         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3508         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3509         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3510         struct mlx5_ib_cq *send_cq, *recv_cq;
3511         struct mlx5_qp_context *context;
3512         struct mlx5_ib_pd *pd;
3513         enum mlx5_qp_state mlx5_cur, mlx5_new;
3514         enum mlx5_qp_optpar optpar;
3515         u32 set_id = 0;
3516         int mlx5_st;
3517         int err;
3518         u16 op;
3519         u8 tx_affinity = 0;
3520
3521         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3522                              qp->qp_sub_type : ibqp->qp_type);
3523         if (mlx5_st < 0)
3524                 return -EINVAL;
3525
3526         context = kzalloc(sizeof(*context), GFP_KERNEL);
3527         if (!context)
3528                 return -ENOMEM;
3529
3530         pd = get_pd(qp);
3531         context->flags = cpu_to_be32(mlx5_st << 16);
3532
3533         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3534                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3535         } else {
3536                 switch (attr->path_mig_state) {
3537                 case IB_MIG_MIGRATED:
3538                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3539                         break;
3540                 case IB_MIG_REARM:
3541                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3542                         break;
3543                 case IB_MIG_ARMED:
3544                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3545                         break;
3546                 }
3547         }
3548
3549         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3550                 if ((ibqp->qp_type == IB_QPT_RC) ||
3551                     (ibqp->qp_type == IB_QPT_UD &&
3552                      !(qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)) ||
3553                     (ibqp->qp_type == IB_QPT_UC) ||
3554                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3555                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3556                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3557                         if (dev->lag_active) {
3558                                 u8 p = mlx5_core_native_port_num(dev->mdev) - 1;
3559                                 tx_affinity = get_tx_affinity(dev, pd, base, p,
3560                                                               udata);
3561                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3562                         }
3563                 }
3564         }
3565
3566         if (is_sqp(ibqp->qp_type)) {
3567                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3568         } else if ((ibqp->qp_type == IB_QPT_UD &&
3569                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
3570                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3571                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3572         } else if (attr_mask & IB_QP_PATH_MTU) {
3573                 if (attr->path_mtu < IB_MTU_256 ||
3574                     attr->path_mtu > IB_MTU_4096) {
3575                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3576                         err = -EINVAL;
3577                         goto out;
3578                 }
3579                 context->mtu_msgmax = (attr->path_mtu << 5) |
3580                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3581         }
3582
3583         if (attr_mask & IB_QP_DEST_QPN)
3584                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3585
3586         if (attr_mask & IB_QP_PKEY_INDEX)
3587                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3588
3589         /* todo implement counter_index functionality */
3590
3591         if (is_sqp(ibqp->qp_type))
3592                 context->pri_path.port = qp->port;
3593
3594         if (attr_mask & IB_QP_PORT)
3595                 context->pri_path.port = attr->port_num;
3596
3597         if (attr_mask & IB_QP_AV) {
3598                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3599                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3600                                     attr_mask, 0, attr, false);
3601                 if (err)
3602                         goto out;
3603         }
3604
3605         if (attr_mask & IB_QP_TIMEOUT)
3606                 context->pri_path.ackto_lt |= attr->timeout << 3;
3607
3608         if (attr_mask & IB_QP_ALT_PATH) {
3609                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3610                                     &context->alt_path,
3611                                     attr->alt_port_num,
3612                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3613                                     0, attr, true);
3614                 if (err)
3615                         goto out;
3616         }
3617
3618         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3619                 &send_cq, &recv_cq);
3620
3621         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3622         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3623         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3624         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3625
3626         if (attr_mask & IB_QP_RNR_RETRY)
3627                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3628
3629         if (attr_mask & IB_QP_RETRY_CNT)
3630                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3631
3632         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3633                 if (attr->max_rd_atomic)
3634                         context->params1 |=
3635                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3636         }
3637
3638         if (attr_mask & IB_QP_SQ_PSN)
3639                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3640
3641         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3642                 if (attr->max_dest_rd_atomic)
3643                         context->params2 |=
3644                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3645         }
3646
3647         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3648                 __be32 access_flags;
3649
3650                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3651                 if (err)
3652                         goto out;
3653
3654                 context->params2 |= access_flags;
3655         }
3656
3657         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3658                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3659
3660         if (attr_mask & IB_QP_RQ_PSN)
3661                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3662
3663         if (attr_mask & IB_QP_QKEY)
3664                 context->qkey = cpu_to_be32(attr->qkey);
3665
3666         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3667                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3668
3669         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3670                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3671                                qp->port) - 1;
3672
3673                 /* Underlay port should be used - index 0 function per port */
3674                 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
3675                         port_num = 0;
3676
3677                 if (ibqp->counter)
3678                         set_id = ibqp->counter->id;
3679                 else
3680                         set_id = mlx5_ib_get_counters_id(dev, port_num);
3681                 context->qp_counter_set_usr_page |=
3682                         cpu_to_be32(set_id << 24);
3683         }
3684
3685         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3686                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3687
3688         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3689                 context->deth_sqpn = cpu_to_be32(1);
3690
3691         mlx5_cur = to_mlx5_state(cur_state);
3692         mlx5_new = to_mlx5_state(new_state);
3693
3694         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3695             !optab[mlx5_cur][mlx5_new]) {
3696                 err = -EINVAL;
3697                 goto out;
3698         }
3699
3700         op = optab[mlx5_cur][mlx5_new];
3701         optpar = ib_mask_to_mlx5_opt(attr_mask);
3702         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3703
3704         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3705             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
3706                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3707
3708                 raw_qp_param.operation = op;
3709                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3710                         raw_qp_param.rq_q_ctr_id = set_id;
3711                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3712                 }
3713
3714                 if (attr_mask & IB_QP_PORT)
3715                         raw_qp_param.port = attr->port_num;
3716
3717                 if (attr_mask & IB_QP_RATE_LIMIT) {
3718                         raw_qp_param.rl.rate = attr->rate_limit;
3719
3720                         if (ucmd->burst_info.max_burst_sz) {
3721                                 if (attr->rate_limit &&
3722                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3723                                         raw_qp_param.rl.max_burst_sz =
3724                                                 ucmd->burst_info.max_burst_sz;
3725                                 } else {
3726                                         err = -EINVAL;
3727                                         goto out;
3728                                 }
3729                         }
3730
3731                         if (ucmd->burst_info.typical_pkt_sz) {
3732                                 if (attr->rate_limit &&
3733                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3734                                         raw_qp_param.rl.typical_pkt_sz =
3735                                                 ucmd->burst_info.typical_pkt_sz;
3736                                 } else {
3737                                         err = -EINVAL;
3738                                         goto out;
3739                                 }
3740                         }
3741
3742                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3743                 }
3744
3745                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3746         } else {
3747                 err = mlx5_core_qp_modify(dev, op, optpar, context, &base->mqp);
3748         }
3749
3750         if (err)
3751                 goto out;
3752
3753         qp->state = new_state;
3754
3755         if (attr_mask & IB_QP_ACCESS_FLAGS)
3756                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3757         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3758                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3759         if (attr_mask & IB_QP_PORT)
3760                 qp->port = attr->port_num;
3761         if (attr_mask & IB_QP_ALT_PATH)
3762                 qp->trans_qp.alt_port = attr->alt_port_num;
3763
3764         /*
3765          * If we moved a kernel QP to RESET, clean up all old CQ
3766          * entries and reinitialize the QP.
3767          */
3768         if (new_state == IB_QPS_RESET &&
3769             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3770                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3771                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3772                 if (send_cq != recv_cq)
3773                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3774
3775                 qp->rq.head = 0;
3776                 qp->rq.tail = 0;
3777                 qp->sq.head = 0;
3778                 qp->sq.tail = 0;
3779                 qp->sq.cur_post = 0;
3780                 if (qp->sq.wqe_cnt)
3781                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3782                 qp->sq.last_poll = 0;
3783                 qp->db.db[MLX5_RCV_DBR] = 0;
3784                 qp->db.db[MLX5_SND_DBR] = 0;
3785         }
3786
3787         if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
3788                 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
3789                 if (!err)
3790                         qp->counter_pending = 0;
3791         }
3792
3793 out:
3794         kfree(context);
3795         return err;
3796 }
3797
3798 static inline bool is_valid_mask(int mask, int req, int opt)
3799 {
3800         if ((mask & req) != req)
3801                 return false;
3802
3803         if (mask & ~(req | opt))
3804                 return false;
3805
3806         return true;
3807 }
3808
3809 /* check valid transition for driver QP types
3810  * for now the only QP type that this function supports is DCI
3811  */
3812 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3813                                 enum ib_qp_attr_mask attr_mask)
3814 {
3815         int req = IB_QP_STATE;
3816         int opt = 0;
3817
3818         if (new_state == IB_QPS_RESET) {
3819                 return is_valid_mask(attr_mask, req, opt);
3820         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3821                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3822                 return is_valid_mask(attr_mask, req, opt);
3823         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3824                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3825                 return is_valid_mask(attr_mask, req, opt);
3826         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3827                 req |= IB_QP_PATH_MTU;
3828                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3829                 return is_valid_mask(attr_mask, req, opt);
3830         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3831                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3832                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3833                 opt = IB_QP_MIN_RNR_TIMER;
3834                 return is_valid_mask(attr_mask, req, opt);
3835         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3836                 opt = IB_QP_MIN_RNR_TIMER;
3837                 return is_valid_mask(attr_mask, req, opt);
3838         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3839                 return is_valid_mask(attr_mask, req, opt);
3840         }
3841         return false;
3842 }
3843
3844 /* mlx5_ib_modify_dct: modify a DCT QP
3845  * valid transitions are:
3846  * RESET to INIT: must set access_flags, pkey_index and port
3847  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3848  *                         mtu, gid_index and hop_limit
3849  * Other transitions and attributes are illegal
3850  */
3851 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3852                               int attr_mask, struct ib_udata *udata)
3853 {
3854         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3855         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3856         enum ib_qp_state cur_state, new_state;
3857         int err = 0;
3858         int required = IB_QP_STATE;
3859         void *dctc;
3860
3861         if (!(attr_mask & IB_QP_STATE))
3862                 return -EINVAL;
3863
3864         cur_state = qp->state;
3865         new_state = attr->qp_state;
3866
3867         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3868         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3869                 u16 set_id;
3870
3871                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3872                 if (!is_valid_mask(attr_mask, required, 0))
3873                         return -EINVAL;
3874
3875                 if (attr->port_num == 0 ||
3876                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3877                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3878                                     attr->port_num, dev->num_ports);
3879                         return -EINVAL;
3880                 }
3881                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3882                         MLX5_SET(dctc, dctc, rre, 1);
3883                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3884                         MLX5_SET(dctc, dctc, rwe, 1);
3885                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3886                         int atomic_mode;
3887
3888                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3889                         if (atomic_mode < 0)
3890                                 return -EOPNOTSUPP;
3891
3892                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3893                         MLX5_SET(dctc, dctc, rae, 1);
3894                 }
3895                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3896                 MLX5_SET(dctc, dctc, port, attr->port_num);
3897
3898                 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
3899                 MLX5_SET(dctc, dctc, counter_set_id, set_id);
3900
3901         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3902                 struct mlx5_ib_modify_qp_resp resp = {};
3903                 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
3904                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3905                                    sizeof(resp.dctn);
3906
3907                 if (udata->outlen < min_resp_len)
3908                         return -EINVAL;
3909                 resp.response_length = min_resp_len;
3910
3911                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3912                 if (!is_valid_mask(attr_mask, required, 0))
3913                         return -EINVAL;
3914                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3915                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3916                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3917                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3918                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3919                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3920
3921                 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
3922                                            MLX5_ST_SZ_BYTES(create_dct_in), out,
3923                                            sizeof(out));
3924                 if (err)
3925                         return err;
3926                 resp.dctn = qp->dct.mdct.mqp.qpn;
3927                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3928                 if (err) {
3929                         mlx5_core_destroy_dct(dev, &qp->dct.mdct);
3930                         return err;
3931                 }
3932         } else {
3933                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3934                 return -EINVAL;
3935         }
3936         if (err)
3937                 qp->state = IB_QPS_ERR;
3938         else
3939                 qp->state = new_state;
3940         return err;
3941 }
3942
3943 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3944                       int attr_mask, struct ib_udata *udata)
3945 {
3946         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3947         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3948         struct mlx5_ib_modify_qp ucmd = {};
3949         enum ib_qp_type qp_type;
3950         enum ib_qp_state cur_state, new_state;
3951         size_t required_cmd_sz;
3952         int err = -EINVAL;
3953         int port;
3954
3955         if (ibqp->rwq_ind_tbl)
3956                 return -ENOSYS;
3957
3958         if (udata && udata->inlen) {
3959                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3960                         sizeof(ucmd.reserved);
3961                 if (udata->inlen < required_cmd_sz)
3962                         return -EINVAL;
3963
3964                 if (udata->inlen > sizeof(ucmd) &&
3965                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3966                                          udata->inlen - sizeof(ucmd)))
3967                         return -EOPNOTSUPP;
3968
3969                 if (ib_copy_from_udata(&ucmd, udata,
3970                                        min(udata->inlen, sizeof(ucmd))))
3971                         return -EFAULT;
3972
3973                 if (ucmd.comp_mask ||
3974                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3975                     memchr_inv(&ucmd.burst_info.reserved, 0,
3976                                sizeof(ucmd.burst_info.reserved)))
3977                         return -EOPNOTSUPP;
3978         }
3979
3980         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3981                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3982
3983         if (ibqp->qp_type == IB_QPT_DRIVER)
3984                 qp_type = qp->qp_sub_type;
3985         else
3986                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3987                         IB_QPT_GSI : ibqp->qp_type;
3988
3989         if (qp_type == MLX5_IB_QPT_DCT)
3990                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3991
3992         mutex_lock(&qp->mutex);
3993
3994         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3995         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3996
3997         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3998                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3999         }
4000
4001         if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4002                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4003                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4004                                     attr_mask);
4005                         goto out;
4006                 }
4007         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
4008                    qp_type != MLX5_IB_QPT_DCI &&
4009                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4010                                        attr_mask)) {
4011                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4012                             cur_state, new_state, ibqp->qp_type, attr_mask);
4013                 goto out;
4014         } else if (qp_type == MLX5_IB_QPT_DCI &&
4015                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4016                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4017                             cur_state, new_state, qp_type, attr_mask);
4018                 goto out;
4019         }
4020
4021         if ((attr_mask & IB_QP_PORT) &&
4022             (attr->port_num == 0 ||
4023              attr->port_num > dev->num_ports)) {
4024                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4025                             attr->port_num, dev->num_ports);
4026                 goto out;
4027         }
4028
4029         if (attr_mask & IB_QP_PKEY_INDEX) {
4030                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4031                 if (attr->pkey_index >=
4032                     dev->mdev->port_caps[port - 1].pkey_table_len) {
4033                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4034                                     attr->pkey_index);
4035                         goto out;
4036                 }
4037         }
4038
4039         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
4040             attr->max_rd_atomic >
4041             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4042                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4043                             attr->max_rd_atomic);
4044                 goto out;
4045         }
4046
4047         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
4048             attr->max_dest_rd_atomic >
4049             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4050                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4051                             attr->max_dest_rd_atomic);
4052                 goto out;
4053         }
4054
4055         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4056                 err = 0;
4057                 goto out;
4058         }
4059
4060         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4061                                   new_state, &ucmd, udata);
4062
4063 out:
4064         mutex_unlock(&qp->mutex);
4065         return err;
4066 }
4067
4068 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4069                                    u32 wqe_sz, void **cur_edge)
4070 {
4071         u32 idx;
4072
4073         idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
4074         *cur_edge = get_sq_edge(sq, idx);
4075
4076         *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
4077 }
4078
4079 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
4080  * next nearby edge and get new address translation for current WQE position.
4081  * @sq - SQ buffer.
4082  * @seg: Current WQE position (16B aligned).
4083  * @wqe_sz: Total current WQE size [16B].
4084  * @cur_edge: Updated current edge.
4085  */
4086 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4087                                          u32 wqe_sz, void **cur_edge)
4088 {
4089         if (likely(*seg != *cur_edge))
4090                 return;
4091
4092         _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
4093 }
4094
4095 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
4096  * pointers. At the end @seg is aligned to 16B regardless the copied size.
4097  * @sq - SQ buffer.
4098  * @cur_edge: Updated current edge.
4099  * @seg: Current WQE position (16B aligned).
4100  * @wqe_sz: Total current WQE size [16B].
4101  * @src: Pointer to copy from.
4102  * @n: Number of bytes to copy.
4103  */
4104 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
4105                                    void **seg, u32 *wqe_sz, const void *src,
4106                                    size_t n)
4107 {
4108         while (likely(n)) {
4109                 size_t leftlen = *cur_edge - *seg;
4110                 size_t copysz = min_t(size_t, leftlen, n);
4111                 size_t stride;
4112
4113                 memcpy(*seg, src, copysz);
4114
4115                 n -= copysz;
4116                 src += copysz;
4117                 stride = !n ? ALIGN(copysz, 16) : copysz;
4118                 *seg += stride;
4119                 *wqe_sz += stride >> 4;
4120                 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
4121         }
4122 }
4123
4124 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
4125 {
4126         struct mlx5_ib_cq *cq;
4127         unsigned cur;
4128
4129         cur = wq->head - wq->tail;
4130         if (likely(cur + nreq < wq->max_post))
4131                 return 0;
4132
4133         cq = to_mcq(ib_cq);
4134         spin_lock(&cq->lock);
4135         cur = wq->head - wq->tail;
4136         spin_unlock(&cq->lock);
4137
4138         return cur + nreq >= wq->max_post;
4139 }
4140
4141 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
4142                                           u64 remote_addr, u32 rkey)
4143 {
4144         rseg->raddr    = cpu_to_be64(remote_addr);
4145         rseg->rkey     = cpu_to_be32(rkey);
4146         rseg->reserved = 0;
4147 }
4148
4149 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
4150                         void **seg, int *size, void **cur_edge)
4151 {
4152         struct mlx5_wqe_eth_seg *eseg = *seg;
4153
4154         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
4155
4156         if (wr->send_flags & IB_SEND_IP_CSUM)
4157                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
4158                                  MLX5_ETH_WQE_L4_CSUM;
4159
4160         if (wr->opcode == IB_WR_LSO) {
4161                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
4162                 size_t left, copysz;
4163                 void *pdata = ud_wr->header;
4164                 size_t stride;
4165
4166                 left = ud_wr->hlen;
4167                 eseg->mss = cpu_to_be16(ud_wr->mss);
4168                 eseg->inline_hdr.sz = cpu_to_be16(left);
4169
4170                 /* memcpy_send_wqe should get a 16B align address. Hence, we
4171                  * first copy up to the current edge and then, if needed,
4172                  * fall-through to memcpy_send_wqe.
4173                  */
4174                 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
4175                                left);
4176                 memcpy(eseg->inline_hdr.start, pdata, copysz);
4177                 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
4178                                sizeof(eseg->inline_hdr.start) + copysz, 16);
4179                 *size += stride / 16;
4180                 *seg += stride;
4181
4182                 if (copysz < left) {
4183                         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4184                         left -= copysz;
4185                         pdata += copysz;
4186                         memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4187                                         left);
4188                 }
4189
4190                 return;
4191         }
4192
4193         *seg += sizeof(struct mlx5_wqe_eth_seg);
4194         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
4195 }
4196
4197 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
4198                              const struct ib_send_wr *wr)
4199 {
4200         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4201         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4202         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
4203 }
4204
4205 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4206 {
4207         dseg->byte_count = cpu_to_be32(sg->length);
4208         dseg->lkey       = cpu_to_be32(sg->lkey);
4209         dseg->addr       = cpu_to_be64(sg->addr);
4210 }
4211
4212 static u64 get_xlt_octo(u64 bytes)
4213 {
4214         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4215                MLX5_IB_UMR_OCTOWORD;
4216 }
4217
4218 static __be64 frwr_mkey_mask(bool atomic)
4219 {
4220         u64 result;
4221
4222         result = MLX5_MKEY_MASK_LEN             |
4223                 MLX5_MKEY_MASK_PAGE_SIZE        |
4224                 MLX5_MKEY_MASK_START_ADDR       |
4225                 MLX5_MKEY_MASK_EN_RINVAL        |
4226                 MLX5_MKEY_MASK_KEY              |
4227                 MLX5_MKEY_MASK_LR               |
4228                 MLX5_MKEY_MASK_LW               |
4229                 MLX5_MKEY_MASK_RR               |
4230                 MLX5_MKEY_MASK_RW               |
4231                 MLX5_MKEY_MASK_SMALL_FENCE      |
4232                 MLX5_MKEY_MASK_FREE;
4233
4234         if (atomic)
4235                 result |= MLX5_MKEY_MASK_A;
4236
4237         return cpu_to_be64(result);
4238 }
4239
4240 static __be64 sig_mkey_mask(void)
4241 {
4242         u64 result;
4243
4244         result = MLX5_MKEY_MASK_LEN             |
4245                 MLX5_MKEY_MASK_PAGE_SIZE        |
4246                 MLX5_MKEY_MASK_START_ADDR       |
4247                 MLX5_MKEY_MASK_EN_SIGERR        |
4248                 MLX5_MKEY_MASK_EN_RINVAL        |
4249                 MLX5_MKEY_MASK_KEY              |
4250                 MLX5_MKEY_MASK_LR               |
4251                 MLX5_MKEY_MASK_LW               |
4252                 MLX5_MKEY_MASK_RR               |
4253                 MLX5_MKEY_MASK_RW               |
4254                 MLX5_MKEY_MASK_SMALL_FENCE      |
4255                 MLX5_MKEY_MASK_FREE             |
4256                 MLX5_MKEY_MASK_BSF_EN;
4257
4258         return cpu_to_be64(result);
4259 }
4260
4261 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
4262                             struct mlx5_ib_mr *mr, u8 flags, bool atomic)
4263 {
4264         int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4265
4266         memset(umr, 0, sizeof(*umr));
4267
4268         umr->flags = flags;
4269         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4270         umr->mkey_mask = frwr_mkey_mask(atomic);
4271 }
4272
4273 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4274 {
4275         memset(umr, 0, sizeof(*umr));
4276         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4277         umr->flags = MLX5_UMR_INLINE;
4278 }
4279
4280 static __be64 get_umr_enable_mr_mask(void)
4281 {
4282         u64 result;
4283
4284         result = MLX5_MKEY_MASK_KEY |
4285                  MLX5_MKEY_MASK_FREE;
4286
4287         return cpu_to_be64(result);
4288 }
4289
4290 static __be64 get_umr_disable_mr_mask(void)
4291 {
4292         u64 result;
4293
4294         result = MLX5_MKEY_MASK_FREE;
4295
4296         return cpu_to_be64(result);
4297 }
4298
4299 static __be64 get_umr_update_translation_mask(void)
4300 {
4301         u64 result;
4302
4303         result = MLX5_MKEY_MASK_LEN |
4304                  MLX5_MKEY_MASK_PAGE_SIZE |
4305                  MLX5_MKEY_MASK_START_ADDR;
4306
4307         return cpu_to_be64(result);
4308 }
4309
4310 static __be64 get_umr_update_access_mask(int atomic)
4311 {
4312         u64 result;
4313
4314         result = MLX5_MKEY_MASK_LR |
4315                  MLX5_MKEY_MASK_LW |
4316                  MLX5_MKEY_MASK_RR |
4317                  MLX5_MKEY_MASK_RW;
4318
4319         if (atomic)
4320                 result |= MLX5_MKEY_MASK_A;
4321
4322         return cpu_to_be64(result);
4323 }
4324
4325 static __be64 get_umr_update_pd_mask(void)
4326 {
4327         u64 result;
4328
4329         result = MLX5_MKEY_MASK_PD;
4330
4331         return cpu_to_be64(result);
4332 }
4333
4334 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4335 {
4336         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4337              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4338             (mask & MLX5_MKEY_MASK_A &&
4339              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4340                 return -EPERM;
4341         return 0;
4342 }
4343
4344 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4345                                struct mlx5_wqe_umr_ctrl_seg *umr,
4346                                const struct ib_send_wr *wr, int atomic)
4347 {
4348         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4349
4350         memset(umr, 0, sizeof(*umr));
4351
4352         if (!umrwr->ignore_free_state) {
4353                 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4354                          /* fail if free */
4355                         umr->flags = MLX5_UMR_CHECK_FREE;
4356                 else
4357                         /* fail if not free */
4358                         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
4359         }
4360
4361         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4362         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4363                 u64 offset = get_xlt_octo(umrwr->offset);
4364
4365                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4366                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4367                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4368         }
4369         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4370                 umr->mkey_mask |= get_umr_update_translation_mask();
4371         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4372                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4373                 umr->mkey_mask |= get_umr_update_pd_mask();
4374         }
4375         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4376                 umr->mkey_mask |= get_umr_enable_mr_mask();
4377         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4378                 umr->mkey_mask |= get_umr_disable_mr_mask();
4379
4380         if (!wr->num_sge)
4381                 umr->flags |= MLX5_UMR_INLINE;
4382
4383         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4384 }
4385
4386 static u8 get_umr_flags(int acc)
4387 {
4388         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4389                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4390                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4391                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4392                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4393 }
4394
4395 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4396                              struct mlx5_ib_mr *mr,
4397                              u32 key, int access)
4398 {
4399         int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1;
4400
4401         memset(seg, 0, sizeof(*seg));
4402
4403         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4404                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4405         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4406                 /* KLMs take twice the size of MTTs */
4407                 ndescs *= 2;
4408
4409         seg->flags = get_umr_flags(access) | mr->access_mode;
4410         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4411         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4412         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4413         seg->len = cpu_to_be64(mr->ibmr.length);
4414         seg->xlt_oct_size = cpu_to_be32(ndescs);
4415 }
4416
4417 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4418 {
4419         memset(seg, 0, sizeof(*seg));
4420         seg->status = MLX5_MKEY_STATUS_FREE;
4421 }
4422
4423 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4424                                  const struct ib_send_wr *wr)
4425 {
4426         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4427
4428         memset(seg, 0, sizeof(*seg));
4429         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4430                 seg->status = MLX5_MKEY_STATUS_FREE;
4431
4432         seg->flags = convert_access(umrwr->access_flags);
4433         if (umrwr->pd)
4434                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4435         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4436             !umrwr->length)
4437                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4438
4439         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4440         seg->len = cpu_to_be64(umrwr->length);
4441         seg->log2_page_size = umrwr->page_shift;
4442         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4443                                        mlx5_mkey_variant(umrwr->mkey));
4444 }
4445
4446 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4447                              struct mlx5_ib_mr *mr,
4448                              struct mlx5_ib_pd *pd)
4449 {
4450         int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs);
4451
4452         dseg->addr = cpu_to_be64(mr->desc_map);
4453         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4454         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4455 }
4456
4457 static __be32 send_ieth(const struct ib_send_wr *wr)
4458 {
4459         switch (wr->opcode) {
4460         case IB_WR_SEND_WITH_IMM:
4461         case IB_WR_RDMA_WRITE_WITH_IMM:
4462                 return wr->ex.imm_data;
4463
4464         case IB_WR_SEND_WITH_INV:
4465                 return cpu_to_be32(wr->ex.invalidate_rkey);
4466
4467         default:
4468                 return 0;
4469         }
4470 }
4471
4472 static u8 calc_sig(void *wqe, int size)
4473 {
4474         u8 *p = wqe;
4475         u8 res = 0;
4476         int i;
4477
4478         for (i = 0; i < size; i++)
4479                 res ^= p[i];
4480
4481         return ~res;
4482 }
4483
4484 static u8 wq_sig(void *wqe)
4485 {
4486         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4487 }
4488
4489 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4490                             void **wqe, int *wqe_sz, void **cur_edge)
4491 {
4492         struct mlx5_wqe_inline_seg *seg;
4493         size_t offset;
4494         int inl = 0;
4495         int i;
4496
4497         seg = *wqe;
4498         *wqe += sizeof(*seg);
4499         offset = sizeof(*seg);
4500
4501         for (i = 0; i < wr->num_sge; i++) {
4502                 size_t len  = wr->sg_list[i].length;
4503                 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4504
4505                 inl += len;
4506
4507                 if (unlikely(inl > qp->max_inline_data))
4508                         return -ENOMEM;
4509
4510                 while (likely(len)) {
4511                         size_t leftlen;
4512                         size_t copysz;
4513
4514                         handle_post_send_edge(&qp->sq, wqe,
4515                                               *wqe_sz + (offset >> 4),
4516                                               cur_edge);
4517
4518                         leftlen = *cur_edge - *wqe;
4519                         copysz = min_t(size_t, leftlen, len);
4520
4521                         memcpy(*wqe, addr, copysz);
4522                         len -= copysz;
4523                         addr += copysz;
4524                         *wqe += copysz;
4525                         offset += copysz;
4526                 }
4527         }
4528
4529         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4530
4531         *wqe_sz +=  ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4532
4533         return 0;
4534 }
4535
4536 static u16 prot_field_size(enum ib_signature_type type)
4537 {
4538         switch (type) {
4539         case IB_SIG_TYPE_T10_DIF:
4540                 return MLX5_DIF_SIZE;
4541         default:
4542                 return 0;
4543         }
4544 }
4545
4546 static u8 bs_selector(int block_size)
4547 {
4548         switch (block_size) {
4549         case 512:           return 0x1;
4550         case 520:           return 0x2;
4551         case 4096:          return 0x3;
4552         case 4160:          return 0x4;
4553         case 1073741824:    return 0x5;
4554         default:            return 0;
4555         }
4556 }
4557
4558 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4559                               struct mlx5_bsf_inl *inl)
4560 {
4561         /* Valid inline section and allow BSF refresh */
4562         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4563                                        MLX5_BSF_REFRESH_DIF);
4564         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4565         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4566         /* repeating block */
4567         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4568         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4569                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4570
4571         if (domain->sig.dif.ref_remap)
4572                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4573
4574         if (domain->sig.dif.app_escape) {
4575                 if (domain->sig.dif.ref_escape)
4576                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4577                 else
4578                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4579         }
4580
4581         inl->dif_app_bitmask_check =
4582                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4583 }
4584
4585 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4586                         struct ib_sig_attrs *sig_attrs,
4587                         struct mlx5_bsf *bsf, u32 data_size)
4588 {
4589         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4590         struct mlx5_bsf_basic *basic = &bsf->basic;
4591         struct ib_sig_domain *mem = &sig_attrs->mem;
4592         struct ib_sig_domain *wire = &sig_attrs->wire;
4593
4594         memset(bsf, 0, sizeof(*bsf));
4595
4596         /* Basic + Extended + Inline */
4597         basic->bsf_size_sbs = 1 << 7;
4598         /* Input domain check byte mask */
4599         basic->check_byte_mask = sig_attrs->check_mask;
4600         basic->raw_data_size = cpu_to_be32(data_size);
4601
4602         /* Memory domain */
4603         switch (sig_attrs->mem.sig_type) {
4604         case IB_SIG_TYPE_NONE:
4605                 break;
4606         case IB_SIG_TYPE_T10_DIF:
4607                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4608                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4609                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4610                 break;
4611         default:
4612                 return -EINVAL;
4613         }
4614
4615         /* Wire domain */
4616         switch (sig_attrs->wire.sig_type) {
4617         case IB_SIG_TYPE_NONE:
4618                 break;
4619         case IB_SIG_TYPE_T10_DIF:
4620                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4621                     mem->sig_type == wire->sig_type) {
4622                         /* Same block structure */
4623                         basic->bsf_size_sbs |= 1 << 4;
4624                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4625                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4626                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4627                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4628                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4629                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4630                 } else
4631                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4632
4633                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4634                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4635                 break;
4636         default:
4637                 return -EINVAL;
4638         }
4639
4640         return 0;
4641 }
4642
4643 static int set_sig_data_segment(const struct ib_send_wr *send_wr,
4644                                 struct ib_mr *sig_mr,
4645                                 struct ib_sig_attrs *sig_attrs,
4646                                 struct mlx5_ib_qp *qp, void **seg, int *size,
4647                                 void **cur_edge)
4648 {
4649         struct mlx5_bsf *bsf;
4650         u32 data_len;
4651         u32 data_key;
4652         u64 data_va;
4653         u32 prot_len = 0;
4654         u32 prot_key = 0;
4655         u64 prot_va = 0;
4656         bool prot = false;
4657         int ret;
4658         int wqe_size;
4659         struct mlx5_ib_mr *mr = to_mmr(sig_mr);
4660         struct mlx5_ib_mr *pi_mr = mr->pi_mr;
4661
4662         data_len = pi_mr->data_length;
4663         data_key = pi_mr->ibmr.lkey;
4664         data_va = pi_mr->data_iova;
4665         if (pi_mr->meta_ndescs) {
4666                 prot_len = pi_mr->meta_length;
4667                 prot_key = pi_mr->ibmr.lkey;
4668                 prot_va = pi_mr->pi_iova;
4669                 prot = true;
4670         }
4671
4672         if (!prot || (data_key == prot_key && data_va == prot_va &&
4673                       data_len == prot_len)) {
4674                 /**
4675                  * Source domain doesn't contain signature information
4676                  * or data and protection are interleaved in memory.
4677                  * So need construct:
4678                  *                  ------------------
4679                  *                 |     data_klm     |
4680                  *                  ------------------
4681                  *                 |       BSF        |
4682                  *                  ------------------
4683                  **/
4684                 struct mlx5_klm *data_klm = *seg;
4685
4686                 data_klm->bcount = cpu_to_be32(data_len);
4687                 data_klm->key = cpu_to_be32(data_key);
4688                 data_klm->va = cpu_to_be64(data_va);
4689                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4690         } else {
4691                 /**
4692                  * Source domain contains signature information
4693                  * So need construct a strided block format:
4694                  *               ---------------------------
4695                  *              |     stride_block_ctrl     |
4696                  *               ---------------------------
4697                  *              |          data_klm         |
4698                  *               ---------------------------
4699                  *              |          prot_klm         |
4700                  *               ---------------------------
4701                  *              |             BSF           |
4702                  *               ---------------------------
4703                  **/
4704                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4705                 struct mlx5_stride_block_entry *data_sentry;
4706                 struct mlx5_stride_block_entry *prot_sentry;
4707                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4708                 int prot_size;
4709
4710                 sblock_ctrl = *seg;
4711                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4712                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4713
4714                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4715                 if (!prot_size) {
4716                         pr_err("Bad block size given: %u\n", block_size);
4717                         return -EINVAL;
4718                 }
4719                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4720                                                             prot_size);
4721                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4722                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4723                 sblock_ctrl->num_entries = cpu_to_be16(2);
4724
4725                 data_sentry->bcount = cpu_to_be16(block_size);
4726                 data_sentry->key = cpu_to_be32(data_key);
4727                 data_sentry->va = cpu_to_be64(data_va);
4728                 data_sentry->stride = cpu_to_be16(block_size);
4729
4730                 prot_sentry->bcount = cpu_to_be16(prot_size);
4731                 prot_sentry->key = cpu_to_be32(prot_key);
4732                 prot_sentry->va = cpu_to_be64(prot_va);
4733                 prot_sentry->stride = cpu_to_be16(prot_size);
4734
4735                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4736                                  sizeof(*prot_sentry), 64);
4737         }
4738
4739         *seg += wqe_size;
4740         *size += wqe_size / 16;
4741         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4742
4743         bsf = *seg;
4744         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4745         if (ret)
4746                 return -EINVAL;
4747
4748         *seg += sizeof(*bsf);
4749         *size += sizeof(*bsf) / 16;
4750         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4751
4752         return 0;
4753 }
4754
4755 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4756                                  struct ib_mr *sig_mr, int access_flags,
4757                                  u32 size, u32 length, u32 pdn)
4758 {
4759         u32 sig_key = sig_mr->rkey;
4760         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4761
4762         memset(seg, 0, sizeof(*seg));
4763
4764         seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS;
4765         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4766         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4767                                     MLX5_MKEY_BSF_EN | pdn);
4768         seg->len = cpu_to_be64(length);
4769         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4770         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4771 }
4772
4773 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4774                                 u32 size)
4775 {
4776         memset(umr, 0, sizeof(*umr));
4777
4778         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4779         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4780         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4781         umr->mkey_mask = sig_mkey_mask();
4782 }
4783
4784 static int set_pi_umr_wr(const struct ib_send_wr *send_wr,
4785                          struct mlx5_ib_qp *qp, void **seg, int *size,
4786                          void **cur_edge)
4787 {
4788         const struct ib_reg_wr *wr = reg_wr(send_wr);
4789         struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr);
4790         struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr;
4791         struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs;
4792         u32 pdn = get_pd(qp)->pdn;
4793         u32 xlt_size;
4794         int region_len, ret;
4795
4796         if (unlikely(send_wr->num_sge != 0) ||
4797             unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) ||
4798             unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) ||
4799             unlikely(!sig_mr->sig->sig_status_checked))
4800                 return -EINVAL;
4801
4802         /* length of the protected region, data + protection */
4803         region_len = pi_mr->ibmr.length;
4804
4805         /**
4806          * KLM octoword size - if protection was provided
4807          * then we use strided block format (3 octowords),
4808          * else we use single KLM (1 octoword)
4809          **/
4810         if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE)
4811                 xlt_size = 0x30;
4812         else
4813                 xlt_size = sizeof(struct mlx5_klm);
4814
4815         set_sig_umr_segment(*seg, xlt_size);
4816         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4817         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4818         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4819
4820         set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len,
4821                              pdn);
4822         *seg += sizeof(struct mlx5_mkey_seg);
4823         *size += sizeof(struct mlx5_mkey_seg) / 16;
4824         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4825
4826         ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size,
4827                                    cur_edge);
4828         if (ret)
4829                 return ret;
4830
4831         sig_mr->sig->sig_status_checked = false;
4832         return 0;
4833 }
4834
4835 static int set_psv_wr(struct ib_sig_domain *domain,
4836                       u32 psv_idx, void **seg, int *size)
4837 {
4838         struct mlx5_seg_set_psv *psv_seg = *seg;
4839
4840         memset(psv_seg, 0, sizeof(*psv_seg));
4841         psv_seg->psv_num = cpu_to_be32(psv_idx);
4842         switch (domain->sig_type) {
4843         case IB_SIG_TYPE_NONE:
4844                 break;
4845         case IB_SIG_TYPE_T10_DIF:
4846                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4847                                                      domain->sig.dif.app_tag);
4848                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4849                 break;
4850         default:
4851                 pr_err("Bad signature type (%d) is given.\n",
4852                        domain->sig_type);
4853                 return -EINVAL;
4854         }
4855
4856         *seg += sizeof(*psv_seg);
4857         *size += sizeof(*psv_seg) / 16;
4858
4859         return 0;
4860 }
4861
4862 static int set_reg_wr(struct mlx5_ib_qp *qp,
4863                       const struct ib_reg_wr *wr,
4864                       void **seg, int *size, void **cur_edge,
4865                       bool check_not_free)
4866 {
4867         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4868         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4869         struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device);
4870         int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4871         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4872         bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC;
4873         u8 flags = 0;
4874
4875         if (!mlx5_ib_can_use_umr(dev, atomic, wr->access)) {
4876                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4877                              "Fast update of %s for MR is disabled\n",
4878                              (MLX5_CAP_GEN(dev->mdev,
4879                                            umr_modify_entity_size_disabled)) ?
4880                                      "entity size" :
4881                                      "atomic access");
4882                 return -EINVAL;
4883         }
4884
4885         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4886                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4887                              "Invalid IB_SEND_INLINE send flag\n");
4888                 return -EINVAL;
4889         }
4890
4891         if (check_not_free)
4892                 flags |= MLX5_UMR_CHECK_NOT_FREE;
4893         if (umr_inline)
4894                 flags |= MLX5_UMR_INLINE;
4895
4896         set_reg_umr_seg(*seg, mr, flags, atomic);
4897         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4898         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4899         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4900
4901         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4902         *seg += sizeof(struct mlx5_mkey_seg);
4903         *size += sizeof(struct mlx5_mkey_seg) / 16;
4904         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4905
4906         if (umr_inline) {
4907                 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4908                                 mr_list_size);
4909                 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4910         } else {
4911                 set_reg_data_seg(*seg, mr, pd);
4912                 *seg += sizeof(struct mlx5_wqe_data_seg);
4913                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4914         }
4915         return 0;
4916 }
4917
4918 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4919                         void **cur_edge)
4920 {
4921         set_linv_umr_seg(*seg);
4922         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4923         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4924         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4925         set_linv_mkey_seg(*seg);
4926         *seg += sizeof(struct mlx5_mkey_seg);
4927         *size += sizeof(struct mlx5_mkey_seg) / 16;
4928         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4929 }
4930
4931 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4932 {
4933         __be32 *p = NULL;
4934         int i, j;
4935
4936         pr_debug("dump WQE index %u:\n", idx);
4937         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4938                 if ((i & 0xf) == 0) {
4939                         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
4940                         pr_debug("WQBB at %p:\n", (void *)p);
4941                         j = 0;
4942                         idx = (idx + 1) & (qp->sq.wqe_cnt - 1);
4943                 }
4944                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4945                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4946                          be32_to_cpu(p[j + 3]));
4947         }
4948 }
4949
4950 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4951                        struct mlx5_wqe_ctrl_seg **ctrl,
4952                        const struct ib_send_wr *wr, unsigned int *idx,
4953                        int *size, void **cur_edge, int nreq,
4954                        bool send_signaled, bool solicited)
4955 {
4956         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4957                 return -ENOMEM;
4958
4959         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4960         *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4961         *ctrl = *seg;
4962         *(uint32_t *)(*seg + 8) = 0;
4963         (*ctrl)->imm = send_ieth(wr);
4964         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4965                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4966                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4967
4968         *seg += sizeof(**ctrl);
4969         *size = sizeof(**ctrl) / 16;
4970         *cur_edge = qp->sq.cur_edge;
4971
4972         return 0;
4973 }
4974
4975 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4976                      struct mlx5_wqe_ctrl_seg **ctrl,
4977                      const struct ib_send_wr *wr, unsigned *idx,
4978                      int *size, void **cur_edge, int nreq)
4979 {
4980         return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4981                            wr->send_flags & IB_SEND_SIGNALED,
4982                            wr->send_flags & IB_SEND_SOLICITED);
4983 }
4984
4985 static void finish_wqe(struct mlx5_ib_qp *qp,
4986                        struct mlx5_wqe_ctrl_seg *ctrl,
4987                        void *seg, u8 size, void *cur_edge,
4988                        unsigned int idx, u64 wr_id, int nreq, u8 fence,
4989                        u32 mlx5_opcode)
4990 {
4991         u8 opmod = 0;
4992
4993         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4994                                              mlx5_opcode | ((u32)opmod << 24));
4995         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4996         ctrl->fm_ce_se |= fence;
4997         if (unlikely(qp->flags_en & MLX5_QP_FLAG_SIGNATURE))
4998                 ctrl->signature = wq_sig(ctrl);
4999
5000         qp->sq.wrid[idx] = wr_id;
5001         qp->sq.w_list[idx].opcode = mlx5_opcode;
5002         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
5003         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
5004         qp->sq.w_list[idx].next = qp->sq.cur_post;
5005
5006         /* We save the edge which was possibly updated during the WQE
5007          * construction, into SQ's cache.
5008          */
5009         seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
5010         qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
5011                           get_sq_edge(&qp->sq, qp->sq.cur_post &
5012                                       (qp->sq.wqe_cnt - 1)) :
5013                           cur_edge;
5014 }
5015
5016 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5017                               const struct ib_send_wr **bad_wr, bool drain)
5018 {
5019         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
5020         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5021         struct mlx5_core_dev *mdev = dev->mdev;
5022         struct ib_reg_wr reg_pi_wr;
5023         struct mlx5_ib_qp *qp;
5024         struct mlx5_ib_mr *mr;
5025         struct mlx5_ib_mr *pi_mr;
5026         struct mlx5_ib_mr pa_pi_mr;
5027         struct ib_sig_attrs *sig_attrs;
5028         struct mlx5_wqe_xrc_seg *xrc;
5029         struct mlx5_bf *bf;
5030         void *cur_edge;
5031         int uninitialized_var(size);
5032         unsigned long flags;
5033         unsigned idx;
5034         int err = 0;
5035         int num_sge;
5036         void *seg;
5037         int nreq;
5038         int i;
5039         u8 next_fence = 0;
5040         u8 fence;
5041
5042         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5043                      !drain)) {
5044                 *bad_wr = wr;
5045                 return -EIO;
5046         }
5047
5048         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5049                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
5050
5051         qp = to_mqp(ibqp);
5052         bf = &qp->bf;
5053
5054         spin_lock_irqsave(&qp->sq.lock, flags);
5055
5056         for (nreq = 0; wr; nreq++, wr = wr->next) {
5057                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
5058                         mlx5_ib_warn(dev, "\n");
5059                         err = -EINVAL;
5060                         *bad_wr = wr;
5061                         goto out;
5062                 }
5063
5064                 num_sge = wr->num_sge;
5065                 if (unlikely(num_sge > qp->sq.max_gs)) {
5066                         mlx5_ib_warn(dev, "\n");
5067                         err = -EINVAL;
5068                         *bad_wr = wr;
5069                         goto out;
5070                 }
5071
5072                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
5073                                 nreq);
5074                 if (err) {
5075                         mlx5_ib_warn(dev, "\n");
5076                         err = -ENOMEM;
5077                         *bad_wr = wr;
5078                         goto out;
5079                 }
5080
5081                 if (wr->opcode == IB_WR_REG_MR ||
5082                     wr->opcode == IB_WR_REG_MR_INTEGRITY) {
5083                         fence = dev->umr_fence;
5084                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
5085                 } else  {
5086                         if (wr->send_flags & IB_SEND_FENCE) {
5087                                 if (qp->next_fence)
5088                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
5089                                 else
5090                                         fence = MLX5_FENCE_MODE_FENCE;
5091                         } else {
5092                                 fence = qp->next_fence;
5093                         }
5094                 }
5095
5096                 switch (ibqp->qp_type) {
5097                 case IB_QPT_XRC_INI:
5098                         xrc = seg;
5099                         seg += sizeof(*xrc);
5100                         size += sizeof(*xrc) / 16;
5101                         /* fall through */
5102                 case IB_QPT_RC:
5103                         switch (wr->opcode) {
5104                         case IB_WR_RDMA_READ:
5105                         case IB_WR_RDMA_WRITE:
5106                         case IB_WR_RDMA_WRITE_WITH_IMM:
5107                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5108                                               rdma_wr(wr)->rkey);
5109                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
5110                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5111                                 break;
5112
5113                         case IB_WR_ATOMIC_CMP_AND_SWP:
5114                         case IB_WR_ATOMIC_FETCH_AND_ADD:
5115                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
5116                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
5117                                 err = -ENOSYS;
5118                                 *bad_wr = wr;
5119                                 goto out;
5120
5121                         case IB_WR_LOCAL_INV:
5122                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
5123                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
5124                                 set_linv_wr(qp, &seg, &size, &cur_edge);
5125                                 num_sge = 0;
5126                                 break;
5127
5128                         case IB_WR_REG_MR:
5129                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
5130                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
5131                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
5132                                                  &cur_edge, true);
5133                                 if (err) {
5134                                         *bad_wr = wr;
5135                                         goto out;
5136                                 }
5137                                 num_sge = 0;
5138                                 break;
5139
5140                         case IB_WR_REG_MR_INTEGRITY:
5141                                 qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY;
5142
5143                                 mr = to_mmr(reg_wr(wr)->mr);
5144                                 pi_mr = mr->pi_mr;
5145
5146                                 if (pi_mr) {
5147                                         memset(&reg_pi_wr, 0,
5148                                                sizeof(struct ib_reg_wr));
5149
5150                                         reg_pi_wr.mr = &pi_mr->ibmr;
5151                                         reg_pi_wr.access = reg_wr(wr)->access;
5152                                         reg_pi_wr.key = pi_mr->ibmr.rkey;
5153
5154                                         ctrl->imm = cpu_to_be32(reg_pi_wr.key);
5155                                         /* UMR for data + prot registration */
5156                                         err = set_reg_wr(qp, &reg_pi_wr, &seg,
5157                                                          &size, &cur_edge,
5158                                                          false);
5159                                         if (err) {
5160                                                 *bad_wr = wr;
5161                                                 goto out;
5162                                         }
5163                                         finish_wqe(qp, ctrl, seg, size,
5164                                                    cur_edge, idx, wr->wr_id,
5165                                                    nreq, fence,
5166                                                    MLX5_OPCODE_UMR);
5167
5168                                         err = begin_wqe(qp, &seg, &ctrl, wr,
5169                                                         &idx, &size, &cur_edge,
5170                                                         nreq);
5171                                         if (err) {
5172                                                 mlx5_ib_warn(dev, "\n");
5173                                                 err = -ENOMEM;
5174                                                 *bad_wr = wr;
5175                                                 goto out;
5176                                         }
5177                                 } else {
5178                                         memset(&pa_pi_mr, 0,
5179                                                sizeof(struct mlx5_ib_mr));
5180                                         /* No UMR, use local_dma_lkey */
5181                                         pa_pi_mr.ibmr.lkey =
5182                                                 mr->ibmr.pd->local_dma_lkey;
5183
5184                                         pa_pi_mr.ndescs = mr->ndescs;
5185                                         pa_pi_mr.data_length = mr->data_length;
5186                                         pa_pi_mr.data_iova = mr->data_iova;
5187                                         if (mr->meta_ndescs) {
5188                                                 pa_pi_mr.meta_ndescs =
5189                                                         mr->meta_ndescs;
5190                                                 pa_pi_mr.meta_length =
5191                                                         mr->meta_length;
5192                                                 pa_pi_mr.pi_iova = mr->pi_iova;
5193                                         }
5194
5195                                         pa_pi_mr.ibmr.length = mr->ibmr.length;
5196                                         mr->pi_mr = &pa_pi_mr;
5197                                 }
5198                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
5199                                 /* UMR for sig MR */
5200                                 err = set_pi_umr_wr(wr, qp, &seg, &size,
5201                                                     &cur_edge);
5202                                 if (err) {
5203                                         mlx5_ib_warn(dev, "\n");
5204                                         *bad_wr = wr;
5205                                         goto out;
5206                                 }
5207                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5208                                            wr->wr_id, nreq, fence,
5209                                            MLX5_OPCODE_UMR);
5210
5211                                 /*
5212                                  * SET_PSV WQEs are not signaled and solicited
5213                                  * on error
5214                                  */
5215                                 sig_attrs = mr->ibmr.sig_attrs;
5216                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5217                                                   &size, &cur_edge, nreq, false,
5218                                                   true);
5219                                 if (err) {
5220                                         mlx5_ib_warn(dev, "\n");
5221                                         err = -ENOMEM;
5222                                         *bad_wr = wr;
5223                                         goto out;
5224                                 }
5225                                 err = set_psv_wr(&sig_attrs->mem,
5226                                                  mr->sig->psv_memory.psv_idx,
5227                                                  &seg, &size);
5228                                 if (err) {
5229                                         mlx5_ib_warn(dev, "\n");
5230                                         *bad_wr = wr;
5231                                         goto out;
5232                                 }
5233                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5234                                            wr->wr_id, nreq, next_fence,
5235                                            MLX5_OPCODE_SET_PSV);
5236
5237                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5238                                                   &size, &cur_edge, nreq, false,
5239                                                   true);
5240                                 if (err) {
5241                                         mlx5_ib_warn(dev, "\n");
5242                                         err = -ENOMEM;
5243                                         *bad_wr = wr;
5244                                         goto out;
5245                                 }
5246                                 err = set_psv_wr(&sig_attrs->wire,
5247                                                  mr->sig->psv_wire.psv_idx,
5248                                                  &seg, &size);
5249                                 if (err) {
5250                                         mlx5_ib_warn(dev, "\n");
5251                                         *bad_wr = wr;
5252                                         goto out;
5253                                 }
5254                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5255                                            wr->wr_id, nreq, next_fence,
5256                                            MLX5_OPCODE_SET_PSV);
5257
5258                                 qp->next_fence =
5259                                         MLX5_FENCE_MODE_INITIATOR_SMALL;
5260                                 num_sge = 0;
5261                                 goto skip_psv;
5262
5263                         default:
5264                                 break;
5265                         }
5266                         break;
5267
5268                 case IB_QPT_UC:
5269                         switch (wr->opcode) {
5270                         case IB_WR_RDMA_WRITE:
5271                         case IB_WR_RDMA_WRITE_WITH_IMM:
5272                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5273                                               rdma_wr(wr)->rkey);
5274                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
5275                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5276                                 break;
5277
5278                         default:
5279                                 break;
5280                         }
5281                         break;
5282
5283                 case IB_QPT_SMI:
5284                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5285                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5286                                 err = -EPERM;
5287                                 *bad_wr = wr;
5288                                 goto out;
5289                         }
5290                         /* fall through */
5291                 case MLX5_IB_QPT_HW_GSI:
5292                         set_datagram_seg(seg, wr);
5293                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5294                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5295                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5296
5297                         break;
5298                 case IB_QPT_UD:
5299                         set_datagram_seg(seg, wr);
5300                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5301                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5302                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5303
5304                         /* handle qp that supports ud offload */
5305                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5306                                 struct mlx5_wqe_eth_pad *pad;
5307
5308                                 pad = seg;
5309                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5310                                 seg += sizeof(struct mlx5_wqe_eth_pad);
5311                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
5312                                 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5313                                 handle_post_send_edge(&qp->sq, &seg, size,
5314                                                       &cur_edge);
5315                         }
5316                         break;
5317                 case MLX5_IB_QPT_REG_UMR:
5318                         if (wr->opcode != MLX5_IB_WR_UMR) {
5319                                 err = -EINVAL;
5320                                 mlx5_ib_warn(dev, "bad opcode\n");
5321                                 goto out;
5322                         }
5323                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
5324                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
5325                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5326                         if (unlikely(err))
5327                                 goto out;
5328                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5329                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5330                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5331                         set_reg_mkey_segment(seg, wr);
5332                         seg += sizeof(struct mlx5_mkey_seg);
5333                         size += sizeof(struct mlx5_mkey_seg) / 16;
5334                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5335                         break;
5336
5337                 default:
5338                         break;
5339                 }
5340
5341                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
5342                         err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
5343                         if (unlikely(err)) {
5344                                 mlx5_ib_warn(dev, "\n");
5345                                 *bad_wr = wr;
5346                                 goto out;
5347                         }
5348                 } else {
5349                         for (i = 0; i < num_sge; i++) {
5350                                 handle_post_send_edge(&qp->sq, &seg, size,
5351                                                       &cur_edge);
5352                                 if (likely(wr->sg_list[i].length)) {
5353                                         set_data_ptr_seg
5354                                         ((struct mlx5_wqe_data_seg *)seg,
5355                                          wr->sg_list + i);
5356                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
5357                                         seg += sizeof(struct mlx5_wqe_data_seg);
5358                                 }
5359                         }
5360                 }
5361
5362                 qp->next_fence = next_fence;
5363                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5364                            fence, mlx5_ib_opcode[wr->opcode]);
5365 skip_psv:
5366                 if (0)
5367                         dump_wqe(qp, idx, size);
5368         }
5369
5370 out:
5371         if (likely(nreq)) {
5372                 qp->sq.head += nreq;
5373
5374                 /* Make sure that descriptors are written before
5375                  * updating doorbell record and ringing the doorbell
5376                  */
5377                 wmb();
5378
5379                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5380
5381                 /* Make sure doorbell record is visible to the HCA before
5382                  * we hit doorbell */
5383                 wmb();
5384
5385                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
5386                 /* Make sure doorbells don't leak out of SQ spinlock
5387                  * and reach the HCA out of order.
5388                  */
5389                 bf->offset ^= bf->buf_size;
5390         }
5391
5392         spin_unlock_irqrestore(&qp->sq.lock, flags);
5393
5394         return err;
5395 }
5396
5397 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5398                       const struct ib_send_wr **bad_wr)
5399 {
5400         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5401 }
5402
5403 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5404 {
5405         sig->signature = calc_sig(sig, size);
5406 }
5407
5408 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5409                       const struct ib_recv_wr **bad_wr, bool drain)
5410 {
5411         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5412         struct mlx5_wqe_data_seg *scat;
5413         struct mlx5_rwqe_sig *sig;
5414         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5415         struct mlx5_core_dev *mdev = dev->mdev;
5416         unsigned long flags;
5417         int err = 0;
5418         int nreq;
5419         int ind;
5420         int i;
5421
5422         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5423                      !drain)) {
5424                 *bad_wr = wr;
5425                 return -EIO;
5426         }
5427
5428         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5429                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5430
5431         spin_lock_irqsave(&qp->rq.lock, flags);
5432
5433         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5434
5435         for (nreq = 0; wr; nreq++, wr = wr->next) {
5436                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5437                         err = -ENOMEM;
5438                         *bad_wr = wr;
5439                         goto out;
5440                 }
5441
5442                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5443                         err = -EINVAL;
5444                         *bad_wr = wr;
5445                         goto out;
5446                 }
5447
5448                 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5449                 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
5450                         scat++;
5451
5452                 for (i = 0; i < wr->num_sge; i++)
5453                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5454
5455                 if (i < qp->rq.max_gs) {
5456                         scat[i].byte_count = 0;
5457                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5458                         scat[i].addr       = 0;
5459                 }
5460
5461                 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) {
5462                         sig = (struct mlx5_rwqe_sig *)scat;
5463                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5464                 }
5465
5466                 qp->rq.wrid[ind] = wr->wr_id;
5467
5468                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5469         }
5470
5471 out:
5472         if (likely(nreq)) {
5473                 qp->rq.head += nreq;
5474
5475                 /* Make sure that descriptors are written before
5476                  * doorbell record.
5477                  */
5478                 wmb();
5479
5480                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5481         }
5482
5483         spin_unlock_irqrestore(&qp->rq.lock, flags);
5484
5485         return err;
5486 }
5487
5488 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5489                       const struct ib_recv_wr **bad_wr)
5490 {
5491         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5492 }
5493
5494 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5495 {
5496         switch (mlx5_state) {
5497         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5498         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5499         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5500         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5501         case MLX5_QP_STATE_SQ_DRAINING:
5502         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5503         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5504         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5505         default:                     return -1;
5506         }
5507 }
5508
5509 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5510 {
5511         switch (mlx5_mig_state) {
5512         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5513         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5514         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5515         default: return -1;
5516         }
5517 }
5518
5519 static int to_ib_qp_access_flags(int mlx5_flags)
5520 {
5521         int ib_flags = 0;
5522
5523         if (mlx5_flags & MLX5_QP_BIT_RRE)
5524                 ib_flags |= IB_ACCESS_REMOTE_READ;
5525         if (mlx5_flags & MLX5_QP_BIT_RWE)
5526                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5527         if (mlx5_flags & MLX5_QP_BIT_RAE)
5528                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5529
5530         return ib_flags;
5531 }
5532
5533 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5534                             struct rdma_ah_attr *ah_attr,
5535                             struct mlx5_qp_path *path)
5536 {
5537
5538         memset(ah_attr, 0, sizeof(*ah_attr));
5539
5540         if (!path->port || path->port > ibdev->num_ports)
5541                 return;
5542
5543         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5544
5545         rdma_ah_set_port_num(ah_attr, path->port);
5546         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5547
5548         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5549         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5550         rdma_ah_set_static_rate(ah_attr,
5551                                 path->static_rate ? path->static_rate - 5 : 0);
5552         if (path->grh_mlid & (1 << 7)) {
5553                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5554
5555                 rdma_ah_set_grh(ah_attr, NULL,
5556                                 tc_fl & 0xfffff,
5557                                 path->mgid_index,
5558                                 path->hop_limit,
5559                                 (tc_fl >> 20) & 0xff);
5560                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5561         }
5562 }
5563
5564 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5565                                         struct mlx5_ib_sq *sq,
5566                                         u8 *sq_state)
5567 {
5568         int err;
5569
5570         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5571         if (err)
5572                 goto out;
5573         sq->state = *sq_state;
5574
5575 out:
5576         return err;
5577 }
5578
5579 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5580                                         struct mlx5_ib_rq *rq,
5581                                         u8 *rq_state)
5582 {
5583         void *out;
5584         void *rqc;
5585         int inlen;
5586         int err;
5587
5588         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5589         out = kvzalloc(inlen, GFP_KERNEL);
5590         if (!out)
5591                 return -ENOMEM;
5592
5593         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5594         if (err)
5595                 goto out;
5596
5597         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5598         *rq_state = MLX5_GET(rqc, rqc, state);
5599         rq->state = *rq_state;
5600
5601 out:
5602         kvfree(out);
5603         return err;
5604 }
5605
5606 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5607                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5608 {
5609         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5610                 [MLX5_RQC_STATE_RST] = {
5611                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5612                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5613                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5614                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5615                 },
5616                 [MLX5_RQC_STATE_RDY] = {
5617                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5618                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5619                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5620                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5621                 },
5622                 [MLX5_RQC_STATE_ERR] = {
5623                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5624                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5625                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5626                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5627                 },
5628                 [MLX5_RQ_STATE_NA] = {
5629                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5630                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5631                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5632                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5633                 },
5634         };
5635
5636         *qp_state = sqrq_trans[rq_state][sq_state];
5637
5638         if (*qp_state == MLX5_QP_STATE_BAD) {
5639                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5640                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5641                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5642                 return -EINVAL;
5643         }
5644
5645         if (*qp_state == MLX5_QP_STATE)
5646                 *qp_state = qp->state;
5647
5648         return 0;
5649 }
5650
5651 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5652                                      struct mlx5_ib_qp *qp,
5653                                      u8 *raw_packet_qp_state)
5654 {
5655         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5656         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5657         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5658         int err;
5659         u8 sq_state = MLX5_SQ_STATE_NA;
5660         u8 rq_state = MLX5_RQ_STATE_NA;
5661
5662         if (qp->sq.wqe_cnt) {
5663                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5664                 if (err)
5665                         return err;
5666         }
5667
5668         if (qp->rq.wqe_cnt) {
5669                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5670                 if (err)
5671                         return err;
5672         }
5673
5674         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5675                                       raw_packet_qp_state);
5676 }
5677
5678 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5679                          struct ib_qp_attr *qp_attr)
5680 {
5681         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5682         struct mlx5_qp_context *context;
5683         int mlx5_state;
5684         u32 *outb;
5685         int err = 0;
5686
5687         outb = kzalloc(outlen, GFP_KERNEL);
5688         if (!outb)
5689                 return -ENOMEM;
5690
5691         err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
5692         if (err)
5693                 goto out;
5694
5695         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5696         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5697
5698         mlx5_state = be32_to_cpu(context->flags) >> 28;
5699
5700         qp->state                    = to_ib_qp_state(mlx5_state);
5701         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5702         qp_attr->path_mig_state      =
5703                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5704         qp_attr->qkey                = be32_to_cpu(context->qkey);
5705         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5706         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5707         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5708         qp_attr->qp_access_flags     =
5709                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5710
5711         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5712                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5713                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5714                 qp_attr->alt_pkey_index =
5715                         be16_to_cpu(context->alt_path.pkey_index);
5716                 qp_attr->alt_port_num   =
5717                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5718         }
5719
5720         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5721         qp_attr->port_num = context->pri_path.port;
5722
5723         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5724         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5725
5726         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5727
5728         qp_attr->max_dest_rd_atomic =
5729                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5730         qp_attr->min_rnr_timer      =
5731                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5732         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5733         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5734         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5735         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5736
5737 out:
5738         kfree(outb);
5739         return err;
5740 }
5741
5742 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5743                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5744                                 struct ib_qp_init_attr *qp_init_attr)
5745 {
5746         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5747         u32 *out;
5748         u32 access_flags = 0;
5749         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5750         void *dctc;
5751         int err;
5752         int supported_mask = IB_QP_STATE |
5753                              IB_QP_ACCESS_FLAGS |
5754                              IB_QP_PORT |
5755                              IB_QP_MIN_RNR_TIMER |
5756                              IB_QP_AV |
5757                              IB_QP_PATH_MTU |
5758                              IB_QP_PKEY_INDEX;
5759
5760         if (qp_attr_mask & ~supported_mask)
5761                 return -EINVAL;
5762         if (mqp->state != IB_QPS_RTR)
5763                 return -EINVAL;
5764
5765         out = kzalloc(outlen, GFP_KERNEL);
5766         if (!out)
5767                 return -ENOMEM;
5768
5769         err = mlx5_core_dct_query(dev, dct, out, outlen);
5770         if (err)
5771                 goto out;
5772
5773         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5774
5775         if (qp_attr_mask & IB_QP_STATE)
5776                 qp_attr->qp_state = IB_QPS_RTR;
5777
5778         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5779                 if (MLX5_GET(dctc, dctc, rre))
5780                         access_flags |= IB_ACCESS_REMOTE_READ;
5781                 if (MLX5_GET(dctc, dctc, rwe))
5782                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5783                 if (MLX5_GET(dctc, dctc, rae))
5784                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5785                 qp_attr->qp_access_flags = access_flags;
5786         }
5787
5788         if (qp_attr_mask & IB_QP_PORT)
5789                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5790         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5791                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5792         if (qp_attr_mask & IB_QP_AV) {
5793                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5794                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5795                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5796                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5797         }
5798         if (qp_attr_mask & IB_QP_PATH_MTU)
5799                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5800         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5801                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5802 out:
5803         kfree(out);
5804         return err;
5805 }
5806
5807 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5808                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5809 {
5810         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5811         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5812         int err = 0;
5813         u8 raw_packet_qp_state;
5814
5815         if (ibqp->rwq_ind_tbl)
5816                 return -ENOSYS;
5817
5818         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5819                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5820                                             qp_init_attr);
5821
5822         /* Not all of output fields are applicable, make sure to zero them */
5823         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5824         memset(qp_attr, 0, sizeof(*qp_attr));
5825
5826         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5827                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5828                                             qp_attr_mask, qp_init_attr);
5829
5830         mutex_lock(&qp->mutex);
5831
5832         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5833             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
5834                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5835                 if (err)
5836                         goto out;
5837                 qp->state = raw_packet_qp_state;
5838                 qp_attr->port_num = 1;
5839         } else {
5840                 err = query_qp_attr(dev, qp, qp_attr);
5841                 if (err)
5842                         goto out;
5843         }
5844
5845         qp_attr->qp_state            = qp->state;
5846         qp_attr->cur_qp_state        = qp_attr->qp_state;
5847         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5848         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5849
5850         if (!ibqp->uobject) {
5851                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5852                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5853                 qp_init_attr->qp_context = ibqp->qp_context;
5854         } else {
5855                 qp_attr->cap.max_send_wr  = 0;
5856                 qp_attr->cap.max_send_sge = 0;
5857         }
5858
5859         qp_init_attr->qp_type = ibqp->qp_type;
5860         qp_init_attr->recv_cq = ibqp->recv_cq;
5861         qp_init_attr->send_cq = ibqp->send_cq;
5862         qp_init_attr->srq = ibqp->srq;
5863         qp_attr->cap.max_inline_data = qp->max_inline_data;
5864
5865         qp_init_attr->cap            = qp_attr->cap;
5866
5867         qp_init_attr->create_flags = qp->flags;
5868
5869         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5870                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5871
5872 out:
5873         mutex_unlock(&qp->mutex);
5874         return err;
5875 }
5876
5877 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5878                                    struct ib_udata *udata)
5879 {
5880         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5881         struct mlx5_ib_xrcd *xrcd;
5882         int err;
5883
5884         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5885                 return ERR_PTR(-ENOSYS);
5886
5887         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5888         if (!xrcd)
5889                 return ERR_PTR(-ENOMEM);
5890
5891         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5892         if (err) {
5893                 kfree(xrcd);
5894                 return ERR_PTR(-ENOMEM);
5895         }
5896
5897         return &xrcd->ibxrcd;
5898 }
5899
5900 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
5901 {
5902         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5903         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5904         int err;
5905
5906         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5907         if (err)
5908                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5909
5910         kfree(xrcd);
5911         return 0;
5912 }
5913
5914 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5915 {
5916         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5917         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5918         struct ib_event event;
5919
5920         if (rwq->ibwq.event_handler) {
5921                 event.device     = rwq->ibwq.device;
5922                 event.element.wq = &rwq->ibwq;
5923                 switch (type) {
5924                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5925                         event.event = IB_EVENT_WQ_FATAL;
5926                         break;
5927                 default:
5928                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5929                         return;
5930                 }
5931
5932                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5933         }
5934 }
5935
5936 static int set_delay_drop(struct mlx5_ib_dev *dev)
5937 {
5938         int err = 0;
5939
5940         mutex_lock(&dev->delay_drop.lock);
5941         if (dev->delay_drop.activate)
5942                 goto out;
5943
5944         err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
5945         if (err)
5946                 goto out;
5947
5948         dev->delay_drop.activate = true;
5949 out:
5950         mutex_unlock(&dev->delay_drop.lock);
5951
5952         if (!err)
5953                 atomic_inc(&dev->delay_drop.rqs_cnt);
5954         return err;
5955 }
5956
5957 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5958                       struct ib_wq_init_attr *init_attr)
5959 {
5960         struct mlx5_ib_dev *dev;
5961         int has_net_offloads;
5962         __be64 *rq_pas0;
5963         void *in;
5964         void *rqc;
5965         void *wq;
5966         int inlen;
5967         int err;
5968
5969         dev = to_mdev(pd->device);
5970
5971         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5972         in = kvzalloc(inlen, GFP_KERNEL);
5973         if (!in)
5974                 return -ENOMEM;
5975
5976         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5977         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5978         MLX5_SET(rqc,  rqc, mem_rq_type,
5979                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5980         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5981         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5982         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5983         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5984         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5985         MLX5_SET(wq, wq, wq_type,
5986                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5987                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5988         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5989                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5990                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5991                         err = -EOPNOTSUPP;
5992                         goto out;
5993                 } else {
5994                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5995                 }
5996         }
5997         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5998         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5999                 /*
6000                  * In Firmware number of strides in each WQE is:
6001                  *   "512 * 2^single_wqe_log_num_of_strides"
6002                  * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
6003                  * accepted as 0 to 9
6004                  */
6005                 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
6006                                              2,  3,  4,  5,  6,  7,  8, 9 };
6007                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
6008                 MLX5_SET(wq, wq, log_wqe_stride_size,
6009                          rwq->single_stride_log_num_of_bytes -
6010                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
6011                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
6012                          fw_map[rwq->log_num_strides -
6013                                 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
6014         }
6015         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
6016         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
6017         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
6018         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
6019         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
6020         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
6021         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
6022         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6023                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6024                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
6025                         err = -EOPNOTSUPP;
6026                         goto out;
6027                 }
6028         } else {
6029                 MLX5_SET(rqc, rqc, vsd, 1);
6030         }
6031         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
6032                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
6033                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
6034                         err = -EOPNOTSUPP;
6035                         goto out;
6036                 }
6037                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
6038         }
6039         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6040                 if (!(dev->ib_dev.attrs.raw_packet_caps &
6041                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
6042                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
6043                         err = -EOPNOTSUPP;
6044                         goto out;
6045                 }
6046                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
6047         }
6048         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
6049         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
6050         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
6051         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6052                 err = set_delay_drop(dev);
6053                 if (err) {
6054                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
6055                                      err);
6056                         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6057                 } else {
6058                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
6059                 }
6060         }
6061 out:
6062         kvfree(in);
6063         return err;
6064 }
6065
6066 static int set_user_rq_size(struct mlx5_ib_dev *dev,
6067                             struct ib_wq_init_attr *wq_init_attr,
6068                             struct mlx5_ib_create_wq *ucmd,
6069                             struct mlx5_ib_rwq *rwq)
6070 {
6071         /* Sanity check RQ size before proceeding */
6072         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
6073                 return -EINVAL;
6074
6075         if (!ucmd->rq_wqe_count)
6076                 return -EINVAL;
6077
6078         rwq->wqe_count = ucmd->rq_wqe_count;
6079         rwq->wqe_shift = ucmd->rq_wqe_shift;
6080         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
6081                 return -EINVAL;
6082
6083         rwq->log_rq_stride = rwq->wqe_shift;
6084         rwq->log_rq_size = ilog2(rwq->wqe_count);
6085         return 0;
6086 }
6087
6088 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
6089 {
6090         if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
6091             (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
6092                 return false;
6093
6094         if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
6095             (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
6096                 return false;
6097
6098         return true;
6099 }
6100
6101 static int prepare_user_rq(struct ib_pd *pd,
6102                            struct ib_wq_init_attr *init_attr,
6103                            struct ib_udata *udata,
6104                            struct mlx5_ib_rwq *rwq)
6105 {
6106         struct mlx5_ib_dev *dev = to_mdev(pd->device);
6107         struct mlx5_ib_create_wq ucmd = {};
6108         int err;
6109         size_t required_cmd_sz;
6110
6111         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
6112                 + sizeof(ucmd.single_stride_log_num_of_bytes);
6113         if (udata->inlen < required_cmd_sz) {
6114                 mlx5_ib_dbg(dev, "invalid inlen\n");
6115                 return -EINVAL;
6116         }
6117
6118         if (udata->inlen > sizeof(ucmd) &&
6119             !ib_is_udata_cleared(udata, sizeof(ucmd),
6120                                  udata->inlen - sizeof(ucmd))) {
6121                 mlx5_ib_dbg(dev, "inlen is not supported\n");
6122                 return -EOPNOTSUPP;
6123         }
6124
6125         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
6126                 mlx5_ib_dbg(dev, "copy failed\n");
6127                 return -EFAULT;
6128         }
6129
6130         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
6131                 mlx5_ib_dbg(dev, "invalid comp mask\n");
6132                 return -EOPNOTSUPP;
6133         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
6134                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
6135                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
6136                         return -EOPNOTSUPP;
6137                 }
6138                 if ((ucmd.single_stride_log_num_of_bytes <
6139                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
6140                     (ucmd.single_stride_log_num_of_bytes >
6141                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
6142                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
6143                                     ucmd.single_stride_log_num_of_bytes,
6144                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
6145                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
6146                         return -EINVAL;
6147                 }
6148                 if (!log_of_strides_valid(dev,
6149                                           ucmd.single_wqe_log_num_of_strides)) {
6150                         mlx5_ib_dbg(
6151                                 dev,
6152                                 "Invalid log num strides (%u. Range is %u - %u)\n",
6153                                 ucmd.single_wqe_log_num_of_strides,
6154                                 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
6155                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
6156                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
6157                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
6158                         return -EINVAL;
6159                 }
6160                 rwq->single_stride_log_num_of_bytes =
6161                         ucmd.single_stride_log_num_of_bytes;
6162                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
6163                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
6164                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
6165         }
6166
6167         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
6168         if (err) {
6169                 mlx5_ib_dbg(dev, "err %d\n", err);
6170                 return err;
6171         }
6172
6173         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
6174         if (err) {
6175                 mlx5_ib_dbg(dev, "err %d\n", err);
6176                 return err;
6177         }
6178
6179         rwq->user_index = ucmd.user_index;
6180         return 0;
6181 }
6182
6183 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
6184                                 struct ib_wq_init_attr *init_attr,
6185                                 struct ib_udata *udata)
6186 {
6187         struct mlx5_ib_dev *dev;
6188         struct mlx5_ib_rwq *rwq;
6189         struct mlx5_ib_create_wq_resp resp = {};
6190         size_t min_resp_len;
6191         int err;
6192
6193         if (!udata)
6194                 return ERR_PTR(-ENOSYS);
6195
6196         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6197         if (udata->outlen && udata->outlen < min_resp_len)
6198                 return ERR_PTR(-EINVAL);
6199
6200         if (!capable(CAP_SYS_RAWIO) &&
6201             init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
6202                 return ERR_PTR(-EPERM);
6203
6204         dev = to_mdev(pd->device);
6205         switch (init_attr->wq_type) {
6206         case IB_WQT_RQ:
6207                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
6208                 if (!rwq)
6209                         return ERR_PTR(-ENOMEM);
6210                 err = prepare_user_rq(pd, init_attr, udata, rwq);
6211                 if (err)
6212                         goto err;
6213                 err = create_rq(rwq, pd, init_attr);
6214                 if (err)
6215                         goto err_user_rq;
6216                 break;
6217         default:
6218                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
6219                             init_attr->wq_type);
6220                 return ERR_PTR(-EINVAL);
6221         }
6222
6223         rwq->ibwq.wq_num = rwq->core_qp.qpn;
6224         rwq->ibwq.state = IB_WQS_RESET;
6225         if (udata->outlen) {
6226                 resp.response_length = offsetof(typeof(resp), response_length) +
6227                                 sizeof(resp.response_length);
6228                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6229                 if (err)
6230                         goto err_copy;
6231         }
6232
6233         rwq->core_qp.event = mlx5_ib_wq_event;
6234         rwq->ibwq.event_handler = init_attr->event_handler;
6235         return &rwq->ibwq;
6236
6237 err_copy:
6238         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6239 err_user_rq:
6240         destroy_user_rq(dev, pd, rwq, udata);
6241 err:
6242         kfree(rwq);
6243         return ERR_PTR(err);
6244 }
6245
6246 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
6247 {
6248         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6249         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6250
6251         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6252         destroy_user_rq(dev, wq->pd, rwq, udata);
6253         kfree(rwq);
6254 }
6255
6256 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
6257                                                       struct ib_rwq_ind_table_init_attr *init_attr,
6258                                                       struct ib_udata *udata)
6259 {
6260         struct mlx5_ib_dev *dev = to_mdev(device);
6261         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
6262         int sz = 1 << init_attr->log_ind_tbl_size;
6263         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
6264         size_t min_resp_len;
6265         int inlen;
6266         int err;
6267         int i;
6268         u32 *in;
6269         void *rqtc;
6270
6271         if (udata->inlen > 0 &&
6272             !ib_is_udata_cleared(udata, 0,
6273                                  udata->inlen))
6274                 return ERR_PTR(-EOPNOTSUPP);
6275
6276         if (init_attr->log_ind_tbl_size >
6277             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
6278                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
6279                             init_attr->log_ind_tbl_size,
6280                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
6281                 return ERR_PTR(-EINVAL);
6282         }
6283
6284         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6285         if (udata->outlen && udata->outlen < min_resp_len)
6286                 return ERR_PTR(-EINVAL);
6287
6288         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6289         if (!rwq_ind_tbl)
6290                 return ERR_PTR(-ENOMEM);
6291
6292         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
6293         in = kvzalloc(inlen, GFP_KERNEL);
6294         if (!in) {
6295                 err = -ENOMEM;
6296                 goto err;
6297         }
6298
6299         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6300
6301         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6302         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6303
6304         for (i = 0; i < sz; i++)
6305                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6306
6307         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6308         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6309
6310         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6311         kvfree(in);
6312
6313         if (err)
6314                 goto err;
6315
6316         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6317         if (udata->outlen) {
6318                 resp.response_length = offsetof(typeof(resp), response_length) +
6319                                         sizeof(resp.response_length);
6320                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6321                 if (err)
6322                         goto err_copy;
6323         }
6324
6325         return &rwq_ind_tbl->ib_rwq_ind_tbl;
6326
6327 err_copy:
6328         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6329 err:
6330         kfree(rwq_ind_tbl);
6331         return ERR_PTR(err);
6332 }
6333
6334 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6335 {
6336         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6337         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6338
6339         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6340
6341         kfree(rwq_ind_tbl);
6342         return 0;
6343 }
6344
6345 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6346                       u32 wq_attr_mask, struct ib_udata *udata)
6347 {
6348         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6349         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6350         struct mlx5_ib_modify_wq ucmd = {};
6351         size_t required_cmd_sz;
6352         int curr_wq_state;
6353         int wq_state;
6354         int inlen;
6355         int err;
6356         void *rqc;
6357         void *in;
6358
6359         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6360         if (udata->inlen < required_cmd_sz)
6361                 return -EINVAL;
6362
6363         if (udata->inlen > sizeof(ucmd) &&
6364             !ib_is_udata_cleared(udata, sizeof(ucmd),
6365                                  udata->inlen - sizeof(ucmd)))
6366                 return -EOPNOTSUPP;
6367
6368         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6369                 return -EFAULT;
6370
6371         if (ucmd.comp_mask || ucmd.reserved)
6372                 return -EOPNOTSUPP;
6373
6374         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
6375         in = kvzalloc(inlen, GFP_KERNEL);
6376         if (!in)
6377                 return -ENOMEM;
6378
6379         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6380
6381         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6382                 wq_attr->curr_wq_state : wq->state;
6383         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6384                 wq_attr->wq_state : curr_wq_state;
6385         if (curr_wq_state == IB_WQS_ERR)
6386                 curr_wq_state = MLX5_RQC_STATE_ERR;
6387         if (wq_state == IB_WQS_ERR)
6388                 wq_state = MLX5_RQC_STATE_ERR;
6389         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6390         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6391         MLX5_SET(rqc, rqc, state, wq_state);
6392
6393         if (wq_attr_mask & IB_WQ_FLAGS) {
6394                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6395                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6396                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6397                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
6398                                             "supported\n");
6399                                 err = -EOPNOTSUPP;
6400                                 goto out;
6401                         }
6402                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6403                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6404                         MLX5_SET(rqc, rqc, vsd,
6405                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6406                 }
6407
6408                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6409                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6410                         err = -EOPNOTSUPP;
6411                         goto out;
6412                 }
6413         }
6414
6415         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6416                 u16 set_id;
6417
6418                 set_id = mlx5_ib_get_counters_id(dev, 0);
6419                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6420                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6421                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6422                         MLX5_SET(rqc, rqc, counter_set_id, set_id);
6423                 } else
6424                         dev_info_once(
6425                                 &dev->ib_dev.dev,
6426                                 "Receive WQ counters are not supported on current FW\n");
6427         }
6428
6429         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
6430         if (!err)
6431                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6432
6433 out:
6434         kvfree(in);
6435         return err;
6436 }
6437
6438 struct mlx5_ib_drain_cqe {
6439         struct ib_cqe cqe;
6440         struct completion done;
6441 };
6442
6443 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6444 {
6445         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6446                                                      struct mlx5_ib_drain_cqe,
6447                                                      cqe);
6448
6449         complete(&cqe->done);
6450 }
6451
6452 /* This function returns only once the drained WR was completed */
6453 static void handle_drain_completion(struct ib_cq *cq,
6454                                     struct mlx5_ib_drain_cqe *sdrain,
6455                                     struct mlx5_ib_dev *dev)
6456 {
6457         struct mlx5_core_dev *mdev = dev->mdev;
6458
6459         if (cq->poll_ctx == IB_POLL_DIRECT) {
6460                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6461                         ib_process_cq_direct(cq, -1);
6462                 return;
6463         }
6464
6465         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6466                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6467                 bool triggered = false;
6468                 unsigned long flags;
6469
6470                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6471                 /* Make sure that the CQ handler won't run if wasn't run yet */
6472                 if (!mcq->mcq.reset_notify_added)
6473                         mcq->mcq.reset_notify_added = 1;
6474                 else
6475                         triggered = true;
6476                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6477
6478                 if (triggered) {
6479                         /* Wait for any scheduled/running task to be ended */
6480                         switch (cq->poll_ctx) {
6481                         case IB_POLL_SOFTIRQ:
6482                                 irq_poll_disable(&cq->iop);
6483                                 irq_poll_enable(&cq->iop);
6484                                 break;
6485                         case IB_POLL_WORKQUEUE:
6486                                 cancel_work_sync(&cq->work);
6487                                 break;
6488                         default:
6489                                 WARN_ON_ONCE(1);
6490                         }
6491                 }
6492
6493                 /* Run the CQ handler - this makes sure that the drain WR will
6494                  * be processed if wasn't processed yet.
6495                  */
6496                 mcq->mcq.comp(&mcq->mcq, NULL);
6497         }
6498
6499         wait_for_completion(&sdrain->done);
6500 }
6501
6502 void mlx5_ib_drain_sq(struct ib_qp *qp)
6503 {
6504         struct ib_cq *cq = qp->send_cq;
6505         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6506         struct mlx5_ib_drain_cqe sdrain;
6507         const struct ib_send_wr *bad_swr;
6508         struct ib_rdma_wr swr = {
6509                 .wr = {
6510                         .next = NULL,
6511                         { .wr_cqe       = &sdrain.cqe, },
6512                         .opcode = IB_WR_RDMA_WRITE,
6513                 },
6514         };
6515         int ret;
6516         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6517         struct mlx5_core_dev *mdev = dev->mdev;
6518
6519         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6520         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6521                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6522                 return;
6523         }
6524
6525         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6526         init_completion(&sdrain.done);
6527
6528         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6529         if (ret) {
6530                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6531                 return;
6532         }
6533
6534         handle_drain_completion(cq, &sdrain, dev);
6535 }
6536
6537 void mlx5_ib_drain_rq(struct ib_qp *qp)
6538 {
6539         struct ib_cq *cq = qp->recv_cq;
6540         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6541         struct mlx5_ib_drain_cqe rdrain;
6542         struct ib_recv_wr rwr = {};
6543         const struct ib_recv_wr *bad_rwr;
6544         int ret;
6545         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6546         struct mlx5_core_dev *mdev = dev->mdev;
6547
6548         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6549         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6550                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6551                 return;
6552         }
6553
6554         rwr.wr_cqe = &rdrain.cqe;
6555         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6556         init_completion(&rdrain.done);
6557
6558         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6559         if (ret) {
6560                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6561                 return;
6562         }
6563
6564         handle_drain_completion(cq, &rdrain, dev);
6565 }
6566
6567 /**
6568  * Bind a qp to a counter. If @counter is NULL then bind the qp to
6569  * the default counter
6570  */
6571 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
6572 {
6573         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6574         struct mlx5_ib_qp *mqp = to_mqp(qp);
6575         int err = 0;
6576
6577         mutex_lock(&mqp->mutex);
6578         if (mqp->state == IB_QPS_RESET) {
6579                 qp->counter = counter;
6580                 goto out;
6581         }
6582
6583         if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
6584                 err = -EOPNOTSUPP;
6585                 goto out;
6586         }
6587
6588         if (mqp->state == IB_QPS_RTS) {
6589                 err = __mlx5_ib_qp_set_counter(qp, counter);
6590                 if (!err)
6591                         qp->counter = counter;
6592
6593                 goto out;
6594         }
6595
6596         mqp->counter_pending = 1;
6597         qp->counter = counter;
6598
6599 out:
6600         mutex_unlock(&mqp->mutex);
6601         return err;
6602 }