drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <rdma/rdma_counter.h>
  38 #include <linux/mlx5/fs.h>
  39 #include "mlx5_ib.h"
  40 #include "ib_rep.h"
  41 #include "cmd.h"
  42 #include "qp.h"
  43
  44 /* not supported currently */
  45 static int wq_signature;
  46
  47 enum {
  48         MLX5_IB_ACK_REQ_FREQ    = 8,
  49 };
  50
  51 enum {
  52         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  53         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  54         MLX5_IB_LINK_TYPE_IB            = 0,
  55         MLX5_IB_LINK_TYPE_ETH           = 1
  56 };
  57
  58 enum {
  59         MLX5_IB_SQ_STRIDE       = 6,
  60         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  61 };
  62
  63 static const u32 mlx5_ib_opcode[] = {
  64         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  65         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  66         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  67         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  68         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  69         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  70         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  71         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  72         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  73         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  74         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  75         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  76         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  77         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  78 };
  79
  80 struct mlx5_wqe_eth_pad {
  81         u8 rsvd0[16];
  82 };
  83
  84 enum raw_qp_set_mask_map {
  85         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  86         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  87 };
  88
  89 struct mlx5_modify_raw_qp_param {
  90         u16 operation;
  91
  92         u32 set_mask; /* raw_qp_set_mask_map */
  93
  94         struct mlx5_rate_limit rl;
  95
  96         u8 rq_q_ctr_id;
  97         u16 port;
  98 };
  99
 100 static void get_cqs(enum ib_qp_type qp_type,
 101                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
 102                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 103
 104 static int is_qp0(enum ib_qp_type qp_type)
 105 {
 106         return qp_type == IB_QPT_SMI;
 107 }
 108
 109 static int is_sqp(enum ib_qp_type qp_type)
 110 {
 111         return is_qp0(qp_type) || is_qp1(qp_type);
 112 }
 113
 114 /**
 115  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
 116  * to kernel buffer
 117  *
 118  * @umem: User space memory where the WQ is
 119  * @buffer: buffer to copy to
 120  * @buflen: buffer length
 121  * @wqe_index: index of WQE to copy from
 122  * @wq_offset: offset to start of WQ
 123  * @wq_wqe_cnt: number of WQEs in WQ
 124  * @wq_wqe_shift: log2 of WQE size
 125  * @bcnt: number of bytes to copy
 126  * @bytes_copied: number of bytes to copy (return value)
 127  *
 128  * Copies from start of WQE bcnt or less bytes.
 129  * Does not gurantee to copy the entire WQE.
 130  *
 131  * Return: zero on success, or an error code.
 132  */
 133 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
 134                                         size_t buflen, int wqe_index,
 135                                         int wq_offset, int wq_wqe_cnt,
 136                                         int wq_wqe_shift, int bcnt,
 137                                         size_t *bytes_copied)
 138 {
 139         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 140         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 141         size_t copy_length;
 142         int ret;
 143
 144         /* don't copy more than requested, more than buffer length or
 145          * beyond WQ end
 146          */
 147         copy_length = min_t(u32, buflen, wq_end - offset);
 148         copy_length = min_t(u32, copy_length, bcnt);
 149
 150         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 151         if (ret)
 152                 return ret;
 153
 154         if (!ret && bytes_copied)
 155                 *bytes_copied = copy_length;
 156
 157         return 0;
 158 }
 159
 160 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 161                                       void *buffer, size_t buflen, size_t *bc)
 162 {
 163         struct mlx5_wqe_ctrl_seg *ctrl;
 164         size_t bytes_copied = 0;
 165         size_t wqe_length;
 166         void *p;
 167         int ds;
 168
 169         wqe_index = wqe_index & qp->sq.fbc.sz_m1;
 170
 171         /* read the control segment first */
 172         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 173         ctrl = p;
 174         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 175         wqe_length = ds * MLX5_WQE_DS_UNITS;
 176
 177         /* read rest of WQE if it spreads over more than one stride */
 178         while (bytes_copied < wqe_length) {
 179                 size_t copy_length =
 180                         min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
 181
 182                 if (!copy_length)
 183                         break;
 184
 185                 memcpy(buffer + bytes_copied, p, copy_length);
 186                 bytes_copied += copy_length;
 187
 188                 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
 189                 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 190         }
 191         *bc = bytes_copied;
 192         return 0;
 193 }
 194
 195 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 196                                     void *buffer, size_t buflen, size_t *bc)
 197 {
 198         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 199         struct ib_umem *umem = base->ubuffer.umem;
 200         struct mlx5_ib_wq *wq = &qp->sq;
 201         struct mlx5_wqe_ctrl_seg *ctrl;
 202         size_t bytes_copied;
 203         size_t bytes_copied2;
 204         size_t wqe_length;
 205         int ret;
 206         int ds;
 207
 208         /* at first read as much as possible */
 209         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 210                                            wq->offset, wq->wqe_cnt,
 211                                            wq->wqe_shift, buflen,
 212                                            &bytes_copied);
 213         if (ret)
 214                 return ret;
 215
 216         /* we need at least control segment size to proceed */
 217         if (bytes_copied < sizeof(*ctrl))
 218                 return -EINVAL;
 219
 220         ctrl = buffer;
 221         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 222         wqe_length = ds * MLX5_WQE_DS_UNITS;
 223
 224         /* if we copied enough then we are done */
 225         if (bytes_copied >= wqe_length) {
 226                 *bc = bytes_copied;
 227                 return 0;
 228         }
 229
 230         /* otherwise this a wrapped around wqe
 231          * so read the remaining bytes starting
 232          * from  wqe_index 0
 233          */
 234         ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
 235                                            buflen - bytes_copied, 0, wq->offset,
 236                                            wq->wqe_cnt, wq->wqe_shift,
 237                                            wqe_length - bytes_copied,
 238                                            &bytes_copied2);
 239
 240         if (ret)
 241                 return ret;
 242         *bc = bytes_copied + bytes_copied2;
 243         return 0;
 244 }
 245
 246 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 247                         size_t buflen, size_t *bc)
 248 {
 249         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 250         struct ib_umem *umem = base->ubuffer.umem;
 251
 252         if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
 253                 return -EINVAL;
 254
 255         if (!umem)
 256                 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
 257                                                   buflen, bc);
 258
 259         return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
 260 }
 261
 262 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
 263                                     void *buffer, size_t buflen, size_t *bc)
 264 {
 265         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 266         struct ib_umem *umem = base->ubuffer.umem;
 267         struct mlx5_ib_wq *wq = &qp->rq;
 268         size_t bytes_copied;
 269         int ret;
 270
 271         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 272                                            wq->offset, wq->wqe_cnt,
 273                                            wq->wqe_shift, buflen,
 274                                            &bytes_copied);
 275
 276         if (ret)
 277                 return ret;
 278         *bc = bytes_copied;
 279         return 0;
 280 }
 281
 282 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 283                         size_t buflen, size_t *bc)
 284 {
 285         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 286         struct ib_umem *umem = base->ubuffer.umem;
 287         struct mlx5_ib_wq *wq = &qp->rq;
 288         size_t wqe_size = 1 << wq->wqe_shift;
 289
 290         if (buflen < wqe_size)
 291                 return -EINVAL;
 292
 293         if (!umem)
 294                 return -EOPNOTSUPP;
 295
 296         return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
 297 }
 298
 299 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
 300                                      void *buffer, size_t buflen, size_t *bc)
 301 {
 302         struct ib_umem *umem = srq->umem;
 303         size_t bytes_copied;
 304         int ret;
 305
 306         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
 307                                            srq->msrq.max, srq->msrq.wqe_shift,
 308                                            buflen, &bytes_copied);
 309
 310         if (ret)
 311                 return ret;
 312         *bc = bytes_copied;
 313         return 0;
 314 }
 315
 316 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
 317                          size_t buflen, size_t *bc)
 318 {
 319         struct ib_umem *umem = srq->umem;
 320         size_t wqe_size = 1 << srq->msrq.wqe_shift;
 321
 322         if (buflen < wqe_size)
 323                 return -EINVAL;
 324
 325         if (!umem)
 326                 return -EOPNOTSUPP;
 327
 328         return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
 329 }
 330
 331 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 332 {
 333         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 334         struct ib_event event;
 335
 336         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 337                 /* This event is only valid for trans_qps */
 338                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 339         }
 340
 341         if (ibqp->event_handler) {
 342                 event.device     = ibqp->device;
 343                 event.element.qp = ibqp;
 344                 switch (type) {
 345                 case MLX5_EVENT_TYPE_PATH_MIG:
 346                         event.event = IB_EVENT_PATH_MIG;
 347                         break;
 348                 case MLX5_EVENT_TYPE_COMM_EST:
 349                         event.event = IB_EVENT_COMM_EST;
 350                         break;
 351                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 352                         event.event = IB_EVENT_SQ_DRAINED;
 353                         break;
 354                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 355                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 356                         break;
 357                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 358                         event.event = IB_EVENT_QP_FATAL;
 359                         break;
 360                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 361                         event.event = IB_EVENT_PATH_MIG_ERR;
 362                         break;
 363                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 364                         event.event = IB_EVENT_QP_REQ_ERR;
 365                         break;
 366                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 367                         event.event = IB_EVENT_QP_ACCESS_ERR;
 368                         break;
 369                 default:
 370                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 371                         return;
 372                 }
 373
 374                 ibqp->event_handler(&event, ibqp->qp_context);
 375         }
 376 }
 377
 378 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 379                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 380 {
 381         int wqe_size;
 382         int wq_size;
 383
 384         /* Sanity check RQ size before proceeding */
 385         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 386                 return -EINVAL;
 387
 388         if (!has_rq) {
 389                 qp->rq.max_gs = 0;
 390                 qp->rq.wqe_cnt = 0;
 391                 qp->rq.wqe_shift = 0;
 392                 cap->max_recv_wr = 0;
 393                 cap->max_recv_sge = 0;
 394         } else {
 395                 if (ucmd) {
 396                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 397                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 398                                 return -EINVAL;
 399                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 400                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 401                                 return -EINVAL;
 402                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 403                         qp->rq.max_post = qp->rq.wqe_cnt;
 404                 } else {
 405                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 406                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 407                         wqe_size = roundup_pow_of_two(wqe_size);
 408                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 409                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 410                         qp->rq.wqe_cnt = wq_size / wqe_size;
 411                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 412                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 413                                             wqe_size,
 414                                             MLX5_CAP_GEN(dev->mdev,
 415                                                          max_wqe_sz_rq));
 416                                 return -EINVAL;
 417                         }
 418                         qp->rq.wqe_shift = ilog2(wqe_size);
 419                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 420                         qp->rq.max_post = qp->rq.wqe_cnt;
 421                 }
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int sq_overhead(struct ib_qp_init_attr *attr)
 428 {
 429         int size = 0;
 430
 431         switch (attr->qp_type) {
 432         case IB_QPT_XRC_INI:
 433                 size += sizeof(struct mlx5_wqe_xrc_seg);
 434                 /* fall through */
 435         case IB_QPT_RC:
 436                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 437                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 438                             sizeof(struct mlx5_wqe_raddr_seg),
 439                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 440                             sizeof(struct mlx5_mkey_seg) +
 441                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 442                             MLX5_IB_UMR_OCTOWORD);
 443                 break;
 444
 445         case IB_QPT_XRC_TGT:
 446                 return 0;
 447
 448         case IB_QPT_UC:
 449                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 450                         max(sizeof(struct mlx5_wqe_raddr_seg),
 451                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 452                             sizeof(struct mlx5_mkey_seg));
 453                 break;
 454
 455         case IB_QPT_UD:
 456                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 457                         size += sizeof(struct mlx5_wqe_eth_pad) +
 458                                 sizeof(struct mlx5_wqe_eth_seg);
 459                 /* fall through */
 460         case IB_QPT_SMI:
 461         case MLX5_IB_QPT_HW_GSI:
 462                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 463                         sizeof(struct mlx5_wqe_datagram_seg);
 464                 break;
 465
 466         case MLX5_IB_QPT_REG_UMR:
 467                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 468                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 469                         sizeof(struct mlx5_mkey_seg);
 470                 break;
 471
 472         default:
 473                 return -EINVAL;
 474         }
 475
 476         return size;
 477 }
 478
 479 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 480 {
 481         int inl_size = 0;
 482         int size;
 483
 484         size = sq_overhead(attr);
 485         if (size < 0)
 486                 return size;
 487
 488         if (attr->cap.max_inline_data) {
 489                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 490                         attr->cap.max_inline_data;
 491         }
 492
 493         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 494         if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
 495             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 496                 return MLX5_SIG_WQE_SIZE;
 497         else
 498                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 499 }
 500
 501 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 502 {
 503         int max_sge;
 504
 505         if (attr->qp_type == IB_QPT_RC)
 506                 max_sge = (min_t(int, wqe_size, 512) -
 507                            sizeof(struct mlx5_wqe_ctrl_seg) -
 508                            sizeof(struct mlx5_wqe_raddr_seg)) /
 509                         sizeof(struct mlx5_wqe_data_seg);
 510         else if (attr->qp_type == IB_QPT_XRC_INI)
 511                 max_sge = (min_t(int, wqe_size, 512) -
 512                            sizeof(struct mlx5_wqe_ctrl_seg) -
 513                            sizeof(struct mlx5_wqe_xrc_seg) -
 514                            sizeof(struct mlx5_wqe_raddr_seg)) /
 515                         sizeof(struct mlx5_wqe_data_seg);
 516         else
 517                 max_sge = (wqe_size - sq_overhead(attr)) /
 518                         sizeof(struct mlx5_wqe_data_seg);
 519
 520         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 521                      sizeof(struct mlx5_wqe_data_seg));
 522 }
 523
 524 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 525                         struct mlx5_ib_qp *qp)
 526 {
 527         int wqe_size;
 528         int wq_size;
 529
 530         if (!attr->cap.max_send_wr)
 531                 return 0;
 532
 533         wqe_size = calc_send_wqe(attr);
 534         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 535         if (wqe_size < 0)
 536                 return wqe_size;
 537
 538         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 539                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 540                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 541                 return -EINVAL;
 542         }
 543
 544         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 545                               sizeof(struct mlx5_wqe_inline_seg);
 546         attr->cap.max_inline_data = qp->max_inline_data;
 547
 548         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 549         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 550         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 551                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 552                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 553                             qp->sq.wqe_cnt,
 554                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 555                 return -ENOMEM;
 556         }
 557         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 558         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 559         if (qp->sq.max_gs < attr->cap.max_send_sge)
 560                 return -ENOMEM;
 561
 562         attr->cap.max_send_sge = qp->sq.max_gs;
 563         qp->sq.max_post = wq_size / wqe_size;
 564         attr->cap.max_send_wr = qp->sq.max_post;
 565
 566         return wq_size;
 567 }
 568
 569 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 570                             struct mlx5_ib_qp *qp,
 571                             struct mlx5_ib_create_qp *ucmd,
 572                             struct mlx5_ib_qp_base *base,
 573                             struct ib_qp_init_attr *attr)
 574 {
 575         int desc_sz = 1 << qp->sq.wqe_shift;
 576
 577         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 578                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 579                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 580                 return -EINVAL;
 581         }
 582
 583         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 584                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 585                              ucmd->sq_wqe_count);
 586                 return -EINVAL;
 587         }
 588
 589         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 590
 591         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 592                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 593                              qp->sq.wqe_cnt,
 594                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 595                 return -EINVAL;
 596         }
 597
 598         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 599             qp->flags & MLX5_IB_QP_UNDERLAY) {
 600                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 601                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 602         } else {
 603                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 604                                          (qp->sq.wqe_cnt << 6);
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int qp_has_rq(struct ib_qp_init_attr *attr)
 611 {
 612         if (attr->qp_type == IB_QPT_XRC_INI ||
 613             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 614             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 615             !attr->cap.max_recv_wr)
 616                 return 0;
 617
 618         return 1;
 619 }
 620
 621 enum {
 622         /* this is the first blue flame register in the array of bfregs assigned
 623          * to a processes. Since we do not use it for blue flame but rather
 624          * regular 64 bit doorbells, we do not need a lock for maintaiing
 625          * "odd/even" order
 626          */
 627         NUM_NON_BLUE_FLAME_BFREGS = 1,
 628 };
 629
 630 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 631 {
 632         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 633 }
 634
 635 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 636                          struct mlx5_bfreg_info *bfregi)
 637 {
 638         int n;
 639
 640         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 641             NUM_NON_BLUE_FLAME_BFREGS;
 642
 643         return n >= 0 ? n : 0;
 644 }
 645
 646 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 647                            struct mlx5_bfreg_info *bfregi)
 648 {
 649         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 650 }
 651
 652 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 653                           struct mlx5_bfreg_info *bfregi)
 654 {
 655         int med;
 656
 657         med = num_med_bfreg(dev, bfregi);
 658         return ++med;
 659 }
 660
 661 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 662                                   struct mlx5_bfreg_info *bfregi)
 663 {
 664         int i;
 665
 666         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 667                 if (!bfregi->count[i]) {
 668                         bfregi->count[i]++;
 669                         return i;
 670                 }
 671         }
 672
 673         return -ENOMEM;
 674 }
 675
 676 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 677                                  struct mlx5_bfreg_info *bfregi)
 678 {
 679         int minidx = first_med_bfreg(dev, bfregi);
 680         int i;
 681
 682         if (minidx < 0)
 683                 return minidx;
 684
 685         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 686                 if (bfregi->count[i] < bfregi->count[minidx])
 687                         minidx = i;
 688                 if (!bfregi->count[minidx])
 689                         break;
 690         }
 691
 692         bfregi->count[minidx]++;
 693         return minidx;
 694 }
 695
 696 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 697                        struct mlx5_bfreg_info *bfregi)
 698 {
 699         int bfregn = -ENOMEM;
 700
 701         if (bfregi->lib_uar_dyn)
 702                 return -EINVAL;
 703
 704         mutex_lock(&bfregi->lock);
 705         if (bfregi->ver >= 2) {
 706                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 707                 if (bfregn < 0)
 708                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 709         }
 710
 711         if (bfregn < 0) {
 712                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 713                 bfregn = 0;
 714                 bfregi->count[bfregn]++;
 715         }
 716         mutex_unlock(&bfregi->lock);
 717
 718         return bfregn;
 719 }
 720
 721 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 722 {
 723         mutex_lock(&bfregi->lock);
 724         bfregi->count[bfregn]--;
 725         mutex_unlock(&bfregi->lock);
 726 }
 727
 728 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 729 {
 730         switch (state) {
 731         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 732         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 733         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 734         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 735         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 736         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 737         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 738         default:                return -1;
 739         }
 740 }
 741
 742 static int to_mlx5_st(enum ib_qp_type type)
 743 {
 744         switch (type) {
 745         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 746         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 747         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 748         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 749         case IB_QPT_XRC_INI:
 750         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 751         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 752         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 753         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 754         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 755         case IB_QPT_RAW_PACKET:
 756         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 757         case IB_QPT_MAX:
 758         default:                return -EINVAL;
 759         }
 760 }
 761
 762 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 763                              struct mlx5_ib_cq *recv_cq);
 764 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 765                                struct mlx5_ib_cq *recv_cq);
 766
 767 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 768                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 769                         bool dyn_bfreg)
 770 {
 771         unsigned int bfregs_per_sys_page;
 772         u32 index_of_sys_page;
 773         u32 offset;
 774
 775         if (bfregi->lib_uar_dyn)
 776                 return -EINVAL;
 777
 778         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 779                                 MLX5_NON_FP_BFREGS_PER_UAR;
 780         index_of_sys_page = bfregn / bfregs_per_sys_page;
 781
 782         if (dyn_bfreg) {
 783                 index_of_sys_page += bfregi->num_static_sys_pages;
 784
 785                 if (index_of_sys_page >= bfregi->num_sys_pages)
 786                         return -EINVAL;
 787
 788                 if (bfregn > bfregi->num_dyn_bfregs ||
 789                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 790                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 791                         return -EINVAL;
 792                 }
 793         }
 794
 795         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 796         return bfregi->sys_pages[index_of_sys_page] + offset;
 797 }
 798
 799 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 800                             unsigned long addr, size_t size,
 801                             struct ib_umem **umem, int *npages, int *page_shift,
 802                             int *ncont, u32 *offset)
 803 {
 804         int err;
 805
 806         *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
 807         if (IS_ERR(*umem)) {
 808                 mlx5_ib_dbg(dev, "umem_get failed\n");
 809                 return PTR_ERR(*umem);
 810         }
 811
 812         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 813
 814         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 815         if (err) {
 816                 mlx5_ib_warn(dev, "bad offset\n");
 817                 goto err_umem;
 818         }
 819
 820         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 821                     addr, size, *npages, *page_shift, *ncont, *offset);
 822
 823         return 0;
 824
 825 err_umem:
 826         ib_umem_release(*umem);
 827         *umem = NULL;
 828
 829         return err;
 830 }
 831
 832 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 833                             struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
 834 {
 835         struct mlx5_ib_ucontext *context =
 836                 rdma_udata_to_drv_context(
 837                         udata,
 838                         struct mlx5_ib_ucontext,
 839                         ibucontext);
 840
 841         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 842                 atomic_dec(&dev->delay_drop.rqs_cnt);
 843
 844         mlx5_ib_db_unmap_user(context, &rwq->db);
 845         ib_umem_release(rwq->umem);
 846 }
 847
 848 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 849                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 850                           struct mlx5_ib_create_wq *ucmd)
 851 {
 852         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
 853                 udata, struct mlx5_ib_ucontext, ibucontext);
 854         int page_shift = 0;
 855         int npages;
 856         u32 offset = 0;
 857         int ncont = 0;
 858         int err;
 859
 860         if (!ucmd->buf_addr)
 861                 return -EINVAL;
 862
 863         rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
 864         if (IS_ERR(rwq->umem)) {
 865                 mlx5_ib_dbg(dev, "umem_get failed\n");
 866                 err = PTR_ERR(rwq->umem);
 867                 return err;
 868         }
 869
 870         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 871                            &ncont, NULL);
 872         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 873                                      &rwq->rq_page_offset);
 874         if (err) {
 875                 mlx5_ib_warn(dev, "bad offset\n");
 876                 goto err_umem;
 877         }
 878
 879         rwq->rq_num_pas = ncont;
 880         rwq->page_shift = page_shift;
 881         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 882         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 883
 884         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 885                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 886                     npages, page_shift, ncont, offset);
 887
 888         err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
 889         if (err) {
 890                 mlx5_ib_dbg(dev, "map failed\n");
 891                 goto err_umem;
 892         }
 893
 894         rwq->create_type = MLX5_WQ_USER;
 895         return 0;
 896
 897 err_umem:
 898         ib_umem_release(rwq->umem);
 899         return err;
 900 }
 901
 902 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 903                          struct mlx5_bfreg_info *bfregi, int bfregn)
 904 {
 905         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 906                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 907 }
 908
 909 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 910                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 911                           struct ib_qp_init_attr *attr,
 912                           u32 **in,
 913                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 914                           struct mlx5_ib_qp_base *base)
 915 {
 916         struct mlx5_ib_ucontext *context;
 917         struct mlx5_ib_create_qp ucmd;
 918         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 919         int page_shift = 0;
 920         int uar_index = 0;
 921         int npages;
 922         u32 offset = 0;
 923         int bfregn;
 924         int ncont = 0;
 925         __be64 *pas;
 926         void *qpc;
 927         int err;
 928         u16 uid;
 929         u32 uar_flags;
 930
 931         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 932         if (err) {
 933                 mlx5_ib_dbg(dev, "copy failed\n");
 934                 return err;
 935         }
 936
 937         context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
 938                                             ibucontext);
 939         uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX |
 940                                   MLX5_QP_FLAG_BFREG_INDEX);
 941         switch (uar_flags) {
 942         case MLX5_QP_FLAG_UAR_PAGE_INDEX:
 943                 uar_index = ucmd.bfreg_index;
 944                 bfregn = MLX5_IB_INVALID_BFREG;
 945                 break;
 946         case MLX5_QP_FLAG_BFREG_INDEX:
 947                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 948                                                 ucmd.bfreg_index, true);
 949                 if (uar_index < 0)
 950                         return uar_index;
 951                 bfregn = MLX5_IB_INVALID_BFREG;
 952                 break;
 953         case 0:
 954                 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 955                         return -EINVAL;
 956                 bfregn = alloc_bfreg(dev, &context->bfregi);
 957                 if (bfregn < 0)
 958                         return bfregn;
 959                 break;
 960         default:
 961                 return -EINVAL;
 962         }
 963
 964         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 965         if (bfregn != MLX5_IB_INVALID_BFREG)
 966                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 967                                                 false);
 968
 969         qp->rq.offset = 0;
 970         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 971         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 972
 973         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 974         if (err)
 975                 goto err_bfreg;
 976
 977         if (ucmd.buf_addr && ubuffer->buf_size) {
 978                 ubuffer->buf_addr = ucmd.buf_addr;
 979                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 980                                        ubuffer->buf_size, &ubuffer->umem,
 981                                        &npages, &page_shift, &ncont, &offset);
 982                 if (err)
 983                         goto err_bfreg;
 984         } else {
 985                 ubuffer->umem = NULL;
 986         }
 987
 988         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 989                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 990         *in = kvzalloc(*inlen, GFP_KERNEL);
 991         if (!*in) {
 992                 err = -ENOMEM;
 993                 goto err_umem;
 994         }
 995
 996         uid = (attr->qp_type != IB_QPT_XRC_TGT &&
 997                attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
 998         MLX5_SET(create_qp_in, *in, uid, uid);
 999         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
1000         if (ubuffer->umem)
1001                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
1002
1003         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1004
1005         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1006         MLX5_SET(qpc, qpc, page_offset, offset);
1007
1008         MLX5_SET(qpc, qpc, uar_page, uar_index);
1009         if (bfregn != MLX5_IB_INVALID_BFREG)
1010                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
1011         else
1012                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
1013         qp->bfregn = bfregn;
1014
1015         err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db);
1016         if (err) {
1017                 mlx5_ib_dbg(dev, "map failed\n");
1018                 goto err_free;
1019         }
1020
1021         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1022         if (err) {
1023                 mlx5_ib_dbg(dev, "copy failed\n");
1024                 goto err_unmap;
1025         }
1026         qp->create_type = MLX5_QP_USER;
1027
1028         return 0;
1029
1030 err_unmap:
1031         mlx5_ib_db_unmap_user(context, &qp->db);
1032
1033 err_free:
1034         kvfree(*in);
1035
1036 err_umem:
1037         ib_umem_release(ubuffer->umem);
1038
1039 err_bfreg:
1040         if (bfregn != MLX5_IB_INVALID_BFREG)
1041                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
1042         return err;
1043 }
1044
1045 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1046                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base,
1047                             struct ib_udata *udata)
1048 {
1049         struct mlx5_ib_ucontext *context =
1050                 rdma_udata_to_drv_context(
1051                         udata,
1052                         struct mlx5_ib_ucontext,
1053                         ibucontext);
1054
1055         mlx5_ib_db_unmap_user(context, &qp->db);
1056         ib_umem_release(base->ubuffer.umem);
1057
1058         /*
1059          * Free only the BFREGs which are handled by the kernel.
1060          * BFREGs of UARs allocated dynamically are handled by user.
1061          */
1062         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1063                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1064 }
1065
1066 /* get_sq_edge - Get the next nearby edge.
1067  *
1068  * An 'edge' is defined as the first following address after the end
1069  * of the fragment or the SQ. Accordingly, during the WQE construction
1070  * which repetitively increases the pointer to write the next data, it
1071  * simply should check if it gets to an edge.
1072  *
1073  * @sq - SQ buffer.
1074  * @idx - Stride index in the SQ buffer.
1075  *
1076  * Return:
1077  *      The new edge.
1078  */
1079 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1080 {
1081         void *fragment_end;
1082
1083         fragment_end = mlx5_frag_buf_get_wqe
1084                 (&sq->fbc,
1085                  mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1086
1087         return fragment_end + MLX5_SEND_WQE_BB;
1088 }
1089
1090 static int create_kernel_qp(struct mlx5_ib_dev *dev,
1091                             struct ib_qp_init_attr *init_attr,
1092                             struct mlx5_ib_qp *qp,
1093                             u32 **in, int *inlen,
1094                             struct mlx5_ib_qp_base *base)
1095 {
1096         int uar_index;
1097         void *qpc;
1098         int err;
1099
1100         if (init_attr->create_flags & ~(IB_QP_CREATE_INTEGRITY_EN |
1101                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
1102                                         IB_QP_CREATE_IPOIB_UD_LSO |
1103                                         IB_QP_CREATE_NETIF_QP |
1104                                         MLX5_IB_QP_CREATE_SQPN_QP1 |
1105                                         MLX5_IB_QP_CREATE_WC_TEST))
1106                 return -EINVAL;
1107
1108         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1109                 qp->bf.bfreg = &dev->fp_bfreg;
1110         else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST)
1111                 qp->bf.bfreg = &dev->wc_bfreg;
1112         else
1113                 qp->bf.bfreg = &dev->bfreg;
1114
1115         /* We need to divide by two since each register is comprised of
1116          * two buffers of identical size, namely odd and even
1117          */
1118         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1119         uar_index = qp->bf.bfreg->index;
1120
1121         err = calc_sq_size(dev, init_attr, qp);
1122         if (err < 0) {
1123                 mlx5_ib_dbg(dev, "err %d\n", err);
1124                 return err;
1125         }
1126
1127         qp->rq.offset = 0;
1128         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1129         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1130
1131         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1132                                        &qp->buf, dev->mdev->priv.numa_node);
1133         if (err) {
1134                 mlx5_ib_dbg(dev, "err %d\n", err);
1135                 return err;
1136         }
1137
1138         if (qp->rq.wqe_cnt)
1139                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1140                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1141
1142         if (qp->sq.wqe_cnt) {
1143                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1144                                         MLX5_SEND_WQE_BB;
1145                 mlx5_init_fbc_offset(qp->buf.frags +
1146                                      (qp->sq.offset / PAGE_SIZE),
1147                                      ilog2(MLX5_SEND_WQE_BB),
1148                                      ilog2(qp->sq.wqe_cnt),
1149                                      sq_strides_offset, &qp->sq.fbc);
1150
1151                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1152         }
1153
1154         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1155                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1156         *in = kvzalloc(*inlen, GFP_KERNEL);
1157         if (!*in) {
1158                 err = -ENOMEM;
1159                 goto err_buf;
1160         }
1161
1162         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1163         MLX5_SET(qpc, qpc, uar_page, uar_index);
1164         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1165
1166         /* Set "fast registration enabled" for all kernel QPs */
1167         MLX5_SET(qpc, qpc, fre, 1);
1168         MLX5_SET(qpc, qpc, rlky, 1);
1169
1170         if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) {
1171                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1172                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1173         }
1174
1175         mlx5_fill_page_frag_array(&qp->buf,
1176                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1177                                                          *in, pas));
1178
1179         err = mlx5_db_alloc(dev->mdev, &qp->db);
1180         if (err) {
1181                 mlx5_ib_dbg(dev, "err %d\n", err);
1182                 goto err_free;
1183         }
1184
1185         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1186                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1187         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1188                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1189         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1190                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1191         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1192                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1193         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1194                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1195
1196         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1197             !qp->sq.w_list || !qp->sq.wqe_head) {
1198                 err = -ENOMEM;
1199                 goto err_wrid;
1200         }
1201         qp->create_type = MLX5_QP_KERNEL;
1202
1203         return 0;
1204
1205 err_wrid:
1206         kvfree(qp->sq.wqe_head);
1207         kvfree(qp->sq.w_list);
1208         kvfree(qp->sq.wrid);
1209         kvfree(qp->sq.wr_data);
1210         kvfree(qp->rq.wrid);
1211         mlx5_db_free(dev->mdev, &qp->db);
1212
1213 err_free:
1214         kvfree(*in);
1215
1216 err_buf:
1217         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1218         return err;
1219 }
1220
1221 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1222 {
1223         kvfree(qp->sq.wqe_head);
1224         kvfree(qp->sq.w_list);
1225         kvfree(qp->sq.wrid);
1226         kvfree(qp->sq.wr_data);
1227         kvfree(qp->rq.wrid);
1228         mlx5_db_free(dev->mdev, &qp->db);
1229         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1230 }
1231
1232 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1233 {
1234         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1235             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1236             (attr->qp_type == IB_QPT_XRC_INI))
1237                 return MLX5_SRQ_RQ;
1238         else if (!qp->has_rq)
1239                 return MLX5_ZERO_LEN_RQ;
1240         else
1241                 return MLX5_NON_ZERO_RQ;
1242 }
1243
1244 static int is_connected(enum ib_qp_type qp_type)
1245 {
1246         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1247             qp_type == MLX5_IB_QPT_DCI)
1248                 return 1;
1249
1250         return 0;
1251 }
1252
1253 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1254                                     struct mlx5_ib_qp *qp,
1255                                     struct mlx5_ib_sq *sq, u32 tdn,
1256                                     struct ib_pd *pd)
1257 {
1258         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
1259         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1260
1261         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1262         MLX5_SET(tisc, tisc, transport_domain, tdn);
1263         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1264                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1265
1266         return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1267 }
1268
1269 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1270                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1271 {
1272         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1273 }
1274
1275 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1276 {
1277         if (sq->flow_rule)
1278                 mlx5_del_flow_rules(sq->flow_rule);
1279         sq->flow_rule = NULL;
1280 }
1281
1282 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1283                                    struct ib_udata *udata,
1284                                    struct mlx5_ib_sq *sq, void *qpin,
1285                                    struct ib_pd *pd)
1286 {
1287         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1288         __be64 *pas;
1289         void *in;
1290         void *sqc;
1291         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1292         void *wq;
1293         int inlen;
1294         int err;
1295         int page_shift = 0;
1296         int npages;
1297         int ncont = 0;
1298         u32 offset = 0;
1299
1300         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1301                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1302                                &offset);
1303         if (err)
1304                 return err;
1305
1306         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1307         in = kvzalloc(inlen, GFP_KERNEL);
1308         if (!in) {
1309                 err = -ENOMEM;
1310                 goto err_umem;
1311         }
1312
1313         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1314         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1315         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1316         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1317                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1318         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1319         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1320         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1321         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1322         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1323         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1324             MLX5_CAP_ETH(dev->mdev, swp))
1325                 MLX5_SET(sqc, sqc, allow_swp, 1);
1326
1327         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1328         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1329         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1330         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1331         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1332         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1333         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1334         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1335         MLX5_SET(wq, wq, page_offset, offset);
1336
1337         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1338         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1339
1340         err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
1341
1342         kvfree(in);
1343
1344         if (err)
1345                 goto err_umem;
1346
1347         return 0;
1348
1349 err_umem:
1350         ib_umem_release(sq->ubuffer.umem);
1351         sq->ubuffer.umem = NULL;
1352
1353         return err;
1354 }
1355
1356 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1357                                      struct mlx5_ib_sq *sq)
1358 {
1359         destroy_flow_rule_vport_sq(sq);
1360         mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
1361         ib_umem_release(sq->ubuffer.umem);
1362 }
1363
1364 static size_t get_rq_pas_size(void *qpc)
1365 {
1366         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1367         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1368         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1369         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1370         u32 po_quanta     = 1 << (log_page_size - 6);
1371         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1372         u32 page_size     = 1 << log_page_size;
1373         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1374         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1375
1376         return rq_num_pas * sizeof(u64);
1377 }
1378
1379 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1380                                    struct mlx5_ib_rq *rq, void *qpin,
1381                                    size_t qpinlen, struct ib_pd *pd)
1382 {
1383         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1384         __be64 *pas;
1385         __be64 *qp_pas;
1386         void *in;
1387         void *rqc;
1388         void *wq;
1389         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1390         size_t rq_pas_size = get_rq_pas_size(qpc);
1391         size_t inlen;
1392         int err;
1393
1394         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1395                 return -EINVAL;
1396
1397         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1398         in = kvzalloc(inlen, GFP_KERNEL);
1399         if (!in)
1400                 return -ENOMEM;
1401
1402         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1403         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1404         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1405                 MLX5_SET(rqc, rqc, vsd, 1);
1406         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1407         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1408         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1409         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1410         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1411
1412         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1413                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1414
1415         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1416         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1417         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1418                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1419         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1420         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1421         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1422         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1423         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1424         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1425
1426         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1427         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1428         memcpy(pas, qp_pas, rq_pas_size);
1429
1430         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
1431
1432         kvfree(in);
1433
1434         return err;
1435 }
1436
1437 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1438                                      struct mlx5_ib_rq *rq)
1439 {
1440         mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
1441 }
1442
1443 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1444 {
1445         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1446                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1447                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1448 }
1449
1450 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1451                                       struct mlx5_ib_rq *rq,
1452                                       u32 qp_flags_en,
1453                                       struct ib_pd *pd)
1454 {
1455         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1456                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1457                 mlx5_ib_disable_lb(dev, false, true);
1458         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1459 }
1460
1461 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1462                                     struct mlx5_ib_rq *rq, u32 tdn,
1463                                     u32 *qp_flags_en, struct ib_pd *pd,
1464                                     u32 *out)
1465 {
1466         u8 lb_flag = 0;
1467         u32 *in;
1468         void *tirc;
1469         int inlen;
1470         int err;
1471
1472         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1473         in = kvzalloc(inlen, GFP_KERNEL);
1474         if (!in)
1475                 return -ENOMEM;
1476
1477         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1478         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1479         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1480         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1481         MLX5_SET(tirc, tirc, transport_domain, tdn);
1482         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1483                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1484
1485         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1486                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1487
1488         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1489                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1490
1491         if (dev->is_rep) {
1492                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1493                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1494         }
1495
1496         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1497         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1498         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1499         rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1500         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1501                 err = mlx5_ib_enable_lb(dev, false, true);
1502
1503                 if (err)
1504                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1505         }
1506         kvfree(in);
1507
1508         return err;
1509 }
1510
1511 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1512                                 u32 *in, size_t inlen,
1513                                 struct ib_pd *pd,
1514                                 struct ib_udata *udata,
1515                                 struct mlx5_ib_create_qp_resp *resp)
1516 {
1517         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1518         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1519         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1520         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1521                 udata, struct mlx5_ib_ucontext, ibucontext);
1522         int err;
1523         u32 tdn = mucontext->tdn;
1524         u16 uid = to_mpd(pd)->uid;
1525         u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1526
1527         if (qp->sq.wqe_cnt) {
1528                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1529                 if (err)
1530                         return err;
1531
1532                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1533                 if (err)
1534                         goto err_destroy_tis;
1535
1536                 if (uid) {
1537                         resp->tisn = sq->tisn;
1538                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1539                         resp->sqn = sq->base.mqp.qpn;
1540                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1541                 }
1542
1543                 sq->base.container_mibqp = qp;
1544                 sq->base.mqp.event = mlx5_ib_qp_event;
1545         }
1546
1547         if (qp->rq.wqe_cnt) {
1548                 rq->base.container_mibqp = qp;
1549
1550                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1551                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1552                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1553                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1554                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1555                 if (err)
1556                         goto err_destroy_sq;
1557
1558                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1559                                                out);
1560                 if (err)
1561                         goto err_destroy_rq;
1562
1563                 if (uid) {
1564                         resp->rqn = rq->base.mqp.qpn;
1565                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1566                         resp->tirn = rq->tirn;
1567                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1568                         if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1569                                 resp->tir_icm_addr = MLX5_GET(
1570                                         create_tir_out, out, icm_address_31_0);
1571                                 resp->tir_icm_addr |=
1572                                         (u64)MLX5_GET(create_tir_out, out,
1573                                                       icm_address_39_32)
1574                                         << 32;
1575                                 resp->tir_icm_addr |=
1576                                         (u64)MLX5_GET(create_tir_out, out,
1577                                                       icm_address_63_40)
1578                                         << 40;
1579                                 resp->comp_mask |=
1580                                         MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1581                         }
1582                 }
1583         }
1584
1585         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1586                                                      rq->base.mqp.qpn;
1587         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1588         if (err)
1589                 goto err_destroy_tir;
1590
1591         return 0;
1592
1593 err_destroy_tir:
1594         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1595 err_destroy_rq:
1596         destroy_raw_packet_qp_rq(dev, rq);
1597 err_destroy_sq:
1598         if (!qp->sq.wqe_cnt)
1599                 return err;
1600         destroy_raw_packet_qp_sq(dev, sq);
1601 err_destroy_tis:
1602         destroy_raw_packet_qp_tis(dev, sq, pd);
1603
1604         return err;
1605 }
1606
1607 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1608                                   struct mlx5_ib_qp *qp)
1609 {
1610         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1611         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1612         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1613
1614         if (qp->rq.wqe_cnt) {
1615                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1616                 destroy_raw_packet_qp_rq(dev, rq);
1617         }
1618
1619         if (qp->sq.wqe_cnt) {
1620                 destroy_raw_packet_qp_sq(dev, sq);
1621                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1622         }
1623 }
1624
1625 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1626                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1627 {
1628         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1629         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1630
1631         sq->sq = &qp->sq;
1632         rq->rq = &qp->rq;
1633         sq->doorbell = &qp->db;
1634         rq->doorbell = &qp->db;
1635 }
1636
1637 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1638 {
1639         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1640                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1641                 mlx5_ib_disable_lb(dev, false, true);
1642         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1643                              to_mpd(qp->ibqp.pd)->uid);
1644 }
1645
1646 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1647                                  struct ib_pd *pd,
1648                                  struct ib_qp_init_attr *init_attr,
1649                                  struct ib_udata *udata)
1650 {
1651         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1652                 udata, struct mlx5_ib_ucontext, ibucontext);
1653         struct mlx5_ib_create_qp_resp resp = {};
1654         int inlen;
1655         int outlen;
1656         int err;
1657         u32 *in;
1658         u32 *out;
1659         void *tirc;
1660         void *hfso;
1661         u32 selected_fields = 0;
1662         u32 outer_l4;
1663         size_t min_resp_len;
1664         u32 tdn = mucontext->tdn;
1665         struct mlx5_ib_create_qp_rss ucmd = {};
1666         size_t required_cmd_sz;
1667         u8 lb_flag = 0;
1668
1669         if (init_attr->create_flags || init_attr->send_cq)
1670                 return -EINVAL;
1671
1672         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1673         if (udata->outlen < min_resp_len)
1674                 return -EINVAL;
1675
1676         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1677         if (udata->inlen < required_cmd_sz) {
1678                 mlx5_ib_dbg(dev, "invalid inlen\n");
1679                 return -EINVAL;
1680         }
1681
1682         if (udata->inlen > sizeof(ucmd) &&
1683             !ib_is_udata_cleared(udata, sizeof(ucmd),
1684                                  udata->inlen - sizeof(ucmd))) {
1685                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1686                 return -EOPNOTSUPP;
1687         }
1688
1689         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1690                 mlx5_ib_dbg(dev, "copy failed\n");
1691                 return -EFAULT;
1692         }
1693
1694         if (ucmd.comp_mask) {
1695                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1696                 return -EOPNOTSUPP;
1697         }
1698
1699         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1700                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1701                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1702                 mlx5_ib_dbg(dev, "invalid flags\n");
1703                 return -EOPNOTSUPP;
1704         }
1705
1706         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1707             !tunnel_offload_supported(dev->mdev)) {
1708                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1709                 return -EOPNOTSUPP;
1710         }
1711
1712         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1713             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1714                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1715                 return -EOPNOTSUPP;
1716         }
1717
1718         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->is_rep) {
1719                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1720                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1721         }
1722
1723         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1724                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1725                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1726         }
1727
1728         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1729         if (err) {
1730                 mlx5_ib_dbg(dev, "copy failed\n");
1731                 return -EINVAL;
1732         }
1733
1734         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1735         outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1736         in = kvzalloc(inlen + outlen, GFP_KERNEL);
1737         if (!in)
1738                 return -ENOMEM;
1739
1740         out = in + MLX5_ST_SZ_DW(create_tir_in);
1741         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1742         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1743         MLX5_SET(tirc, tirc, disp_type,
1744                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1745         MLX5_SET(tirc, tirc, indirect_table,
1746                  init_attr->rwq_ind_tbl->ind_tbl_num);
1747         MLX5_SET(tirc, tirc, transport_domain, tdn);
1748
1749         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1750
1751         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1752                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1753
1754         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1755
1756         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1757                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1758         else
1759                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1760
1761         switch (ucmd.rx_hash_function) {
1762         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1763         {
1764                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1765                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1766
1767                 if (len != ucmd.rx_key_len) {
1768                         err = -EINVAL;
1769                         goto err;
1770                 }
1771
1772                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1773                 memcpy(rss_key, ucmd.rx_hash_key, len);
1774                 break;
1775         }
1776         default:
1777                 err = -EOPNOTSUPP;
1778                 goto err;
1779         }
1780
1781         if (!ucmd.rx_hash_fields_mask) {
1782                 /* special case when this TIR serves as steering entry without hashing */
1783                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1784                         goto create_tir;
1785                 err = -EINVAL;
1786                 goto err;
1787         }
1788
1789         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1790              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1791              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1792              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1793                 err = -EINVAL;
1794                 goto err;
1795         }
1796
1797         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1798         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1799             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1800                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1801                          MLX5_L3_PROT_TYPE_IPV4);
1802         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1803                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1804                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1805                          MLX5_L3_PROT_TYPE_IPV6);
1806
1807         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1808                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1809                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1810                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1811                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1812
1813         /* Check that only one l4 protocol is set */
1814         if (outer_l4 & (outer_l4 - 1)) {
1815                 err = -EINVAL;
1816                 goto err;
1817         }
1818
1819         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1820         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1821             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1822                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1823                          MLX5_L4_PROT_TYPE_TCP);
1824         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1825                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1826                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1827                          MLX5_L4_PROT_TYPE_UDP);
1828
1829         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1830             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1831                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1832
1833         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1834             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1835                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1836
1837         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1838             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1839                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1840
1841         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1842             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1843                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1844
1845         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1846                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1847
1848         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1849
1850 create_tir:
1851         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1852         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1853
1854         qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1855         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1856                 err = mlx5_ib_enable_lb(dev, false, true);
1857
1858                 if (err)
1859                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1860                                              to_mpd(pd)->uid);
1861         }
1862
1863         if (err)
1864                 goto err;
1865
1866         if (mucontext->devx_uid) {
1867                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1868                 resp.tirn = qp->rss_qp.tirn;
1869                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1870                         resp.tir_icm_addr =
1871                                 MLX5_GET(create_tir_out, out, icm_address_31_0);
1872                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1873                                                            icm_address_39_32)
1874                                              << 32;
1875                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1876                                                            icm_address_63_40)
1877                                              << 40;
1878                         resp.comp_mask |=
1879                                 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1880                 }
1881         }
1882
1883         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1884         if (err)
1885                 goto err_copy;
1886
1887         kvfree(in);
1888         /* qpn is reserved for that QP */
1889         qp->trans_qp.base.mqp.qpn = 0;
1890         qp->flags |= MLX5_IB_QP_RSS;
1891         return 0;
1892
1893 err_copy:
1894         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1895 err:
1896         kvfree(in);
1897         return err;
1898 }
1899
1900 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1901                                          void *qpc)
1902 {
1903         int rcqe_sz;
1904
1905         if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1906                 return;
1907
1908         rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1909
1910         if (init_attr->qp_type == MLX5_IB_QPT_DCT) {
1911                 if (rcqe_sz == 128)
1912                         MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1913
1914                 return;
1915         }
1916
1917         MLX5_SET(qpc, qpc, cs_res,
1918                  rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
1919                                   MLX5_RES_SCAT_DATA32_CQE);
1920 }
1921
1922 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1923                                          struct ib_qp_init_attr *init_attr,
1924                                          struct mlx5_ib_create_qp *ucmd,
1925                                          void *qpc)
1926 {
1927         enum ib_qp_type qpt = init_attr->qp_type;
1928         int scqe_sz;
1929         bool allow_scat_cqe = false;
1930
1931         if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1932                 return;
1933
1934         if (ucmd)
1935                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1936
1937         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1938                 return;
1939
1940         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1941         if (scqe_sz == 128) {
1942                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1943                 return;
1944         }
1945
1946         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1947             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1948                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1949 }
1950
1951 static int atomic_size_to_mode(int size_mask)
1952 {
1953         /* driver does not support atomic_size > 256B
1954          * and does not know how to translate bigger sizes
1955          */
1956         int supported_size_mask = size_mask & 0x1ff;
1957         int log_max_size;
1958
1959         if (!supported_size_mask)
1960                 return -EOPNOTSUPP;
1961
1962         log_max_size = __fls(supported_size_mask);
1963
1964         if (log_max_size > 3)
1965                 return log_max_size;
1966
1967         return MLX5_ATOMIC_MODE_8B;
1968 }
1969
1970 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1971                            enum ib_qp_type qp_type)
1972 {
1973         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1974         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1975         int atomic_mode = -EOPNOTSUPP;
1976         int atomic_size_mask;
1977
1978         if (!atomic)
1979                 return -EOPNOTSUPP;
1980
1981         if (qp_type == MLX5_IB_QPT_DCT)
1982                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1983         else
1984                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1985
1986         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1987             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1988                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1989
1990         if (atomic_mode <= 0 &&
1991             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1992              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1993                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1994
1995         return atomic_mode;
1996 }
1997
1998 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1999 {
2000         return (input & ~supported) == 0;
2001 }
2002
2003 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2004                             struct ib_qp_init_attr *init_attr,
2005                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
2006 {
2007         struct mlx5_ib_resources *devr = &dev->devr;
2008         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2009         struct mlx5_core_dev *mdev = dev->mdev;
2010         struct mlx5_ib_create_qp_resp resp = {};
2011         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2012                 udata, struct mlx5_ib_ucontext, ibucontext);
2013         struct mlx5_ib_cq *send_cq;
2014         struct mlx5_ib_cq *recv_cq;
2015         unsigned long flags;
2016         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2017         struct mlx5_ib_create_qp ucmd;
2018         struct mlx5_ib_qp_base *base;
2019         int mlx5_st;
2020         void *qpc;
2021         u32 *in;
2022         int err;
2023
2024         mutex_init(&qp->mutex);
2025         spin_lock_init(&qp->sq.lock);
2026         spin_lock_init(&qp->rq.lock);
2027
2028         mlx5_st = to_mlx5_st(init_attr->qp_type);
2029         if (mlx5_st < 0)
2030                 return -EINVAL;
2031
2032         if (init_attr->rwq_ind_tbl)
2033                 return create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
2034
2035         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
2036                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
2037                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
2038                         return -EINVAL;
2039                 } else {
2040                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
2041                 }
2042         }
2043
2044         if (init_attr->create_flags &
2045                         (IB_QP_CREATE_CROSS_CHANNEL |
2046                          IB_QP_CREATE_MANAGED_SEND |
2047                          IB_QP_CREATE_MANAGED_RECV)) {
2048                 if (!MLX5_CAP_GEN(mdev, cd)) {
2049                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
2050                         return -EINVAL;
2051                 }
2052                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
2053                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
2054                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
2055                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
2056                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
2057                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
2058         }
2059
2060         if (init_attr->qp_type == IB_QPT_UD &&
2061             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
2062                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
2063                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
2064                         return -EOPNOTSUPP;
2065                 }
2066
2067         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
2068                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2069                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
2070                         return -EOPNOTSUPP;
2071                 }
2072                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
2073                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
2074                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
2075                         return -EOPNOTSUPP;
2076                 }
2077                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
2078         }
2079
2080         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2081                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2082
2083         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
2084                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
2085                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
2086                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
2087                         return -EOPNOTSUPP;
2088                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
2089         }
2090
2091         if (udata) {
2092                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
2093                         mlx5_ib_dbg(dev, "copy failed\n");
2094                         return -EFAULT;
2095                 }
2096
2097                 if (!check_flags_mask(ucmd.flags,
2098                                       MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
2099                                       MLX5_QP_FLAG_BFREG_INDEX |
2100                                       MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE |
2101                                       MLX5_QP_FLAG_SCATTER_CQE |
2102                                       MLX5_QP_FLAG_SIGNATURE |
2103                                       MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC |
2104                                       MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2105                                       MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2106                                       MLX5_QP_FLAG_UAR_PAGE_INDEX |
2107                                       MLX5_QP_FLAG_TYPE_DCI |
2108                                       MLX5_QP_FLAG_TYPE_DCT))
2109                         return -EINVAL;
2110
2111                 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx);
2112                 if (err)
2113                         return err;
2114
2115                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
2116                 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
2117                         qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
2118                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
2119                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
2120                             !tunnel_offload_supported(mdev)) {
2121                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
2122                                 return -EOPNOTSUPP;
2123                         }
2124                         qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
2125                 }
2126
2127                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
2128                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2129                                 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
2130                                 return -EOPNOTSUPP;
2131                         }
2132                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
2133                 }
2134
2135                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
2136                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2137                                 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
2138                                 return -EOPNOTSUPP;
2139                         }
2140                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
2141                 }
2142
2143                 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
2144                         if (init_attr->qp_type != IB_QPT_RC ||
2145                                 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
2146                                 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
2147                                 return -EOPNOTSUPP;
2148                         }
2149                         qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
2150                 }
2151
2152                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
2153                         if (init_attr->qp_type != IB_QPT_UD ||
2154                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
2155                              MLX5_CAP_PORT_TYPE_IB) ||
2156                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
2157                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
2158                                 return -EOPNOTSUPP;
2159                         }
2160
2161                         qp->flags |= MLX5_IB_QP_UNDERLAY;
2162                         qp->underlay_qpn = init_attr->source_qpn;
2163                 }
2164         } else {
2165                 qp->wq_sig = !!wq_signature;
2166         }
2167
2168         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2169                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2170                &qp->raw_packet_qp.rq.base :
2171                &qp->trans_qp.base;
2172
2173         qp->has_rq = qp_has_rq(init_attr);
2174         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
2175                           qp, udata ? &ucmd : NULL);
2176         if (err) {
2177                 mlx5_ib_dbg(dev, "err %d\n", err);
2178                 return err;
2179         }
2180
2181         if (pd) {
2182                 if (udata) {
2183                         __u32 max_wqes =
2184                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
2185                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
2186                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
2187                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
2188                                 mlx5_ib_dbg(dev, "invalid rq params\n");
2189                                 return -EINVAL;
2190                         }
2191                         if (ucmd.sq_wqe_count > max_wqes) {
2192                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
2193                                             ucmd.sq_wqe_count, max_wqes);
2194                                 return -EINVAL;
2195                         }
2196                         if (init_attr->create_flags &
2197                             MLX5_IB_QP_CREATE_SQPN_QP1) {
2198                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2199                                 return -EINVAL;
2200                         }
2201                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2202                                              &resp, &inlen, base);
2203                         if (err)
2204                                 mlx5_ib_dbg(dev, "err %d\n", err);
2205                 } else {
2206                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2207                                                base);
2208                         if (err)
2209                                 mlx5_ib_dbg(dev, "err %d\n", err);
2210                 }
2211
2212                 if (err)
2213                         return err;
2214         } else {
2215                 in = kvzalloc(inlen, GFP_KERNEL);
2216                 if (!in)
2217                         return -ENOMEM;
2218
2219                 qp->create_type = MLX5_QP_EMPTY;
2220         }
2221
2222         if (is_sqp(init_attr->qp_type))
2223                 qp->port = init_attr->port_num;
2224
2225         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2226
2227         MLX5_SET(qpc, qpc, st, mlx5_st);
2228         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2229
2230         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2231                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2232         else
2233                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2234
2235
2236         if (qp->wq_sig)
2237                 MLX5_SET(qpc, qpc, wq_signature, 1);
2238
2239         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2240                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2241
2242         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
2243                 MLX5_SET(qpc, qpc, cd_master, 1);
2244         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
2245                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2246         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
2247                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2248         if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2249                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2250         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
2251                 configure_responder_scat_cqe(init_attr, qpc);
2252                 configure_requester_scat_cqe(dev, init_attr,
2253                                              udata ? &ucmd : NULL,
2254                                              qpc);
2255         }
2256
2257         if (qp->rq.wqe_cnt) {
2258                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2259                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2260         }
2261
2262         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2263
2264         if (qp->sq.wqe_cnt) {
2265                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2266         } else {
2267                 MLX5_SET(qpc, qpc, no_sq, 1);
2268                 if (init_attr->srq &&
2269                     init_attr->srq->srq_type == IB_SRQT_TM)
2270                         MLX5_SET(qpc, qpc, offload_type,
2271                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2272         }
2273
2274         /* Set default resources */
2275         switch (init_attr->qp_type) {
2276         case IB_QPT_XRC_TGT:
2277                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2278                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2279                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2280                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2281                 break;
2282         case IB_QPT_XRC_INI:
2283                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2284                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2285                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2286                 break;
2287         default:
2288                 if (init_attr->srq) {
2289                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2290                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2291                 } else {
2292                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2293                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2294                 }
2295         }
2296
2297         if (init_attr->send_cq)
2298                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2299
2300         if (init_attr->recv_cq)
2301                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2302
2303         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2304
2305         /* 0xffffff means we ask to work with cqe version 0 */
2306         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2307                 MLX5_SET(qpc, qpc, user_index, uidx);
2308
2309         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2310         if (init_attr->qp_type == IB_QPT_UD &&
2311             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2312                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2313                 qp->flags |= MLX5_IB_QP_LSO;
2314         }
2315
2316         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2317                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2318                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2319                         err = -EOPNOTSUPP;
2320                         goto err;
2321                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2322                         MLX5_SET(qpc, qpc, end_padding_mode,
2323                                  MLX5_WQ_END_PAD_MODE_ALIGN);
2324                 } else {
2325                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2326                 }
2327         }
2328
2329         if (inlen < 0) {
2330                 err = -EINVAL;
2331                 goto err;
2332         }
2333
2334         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2335             qp->flags & MLX5_IB_QP_UNDERLAY) {
2336                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2337                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2338                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2339                                            &resp);
2340         } else {
2341                 err = mlx5_core_create_qp(dev, &base->mqp, in, inlen);
2342         }
2343
2344         if (err) {
2345                 mlx5_ib_dbg(dev, "create qp failed\n");
2346                 goto err_create;
2347         }
2348
2349         kvfree(in);
2350
2351         base->container_mibqp = qp;
2352         base->mqp.event = mlx5_ib_qp_event;
2353
2354         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2355                 &send_cq, &recv_cq);
2356         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2357         mlx5_ib_lock_cqs(send_cq, recv_cq);
2358         /* Maintain device to QPs access, needed for further handling via reset
2359          * flow
2360          */
2361         list_add_tail(&qp->qps_list, &dev->qp_list);
2362         /* Maintain CQ to QPs access, needed for further handling via reset flow
2363          */
2364         if (send_cq)
2365                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2366         if (recv_cq)
2367                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2368         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2369         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2370
2371         return 0;
2372
2373 err_create:
2374         if (qp->create_type == MLX5_QP_USER)
2375                 destroy_qp_user(dev, pd, qp, base, udata);
2376         else if (qp->create_type == MLX5_QP_KERNEL)
2377                 destroy_qp_kernel(dev, qp);
2378
2379 err:
2380         kvfree(in);
2381         return err;
2382 }
2383
2384 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2385         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2386 {
2387         if (send_cq) {
2388                 if (recv_cq) {
2389                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2390                                 spin_lock(&send_cq->lock);
2391                                 spin_lock_nested(&recv_cq->lock,
2392                                                  SINGLE_DEPTH_NESTING);
2393                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2394                                 spin_lock(&send_cq->lock);
2395                                 __acquire(&recv_cq->lock);
2396                         } else {
2397                                 spin_lock(&recv_cq->lock);
2398                                 spin_lock_nested(&send_cq->lock,
2399                                                  SINGLE_DEPTH_NESTING);
2400                         }
2401                 } else {
2402                         spin_lock(&send_cq->lock);
2403                         __acquire(&recv_cq->lock);
2404                 }
2405         } else if (recv_cq) {
2406                 spin_lock(&recv_cq->lock);
2407                 __acquire(&send_cq->lock);
2408         } else {
2409                 __acquire(&send_cq->lock);
2410                 __acquire(&recv_cq->lock);
2411         }
2412 }
2413
2414 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2415         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2416 {
2417         if (send_cq) {
2418                 if (recv_cq) {
2419                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2420                                 spin_unlock(&recv_cq->lock);
2421                                 spin_unlock(&send_cq->lock);
2422                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2423                                 __release(&recv_cq->lock);
2424                                 spin_unlock(&send_cq->lock);
2425                         } else {
2426                                 spin_unlock(&send_cq->lock);
2427                                 spin_unlock(&recv_cq->lock);
2428                         }
2429                 } else {
2430                         __release(&recv_cq->lock);
2431                         spin_unlock(&send_cq->lock);
2432                 }
2433         } else if (recv_cq) {
2434                 __release(&send_cq->lock);
2435                 spin_unlock(&recv_cq->lock);
2436         } else {
2437                 __release(&recv_cq->lock);
2438                 __release(&send_cq->lock);
2439         }
2440 }
2441
2442 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2443 {
2444         return to_mpd(qp->ibqp.pd);
2445 }
2446
2447 static void get_cqs(enum ib_qp_type qp_type,
2448                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2449                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2450 {
2451         switch (qp_type) {
2452         case IB_QPT_XRC_TGT:
2453                 *send_cq = NULL;
2454                 *recv_cq = NULL;
2455                 break;
2456         case MLX5_IB_QPT_REG_UMR:
2457         case IB_QPT_XRC_INI:
2458                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2459                 *recv_cq = NULL;
2460                 break;
2461
2462         case IB_QPT_SMI:
2463         case MLX5_IB_QPT_HW_GSI:
2464         case IB_QPT_RC:
2465         case IB_QPT_UC:
2466         case IB_QPT_UD:
2467         case IB_QPT_RAW_IPV6:
2468         case IB_QPT_RAW_ETHERTYPE:
2469         case IB_QPT_RAW_PACKET:
2470                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2471                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2472                 break;
2473
2474         case IB_QPT_MAX:
2475         default:
2476                 *send_cq = NULL;
2477                 *recv_cq = NULL;
2478                 break;
2479         }
2480 }
2481
2482 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2483                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2484                                 u8 lag_tx_affinity);
2485
2486 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2487                               struct ib_udata *udata)
2488 {
2489         struct mlx5_ib_cq *send_cq, *recv_cq;
2490         struct mlx5_ib_qp_base *base;
2491         unsigned long flags;
2492         int err;
2493
2494         if (qp->ibqp.rwq_ind_tbl) {
2495                 destroy_rss_raw_qp_tir(dev, qp);
2496                 return;
2497         }
2498
2499         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2500                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2501                &qp->raw_packet_qp.rq.base :
2502                &qp->trans_qp.base;
2503
2504         if (qp->state != IB_QPS_RESET) {
2505                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2506                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2507                         err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
2508                                                   NULL, &base->mqp);
2509                 } else {
2510                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2511                                 .operation = MLX5_CMD_OP_2RST_QP
2512                         };
2513
2514                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2515                 }
2516                 if (err)
2517                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2518                                      base->mqp.qpn);
2519         }
2520
2521         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2522                 &send_cq, &recv_cq);
2523
2524         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2525         mlx5_ib_lock_cqs(send_cq, recv_cq);
2526         /* del from lists under both locks above to protect reset flow paths */
2527         list_del(&qp->qps_list);
2528         if (send_cq)
2529                 list_del(&qp->cq_send_list);
2530
2531         if (recv_cq)
2532                 list_del(&qp->cq_recv_list);
2533
2534         if (qp->create_type == MLX5_QP_KERNEL) {
2535                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2536                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2537                 if (send_cq != recv_cq)
2538                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2539                                            NULL);
2540         }
2541         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2542         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2543
2544         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2545             qp->flags & MLX5_IB_QP_UNDERLAY) {
2546                 destroy_raw_packet_qp(dev, qp);
2547         } else {
2548                 err = mlx5_core_destroy_qp(dev, &base->mqp);
2549                 if (err)
2550                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2551                                      base->mqp.qpn);
2552         }
2553
2554         if (qp->create_type == MLX5_QP_KERNEL)
2555                 destroy_qp_kernel(dev, qp);
2556         else if (qp->create_type == MLX5_QP_USER)
2557                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
2558 }
2559
2560 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, struct mlx5_ib_qp *qp,
2561                                         struct ib_qp_init_attr *attr,
2562                                         struct mlx5_ib_create_qp *ucmd,
2563                                         struct ib_udata *udata)
2564 {
2565         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2566                 udata, struct mlx5_ib_ucontext, ibucontext);
2567         int err = 0;
2568         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2569         void *dctc;
2570
2571         if (!attr->srq || !attr->recv_cq)
2572                 return ERR_PTR(-EINVAL);
2573
2574         err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx);
2575         if (err)
2576                 return ERR_PTR(err);
2577
2578         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2579         if (!qp->dct.in)
2580                 return ERR_PTR(-ENOMEM);
2581
2582         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2583         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2584         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2585         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2586         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2587         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2588         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2589         MLX5_SET(dctc, dctc, user_index, uidx);
2590
2591         if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2592                 configure_responder_scat_cqe(attr, dctc);
2593
2594         qp->state = IB_QPS_RESET;
2595
2596         return &qp->ibqp;
2597 }
2598
2599 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2600                            struct ib_qp_init_attr *init_attr,
2601                            struct mlx5_ib_create_qp *ucmd,
2602                            struct ib_udata *udata)
2603 {
2604         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2605         int err;
2606
2607         if (udata->inlen < sizeof(*ucmd)) {
2608                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2609                 return -EINVAL;
2610         }
2611         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2612         if (err)
2613                 return err;
2614
2615         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2616                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2617         } else {
2618                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2619                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2620                 } else {
2621                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2622                         return -EINVAL;
2623                 }
2624         }
2625
2626         return 0;
2627 }
2628
2629 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr)
2630 {
2631         if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2632                 goto out;
2633
2634         switch (attr->qp_type) {
2635         case IB_QPT_XRC_TGT:
2636         case IB_QPT_XRC_INI:
2637                 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2638                         goto out;
2639                 fallthrough;
2640         case IB_QPT_RAW_PACKET:
2641         case IB_QPT_RC:
2642         case IB_QPT_UC:
2643         case IB_QPT_UD:
2644         case IB_QPT_SMI:
2645         case MLX5_IB_QPT_HW_GSI:
2646         case MLX5_IB_QPT_REG_UMR:
2647         case IB_QPT_DRIVER:
2648         case IB_QPT_GSI:
2649                 return 0;
2650         case IB_QPT_RAW_IPV6:
2651         case IB_QPT_RAW_ETHERTYPE:
2652         case IB_QPT_MAX:
2653         default:
2654                 goto out;
2655         }
2656
2657         return 0;
2658
2659 out:
2660         mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2661         return -EOPNOTSUPP;
2662 }
2663
2664 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2665                             struct ib_qp_init_attr *attr,
2666                             struct ib_udata *udata)
2667 {
2668         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2669                 udata, struct mlx5_ib_ucontext, ibucontext);
2670
2671         if (!udata) {
2672                 /* Kernel create_qp callers */
2673                 if (attr->rwq_ind_tbl)
2674                         return -EOPNOTSUPP;
2675
2676                 switch (attr->qp_type) {
2677                 case IB_QPT_RAW_PACKET:
2678                 case IB_QPT_DRIVER:
2679                         return -EOPNOTSUPP;
2680                 default:
2681                         return 0;
2682                 }
2683         }
2684
2685         /* Userspace create_qp callers */
2686         if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2687                 mlx5_ib_dbg(dev,
2688                         "Raw Packet QP is only supported for CQE version > 0\n");
2689                 return -EINVAL;
2690         }
2691
2692         if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2693                 mlx5_ib_dbg(dev,
2694                             "Wrong QP type %d for the RWQ indirect table\n",
2695                             attr->qp_type);
2696                 return -EINVAL;
2697         }
2698
2699         switch (attr->qp_type) {
2700         case IB_QPT_SMI:
2701         case MLX5_IB_QPT_HW_GSI:
2702         case MLX5_IB_QPT_REG_UMR:
2703         case IB_QPT_GSI:
2704                 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2705                             attr->qp_type);
2706                 return -EINVAL;
2707         default:
2708                 break;
2709         }
2710
2711         /*
2712          * We don't need to see this warning, it means that kernel code
2713          * missing ib_pd. Placed here to catch developer's mistakes.
2714          */
2715         WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2716                   "There is a missing PD pointer assignment\n");
2717         return 0;
2718 }
2719
2720 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2721                                 struct ib_qp_init_attr *verbs_init_attr,
2722                                 struct ib_udata *udata)
2723 {
2724         struct mlx5_ib_dev *dev;
2725         struct mlx5_ib_qp *qp;
2726         u16 xrcdn = 0;
2727         int err;
2728         struct ib_qp_init_attr mlx_init_attr;
2729         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2730
2731         dev = pd ? to_mdev(pd->device) :
2732                    to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2733
2734         err = check_qp_type(dev, init_attr);
2735         if (err) {
2736                 mlx5_ib_dbg(dev, "Unsupported QP type %d\n",
2737                             init_attr->qp_type);
2738                 return ERR_PTR(err);
2739         }
2740
2741         err = check_valid_flow(dev, pd, init_attr, udata);
2742         if (err)
2743                 return ERR_PTR(err);
2744
2745         if (init_attr->qp_type == IB_QPT_GSI)
2746                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2747
2748         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2749         if (!qp)
2750                 return ERR_PTR(-ENOMEM);
2751
2752         if (init_attr->qp_type == IB_QPT_DRIVER) {
2753                 struct mlx5_ib_create_qp ucmd;
2754
2755                 init_attr = &mlx_init_attr;
2756                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2757                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2758                 if (err)
2759                         goto free_qp;
2760
2761                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2762                         if (init_attr->cap.max_recv_wr ||
2763                             init_attr->cap.max_recv_sge) {
2764                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2765                                 err = -EINVAL;
2766                                 goto free_qp;
2767                         }
2768                 } else {
2769                         return mlx5_ib_create_dct(pd, qp, init_attr, &ucmd,
2770                                                   udata);
2771                 }
2772         }
2773
2774         if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2775                 init_attr->recv_cq = NULL;
2776                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2777                 init_attr->send_cq = NULL;
2778         }
2779
2780         if (init_attr->qp_type == IB_QPT_XRC_INI)
2781                 init_attr->recv_cq = NULL;
2782
2783         err = create_qp_common(dev, pd, init_attr, udata, qp);
2784         if (err) {
2785                 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2786                 goto free_qp;
2787         }
2788
2789         if (is_qp0(init_attr->qp_type))
2790                 qp->ibqp.qp_num = 0;
2791         else if (is_qp1(init_attr->qp_type))
2792                 qp->ibqp.qp_num = 1;
2793         else
2794                 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2795
2796         qp->trans_qp.xrcdn = xrcdn;
2797
2798         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2799                 qp->qp_sub_type = init_attr->qp_type;
2800
2801         return &qp->ibqp;
2802
2803 free_qp:
2804         kfree(qp);
2805         return ERR_PTR(err);
2806 }
2807
2808 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2809 {
2810         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2811
2812         if (mqp->state == IB_QPS_RTR) {
2813                 int err;
2814
2815                 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2816                 if (err) {
2817                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2818                         return err;
2819                 }
2820         }
2821
2822         kfree(mqp->dct.in);
2823         kfree(mqp);
2824         return 0;
2825 }
2826
2827 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
2828 {
2829         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2830         struct mlx5_ib_qp *mqp = to_mqp(qp);
2831
2832         if (unlikely(qp->qp_type == IB_QPT_GSI))
2833                 return mlx5_ib_gsi_destroy_qp(qp);
2834
2835         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2836                 return mlx5_ib_destroy_dct(mqp);
2837
2838         destroy_qp_common(dev, mqp, udata);
2839
2840         kfree(mqp);
2841
2842         return 0;
2843 }
2844
2845 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2846                                 const struct ib_qp_attr *attr,
2847                                 int attr_mask, __be32 *hw_access_flags_be)
2848 {
2849         u8 dest_rd_atomic;
2850         u32 access_flags, hw_access_flags = 0;
2851
2852         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2853
2854         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2855                 dest_rd_atomic = attr->max_dest_rd_atomic;
2856         else
2857                 dest_rd_atomic = qp->trans_qp.resp_depth;
2858
2859         if (attr_mask & IB_QP_ACCESS_FLAGS)
2860                 access_flags = attr->qp_access_flags;
2861         else
2862                 access_flags = qp->trans_qp.atomic_rd_en;
2863
2864         if (!dest_rd_atomic)
2865                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2866
2867         if (access_flags & IB_ACCESS_REMOTE_READ)
2868                 hw_access_flags |= MLX5_QP_BIT_RRE;
2869         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2870                 int atomic_mode;
2871
2872                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2873                 if (atomic_mode < 0)
2874                         return -EOPNOTSUPP;
2875
2876                 hw_access_flags |= MLX5_QP_BIT_RAE;
2877                 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2878         }
2879
2880         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2881                 hw_access_flags |= MLX5_QP_BIT_RWE;
2882
2883         *hw_access_flags_be = cpu_to_be32(hw_access_flags);
2884
2885         return 0;
2886 }
2887
2888 enum {
2889         MLX5_PATH_FLAG_FL       = 1 << 0,
2890         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2891         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2892 };
2893
2894 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2895 {
2896         if (rate == IB_RATE_PORT_CURRENT)
2897                 return 0;
2898
2899         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
2900                 return -EINVAL;
2901
2902         while (rate != IB_RATE_PORT_CURRENT &&
2903                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2904                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2905                 --rate;
2906
2907         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2908 }
2909
2910 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2911                                       struct mlx5_ib_sq *sq, u8 sl,
2912                                       struct ib_pd *pd)
2913 {
2914         void *in;
2915         void *tisc;
2916         int inlen;
2917         int err;
2918
2919         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2920         in = kvzalloc(inlen, GFP_KERNEL);
2921         if (!in)
2922                 return -ENOMEM;
2923
2924         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2925         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2926
2927         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2928         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2929
2930         err = mlx5_core_modify_tis(dev, sq->tisn, in);
2931
2932         kvfree(in);
2933
2934         return err;
2935 }
2936
2937 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2938                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2939                                          struct ib_pd *pd)
2940 {
2941         void *in;
2942         void *tisc;
2943         int inlen;
2944         int err;
2945
2946         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2947         in = kvzalloc(inlen, GFP_KERNEL);
2948         if (!in)
2949                 return -ENOMEM;
2950
2951         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2952         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2953
2954         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2955         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2956
2957         err = mlx5_core_modify_tis(dev, sq->tisn, in);
2958
2959         kvfree(in);
2960
2961         return err;
2962 }
2963
2964 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2965                          const struct rdma_ah_attr *ah,
2966                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2967                          u32 path_flags, const struct ib_qp_attr *attr,
2968                          bool alt)
2969 {
2970         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2971         int err;
2972         enum ib_gid_type gid_type;
2973         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2974         u8 sl = rdma_ah_get_sl(ah);
2975
2976         if (attr_mask & IB_QP_PKEY_INDEX)
2977                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2978                                                      attr->pkey_index);
2979
2980         if (ah_flags & IB_AH_GRH) {
2981                 if (grh->sgid_index >=
2982                     dev->mdev->port_caps[port - 1].gid_table_len) {
2983                         pr_err("sgid_index (%u) too large. max is %d\n",
2984                                grh->sgid_index,
2985                                dev->mdev->port_caps[port - 1].gid_table_len);
2986                         return -EINVAL;
2987                 }
2988         }
2989
2990         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2991                 if (!(ah_flags & IB_AH_GRH))
2992                         return -EINVAL;
2993
2994                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2995                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2996                     qp->ibqp.qp_type == IB_QPT_UC ||
2997                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2998                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2999                         path->udp_sport =
3000                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
3001                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
3002                 gid_type = ah->grh.sgid_attr->gid_type;
3003                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3004                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
3005         } else {
3006                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
3007                 path->fl_free_ar |=
3008                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
3009                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
3010                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
3011                 if (ah_flags & IB_AH_GRH)
3012                         path->grh_mlid  |= 1 << 7;
3013                 path->dci_cfi_prio_sl = sl & 0xf;
3014         }
3015
3016         if (ah_flags & IB_AH_GRH) {
3017                 path->mgid_index = grh->sgid_index;
3018                 path->hop_limit  = grh->hop_limit;
3019                 path->tclass_flowlabel =
3020                         cpu_to_be32((grh->traffic_class << 20) |
3021                                     (grh->flow_label));
3022                 memcpy(path->rgid, grh->dgid.raw, 16);
3023         }
3024
3025         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
3026         if (err < 0)
3027                 return err;
3028         path->static_rate = err;
3029         path->port = port;
3030
3031         if (attr_mask & IB_QP_TIMEOUT)
3032                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
3033
3034         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3035                 return modify_raw_packet_eth_prio(dev->mdev,
3036                                                   &qp->raw_packet_qp.sq,
3037                                                   sl & 0xf, qp->ibqp.pd);
3038
3039         return 0;
3040 }
3041
3042 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3043         [MLX5_QP_STATE_INIT] = {
3044                 [MLX5_QP_STATE_INIT] = {
3045                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3046                                           MLX5_QP_OPTPAR_RAE            |
3047                                           MLX5_QP_OPTPAR_RWE            |
3048                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3049                                           MLX5_QP_OPTPAR_PRI_PORT,
3050                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3051                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3052                                           MLX5_QP_OPTPAR_PRI_PORT,
3053                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3054                                           MLX5_QP_OPTPAR_Q_KEY          |
3055                                           MLX5_QP_OPTPAR_PRI_PORT,
3056                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3057                                           MLX5_QP_OPTPAR_RAE            |
3058                                           MLX5_QP_OPTPAR_RWE            |
3059                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3060                                           MLX5_QP_OPTPAR_PRI_PORT,
3061                 },
3062                 [MLX5_QP_STATE_RTR] = {
3063                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3064                                           MLX5_QP_OPTPAR_RRE            |
3065                                           MLX5_QP_OPTPAR_RAE            |
3066                                           MLX5_QP_OPTPAR_RWE            |
3067                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3068                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3069                                           MLX5_QP_OPTPAR_RWE            |
3070                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3071                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3072                                           MLX5_QP_OPTPAR_Q_KEY,
3073                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
3074                                            MLX5_QP_OPTPAR_Q_KEY,
3075                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3076                                           MLX5_QP_OPTPAR_RRE            |
3077                                           MLX5_QP_OPTPAR_RAE            |
3078                                           MLX5_QP_OPTPAR_RWE            |
3079                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3080                 },
3081         },
3082         [MLX5_QP_STATE_RTR] = {
3083                 [MLX5_QP_STATE_RTS] = {
3084                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3085                                           MLX5_QP_OPTPAR_RRE            |
3086                                           MLX5_QP_OPTPAR_RAE            |
3087                                           MLX5_QP_OPTPAR_RWE            |
3088                                           MLX5_QP_OPTPAR_PM_STATE       |
3089                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3090                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3091                                           MLX5_QP_OPTPAR_RWE            |
3092                                           MLX5_QP_OPTPAR_PM_STATE,
3093                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3094                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3095                                           MLX5_QP_OPTPAR_RRE            |
3096                                           MLX5_QP_OPTPAR_RAE            |
3097                                           MLX5_QP_OPTPAR_RWE            |
3098                                           MLX5_QP_OPTPAR_PM_STATE       |
3099                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3100                 },
3101         },
3102         [MLX5_QP_STATE_RTS] = {
3103                 [MLX5_QP_STATE_RTS] = {
3104                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3105                                           MLX5_QP_OPTPAR_RAE            |
3106                                           MLX5_QP_OPTPAR_RWE            |
3107                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3108                                           MLX5_QP_OPTPAR_PM_STATE       |
3109                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3110                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3111                                           MLX5_QP_OPTPAR_PM_STATE       |
3112                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3113                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3114                                           MLX5_QP_OPTPAR_SRQN           |
3115                                           MLX5_QP_OPTPAR_CQN_RCV,
3116                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3117                                           MLX5_QP_OPTPAR_RAE            |
3118                                           MLX5_QP_OPTPAR_RWE            |
3119                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3120                                           MLX5_QP_OPTPAR_PM_STATE       |
3121                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3122                 },
3123         },
3124         [MLX5_QP_STATE_SQER] = {
3125                 [MLX5_QP_STATE_RTS] = {
3126                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3127                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3128                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3129                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3130                                            MLX5_QP_OPTPAR_RWE           |
3131                                            MLX5_QP_OPTPAR_RAE           |
3132                                            MLX5_QP_OPTPAR_RRE,
3133                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
3134                                            MLX5_QP_OPTPAR_RWE           |
3135                                            MLX5_QP_OPTPAR_RAE           |
3136                                            MLX5_QP_OPTPAR_RRE,
3137                 },
3138         },
3139 };
3140
3141 static int ib_nr_to_mlx5_nr(int ib_mask)
3142 {
3143         switch (ib_mask) {
3144         case IB_QP_STATE:
3145                 return 0;
3146         case IB_QP_CUR_STATE:
3147                 return 0;
3148         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3149                 return 0;
3150         case IB_QP_ACCESS_FLAGS:
3151                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3152                         MLX5_QP_OPTPAR_RAE;
3153         case IB_QP_PKEY_INDEX:
3154                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3155         case IB_QP_PORT:
3156                 return MLX5_QP_OPTPAR_PRI_PORT;
3157         case IB_QP_QKEY:
3158                 return MLX5_QP_OPTPAR_Q_KEY;
3159         case IB_QP_AV:
3160                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3161                         MLX5_QP_OPTPAR_PRI_PORT;
3162         case IB_QP_PATH_MTU:
3163                 return 0;
3164         case IB_QP_TIMEOUT:
3165                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3166         case IB_QP_RETRY_CNT:
3167                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3168         case IB_QP_RNR_RETRY:
3169                 return MLX5_QP_OPTPAR_RNR_RETRY;
3170         case IB_QP_RQ_PSN:
3171                 return 0;
3172         case IB_QP_MAX_QP_RD_ATOMIC:
3173                 return MLX5_QP_OPTPAR_SRA_MAX;
3174         case IB_QP_ALT_PATH:
3175                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3176         case IB_QP_MIN_RNR_TIMER:
3177                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3178         case IB_QP_SQ_PSN:
3179                 return 0;
3180         case IB_QP_MAX_DEST_RD_ATOMIC:
3181                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3182                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3183         case IB_QP_PATH_MIG_STATE:
3184                 return MLX5_QP_OPTPAR_PM_STATE;
3185         case IB_QP_CAP:
3186                 return 0;
3187         case IB_QP_DEST_QPN:
3188                 return 0;
3189         }
3190         return 0;
3191 }
3192
3193 static int ib_mask_to_mlx5_opt(int ib_mask)
3194 {
3195         int result = 0;
3196         int i;
3197
3198         for (i = 0; i < 8 * sizeof(int); i++) {
3199                 if ((1 << i) & ib_mask)
3200                         result |= ib_nr_to_mlx5_nr(1 << i);
3201         }
3202
3203         return result;
3204 }
3205
3206 static int modify_raw_packet_qp_rq(
3207         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3208         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3209 {
3210         void *in;
3211         void *rqc;
3212         int inlen;
3213         int err;
3214
3215         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3216         in = kvzalloc(inlen, GFP_KERNEL);
3217         if (!in)
3218                 return -ENOMEM;
3219
3220         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3221         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3222
3223         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3224         MLX5_SET(rqc, rqc, state, new_state);
3225
3226         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3227                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3228                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3229                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3230                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3231                 } else
3232                         dev_info_once(
3233                                 &dev->ib_dev.dev,
3234                                 "RAW PACKET QP counters are not supported on current FW\n");
3235         }
3236
3237         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3238         if (err)
3239                 goto out;
3240
3241         rq->state = new_state;
3242
3243 out:
3244         kvfree(in);
3245         return err;
3246 }
3247
3248 static int modify_raw_packet_qp_sq(
3249         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3250         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3251 {
3252         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3253         struct mlx5_rate_limit old_rl = ibqp->rl;
3254         struct mlx5_rate_limit new_rl = old_rl;
3255         bool new_rate_added = false;
3256         u16 rl_index = 0;
3257         void *in;
3258         void *sqc;
3259         int inlen;
3260         int err;
3261
3262         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3263         in = kvzalloc(inlen, GFP_KERNEL);
3264         if (!in)
3265                 return -ENOMEM;
3266
3267         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3268         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3269
3270         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3271         MLX5_SET(sqc, sqc, state, new_state);
3272
3273         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3274                 if (new_state != MLX5_SQC_STATE_RDY)
3275                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3276                                 __func__);
3277                 else
3278                         new_rl = raw_qp_param->rl;
3279         }
3280
3281         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3282                 if (new_rl.rate) {
3283                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3284                         if (err) {
3285                                 pr_err("Failed configuring rate limit(err %d): \
3286                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3287                                        err, new_rl.rate, new_rl.max_burst_sz,
3288                                        new_rl.typical_pkt_sz);
3289
3290                                 goto out;
3291                         }
3292                         new_rate_added = true;
3293                 }
3294
3295                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3296                 /* index 0 means no limit */
3297                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3298         }
3299
3300         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
3301         if (err) {
3302                 /* Remove new rate from table if failed */
3303                 if (new_rate_added)
3304                         mlx5_rl_remove_rate(dev, &new_rl);
3305                 goto out;
3306         }
3307
3308         /* Only remove the old rate after new rate was set */
3309         if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3310             (new_state != MLX5_SQC_STATE_RDY)) {
3311                 mlx5_rl_remove_rate(dev, &old_rl);
3312                 if (new_state != MLX5_SQC_STATE_RDY)
3313                         memset(&new_rl, 0, sizeof(new_rl));
3314         }
3315
3316         ibqp->rl = new_rl;
3317         sq->state = new_state;
3318
3319 out:
3320         kvfree(in);
3321         return err;
3322 }
3323
3324 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3325                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3326                                 u8 tx_affinity)
3327 {
3328         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3329         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3330         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3331         int modify_rq = !!qp->rq.wqe_cnt;
3332         int modify_sq = !!qp->sq.wqe_cnt;
3333         int rq_state;
3334         int sq_state;
3335         int err;
3336
3337         switch (raw_qp_param->operation) {
3338         case MLX5_CMD_OP_RST2INIT_QP:
3339                 rq_state = MLX5_RQC_STATE_RDY;
3340                 sq_state = MLX5_SQC_STATE_RDY;
3341                 break;
3342         case MLX5_CMD_OP_2ERR_QP:
3343                 rq_state = MLX5_RQC_STATE_ERR;
3344                 sq_state = MLX5_SQC_STATE_ERR;
3345                 break;
3346         case MLX5_CMD_OP_2RST_QP:
3347                 rq_state = MLX5_RQC_STATE_RST;
3348                 sq_state = MLX5_SQC_STATE_RST;
3349                 break;
3350         case MLX5_CMD_OP_RTR2RTS_QP:
3351         case MLX5_CMD_OP_RTS2RTS_QP:
3352                 if (raw_qp_param->set_mask ==
3353                     MLX5_RAW_QP_RATE_LIMIT) {
3354                         modify_rq = 0;
3355                         sq_state = sq->state;
3356                 } else {
3357                         return raw_qp_param->set_mask ? -EINVAL : 0;
3358                 }
3359                 break;
3360         case MLX5_CMD_OP_INIT2INIT_QP:
3361         case MLX5_CMD_OP_INIT2RTR_QP:
3362                 if (raw_qp_param->set_mask)
3363                         return -EINVAL;
3364                 else
3365                         return 0;
3366         default:
3367                 WARN_ON(1);
3368                 return -EINVAL;
3369         }
3370
3371         if (modify_rq) {
3372                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3373                                                qp->ibqp.pd);
3374                 if (err)
3375                         return err;
3376         }
3377
3378         if (modify_sq) {
3379                 struct mlx5_flow_handle *flow_rule;
3380
3381                 if (tx_affinity) {
3382                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3383                                                             tx_affinity,
3384                                                             qp->ibqp.pd);
3385                         if (err)
3386                                 return err;
3387                 }
3388
3389                 flow_rule = create_flow_rule_vport_sq(dev, sq,
3390                                                       raw_qp_param->port);
3391                 if (IS_ERR(flow_rule))
3392                         return PTR_ERR(flow_rule);
3393
3394                 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3395                                               raw_qp_param, qp->ibqp.pd);
3396                 if (err) {
3397                         if (flow_rule)
3398                                 mlx5_del_flow_rules(flow_rule);
3399                         return err;
3400                 }
3401
3402                 if (flow_rule) {
3403                         destroy_flow_rule_vport_sq(sq);
3404                         sq->flow_rule = flow_rule;
3405                 }
3406
3407                 return err;
3408         }
3409
3410         return 0;
3411 }
3412
3413 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3414                                     struct mlx5_ib_pd *pd,
3415                                     struct mlx5_ib_qp_base *qp_base,
3416                                     u8 port_num, struct ib_udata *udata)
3417 {
3418         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3419                 udata, struct mlx5_ib_ucontext, ibucontext);
3420         unsigned int tx_port_affinity;
3421
3422         if (ucontext) {
3423                 tx_port_affinity = (unsigned int)atomic_add_return(
3424                                            1, &ucontext->tx_port_affinity) %
3425                                            MLX5_MAX_PORTS +
3426                                    1;
3427                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3428                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3429         } else {
3430                 tx_port_affinity =
3431                         (unsigned int)atomic_add_return(
3432                                 1, &dev->port[port_num].roce.tx_port_affinity) %
3433                                 MLX5_MAX_PORTS +
3434                         1;
3435                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3436                                 tx_port_affinity, qp_base->mqp.qpn);
3437         }
3438
3439         return tx_port_affinity;
3440 }
3441
3442 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3443                                     struct rdma_counter *counter)
3444 {
3445         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3446         struct mlx5_ib_qp *mqp = to_mqp(qp);
3447         struct mlx5_qp_context context = {};
3448         struct mlx5_ib_qp_base *base;
3449         u32 set_id;
3450
3451         if (counter)
3452                 set_id = counter->id;
3453         else
3454                 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3455
3456         base = &mqp->trans_qp.base;
3457         context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff);
3458         context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24);
3459         return mlx5_core_qp_modify(dev, MLX5_CMD_OP_RTS2RTS_QP,
3460                                    MLX5_QP_OPTPAR_COUNTER_SET_ID, &context,
3461                                    &base->mqp);
3462 }
3463
3464 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3465                                const struct ib_qp_attr *attr, int attr_mask,
3466                                enum ib_qp_state cur_state,
3467                                enum ib_qp_state new_state,
3468                                const struct mlx5_ib_modify_qp *ucmd,
3469                                struct ib_udata *udata)
3470 {
3471         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3472                 [MLX5_QP_STATE_RST] = {
3473                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3474                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3475                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3476                 },
3477                 [MLX5_QP_STATE_INIT]  = {
3478                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3479                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3480                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3481                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3482                 },
3483                 [MLX5_QP_STATE_RTR]   = {
3484                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3485                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3486                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3487                 },
3488                 [MLX5_QP_STATE_RTS]   = {
3489                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3490                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3491                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3492                 },
3493                 [MLX5_QP_STATE_SQD] = {
3494                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3495                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3496                 },
3497                 [MLX5_QP_STATE_SQER] = {
3498                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3499                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3500                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3501                 },
3502                 [MLX5_QP_STATE_ERR] = {
3503                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3504                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3505                 }
3506         };
3507
3508         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3509         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3510         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3511         struct mlx5_ib_cq *send_cq, *recv_cq;
3512         struct mlx5_qp_context *context;
3513         struct mlx5_ib_pd *pd;
3514         enum mlx5_qp_state mlx5_cur, mlx5_new;
3515         enum mlx5_qp_optpar optpar;
3516         u32 set_id = 0;
3517         int mlx5_st;
3518         int err;
3519         u16 op;
3520         u8 tx_affinity = 0;
3521
3522         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3523                              qp->qp_sub_type : ibqp->qp_type);
3524         if (mlx5_st < 0)
3525                 return -EINVAL;
3526
3527         context = kzalloc(sizeof(*context), GFP_KERNEL);
3528         if (!context)
3529                 return -ENOMEM;
3530
3531         pd = get_pd(qp);
3532         context->flags = cpu_to_be32(mlx5_st << 16);
3533
3534         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3535                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3536         } else {
3537                 switch (attr->path_mig_state) {
3538                 case IB_MIG_MIGRATED:
3539                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3540                         break;
3541                 case IB_MIG_REARM:
3542                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3543                         break;
3544                 case IB_MIG_ARMED:
3545                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3546                         break;
3547                 }
3548         }
3549
3550         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3551                 if ((ibqp->qp_type == IB_QPT_RC) ||
3552                     (ibqp->qp_type == IB_QPT_UD &&
3553                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3554                     (ibqp->qp_type == IB_QPT_UC) ||
3555                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3556                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3557                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3558                         if (dev->lag_active) {
3559                                 u8 p = mlx5_core_native_port_num(dev->mdev) - 1;
3560                                 tx_affinity = get_tx_affinity(dev, pd, base, p,
3561                                                               udata);
3562                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3563                         }
3564                 }
3565         }
3566
3567         if (is_sqp(ibqp->qp_type)) {
3568                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3569         } else if ((ibqp->qp_type == IB_QPT_UD &&
3570                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3571                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3572                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3573         } else if (attr_mask & IB_QP_PATH_MTU) {
3574                 if (attr->path_mtu < IB_MTU_256 ||
3575                     attr->path_mtu > IB_MTU_4096) {
3576                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3577                         err = -EINVAL;
3578                         goto out;
3579                 }
3580                 context->mtu_msgmax = (attr->path_mtu << 5) |
3581                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3582         }
3583
3584         if (attr_mask & IB_QP_DEST_QPN)
3585                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3586
3587         if (attr_mask & IB_QP_PKEY_INDEX)
3588                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3589
3590         /* todo implement counter_index functionality */
3591
3592         if (is_sqp(ibqp->qp_type))
3593                 context->pri_path.port = qp->port;
3594
3595         if (attr_mask & IB_QP_PORT)
3596                 context->pri_path.port = attr->port_num;
3597
3598         if (attr_mask & IB_QP_AV) {
3599                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3600                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3601                                     attr_mask, 0, attr, false);
3602                 if (err)
3603                         goto out;
3604         }
3605
3606         if (attr_mask & IB_QP_TIMEOUT)
3607                 context->pri_path.ackto_lt |= attr->timeout << 3;
3608
3609         if (attr_mask & IB_QP_ALT_PATH) {
3610                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3611                                     &context->alt_path,
3612                                     attr->alt_port_num,
3613                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3614                                     0, attr, true);
3615                 if (err)
3616                         goto out;
3617         }
3618
3619         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3620                 &send_cq, &recv_cq);
3621
3622         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3623         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3624         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3625         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3626
3627         if (attr_mask & IB_QP_RNR_RETRY)
3628                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3629
3630         if (attr_mask & IB_QP_RETRY_CNT)
3631                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3632
3633         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3634                 if (attr->max_rd_atomic)
3635                         context->params1 |=
3636                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3637         }
3638
3639         if (attr_mask & IB_QP_SQ_PSN)
3640                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3641
3642         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3643                 if (attr->max_dest_rd_atomic)
3644                         context->params2 |=
3645                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3646         }
3647
3648         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3649                 __be32 access_flags;
3650
3651                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3652                 if (err)
3653                         goto out;
3654
3655                 context->params2 |= access_flags;
3656         }
3657
3658         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3659                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3660
3661         if (attr_mask & IB_QP_RQ_PSN)
3662                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3663
3664         if (attr_mask & IB_QP_QKEY)
3665                 context->qkey = cpu_to_be32(attr->qkey);
3666
3667         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3668                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3669
3670         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3671                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3672                                qp->port) - 1;
3673
3674                 /* Underlay port should be used - index 0 function per port */
3675                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3676                         port_num = 0;
3677
3678                 if (ibqp->counter)
3679                         set_id = ibqp->counter->id;
3680                 else
3681                         set_id = mlx5_ib_get_counters_id(dev, port_num);
3682                 context->qp_counter_set_usr_page |=
3683                         cpu_to_be32(set_id << 24);
3684         }
3685
3686         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3687                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3688
3689         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3690                 context->deth_sqpn = cpu_to_be32(1);
3691
3692         mlx5_cur = to_mlx5_state(cur_state);
3693         mlx5_new = to_mlx5_state(new_state);
3694
3695         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3696             !optab[mlx5_cur][mlx5_new]) {
3697                 err = -EINVAL;
3698                 goto out;
3699         }
3700
3701         op = optab[mlx5_cur][mlx5_new];
3702         optpar = ib_mask_to_mlx5_opt(attr_mask);
3703         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3704
3705         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3706             qp->flags & MLX5_IB_QP_UNDERLAY) {
3707                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3708
3709                 raw_qp_param.operation = op;
3710                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3711                         raw_qp_param.rq_q_ctr_id = set_id;
3712                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3713                 }
3714
3715                 if (attr_mask & IB_QP_PORT)
3716                         raw_qp_param.port = attr->port_num;
3717
3718                 if (attr_mask & IB_QP_RATE_LIMIT) {
3719                         raw_qp_param.rl.rate = attr->rate_limit;
3720
3721                         if (ucmd->burst_info.max_burst_sz) {
3722                                 if (attr->rate_limit &&
3723                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3724                                         raw_qp_param.rl.max_burst_sz =
3725                                                 ucmd->burst_info.max_burst_sz;
3726                                 } else {
3727                                         err = -EINVAL;
3728                                         goto out;
3729                                 }
3730                         }
3731
3732                         if (ucmd->burst_info.typical_pkt_sz) {
3733                                 if (attr->rate_limit &&
3734                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3735                                         raw_qp_param.rl.typical_pkt_sz =
3736                                                 ucmd->burst_info.typical_pkt_sz;
3737                                 } else {
3738                                         err = -EINVAL;
3739                                         goto out;
3740                                 }
3741                         }
3742
3743                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3744                 }
3745
3746                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3747         } else {
3748                 err = mlx5_core_qp_modify(dev, op, optpar, context, &base->mqp);
3749         }
3750
3751         if (err)
3752                 goto out;
3753
3754         qp->state = new_state;
3755
3756         if (attr_mask & IB_QP_ACCESS_FLAGS)
3757                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3758         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3759                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3760         if (attr_mask & IB_QP_PORT)
3761                 qp->port = attr->port_num;
3762         if (attr_mask & IB_QP_ALT_PATH)
3763                 qp->trans_qp.alt_port = attr->alt_port_num;
3764
3765         /*
3766          * If we moved a kernel QP to RESET, clean up all old CQ
3767          * entries and reinitialize the QP.
3768          */
3769         if (new_state == IB_QPS_RESET &&
3770             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3771                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3772                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3773                 if (send_cq != recv_cq)
3774                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3775
3776                 qp->rq.head = 0;
3777                 qp->rq.tail = 0;
3778                 qp->sq.head = 0;
3779                 qp->sq.tail = 0;
3780                 qp->sq.cur_post = 0;
3781                 if (qp->sq.wqe_cnt)
3782                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3783                 qp->sq.last_poll = 0;
3784                 qp->db.db[MLX5_RCV_DBR] = 0;
3785                 qp->db.db[MLX5_SND_DBR] = 0;
3786         }
3787
3788         if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
3789                 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
3790                 if (!err)
3791                         qp->counter_pending = 0;
3792         }
3793
3794 out:
3795         kfree(context);
3796         return err;
3797 }
3798
3799 static inline bool is_valid_mask(int mask, int req, int opt)
3800 {
3801         if ((mask & req) != req)
3802                 return false;
3803
3804         if (mask & ~(req | opt))
3805                 return false;
3806
3807         return true;
3808 }
3809
3810 /* check valid transition for driver QP types
3811  * for now the only QP type that this function supports is DCI
3812  */
3813 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3814                                 enum ib_qp_attr_mask attr_mask)
3815 {
3816         int req = IB_QP_STATE;
3817         int opt = 0;
3818
3819         if (new_state == IB_QPS_RESET) {
3820                 return is_valid_mask(attr_mask, req, opt);
3821         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3822                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3823                 return is_valid_mask(attr_mask, req, opt);
3824         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3825                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3826                 return is_valid_mask(attr_mask, req, opt);
3827         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3828                 req |= IB_QP_PATH_MTU;
3829                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3830                 return is_valid_mask(attr_mask, req, opt);
3831         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3832                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3833                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3834                 opt = IB_QP_MIN_RNR_TIMER;
3835                 return is_valid_mask(attr_mask, req, opt);
3836         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3837                 opt = IB_QP_MIN_RNR_TIMER;
3838                 return is_valid_mask(attr_mask, req, opt);
3839         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3840                 return is_valid_mask(attr_mask, req, opt);
3841         }
3842         return false;
3843 }
3844
3845 /* mlx5_ib_modify_dct: modify a DCT QP
3846  * valid transitions are:
3847  * RESET to INIT: must set access_flags, pkey_index and port
3848  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3849  *                         mtu, gid_index and hop_limit
3850  * Other transitions and attributes are illegal
3851  */
3852 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3853                               int attr_mask, struct ib_udata *udata)
3854 {
3855         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3856         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3857         enum ib_qp_state cur_state, new_state;
3858         int err = 0;
3859         int required = IB_QP_STATE;
3860         void *dctc;
3861
3862         if (!(attr_mask & IB_QP_STATE))
3863                 return -EINVAL;
3864
3865         cur_state = qp->state;
3866         new_state = attr->qp_state;
3867
3868         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3869         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3870                 u16 set_id;
3871
3872                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3873                 if (!is_valid_mask(attr_mask, required, 0))
3874                         return -EINVAL;
3875
3876                 if (attr->port_num == 0 ||
3877                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3878                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3879                                     attr->port_num, dev->num_ports);
3880                         return -EINVAL;
3881                 }
3882                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3883                         MLX5_SET(dctc, dctc, rre, 1);
3884                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3885                         MLX5_SET(dctc, dctc, rwe, 1);
3886                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3887                         int atomic_mode;
3888
3889                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3890                         if (atomic_mode < 0)
3891                                 return -EOPNOTSUPP;
3892
3893                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3894                         MLX5_SET(dctc, dctc, rae, 1);
3895                 }
3896                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3897                 MLX5_SET(dctc, dctc, port, attr->port_num);
3898
3899                 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
3900                 MLX5_SET(dctc, dctc, counter_set_id, set_id);
3901
3902         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3903                 struct mlx5_ib_modify_qp_resp resp = {};
3904                 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
3905                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3906                                    sizeof(resp.dctn);
3907
3908                 if (udata->outlen < min_resp_len)
3909                         return -EINVAL;
3910                 resp.response_length = min_resp_len;
3911
3912                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3913                 if (!is_valid_mask(attr_mask, required, 0))
3914                         return -EINVAL;
3915                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3916                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3917                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3918                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3919                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3920                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3921
3922                 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
3923                                            MLX5_ST_SZ_BYTES(create_dct_in), out,
3924                                            sizeof(out));
3925                 if (err)
3926                         return err;
3927                 resp.dctn = qp->dct.mdct.mqp.qpn;
3928                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3929                 if (err) {
3930                         mlx5_core_destroy_dct(dev, &qp->dct.mdct);
3931                         return err;
3932                 }
3933         } else {
3934                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3935                 return -EINVAL;
3936         }
3937         if (err)
3938                 qp->state = IB_QPS_ERR;
3939         else
3940                 qp->state = new_state;
3941         return err;
3942 }
3943
3944 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3945                       int attr_mask, struct ib_udata *udata)
3946 {
3947         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3948         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3949         struct mlx5_ib_modify_qp ucmd = {};
3950         enum ib_qp_type qp_type;
3951         enum ib_qp_state cur_state, new_state;
3952         size_t required_cmd_sz;
3953         int err = -EINVAL;
3954         int port;
3955
3956         if (ibqp->rwq_ind_tbl)
3957                 return -ENOSYS;
3958
3959         if (udata && udata->inlen) {
3960                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3961                         sizeof(ucmd.reserved);
3962                 if (udata->inlen < required_cmd_sz)
3963                         return -EINVAL;
3964
3965                 if (udata->inlen > sizeof(ucmd) &&
3966                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3967                                          udata->inlen - sizeof(ucmd)))
3968                         return -EOPNOTSUPP;
3969
3970                 if (ib_copy_from_udata(&ucmd, udata,
3971                                        min(udata->inlen, sizeof(ucmd))))
3972                         return -EFAULT;
3973
3974                 if (ucmd.comp_mask ||
3975                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3976                     memchr_inv(&ucmd.burst_info.reserved, 0,
3977                                sizeof(ucmd.burst_info.reserved)))
3978                         return -EOPNOTSUPP;
3979         }
3980
3981         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3982                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3983
3984         if (ibqp->qp_type == IB_QPT_DRIVER)
3985                 qp_type = qp->qp_sub_type;
3986         else
3987                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3988                         IB_QPT_GSI : ibqp->qp_type;
3989
3990         if (qp_type == MLX5_IB_QPT_DCT)
3991                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3992
3993         mutex_lock(&qp->mutex);
3994
3995         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3996         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3997
3998         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3999                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4000         }
4001
4002         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
4003                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4004                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4005                                     attr_mask);
4006                         goto out;
4007                 }
4008         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
4009                    qp_type != MLX5_IB_QPT_DCI &&
4010                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4011                                        attr_mask)) {
4012                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4013                             cur_state, new_state, ibqp->qp_type, attr_mask);
4014                 goto out;
4015         } else if (qp_type == MLX5_IB_QPT_DCI &&
4016                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4017                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4018                             cur_state, new_state, qp_type, attr_mask);
4019                 goto out;
4020         }
4021
4022         if ((attr_mask & IB_QP_PORT) &&
4023             (attr->port_num == 0 ||
4024              attr->port_num > dev->num_ports)) {
4025                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4026                             attr->port_num, dev->num_ports);
4027                 goto out;
4028         }
4029
4030         if (attr_mask & IB_QP_PKEY_INDEX) {
4031                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4032                 if (attr->pkey_index >=
4033                     dev->mdev->port_caps[port - 1].pkey_table_len) {
4034                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4035                                     attr->pkey_index);
4036                         goto out;
4037                 }
4038         }
4039
4040         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
4041             attr->max_rd_atomic >
4042             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4043                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4044                             attr->max_rd_atomic);
4045                 goto out;
4046         }
4047
4048         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
4049             attr->max_dest_rd_atomic >
4050             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4051                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4052                             attr->max_dest_rd_atomic);
4053                 goto out;
4054         }
4055
4056         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4057                 err = 0;
4058                 goto out;
4059         }
4060
4061         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4062                                   new_state, &ucmd, udata);
4063
4064 out:
4065         mutex_unlock(&qp->mutex);
4066         return err;
4067 }
4068
4069 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4070                                    u32 wqe_sz, void **cur_edge)
4071 {
4072         u32 idx;
4073
4074         idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
4075         *cur_edge = get_sq_edge(sq, idx);
4076
4077         *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
4078 }
4079
4080 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
4081  * next nearby edge and get new address translation for current WQE position.
4082  * @sq - SQ buffer.
4083  * @seg: Current WQE position (16B aligned).
4084  * @wqe_sz: Total current WQE size [16B].
4085  * @cur_edge: Updated current edge.
4086  */
4087 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4088                                          u32 wqe_sz, void **cur_edge)
4089 {
4090         if (likely(*seg != *cur_edge))
4091                 return;
4092
4093         _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
4094 }
4095
4096 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
4097  * pointers. At the end @seg is aligned to 16B regardless the copied size.
4098  * @sq - SQ buffer.
4099  * @cur_edge: Updated current edge.
4100  * @seg: Current WQE position (16B aligned).
4101  * @wqe_sz: Total current WQE size [16B].
4102  * @src: Pointer to copy from.
4103  * @n: Number of bytes to copy.
4104  */
4105 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
4106                                    void **seg, u32 *wqe_sz, const void *src,
4107                                    size_t n)
4108 {
4109         while (likely(n)) {
4110                 size_t leftlen = *cur_edge - *seg;
4111                 size_t copysz = min_t(size_t, leftlen, n);
4112                 size_t stride;
4113
4114                 memcpy(*seg, src, copysz);
4115
4116                 n -= copysz;
4117                 src += copysz;
4118                 stride = !n ? ALIGN(copysz, 16) : copysz;
4119                 *seg += stride;
4120                 *wqe_sz += stride >> 4;
4121                 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
4122         }
4123 }
4124
4125 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
4126 {
4127         struct mlx5_ib_cq *cq;
4128         unsigned cur;
4129
4130         cur = wq->head - wq->tail;
4131         if (likely(cur + nreq < wq->max_post))
4132                 return 0;
4133
4134         cq = to_mcq(ib_cq);
4135         spin_lock(&cq->lock);
4136         cur = wq->head - wq->tail;
4137         spin_unlock(&cq->lock);
4138
4139         return cur + nreq >= wq->max_post;
4140 }
4141
4142 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
4143                                           u64 remote_addr, u32 rkey)
4144 {
4145         rseg->raddr    = cpu_to_be64(remote_addr);
4146         rseg->rkey     = cpu_to_be32(rkey);
4147         rseg->reserved = 0;
4148 }
4149
4150 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
4151                         void **seg, int *size, void **cur_edge)
4152 {
4153         struct mlx5_wqe_eth_seg *eseg = *seg;
4154
4155         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
4156
4157         if (wr->send_flags & IB_SEND_IP_CSUM)
4158                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
4159                                  MLX5_ETH_WQE_L4_CSUM;
4160
4161         if (wr->opcode == IB_WR_LSO) {
4162                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
4163                 size_t left, copysz;
4164                 void *pdata = ud_wr->header;
4165                 size_t stride;
4166
4167                 left = ud_wr->hlen;
4168                 eseg->mss = cpu_to_be16(ud_wr->mss);
4169                 eseg->inline_hdr.sz = cpu_to_be16(left);
4170
4171                 /* memcpy_send_wqe should get a 16B align address. Hence, we
4172                  * first copy up to the current edge and then, if needed,
4173                  * fall-through to memcpy_send_wqe.
4174                  */
4175                 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
4176                                left);
4177                 memcpy(eseg->inline_hdr.start, pdata, copysz);
4178                 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
4179                                sizeof(eseg->inline_hdr.start) + copysz, 16);
4180                 *size += stride / 16;
4181                 *seg += stride;
4182
4183                 if (copysz < left) {
4184                         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4185                         left -= copysz;
4186                         pdata += copysz;
4187                         memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4188                                         left);
4189                 }
4190
4191                 return;
4192         }
4193
4194         *seg += sizeof(struct mlx5_wqe_eth_seg);
4195         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
4196 }
4197
4198 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
4199                              const struct ib_send_wr *wr)
4200 {
4201         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4202         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4203         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
4204 }
4205
4206 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4207 {
4208         dseg->byte_count = cpu_to_be32(sg->length);
4209         dseg->lkey       = cpu_to_be32(sg->lkey);
4210         dseg->addr       = cpu_to_be64(sg->addr);
4211 }
4212
4213 static u64 get_xlt_octo(u64 bytes)
4214 {
4215         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4216                MLX5_IB_UMR_OCTOWORD;
4217 }
4218
4219 static __be64 frwr_mkey_mask(bool atomic)
4220 {
4221         u64 result;
4222
4223         result = MLX5_MKEY_MASK_LEN             |
4224                 MLX5_MKEY_MASK_PAGE_SIZE        |
4225                 MLX5_MKEY_MASK_START_ADDR       |
4226                 MLX5_MKEY_MASK_EN_RINVAL        |
4227                 MLX5_MKEY_MASK_KEY              |
4228                 MLX5_MKEY_MASK_LR               |
4229                 MLX5_MKEY_MASK_LW               |
4230                 MLX5_MKEY_MASK_RR               |
4231                 MLX5_MKEY_MASK_RW               |
4232                 MLX5_MKEY_MASK_SMALL_FENCE      |
4233                 MLX5_MKEY_MASK_FREE;
4234
4235         if (atomic)
4236                 result |= MLX5_MKEY_MASK_A;
4237
4238         return cpu_to_be64(result);
4239 }
4240
4241 static __be64 sig_mkey_mask(void)
4242 {
4243         u64 result;
4244
4245         result = MLX5_MKEY_MASK_LEN             |
4246                 MLX5_MKEY_MASK_PAGE_SIZE        |
4247                 MLX5_MKEY_MASK_START_ADDR       |
4248                 MLX5_MKEY_MASK_EN_SIGERR        |
4249                 MLX5_MKEY_MASK_EN_RINVAL        |
4250                 MLX5_MKEY_MASK_KEY              |
4251                 MLX5_MKEY_MASK_LR               |
4252                 MLX5_MKEY_MASK_LW               |
4253                 MLX5_MKEY_MASK_RR               |
4254                 MLX5_MKEY_MASK_RW               |
4255                 MLX5_MKEY_MASK_SMALL_FENCE      |
4256                 MLX5_MKEY_MASK_FREE             |
4257                 MLX5_MKEY_MASK_BSF_EN;
4258
4259         return cpu_to_be64(result);
4260 }
4261
4262 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
4263                             struct mlx5_ib_mr *mr, u8 flags, bool atomic)
4264 {
4265         int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4266
4267         memset(umr, 0, sizeof(*umr));
4268
4269         umr->flags = flags;
4270         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4271         umr->mkey_mask = frwr_mkey_mask(atomic);
4272 }
4273
4274 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4275 {
4276         memset(umr, 0, sizeof(*umr));
4277         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4278         umr->flags = MLX5_UMR_INLINE;
4279 }
4280
4281 static __be64 get_umr_enable_mr_mask(void)
4282 {
4283         u64 result;
4284
4285         result = MLX5_MKEY_MASK_KEY |
4286                  MLX5_MKEY_MASK_FREE;
4287
4288         return cpu_to_be64(result);
4289 }
4290
4291 static __be64 get_umr_disable_mr_mask(void)
4292 {
4293         u64 result;
4294
4295         result = MLX5_MKEY_MASK_FREE;
4296
4297         return cpu_to_be64(result);
4298 }
4299
4300 static __be64 get_umr_update_translation_mask(void)
4301 {
4302         u64 result;
4303
4304         result = MLX5_MKEY_MASK_LEN |
4305                  MLX5_MKEY_MASK_PAGE_SIZE |
4306                  MLX5_MKEY_MASK_START_ADDR;
4307
4308         return cpu_to_be64(result);
4309 }
4310
4311 static __be64 get_umr_update_access_mask(int atomic)
4312 {
4313         u64 result;
4314
4315         result = MLX5_MKEY_MASK_LR |
4316                  MLX5_MKEY_MASK_LW |
4317                  MLX5_MKEY_MASK_RR |
4318                  MLX5_MKEY_MASK_RW;
4319
4320         if (atomic)
4321                 result |= MLX5_MKEY_MASK_A;
4322
4323         return cpu_to_be64(result);
4324 }
4325
4326 static __be64 get_umr_update_pd_mask(void)
4327 {
4328         u64 result;
4329
4330         result = MLX5_MKEY_MASK_PD;
4331
4332         return cpu_to_be64(result);
4333 }
4334
4335 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4336 {
4337         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4338              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4339             (mask & MLX5_MKEY_MASK_A &&
4340              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4341                 return -EPERM;
4342         return 0;
4343 }
4344
4345 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4346                                struct mlx5_wqe_umr_ctrl_seg *umr,
4347                                const struct ib_send_wr *wr, int atomic)
4348 {
4349         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4350
4351         memset(umr, 0, sizeof(*umr));
4352
4353         if (!umrwr->ignore_free_state) {
4354                 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4355                          /* fail if free */
4356                         umr->flags = MLX5_UMR_CHECK_FREE;
4357                 else
4358                         /* fail if not free */
4359                         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
4360         }
4361
4362         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4363         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4364                 u64 offset = get_xlt_octo(umrwr->offset);
4365
4366                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4367                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4368                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4369         }
4370         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4371                 umr->mkey_mask |= get_umr_update_translation_mask();
4372         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4373                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4374                 umr->mkey_mask |= get_umr_update_pd_mask();
4375         }
4376         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4377                 umr->mkey_mask |= get_umr_enable_mr_mask();
4378         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4379                 umr->mkey_mask |= get_umr_disable_mr_mask();
4380
4381         if (!wr->num_sge)
4382                 umr->flags |= MLX5_UMR_INLINE;
4383
4384         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4385 }
4386
4387 static u8 get_umr_flags(int acc)
4388 {
4389         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4390                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4391                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4392                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4393                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4394 }
4395
4396 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4397                              struct mlx5_ib_mr *mr,
4398                              u32 key, int access)
4399 {
4400         int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1;
4401
4402         memset(seg, 0, sizeof(*seg));
4403
4404         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4405                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4406         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4407                 /* KLMs take twice the size of MTTs */
4408                 ndescs *= 2;
4409
4410         seg->flags = get_umr_flags(access) | mr->access_mode;
4411         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4412         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4413         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4414         seg->len = cpu_to_be64(mr->ibmr.length);
4415         seg->xlt_oct_size = cpu_to_be32(ndescs);
4416 }
4417
4418 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4419 {
4420         memset(seg, 0, sizeof(*seg));
4421         seg->status = MLX5_MKEY_STATUS_FREE;
4422 }
4423
4424 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4425                                  const struct ib_send_wr *wr)
4426 {
4427         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4428
4429         memset(seg, 0, sizeof(*seg));
4430         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4431                 seg->status = MLX5_MKEY_STATUS_FREE;
4432
4433         seg->flags = convert_access(umrwr->access_flags);
4434         if (umrwr->pd)
4435                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4436         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4437             !umrwr->length)
4438                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4439
4440         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4441         seg->len = cpu_to_be64(umrwr->length);
4442         seg->log2_page_size = umrwr->page_shift;
4443         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4444                                        mlx5_mkey_variant(umrwr->mkey));
4445 }
4446
4447 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4448                              struct mlx5_ib_mr *mr,
4449                              struct mlx5_ib_pd *pd)
4450 {
4451         int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs);
4452
4453         dseg->addr = cpu_to_be64(mr->desc_map);
4454         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4455         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4456 }
4457
4458 static __be32 send_ieth(const struct ib_send_wr *wr)
4459 {
4460         switch (wr->opcode) {
4461         case IB_WR_SEND_WITH_IMM:
4462         case IB_WR_RDMA_WRITE_WITH_IMM:
4463                 return wr->ex.imm_data;
4464
4465         case IB_WR_SEND_WITH_INV:
4466                 return cpu_to_be32(wr->ex.invalidate_rkey);
4467
4468         default:
4469                 return 0;
4470         }
4471 }
4472
4473 static u8 calc_sig(void *wqe, int size)
4474 {
4475         u8 *p = wqe;
4476         u8 res = 0;
4477         int i;
4478
4479         for (i = 0; i < size; i++)
4480                 res ^= p[i];
4481
4482         return ~res;
4483 }
4484
4485 static u8 wq_sig(void *wqe)
4486 {
4487         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4488 }
4489
4490 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4491                             void **wqe, int *wqe_sz, void **cur_edge)
4492 {
4493         struct mlx5_wqe_inline_seg *seg;
4494         size_t offset;
4495         int inl = 0;
4496         int i;
4497
4498         seg = *wqe;
4499         *wqe += sizeof(*seg);
4500         offset = sizeof(*seg);
4501
4502         for (i = 0; i < wr->num_sge; i++) {
4503                 size_t len  = wr->sg_list[i].length;
4504                 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4505
4506                 inl += len;
4507
4508                 if (unlikely(inl > qp->max_inline_data))
4509                         return -ENOMEM;
4510
4511                 while (likely(len)) {
4512                         size_t leftlen;
4513                         size_t copysz;
4514
4515                         handle_post_send_edge(&qp->sq, wqe,
4516                                               *wqe_sz + (offset >> 4),
4517                                               cur_edge);
4518
4519                         leftlen = *cur_edge - *wqe;
4520                         copysz = min_t(size_t, leftlen, len);
4521
4522                         memcpy(*wqe, addr, copysz);
4523                         len -= copysz;
4524                         addr += copysz;
4525                         *wqe += copysz;
4526                         offset += copysz;
4527                 }
4528         }
4529
4530         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4531
4532         *wqe_sz +=  ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4533
4534         return 0;
4535 }
4536
4537 static u16 prot_field_size(enum ib_signature_type type)
4538 {
4539         switch (type) {
4540         case IB_SIG_TYPE_T10_DIF:
4541                 return MLX5_DIF_SIZE;
4542         default:
4543                 return 0;
4544         }
4545 }
4546
4547 static u8 bs_selector(int block_size)
4548 {
4549         switch (block_size) {
4550         case 512:           return 0x1;
4551         case 520:           return 0x2;
4552         case 4096:          return 0x3;
4553         case 4160:          return 0x4;
4554         case 1073741824:    return 0x5;
4555         default:            return 0;
4556         }
4557 }
4558
4559 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4560                               struct mlx5_bsf_inl *inl)
4561 {
4562         /* Valid inline section and allow BSF refresh */
4563         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4564                                        MLX5_BSF_REFRESH_DIF);
4565         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4566         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4567         /* repeating block */
4568         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4569         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4570                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4571
4572         if (domain->sig.dif.ref_remap)
4573                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4574
4575         if (domain->sig.dif.app_escape) {
4576                 if (domain->sig.dif.ref_escape)
4577                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4578                 else
4579                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4580         }
4581
4582         inl->dif_app_bitmask_check =
4583                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4584 }
4585
4586 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4587                         struct ib_sig_attrs *sig_attrs,
4588                         struct mlx5_bsf *bsf, u32 data_size)
4589 {
4590         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4591         struct mlx5_bsf_basic *basic = &bsf->basic;
4592         struct ib_sig_domain *mem = &sig_attrs->mem;
4593         struct ib_sig_domain *wire = &sig_attrs->wire;
4594
4595         memset(bsf, 0, sizeof(*bsf));
4596
4597         /* Basic + Extended + Inline */
4598         basic->bsf_size_sbs = 1 << 7;
4599         /* Input domain check byte mask */
4600         basic->check_byte_mask = sig_attrs->check_mask;
4601         basic->raw_data_size = cpu_to_be32(data_size);
4602
4603         /* Memory domain */
4604         switch (sig_attrs->mem.sig_type) {
4605         case IB_SIG_TYPE_NONE:
4606                 break;
4607         case IB_SIG_TYPE_T10_DIF:
4608                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4609                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4610                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4611                 break;
4612         default:
4613                 return -EINVAL;
4614         }
4615
4616         /* Wire domain */
4617         switch (sig_attrs->wire.sig_type) {
4618         case IB_SIG_TYPE_NONE:
4619                 break;
4620         case IB_SIG_TYPE_T10_DIF:
4621                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4622                     mem->sig_type == wire->sig_type) {
4623                         /* Same block structure */
4624                         basic->bsf_size_sbs |= 1 << 4;
4625                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4626                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4627                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4628                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4629                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4630                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4631                 } else
4632                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4633
4634                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4635                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4636                 break;
4637         default:
4638                 return -EINVAL;
4639         }
4640
4641         return 0;
4642 }
4643
4644 static int set_sig_data_segment(const struct ib_send_wr *send_wr,
4645                                 struct ib_mr *sig_mr,
4646                                 struct ib_sig_attrs *sig_attrs,
4647                                 struct mlx5_ib_qp *qp, void **seg, int *size,
4648                                 void **cur_edge)
4649 {
4650         struct mlx5_bsf *bsf;
4651         u32 data_len;
4652         u32 data_key;
4653         u64 data_va;
4654         u32 prot_len = 0;
4655         u32 prot_key = 0;
4656         u64 prot_va = 0;
4657         bool prot = false;
4658         int ret;
4659         int wqe_size;
4660         struct mlx5_ib_mr *mr = to_mmr(sig_mr);
4661         struct mlx5_ib_mr *pi_mr = mr->pi_mr;
4662
4663         data_len = pi_mr->data_length;
4664         data_key = pi_mr->ibmr.lkey;
4665         data_va = pi_mr->data_iova;
4666         if (pi_mr->meta_ndescs) {
4667                 prot_len = pi_mr->meta_length;
4668                 prot_key = pi_mr->ibmr.lkey;
4669                 prot_va = pi_mr->pi_iova;
4670                 prot = true;
4671         }
4672
4673         if (!prot || (data_key == prot_key && data_va == prot_va &&
4674                       data_len == prot_len)) {
4675                 /**
4676                  * Source domain doesn't contain signature information
4677                  * or data and protection are interleaved in memory.
4678                  * So need construct:
4679                  *                  ------------------
4680                  *                 |     data_klm     |
4681                  *                  ------------------
4682                  *                 |       BSF        |
4683                  *                  ------------------
4684                  **/
4685                 struct mlx5_klm *data_klm = *seg;
4686
4687                 data_klm->bcount = cpu_to_be32(data_len);
4688                 data_klm->key = cpu_to_be32(data_key);
4689                 data_klm->va = cpu_to_be64(data_va);
4690                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4691         } else {
4692                 /**
4693                  * Source domain contains signature information
4694                  * So need construct a strided block format:
4695                  *               ---------------------------
4696                  *              |     stride_block_ctrl     |
4697                  *               ---------------------------
4698                  *              |          data_klm         |
4699                  *               ---------------------------
4700                  *              |          prot_klm         |
4701                  *               ---------------------------
4702                  *              |             BSF           |
4703                  *               ---------------------------
4704                  **/
4705                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4706                 struct mlx5_stride_block_entry *data_sentry;
4707                 struct mlx5_stride_block_entry *prot_sentry;
4708                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4709                 int prot_size;
4710
4711                 sblock_ctrl = *seg;
4712                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4713                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4714
4715                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4716                 if (!prot_size) {
4717                         pr_err("Bad block size given: %u\n", block_size);
4718                         return -EINVAL;
4719                 }
4720                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4721                                                             prot_size);
4722                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4723                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4724                 sblock_ctrl->num_entries = cpu_to_be16(2);
4725
4726                 data_sentry->bcount = cpu_to_be16(block_size);
4727                 data_sentry->key = cpu_to_be32(data_key);
4728                 data_sentry->va = cpu_to_be64(data_va);
4729                 data_sentry->stride = cpu_to_be16(block_size);
4730
4731                 prot_sentry->bcount = cpu_to_be16(prot_size);
4732                 prot_sentry->key = cpu_to_be32(prot_key);
4733                 prot_sentry->va = cpu_to_be64(prot_va);
4734                 prot_sentry->stride = cpu_to_be16(prot_size);
4735
4736                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4737                                  sizeof(*prot_sentry), 64);
4738         }
4739
4740         *seg += wqe_size;
4741         *size += wqe_size / 16;
4742         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4743
4744         bsf = *seg;
4745         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4746         if (ret)
4747                 return -EINVAL;
4748
4749         *seg += sizeof(*bsf);
4750         *size += sizeof(*bsf) / 16;
4751         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4752
4753         return 0;
4754 }
4755
4756 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4757                                  struct ib_mr *sig_mr, int access_flags,
4758                                  u32 size, u32 length, u32 pdn)
4759 {
4760         u32 sig_key = sig_mr->rkey;
4761         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4762
4763         memset(seg, 0, sizeof(*seg));
4764
4765         seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS;
4766         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4767         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4768                                     MLX5_MKEY_BSF_EN | pdn);
4769         seg->len = cpu_to_be64(length);
4770         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4771         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4772 }
4773
4774 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4775                                 u32 size)
4776 {
4777         memset(umr, 0, sizeof(*umr));
4778
4779         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4780         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4781         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4782         umr->mkey_mask = sig_mkey_mask();
4783 }
4784
4785 static int set_pi_umr_wr(const struct ib_send_wr *send_wr,
4786                          struct mlx5_ib_qp *qp, void **seg, int *size,
4787                          void **cur_edge)
4788 {
4789         const struct ib_reg_wr *wr = reg_wr(send_wr);
4790         struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr);
4791         struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr;
4792         struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs;
4793         u32 pdn = get_pd(qp)->pdn;
4794         u32 xlt_size;
4795         int region_len, ret;
4796
4797         if (unlikely(send_wr->num_sge != 0) ||
4798             unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) ||
4799             unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) ||
4800             unlikely(!sig_mr->sig->sig_status_checked))
4801                 return -EINVAL;
4802
4803         /* length of the protected region, data + protection */
4804         region_len = pi_mr->ibmr.length;
4805
4806         /**
4807          * KLM octoword size - if protection was provided
4808          * then we use strided block format (3 octowords),
4809          * else we use single KLM (1 octoword)
4810          **/
4811         if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE)
4812                 xlt_size = 0x30;
4813         else
4814                 xlt_size = sizeof(struct mlx5_klm);
4815
4816         set_sig_umr_segment(*seg, xlt_size);
4817         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4818         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4819         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4820
4821         set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len,
4822                              pdn);
4823         *seg += sizeof(struct mlx5_mkey_seg);
4824         *size += sizeof(struct mlx5_mkey_seg) / 16;
4825         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4826
4827         ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size,
4828                                    cur_edge);
4829         if (ret)
4830                 return ret;
4831
4832         sig_mr->sig->sig_status_checked = false;
4833         return 0;
4834 }
4835
4836 static int set_psv_wr(struct ib_sig_domain *domain,
4837                       u32 psv_idx, void **seg, int *size)
4838 {
4839         struct mlx5_seg_set_psv *psv_seg = *seg;
4840
4841         memset(psv_seg, 0, sizeof(*psv_seg));
4842         psv_seg->psv_num = cpu_to_be32(psv_idx);
4843         switch (domain->sig_type) {
4844         case IB_SIG_TYPE_NONE:
4845                 break;
4846         case IB_SIG_TYPE_T10_DIF:
4847                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4848                                                      domain->sig.dif.app_tag);
4849                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4850                 break;
4851         default:
4852                 pr_err("Bad signature type (%d) is given.\n",
4853                        domain->sig_type);
4854                 return -EINVAL;
4855         }
4856
4857         *seg += sizeof(*psv_seg);
4858         *size += sizeof(*psv_seg) / 16;
4859
4860         return 0;
4861 }
4862
4863 static int set_reg_wr(struct mlx5_ib_qp *qp,
4864                       const struct ib_reg_wr *wr,
4865                       void **seg, int *size, void **cur_edge,
4866                       bool check_not_free)
4867 {
4868         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4869         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4870         struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device);
4871         int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4872         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4873         bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC;
4874         u8 flags = 0;
4875
4876         if (!mlx5_ib_can_use_umr(dev, atomic, wr->access)) {
4877                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4878                              "Fast update of %s for MR is disabled\n",
4879                              (MLX5_CAP_GEN(dev->mdev,
4880                                            umr_modify_entity_size_disabled)) ?
4881                                      "entity size" :
4882                                      "atomic access");
4883                 return -EINVAL;
4884         }
4885
4886         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4887                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4888                              "Invalid IB_SEND_INLINE send flag\n");
4889                 return -EINVAL;
4890         }
4891
4892         if (check_not_free)
4893                 flags |= MLX5_UMR_CHECK_NOT_FREE;
4894         if (umr_inline)
4895                 flags |= MLX5_UMR_INLINE;
4896
4897         set_reg_umr_seg(*seg, mr, flags, atomic);
4898         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4899         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4900         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4901
4902         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4903         *seg += sizeof(struct mlx5_mkey_seg);
4904         *size += sizeof(struct mlx5_mkey_seg) / 16;
4905         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4906
4907         if (umr_inline) {
4908                 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4909                                 mr_list_size);
4910                 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4911         } else {
4912                 set_reg_data_seg(*seg, mr, pd);
4913                 *seg += sizeof(struct mlx5_wqe_data_seg);
4914                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4915         }
4916         return 0;
4917 }
4918
4919 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4920                         void **cur_edge)
4921 {
4922         set_linv_umr_seg(*seg);
4923         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4924         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4925         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4926         set_linv_mkey_seg(*seg);
4927         *seg += sizeof(struct mlx5_mkey_seg);
4928         *size += sizeof(struct mlx5_mkey_seg) / 16;
4929         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4930 }
4931
4932 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4933 {
4934         __be32 *p = NULL;
4935         int i, j;
4936
4937         pr_debug("dump WQE index %u:\n", idx);
4938         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4939                 if ((i & 0xf) == 0) {
4940                         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
4941                         pr_debug("WQBB at %p:\n", (void *)p);
4942                         j = 0;
4943                         idx = (idx + 1) & (qp->sq.wqe_cnt - 1);
4944                 }
4945                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4946                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4947                          be32_to_cpu(p[j + 3]));
4948         }
4949 }
4950
4951 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4952                        struct mlx5_wqe_ctrl_seg **ctrl,
4953                        const struct ib_send_wr *wr, unsigned int *idx,
4954                        int *size, void **cur_edge, int nreq,
4955                        bool send_signaled, bool solicited)
4956 {
4957         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4958                 return -ENOMEM;
4959
4960         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4961         *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4962         *ctrl = *seg;
4963         *(uint32_t *)(*seg + 8) = 0;
4964         (*ctrl)->imm = send_ieth(wr);
4965         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4966                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4967                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4968
4969         *seg += sizeof(**ctrl);
4970         *size = sizeof(**ctrl) / 16;
4971         *cur_edge = qp->sq.cur_edge;
4972
4973         return 0;
4974 }
4975
4976 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4977                      struct mlx5_wqe_ctrl_seg **ctrl,
4978                      const struct ib_send_wr *wr, unsigned *idx,
4979                      int *size, void **cur_edge, int nreq)
4980 {
4981         return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4982                            wr->send_flags & IB_SEND_SIGNALED,
4983                            wr->send_flags & IB_SEND_SOLICITED);
4984 }
4985
4986 static void finish_wqe(struct mlx5_ib_qp *qp,
4987                        struct mlx5_wqe_ctrl_seg *ctrl,
4988                        void *seg, u8 size, void *cur_edge,
4989                        unsigned int idx, u64 wr_id, int nreq, u8 fence,
4990                        u32 mlx5_opcode)
4991 {
4992         u8 opmod = 0;
4993
4994         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4995                                              mlx5_opcode | ((u32)opmod << 24));
4996         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4997         ctrl->fm_ce_se |= fence;
4998         if (unlikely(qp->wq_sig))
4999                 ctrl->signature = wq_sig(ctrl);
5000
5001         qp->sq.wrid[idx] = wr_id;
5002         qp->sq.w_list[idx].opcode = mlx5_opcode;
5003         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
5004         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
5005         qp->sq.w_list[idx].next = qp->sq.cur_post;
5006
5007         /* We save the edge which was possibly updated during the WQE
5008          * construction, into SQ's cache.
5009          */
5010         seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
5011         qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
5012                           get_sq_edge(&qp->sq, qp->sq.cur_post &
5013                                       (qp->sq.wqe_cnt - 1)) :
5014                           cur_edge;
5015 }
5016
5017 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5018                               const struct ib_send_wr **bad_wr, bool drain)
5019 {
5020         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
5021         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5022         struct mlx5_core_dev *mdev = dev->mdev;
5023         struct ib_reg_wr reg_pi_wr;
5024         struct mlx5_ib_qp *qp;
5025         struct mlx5_ib_mr *mr;
5026         struct mlx5_ib_mr *pi_mr;
5027         struct mlx5_ib_mr pa_pi_mr;
5028         struct ib_sig_attrs *sig_attrs;
5029         struct mlx5_wqe_xrc_seg *xrc;
5030         struct mlx5_bf *bf;
5031         void *cur_edge;
5032         int uninitialized_var(size);
5033         unsigned long flags;
5034         unsigned idx;
5035         int err = 0;
5036         int num_sge;
5037         void *seg;
5038         int nreq;
5039         int i;
5040         u8 next_fence = 0;
5041         u8 fence;
5042
5043         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5044                      !drain)) {
5045                 *bad_wr = wr;
5046                 return -EIO;
5047         }
5048
5049         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5050                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
5051
5052         qp = to_mqp(ibqp);
5053         bf = &qp->bf;
5054
5055         spin_lock_irqsave(&qp->sq.lock, flags);
5056
5057         for (nreq = 0; wr; nreq++, wr = wr->next) {
5058                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
5059                         mlx5_ib_warn(dev, "\n");
5060                         err = -EINVAL;
5061                         *bad_wr = wr;
5062                         goto out;
5063                 }
5064
5065                 num_sge = wr->num_sge;
5066                 if (unlikely(num_sge > qp->sq.max_gs)) {
5067                         mlx5_ib_warn(dev, "\n");
5068                         err = -EINVAL;
5069                         *bad_wr = wr;
5070                         goto out;
5071                 }
5072
5073                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
5074                                 nreq);
5075                 if (err) {
5076                         mlx5_ib_warn(dev, "\n");
5077                         err = -ENOMEM;
5078                         *bad_wr = wr;
5079                         goto out;
5080                 }
5081
5082                 if (wr->opcode == IB_WR_REG_MR ||
5083                     wr->opcode == IB_WR_REG_MR_INTEGRITY) {
5084                         fence = dev->umr_fence;
5085                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
5086                 } else  {
5087                         if (wr->send_flags & IB_SEND_FENCE) {
5088                                 if (qp->next_fence)
5089                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
5090                                 else
5091                                         fence = MLX5_FENCE_MODE_FENCE;
5092                         } else {
5093                                 fence = qp->next_fence;
5094                         }
5095                 }
5096
5097                 switch (ibqp->qp_type) {
5098                 case IB_QPT_XRC_INI:
5099                         xrc = seg;
5100                         seg += sizeof(*xrc);
5101                         size += sizeof(*xrc) / 16;
5102                         /* fall through */
5103                 case IB_QPT_RC:
5104                         switch (wr->opcode) {
5105                         case IB_WR_RDMA_READ:
5106                         case IB_WR_RDMA_WRITE:
5107                         case IB_WR_RDMA_WRITE_WITH_IMM:
5108                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5109                                               rdma_wr(wr)->rkey);
5110                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
5111                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5112                                 break;
5113
5114                         case IB_WR_ATOMIC_CMP_AND_SWP:
5115                         case IB_WR_ATOMIC_FETCH_AND_ADD:
5116                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
5117                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
5118                                 err = -ENOSYS;
5119                                 *bad_wr = wr;
5120                                 goto out;
5121
5122                         case IB_WR_LOCAL_INV:
5123                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
5124                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
5125                                 set_linv_wr(qp, &seg, &size, &cur_edge);
5126                                 num_sge = 0;
5127                                 break;
5128
5129                         case IB_WR_REG_MR:
5130                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
5131                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
5132                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
5133                                                  &cur_edge, true);
5134                                 if (err) {
5135                                         *bad_wr = wr;
5136                                         goto out;
5137                                 }
5138                                 num_sge = 0;
5139                                 break;
5140
5141                         case IB_WR_REG_MR_INTEGRITY:
5142                                 qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY;
5143
5144                                 mr = to_mmr(reg_wr(wr)->mr);
5145                                 pi_mr = mr->pi_mr;
5146
5147                                 if (pi_mr) {
5148                                         memset(&reg_pi_wr, 0,
5149                                                sizeof(struct ib_reg_wr));
5150
5151                                         reg_pi_wr.mr = &pi_mr->ibmr;
5152                                         reg_pi_wr.access = reg_wr(wr)->access;
5153                                         reg_pi_wr.key = pi_mr->ibmr.rkey;
5154
5155                                         ctrl->imm = cpu_to_be32(reg_pi_wr.key);
5156                                         /* UMR for data + prot registration */
5157                                         err = set_reg_wr(qp, &reg_pi_wr, &seg,
5158                                                          &size, &cur_edge,
5159                                                          false);
5160                                         if (err) {
5161                                                 *bad_wr = wr;
5162                                                 goto out;
5163                                         }
5164                                         finish_wqe(qp, ctrl, seg, size,
5165                                                    cur_edge, idx, wr->wr_id,
5166                                                    nreq, fence,
5167                                                    MLX5_OPCODE_UMR);
5168
5169                                         err = begin_wqe(qp, &seg, &ctrl, wr,
5170                                                         &idx, &size, &cur_edge,
5171                                                         nreq);
5172                                         if (err) {
5173                                                 mlx5_ib_warn(dev, "\n");
5174                                                 err = -ENOMEM;
5175                                                 *bad_wr = wr;
5176                                                 goto out;
5177                                         }
5178                                 } else {
5179                                         memset(&pa_pi_mr, 0,
5180                                                sizeof(struct mlx5_ib_mr));
5181                                         /* No UMR, use local_dma_lkey */
5182                                         pa_pi_mr.ibmr.lkey =
5183                                                 mr->ibmr.pd->local_dma_lkey;
5184
5185                                         pa_pi_mr.ndescs = mr->ndescs;
5186                                         pa_pi_mr.data_length = mr->data_length;
5187                                         pa_pi_mr.data_iova = mr->data_iova;
5188                                         if (mr->meta_ndescs) {
5189                                                 pa_pi_mr.meta_ndescs =
5190                                                         mr->meta_ndescs;
5191                                                 pa_pi_mr.meta_length =
5192                                                         mr->meta_length;
5193                                                 pa_pi_mr.pi_iova = mr->pi_iova;
5194                                         }
5195
5196                                         pa_pi_mr.ibmr.length = mr->ibmr.length;
5197                                         mr->pi_mr = &pa_pi_mr;
5198                                 }
5199                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
5200                                 /* UMR for sig MR */
5201                                 err = set_pi_umr_wr(wr, qp, &seg, &size,
5202                                                     &cur_edge);
5203                                 if (err) {
5204                                         mlx5_ib_warn(dev, "\n");
5205                                         *bad_wr = wr;
5206                                         goto out;
5207                                 }
5208                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5209                                            wr->wr_id, nreq, fence,
5210                                            MLX5_OPCODE_UMR);
5211
5212                                 /*
5213                                  * SET_PSV WQEs are not signaled and solicited
5214                                  * on error
5215                                  */
5216                                 sig_attrs = mr->ibmr.sig_attrs;
5217                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5218                                                   &size, &cur_edge, nreq, false,
5219                                                   true);
5220                                 if (err) {
5221                                         mlx5_ib_warn(dev, "\n");
5222                                         err = -ENOMEM;
5223                                         *bad_wr = wr;
5224                                         goto out;
5225                                 }
5226                                 err = set_psv_wr(&sig_attrs->mem,
5227                                                  mr->sig->psv_memory.psv_idx,
5228                                                  &seg, &size);
5229                                 if (err) {
5230                                         mlx5_ib_warn(dev, "\n");
5231                                         *bad_wr = wr;
5232                                         goto out;
5233                                 }
5234                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5235                                            wr->wr_id, nreq, next_fence,
5236                                            MLX5_OPCODE_SET_PSV);
5237
5238                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5239                                                   &size, &cur_edge, nreq, false,
5240                                                   true);
5241                                 if (err) {
5242                                         mlx5_ib_warn(dev, "\n");
5243                                         err = -ENOMEM;
5244                                         *bad_wr = wr;
5245                                         goto out;
5246                                 }
5247                                 err = set_psv_wr(&sig_attrs->wire,
5248                                                  mr->sig->psv_wire.psv_idx,
5249                                                  &seg, &size);
5250                                 if (err) {
5251                                         mlx5_ib_warn(dev, "\n");
5252                                         *bad_wr = wr;
5253                                         goto out;
5254                                 }
5255                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5256                                            wr->wr_id, nreq, next_fence,
5257                                            MLX5_OPCODE_SET_PSV);
5258
5259                                 qp->next_fence =
5260                                         MLX5_FENCE_MODE_INITIATOR_SMALL;
5261                                 num_sge = 0;
5262                                 goto skip_psv;
5263
5264                         default:
5265                                 break;
5266                         }
5267                         break;
5268
5269                 case IB_QPT_UC:
5270                         switch (wr->opcode) {
5271                         case IB_WR_RDMA_WRITE:
5272                         case IB_WR_RDMA_WRITE_WITH_IMM:
5273                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5274                                               rdma_wr(wr)->rkey);
5275                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
5276                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5277                                 break;
5278
5279                         default:
5280                                 break;
5281                         }
5282                         break;
5283
5284                 case IB_QPT_SMI:
5285                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5286                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5287                                 err = -EPERM;
5288                                 *bad_wr = wr;
5289                                 goto out;
5290                         }
5291                         /* fall through */
5292                 case MLX5_IB_QPT_HW_GSI:
5293                         set_datagram_seg(seg, wr);
5294                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5295                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5296                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5297
5298                         break;
5299                 case IB_QPT_UD:
5300                         set_datagram_seg(seg, wr);
5301                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5302                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5303                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5304
5305                         /* handle qp that supports ud offload */
5306                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5307                                 struct mlx5_wqe_eth_pad *pad;
5308
5309                                 pad = seg;
5310                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5311                                 seg += sizeof(struct mlx5_wqe_eth_pad);
5312                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
5313                                 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5314                                 handle_post_send_edge(&qp->sq, &seg, size,
5315                                                       &cur_edge);
5316                         }
5317                         break;
5318                 case MLX5_IB_QPT_REG_UMR:
5319                         if (wr->opcode != MLX5_IB_WR_UMR) {
5320                                 err = -EINVAL;
5321                                 mlx5_ib_warn(dev, "bad opcode\n");
5322                                 goto out;
5323                         }
5324                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
5325                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
5326                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5327                         if (unlikely(err))
5328                                 goto out;
5329                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5330                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5331                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5332                         set_reg_mkey_segment(seg, wr);
5333                         seg += sizeof(struct mlx5_mkey_seg);
5334                         size += sizeof(struct mlx5_mkey_seg) / 16;
5335                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5336                         break;
5337
5338                 default:
5339                         break;
5340                 }
5341
5342                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
5343                         err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
5344                         if (unlikely(err)) {
5345                                 mlx5_ib_warn(dev, "\n");
5346                                 *bad_wr = wr;
5347                                 goto out;
5348                         }
5349                 } else {
5350                         for (i = 0; i < num_sge; i++) {
5351                                 handle_post_send_edge(&qp->sq, &seg, size,
5352                                                       &cur_edge);
5353                                 if (likely(wr->sg_list[i].length)) {
5354                                         set_data_ptr_seg
5355                                         ((struct mlx5_wqe_data_seg *)seg,
5356                                          wr->sg_list + i);
5357                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
5358                                         seg += sizeof(struct mlx5_wqe_data_seg);
5359                                 }
5360                         }
5361                 }
5362
5363                 qp->next_fence = next_fence;
5364                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5365                            fence, mlx5_ib_opcode[wr->opcode]);
5366 skip_psv:
5367                 if (0)
5368                         dump_wqe(qp, idx, size);
5369         }
5370
5371 out:
5372         if (likely(nreq)) {
5373                 qp->sq.head += nreq;
5374
5375                 /* Make sure that descriptors are written before
5376                  * updating doorbell record and ringing the doorbell
5377                  */
5378                 wmb();
5379
5380                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5381
5382                 /* Make sure doorbell record is visible to the HCA before
5383                  * we hit doorbell */
5384                 wmb();
5385
5386                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
5387                 /* Make sure doorbells don't leak out of SQ spinlock
5388                  * and reach the HCA out of order.
5389                  */
5390                 bf->offset ^= bf->buf_size;
5391         }
5392
5393         spin_unlock_irqrestore(&qp->sq.lock, flags);
5394
5395         return err;
5396 }
5397
5398 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5399                       const struct ib_send_wr **bad_wr)
5400 {
5401         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5402 }
5403
5404 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5405 {
5406         sig->signature = calc_sig(sig, size);
5407 }
5408
5409 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5410                       const struct ib_recv_wr **bad_wr, bool drain)
5411 {
5412         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5413         struct mlx5_wqe_data_seg *scat;
5414         struct mlx5_rwqe_sig *sig;
5415         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5416         struct mlx5_core_dev *mdev = dev->mdev;
5417         unsigned long flags;
5418         int err = 0;
5419         int nreq;
5420         int ind;
5421         int i;
5422
5423         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5424                      !drain)) {
5425                 *bad_wr = wr;
5426                 return -EIO;
5427         }
5428
5429         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5430                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5431
5432         spin_lock_irqsave(&qp->rq.lock, flags);
5433
5434         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5435
5436         for (nreq = 0; wr; nreq++, wr = wr->next) {
5437                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5438                         err = -ENOMEM;
5439                         *bad_wr = wr;
5440                         goto out;
5441                 }
5442
5443                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5444                         err = -EINVAL;
5445                         *bad_wr = wr;
5446                         goto out;
5447                 }
5448
5449                 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5450                 if (qp->wq_sig)
5451                         scat++;
5452
5453                 for (i = 0; i < wr->num_sge; i++)
5454                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5455
5456                 if (i < qp->rq.max_gs) {
5457                         scat[i].byte_count = 0;
5458                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5459                         scat[i].addr       = 0;
5460                 }
5461
5462                 if (qp->wq_sig) {
5463                         sig = (struct mlx5_rwqe_sig *)scat;
5464                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5465                 }
5466
5467                 qp->rq.wrid[ind] = wr->wr_id;
5468
5469                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5470         }
5471
5472 out:
5473         if (likely(nreq)) {
5474                 qp->rq.head += nreq;
5475
5476                 /* Make sure that descriptors are written before
5477                  * doorbell record.
5478                  */
5479                 wmb();
5480
5481                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5482         }
5483
5484         spin_unlock_irqrestore(&qp->rq.lock, flags);
5485
5486         return err;
5487 }
5488
5489 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5490                       const struct ib_recv_wr **bad_wr)
5491 {
5492         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5493 }
5494
5495 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5496 {
5497         switch (mlx5_state) {
5498         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5499         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5500         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5501         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5502         case MLX5_QP_STATE_SQ_DRAINING:
5503         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5504         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5505         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5506         default:                     return -1;
5507         }
5508 }
5509
5510 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5511 {
5512         switch (mlx5_mig_state) {
5513         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5514         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5515         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5516         default: return -1;
5517         }
5518 }
5519
5520 static int to_ib_qp_access_flags(int mlx5_flags)
5521 {
5522         int ib_flags = 0;
5523
5524         if (mlx5_flags & MLX5_QP_BIT_RRE)
5525                 ib_flags |= IB_ACCESS_REMOTE_READ;
5526         if (mlx5_flags & MLX5_QP_BIT_RWE)
5527                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5528         if (mlx5_flags & MLX5_QP_BIT_RAE)
5529                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5530
5531         return ib_flags;
5532 }
5533
5534 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5535                             struct rdma_ah_attr *ah_attr,
5536                             struct mlx5_qp_path *path)
5537 {
5538
5539         memset(ah_attr, 0, sizeof(*ah_attr));
5540
5541         if (!path->port || path->port > ibdev->num_ports)
5542                 return;
5543
5544         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5545
5546         rdma_ah_set_port_num(ah_attr, path->port);
5547         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5548
5549         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5550         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5551         rdma_ah_set_static_rate(ah_attr,
5552                                 path->static_rate ? path->static_rate - 5 : 0);
5553         if (path->grh_mlid & (1 << 7)) {
5554                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5555
5556                 rdma_ah_set_grh(ah_attr, NULL,
5557                                 tc_fl & 0xfffff,
5558                                 path->mgid_index,
5559                                 path->hop_limit,
5560                                 (tc_fl >> 20) & 0xff);
5561                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5562         }
5563 }
5564
5565 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5566                                         struct mlx5_ib_sq *sq,
5567                                         u8 *sq_state)
5568 {
5569         int err;
5570
5571         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5572         if (err)
5573                 goto out;
5574         sq->state = *sq_state;
5575
5576 out:
5577         return err;
5578 }
5579
5580 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5581                                         struct mlx5_ib_rq *rq,
5582                                         u8 *rq_state)
5583 {
5584         void *out;
5585         void *rqc;
5586         int inlen;
5587         int err;
5588
5589         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5590         out = kvzalloc(inlen, GFP_KERNEL);
5591         if (!out)
5592                 return -ENOMEM;
5593
5594         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5595         if (err)
5596                 goto out;
5597
5598         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5599         *rq_state = MLX5_GET(rqc, rqc, state);
5600         rq->state = *rq_state;
5601
5602 out:
5603         kvfree(out);
5604         return err;
5605 }
5606
5607 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5608                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5609 {
5610         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5611                 [MLX5_RQC_STATE_RST] = {
5612                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5613                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5614                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5615                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5616                 },
5617                 [MLX5_RQC_STATE_RDY] = {
5618                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5619                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5620                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5621                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5622                 },
5623                 [MLX5_RQC_STATE_ERR] = {
5624                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5625                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5626                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5627                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5628                 },
5629                 [MLX5_RQ_STATE_NA] = {
5630                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5631                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5632                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5633                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5634                 },
5635         };
5636
5637         *qp_state = sqrq_trans[rq_state][sq_state];
5638
5639         if (*qp_state == MLX5_QP_STATE_BAD) {
5640                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5641                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5642                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5643                 return -EINVAL;
5644         }
5645
5646         if (*qp_state == MLX5_QP_STATE)
5647                 *qp_state = qp->state;
5648
5649         return 0;
5650 }
5651
5652 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5653                                      struct mlx5_ib_qp *qp,
5654                                      u8 *raw_packet_qp_state)
5655 {
5656         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5657         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5658         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5659         int err;
5660         u8 sq_state = MLX5_SQ_STATE_NA;
5661         u8 rq_state = MLX5_RQ_STATE_NA;
5662
5663         if (qp->sq.wqe_cnt) {
5664                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5665                 if (err)
5666                         return err;
5667         }
5668
5669         if (qp->rq.wqe_cnt) {
5670                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5671                 if (err)
5672                         return err;
5673         }
5674
5675         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5676                                       raw_packet_qp_state);
5677 }
5678
5679 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5680                          struct ib_qp_attr *qp_attr)
5681 {
5682         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5683         struct mlx5_qp_context *context;
5684         int mlx5_state;
5685         u32 *outb;
5686         int err = 0;
5687
5688         outb = kzalloc(outlen, GFP_KERNEL);
5689         if (!outb)
5690                 return -ENOMEM;
5691
5692         err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
5693         if (err)
5694                 goto out;
5695
5696         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5697         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5698
5699         mlx5_state = be32_to_cpu(context->flags) >> 28;
5700
5701         qp->state                    = to_ib_qp_state(mlx5_state);
5702         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5703         qp_attr->path_mig_state      =
5704                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5705         qp_attr->qkey                = be32_to_cpu(context->qkey);
5706         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5707         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5708         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5709         qp_attr->qp_access_flags     =
5710                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5711
5712         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5713                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5714                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5715                 qp_attr->alt_pkey_index =
5716                         be16_to_cpu(context->alt_path.pkey_index);
5717                 qp_attr->alt_port_num   =
5718                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5719         }
5720
5721         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5722         qp_attr->port_num = context->pri_path.port;
5723
5724         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5725         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5726
5727         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5728
5729         qp_attr->max_dest_rd_atomic =
5730                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5731         qp_attr->min_rnr_timer      =
5732                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5733         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5734         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5735         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5736         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5737
5738 out:
5739         kfree(outb);
5740         return err;
5741 }
5742
5743 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5744                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5745                                 struct ib_qp_init_attr *qp_init_attr)
5746 {
5747         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5748         u32 *out;
5749         u32 access_flags = 0;
5750         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5751         void *dctc;
5752         int err;
5753         int supported_mask = IB_QP_STATE |
5754                              IB_QP_ACCESS_FLAGS |
5755                              IB_QP_PORT |
5756                              IB_QP_MIN_RNR_TIMER |
5757                              IB_QP_AV |
5758                              IB_QP_PATH_MTU |
5759                              IB_QP_PKEY_INDEX;
5760
5761         if (qp_attr_mask & ~supported_mask)
5762                 return -EINVAL;
5763         if (mqp->state != IB_QPS_RTR)
5764                 return -EINVAL;
5765
5766         out = kzalloc(outlen, GFP_KERNEL);
5767         if (!out)
5768                 return -ENOMEM;
5769
5770         err = mlx5_core_dct_query(dev, dct, out, outlen);
5771         if (err)
5772                 goto out;
5773
5774         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5775
5776         if (qp_attr_mask & IB_QP_STATE)
5777                 qp_attr->qp_state = IB_QPS_RTR;
5778
5779         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5780                 if (MLX5_GET(dctc, dctc, rre))
5781                         access_flags |= IB_ACCESS_REMOTE_READ;
5782                 if (MLX5_GET(dctc, dctc, rwe))
5783                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5784                 if (MLX5_GET(dctc, dctc, rae))
5785                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5786                 qp_attr->qp_access_flags = access_flags;
5787         }
5788
5789         if (qp_attr_mask & IB_QP_PORT)
5790                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5791         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5792                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5793         if (qp_attr_mask & IB_QP_AV) {
5794                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5795                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5796                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5797                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5798         }
5799         if (qp_attr_mask & IB_QP_PATH_MTU)
5800                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5801         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5802                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5803 out:
5804         kfree(out);
5805         return err;
5806 }
5807
5808 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5809                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5810 {
5811         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5812         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5813         int err = 0;
5814         u8 raw_packet_qp_state;
5815
5816         if (ibqp->rwq_ind_tbl)
5817                 return -ENOSYS;
5818
5819         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5820                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5821                                             qp_init_attr);
5822
5823         /* Not all of output fields are applicable, make sure to zero them */
5824         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5825         memset(qp_attr, 0, sizeof(*qp_attr));
5826
5827         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5828                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5829                                             qp_attr_mask, qp_init_attr);
5830
5831         mutex_lock(&qp->mutex);
5832
5833         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5834             qp->flags & MLX5_IB_QP_UNDERLAY) {
5835                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5836                 if (err)
5837                         goto out;
5838                 qp->state = raw_packet_qp_state;
5839                 qp_attr->port_num = 1;
5840         } else {
5841                 err = query_qp_attr(dev, qp, qp_attr);
5842                 if (err)
5843                         goto out;
5844         }
5845
5846         qp_attr->qp_state            = qp->state;
5847         qp_attr->cur_qp_state        = qp_attr->qp_state;
5848         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5849         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5850
5851         if (!ibqp->uobject) {
5852                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5853                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5854                 qp_init_attr->qp_context = ibqp->qp_context;
5855         } else {
5856                 qp_attr->cap.max_send_wr  = 0;
5857                 qp_attr->cap.max_send_sge = 0;
5858         }
5859
5860         qp_init_attr->qp_type = ibqp->qp_type;
5861         qp_init_attr->recv_cq = ibqp->recv_cq;
5862         qp_init_attr->send_cq = ibqp->send_cq;
5863         qp_init_attr->srq = ibqp->srq;
5864         qp_attr->cap.max_inline_data = qp->max_inline_data;
5865
5866         qp_init_attr->cap            = qp_attr->cap;
5867
5868         qp_init_attr->create_flags = 0;
5869         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5870                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5871
5872         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5873                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5874         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5875                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5876         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5877                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5878         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5879                 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1;
5880
5881         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5882                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5883
5884 out:
5885         mutex_unlock(&qp->mutex);
5886         return err;
5887 }
5888
5889 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5890                                    struct ib_udata *udata)
5891 {
5892         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5893         struct mlx5_ib_xrcd *xrcd;
5894         int err;
5895
5896         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5897                 return ERR_PTR(-ENOSYS);
5898
5899         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5900         if (!xrcd)
5901                 return ERR_PTR(-ENOMEM);
5902
5903         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5904         if (err) {
5905                 kfree(xrcd);
5906                 return ERR_PTR(-ENOMEM);
5907         }
5908
5909         return &xrcd->ibxrcd;
5910 }
5911
5912 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
5913 {
5914         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5915         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5916         int err;
5917
5918         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5919         if (err)
5920                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5921
5922         kfree(xrcd);
5923         return 0;
5924 }
5925
5926 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5927 {
5928         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5929         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5930         struct ib_event event;
5931
5932         if (rwq->ibwq.event_handler) {
5933                 event.device     = rwq->ibwq.device;
5934                 event.element.wq = &rwq->ibwq;
5935                 switch (type) {
5936                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5937                         event.event = IB_EVENT_WQ_FATAL;
5938                         break;
5939                 default:
5940                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5941                         return;
5942                 }
5943
5944                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5945         }
5946 }
5947
5948 static int set_delay_drop(struct mlx5_ib_dev *dev)
5949 {
5950         int err = 0;
5951
5952         mutex_lock(&dev->delay_drop.lock);
5953         if (dev->delay_drop.activate)
5954                 goto out;
5955
5956         err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
5957         if (err)
5958                 goto out;
5959
5960         dev->delay_drop.activate = true;
5961 out:
5962         mutex_unlock(&dev->delay_drop.lock);
5963
5964         if (!err)
5965                 atomic_inc(&dev->delay_drop.rqs_cnt);
5966         return err;
5967 }
5968
5969 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5970                       struct ib_wq_init_attr *init_attr)
5971 {
5972         struct mlx5_ib_dev *dev;
5973         int has_net_offloads;
5974         __be64 *rq_pas0;
5975         void *in;
5976         void *rqc;
5977         void *wq;
5978         int inlen;
5979         int err;
5980
5981         dev = to_mdev(pd->device);
5982
5983         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5984         in = kvzalloc(inlen, GFP_KERNEL);
5985         if (!in)
5986                 return -ENOMEM;
5987
5988         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5989         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5990         MLX5_SET(rqc,  rqc, mem_rq_type,
5991                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5992         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5993         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5994         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5995         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5996         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5997         MLX5_SET(wq, wq, wq_type,
5998                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5999                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
6000         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6001                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
6002                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
6003                         err = -EOPNOTSUPP;
6004                         goto out;
6005                 } else {
6006                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
6007                 }
6008         }
6009         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
6010         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
6011                 /*
6012                  * In Firmware number of strides in each WQE is:
6013                  *   "512 * 2^single_wqe_log_num_of_strides"
6014                  * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
6015                  * accepted as 0 to 9
6016                  */
6017                 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
6018                                              2,  3,  4,  5,  6,  7,  8, 9 };
6019                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
6020                 MLX5_SET(wq, wq, log_wqe_stride_size,
6021                          rwq->single_stride_log_num_of_bytes -
6022                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
6023                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
6024                          fw_map[rwq->log_num_strides -
6025                                 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
6026         }
6027         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
6028         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
6029         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
6030         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
6031         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
6032         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
6033         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
6034         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6035                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6036                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
6037                         err = -EOPNOTSUPP;
6038                         goto out;
6039                 }
6040         } else {
6041                 MLX5_SET(rqc, rqc, vsd, 1);
6042         }
6043         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
6044                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
6045                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
6046                         err = -EOPNOTSUPP;
6047                         goto out;
6048                 }
6049                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
6050         }
6051         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6052                 if (!(dev->ib_dev.attrs.raw_packet_caps &
6053                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
6054                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
6055                         err = -EOPNOTSUPP;
6056                         goto out;
6057                 }
6058                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
6059         }
6060         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
6061         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
6062         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
6063         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
6064                 err = set_delay_drop(dev);
6065                 if (err) {
6066                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
6067                                      err);
6068                         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6069                 } else {
6070                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
6071                 }
6072         }
6073 out:
6074         kvfree(in);
6075         return err;
6076 }
6077
6078 static int set_user_rq_size(struct mlx5_ib_dev *dev,
6079                             struct ib_wq_init_attr *wq_init_attr,
6080                             struct mlx5_ib_create_wq *ucmd,
6081                             struct mlx5_ib_rwq *rwq)
6082 {
6083         /* Sanity check RQ size before proceeding */
6084         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
6085                 return -EINVAL;
6086
6087         if (!ucmd->rq_wqe_count)
6088                 return -EINVAL;
6089
6090         rwq->wqe_count = ucmd->rq_wqe_count;
6091         rwq->wqe_shift = ucmd->rq_wqe_shift;
6092         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
6093                 return -EINVAL;
6094
6095         rwq->log_rq_stride = rwq->wqe_shift;
6096         rwq->log_rq_size = ilog2(rwq->wqe_count);
6097         return 0;
6098 }
6099
6100 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
6101 {
6102         if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
6103             (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
6104                 return false;
6105
6106         if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
6107             (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
6108                 return false;
6109
6110         return true;
6111 }
6112
6113 static int prepare_user_rq(struct ib_pd *pd,
6114                            struct ib_wq_init_attr *init_attr,
6115                            struct ib_udata *udata,
6116                            struct mlx5_ib_rwq *rwq)
6117 {
6118         struct mlx5_ib_dev *dev = to_mdev(pd->device);
6119         struct mlx5_ib_create_wq ucmd = {};
6120         int err;
6121         size_t required_cmd_sz;
6122
6123         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
6124                 + sizeof(ucmd.single_stride_log_num_of_bytes);
6125         if (udata->inlen < required_cmd_sz) {
6126                 mlx5_ib_dbg(dev, "invalid inlen\n");
6127                 return -EINVAL;
6128         }
6129
6130         if (udata->inlen > sizeof(ucmd) &&
6131             !ib_is_udata_cleared(udata, sizeof(ucmd),
6132                                  udata->inlen - sizeof(ucmd))) {
6133                 mlx5_ib_dbg(dev, "inlen is not supported\n");
6134                 return -EOPNOTSUPP;
6135         }
6136
6137         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
6138                 mlx5_ib_dbg(dev, "copy failed\n");
6139                 return -EFAULT;
6140         }
6141
6142         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
6143                 mlx5_ib_dbg(dev, "invalid comp mask\n");
6144                 return -EOPNOTSUPP;
6145         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
6146                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
6147                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
6148                         return -EOPNOTSUPP;
6149                 }
6150                 if ((ucmd.single_stride_log_num_of_bytes <
6151                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
6152                     (ucmd.single_stride_log_num_of_bytes >
6153                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
6154                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
6155                                     ucmd.single_stride_log_num_of_bytes,
6156                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
6157                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
6158                         return -EINVAL;
6159                 }
6160                 if (!log_of_strides_valid(dev,
6161                                           ucmd.single_wqe_log_num_of_strides)) {
6162                         mlx5_ib_dbg(
6163                                 dev,
6164                                 "Invalid log num strides (%u. Range is %u - %u)\n",
6165                                 ucmd.single_wqe_log_num_of_strides,
6166                                 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
6167                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
6168                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
6169                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
6170                         return -EINVAL;
6171                 }
6172                 rwq->single_stride_log_num_of_bytes =
6173                         ucmd.single_stride_log_num_of_bytes;
6174                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
6175                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
6176                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
6177         }
6178
6179         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
6180         if (err) {
6181                 mlx5_ib_dbg(dev, "err %d\n", err);
6182                 return err;
6183         }
6184
6185         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
6186         if (err) {
6187                 mlx5_ib_dbg(dev, "err %d\n", err);
6188                 return err;
6189         }
6190
6191         rwq->user_index = ucmd.user_index;
6192         return 0;
6193 }
6194
6195 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
6196                                 struct ib_wq_init_attr *init_attr,
6197                                 struct ib_udata *udata)
6198 {
6199         struct mlx5_ib_dev *dev;
6200         struct mlx5_ib_rwq *rwq;
6201         struct mlx5_ib_create_wq_resp resp = {};
6202         size_t min_resp_len;
6203         int err;
6204
6205         if (!udata)
6206                 return ERR_PTR(-ENOSYS);
6207
6208         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6209         if (udata->outlen && udata->outlen < min_resp_len)
6210                 return ERR_PTR(-EINVAL);
6211
6212         if (!capable(CAP_SYS_RAWIO) &&
6213             init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
6214                 return ERR_PTR(-EPERM);
6215
6216         dev = to_mdev(pd->device);
6217         switch (init_attr->wq_type) {
6218         case IB_WQT_RQ:
6219                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
6220                 if (!rwq)
6221                         return ERR_PTR(-ENOMEM);
6222                 err = prepare_user_rq(pd, init_attr, udata, rwq);
6223                 if (err)
6224                         goto err;
6225                 err = create_rq(rwq, pd, init_attr);
6226                 if (err)
6227                         goto err_user_rq;
6228                 break;
6229         default:
6230                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
6231                             init_attr->wq_type);
6232                 return ERR_PTR(-EINVAL);
6233         }
6234
6235         rwq->ibwq.wq_num = rwq->core_qp.qpn;
6236         rwq->ibwq.state = IB_WQS_RESET;
6237         if (udata->outlen) {
6238                 resp.response_length = offsetof(typeof(resp), response_length) +
6239                                 sizeof(resp.response_length);
6240                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6241                 if (err)
6242                         goto err_copy;
6243         }
6244
6245         rwq->core_qp.event = mlx5_ib_wq_event;
6246         rwq->ibwq.event_handler = init_attr->event_handler;
6247         return &rwq->ibwq;
6248
6249 err_copy:
6250         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6251 err_user_rq:
6252         destroy_user_rq(dev, pd, rwq, udata);
6253 err:
6254         kfree(rwq);
6255         return ERR_PTR(err);
6256 }
6257
6258 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
6259 {
6260         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6261         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6262
6263         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
6264         destroy_user_rq(dev, wq->pd, rwq, udata);
6265         kfree(rwq);
6266 }
6267
6268 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
6269                                                       struct ib_rwq_ind_table_init_attr *init_attr,
6270                                                       struct ib_udata *udata)
6271 {
6272         struct mlx5_ib_dev *dev = to_mdev(device);
6273         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
6274         int sz = 1 << init_attr->log_ind_tbl_size;
6275         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
6276         size_t min_resp_len;
6277         int inlen;
6278         int err;
6279         int i;
6280         u32 *in;
6281         void *rqtc;
6282
6283         if (udata->inlen > 0 &&
6284             !ib_is_udata_cleared(udata, 0,
6285                                  udata->inlen))
6286                 return ERR_PTR(-EOPNOTSUPP);
6287
6288         if (init_attr->log_ind_tbl_size >
6289             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
6290                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
6291                             init_attr->log_ind_tbl_size,
6292                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
6293                 return ERR_PTR(-EINVAL);
6294         }
6295
6296         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6297         if (udata->outlen && udata->outlen < min_resp_len)
6298                 return ERR_PTR(-EINVAL);
6299
6300         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6301         if (!rwq_ind_tbl)
6302                 return ERR_PTR(-ENOMEM);
6303
6304         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
6305         in = kvzalloc(inlen, GFP_KERNEL);
6306         if (!in) {
6307                 err = -ENOMEM;
6308                 goto err;
6309         }
6310
6311         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6312
6313         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6314         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6315
6316         for (i = 0; i < sz; i++)
6317                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6318
6319         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6320         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6321
6322         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6323         kvfree(in);
6324
6325         if (err)
6326                 goto err;
6327
6328         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6329         if (udata->outlen) {
6330                 resp.response_length = offsetof(typeof(resp), response_length) +
6331                                         sizeof(resp.response_length);
6332                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6333                 if (err)
6334                         goto err_copy;
6335         }
6336
6337         return &rwq_ind_tbl->ib_rwq_ind_tbl;
6338
6339 err_copy:
6340         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6341 err:
6342         kfree(rwq_ind_tbl);
6343         return ERR_PTR(err);
6344 }
6345
6346 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6347 {
6348         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6349         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6350
6351         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6352
6353         kfree(rwq_ind_tbl);
6354         return 0;
6355 }
6356
6357 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6358                       u32 wq_attr_mask, struct ib_udata *udata)
6359 {
6360         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6361         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6362         struct mlx5_ib_modify_wq ucmd = {};
6363         size_t required_cmd_sz;
6364         int curr_wq_state;
6365         int wq_state;
6366         int inlen;
6367         int err;
6368         void *rqc;
6369         void *in;
6370
6371         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6372         if (udata->inlen < required_cmd_sz)
6373                 return -EINVAL;
6374
6375         if (udata->inlen > sizeof(ucmd) &&
6376             !ib_is_udata_cleared(udata, sizeof(ucmd),
6377                                  udata->inlen - sizeof(ucmd)))
6378                 return -EOPNOTSUPP;
6379
6380         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6381                 return -EFAULT;
6382
6383         if (ucmd.comp_mask || ucmd.reserved)
6384                 return -EOPNOTSUPP;
6385
6386         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
6387         in = kvzalloc(inlen, GFP_KERNEL);
6388         if (!in)
6389                 return -ENOMEM;
6390
6391         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6392
6393         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6394                 wq_attr->curr_wq_state : wq->state;
6395         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6396                 wq_attr->wq_state : curr_wq_state;
6397         if (curr_wq_state == IB_WQS_ERR)
6398                 curr_wq_state = MLX5_RQC_STATE_ERR;
6399         if (wq_state == IB_WQS_ERR)
6400                 wq_state = MLX5_RQC_STATE_ERR;
6401         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6402         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6403         MLX5_SET(rqc, rqc, state, wq_state);
6404
6405         if (wq_attr_mask & IB_WQ_FLAGS) {
6406                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6407                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6408                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6409                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
6410                                             "supported\n");
6411                                 err = -EOPNOTSUPP;
6412                                 goto out;
6413                         }
6414                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6415                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6416                         MLX5_SET(rqc, rqc, vsd,
6417                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6418                 }
6419
6420                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6421                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6422                         err = -EOPNOTSUPP;
6423                         goto out;
6424                 }
6425         }
6426
6427         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6428                 u16 set_id;
6429
6430                 set_id = mlx5_ib_get_counters_id(dev, 0);
6431                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6432                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6433                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6434                         MLX5_SET(rqc, rqc, counter_set_id, set_id);
6435                 } else
6436                         dev_info_once(
6437                                 &dev->ib_dev.dev,
6438                                 "Receive WQ counters are not supported on current FW\n");
6439         }
6440
6441         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
6442         if (!err)
6443                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6444
6445 out:
6446         kvfree(in);
6447         return err;
6448 }
6449
6450 struct mlx5_ib_drain_cqe {
6451         struct ib_cqe cqe;
6452         struct completion done;
6453 };
6454
6455 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6456 {
6457         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6458                                                      struct mlx5_ib_drain_cqe,
6459                                                      cqe);
6460
6461         complete(&cqe->done);
6462 }
6463
6464 /* This function returns only once the drained WR was completed */
6465 static void handle_drain_completion(struct ib_cq *cq,
6466                                     struct mlx5_ib_drain_cqe *sdrain,
6467                                     struct mlx5_ib_dev *dev)
6468 {
6469         struct mlx5_core_dev *mdev = dev->mdev;
6470
6471         if (cq->poll_ctx == IB_POLL_DIRECT) {
6472                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6473                         ib_process_cq_direct(cq, -1);
6474                 return;
6475         }
6476
6477         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6478                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6479                 bool triggered = false;
6480                 unsigned long flags;
6481
6482                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6483                 /* Make sure that the CQ handler won't run if wasn't run yet */
6484                 if (!mcq->mcq.reset_notify_added)
6485                         mcq->mcq.reset_notify_added = 1;
6486                 else
6487                         triggered = true;
6488                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6489
6490                 if (triggered) {
6491                         /* Wait for any scheduled/running task to be ended */
6492                         switch (cq->poll_ctx) {
6493                         case IB_POLL_SOFTIRQ:
6494                                 irq_poll_disable(&cq->iop);
6495                                 irq_poll_enable(&cq->iop);
6496                                 break;
6497                         case IB_POLL_WORKQUEUE:
6498                                 cancel_work_sync(&cq->work);
6499                                 break;
6500                         default:
6501                                 WARN_ON_ONCE(1);
6502                         }
6503                 }
6504
6505                 /* Run the CQ handler - this makes sure that the drain WR will
6506                  * be processed if wasn't processed yet.
6507                  */
6508                 mcq->mcq.comp(&mcq->mcq, NULL);
6509         }
6510
6511         wait_for_completion(&sdrain->done);
6512 }
6513
6514 void mlx5_ib_drain_sq(struct ib_qp *qp)
6515 {
6516         struct ib_cq *cq = qp->send_cq;
6517         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6518         struct mlx5_ib_drain_cqe sdrain;
6519         const struct ib_send_wr *bad_swr;
6520         struct ib_rdma_wr swr = {
6521                 .wr = {
6522                         .next = NULL,
6523                         { .wr_cqe       = &sdrain.cqe, },
6524                         .opcode = IB_WR_RDMA_WRITE,
6525                 },
6526         };
6527         int ret;
6528         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6529         struct mlx5_core_dev *mdev = dev->mdev;
6530
6531         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6532         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6533                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6534                 return;
6535         }
6536
6537         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6538         init_completion(&sdrain.done);
6539
6540         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6541         if (ret) {
6542                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6543                 return;
6544         }
6545
6546         handle_drain_completion(cq, &sdrain, dev);
6547 }
6548
6549 void mlx5_ib_drain_rq(struct ib_qp *qp)
6550 {
6551         struct ib_cq *cq = qp->recv_cq;
6552         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6553         struct mlx5_ib_drain_cqe rdrain;
6554         struct ib_recv_wr rwr = {};
6555         const struct ib_recv_wr *bad_rwr;
6556         int ret;
6557         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6558         struct mlx5_core_dev *mdev = dev->mdev;
6559
6560         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6561         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6562                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6563                 return;
6564         }
6565
6566         rwr.wr_cqe = &rdrain.cqe;
6567         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6568         init_completion(&rdrain.done);
6569
6570         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6571         if (ret) {
6572                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6573                 return;
6574         }
6575
6576         handle_drain_completion(cq, &rdrain, dev);
6577 }
6578
6579 /**
6580  * Bind a qp to a counter. If @counter is NULL then bind the qp to
6581  * the default counter
6582  */
6583 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
6584 {
6585         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6586         struct mlx5_ib_qp *mqp = to_mqp(qp);
6587         int err = 0;
6588
6589         mutex_lock(&mqp->mutex);
6590         if (mqp->state == IB_QPS_RESET) {
6591                 qp->counter = counter;
6592                 goto out;
6593         }
6594
6595         if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
6596                 err = -EOPNOTSUPP;
6597                 goto out;
6598         }
6599
6600         if (mqp->state == IB_QPS_RTS) {
6601                 err = __mlx5_ib_qp_set_counter(qp, counter);
6602                 if (!err)
6603                         qp->counter = counter;
6604
6605                 goto out;
6606         }
6607
6608         mqp->counter_pending = 1;
6609         qp->counter = counter;
6610
6611 out:
6612         mutex_unlock(&mqp->mutex);
6613         return err;
6614 }