drivers/infiniband/hw/mlx5/odp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <rdma/ib_umem.h>
  34 #include <rdma/ib_umem_odp.h>
  35 #include <linux/kernel.h>
  36
  37 #include "mlx5_ib.h"
  38 #include "cmd.h"
  39 #include "qp.h"
  40
  41 #include <linux/mlx5/eq.h>
  42
  43 /* Contains the details of a pagefault. */
  44 struct mlx5_pagefault {
  45         u32                     bytes_committed;
  46         u32                     token;
  47         u8                      event_subtype;
  48         u8                      type;
  49         union {
  50                 /* Initiator or send message responder pagefault details. */
  51                 struct {
  52                         /* Received packet size, only valid for responders. */
  53                         u32     packet_size;
  54                         /*
  55                          * Number of resource holding WQE, depends on type.
  56                          */
  57                         u32     wq_num;
  58                         /*
  59                          * WQE index. Refers to either the send queue or
  60                          * receive queue, according to event_subtype.
  61                          */
  62                         u16     wqe_index;
  63                 } wqe;
  64                 /* RDMA responder pagefault details */
  65                 struct {
  66                         u32     r_key;
  67                         /*
  68                          * Received packet size, minimal size page fault
  69                          * resolution required for forward progress.
  70                          */
  71                         u32     packet_size;
  72                         u32     rdma_op_len;
  73                         u64     rdma_va;
  74                 } rdma;
  75         };
  76
  77         struct mlx5_ib_pf_eq    *eq;
  78         struct work_struct      work;
  79 };
  80
  81 #define MAX_PREFETCH_LEN (4*1024*1024U)
  82
  83 /* Timeout in ms to wait for an active mmu notifier to complete when handling
  84  * a pagefault. */
  85 #define MMU_NOTIFIER_TIMEOUT 1000
  86
  87 #define MLX5_IMR_MTT_BITS (30 - PAGE_SHIFT)
  88 #define MLX5_IMR_MTT_SHIFT (MLX5_IMR_MTT_BITS + PAGE_SHIFT)
  89 #define MLX5_IMR_MTT_ENTRIES BIT_ULL(MLX5_IMR_MTT_BITS)
  90 #define MLX5_IMR_MTT_SIZE BIT_ULL(MLX5_IMR_MTT_SHIFT)
  91 #define MLX5_IMR_MTT_MASK (~(MLX5_IMR_MTT_SIZE - 1))
  92
  93 #define MLX5_KSM_PAGE_SHIFT MLX5_IMR_MTT_SHIFT
  94
  95 static u64 mlx5_imr_ksm_entries;
  96
  97 static void populate_klm(struct mlx5_klm *pklm, size_t idx, size_t nentries,
  98                         struct mlx5_ib_mr *imr, int flags)
  99 {
 100         struct mlx5_klm *end = pklm + nentries;
 101
 102         if (flags & MLX5_IB_UPD_XLT_ZAP) {
 103                 for (; pklm != end; pklm++, idx++) {
 104                         pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE);
 105                         pklm->key = cpu_to_be32(imr->dev->null_mkey);
 106                         pklm->va = 0;
 107                 }
 108                 return;
 109         }
 110
 111         /*
 112          * The locking here is pretty subtle. Ideally the implicit_children
 113          * xarray would be protected by the umem_mutex, however that is not
 114          * possible. Instead this uses a weaker update-then-lock pattern:
 115          *
 116          *  srcu_read_lock()
 117          *    xa_store()
 118          *    mutex_lock(umem_mutex)
 119          *     mlx5_ib_update_xlt()
 120          *    mutex_unlock(umem_mutex)
 121          *    destroy lkey
 122          *
 123          * ie any change the xarray must be followed by the locked update_xlt
 124          * before destroying.
 125          *
 126          * The umem_mutex provides the acquire/release semantic needed to make
 127          * the xa_store() visible to a racing thread. While SRCU is not
 128          * technically required, using it gives consistent use of the SRCU
 129          * locking around the xarray.
 130          */
 131         lockdep_assert_held(&to_ib_umem_odp(imr->umem)->umem_mutex);
 132         lockdep_assert_held(&imr->dev->odp_srcu);
 133
 134         for (; pklm != end; pklm++, idx++) {
 135                 struct mlx5_ib_mr *mtt = xa_load(&imr->implicit_children, idx);
 136
 137                 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE);
 138                 if (mtt) {
 139                         pklm->key = cpu_to_be32(mtt->ibmr.lkey);
 140                         pklm->va = cpu_to_be64(idx * MLX5_IMR_MTT_SIZE);
 141                 } else {
 142                         pklm->key = cpu_to_be32(imr->dev->null_mkey);
 143                         pklm->va = 0;
 144                 }
 145         }
 146 }
 147
 148 static u64 umem_dma_to_mtt(dma_addr_t umem_dma)
 149 {
 150         u64 mtt_entry = umem_dma & ODP_DMA_ADDR_MASK;
 151
 152         if (umem_dma & ODP_READ_ALLOWED_BIT)
 153                 mtt_entry |= MLX5_IB_MTT_READ;
 154         if (umem_dma & ODP_WRITE_ALLOWED_BIT)
 155                 mtt_entry |= MLX5_IB_MTT_WRITE;
 156
 157         return mtt_entry;
 158 }
 159
 160 static void populate_mtt(__be64 *pas, size_t idx, size_t nentries,
 161                          struct mlx5_ib_mr *mr, int flags)
 162 {
 163         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 164         dma_addr_t pa;
 165         size_t i;
 166
 167         if (flags & MLX5_IB_UPD_XLT_ZAP)
 168                 return;
 169
 170         for (i = 0; i < nentries; i++) {
 171                 pa = odp->dma_list[idx + i];
 172                 pas[i] = cpu_to_be64(umem_dma_to_mtt(pa));
 173         }
 174 }
 175
 176 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
 177                            struct mlx5_ib_mr *mr, int flags)
 178 {
 179         if (flags & MLX5_IB_UPD_XLT_INDIRECT) {
 180                 populate_klm(xlt, idx, nentries, mr, flags);
 181         } else {
 182                 populate_mtt(xlt, idx, nentries, mr, flags);
 183         }
 184 }
 185
 186 static void dma_fence_odp_mr(struct mlx5_ib_mr *mr)
 187 {
 188         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 189
 190         /* Ensure mlx5_ib_invalidate_range() will not touch the MR any more */
 191         mutex_lock(&odp->umem_mutex);
 192         if (odp->npages) {
 193                 mlx5_mr_cache_invalidate(mr);
 194                 ib_umem_odp_unmap_dma_pages(odp, ib_umem_start(odp),
 195                                             ib_umem_end(odp));
 196                 WARN_ON(odp->npages);
 197         }
 198         odp->private = NULL;
 199         mutex_unlock(&odp->umem_mutex);
 200
 201         if (!mr->cache_ent) {
 202                 mlx5_core_destroy_mkey(mr->dev->mdev, &mr->mmkey);
 203                 WARN_ON(mr->descs);
 204         }
 205 }
 206
 207 /*
 208  * This must be called after the mr has been removed from implicit_children
 209  * and the SRCU synchronized.  NOTE: The MR does not necessarily have to be
 210  * empty here, parallel page faults could have raced with the free process and
 211  * added pages to it.
 212  */
 213 static void free_implicit_child_mr(struct mlx5_ib_mr *mr, bool need_imr_xlt)
 214 {
 215         struct mlx5_ib_mr *imr = mr->parent;
 216         struct ib_umem_odp *odp_imr = to_ib_umem_odp(imr->umem);
 217         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 218         unsigned long idx = ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT;
 219         int srcu_key;
 220
 221         /* implicit_child_mr's are not allowed to have deferred work */
 222         WARN_ON(atomic_read(&mr->num_deferred_work));
 223
 224         if (need_imr_xlt) {
 225                 srcu_key = srcu_read_lock(&mr->dev->odp_srcu);
 226                 mutex_lock(&odp_imr->umem_mutex);
 227                 mlx5_ib_update_xlt(mr->parent, idx, 1, 0,
 228                                    MLX5_IB_UPD_XLT_INDIRECT |
 229                                    MLX5_IB_UPD_XLT_ATOMIC);
 230                 mutex_unlock(&odp_imr->umem_mutex);
 231                 srcu_read_unlock(&mr->dev->odp_srcu, srcu_key);
 232         }
 233
 234         dma_fence_odp_mr(mr);
 235
 236         mr->parent = NULL;
 237         mlx5_mr_cache_free(mr->dev, mr);
 238         ib_umem_odp_release(odp);
 239         if (atomic_dec_and_test(&imr->num_deferred_work))
 240                 wake_up(&imr->q_deferred_work);
 241 }
 242
 243 static void free_implicit_child_mr_work(struct work_struct *work)
 244 {
 245         struct mlx5_ib_mr *mr =
 246                 container_of(work, struct mlx5_ib_mr, odp_destroy.work);
 247
 248         free_implicit_child_mr(mr, true);
 249 }
 250
 251 static void free_implicit_child_mr_rcu(struct rcu_head *head)
 252 {
 253         struct mlx5_ib_mr *mr =
 254                 container_of(head, struct mlx5_ib_mr, odp_destroy.rcu);
 255
 256         /* Freeing a MR is a sleeping operation, so bounce to a work queue */
 257         INIT_WORK(&mr->odp_destroy.work, free_implicit_child_mr_work);
 258         queue_work(system_unbound_wq, &mr->odp_destroy.work);
 259 }
 260
 261 static void destroy_unused_implicit_child_mr(struct mlx5_ib_mr *mr)
 262 {
 263         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 264         unsigned long idx = ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT;
 265         struct mlx5_ib_mr *imr = mr->parent;
 266
 267         xa_lock(&imr->implicit_children);
 268         /*
 269          * This can race with mlx5_ib_free_implicit_mr(), the first one to
 270          * reach the xa lock wins the race and destroys the MR.
 271          */
 272         if (__xa_cmpxchg(&imr->implicit_children, idx, mr, NULL, GFP_ATOMIC) !=
 273             mr)
 274                 goto out_unlock;
 275
 276         atomic_inc(&imr->num_deferred_work);
 277         call_srcu(&mr->dev->odp_srcu, &mr->odp_destroy.rcu,
 278                   free_implicit_child_mr_rcu);
 279
 280 out_unlock:
 281         xa_unlock(&imr->implicit_children);
 282 }
 283
 284 static bool mlx5_ib_invalidate_range(struct mmu_interval_notifier *mni,
 285                                      const struct mmu_notifier_range *range,
 286                                      unsigned long cur_seq)
 287 {
 288         struct ib_umem_odp *umem_odp =
 289                 container_of(mni, struct ib_umem_odp, notifier);
 290         struct mlx5_ib_mr *mr;
 291         const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT /
 292                                     sizeof(struct mlx5_mtt)) - 1;
 293         u64 idx = 0, blk_start_idx = 0;
 294         u64 invalidations = 0;
 295         unsigned long start;
 296         unsigned long end;
 297         int in_block = 0;
 298         u64 addr;
 299
 300         if (!mmu_notifier_range_blockable(range))
 301                 return false;
 302
 303         mutex_lock(&umem_odp->umem_mutex);
 304         mmu_interval_set_seq(mni, cur_seq);
 305         /*
 306          * If npages is zero then umem_odp->private may not be setup yet. This
 307          * does not complete until after the first page is mapped for DMA.
 308          */
 309         if (!umem_odp->npages)
 310                 goto out;
 311         mr = umem_odp->private;
 312
 313         start = max_t(u64, ib_umem_start(umem_odp), range->start);
 314         end = min_t(u64, ib_umem_end(umem_odp), range->end);
 315
 316         /*
 317          * Iteration one - zap the HW's MTTs. The notifiers_count ensures that
 318          * while we are doing the invalidation, no page fault will attempt to
 319          * overwrite the same MTTs.  Concurent invalidations might race us,
 320          * but they will write 0s as well, so no difference in the end result.
 321          */
 322         for (addr = start; addr < end; addr += BIT(umem_odp->page_shift)) {
 323                 idx = (addr - ib_umem_start(umem_odp)) >> umem_odp->page_shift;
 324                 /*
 325                  * Strive to write the MTTs in chunks, but avoid overwriting
 326                  * non-existing MTTs. The huristic here can be improved to
 327                  * estimate the cost of another UMR vs. the cost of bigger
 328                  * UMR.
 329                  */
 330                 if (umem_odp->dma_list[idx] &
 331                     (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) {
 332                         if (!in_block) {
 333                                 blk_start_idx = idx;
 334                                 in_block = 1;
 335                         }
 336
 337                         /* Count page invalidations */
 338                         invalidations += idx - blk_start_idx + 1;
 339                 } else {
 340                         u64 umr_offset = idx & umr_block_mask;
 341
 342                         if (in_block && umr_offset == 0) {
 343                                 mlx5_ib_update_xlt(mr, blk_start_idx,
 344                                                    idx - blk_start_idx, 0,
 345                                                    MLX5_IB_UPD_XLT_ZAP |
 346                                                    MLX5_IB_UPD_XLT_ATOMIC);
 347                                 in_block = 0;
 348                         }
 349                 }
 350         }
 351         if (in_block)
 352                 mlx5_ib_update_xlt(mr, blk_start_idx,
 353                                    idx - blk_start_idx + 1, 0,
 354                                    MLX5_IB_UPD_XLT_ZAP |
 355                                    MLX5_IB_UPD_XLT_ATOMIC);
 356
 357         mlx5_update_odp_stats(mr, invalidations, invalidations);
 358
 359         /*
 360          * We are now sure that the device will not access the
 361          * memory. We can safely unmap it, and mark it as dirty if
 362          * needed.
 363          */
 364
 365         ib_umem_odp_unmap_dma_pages(umem_odp, start, end);
 366
 367         if (unlikely(!umem_odp->npages && mr->parent))
 368                 destroy_unused_implicit_child_mr(mr);
 369 out:
 370         mutex_unlock(&umem_odp->umem_mutex);
 371         return true;
 372 }
 373
 374 const struct mmu_interval_notifier_ops mlx5_mn_ops = {
 375         .invalidate = mlx5_ib_invalidate_range,
 376 };
 377
 378 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
 379 {
 380         struct ib_odp_caps *caps = &dev->odp_caps;
 381
 382         memset(caps, 0, sizeof(*caps));
 383
 384         if (!MLX5_CAP_GEN(dev->mdev, pg) ||
 385             !mlx5_ib_can_use_umr(dev, true, 0))
 386                 return;
 387
 388         caps->general_caps = IB_ODP_SUPPORT;
 389
 390         if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
 391                 dev->odp_max_size = U64_MAX;
 392         else
 393                 dev->odp_max_size = BIT_ULL(MLX5_MAX_UMR_SHIFT + PAGE_SHIFT);
 394
 395         if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.send))
 396                 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SEND;
 397
 398         if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.srq_receive))
 399                 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV;
 400
 401         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.send))
 402                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SEND;
 403
 404         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.receive))
 405                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_RECV;
 406
 407         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.write))
 408                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_WRITE;
 409
 410         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.read))
 411                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_READ;
 412
 413         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.atomic))
 414                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_ATOMIC;
 415
 416         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.srq_receive))
 417                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV;
 418
 419         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.send))
 420                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_SEND;
 421
 422         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.receive))
 423                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_RECV;
 424
 425         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.write))
 426                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_WRITE;
 427
 428         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.read))
 429                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_READ;
 430
 431         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.atomic))
 432                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_ATOMIC;
 433
 434         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.srq_receive))
 435                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV;
 436
 437         if (MLX5_CAP_GEN(dev->mdev, fixed_buffer_size) &&
 438             MLX5_CAP_GEN(dev->mdev, null_mkey) &&
 439             MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) &&
 440             !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled))
 441                 caps->general_caps |= IB_ODP_SUPPORT_IMPLICIT;
 442 }
 443
 444 static void mlx5_ib_page_fault_resume(struct mlx5_ib_dev *dev,
 445                                       struct mlx5_pagefault *pfault,
 446                                       int error)
 447 {
 448         int wq_num = pfault->event_subtype == MLX5_PFAULT_SUBTYPE_WQE ?
 449                      pfault->wqe.wq_num : pfault->token;
 450         u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)] = {};
 451         int err;
 452
 453         MLX5_SET(page_fault_resume_in, in, opcode, MLX5_CMD_OP_PAGE_FAULT_RESUME);
 454         MLX5_SET(page_fault_resume_in, in, page_fault_type, pfault->type);
 455         MLX5_SET(page_fault_resume_in, in, token, pfault->token);
 456         MLX5_SET(page_fault_resume_in, in, wq_number, wq_num);
 457         MLX5_SET(page_fault_resume_in, in, error, !!error);
 458
 459         err = mlx5_cmd_exec_in(dev->mdev, page_fault_resume, in);
 460         if (err)
 461                 mlx5_ib_err(dev, "Failed to resolve the page fault on WQ 0x%x err %d\n",
 462                             wq_num, err);
 463 }
 464
 465 static struct mlx5_ib_mr *implicit_get_child_mr(struct mlx5_ib_mr *imr,
 466                                                 unsigned long idx)
 467 {
 468         struct ib_umem_odp *odp;
 469         struct mlx5_ib_mr *mr;
 470         struct mlx5_ib_mr *ret;
 471         int err;
 472
 473         odp = ib_umem_odp_alloc_child(to_ib_umem_odp(imr->umem),
 474                                       idx * MLX5_IMR_MTT_SIZE,
 475                                       MLX5_IMR_MTT_SIZE, &mlx5_mn_ops);
 476         if (IS_ERR(odp))
 477                 return ERR_CAST(odp);
 478
 479         ret = mr = mlx5_mr_cache_alloc(imr->dev, MLX5_IMR_MTT_CACHE_ENTRY);
 480         if (IS_ERR(mr))
 481                 goto out_umem;
 482
 483         mr->ibmr.pd = imr->ibmr.pd;
 484         mr->access_flags = imr->access_flags;
 485         mr->umem = &odp->umem;
 486         mr->ibmr.lkey = mr->mmkey.key;
 487         mr->ibmr.rkey = mr->mmkey.key;
 488         mr->mmkey.iova = idx * MLX5_IMR_MTT_SIZE;
 489         mr->parent = imr;
 490         odp->private = mr;
 491
 492         err = mlx5_ib_update_xlt(mr, 0,
 493                                  MLX5_IMR_MTT_ENTRIES,
 494                                  PAGE_SHIFT,
 495                                  MLX5_IB_UPD_XLT_ZAP |
 496                                  MLX5_IB_UPD_XLT_ENABLE);
 497         if (err) {
 498                 ret = ERR_PTR(err);
 499                 goto out_mr;
 500         }
 501
 502         /*
 503          * Once the store to either xarray completes any error unwind has to
 504          * use synchronize_srcu(). Avoid this with xa_reserve()
 505          */
 506         ret = xa_cmpxchg(&imr->implicit_children, idx, NULL, mr,
 507                          GFP_KERNEL);
 508         if (unlikely(ret)) {
 509                 if (xa_is_err(ret)) {
 510                         ret = ERR_PTR(xa_err(ret));
 511                         goto out_mr;
 512                 }
 513                 /*
 514                  * Another thread beat us to creating the child mr, use
 515                  * theirs.
 516                  */
 517                 goto out_mr;
 518         }
 519
 520         mlx5_ib_dbg(imr->dev, "key %x mr %p\n", mr->mmkey.key, mr);
 521         return mr;
 522
 523 out_mr:
 524         mlx5_mr_cache_free(imr->dev, mr);
 525 out_umem:
 526         ib_umem_odp_release(odp);
 527         return ret;
 528 }
 529
 530 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
 531                                              struct ib_udata *udata,
 532                                              int access_flags)
 533 {
 534         struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device);
 535         struct ib_umem_odp *umem_odp;
 536         struct mlx5_ib_mr *imr;
 537         int err;
 538
 539         umem_odp = ib_umem_odp_alloc_implicit(&dev->ib_dev, access_flags);
 540         if (IS_ERR(umem_odp))
 541                 return ERR_CAST(umem_odp);
 542
 543         imr = mlx5_mr_cache_alloc(dev, MLX5_IMR_KSM_CACHE_ENTRY);
 544         if (IS_ERR(imr)) {
 545                 err = PTR_ERR(imr);
 546                 goto out_umem;
 547         }
 548
 549         imr->ibmr.pd = &pd->ibpd;
 550         imr->access_flags = access_flags;
 551         imr->mmkey.iova = 0;
 552         imr->umem = &umem_odp->umem;
 553         imr->ibmr.lkey = imr->mmkey.key;
 554         imr->ibmr.rkey = imr->mmkey.key;
 555         imr->umem = &umem_odp->umem;
 556         imr->is_odp_implicit = true;
 557         atomic_set(&imr->num_deferred_work, 0);
 558         init_waitqueue_head(&imr->q_deferred_work);
 559         xa_init(&imr->implicit_children);
 560
 561         err = mlx5_ib_update_xlt(imr, 0,
 562                                  mlx5_imr_ksm_entries,
 563                                  MLX5_KSM_PAGE_SHIFT,
 564                                  MLX5_IB_UPD_XLT_INDIRECT |
 565                                  MLX5_IB_UPD_XLT_ZAP |
 566                                  MLX5_IB_UPD_XLT_ENABLE);
 567         if (err)
 568                 goto out_mr;
 569
 570         err = xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(imr->mmkey.key),
 571                               &imr->mmkey, GFP_KERNEL));
 572         if (err)
 573                 goto out_mr;
 574
 575         mlx5_ib_dbg(dev, "key %x mr %p\n", imr->mmkey.key, imr);
 576         return imr;
 577 out_mr:
 578         mlx5_ib_err(dev, "Failed to register MKEY %d\n", err);
 579         mlx5_mr_cache_free(dev, imr);
 580 out_umem:
 581         ib_umem_odp_release(umem_odp);
 582         return ERR_PTR(err);
 583 }
 584
 585 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *imr)
 586 {
 587         struct ib_umem_odp *odp_imr = to_ib_umem_odp(imr->umem);
 588         struct mlx5_ib_dev *dev = imr->dev;
 589         struct list_head destroy_list;
 590         struct mlx5_ib_mr *mtt;
 591         struct mlx5_ib_mr *tmp;
 592         unsigned long idx;
 593
 594         INIT_LIST_HEAD(&destroy_list);
 595
 596         xa_erase(&dev->odp_mkeys, mlx5_base_mkey(imr->mmkey.key));
 597         /*
 598          * This stops the SRCU protected page fault path from touching either
 599          * the imr or any children. The page fault path can only reach the
 600          * children xarray via the imr.
 601          */
 602         synchronize_srcu(&dev->odp_srcu);
 603
 604         xa_lock(&imr->implicit_children);
 605         xa_for_each (&imr->implicit_children, idx, mtt) {
 606                 __xa_erase(&imr->implicit_children, idx);
 607                 list_add(&mtt->odp_destroy.elm, &destroy_list);
 608         }
 609         xa_unlock(&imr->implicit_children);
 610
 611         /*
 612          * num_deferred_work can only be incremented inside the odp_srcu, or
 613          * under xa_lock while the child is in the xarray. Thus at this point
 614          * it is only decreasing, and all work holding it is now on the wq.
 615          */
 616         wait_event(imr->q_deferred_work, !atomic_read(&imr->num_deferred_work));
 617
 618         /*
 619          * Fence the imr before we destroy the children. This allows us to
 620          * skip updating the XLT of the imr during destroy of the child mkey
 621          * the imr points to.
 622          */
 623         mlx5_mr_cache_invalidate(imr);
 624
 625         list_for_each_entry_safe (mtt, tmp, &destroy_list, odp_destroy.elm)
 626                 free_implicit_child_mr(mtt, false);
 627
 628         mlx5_mr_cache_free(dev, imr);
 629         ib_umem_odp_release(odp_imr);
 630 }
 631
 632 /**
 633  * mlx5_ib_fence_odp_mr - Stop all access to the ODP MR
 634  * @mr: to fence
 635  *
 636  * On return no parallel threads will be touching this MR and no DMA will be
 637  * active.
 638  */
 639 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr)
 640 {
 641         /* Prevent new page faults and prefetch requests from succeeding */
 642         xa_erase(&mr->dev->odp_mkeys, mlx5_base_mkey(mr->mmkey.key));
 643
 644         /* Wait for all running page-fault handlers to finish. */
 645         synchronize_srcu(&mr->dev->odp_srcu);
 646
 647         wait_event(mr->q_deferred_work, !atomic_read(&mr->num_deferred_work));
 648
 649         dma_fence_odp_mr(mr);
 650 }
 651
 652 #define MLX5_PF_FLAGS_DOWNGRADE BIT(1)
 653 static int pagefault_real_mr(struct mlx5_ib_mr *mr, struct ib_umem_odp *odp,
 654                              u64 user_va, size_t bcnt, u32 *bytes_mapped,
 655                              u32 flags)
 656 {
 657         int page_shift, ret, np;
 658         bool downgrade = flags & MLX5_PF_FLAGS_DOWNGRADE;
 659         unsigned long current_seq;
 660         u64 access_mask;
 661         u64 start_idx;
 662
 663         page_shift = odp->page_shift;
 664         start_idx = (user_va - ib_umem_start(odp)) >> page_shift;
 665         access_mask = ODP_READ_ALLOWED_BIT;
 666
 667         if (odp->umem.writable && !downgrade)
 668                 access_mask |= ODP_WRITE_ALLOWED_BIT;
 669
 670         current_seq = mmu_interval_read_begin(&odp->notifier);
 671
 672         np = ib_umem_odp_map_dma_pages(odp, user_va, bcnt, access_mask,
 673                                        current_seq);
 674         if (np < 0)
 675                 return np;
 676
 677         mutex_lock(&odp->umem_mutex);
 678         if (!mmu_interval_read_retry(&odp->notifier, current_seq)) {
 679                 /*
 680                  * No need to check whether the MTTs really belong to
 681                  * this MR, since ib_umem_odp_map_dma_pages already
 682                  * checks this.
 683                  */
 684                 ret = mlx5_ib_update_xlt(mr, start_idx, np,
 685                                          page_shift, MLX5_IB_UPD_XLT_ATOMIC);
 686         } else {
 687                 ret = -EAGAIN;
 688         }
 689         mutex_unlock(&odp->umem_mutex);
 690
 691         if (ret < 0) {
 692                 if (ret != -EAGAIN)
 693                         mlx5_ib_err(mr->dev,
 694                                     "Failed to update mkey page tables\n");
 695                 goto out;
 696         }
 697
 698         if (bytes_mapped) {
 699                 u32 new_mappings = (np << page_shift) -
 700                         (user_va - round_down(user_va, 1 << page_shift));
 701
 702                 *bytes_mapped += min_t(u32, new_mappings, bcnt);
 703         }
 704
 705         return np << (page_shift - PAGE_SHIFT);
 706
 707 out:
 708         return ret;
 709 }
 710
 711 static int pagefault_implicit_mr(struct mlx5_ib_mr *imr,
 712                                  struct ib_umem_odp *odp_imr, u64 user_va,
 713                                  size_t bcnt, u32 *bytes_mapped, u32 flags)
 714 {
 715         unsigned long end_idx = (user_va + bcnt - 1) >> MLX5_IMR_MTT_SHIFT;
 716         unsigned long upd_start_idx = end_idx + 1;
 717         unsigned long upd_len = 0;
 718         unsigned long npages = 0;
 719         int err;
 720         int ret;
 721
 722         if (unlikely(user_va >= mlx5_imr_ksm_entries * MLX5_IMR_MTT_SIZE ||
 723                      mlx5_imr_ksm_entries * MLX5_IMR_MTT_SIZE - user_va < bcnt))
 724                 return -EFAULT;
 725
 726         /* Fault each child mr that intersects with our interval. */
 727         while (bcnt) {
 728                 unsigned long idx = user_va >> MLX5_IMR_MTT_SHIFT;
 729                 struct ib_umem_odp *umem_odp;
 730                 struct mlx5_ib_mr *mtt;
 731                 u64 len;
 732
 733                 mtt = xa_load(&imr->implicit_children, idx);
 734                 if (unlikely(!mtt)) {
 735                         mtt = implicit_get_child_mr(imr, idx);
 736                         if (IS_ERR(mtt)) {
 737                                 ret = PTR_ERR(mtt);
 738                                 goto out;
 739                         }
 740                         upd_start_idx = min(upd_start_idx, idx);
 741                         upd_len = idx - upd_start_idx + 1;
 742                 }
 743
 744                 umem_odp = to_ib_umem_odp(mtt->umem);
 745                 len = min_t(u64, user_va + bcnt, ib_umem_end(umem_odp)) -
 746                       user_va;
 747
 748                 ret = pagefault_real_mr(mtt, umem_odp, user_va, len,
 749                                         bytes_mapped, flags);
 750                 if (ret < 0)
 751                         goto out;
 752                 user_va += len;
 753                 bcnt -= len;
 754                 npages += ret;
 755         }
 756
 757         ret = npages;
 758
 759         /*
 760          * Any time the implicit_children are changed we must perform an
 761          * update of the xlt before exiting to ensure the HW and the
 762          * implicit_children remains synchronized.
 763          */
 764 out:
 765         if (likely(!upd_len))
 766                 return ret;
 767
 768         /*
 769          * Notice this is not strictly ordered right, the KSM is updated after
 770          * the implicit_children is updated, so a parallel page fault could
 771          * see a MR that is not yet visible in the KSM.  This is similar to a
 772          * parallel page fault seeing a MR that is being concurrently removed
 773          * from the KSM. Both of these improbable situations are resolved
 774          * safely by resuming the HW and then taking another page fault. The
 775          * next pagefault handler will see the new information.
 776          */
 777         mutex_lock(&odp_imr->umem_mutex);
 778         err = mlx5_ib_update_xlt(imr, upd_start_idx, upd_len, 0,
 779                                  MLX5_IB_UPD_XLT_INDIRECT |
 780                                          MLX5_IB_UPD_XLT_ATOMIC);
 781         mutex_unlock(&odp_imr->umem_mutex);
 782         if (err) {
 783                 mlx5_ib_err(imr->dev, "Failed to update PAS\n");
 784                 return err;
 785         }
 786         return ret;
 787 }
 788
 789 /*
 790  * Returns:
 791  *  -EFAULT: The io_virt->bcnt is not within the MR, it covers pages that are
 792  *           not accessible, or the MR is no longer valid.
 793  *  -EAGAIN/-ENOMEM: The operation should be retried
 794  *
 795  *  -EINVAL/others: General internal malfunction
 796  *  >0: Number of pages mapped
 797  */
 798 static int pagefault_mr(struct mlx5_ib_mr *mr, u64 io_virt, size_t bcnt,
 799                         u32 *bytes_mapped, u32 flags)
 800 {
 801         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 802
 803         if (unlikely(io_virt < mr->mmkey.iova))
 804                 return -EFAULT;
 805
 806         if (!odp->is_implicit_odp) {
 807                 u64 user_va;
 808
 809                 if (check_add_overflow(io_virt - mr->mmkey.iova,
 810                                        (u64)odp->umem.address, &user_va))
 811                         return -EFAULT;
 812                 if (unlikely(user_va >= ib_umem_end(odp) ||
 813                              ib_umem_end(odp) - user_va < bcnt))
 814                         return -EFAULT;
 815                 return pagefault_real_mr(mr, odp, user_va, bcnt, bytes_mapped,
 816                                          flags);
 817         }
 818         return pagefault_implicit_mr(mr, odp, io_virt, bcnt, bytes_mapped,
 819                                      flags);
 820 }
 821
 822 struct pf_frame {
 823         struct pf_frame *next;
 824         u32 key;
 825         u64 io_virt;
 826         size_t bcnt;
 827         int depth;
 828 };
 829
 830 static bool mkey_is_eq(struct mlx5_core_mkey *mmkey, u32 key)
 831 {
 832         if (!mmkey)
 833                 return false;
 834         if (mmkey->type == MLX5_MKEY_MW)
 835                 return mlx5_base_mkey(mmkey->key) == mlx5_base_mkey(key);
 836         return mmkey->key == key;
 837 }
 838
 839 static int get_indirect_num_descs(struct mlx5_core_mkey *mmkey)
 840 {
 841         struct mlx5_ib_mw *mw;
 842         struct mlx5_ib_devx_mr *devx_mr;
 843
 844         if (mmkey->type == MLX5_MKEY_MW) {
 845                 mw = container_of(mmkey, struct mlx5_ib_mw, mmkey);
 846                 return mw->ndescs;
 847         }
 848
 849         devx_mr = container_of(mmkey, struct mlx5_ib_devx_mr,
 850                                mmkey);
 851         return devx_mr->ndescs;
 852 }
 853
 854 /*
 855  * Handle a single data segment in a page-fault WQE or RDMA region.
 856  *
 857  * Returns number of OS pages retrieved on success. The caller may continue to
 858  * the next data segment.
 859  * Can return the following error codes:
 860  * -EAGAIN to designate a temporary error. The caller will abort handling the
 861  *  page fault and resolve it.
 862  * -EFAULT when there's an error mapping the requested pages. The caller will
 863  *  abort the page fault handling.
 864  */
 865 static int pagefault_single_data_segment(struct mlx5_ib_dev *dev,
 866                                          struct ib_pd *pd, u32 key,
 867                                          u64 io_virt, size_t bcnt,
 868                                          u32 *bytes_committed,
 869                                          u32 *bytes_mapped)
 870 {
 871         int npages = 0, srcu_key, ret, i, outlen, cur_outlen = 0, depth = 0;
 872         struct pf_frame *head = NULL, *frame;
 873         struct mlx5_core_mkey *mmkey;
 874         struct mlx5_ib_mr *mr;
 875         struct mlx5_klm *pklm;
 876         u32 *out = NULL;
 877         size_t offset;
 878         int ndescs;
 879
 880         srcu_key = srcu_read_lock(&dev->odp_srcu);
 881
 882         io_virt += *bytes_committed;
 883         bcnt -= *bytes_committed;
 884
 885 next_mr:
 886         mmkey = xa_load(&dev->odp_mkeys, mlx5_base_mkey(key));
 887         if (!mmkey) {
 888                 mlx5_ib_dbg(
 889                         dev,
 890                         "skipping non ODP MR (lkey=0x%06x) in page fault handler.\n",
 891                         key);
 892                 if (bytes_mapped)
 893                         *bytes_mapped += bcnt;
 894                 /*
 895                  * The user could specify a SGL with multiple lkeys and only
 896                  * some of them are ODP. Treat the non-ODP ones as fully
 897                  * faulted.
 898                  */
 899                 ret = 0;
 900                 goto srcu_unlock;
 901         }
 902         if (!mkey_is_eq(mmkey, key)) {
 903                 mlx5_ib_dbg(dev, "failed to find mkey %x\n", key);
 904                 ret = -EFAULT;
 905                 goto srcu_unlock;
 906         }
 907
 908         switch (mmkey->type) {
 909         case MLX5_MKEY_MR:
 910                 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey);
 911
 912                 ret = pagefault_mr(mr, io_virt, bcnt, bytes_mapped, 0);
 913                 if (ret < 0)
 914                         goto srcu_unlock;
 915
 916                 /*
 917                  * When prefetching a page, page fault is generated
 918                  * in order to bring the page to the main memory.
 919                  * In the current flow, page faults are being counted.
 920                  */
 921                 mlx5_update_odp_stats(mr, faults, ret);
 922
 923                 npages += ret;
 924                 ret = 0;
 925                 break;
 926
 927         case MLX5_MKEY_MW:
 928         case MLX5_MKEY_INDIRECT_DEVX:
 929                 ndescs = get_indirect_num_descs(mmkey);
 930
 931                 if (depth >= MLX5_CAP_GEN(dev->mdev, max_indirection)) {
 932                         mlx5_ib_dbg(dev, "indirection level exceeded\n");
 933                         ret = -EFAULT;
 934                         goto srcu_unlock;
 935                 }
 936
 937                 outlen = MLX5_ST_SZ_BYTES(query_mkey_out) +
 938                         sizeof(*pklm) * (ndescs - 2);
 939
 940                 if (outlen > cur_outlen) {
 941                         kfree(out);
 942                         out = kzalloc(outlen, GFP_KERNEL);
 943                         if (!out) {
 944                                 ret = -ENOMEM;
 945                                 goto srcu_unlock;
 946                         }
 947                         cur_outlen = outlen;
 948                 }
 949
 950                 pklm = (struct mlx5_klm *)MLX5_ADDR_OF(query_mkey_out, out,
 951                                                        bsf0_klm0_pas_mtt0_1);
 952
 953                 ret = mlx5_core_query_mkey(dev->mdev, mmkey, out, outlen);
 954                 if (ret)
 955                         goto srcu_unlock;
 956
 957                 offset = io_virt - MLX5_GET64(query_mkey_out, out,
 958                                               memory_key_mkey_entry.start_addr);
 959
 960                 for (i = 0; bcnt && i < ndescs; i++, pklm++) {
 961                         if (offset >= be32_to_cpu(pklm->bcount)) {
 962                                 offset -= be32_to_cpu(pklm->bcount);
 963                                 continue;
 964                         }
 965
 966                         frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 967                         if (!frame) {
 968                                 ret = -ENOMEM;
 969                                 goto srcu_unlock;
 970                         }
 971
 972                         frame->key = be32_to_cpu(pklm->key);
 973                         frame->io_virt = be64_to_cpu(pklm->va) + offset;
 974                         frame->bcnt = min_t(size_t, bcnt,
 975                                             be32_to_cpu(pklm->bcount) - offset);
 976                         frame->depth = depth + 1;
 977                         frame->next = head;
 978                         head = frame;
 979
 980                         bcnt -= frame->bcnt;
 981                         offset = 0;
 982                 }
 983                 break;
 984
 985         default:
 986                 mlx5_ib_dbg(dev, "wrong mkey type %d\n", mmkey->type);
 987                 ret = -EFAULT;
 988                 goto srcu_unlock;
 989         }
 990
 991         if (head) {
 992                 frame = head;
 993                 head = frame->next;
 994
 995                 key = frame->key;
 996                 io_virt = frame->io_virt;
 997                 bcnt = frame->bcnt;
 998                 depth = frame->depth;
 999                 kfree(frame);
1000
1001                 goto next_mr;
1002         }
1003
1004 srcu_unlock:
1005         while (head) {
1006                 frame = head;
1007                 head = frame->next;
1008                 kfree(frame);
1009         }
1010         kfree(out);
1011
1012         srcu_read_unlock(&dev->odp_srcu, srcu_key);
1013         *bytes_committed = 0;
1014         return ret ? ret : npages;
1015 }
1016
1017 /**
1018  * Parse a series of data segments for page fault handling.
1019  *
1020  * @pfault contains page fault information.
1021  * @wqe points at the first data segment in the WQE.
1022  * @wqe_end points after the end of the WQE.
1023  * @bytes_mapped receives the number of bytes that the function was able to
1024  *               map. This allows the caller to decide intelligently whether
1025  *               enough memory was mapped to resolve the page fault
1026  *               successfully (e.g. enough for the next MTU, or the entire
1027  *               WQE).
1028  * @total_wqe_bytes receives the total data size of this WQE in bytes (minus
1029  *                  the committed bytes).
1030  *
1031  * Returns the number of pages loaded if positive, zero for an empty WQE, or a
1032  * negative error code.
1033  */
1034 static int pagefault_data_segments(struct mlx5_ib_dev *dev,
1035                                    struct mlx5_pagefault *pfault,
1036                                    void *wqe,
1037                                    void *wqe_end, u32 *bytes_mapped,
1038                                    u32 *total_wqe_bytes, bool receive_queue)
1039 {
1040         int ret = 0, npages = 0;
1041         u64 io_virt;
1042         u32 key;
1043         u32 byte_count;
1044         size_t bcnt;
1045         int inline_segment;
1046
1047         if (bytes_mapped)
1048                 *bytes_mapped = 0;
1049         if (total_wqe_bytes)
1050                 *total_wqe_bytes = 0;
1051
1052         while (wqe < wqe_end) {
1053                 struct mlx5_wqe_data_seg *dseg = wqe;
1054
1055                 io_virt = be64_to_cpu(dseg->addr);
1056                 key = be32_to_cpu(dseg->lkey);
1057                 byte_count = be32_to_cpu(dseg->byte_count);
1058                 inline_segment = !!(byte_count &  MLX5_INLINE_SEG);
1059                 bcnt           = byte_count & ~MLX5_INLINE_SEG;
1060
1061                 if (inline_segment) {
1062                         bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK;
1063                         wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt,
1064                                      16);
1065                 } else {
1066                         wqe += sizeof(*dseg);
1067                 }
1068
1069                 /* receive WQE end of sg list. */
1070                 if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY &&
1071                     io_virt == 0)
1072                         break;
1073
1074                 if (!inline_segment && total_wqe_bytes) {
1075                         *total_wqe_bytes += bcnt - min_t(size_t, bcnt,
1076                                         pfault->bytes_committed);
1077                 }
1078
1079                 /* A zero length data segment designates a length of 2GB. */
1080                 if (bcnt == 0)
1081                         bcnt = 1U << 31;
1082
1083                 if (inline_segment || bcnt <= pfault->bytes_committed) {
1084                         pfault->bytes_committed -=
1085                                 min_t(size_t, bcnt,
1086                                       pfault->bytes_committed);
1087                         continue;
1088                 }
1089
1090                 ret = pagefault_single_data_segment(dev, NULL, key,
1091                                                     io_virt, bcnt,
1092                                                     &pfault->bytes_committed,
1093                                                     bytes_mapped);
1094                 if (ret < 0)
1095                         break;
1096                 npages += ret;
1097         }
1098
1099         return ret < 0 ? ret : npages;
1100 }
1101
1102 /*
1103  * Parse initiator WQE. Advances the wqe pointer to point at the
1104  * scatter-gather list, and set wqe_end to the end of the WQE.
1105  */
1106 static int mlx5_ib_mr_initiator_pfault_handler(
1107         struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault,
1108         struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length)
1109 {
1110         struct mlx5_wqe_ctrl_seg *ctrl = *wqe;
1111         u16 wqe_index = pfault->wqe.wqe_index;
1112         struct mlx5_base_av *av;
1113         unsigned ds, opcode;
1114         u32 qpn = qp->trans_qp.base.mqp.qpn;
1115
1116         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
1117         if (ds * MLX5_WQE_DS_UNITS > wqe_length) {
1118                 mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n",
1119                             ds, wqe_length);
1120                 return -EFAULT;
1121         }
1122
1123         if (ds == 0) {
1124                 mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n",
1125                             wqe_index, qpn);
1126                 return -EFAULT;
1127         }
1128
1129         *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS;
1130         *wqe += sizeof(*ctrl);
1131
1132         opcode = be32_to_cpu(ctrl->opmod_idx_opcode) &
1133                  MLX5_WQE_CTRL_OPCODE_MASK;
1134
1135         if (qp->ibqp.qp_type == IB_QPT_XRC_INI)
1136                 *wqe += sizeof(struct mlx5_wqe_xrc_seg);
1137
1138         if (qp->type == IB_QPT_UD || qp->type == MLX5_IB_QPT_DCI) {
1139                 av = *wqe;
1140                 if (av->dqp_dct & cpu_to_be32(MLX5_EXTENDED_UD_AV))
1141                         *wqe += sizeof(struct mlx5_av);
1142                 else
1143                         *wqe += sizeof(struct mlx5_base_av);
1144         }
1145
1146         switch (opcode) {
1147         case MLX5_OPCODE_RDMA_WRITE:
1148         case MLX5_OPCODE_RDMA_WRITE_IMM:
1149         case MLX5_OPCODE_RDMA_READ:
1150                 *wqe += sizeof(struct mlx5_wqe_raddr_seg);
1151                 break;
1152         case MLX5_OPCODE_ATOMIC_CS:
1153         case MLX5_OPCODE_ATOMIC_FA:
1154                 *wqe += sizeof(struct mlx5_wqe_raddr_seg);
1155                 *wqe += sizeof(struct mlx5_wqe_atomic_seg);
1156                 break;
1157         }
1158
1159         return 0;
1160 }
1161
1162 /*
1163  * Parse responder WQE and set wqe_end to the end of the WQE.
1164  */
1165 static int mlx5_ib_mr_responder_pfault_handler_srq(struct mlx5_ib_dev *dev,
1166                                                    struct mlx5_ib_srq *srq,
1167                                                    void **wqe, void **wqe_end,
1168                                                    int wqe_length)
1169 {
1170         int wqe_size = 1 << srq->msrq.wqe_shift;
1171
1172         if (wqe_size > wqe_length) {
1173                 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n");
1174                 return -EFAULT;
1175         }
1176
1177         *wqe_end = *wqe + wqe_size;
1178         *wqe += sizeof(struct mlx5_wqe_srq_next_seg);
1179
1180         return 0;
1181 }
1182
1183 static int mlx5_ib_mr_responder_pfault_handler_rq(struct mlx5_ib_dev *dev,
1184                                                   struct mlx5_ib_qp *qp,
1185                                                   void *wqe, void **wqe_end,
1186                                                   int wqe_length)
1187 {
1188         struct mlx5_ib_wq *wq = &qp->rq;
1189         int wqe_size = 1 << wq->wqe_shift;
1190
1191         if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) {
1192                 mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n");
1193                 return -EFAULT;
1194         }
1195
1196         if (wqe_size > wqe_length) {
1197                 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n");
1198                 return -EFAULT;
1199         }
1200
1201         *wqe_end = wqe + wqe_size;
1202
1203         return 0;
1204 }
1205
1206 static inline struct mlx5_core_rsc_common *odp_get_rsc(struct mlx5_ib_dev *dev,
1207                                                        u32 wq_num, int pf_type)
1208 {
1209         struct mlx5_core_rsc_common *common = NULL;
1210         struct mlx5_core_srq *srq;
1211
1212         switch (pf_type) {
1213         case MLX5_WQE_PF_TYPE_RMP:
1214                 srq = mlx5_cmd_get_srq(dev, wq_num);
1215                 if (srq)
1216                         common = &srq->common;
1217                 break;
1218         case MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE:
1219         case MLX5_WQE_PF_TYPE_RESP:
1220         case MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC:
1221                 common = mlx5_core_res_hold(dev, wq_num, MLX5_RES_QP);
1222                 break;
1223         default:
1224                 break;
1225         }
1226
1227         return common;
1228 }
1229
1230 static inline struct mlx5_ib_qp *res_to_qp(struct mlx5_core_rsc_common *res)
1231 {
1232         struct mlx5_core_qp *mqp = (struct mlx5_core_qp *)res;
1233
1234         return to_mibqp(mqp);
1235 }
1236
1237 static inline struct mlx5_ib_srq *res_to_srq(struct mlx5_core_rsc_common *res)
1238 {
1239         struct mlx5_core_srq *msrq =
1240                 container_of(res, struct mlx5_core_srq, common);
1241
1242         return to_mibsrq(msrq);
1243 }
1244
1245 static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_dev *dev,
1246                                           struct mlx5_pagefault *pfault)
1247 {
1248         bool sq = pfault->type & MLX5_PFAULT_REQUESTOR;
1249         u16 wqe_index = pfault->wqe.wqe_index;
1250         void *wqe, *wqe_start = NULL, *wqe_end = NULL;
1251         u32 bytes_mapped, total_wqe_bytes;
1252         struct mlx5_core_rsc_common *res;
1253         int resume_with_error = 1;
1254         struct mlx5_ib_qp *qp;
1255         size_t bytes_copied;
1256         int ret = 0;
1257
1258         res = odp_get_rsc(dev, pfault->wqe.wq_num, pfault->type);
1259         if (!res) {
1260                 mlx5_ib_dbg(dev, "wqe page fault for missing resource %d\n", pfault->wqe.wq_num);
1261                 return;
1262         }
1263
1264         if (res->res != MLX5_RES_QP && res->res != MLX5_RES_SRQ &&
1265             res->res != MLX5_RES_XSRQ) {
1266                 mlx5_ib_err(dev, "wqe page fault for unsupported type %d\n",
1267                             pfault->type);
1268                 goto resolve_page_fault;
1269         }
1270
1271         wqe_start = (void *)__get_free_page(GFP_KERNEL);
1272         if (!wqe_start) {
1273                 mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n");
1274                 goto resolve_page_fault;
1275         }
1276
1277         wqe = wqe_start;
1278         qp = (res->res == MLX5_RES_QP) ? res_to_qp(res) : NULL;
1279         if (qp && sq) {
1280                 ret = mlx5_ib_read_wqe_sq(qp, wqe_index, wqe, PAGE_SIZE,
1281                                           &bytes_copied);
1282                 if (ret)
1283                         goto read_user;
1284                 ret = mlx5_ib_mr_initiator_pfault_handler(
1285                         dev, pfault, qp, &wqe, &wqe_end, bytes_copied);
1286         } else if (qp && !sq) {
1287                 ret = mlx5_ib_read_wqe_rq(qp, wqe_index, wqe, PAGE_SIZE,
1288                                           &bytes_copied);
1289                 if (ret)
1290                         goto read_user;
1291                 ret = mlx5_ib_mr_responder_pfault_handler_rq(
1292                         dev, qp, wqe, &wqe_end, bytes_copied);
1293         } else if (!qp) {
1294                 struct mlx5_ib_srq *srq = res_to_srq(res);
1295
1296                 ret = mlx5_ib_read_wqe_srq(srq, wqe_index, wqe, PAGE_SIZE,
1297                                            &bytes_copied);
1298                 if (ret)
1299                         goto read_user;
1300                 ret = mlx5_ib_mr_responder_pfault_handler_srq(
1301                         dev, srq, &wqe, &wqe_end, bytes_copied);
1302         }
1303
1304         if (ret < 0 || wqe >= wqe_end)
1305                 goto resolve_page_fault;
1306
1307         ret = pagefault_data_segments(dev, pfault, wqe, wqe_end, &bytes_mapped,
1308                                       &total_wqe_bytes, !sq);
1309         if (ret == -EAGAIN)
1310                 goto out;
1311
1312         if (ret < 0 || total_wqe_bytes > bytes_mapped)
1313                 goto resolve_page_fault;
1314
1315 out:
1316         ret = 0;
1317         resume_with_error = 0;
1318
1319 read_user:
1320         if (ret)
1321                 mlx5_ib_err(
1322                         dev,
1323                         "Failed reading a WQE following page fault, error %d, wqe_index %x, qpn %x\n",
1324                         ret, wqe_index, pfault->token);
1325
1326 resolve_page_fault:
1327         mlx5_ib_page_fault_resume(dev, pfault, resume_with_error);
1328         mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, type: 0x%x\n",
1329                     pfault->wqe.wq_num, resume_with_error,
1330                     pfault->type);
1331         mlx5_core_res_put(res);
1332         free_page((unsigned long)wqe_start);
1333 }
1334
1335 static int pages_in_range(u64 address, u32 length)
1336 {
1337         return (ALIGN(address + length, PAGE_SIZE) -
1338                 (address & PAGE_MASK)) >> PAGE_SHIFT;
1339 }
1340
1341 static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev,
1342                                            struct mlx5_pagefault *pfault)
1343 {
1344         u64 address;
1345         u32 length;
1346         u32 prefetch_len = pfault->bytes_committed;
1347         int prefetch_activated = 0;
1348         u32 rkey = pfault->rdma.r_key;
1349         int ret;
1350
1351         /* The RDMA responder handler handles the page fault in two parts.
1352          * First it brings the necessary pages for the current packet
1353          * (and uses the pfault context), and then (after resuming the QP)
1354          * prefetches more pages. The second operation cannot use the pfault
1355          * context and therefore uses the dummy_pfault context allocated on
1356          * the stack */
1357         pfault->rdma.rdma_va += pfault->bytes_committed;
1358         pfault->rdma.rdma_op_len -= min(pfault->bytes_committed,
1359                                          pfault->rdma.rdma_op_len);
1360         pfault->bytes_committed = 0;
1361
1362         address = pfault->rdma.rdma_va;
1363         length  = pfault->rdma.rdma_op_len;
1364
1365         /* For some operations, the hardware cannot tell the exact message
1366          * length, and in those cases it reports zero. Use prefetch
1367          * logic. */
1368         if (length == 0) {
1369                 prefetch_activated = 1;
1370                 length = pfault->rdma.packet_size;
1371                 prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len);
1372         }
1373
1374         ret = pagefault_single_data_segment(dev, NULL, rkey, address, length,
1375                                             &pfault->bytes_committed, NULL);
1376         if (ret == -EAGAIN) {
1377                 /* We're racing with an invalidation, don't prefetch */
1378                 prefetch_activated = 0;
1379         } else if (ret < 0 || pages_in_range(address, length) > ret) {
1380                 mlx5_ib_page_fault_resume(dev, pfault, 1);
1381                 if (ret != -ENOENT)
1382                         mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%x, type: 0x%x\n",
1383                                     ret, pfault->token, pfault->type);
1384                 return;
1385         }
1386
1387         mlx5_ib_page_fault_resume(dev, pfault, 0);
1388         mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x, type: 0x%x, prefetch_activated: %d\n",
1389                     pfault->token, pfault->type,
1390                     prefetch_activated);
1391
1392         /* At this point, there might be a new pagefault already arriving in
1393          * the eq, switch to the dummy pagefault for the rest of the
1394          * processing. We're still OK with the objects being alive as the
1395          * work-queue is being fenced. */
1396
1397         if (prefetch_activated) {
1398                 u32 bytes_committed = 0;
1399
1400                 ret = pagefault_single_data_segment(dev, NULL, rkey, address,
1401                                                     prefetch_len,
1402                                                     &bytes_committed, NULL);
1403                 if (ret < 0 && ret != -EAGAIN) {
1404                         mlx5_ib_dbg(dev, "Prefetch failed. ret: %d, QP 0x%x, address: 0x%.16llx, length = 0x%.16x\n",
1405                                     ret, pfault->token, address, prefetch_len);
1406                 }
1407         }
1408 }
1409
1410 static void mlx5_ib_pfault(struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault)
1411 {
1412         u8 event_subtype = pfault->event_subtype;
1413
1414         switch (event_subtype) {
1415         case MLX5_PFAULT_SUBTYPE_WQE:
1416                 mlx5_ib_mr_wqe_pfault_handler(dev, pfault);
1417                 break;
1418         case MLX5_PFAULT_SUBTYPE_RDMA:
1419                 mlx5_ib_mr_rdma_pfault_handler(dev, pfault);
1420                 break;
1421         default:
1422                 mlx5_ib_err(dev, "Invalid page fault event subtype: 0x%x\n",
1423                             event_subtype);
1424                 mlx5_ib_page_fault_resume(dev, pfault, 1);
1425         }
1426 }
1427
1428 static void mlx5_ib_eqe_pf_action(struct work_struct *work)
1429 {
1430         struct mlx5_pagefault *pfault = container_of(work,
1431                                                      struct mlx5_pagefault,
1432                                                      work);
1433         struct mlx5_ib_pf_eq *eq = pfault->eq;
1434
1435         mlx5_ib_pfault(eq->dev, pfault);
1436         mempool_free(pfault, eq->pool);
1437 }
1438
1439 static void mlx5_ib_eq_pf_process(struct mlx5_ib_pf_eq *eq)
1440 {
1441         struct mlx5_eqe_page_fault *pf_eqe;
1442         struct mlx5_pagefault *pfault;
1443         struct mlx5_eqe *eqe;
1444         int cc = 0;
1445
1446         while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) {
1447                 pfault = mempool_alloc(eq->pool, GFP_ATOMIC);
1448                 if (!pfault) {
1449                         schedule_work(&eq->work);
1450                         break;
1451                 }
1452
1453                 pf_eqe = &eqe->data.page_fault;
1454                 pfault->event_subtype = eqe->sub_type;
1455                 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed);
1456
1457                 mlx5_ib_dbg(eq->dev,
1458                             "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n",
1459                             eqe->sub_type, pfault->bytes_committed);
1460
1461                 switch (eqe->sub_type) {
1462                 case MLX5_PFAULT_SUBTYPE_RDMA:
1463                         /* RDMA based event */
1464                         pfault->type =
1465                                 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24;
1466                         pfault->token =
1467                                 be32_to_cpu(pf_eqe->rdma.pftype_token) &
1468                                 MLX5_24BIT_MASK;
1469                         pfault->rdma.r_key =
1470                                 be32_to_cpu(pf_eqe->rdma.r_key);
1471                         pfault->rdma.packet_size =
1472                                 be16_to_cpu(pf_eqe->rdma.packet_length);
1473                         pfault->rdma.rdma_op_len =
1474                                 be32_to_cpu(pf_eqe->rdma.rdma_op_len);
1475                         pfault->rdma.rdma_va =
1476                                 be64_to_cpu(pf_eqe->rdma.rdma_va);
1477                         mlx5_ib_dbg(eq->dev,
1478                                     "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n",
1479                                     pfault->type, pfault->token,
1480                                     pfault->rdma.r_key);
1481                         mlx5_ib_dbg(eq->dev,
1482                                     "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n",
1483                                     pfault->rdma.rdma_op_len,
1484                                     pfault->rdma.rdma_va);
1485                         break;
1486
1487                 case MLX5_PFAULT_SUBTYPE_WQE:
1488                         /* WQE based event */
1489                         pfault->type =
1490                                 (be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24) & 0x7;
1491                         pfault->token =
1492                                 be32_to_cpu(pf_eqe->wqe.token);
1493                         pfault->wqe.wq_num =
1494                                 be32_to_cpu(pf_eqe->wqe.pftype_wq) &
1495                                 MLX5_24BIT_MASK;
1496                         pfault->wqe.wqe_index =
1497                                 be16_to_cpu(pf_eqe->wqe.wqe_index);
1498                         pfault->wqe.packet_size =
1499                                 be16_to_cpu(pf_eqe->wqe.packet_length);
1500                         mlx5_ib_dbg(eq->dev,
1501                                     "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n",
1502                                     pfault->type, pfault->token,
1503                                     pfault->wqe.wq_num,
1504                                     pfault->wqe.wqe_index);
1505                         break;
1506
1507                 default:
1508                         mlx5_ib_warn(eq->dev,
1509                                      "Unsupported page fault event sub-type: 0x%02hhx\n",
1510                                      eqe->sub_type);
1511                         /* Unsupported page faults should still be
1512                          * resolved by the page fault handler
1513                          */
1514                 }
1515
1516                 pfault->eq = eq;
1517                 INIT_WORK(&pfault->work, mlx5_ib_eqe_pf_action);
1518                 queue_work(eq->wq, &pfault->work);
1519
1520                 cc = mlx5_eq_update_cc(eq->core, ++cc);
1521         }
1522
1523         mlx5_eq_update_ci(eq->core, cc, 1);
1524 }
1525
1526 static int mlx5_ib_eq_pf_int(struct notifier_block *nb, unsigned long type,
1527                              void *data)
1528 {
1529         struct mlx5_ib_pf_eq *eq =
1530                 container_of(nb, struct mlx5_ib_pf_eq, irq_nb);
1531         unsigned long flags;
1532
1533         if (spin_trylock_irqsave(&eq->lock, flags)) {
1534                 mlx5_ib_eq_pf_process(eq);
1535                 spin_unlock_irqrestore(&eq->lock, flags);
1536         } else {
1537                 schedule_work(&eq->work);
1538         }
1539
1540         return IRQ_HANDLED;
1541 }
1542
1543 /* mempool_refill() was proposed but unfortunately wasn't accepted
1544  * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html
1545  * Cheap workaround.
1546  */
1547 static void mempool_refill(mempool_t *pool)
1548 {
1549         while (pool->curr_nr < pool->min_nr)
1550                 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool);
1551 }
1552
1553 static void mlx5_ib_eq_pf_action(struct work_struct *work)
1554 {
1555         struct mlx5_ib_pf_eq *eq =
1556                 container_of(work, struct mlx5_ib_pf_eq, work);
1557
1558         mempool_refill(eq->pool);
1559
1560         spin_lock_irq(&eq->lock);
1561         mlx5_ib_eq_pf_process(eq);
1562         spin_unlock_irq(&eq->lock);
1563 }
1564
1565 enum {
1566         MLX5_IB_NUM_PF_EQE      = 0x1000,
1567         MLX5_IB_NUM_PF_DRAIN    = 64,
1568 };
1569
1570 static int
1571 mlx5_ib_create_pf_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq)
1572 {
1573         struct mlx5_eq_param param = {};
1574         int err;
1575
1576         INIT_WORK(&eq->work, mlx5_ib_eq_pf_action);
1577         spin_lock_init(&eq->lock);
1578         eq->dev = dev;
1579
1580         eq->pool = mempool_create_kmalloc_pool(MLX5_IB_NUM_PF_DRAIN,
1581                                                sizeof(struct mlx5_pagefault));
1582         if (!eq->pool)
1583                 return -ENOMEM;
1584
1585         eq->wq = alloc_workqueue("mlx5_ib_page_fault",
1586                                  WQ_HIGHPRI | WQ_UNBOUND | WQ_MEM_RECLAIM,
1587                                  MLX5_NUM_CMD_EQE);
1588         if (!eq->wq) {
1589                 err = -ENOMEM;
1590                 goto err_mempool;
1591         }
1592
1593         eq->irq_nb.notifier_call = mlx5_ib_eq_pf_int;
1594         param = (struct mlx5_eq_param) {
1595                 .irq_index = 0,
1596                 .nent = MLX5_IB_NUM_PF_EQE,
1597         };
1598         param.mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_FAULT;
1599         eq->core = mlx5_eq_create_generic(dev->mdev, &param);
1600         if (IS_ERR(eq->core)) {
1601                 err = PTR_ERR(eq->core);
1602                 goto err_wq;
1603         }
1604         err = mlx5_eq_enable(dev->mdev, eq->core, &eq->irq_nb);
1605         if (err) {
1606                 mlx5_ib_err(dev, "failed to enable odp EQ %d\n", err);
1607                 goto err_eq;
1608         }
1609
1610         return 0;
1611 err_eq:
1612         mlx5_eq_destroy_generic(dev->mdev, eq->core);
1613 err_wq:
1614         destroy_workqueue(eq->wq);
1615 err_mempool:
1616         mempool_destroy(eq->pool);
1617         return err;
1618 }
1619
1620 static int
1621 mlx5_ib_destroy_pf_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq)
1622 {
1623         int err;
1624
1625         mlx5_eq_disable(dev->mdev, eq->core, &eq->irq_nb);
1626         err = mlx5_eq_destroy_generic(dev->mdev, eq->core);
1627         cancel_work_sync(&eq->work);
1628         destroy_workqueue(eq->wq);
1629         mempool_destroy(eq->pool);
1630
1631         return err;
1632 }
1633
1634 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent)
1635 {
1636         if (!(ent->dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1637                 return;
1638
1639         switch (ent->order - 2) {
1640         case MLX5_IMR_MTT_CACHE_ENTRY:
1641                 ent->page = PAGE_SHIFT;
1642                 ent->xlt = MLX5_IMR_MTT_ENTRIES *
1643                            sizeof(struct mlx5_mtt) /
1644                            MLX5_IB_UMR_OCTOWORD;
1645                 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
1646                 ent->limit = 0;
1647                 break;
1648
1649         case MLX5_IMR_KSM_CACHE_ENTRY:
1650                 ent->page = MLX5_KSM_PAGE_SHIFT;
1651                 ent->xlt = mlx5_imr_ksm_entries *
1652                            sizeof(struct mlx5_klm) /
1653                            MLX5_IB_UMR_OCTOWORD;
1654                 ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM;
1655                 ent->limit = 0;
1656                 break;
1657         }
1658 }
1659
1660 static const struct ib_device_ops mlx5_ib_dev_odp_ops = {
1661         .advise_mr = mlx5_ib_advise_mr,
1662 };
1663
1664 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *dev)
1665 {
1666         int ret = 0;
1667
1668         if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT))
1669                 return ret;
1670
1671         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_odp_ops);
1672
1673         if (dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT) {
1674                 ret = mlx5_cmd_null_mkey(dev->mdev, &dev->null_mkey);
1675                 if (ret) {
1676                         mlx5_ib_err(dev, "Error getting null_mkey %d\n", ret);
1677                         return ret;
1678                 }
1679         }
1680
1681         ret = mlx5_ib_create_pf_eq(dev, &dev->odp_pf_eq);
1682
1683         return ret;
1684 }
1685
1686 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *dev)
1687 {
1688         if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT))
1689                 return;
1690
1691         mlx5_ib_destroy_pf_eq(dev, &dev->odp_pf_eq);
1692 }
1693
1694 int mlx5_ib_odp_init(void)
1695 {
1696         mlx5_imr_ksm_entries = BIT_ULL(get_order(TASK_SIZE) -
1697                                        MLX5_IMR_MTT_BITS);
1698
1699         return 0;
1700 }
1701
1702 struct prefetch_mr_work {
1703         struct work_struct work;
1704         u32 pf_flags;
1705         u32 num_sge;
1706         struct {
1707                 u64 io_virt;
1708                 struct mlx5_ib_mr *mr;
1709                 size_t length;
1710         } frags[];
1711 };
1712
1713 static void destroy_prefetch_work(struct prefetch_mr_work *work)
1714 {
1715         u32 i;
1716
1717         for (i = 0; i < work->num_sge; ++i)
1718                 if (atomic_dec_and_test(&work->frags[i].mr->num_deferred_work))
1719                         wake_up(&work->frags[i].mr->q_deferred_work);
1720         kvfree(work);
1721 }
1722
1723 static struct mlx5_ib_mr *
1724 get_prefetchable_mr(struct ib_pd *pd, enum ib_uverbs_advise_mr_advice advice,
1725                     u32 lkey)
1726 {
1727         struct mlx5_ib_dev *dev = to_mdev(pd->device);
1728         struct mlx5_core_mkey *mmkey;
1729         struct ib_umem_odp *odp;
1730         struct mlx5_ib_mr *mr;
1731
1732         lockdep_assert_held(&dev->odp_srcu);
1733
1734         mmkey = xa_load(&dev->odp_mkeys, mlx5_base_mkey(lkey));
1735         if (!mmkey || mmkey->key != lkey || mmkey->type != MLX5_MKEY_MR)
1736                 return NULL;
1737
1738         mr = container_of(mmkey, struct mlx5_ib_mr, mmkey);
1739
1740         if (mr->ibmr.pd != pd)
1741                 return NULL;
1742
1743         odp = to_ib_umem_odp(mr->umem);
1744
1745         /* prefetch with write-access must be supported by the MR */
1746         if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE &&
1747             !odp->umem.writable)
1748                 return NULL;
1749
1750         return mr;
1751 }
1752
1753 static void mlx5_ib_prefetch_mr_work(struct work_struct *w)
1754 {
1755         struct prefetch_mr_work *work =
1756                 container_of(w, struct prefetch_mr_work, work);
1757         u32 bytes_mapped = 0;
1758         u32 i;
1759
1760         for (i = 0; i < work->num_sge; ++i)
1761                 pagefault_mr(work->frags[i].mr, work->frags[i].io_virt,
1762                              work->frags[i].length, &bytes_mapped,
1763                              work->pf_flags);
1764
1765         destroy_prefetch_work(work);
1766 }
1767
1768 static bool init_prefetch_work(struct ib_pd *pd,
1769                                enum ib_uverbs_advise_mr_advice advice,
1770                                u32 pf_flags, struct prefetch_mr_work *work,
1771                                struct ib_sge *sg_list, u32 num_sge)
1772 {
1773         u32 i;
1774
1775         INIT_WORK(&work->work, mlx5_ib_prefetch_mr_work);
1776         work->pf_flags = pf_flags;
1777
1778         for (i = 0; i < num_sge; ++i) {
1779                 work->frags[i].io_virt = sg_list[i].addr;
1780                 work->frags[i].length = sg_list[i].length;
1781                 work->frags[i].mr =
1782                         get_prefetchable_mr(pd, advice, sg_list[i].lkey);
1783                 if (!work->frags[i].mr) {
1784                         work->num_sge = i - 1;
1785                         if (i)
1786                                 destroy_prefetch_work(work);
1787                         return false;
1788                 }
1789
1790                 /* Keep the MR pointer will valid outside the SRCU */
1791                 atomic_inc(&work->frags[i].mr->num_deferred_work);
1792         }
1793         work->num_sge = num_sge;
1794         return true;
1795 }
1796
1797 static int mlx5_ib_prefetch_sg_list(struct ib_pd *pd,
1798                                     enum ib_uverbs_advise_mr_advice advice,
1799                                     u32 pf_flags, struct ib_sge *sg_list,
1800                                     u32 num_sge)
1801 {
1802         struct mlx5_ib_dev *dev = to_mdev(pd->device);
1803         u32 bytes_mapped = 0;
1804         int srcu_key;
1805         int ret = 0;
1806         u32 i;
1807
1808         srcu_key = srcu_read_lock(&dev->odp_srcu);
1809         for (i = 0; i < num_sge; ++i) {
1810                 struct mlx5_ib_mr *mr;
1811
1812                 mr = get_prefetchable_mr(pd, advice, sg_list[i].lkey);
1813                 if (!mr) {
1814                         ret = -ENOENT;
1815                         goto out;
1816                 }
1817                 ret = pagefault_mr(mr, sg_list[i].addr, sg_list[i].length,
1818                                    &bytes_mapped, pf_flags);
1819                 if (ret < 0)
1820                         goto out;
1821         }
1822         ret = 0;
1823
1824 out:
1825         srcu_read_unlock(&dev->odp_srcu, srcu_key);
1826         return ret;
1827 }
1828
1829 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1830                                enum ib_uverbs_advise_mr_advice advice,
1831                                u32 flags, struct ib_sge *sg_list, u32 num_sge)
1832 {
1833         struct mlx5_ib_dev *dev = to_mdev(pd->device);
1834         u32 pf_flags = 0;
1835         struct prefetch_mr_work *work;
1836         int srcu_key;
1837
1838         if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH)
1839                 pf_flags |= MLX5_PF_FLAGS_DOWNGRADE;
1840
1841         if (flags & IB_UVERBS_ADVISE_MR_FLAG_FLUSH)
1842                 return mlx5_ib_prefetch_sg_list(pd, advice, pf_flags, sg_list,
1843                                                 num_sge);
1844
1845         work = kvzalloc(struct_size(work, frags, num_sge), GFP_KERNEL);
1846         if (!work)
1847                 return -ENOMEM;
1848
1849         srcu_key = srcu_read_lock(&dev->odp_srcu);
1850         if (!init_prefetch_work(pd, advice, pf_flags, work, sg_list, num_sge)) {
1851                 srcu_read_unlock(&dev->odp_srcu, srcu_key);
1852                 return -EINVAL;
1853         }
1854         queue_work(system_unbound_wq, &work->work);
1855         srcu_read_unlock(&dev->odp_srcu, srcu_key);
1856         return 0;
1857 }