drivers/infiniband/hw/mlx5/odp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <rdma/ib_umem.h>
  34 #include <rdma/ib_umem_odp.h>
  35 #include <linux/kernel.h>
  36
  37 #include "mlx5_ib.h"
  38 #include "cmd.h"
  39
  40 #include <linux/mlx5/eq.h>
  41
  42 /* Contains the details of a pagefault. */
  43 struct mlx5_pagefault {
  44         u32                     bytes_committed;
  45         u32                     token;
  46         u8                      event_subtype;
  47         u8                      type;
  48         union {
  49                 /* Initiator or send message responder pagefault details. */
  50                 struct {
  51                         /* Received packet size, only valid for responders. */
  52                         u32     packet_size;
  53                         /*
  54                          * Number of resource holding WQE, depends on type.
  55                          */
  56                         u32     wq_num;
  57                         /*
  58                          * WQE index. Refers to either the send queue or
  59                          * receive queue, according to event_subtype.
  60                          */
  61                         u16     wqe_index;
  62                 } wqe;
  63                 /* RDMA responder pagefault details */
  64                 struct {
  65                         u32     r_key;
  66                         /*
  67                          * Received packet size, minimal size page fault
  68                          * resolution required for forward progress.
  69                          */
  70                         u32     packet_size;
  71                         u32     rdma_op_len;
  72                         u64     rdma_va;
  73                 } rdma;
  74         };
  75
  76         struct mlx5_ib_pf_eq    *eq;
  77         struct work_struct      work;
  78 };
  79
  80 #define MAX_PREFETCH_LEN (4*1024*1024U)
  81
  82 /* Timeout in ms to wait for an active mmu notifier to complete when handling
  83  * a pagefault. */
  84 #define MMU_NOTIFIER_TIMEOUT 1000
  85
  86 #define MLX5_IMR_MTT_BITS (30 - PAGE_SHIFT)
  87 #define MLX5_IMR_MTT_SHIFT (MLX5_IMR_MTT_BITS + PAGE_SHIFT)
  88 #define MLX5_IMR_MTT_ENTRIES BIT_ULL(MLX5_IMR_MTT_BITS)
  89 #define MLX5_IMR_MTT_SIZE BIT_ULL(MLX5_IMR_MTT_SHIFT)
  90 #define MLX5_IMR_MTT_MASK (~(MLX5_IMR_MTT_SIZE - 1))
  91
  92 #define MLX5_KSM_PAGE_SHIFT MLX5_IMR_MTT_SHIFT
  93
  94 static u64 mlx5_imr_ksm_entries;
  95
  96 static int check_parent(struct ib_umem_odp *odp,
  97                                struct mlx5_ib_mr *parent)
  98 {
  99         struct mlx5_ib_mr *mr = odp->private;
 100
 101         return mr && mr->parent == parent && !odp->dying;
 102 }
 103
 104 struct ib_ucontext_per_mm *mr_to_per_mm(struct mlx5_ib_mr *mr)
 105 {
 106         if (WARN_ON(!mr || !mr->umem || !mr->umem->is_odp))
 107                 return NULL;
 108
 109         return to_ib_umem_odp(mr->umem)->per_mm;
 110 }
 111
 112 static struct ib_umem_odp *odp_next(struct ib_umem_odp *odp)
 113 {
 114         struct mlx5_ib_mr *mr = odp->private, *parent = mr->parent;
 115         struct ib_ucontext_per_mm *per_mm = odp->per_mm;
 116         struct rb_node *rb;
 117
 118         down_read(&per_mm->umem_rwsem);
 119         while (1) {
 120                 rb = rb_next(&odp->interval_tree.rb);
 121                 if (!rb)
 122                         goto not_found;
 123                 odp = rb_entry(rb, struct ib_umem_odp, interval_tree.rb);
 124                 if (check_parent(odp, parent))
 125                         goto end;
 126         }
 127 not_found:
 128         odp = NULL;
 129 end:
 130         up_read(&per_mm->umem_rwsem);
 131         return odp;
 132 }
 133
 134 static struct ib_umem_odp *odp_lookup(u64 start, u64 length,
 135                                       struct mlx5_ib_mr *parent)
 136 {
 137         struct ib_ucontext_per_mm *per_mm = mr_to_per_mm(parent);
 138         struct ib_umem_odp *odp;
 139         struct rb_node *rb;
 140
 141         down_read(&per_mm->umem_rwsem);
 142         odp = rbt_ib_umem_lookup(&per_mm->umem_tree, start, length);
 143         if (!odp)
 144                 goto end;
 145
 146         while (1) {
 147                 if (check_parent(odp, parent))
 148                         goto end;
 149                 rb = rb_next(&odp->interval_tree.rb);
 150                 if (!rb)
 151                         goto not_found;
 152                 odp = rb_entry(rb, struct ib_umem_odp, interval_tree.rb);
 153                 if (ib_umem_start(&odp->umem) > start + length)
 154                         goto not_found;
 155         }
 156 not_found:
 157         odp = NULL;
 158 end:
 159         up_read(&per_mm->umem_rwsem);
 160         return odp;
 161 }
 162
 163 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
 164                            size_t nentries, struct mlx5_ib_mr *mr, int flags)
 165 {
 166         struct ib_pd *pd = mr->ibmr.pd;
 167         struct mlx5_ib_dev *dev = to_mdev(pd->device);
 168         struct ib_umem_odp *odp;
 169         unsigned long va;
 170         int i;
 171
 172         if (flags & MLX5_IB_UPD_XLT_ZAP) {
 173                 for (i = 0; i < nentries; i++, pklm++) {
 174                         pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE);
 175                         pklm->key = cpu_to_be32(dev->null_mkey);
 176                         pklm->va = 0;
 177                 }
 178                 return;
 179         }
 180
 181         odp = odp_lookup(offset * MLX5_IMR_MTT_SIZE,
 182                          nentries * MLX5_IMR_MTT_SIZE, mr);
 183
 184         for (i = 0; i < nentries; i++, pklm++) {
 185                 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE);
 186                 va = (offset + i) * MLX5_IMR_MTT_SIZE;
 187                 if (odp && odp->umem.address == va) {
 188                         struct mlx5_ib_mr *mtt = odp->private;
 189
 190                         pklm->key = cpu_to_be32(mtt->ibmr.lkey);
 191                         odp = odp_next(odp);
 192                 } else {
 193                         pklm->key = cpu_to_be32(dev->null_mkey);
 194                 }
 195                 mlx5_ib_dbg(dev, "[%d] va %lx key %x\n",
 196                             i, va, be32_to_cpu(pklm->key));
 197         }
 198 }
 199
 200 static void mr_leaf_free_action(struct work_struct *work)
 201 {
 202         struct ib_umem_odp *odp = container_of(work, struct ib_umem_odp, work);
 203         int idx = ib_umem_start(&odp->umem) >> MLX5_IMR_MTT_SHIFT;
 204         struct mlx5_ib_mr *mr = odp->private, *imr = mr->parent;
 205
 206         mr->parent = NULL;
 207         synchronize_srcu(&mr->dev->mr_srcu);
 208
 209         ib_umem_release(&odp->umem);
 210         if (imr->live)
 211                 mlx5_ib_update_xlt(imr, idx, 1, 0,
 212                                    MLX5_IB_UPD_XLT_INDIRECT |
 213                                    MLX5_IB_UPD_XLT_ATOMIC);
 214         mlx5_mr_cache_free(mr->dev, mr);
 215
 216         if (atomic_dec_and_test(&imr->num_leaf_free))
 217                 wake_up(&imr->q_leaf_free);
 218 }
 219
 220 void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, unsigned long start,
 221                               unsigned long end)
 222 {
 223         struct mlx5_ib_mr *mr;
 224         const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT /
 225                                     sizeof(struct mlx5_mtt)) - 1;
 226         u64 idx = 0, blk_start_idx = 0;
 227         struct ib_umem *umem;
 228         int in_block = 0;
 229         u64 addr;
 230
 231         if (!umem_odp) {
 232                 pr_err("invalidation called on NULL umem or non-ODP umem\n");
 233                 return;
 234         }
 235         umem = &umem_odp->umem;
 236
 237         mr = umem_odp->private;
 238
 239         if (!mr || !mr->ibmr.pd)
 240                 return;
 241
 242         start = max_t(u64, ib_umem_start(umem), start);
 243         end = min_t(u64, ib_umem_end(umem), end);
 244
 245         /*
 246          * Iteration one - zap the HW's MTTs. The notifiers_count ensures that
 247          * while we are doing the invalidation, no page fault will attempt to
 248          * overwrite the same MTTs.  Concurent invalidations might race us,
 249          * but they will write 0s as well, so no difference in the end result.
 250          */
 251
 252         for (addr = start; addr < end; addr += BIT(umem->page_shift)) {
 253                 idx = (addr - ib_umem_start(umem)) >> umem->page_shift;
 254                 /*
 255                  * Strive to write the MTTs in chunks, but avoid overwriting
 256                  * non-existing MTTs. The huristic here can be improved to
 257                  * estimate the cost of another UMR vs. the cost of bigger
 258                  * UMR.
 259                  */
 260                 if (umem_odp->dma_list[idx] &
 261                     (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) {
 262                         if (!in_block) {
 263                                 blk_start_idx = idx;
 264                                 in_block = 1;
 265                         }
 266                 } else {
 267                         u64 umr_offset = idx & umr_block_mask;
 268
 269                         if (in_block && umr_offset == 0) {
 270                                 mlx5_ib_update_xlt(mr, blk_start_idx,
 271                                                    idx - blk_start_idx, 0,
 272                                                    MLX5_IB_UPD_XLT_ZAP |
 273                                                    MLX5_IB_UPD_XLT_ATOMIC);
 274                                 in_block = 0;
 275                         }
 276                 }
 277         }
 278         if (in_block)
 279                 mlx5_ib_update_xlt(mr, blk_start_idx,
 280                                    idx - blk_start_idx + 1, 0,
 281                                    MLX5_IB_UPD_XLT_ZAP |
 282                                    MLX5_IB_UPD_XLT_ATOMIC);
 283         /*
 284          * We are now sure that the device will not access the
 285          * memory. We can safely unmap it, and mark it as dirty if
 286          * needed.
 287          */
 288
 289         ib_umem_odp_unmap_dma_pages(umem_odp, start, end);
 290
 291         if (unlikely(!umem->npages && mr->parent &&
 292                      !umem_odp->dying)) {
 293                 WRITE_ONCE(umem_odp->dying, 1);
 294                 atomic_inc(&mr->parent->num_leaf_free);
 295                 schedule_work(&umem_odp->work);
 296         }
 297 }
 298
 299 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
 300 {
 301         struct ib_odp_caps *caps = &dev->odp_caps;
 302
 303         memset(caps, 0, sizeof(*caps));
 304
 305         if (!MLX5_CAP_GEN(dev->mdev, pg))
 306                 return;
 307
 308         caps->general_caps = IB_ODP_SUPPORT;
 309
 310         if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
 311                 dev->odp_max_size = U64_MAX;
 312         else
 313                 dev->odp_max_size = BIT_ULL(MLX5_MAX_UMR_SHIFT + PAGE_SHIFT);
 314
 315         if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.send))
 316                 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SEND;
 317
 318         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.send))
 319                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SEND;
 320
 321         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.receive))
 322                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_RECV;
 323
 324         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.write))
 325                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_WRITE;
 326
 327         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.read))
 328                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_READ;
 329
 330         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.atomic))
 331                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_ATOMIC;
 332
 333         if (MLX5_CAP_GEN(dev->mdev, fixed_buffer_size) &&
 334             MLX5_CAP_GEN(dev->mdev, null_mkey) &&
 335             MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
 336                 caps->general_caps |= IB_ODP_SUPPORT_IMPLICIT;
 337
 338         return;
 339 }
 340
 341 static void mlx5_ib_page_fault_resume(struct mlx5_ib_dev *dev,
 342                                       struct mlx5_pagefault *pfault,
 343                                       int error)
 344 {
 345         int wq_num = pfault->event_subtype == MLX5_PFAULT_SUBTYPE_WQE ?
 346                      pfault->wqe.wq_num : pfault->token;
 347         u32 out[MLX5_ST_SZ_DW(page_fault_resume_out)] = { };
 348         u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)]   = { };
 349         int err;
 350
 351         MLX5_SET(page_fault_resume_in, in, opcode, MLX5_CMD_OP_PAGE_FAULT_RESUME);
 352         MLX5_SET(page_fault_resume_in, in, page_fault_type, pfault->type);
 353         MLX5_SET(page_fault_resume_in, in, token, pfault->token);
 354         MLX5_SET(page_fault_resume_in, in, wq_number, wq_num);
 355         MLX5_SET(page_fault_resume_in, in, error, !!error);
 356
 357         err = mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 358         if (err)
 359                 mlx5_ib_err(dev, "Failed to resolve the page fault on WQ 0x%x err %d\n",
 360                             wq_num, err);
 361 }
 362
 363 static struct mlx5_ib_mr *implicit_mr_alloc(struct ib_pd *pd,
 364                                             struct ib_umem *umem,
 365                                             bool ksm, int access_flags)
 366 {
 367         struct mlx5_ib_dev *dev = to_mdev(pd->device);
 368         struct mlx5_ib_mr *mr;
 369         int err;
 370
 371         mr = mlx5_mr_cache_alloc(dev, ksm ? MLX5_IMR_KSM_CACHE_ENTRY :
 372                                             MLX5_IMR_MTT_CACHE_ENTRY);
 373
 374         if (IS_ERR(mr))
 375                 return mr;
 376
 377         mr->ibmr.pd = pd;
 378
 379         mr->dev = dev;
 380         mr->access_flags = access_flags;
 381         mr->mmkey.iova = 0;
 382         mr->umem = umem;
 383
 384         if (ksm) {
 385                 err = mlx5_ib_update_xlt(mr, 0,
 386                                          mlx5_imr_ksm_entries,
 387                                          MLX5_KSM_PAGE_SHIFT,
 388                                          MLX5_IB_UPD_XLT_INDIRECT |
 389                                          MLX5_IB_UPD_XLT_ZAP |
 390                                          MLX5_IB_UPD_XLT_ENABLE);
 391
 392         } else {
 393                 err = mlx5_ib_update_xlt(mr, 0,
 394                                          MLX5_IMR_MTT_ENTRIES,
 395                                          PAGE_SHIFT,
 396                                          MLX5_IB_UPD_XLT_ZAP |
 397                                          MLX5_IB_UPD_XLT_ENABLE |
 398                                          MLX5_IB_UPD_XLT_ATOMIC);
 399         }
 400
 401         if (err)
 402                 goto fail;
 403
 404         mr->ibmr.lkey = mr->mmkey.key;
 405         mr->ibmr.rkey = mr->mmkey.key;
 406
 407         mr->live = 1;
 408
 409         mlx5_ib_dbg(dev, "key %x dev %p mr %p\n",
 410                     mr->mmkey.key, dev->mdev, mr);
 411
 412         return mr;
 413
 414 fail:
 415         mlx5_ib_err(dev, "Failed to register MKEY %d\n", err);
 416         mlx5_mr_cache_free(dev, mr);
 417
 418         return ERR_PTR(err);
 419 }
 420
 421 static struct ib_umem_odp *implicit_mr_get_data(struct mlx5_ib_mr *mr,
 422                                                 u64 io_virt, size_t bcnt)
 423 {
 424         struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.pd->device);
 425         struct ib_umem_odp *odp, *result = NULL;
 426         struct ib_umem_odp *odp_mr = to_ib_umem_odp(mr->umem);
 427         u64 addr = io_virt & MLX5_IMR_MTT_MASK;
 428         int nentries = 0, start_idx = 0, ret;
 429         struct mlx5_ib_mr *mtt;
 430
 431         mutex_lock(&odp_mr->umem_mutex);
 432         odp = odp_lookup(addr, 1, mr);
 433
 434         mlx5_ib_dbg(dev, "io_virt:%llx bcnt:%zx addr:%llx odp:%p\n",
 435                     io_virt, bcnt, addr, odp);
 436
 437 next_mr:
 438         if (likely(odp)) {
 439                 if (nentries)
 440                         nentries++;
 441         } else {
 442                 odp = ib_alloc_odp_umem(odp_mr->per_mm, addr,
 443                                         MLX5_IMR_MTT_SIZE);
 444                 if (IS_ERR(odp)) {
 445                         mutex_unlock(&odp_mr->umem_mutex);
 446                         return ERR_CAST(odp);
 447                 }
 448
 449                 mtt = implicit_mr_alloc(mr->ibmr.pd, &odp->umem, 0,
 450                                         mr->access_flags);
 451                 if (IS_ERR(mtt)) {
 452                         mutex_unlock(&odp_mr->umem_mutex);
 453                         ib_umem_release(&odp->umem);
 454                         return ERR_CAST(mtt);
 455                 }
 456
 457                 odp->private = mtt;
 458                 mtt->umem = &odp->umem;
 459                 mtt->mmkey.iova = addr;
 460                 mtt->parent = mr;
 461                 INIT_WORK(&odp->work, mr_leaf_free_action);
 462
 463                 if (!nentries)
 464                         start_idx = addr >> MLX5_IMR_MTT_SHIFT;
 465                 nentries++;
 466         }
 467
 468         /* Return first odp if region not covered by single one */
 469         if (likely(!result))
 470                 result = odp;
 471
 472         addr += MLX5_IMR_MTT_SIZE;
 473         if (unlikely(addr < io_virt + bcnt)) {
 474                 odp = odp_next(odp);
 475                 if (odp && odp->umem.address != addr)
 476                         odp = NULL;
 477                 goto next_mr;
 478         }
 479
 480         if (unlikely(nentries)) {
 481                 ret = mlx5_ib_update_xlt(mr, start_idx, nentries, 0,
 482                                          MLX5_IB_UPD_XLT_INDIRECT |
 483                                          MLX5_IB_UPD_XLT_ATOMIC);
 484                 if (ret) {
 485                         mlx5_ib_err(dev, "Failed to update PAS\n");
 486                         result = ERR_PTR(ret);
 487                 }
 488         }
 489
 490         mutex_unlock(&odp_mr->umem_mutex);
 491         return result;
 492 }
 493
 494 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
 495                                              int access_flags)
 496 {
 497         struct ib_ucontext *ctx = pd->ibpd.uobject->context;
 498         struct mlx5_ib_mr *imr;
 499         struct ib_umem *umem;
 500
 501         umem = ib_umem_get(ctx, 0, 0, IB_ACCESS_ON_DEMAND, 0);
 502         if (IS_ERR(umem))
 503                 return ERR_CAST(umem);
 504
 505         imr = implicit_mr_alloc(&pd->ibpd, umem, 1, access_flags);
 506         if (IS_ERR(imr)) {
 507                 ib_umem_release(umem);
 508                 return ERR_CAST(imr);
 509         }
 510
 511         imr->umem = umem;
 512         init_waitqueue_head(&imr->q_leaf_free);
 513         atomic_set(&imr->num_leaf_free, 0);
 514
 515         return imr;
 516 }
 517
 518 static int mr_leaf_free(struct ib_umem_odp *umem_odp, u64 start, u64 end,
 519                         void *cookie)
 520 {
 521         struct mlx5_ib_mr *mr = umem_odp->private, *imr = cookie;
 522         struct ib_umem *umem = &umem_odp->umem;
 523
 524         if (mr->parent != imr)
 525                 return 0;
 526
 527         ib_umem_odp_unmap_dma_pages(umem_odp, ib_umem_start(umem),
 528                                     ib_umem_end(umem));
 529
 530         if (umem_odp->dying)
 531                 return 0;
 532
 533         WRITE_ONCE(umem_odp->dying, 1);
 534         atomic_inc(&imr->num_leaf_free);
 535         schedule_work(&umem_odp->work);
 536
 537         return 0;
 538 }
 539
 540 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *imr)
 541 {
 542         struct ib_ucontext_per_mm *per_mm = mr_to_per_mm(imr);
 543
 544         down_read(&per_mm->umem_rwsem);
 545         rbt_ib_umem_for_each_in_range(&per_mm->umem_tree, 0, ULLONG_MAX,
 546                                       mr_leaf_free, true, imr);
 547         up_read(&per_mm->umem_rwsem);
 548
 549         wait_event(imr->q_leaf_free, !atomic_read(&imr->num_leaf_free));
 550 }
 551
 552 static int pagefault_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
 553                         u64 io_virt, size_t bcnt, u32 *bytes_mapped)
 554 {
 555         int npages = 0, current_seq, page_shift, ret, np;
 556         bool implicit = false;
 557         struct ib_umem_odp *odp_mr = to_ib_umem_odp(mr->umem);
 558         u64 access_mask = ODP_READ_ALLOWED_BIT;
 559         u64 start_idx, page_mask;
 560         struct ib_umem_odp *odp;
 561         size_t size;
 562
 563         if (!odp_mr->page_list) {
 564                 odp = implicit_mr_get_data(mr, io_virt, bcnt);
 565
 566                 if (IS_ERR(odp))
 567                         return PTR_ERR(odp);
 568                 mr = odp->private;
 569                 implicit = true;
 570         } else {
 571                 odp = odp_mr;
 572         }
 573
 574 next_mr:
 575         size = min_t(size_t, bcnt, ib_umem_end(&odp->umem) - io_virt);
 576
 577         page_shift = mr->umem->page_shift;
 578         page_mask = ~(BIT(page_shift) - 1);
 579         start_idx = (io_virt - (mr->mmkey.iova & page_mask)) >> page_shift;
 580
 581         if (mr->umem->writable)
 582                 access_mask |= ODP_WRITE_ALLOWED_BIT;
 583
 584         current_seq = READ_ONCE(odp->notifiers_seq);
 585         /*
 586          * Ensure the sequence number is valid for some time before we call
 587          * gup.
 588          */
 589         smp_rmb();
 590
 591         ret = ib_umem_odp_map_dma_pages(to_ib_umem_odp(mr->umem), io_virt, size,
 592                                         access_mask, current_seq);
 593
 594         if (ret < 0)
 595                 goto out;
 596
 597         np = ret;
 598
 599         mutex_lock(&odp->umem_mutex);
 600         if (!ib_umem_mmu_notifier_retry(to_ib_umem_odp(mr->umem),
 601                                         current_seq)) {
 602                 /*
 603                  * No need to check whether the MTTs really belong to
 604                  * this MR, since ib_umem_odp_map_dma_pages already
 605                  * checks this.
 606                  */
 607                 ret = mlx5_ib_update_xlt(mr, start_idx, np,
 608                                          page_shift, MLX5_IB_UPD_XLT_ATOMIC);
 609         } else {
 610                 ret = -EAGAIN;
 611         }
 612         mutex_unlock(&odp->umem_mutex);
 613
 614         if (ret < 0) {
 615                 if (ret != -EAGAIN)
 616                         mlx5_ib_err(dev, "Failed to update mkey page tables\n");
 617                 goto out;
 618         }
 619
 620         if (bytes_mapped) {
 621                 u32 new_mappings = (np << page_shift) -
 622                         (io_virt - round_down(io_virt, 1 << page_shift));
 623                 *bytes_mapped += min_t(u32, new_mappings, size);
 624         }
 625
 626         npages += np << (page_shift - PAGE_SHIFT);
 627         bcnt -= size;
 628
 629         if (unlikely(bcnt)) {
 630                 struct ib_umem_odp *next;
 631
 632                 io_virt += size;
 633                 next = odp_next(odp);
 634                 if (unlikely(!next || next->umem.address != io_virt)) {
 635                         mlx5_ib_dbg(dev, "next implicit leaf removed at 0x%llx. got %p\n",
 636                                     io_virt, next);
 637                         return -EAGAIN;
 638                 }
 639                 odp = next;
 640                 mr = odp->private;
 641                 goto next_mr;
 642         }
 643
 644         return npages;
 645
 646 out:
 647         if (ret == -EAGAIN) {
 648                 if (implicit || !odp->dying) {
 649                         unsigned long timeout =
 650                                 msecs_to_jiffies(MMU_NOTIFIER_TIMEOUT);
 651
 652                         if (!wait_for_completion_timeout(
 653                                         &odp->notifier_completion,
 654                                         timeout)) {
 655                                 mlx5_ib_warn(dev, "timeout waiting for mmu notifier. seq %d against %d. notifiers_count=%d\n",
 656                                              current_seq, odp->notifiers_seq, odp->notifiers_count);
 657                         }
 658                 } else {
 659                         /* The MR is being killed, kill the QP as well. */
 660                         ret = -EFAULT;
 661                 }
 662         }
 663
 664         return ret;
 665 }
 666
 667 struct pf_frame {
 668         struct pf_frame *next;
 669         u32 key;
 670         u64 io_virt;
 671         size_t bcnt;
 672         int depth;
 673 };
 674
 675 /*
 676  * Handle a single data segment in a page-fault WQE or RDMA region.
 677  *
 678  * Returns number of OS pages retrieved on success. The caller may continue to
 679  * the next data segment.
 680  * Can return the following error codes:
 681  * -EAGAIN to designate a temporary error. The caller will abort handling the
 682  *  page fault and resolve it.
 683  * -EFAULT when there's an error mapping the requested pages. The caller will
 684  *  abort the page fault handling.
 685  */
 686 static int pagefault_single_data_segment(struct mlx5_ib_dev *dev,
 687                                          u32 key, u64 io_virt, size_t bcnt,
 688                                          u32 *bytes_committed,
 689                                          u32 *bytes_mapped)
 690 {
 691         int npages = 0, srcu_key, ret, i, outlen, cur_outlen = 0, depth = 0;
 692         struct pf_frame *head = NULL, *frame;
 693         struct mlx5_core_mkey *mmkey;
 694         struct mlx5_ib_mw *mw;
 695         struct mlx5_ib_mr *mr;
 696         struct mlx5_klm *pklm;
 697         u32 *out = NULL;
 698         size_t offset;
 699
 700         srcu_key = srcu_read_lock(&dev->mr_srcu);
 701
 702         io_virt += *bytes_committed;
 703         bcnt -= *bytes_committed;
 704
 705 next_mr:
 706         mmkey = __mlx5_mr_lookup(dev->mdev, mlx5_base_mkey(key));
 707         if (!mmkey || mmkey->key != key) {
 708                 mlx5_ib_dbg(dev, "failed to find mkey %x\n", key);
 709                 ret = -EFAULT;
 710                 goto srcu_unlock;
 711         }
 712
 713         switch (mmkey->type) {
 714         case MLX5_MKEY_MR:
 715                 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey);
 716                 if (!mr->live || !mr->ibmr.pd) {
 717                         mlx5_ib_dbg(dev, "got dead MR\n");
 718                         ret = -EFAULT;
 719                         goto srcu_unlock;
 720                 }
 721
 722                 if (!mr->umem->is_odp) {
 723                         mlx5_ib_dbg(dev, "skipping non ODP MR (lkey=0x%06x) in page fault handler.\n",
 724                                     key);
 725                         if (bytes_mapped)
 726                                 *bytes_mapped += bcnt;
 727                         ret = 0;
 728                         goto srcu_unlock;
 729                 }
 730
 731                 ret = pagefault_mr(dev, mr, io_virt, bcnt, bytes_mapped);
 732                 if (ret < 0)
 733                         goto srcu_unlock;
 734
 735                 npages += ret;
 736                 ret = 0;
 737                 break;
 738
 739         case MLX5_MKEY_MW:
 740                 mw = container_of(mmkey, struct mlx5_ib_mw, mmkey);
 741
 742                 if (depth >= MLX5_CAP_GEN(dev->mdev, max_indirection)) {
 743                         mlx5_ib_dbg(dev, "indirection level exceeded\n");
 744                         ret = -EFAULT;
 745                         goto srcu_unlock;
 746                 }
 747
 748                 outlen = MLX5_ST_SZ_BYTES(query_mkey_out) +
 749                         sizeof(*pklm) * (mw->ndescs - 2);
 750
 751                 if (outlen > cur_outlen) {
 752                         kfree(out);
 753                         out = kzalloc(outlen, GFP_KERNEL);
 754                         if (!out) {
 755                                 ret = -ENOMEM;
 756                                 goto srcu_unlock;
 757                         }
 758                         cur_outlen = outlen;
 759                 }
 760
 761                 pklm = (struct mlx5_klm *)MLX5_ADDR_OF(query_mkey_out, out,
 762                                                        bsf0_klm0_pas_mtt0_1);
 763
 764                 ret = mlx5_core_query_mkey(dev->mdev, &mw->mmkey, out, outlen);
 765                 if (ret)
 766                         goto srcu_unlock;
 767
 768                 offset = io_virt - MLX5_GET64(query_mkey_out, out,
 769                                               memory_key_mkey_entry.start_addr);
 770
 771                 for (i = 0; bcnt && i < mw->ndescs; i++, pklm++) {
 772                         if (offset >= be32_to_cpu(pklm->bcount)) {
 773                                 offset -= be32_to_cpu(pklm->bcount);
 774                                 continue;
 775                         }
 776
 777                         frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 778                         if (!frame) {
 779                                 ret = -ENOMEM;
 780                                 goto srcu_unlock;
 781                         }
 782
 783                         frame->key = be32_to_cpu(pklm->key);
 784                         frame->io_virt = be64_to_cpu(pklm->va) + offset;
 785                         frame->bcnt = min_t(size_t, bcnt,
 786                                             be32_to_cpu(pklm->bcount) - offset);
 787                         frame->depth = depth + 1;
 788                         frame->next = head;
 789                         head = frame;
 790
 791                         bcnt -= frame->bcnt;
 792                         offset = 0;
 793                 }
 794                 break;
 795
 796         default:
 797                 mlx5_ib_dbg(dev, "wrong mkey type %d\n", mmkey->type);
 798                 ret = -EFAULT;
 799                 goto srcu_unlock;
 800         }
 801
 802         if (head) {
 803                 frame = head;
 804                 head = frame->next;
 805
 806                 key = frame->key;
 807                 io_virt = frame->io_virt;
 808                 bcnt = frame->bcnt;
 809                 depth = frame->depth;
 810                 kfree(frame);
 811
 812                 goto next_mr;
 813         }
 814
 815 srcu_unlock:
 816         while (head) {
 817                 frame = head;
 818                 head = frame->next;
 819                 kfree(frame);
 820         }
 821         kfree(out);
 822
 823         srcu_read_unlock(&dev->mr_srcu, srcu_key);
 824         *bytes_committed = 0;
 825         return ret ? ret : npages;
 826 }
 827
 828 /**
 829  * Parse a series of data segments for page fault handling.
 830  *
 831  * @qp the QP on which the fault occurred.
 832  * @pfault contains page fault information.
 833  * @wqe points at the first data segment in the WQE.
 834  * @wqe_end points after the end of the WQE.
 835  * @bytes_mapped receives the number of bytes that the function was able to
 836  *               map. This allows the caller to decide intelligently whether
 837  *               enough memory was mapped to resolve the page fault
 838  *               successfully (e.g. enough for the next MTU, or the entire
 839  *               WQE).
 840  * @total_wqe_bytes receives the total data size of this WQE in bytes (minus
 841  *                  the committed bytes).
 842  *
 843  * Returns the number of pages loaded if positive, zero for an empty WQE, or a
 844  * negative error code.
 845  */
 846 static int pagefault_data_segments(struct mlx5_ib_dev *dev,
 847                                    struct mlx5_pagefault *pfault,
 848                                    struct mlx5_ib_qp *qp, void *wqe,
 849                                    void *wqe_end, u32 *bytes_mapped,
 850                                    u32 *total_wqe_bytes, int receive_queue)
 851 {
 852         int ret = 0, npages = 0;
 853         u64 io_virt;
 854         u32 key;
 855         u32 byte_count;
 856         size_t bcnt;
 857         int inline_segment;
 858
 859         /* Skip SRQ next-WQE segment. */
 860         if (receive_queue && qp->ibqp.srq)
 861                 wqe += sizeof(struct mlx5_wqe_srq_next_seg);
 862
 863         if (bytes_mapped)
 864                 *bytes_mapped = 0;
 865         if (total_wqe_bytes)
 866                 *total_wqe_bytes = 0;
 867
 868         while (wqe < wqe_end) {
 869                 struct mlx5_wqe_data_seg *dseg = wqe;
 870
 871                 io_virt = be64_to_cpu(dseg->addr);
 872                 key = be32_to_cpu(dseg->lkey);
 873                 byte_count = be32_to_cpu(dseg->byte_count);
 874                 inline_segment = !!(byte_count &  MLX5_INLINE_SEG);
 875                 bcnt           = byte_count & ~MLX5_INLINE_SEG;
 876
 877                 if (inline_segment) {
 878                         bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK;
 879                         wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt,
 880                                      16);
 881                 } else {
 882                         wqe += sizeof(*dseg);
 883                 }
 884
 885                 /* receive WQE end of sg list. */
 886                 if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY &&
 887                     io_virt == 0)
 888                         break;
 889
 890                 if (!inline_segment && total_wqe_bytes) {
 891                         *total_wqe_bytes += bcnt - min_t(size_t, bcnt,
 892                                         pfault->bytes_committed);
 893                 }
 894
 895                 /* A zero length data segment designates a length of 2GB. */
 896                 if (bcnt == 0)
 897                         bcnt = 1U << 31;
 898
 899                 if (inline_segment || bcnt <= pfault->bytes_committed) {
 900                         pfault->bytes_committed -=
 901                                 min_t(size_t, bcnt,
 902                                       pfault->bytes_committed);
 903                         continue;
 904                 }
 905
 906                 ret = pagefault_single_data_segment(dev, key, io_virt, bcnt,
 907                                                     &pfault->bytes_committed,
 908                                                     bytes_mapped);
 909                 if (ret < 0)
 910                         break;
 911                 npages += ret;
 912         }
 913
 914         return ret < 0 ? ret : npages;
 915 }
 916
 917 static const u32 mlx5_ib_odp_opcode_cap[] = {
 918         [MLX5_OPCODE_SEND]             = IB_ODP_SUPPORT_SEND,
 919         [MLX5_OPCODE_SEND_IMM]         = IB_ODP_SUPPORT_SEND,
 920         [MLX5_OPCODE_SEND_INVAL]       = IB_ODP_SUPPORT_SEND,
 921         [MLX5_OPCODE_RDMA_WRITE]       = IB_ODP_SUPPORT_WRITE,
 922         [MLX5_OPCODE_RDMA_WRITE_IMM]   = IB_ODP_SUPPORT_WRITE,
 923         [MLX5_OPCODE_RDMA_READ]        = IB_ODP_SUPPORT_READ,
 924         [MLX5_OPCODE_ATOMIC_CS]        = IB_ODP_SUPPORT_ATOMIC,
 925         [MLX5_OPCODE_ATOMIC_FA]        = IB_ODP_SUPPORT_ATOMIC,
 926 };
 927
 928 /*
 929  * Parse initiator WQE. Advances the wqe pointer to point at the
 930  * scatter-gather list, and set wqe_end to the end of the WQE.
 931  */
 932 static int mlx5_ib_mr_initiator_pfault_handler(
 933         struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault,
 934         struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length)
 935 {
 936         struct mlx5_wqe_ctrl_seg *ctrl = *wqe;
 937         u16 wqe_index = pfault->wqe.wqe_index;
 938         u32 transport_caps;
 939         struct mlx5_base_av *av;
 940         unsigned ds, opcode;
 941 #if defined(DEBUG)
 942         u32 ctrl_wqe_index, ctrl_qpn;
 943 #endif
 944         u32 qpn = qp->trans_qp.base.mqp.qpn;
 945
 946         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 947         if (ds * MLX5_WQE_DS_UNITS > wqe_length) {
 948                 mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n",
 949                             ds, wqe_length);
 950                 return -EFAULT;
 951         }
 952
 953         if (ds == 0) {
 954                 mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n",
 955                             wqe_index, qpn);
 956                 return -EFAULT;
 957         }
 958
 959 #if defined(DEBUG)
 960         ctrl_wqe_index = (be32_to_cpu(ctrl->opmod_idx_opcode) &
 961                         MLX5_WQE_CTRL_WQE_INDEX_MASK) >>
 962                         MLX5_WQE_CTRL_WQE_INDEX_SHIFT;
 963         if (wqe_index != ctrl_wqe_index) {
 964                 mlx5_ib_err(dev, "Got WQE with invalid wqe_index. wqe_index=0x%x, qpn=0x%x ctrl->wqe_index=0x%x\n",
 965                             wqe_index, qpn,
 966                             ctrl_wqe_index);
 967                 return -EFAULT;
 968         }
 969
 970         ctrl_qpn = (be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_QPN_MASK) >>
 971                 MLX5_WQE_CTRL_QPN_SHIFT;
 972         if (qpn != ctrl_qpn) {
 973                 mlx5_ib_err(dev, "Got WQE with incorrect QP number. wqe_index=0x%x, qpn=0x%x ctrl->qpn=0x%x\n",
 974                             wqe_index, qpn,
 975                             ctrl_qpn);
 976                 return -EFAULT;
 977         }
 978 #endif /* DEBUG */
 979
 980         *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS;
 981         *wqe += sizeof(*ctrl);
 982
 983         opcode = be32_to_cpu(ctrl->opmod_idx_opcode) &
 984                  MLX5_WQE_CTRL_OPCODE_MASK;
 985
 986         switch (qp->ibqp.qp_type) {
 987         case IB_QPT_RC:
 988                 transport_caps = dev->odp_caps.per_transport_caps.rc_odp_caps;
 989                 break;
 990         case IB_QPT_UD:
 991                 transport_caps = dev->odp_caps.per_transport_caps.ud_odp_caps;
 992                 break;
 993         default:
 994                 mlx5_ib_err(dev, "ODP fault on QP of an unsupported transport 0x%x\n",
 995                             qp->ibqp.qp_type);
 996                 return -EFAULT;
 997         }
 998
 999         if (unlikely(opcode >= ARRAY_SIZE(mlx5_ib_odp_opcode_cap) ||
1000                      !(transport_caps & mlx5_ib_odp_opcode_cap[opcode]))) {
1001                 mlx5_ib_err(dev, "ODP fault on QP of an unsupported opcode 0x%x\n",
1002                             opcode);
1003                 return -EFAULT;
1004         }
1005
1006         if (qp->ibqp.qp_type != IB_QPT_RC) {
1007                 av = *wqe;
1008                 if (av->dqp_dct & cpu_to_be32(MLX5_EXTENDED_UD_AV))
1009                         *wqe += sizeof(struct mlx5_av);
1010                 else
1011                         *wqe += sizeof(struct mlx5_base_av);
1012         }
1013
1014         switch (opcode) {
1015         case MLX5_OPCODE_RDMA_WRITE:
1016         case MLX5_OPCODE_RDMA_WRITE_IMM:
1017         case MLX5_OPCODE_RDMA_READ:
1018                 *wqe += sizeof(struct mlx5_wqe_raddr_seg);
1019                 break;
1020         case MLX5_OPCODE_ATOMIC_CS:
1021         case MLX5_OPCODE_ATOMIC_FA:
1022                 *wqe += sizeof(struct mlx5_wqe_raddr_seg);
1023                 *wqe += sizeof(struct mlx5_wqe_atomic_seg);
1024                 break;
1025         }
1026
1027         return 0;
1028 }
1029
1030 /*
1031  * Parse responder WQE. Advances the wqe pointer to point at the
1032  * scatter-gather list, and set wqe_end to the end of the WQE.
1033  */
1034 static int mlx5_ib_mr_responder_pfault_handler(
1035         struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault,
1036         struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length)
1037 {
1038         struct mlx5_ib_wq *wq = &qp->rq;
1039         int wqe_size = 1 << wq->wqe_shift;
1040
1041         if (qp->ibqp.srq) {
1042                 mlx5_ib_err(dev, "ODP fault on SRQ is not supported\n");
1043                 return -EFAULT;
1044         }
1045
1046         if (qp->wq_sig) {
1047                 mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n");
1048                 return -EFAULT;
1049         }
1050
1051         if (wqe_size > wqe_length) {
1052                 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n");
1053                 return -EFAULT;
1054         }
1055
1056         switch (qp->ibqp.qp_type) {
1057         case IB_QPT_RC:
1058                 if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
1059                       IB_ODP_SUPPORT_RECV))
1060                         goto invalid_transport_or_opcode;
1061                 break;
1062         default:
1063 invalid_transport_or_opcode:
1064                 mlx5_ib_err(dev, "ODP fault on QP of an unsupported transport. transport: 0x%x\n",
1065                             qp->ibqp.qp_type);
1066                 return -EFAULT;
1067         }
1068
1069         *wqe_end = *wqe + wqe_size;
1070
1071         return 0;
1072 }
1073
1074 static inline struct mlx5_core_rsc_common *odp_get_rsc(struct mlx5_ib_dev *dev,
1075                                                        u32 wq_num, int pf_type)
1076 {
1077         enum mlx5_res_type res_type;
1078
1079         switch (pf_type) {
1080         case MLX5_WQE_PF_TYPE_RMP:
1081                 res_type = MLX5_RES_SRQ;
1082                 break;
1083         case MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE:
1084         case MLX5_WQE_PF_TYPE_RESP:
1085         case MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC:
1086                 res_type = MLX5_RES_QP;
1087                 break;
1088         default:
1089                 return NULL;
1090         }
1091
1092         return mlx5_core_res_hold(dev->mdev, wq_num, res_type);
1093 }
1094
1095 static inline struct mlx5_ib_qp *res_to_qp(struct mlx5_core_rsc_common *res)
1096 {
1097         struct mlx5_core_qp *mqp = (struct mlx5_core_qp *)res;
1098
1099         return to_mibqp(mqp);
1100 }
1101
1102 static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_dev *dev,
1103                                           struct mlx5_pagefault *pfault)
1104 {
1105         int ret;
1106         void *wqe, *wqe_end;
1107         u32 bytes_mapped, total_wqe_bytes;
1108         char *buffer = NULL;
1109         int resume_with_error = 1;
1110         u16 wqe_index = pfault->wqe.wqe_index;
1111         int requestor = pfault->type & MLX5_PFAULT_REQUESTOR;
1112         struct mlx5_core_rsc_common *res;
1113         struct mlx5_ib_qp *qp;
1114
1115         res = odp_get_rsc(dev, pfault->wqe.wq_num, pfault->type);
1116         if (!res) {
1117                 mlx5_ib_dbg(dev, "wqe page fault for missing resource %d\n", pfault->wqe.wq_num);
1118                 return;
1119         }
1120
1121         switch (res->res) {
1122         case MLX5_RES_QP:
1123                 qp = res_to_qp(res);
1124                 break;
1125         default:
1126                 mlx5_ib_err(dev, "wqe page fault for unsupported type %d\n", pfault->type);
1127                 goto resolve_page_fault;
1128         }
1129
1130         buffer = (char *)__get_free_page(GFP_KERNEL);
1131         if (!buffer) {
1132                 mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n");
1133                 goto resolve_page_fault;
1134         }
1135
1136         ret = mlx5_ib_read_user_wqe(qp, requestor, wqe_index, buffer,
1137                                     PAGE_SIZE, &qp->trans_qp.base);
1138         if (ret < 0) {
1139                 mlx5_ib_err(dev, "Failed reading a WQE following page fault, error=%d, wqe_index=%x, qpn=%x\n",
1140                             ret, wqe_index, pfault->token);
1141                 goto resolve_page_fault;
1142         }
1143
1144         wqe = buffer;
1145         if (requestor)
1146                 ret = mlx5_ib_mr_initiator_pfault_handler(dev, pfault, qp, &wqe,
1147                                                           &wqe_end, ret);
1148         else
1149                 ret = mlx5_ib_mr_responder_pfault_handler(dev, pfault, qp, &wqe,
1150                                                           &wqe_end, ret);
1151         if (ret < 0)
1152                 goto resolve_page_fault;
1153
1154         if (wqe >= wqe_end) {
1155                 mlx5_ib_err(dev, "ODP fault on invalid WQE.\n");
1156                 goto resolve_page_fault;
1157         }
1158
1159         ret = pagefault_data_segments(dev, pfault, qp, wqe, wqe_end,
1160                                       &bytes_mapped, &total_wqe_bytes,
1161                                       !requestor);
1162         if (ret == -EAGAIN) {
1163                 resume_with_error = 0;
1164                 goto resolve_page_fault;
1165         } else if (ret < 0 || total_wqe_bytes > bytes_mapped) {
1166                 goto resolve_page_fault;
1167         }
1168
1169         resume_with_error = 0;
1170 resolve_page_fault:
1171         mlx5_ib_page_fault_resume(dev, pfault, resume_with_error);
1172         mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, type: 0x%x\n",
1173                     pfault->wqe.wq_num, resume_with_error,
1174                     pfault->type);
1175         mlx5_core_res_put(res);
1176         free_page((unsigned long)buffer);
1177 }
1178
1179 static int pages_in_range(u64 address, u32 length)
1180 {
1181         return (ALIGN(address + length, PAGE_SIZE) -
1182                 (address & PAGE_MASK)) >> PAGE_SHIFT;
1183 }
1184
1185 static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev,
1186                                            struct mlx5_pagefault *pfault)
1187 {
1188         u64 address;
1189         u32 length;
1190         u32 prefetch_len = pfault->bytes_committed;
1191         int prefetch_activated = 0;
1192         u32 rkey = pfault->rdma.r_key;
1193         int ret;
1194
1195         /* The RDMA responder handler handles the page fault in two parts.
1196          * First it brings the necessary pages for the current packet
1197          * (and uses the pfault context), and then (after resuming the QP)
1198          * prefetches more pages. The second operation cannot use the pfault
1199          * context and therefore uses the dummy_pfault context allocated on
1200          * the stack */
1201         pfault->rdma.rdma_va += pfault->bytes_committed;
1202         pfault->rdma.rdma_op_len -= min(pfault->bytes_committed,
1203                                          pfault->rdma.rdma_op_len);
1204         pfault->bytes_committed = 0;
1205
1206         address = pfault->rdma.rdma_va;
1207         length  = pfault->rdma.rdma_op_len;
1208
1209         /* For some operations, the hardware cannot tell the exact message
1210          * length, and in those cases it reports zero. Use prefetch
1211          * logic. */
1212         if (length == 0) {
1213                 prefetch_activated = 1;
1214                 length = pfault->rdma.packet_size;
1215                 prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len);
1216         }
1217
1218         ret = pagefault_single_data_segment(dev, rkey, address, length,
1219                                             &pfault->bytes_committed, NULL);
1220         if (ret == -EAGAIN) {
1221                 /* We're racing with an invalidation, don't prefetch */
1222                 prefetch_activated = 0;
1223         } else if (ret < 0 || pages_in_range(address, length) > ret) {
1224                 mlx5_ib_page_fault_resume(dev, pfault, 1);
1225                 if (ret != -ENOENT)
1226                         mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%x, type: 0x%x\n",
1227                                     ret, pfault->token, pfault->type);
1228                 return;
1229         }
1230
1231         mlx5_ib_page_fault_resume(dev, pfault, 0);
1232         mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x, type: 0x%x, prefetch_activated: %d\n",
1233                     pfault->token, pfault->type,
1234                     prefetch_activated);
1235
1236         /* At this point, there might be a new pagefault already arriving in
1237          * the eq, switch to the dummy pagefault for the rest of the
1238          * processing. We're still OK with the objects being alive as the
1239          * work-queue is being fenced. */
1240
1241         if (prefetch_activated) {
1242                 u32 bytes_committed = 0;
1243
1244                 ret = pagefault_single_data_segment(dev, rkey, address,
1245                                                     prefetch_len,
1246                                                     &bytes_committed, NULL);
1247                 if (ret < 0 && ret != -EAGAIN) {
1248                         mlx5_ib_dbg(dev, "Prefetch failed. ret: %d, QP 0x%x, address: 0x%.16llx, length = 0x%.16x\n",
1249                                     ret, pfault->token, address, prefetch_len);
1250                 }
1251         }
1252 }
1253
1254 static void mlx5_ib_pfault(struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault)
1255 {
1256         u8 event_subtype = pfault->event_subtype;
1257
1258         switch (event_subtype) {
1259         case MLX5_PFAULT_SUBTYPE_WQE:
1260                 mlx5_ib_mr_wqe_pfault_handler(dev, pfault);
1261                 break;
1262         case MLX5_PFAULT_SUBTYPE_RDMA:
1263                 mlx5_ib_mr_rdma_pfault_handler(dev, pfault);
1264                 break;
1265         default:
1266                 mlx5_ib_err(dev, "Invalid page fault event subtype: 0x%x\n",
1267                             event_subtype);
1268                 mlx5_ib_page_fault_resume(dev, pfault, 1);
1269         }
1270 }
1271
1272 static void mlx5_ib_eqe_pf_action(struct work_struct *work)
1273 {
1274         struct mlx5_pagefault *pfault = container_of(work,
1275                                                      struct mlx5_pagefault,
1276                                                      work);
1277         struct mlx5_ib_pf_eq *eq = pfault->eq;
1278
1279         mlx5_ib_pfault(eq->dev, pfault);
1280         mempool_free(pfault, eq->pool);
1281 }
1282
1283 static void mlx5_ib_eq_pf_process(struct mlx5_ib_pf_eq *eq)
1284 {
1285         struct mlx5_eqe_page_fault *pf_eqe;
1286         struct mlx5_pagefault *pfault;
1287         struct mlx5_eqe *eqe;
1288         int cc = 0;
1289
1290         while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) {
1291                 pfault = mempool_alloc(eq->pool, GFP_ATOMIC);
1292                 if (!pfault) {
1293                         schedule_work(&eq->work);
1294                         break;
1295                 }
1296
1297                 pf_eqe = &eqe->data.page_fault;
1298                 pfault->event_subtype = eqe->sub_type;
1299                 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed);
1300
1301                 mlx5_ib_dbg(eq->dev,
1302                             "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n",
1303                             eqe->sub_type, pfault->bytes_committed);
1304
1305                 switch (eqe->sub_type) {
1306                 case MLX5_PFAULT_SUBTYPE_RDMA:
1307                         /* RDMA based event */
1308                         pfault->type =
1309                                 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24;
1310                         pfault->token =
1311                                 be32_to_cpu(pf_eqe->rdma.pftype_token) &
1312                                 MLX5_24BIT_MASK;
1313                         pfault->rdma.r_key =
1314                                 be32_to_cpu(pf_eqe->rdma.r_key);
1315                         pfault->rdma.packet_size =
1316                                 be16_to_cpu(pf_eqe->rdma.packet_length);
1317                         pfault->rdma.rdma_op_len =
1318                                 be32_to_cpu(pf_eqe->rdma.rdma_op_len);
1319                         pfault->rdma.rdma_va =
1320                                 be64_to_cpu(pf_eqe->rdma.rdma_va);
1321                         mlx5_ib_dbg(eq->dev,
1322                                     "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n",
1323                                     pfault->type, pfault->token,
1324                                     pfault->rdma.r_key);
1325                         mlx5_ib_dbg(eq->dev,
1326                                     "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n",
1327                                     pfault->rdma.rdma_op_len,
1328                                     pfault->rdma.rdma_va);
1329                         break;
1330
1331                 case MLX5_PFAULT_SUBTYPE_WQE:
1332                         /* WQE based event */
1333                         pfault->type =
1334                                 (be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24) & 0x7;
1335                         pfault->token =
1336                                 be32_to_cpu(pf_eqe->wqe.token);
1337                         pfault->wqe.wq_num =
1338                                 be32_to_cpu(pf_eqe->wqe.pftype_wq) &
1339                                 MLX5_24BIT_MASK;
1340                         pfault->wqe.wqe_index =
1341                                 be16_to_cpu(pf_eqe->wqe.wqe_index);
1342                         pfault->wqe.packet_size =
1343                                 be16_to_cpu(pf_eqe->wqe.packet_length);
1344                         mlx5_ib_dbg(eq->dev,
1345                                     "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n",
1346                                     pfault->type, pfault->token,
1347                                     pfault->wqe.wq_num,
1348                                     pfault->wqe.wqe_index);
1349                         break;
1350
1351                 default:
1352                         mlx5_ib_warn(eq->dev,
1353                                      "Unsupported page fault event sub-type: 0x%02hhx\n",
1354                                      eqe->sub_type);
1355                         /* Unsupported page faults should still be
1356                          * resolved by the page fault handler
1357                          */
1358                 }
1359
1360                 pfault->eq = eq;
1361                 INIT_WORK(&pfault->work, mlx5_ib_eqe_pf_action);
1362                 queue_work(eq->wq, &pfault->work);
1363
1364                 cc = mlx5_eq_update_cc(eq->core, ++cc);
1365         }
1366
1367         mlx5_eq_update_ci(eq->core, cc, 1);
1368 }
1369
1370 static irqreturn_t mlx5_ib_eq_pf_int(int irq, void *eq_ptr)
1371 {
1372         struct mlx5_ib_pf_eq *eq = eq_ptr;
1373         unsigned long flags;
1374
1375         if (spin_trylock_irqsave(&eq->lock, flags)) {
1376                 mlx5_ib_eq_pf_process(eq);
1377                 spin_unlock_irqrestore(&eq->lock, flags);
1378         } else {
1379                 schedule_work(&eq->work);
1380         }
1381
1382         return IRQ_HANDLED;
1383 }
1384
1385 /* mempool_refill() was proposed but unfortunately wasn't accepted
1386  * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html
1387  * Cheap workaround.
1388  */
1389 static void mempool_refill(mempool_t *pool)
1390 {
1391         while (pool->curr_nr < pool->min_nr)
1392                 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool);
1393 }
1394
1395 static void mlx5_ib_eq_pf_action(struct work_struct *work)
1396 {
1397         struct mlx5_ib_pf_eq *eq =
1398                 container_of(work, struct mlx5_ib_pf_eq, work);
1399
1400         mempool_refill(eq->pool);
1401
1402         spin_lock_irq(&eq->lock);
1403         mlx5_ib_eq_pf_process(eq);
1404         spin_unlock_irq(&eq->lock);
1405 }
1406
1407 enum {
1408         MLX5_IB_NUM_PF_EQE      = 0x1000,
1409         MLX5_IB_NUM_PF_DRAIN    = 64,
1410 };
1411
1412 static int
1413 mlx5_ib_create_pf_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq)
1414 {
1415         struct mlx5_eq_param param = {};
1416         int err;
1417
1418         INIT_WORK(&eq->work, mlx5_ib_eq_pf_action);
1419         spin_lock_init(&eq->lock);
1420         eq->dev = dev;
1421
1422         eq->pool = mempool_create_kmalloc_pool(MLX5_IB_NUM_PF_DRAIN,
1423                                                sizeof(struct mlx5_pagefault));
1424         if (!eq->pool)
1425                 return -ENOMEM;
1426
1427         eq->wq = alloc_workqueue("mlx5_ib_page_fault",
1428                                  WQ_HIGHPRI | WQ_UNBOUND | WQ_MEM_RECLAIM,
1429                                  MLX5_NUM_CMD_EQE);
1430         if (!eq->wq) {
1431                 err = -ENOMEM;
1432                 goto err_mempool;
1433         }
1434
1435         param = (struct mlx5_eq_param) {
1436                 .index = MLX5_EQ_PFAULT_IDX,
1437                 .mask = 1 << MLX5_EVENT_TYPE_PAGE_FAULT,
1438                 .nent = MLX5_IB_NUM_PF_EQE,
1439                 .context = eq,
1440                 .handler = mlx5_ib_eq_pf_int
1441         };
1442         eq->core = mlx5_eq_create_generic(dev->mdev, "mlx5_ib_page_fault_eq", &param);
1443         if (IS_ERR(eq->core)) {
1444                 err = PTR_ERR(eq->core);
1445                 goto err_wq;
1446         }
1447
1448         return 0;
1449 err_wq:
1450         destroy_workqueue(eq->wq);
1451 err_mempool:
1452         mempool_destroy(eq->pool);
1453         return err;
1454 }
1455
1456 static int
1457 mlx5_ib_destroy_pf_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq)
1458 {
1459         int err;
1460
1461         err = mlx5_eq_destroy_generic(dev->mdev, eq->core);
1462         cancel_work_sync(&eq->work);
1463         destroy_workqueue(eq->wq);
1464         mempool_destroy(eq->pool);
1465
1466         return err;
1467 }
1468
1469 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent)
1470 {
1471         if (!(ent->dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1472                 return;
1473
1474         switch (ent->order - 2) {
1475         case MLX5_IMR_MTT_CACHE_ENTRY:
1476                 ent->page = PAGE_SHIFT;
1477                 ent->xlt = MLX5_IMR_MTT_ENTRIES *
1478                            sizeof(struct mlx5_mtt) /
1479                            MLX5_IB_UMR_OCTOWORD;
1480                 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
1481                 ent->limit = 0;
1482                 break;
1483
1484         case MLX5_IMR_KSM_CACHE_ENTRY:
1485                 ent->page = MLX5_KSM_PAGE_SHIFT;
1486                 ent->xlt = mlx5_imr_ksm_entries *
1487                            sizeof(struct mlx5_klm) /
1488                            MLX5_IB_UMR_OCTOWORD;
1489                 ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM;
1490                 ent->limit = 0;
1491                 break;
1492         }
1493 }
1494
1495 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *dev)
1496 {
1497         int ret = 0;
1498
1499         if (dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT) {
1500                 ret = mlx5_cmd_null_mkey(dev->mdev, &dev->null_mkey);
1501                 if (ret) {
1502                         mlx5_ib_err(dev, "Error getting null_mkey %d\n", ret);
1503                         return ret;
1504                 }
1505         }
1506
1507         if (!MLX5_CAP_GEN(dev->mdev, pg))
1508                 return ret;
1509
1510         ret = mlx5_ib_create_pf_eq(dev, &dev->odp_pf_eq);
1511
1512         return ret;
1513 }
1514
1515 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *dev)
1516 {
1517         if (!MLX5_CAP_GEN(dev->mdev, pg))
1518                 return;
1519
1520         mlx5_ib_destroy_pf_eq(dev, &dev->odp_pf_eq);
1521 }
1522
1523 int mlx5_ib_odp_init(void)
1524 {
1525         mlx5_imr_ksm_entries = BIT_ULL(get_order(TASK_SIZE) -
1526                                        MLX5_IMR_MTT_BITS);
1527
1528         return 0;
1529 }