2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_smi.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/fs.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/types.h>
46 #include <linux/mlx5/transobj.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/mlx5-abi.h>
49 #include <rdma/uverbs_ioctl.h>
50 #include <rdma/mlx5_user_ioctl_cmds.h>
51 #include <rdma/mlx5_user_ioctl_verbs.h>
55 #define mlx5_ib_dbg(_dev, format, arg...) \
56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
57 __LINE__, current->pid, ##arg)
59 #define mlx5_ib_err(_dev, format, arg...) \
60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
61 __LINE__, current->pid, ##arg)
63 #define mlx5_ib_warn(_dev, format, arg...) \
64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
65 __LINE__, current->pid, ##arg)
67 #define MLX5_IB_DEFAULT_UIDX 0xffffff
68 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
70 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
73 MLX5_IB_MMAP_OFFSET_START = 9,
74 MLX5_IB_MMAP_OFFSET_END = 255,
78 MLX5_IB_MMAP_CMD_SHIFT = 8,
79 MLX5_IB_MMAP_CMD_MASK = 0xff,
83 MLX5_RES_SCAT_DATA32_CQE = 0x1,
84 MLX5_RES_SCAT_DATA64_CQE = 0x2,
85 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
86 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
89 enum mlx5_ib_mad_ifc_flags {
90 MLX5_MAD_IFC_IGNORE_MKEY = 1,
91 MLX5_MAD_IFC_IGNORE_BKEY = 2,
92 MLX5_MAD_IFC_NET_VIEW = 4,
96 MLX5_CROSS_CHANNEL_BFREG = 0,
105 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
110 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
111 MLX5_IB_INVALID_BFREG = BIT(31),
115 MLX5_MAX_MEMIC_PAGES = 0x100,
116 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
120 MLX5_MEMIC_BASE_ALIGN = 6,
121 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
124 enum mlx5_ib_mmap_type {
125 MLX5_IB_MMAP_TYPE_MEMIC = 1,
126 MLX5_IB_MMAP_TYPE_VAR = 2,
127 MLX5_IB_MMAP_TYPE_UAR_WC = 3,
128 MLX5_IB_MMAP_TYPE_UAR_NC = 4,
131 struct mlx5_bfreg_info {
133 int num_low_latency_bfregs;
137 * protect bfreg allocation data structs
144 u32 num_static_sys_pages;
145 u32 total_num_bfregs;
149 struct mlx5_ib_ucontext {
150 struct ib_ucontext ibucontext;
151 struct list_head db_page_list;
153 /* protect doorbell record alloc/free
155 struct mutex db_page_mutex;
156 struct mlx5_bfreg_info bfregi;
158 /* Transport Domain number */
163 /* For RoCE LAG TX affinity */
164 atomic_t tx_port_affinity;
167 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
169 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
179 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
180 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
181 MLX5_IB_FLOW_ACTION_DECAP,
184 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
185 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
186 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
187 #error "Invalid number of bypass priorities"
189 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
191 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
192 #define MLX5_IB_NUM_SNIFFER_FTS 2
193 #define MLX5_IB_NUM_EGRESS_FTS 1
194 struct mlx5_ib_flow_prio {
195 struct mlx5_flow_table *flow_table;
196 unsigned int refcount;
199 struct mlx5_ib_flow_handler {
200 struct list_head list;
201 struct ib_flow ibflow;
202 struct mlx5_ib_flow_prio *prio;
203 struct mlx5_flow_handle *rule;
204 struct ib_counters *ibcounters;
205 struct mlx5_ib_dev *dev;
206 struct mlx5_ib_flow_matcher *flow_matcher;
209 struct mlx5_ib_flow_matcher {
210 struct mlx5_ib_match_params matcher_mask;
212 enum mlx5_ib_flow_type flow_type;
213 enum mlx5_flow_namespace_type ns_type;
215 struct mlx5_core_dev *mdev;
217 u8 match_criteria_enable;
222 struct mlx5_core_dev *mdev;
225 struct mlx5_ib_flow_db {
226 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
227 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
228 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
229 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
230 struct mlx5_ib_flow_prio fdb;
231 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
232 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT];
233 struct mlx5_flow_table *lag_demux_ft;
234 /* Protect flow steering bypass flow tables
235 * when add/del flow rules.
236 * only single add/removal of flow steering rule could be done
242 /* Use macros here so that don't have to duplicate
243 * enum ib_send_flags and enum ib_qp_type for low-level driver
246 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
247 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
248 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
249 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
250 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
251 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
253 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
255 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
256 * creates the actual hardware QP.
258 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
259 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
260 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
261 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
263 #define MLX5_IB_UMR_OCTOWORD 16
264 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
266 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
267 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
268 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
269 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
270 #define MLX5_IB_UPD_XLT_PD BIT(4)
271 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
272 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
274 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
276 * These flags are intended for internal use by the mlx5_ib driver, and they
277 * rely on the range reserved for that use in the ib_qp_create_flags enum.
279 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START
280 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1)
287 enum mlx5_ib_rq_flags {
288 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
289 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
293 struct mlx5_frag_buf_ctrl fbc;
296 struct wr_list *w_list;
300 /* serialize post to the work queue
315 enum mlx5_ib_wq_flags {
316 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
317 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
320 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
321 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
322 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
323 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
324 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3
328 struct mlx5_core_qp core_qp;
335 u32 two_byte_shift_en;
336 u32 single_stride_log_num_of_bytes;
337 struct ib_umem *umem;
339 unsigned int page_shift;
345 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
348 struct mlx5_ib_rwq_ind_table {
349 struct ib_rwq_ind_table ib_rwq_ind_tbl;
354 struct mlx5_ib_ubuffer {
355 struct ib_umem *umem;
360 struct mlx5_ib_qp_base {
361 struct mlx5_ib_qp *container_mibqp;
362 struct mlx5_core_qp mqp;
363 struct mlx5_ib_ubuffer ubuffer;
366 struct mlx5_ib_qp_trans {
367 struct mlx5_ib_qp_base base;
374 struct mlx5_ib_rss_qp {
379 struct mlx5_ib_qp_base base;
380 struct mlx5_ib_wq *rq;
381 struct mlx5_ib_ubuffer ubuffer;
382 struct mlx5_db *doorbell;
389 struct mlx5_ib_qp_base base;
390 struct mlx5_ib_wq *sq;
391 struct mlx5_ib_ubuffer ubuffer;
392 struct mlx5_db *doorbell;
393 struct mlx5_flow_handle *flow_rule;
398 struct mlx5_ib_raw_packet_qp {
399 struct mlx5_ib_sq sq;
400 struct mlx5_ib_rq rq;
405 unsigned long offset;
406 struct mlx5_sq_bfreg *bfreg;
410 struct mlx5_core_dct mdct;
417 struct mlx5_ib_qp_trans trans_qp;
418 struct mlx5_ib_raw_packet_qp raw_packet_qp;
419 struct mlx5_ib_rss_qp rss_qp;
420 struct mlx5_ib_dct dct;
422 struct mlx5_frag_buf buf;
425 struct mlx5_ib_wq rq;
429 struct mlx5_ib_wq sq;
431 /* serialize qp state modifications
434 /* cached variant of create_flags from struct ib_qp_init_attr */
443 /* only for user space QPs. For kernel
444 * we have it from the bf object
448 struct list_head qps_list;
449 struct list_head cq_recv_list;
450 struct list_head cq_send_list;
451 struct mlx5_rate_limit rl;
455 * IB/core doesn't store low-level QP types, so
456 * store both MLX and IBTA types in the field below.
457 * IB_QPT_DRIVER will be break to DCI/DCT subtypes.
459 enum ib_qp_type type;
460 /* A flag to indicate if there's a new counter is configured
461 * but not take effective
466 struct mlx5_ib_cq_buf {
467 struct mlx5_frag_buf_ctrl fbc;
468 struct mlx5_frag_buf frag_buf;
469 struct ib_umem *umem;
475 struct ib_send_wr wr;
479 unsigned int page_shift;
480 unsigned int xlt_size;
484 u8 ignore_free_state:1;
487 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
489 return container_of(wr, struct mlx5_umr_wr, wr);
492 struct mlx5_shared_mr_info {
494 struct ib_umem *umem;
497 enum mlx5_ib_cq_pr_flags {
498 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
503 struct mlx5_core_cq mcq;
504 struct mlx5_ib_cq_buf buf;
507 /* serialize access to the CQ
513 struct mutex resize_mutex;
514 struct mlx5_ib_cq_buf *resize_buf;
515 struct ib_umem *resize_umem;
517 struct list_head list_send_qp;
518 struct list_head list_recv_qp;
520 struct list_head wc_list;
521 enum ib_cq_notify_flags notify_flags;
522 struct work_struct notify_work;
523 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
528 struct list_head list;
533 struct mlx5_core_srq msrq;
534 struct mlx5_frag_buf buf;
536 struct mlx5_frag_buf_ctrl fbc;
538 /* protect SRQ hanlding
544 struct ib_umem *umem;
545 /* serialize arming a SRQ
551 struct mlx5_ib_xrcd {
552 struct ib_xrcd ibxrcd;
556 enum mlx5_ib_mtt_access_flags {
557 MLX5_IB_MTT_READ = (1 << 0),
558 MLX5_IB_MTT_WRITE = (1 << 1),
561 struct mlx5_user_mmap_entry {
562 struct rdma_user_mmap_entry rdma_entry;
570 phys_addr_t dev_addr;
577 /* other dm types specific params should be added here */
579 struct mlx5_user_mmap_entry mentry;
582 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
584 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
585 IB_ACCESS_REMOTE_WRITE |\
586 IB_ACCESS_REMOTE_READ |\
587 IB_ACCESS_REMOTE_ATOMIC |\
590 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
591 IB_ACCESS_REMOTE_WRITE |\
592 IB_ACCESS_REMOTE_READ |\
595 #define mlx5_update_odp_stats(mr, counter_name, value) \
596 atomic64_add(value, &((mr)->odp_stats.counter_name))
609 struct mlx5_core_mkey mmkey;
610 struct ib_umem *umem;
611 struct mlx5_shared_mr_info *smr_info;
612 struct list_head list;
614 struct mlx5_cache_ent *cache_ent;
616 struct mlx5_ib_dev *dev;
617 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
618 struct mlx5_core_sig_ctx *sig;
620 int access_flags; /* Needed for rereg MR */
622 struct mlx5_ib_mr *parent;
623 /* Needed for IB_MR_TYPE_INTEGRITY */
624 struct mlx5_ib_mr *pi_mr;
625 struct mlx5_ib_mr *klm_mr;
626 struct mlx5_ib_mr *mtt_mr;
630 /* For ODP and implicit */
631 atomic_t num_deferred_work;
632 wait_queue_head_t q_deferred_work;
633 struct xarray implicit_children;
636 struct list_head elm;
637 struct work_struct work;
639 struct ib_odp_counters odp_stats;
640 bool is_odp_implicit;
642 struct mlx5_async_work cb_work;
645 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
647 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
653 struct mlx5_core_mkey mmkey;
657 struct mlx5_ib_devx_mr {
658 struct mlx5_core_mkey mmkey;
662 struct mlx5_ib_umr_context {
664 enum ib_wc_status status;
665 struct completion done;
672 /* control access to UMR QP
674 struct semaphore sem;
683 struct mlx5_cache_ent {
684 struct list_head head;
685 /* sync access to the cahce entry
697 u8 fill_to_high_water:1;
700 * - available_mrs is the length of list head, ie the number of MRs
701 * available for immediate allocation.
702 * - total_mrs is available_mrs plus all in use MRs that could be
703 * returned to the cache.
704 * - limit is the low water mark for available_mrs, 2* limit is the
706 * - pending is the number of MRs currently being created
716 struct mlx5_ib_dev *dev;
717 struct work_struct work;
718 struct delayed_work dwork;
721 struct mlx5_mr_cache {
722 struct workqueue_struct *wq;
723 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
725 unsigned long last_add;
728 struct mlx5_ib_gsi_qp;
730 struct mlx5_ib_port_resources {
731 struct mlx5_ib_resources *devr;
732 struct mlx5_ib_gsi_qp *gsi;
733 struct work_struct pkey_change_work;
736 struct mlx5_ib_resources {
743 struct mlx5_ib_port_resources ports[2];
744 /* Protects changes to the port resources */
748 struct mlx5_ib_counters {
752 u32 num_cong_counters;
753 u32 num_ext_ppcnt_counters;
757 struct mlx5_ib_multiport_info;
759 struct mlx5_ib_multiport {
760 struct mlx5_ib_multiport_info *mpi;
761 /* To be held when accessing the multiport info */
766 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
769 rwlock_t netdev_lock;
770 struct net_device *netdev;
771 struct notifier_block nb;
772 atomic_t tx_port_affinity;
773 enum ib_port_state last_port_state;
774 struct mlx5_ib_dev *dev;
778 struct mlx5_ib_port {
779 struct mlx5_ib_counters cnts;
780 struct mlx5_ib_multiport mp;
781 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
782 struct mlx5_roce roce;
783 struct mlx5_eswitch_rep *rep;
786 struct mlx5_ib_dbg_param {
788 struct mlx5_ib_dev *dev;
789 struct dentry *dentry;
793 enum mlx5_ib_dbg_cc_types {
794 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
795 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
796 MLX5_IB_DBG_CC_RP_TIME_RESET,
797 MLX5_IB_DBG_CC_RP_BYTE_RESET,
798 MLX5_IB_DBG_CC_RP_THRESHOLD,
799 MLX5_IB_DBG_CC_RP_AI_RATE,
800 MLX5_IB_DBG_CC_RP_MAX_RATE,
801 MLX5_IB_DBG_CC_RP_HAI_RATE,
802 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
803 MLX5_IB_DBG_CC_RP_MIN_RATE,
804 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
805 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
806 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
807 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
808 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
809 MLX5_IB_DBG_CC_RP_GD,
810 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS,
811 MLX5_IB_DBG_CC_NP_CNP_DSCP,
812 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
813 MLX5_IB_DBG_CC_NP_CNP_PRIO,
817 struct mlx5_ib_dbg_cc_params {
819 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
823 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
826 struct mlx5_ib_delay_drop {
827 struct mlx5_ib_dev *dev;
828 struct work_struct delay_drop_work;
829 /* serialize setting of delay drop */
835 struct dentry *dir_debugfs;
838 enum mlx5_ib_stages {
840 MLX5_IB_STAGE_FLOW_DB,
842 MLX5_IB_STAGE_NON_DEFAULT_CB,
846 MLX5_IB_STAGE_DEVICE_RESOURCES,
847 MLX5_IB_STAGE_DEVICE_NOTIFIER,
849 MLX5_IB_STAGE_COUNTERS,
850 MLX5_IB_STAGE_CONG_DEBUGFS,
853 MLX5_IB_STAGE_PRE_IB_REG_UMR,
854 MLX5_IB_STAGE_WHITELIST_UID,
855 MLX5_IB_STAGE_IB_REG,
856 MLX5_IB_STAGE_POST_IB_REG_UMR,
857 MLX5_IB_STAGE_DELAY_DROP,
858 MLX5_IB_STAGE_CLASS_ATTR,
862 struct mlx5_ib_stage {
863 int (*init)(struct mlx5_ib_dev *dev);
864 void (*cleanup)(struct mlx5_ib_dev *dev);
867 #define STAGE_CREATE(_stage, _init, _cleanup) \
868 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
870 struct mlx5_ib_profile {
871 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
874 struct mlx5_ib_multiport_info {
875 struct list_head list;
876 struct mlx5_ib_dev *ibdev;
877 struct mlx5_core_dev *mdev;
878 struct notifier_block mdev_events;
879 struct completion unref_comp;
886 struct mlx5_ib_flow_action {
887 struct ib_flow_action ib_action;
891 struct mlx5_accel_esp_xfrm *ctx;
894 struct mlx5_ib_dev *dev;
897 struct mlx5_modify_hdr *modify_hdr;
898 struct mlx5_pkt_reformat *pkt_reformat;
905 struct mlx5_core_dev *dev;
906 /* This lock is used to protect the access to the shared
907 * allocation map when concurrent requests by different
908 * processes are handled.
911 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
914 struct mlx5_read_counters_attr {
915 struct mlx5_fc *hw_cntrs_hndl;
920 enum mlx5_ib_counters_type {
921 MLX5_IB_COUNTERS_FLOW,
924 struct mlx5_ib_mcounters {
925 struct ib_counters ibcntrs;
926 enum mlx5_ib_counters_type type;
927 /* number of counters supported for this counters type */
929 struct mlx5_fc *hw_cntrs_hndl;
930 /* read function for this counters type */
931 int (*read_counters)(struct ib_device *ibdev,
932 struct mlx5_read_counters_attr *read_attr);
933 /* max index set as part of create_flow */
935 /* number of counters data entries (<description,index> pair) */
937 /* counters data array for descriptions and indexes */
938 struct mlx5_ib_flow_counters_desc *counters_data;
939 /* protects access to mcounters internal data */
940 struct mutex mcntrs_mutex;
943 static inline struct mlx5_ib_mcounters *
944 to_mcounters(struct ib_counters *ibcntrs)
946 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
949 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
951 struct mlx5_flow_act *action);
952 struct mlx5_ib_lb_state {
953 /* protect the user_td */
960 struct mlx5_ib_pf_eq {
961 struct notifier_block irq_nb;
962 struct mlx5_ib_dev *dev;
963 struct mlx5_eq *core;
964 struct work_struct work;
965 spinlock_t lock; /* Pagefaults spinlock */
966 struct workqueue_struct *wq;
970 struct mlx5_devx_event_table {
971 struct mlx5_nb devx_nb;
972 /* serialize updating the event_xa */
973 struct mutex event_xa_lock;
974 struct xarray event_xa;
977 struct mlx5_var_table {
978 /* serialize updating the bitmap */
979 struct mutex bitmap_lock;
980 unsigned long *bitmap;
983 u64 num_var_hw_entries;
987 struct ib_device ib_dev;
988 struct mlx5_core_dev *mdev;
989 struct notifier_block mdev_events;
991 /* serialize update of capability mask
993 struct mutex cap_mask_mutex;
999 struct umr_common umrc;
1000 /* sync used page count stats
1002 struct mlx5_ib_resources devr;
1005 struct mlx5_mr_cache cache;
1006 struct timer_list delay_timer;
1007 /* Prevents soft lock on massive reg MRs */
1008 struct mutex slow_path_mutex;
1009 struct ib_odp_caps odp_caps;
1011 struct mlx5_ib_pf_eq odp_pf_eq;
1014 * Sleepable RCU that prevents destruction of MRs while they are still
1015 * being used by a page fault handler.
1017 struct srcu_struct odp_srcu;
1018 struct xarray odp_mkeys;
1021 struct mlx5_ib_flow_db *flow_db;
1022 /* protect resources needed as part of reset flow */
1023 spinlock_t reset_flow_resource_lock;
1024 struct list_head qp_list;
1025 /* Array with num_ports elements */
1026 struct mlx5_ib_port *port;
1027 struct mlx5_sq_bfreg bfreg;
1028 struct mlx5_sq_bfreg wc_bfreg;
1029 struct mlx5_sq_bfreg fp_bfreg;
1030 struct mlx5_ib_delay_drop delay_drop;
1031 const struct mlx5_ib_profile *profile;
1033 struct mlx5_ib_lb_state lb;
1035 struct list_head ib_dev_list;
1038 u16 devx_whitelist_uid;
1039 struct mlx5_srq_table srq_table;
1040 struct mlx5_qp_table qp_table;
1041 struct mlx5_async_ctx async_ctx;
1042 struct mlx5_devx_event_table devx_event_table;
1043 struct mlx5_var_table var_table;
1045 struct xarray sig_mrs;
1048 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1050 return container_of(mcq, struct mlx5_ib_cq, mcq);
1053 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1055 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1058 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1060 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1063 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1065 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1066 udata, struct mlx5_ib_ucontext, ibucontext);
1068 return to_mdev(context->ibucontext.device);
1071 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1073 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1076 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1078 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1081 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1083 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1086 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
1088 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
1091 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1093 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1096 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1098 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1101 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1103 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1106 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1108 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1111 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1113 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1116 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1118 return container_of(msrq, struct mlx5_ib_srq, msrq);
1121 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
1123 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
1126 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1128 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1131 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1133 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1136 static inline struct mlx5_ib_flow_action *
1137 to_mflow_act(struct ib_flow_action *ibact)
1139 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1142 static inline struct mlx5_user_mmap_entry *
1143 to_mmmap(struct rdma_user_mmap_entry *rdma_entry)
1145 return container_of(rdma_entry,
1146 struct mlx5_user_mmap_entry, rdma_entry);
1149 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context,
1150 struct ib_udata *udata, unsigned long virt,
1151 struct mlx5_db *db);
1152 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1153 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1154 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1155 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1156 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, u32 flags,
1157 struct ib_udata *udata);
1158 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1159 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags);
1160 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1161 struct ib_udata *udata);
1162 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1163 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1164 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1165 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1166 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1167 const struct ib_recv_wr **bad_wr);
1168 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1169 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1170 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1171 struct ib_qp_init_attr *init_attr,
1172 struct ib_udata *udata);
1173 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1174 int attr_mask, struct ib_udata *udata);
1175 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1176 struct ib_qp_init_attr *qp_init_attr);
1177 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1178 void mlx5_ib_drain_sq(struct ib_qp *qp);
1179 void mlx5_ib_drain_rq(struct ib_qp *qp);
1180 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1181 const struct ib_send_wr **bad_wr);
1182 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1183 const struct ib_recv_wr **bad_wr);
1184 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1185 size_t buflen, size_t *bc);
1186 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1187 size_t buflen, size_t *bc);
1188 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1189 size_t buflen, size_t *bc);
1190 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1191 struct ib_udata *udata);
1192 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1193 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1194 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1195 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1196 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1197 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1198 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1199 u64 virt_addr, int access_flags,
1200 struct ib_udata *udata);
1201 int mlx5_ib_advise_mr(struct ib_pd *pd,
1202 enum ib_uverbs_advise_mr_advice advice,
1204 struct ib_sge *sg_list,
1206 struct uverbs_attr_bundle *attrs);
1207 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1208 struct ib_udata *udata);
1209 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1210 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1211 int page_shift, int flags);
1212 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1213 struct ib_udata *udata,
1215 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1216 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr);
1217 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1218 u64 length, u64 virt_addr, int access_flags,
1219 struct ib_pd *pd, struct ib_udata *udata);
1220 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1221 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1222 u32 max_num_sg, struct ib_udata *udata);
1223 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1225 u32 max_num_meta_sg);
1226 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1227 unsigned int *sg_offset);
1228 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1229 int data_sg_nents, unsigned int *data_sg_offset,
1230 struct scatterlist *meta_sg, int meta_sg_nents,
1231 unsigned int *meta_sg_offset);
1232 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1233 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1234 const struct ib_mad *in, struct ib_mad *out,
1235 size_t *out_mad_size, u16 *out_mad_pkey_index);
1236 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1237 struct ib_udata *udata);
1238 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1239 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1240 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1241 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1242 struct ib_smp *out_mad);
1243 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1244 __be64 *sys_image_guid);
1245 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1247 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1249 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1250 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1251 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1253 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1255 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1256 struct ib_port_attr *props);
1257 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1258 struct ib_port_attr *props);
1259 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
1260 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
1261 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1262 unsigned long max_page_shift,
1263 int *count, int *shift,
1264 int *ncont, int *order);
1265 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1266 int page_shift, size_t offset, size_t num_pages,
1267 __be64 *pas, int access_flags);
1268 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1269 int page_shift, __be64 *pas, int access_flags);
1270 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1271 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1272 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1273 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1275 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
1276 unsigned int entry);
1277 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1278 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr);
1280 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1281 struct ib_mr_status *mr_status);
1282 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1283 struct ib_wq_init_attr *init_attr,
1284 struct ib_udata *udata);
1285 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1286 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1287 u32 wq_attr_mask, struct ib_udata *udata);
1288 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1289 struct ib_rwq_ind_table_init_attr *init_attr,
1290 struct ib_udata *udata);
1291 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1292 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1293 struct ib_ucontext *context,
1294 struct ib_dm_alloc_attr *attr,
1295 struct uverbs_attr_bundle *attrs);
1296 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs);
1297 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1298 struct ib_dm_mr_attr *attr,
1299 struct uverbs_attr_bundle *attrs);
1301 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1302 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1303 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1304 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1305 int __init mlx5_ib_odp_init(void);
1306 void mlx5_ib_odp_cleanup(void);
1307 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1308 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1309 struct mlx5_ib_mr *mr, int flags);
1311 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1312 enum ib_uverbs_advise_mr_advice advice,
1313 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1314 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1315 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1320 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1321 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
1322 static inline int mlx5_ib_odp_init(void) { return 0; }
1323 static inline void mlx5_ib_odp_cleanup(void) {}
1324 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
1325 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1326 struct mlx5_ib_mr *mr, int flags) {}
1329 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1330 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1331 struct ib_sge *sg_list, u32 num_sge)
1335 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1337 extern const struct mmu_interval_notifier_ops mlx5_mn_ops;
1339 /* Needed for rep profile */
1340 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1341 const struct mlx5_ib_profile *profile,
1343 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1344 const struct mlx5_ib_profile *profile);
1346 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1347 u8 port, struct ifla_vf_info *info);
1348 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1349 u8 port, int state);
1350 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1351 u8 port, struct ifla_vf_stats *stats);
1352 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port,
1353 struct ifla_vf_guid *node_guid,
1354 struct ifla_vf_guid *port_guid);
1355 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1356 u64 guid, int type);
1358 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
1359 const struct ib_gid_attr *attr);
1361 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1362 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1364 /* GSI QP helper functions */
1365 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1366 struct ib_qp_init_attr *init_attr);
1367 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1368 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1370 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1372 struct ib_qp_init_attr *qp_init_attr);
1373 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1374 const struct ib_send_wr **bad_wr);
1375 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1376 const struct ib_recv_wr **bad_wr);
1377 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1379 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1381 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1383 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1384 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1386 u8 *native_port_num);
1387 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1389 int mlx5_ib_fill_res_entry(struct sk_buff *msg,
1390 struct rdma_restrack_entry *res);
1391 int mlx5_ib_fill_stat_entry(struct sk_buff *msg,
1392 struct rdma_restrack_entry *res);
1394 extern const struct uapi_definition mlx5_ib_devx_defs[];
1395 extern const struct uapi_definition mlx5_ib_flow_defs[];
1396 extern const struct uapi_definition mlx5_ib_qos_defs[];
1398 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
1399 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user);
1400 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid);
1401 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev);
1402 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev);
1403 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1404 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1405 struct mlx5_flow_context *flow_context,
1406 struct mlx5_flow_act *flow_act, u32 counter_id,
1407 void *cmd_in, int inlen, int dest_id, int dest_type);
1408 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type);
1409 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 offset, u32 *counter_id);
1410 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction);
1413 mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1414 bool is_user) { return -EOPNOTSUPP; }
1415 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {}
1416 static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {}
1417 static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {}
1418 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id,
1424 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction)
1429 static inline void init_query_mad(struct ib_smp *mad)
1431 mad->base_version = 1;
1432 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1433 mad->class_version = 1;
1434 mad->method = IB_MGMT_METHOD_GET;
1437 static inline u8 convert_access(int acc)
1439 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1440 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1441 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1442 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1443 MLX5_PERM_LOCAL_READ;
1446 static inline int is_qp1(enum ib_qp_type qp_type)
1448 return qp_type == MLX5_IB_QPT_HW_GSI;
1451 #define MLX5_MAX_UMR_SHIFT 16
1452 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1454 static inline u32 check_cq_create_flags(u32 flags)
1457 * It returns non-zero value for unsupported CQ
1458 * create flags, otherwise it returns zero.
1460 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1461 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1464 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1468 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1469 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1471 *user_index = cmd_uidx;
1473 *user_index = MLX5_IB_DEFAULT_UIDX;
1479 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1480 struct mlx5_ib_create_qp *ucmd,
1484 u8 cqe_version = ucontext->cqe_version;
1486 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1487 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1490 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1493 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1496 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1497 struct mlx5_ib_create_srq *ucmd,
1501 u8 cqe_version = ucontext->cqe_version;
1503 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1504 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1507 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1510 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1513 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1515 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1516 MLX5_UARS_IN_PAGE : 1;
1519 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1520 struct mlx5_bfreg_info *bfregi)
1522 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1525 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1526 void mlx5_ib_put_xlt_emergency_page(void);
1528 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1529 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1532 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter);
1533 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num);
1535 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev,
1536 bool do_modify_atomic, int access_flags)
1538 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
1541 if (do_modify_atomic &&
1542 MLX5_CAP_GEN(dev->mdev, atomic) &&
1543 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
1546 if (access_flags & IB_ACCESS_RELAXED_ORDERING &&
1547 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) ||
1548 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)))
1554 int mlx5_ib_enable_driver(struct ib_device *dev);
1555 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev);
1556 #endif /* MLX5_IB_H */