2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/bitmap.h>
42 #if defined(CONFIG_X86)
45 #include <linux/sched.h>
46 #include <linux/sched/mm.h>
47 #include <linux/sched/task.h>
48 #include <linux/delay.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_cache.h>
52 #include <linux/mlx5/port.h>
53 #include <linux/mlx5/vport.h>
54 #include <linux/mlx5/fs.h>
55 #include <linux/list.h>
56 #include <rdma/ib_smi.h>
57 #include <rdma/ib_umem.h>
59 #include <linux/etherdevice.h>
63 #include <linux/mlx5/fs_helpers.h>
64 #include <linux/mlx5/accel.h>
65 #include <rdma/uverbs_std_types.h>
66 #include <rdma/mlx5_user_ioctl_verbs.h>
67 #include <rdma/mlx5_user_ioctl_cmds.h>
69 #define UVERBS_MODULE_NAME mlx5_ib
70 #include <rdma/uverbs_named_ioctl.h>
72 #define DRIVER_NAME "mlx5_ib"
73 #define DRIVER_VERSION "5.0-0"
75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77 MODULE_LICENSE("Dual BSD/GPL");
79 static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
83 struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
87 enum mlx5_dev_event event;
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
95 static struct workqueue_struct *mlx5_ib_event_wq;
96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97 static LIST_HEAD(mlx5_ib_dev_list);
99 * This mutex should be held when accessing either of the above lists
101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
103 /* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
106 static unsigned long xlt_emergency_page;
107 static struct mutex xlt_emergency_page_mutex;
109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
111 struct mlx5_ib_dev *dev;
113 mutex_lock(&mlx5_ib_multiport_mutex);
115 mutex_unlock(&mlx5_ib_multiport_mutex);
119 static enum rdma_link_layer
120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
122 switch (port_type_cap) {
123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
128 return IB_LINK_LAYER_UNSPECIFIED;
132 static enum rdma_link_layer
133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
141 static int get_port_state(struct ib_device *ibdev,
143 enum ib_port_state *state)
145 struct ib_port_attr attr;
148 memset(&attr, 0, sizeof(attr));
149 ret = ibdev->query_port(ibdev, port_num, &attr);
155 static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
172 write_lock(&roce->netdev_lock);
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
183 roce->netdev = (event == NETDEV_UNREGISTER) ?
186 write_unlock(&roce->netdev_lock);
192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
193 struct net_device *upper = NULL;
196 upper = netdev_master_upper_dev_get(lag_ndev);
200 if ((upper == ndev || (!upper && ndev == roce->netdev))
201 && ibdev->ib_active) {
202 struct ib_event ibev = { };
203 enum ib_port_state port_state;
205 if (get_port_state(&ibdev->ib_dev, port_num,
209 if (roce->last_port_state == port_state)
212 roce->last_port_state = port_state;
213 ibev.device = &ibdev->ib_dev;
214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
221 ibev.element.port_num = port_num;
222 ib_dispatch_event(&ibev);
231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
240 struct mlx5_core_dev *mdev;
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
246 ndev = mlx5_lag_get_roce_netdev(mdev);
250 /* Ensure ndev does not disappear before we invoke dev_hold()
252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
276 *native_port_num = ib_port_num;
281 *native_port_num = 1;
283 port = &ibdev->port[ib_port_num - 1];
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
297 spin_unlock(&port->mp.mpi_lock);
302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
312 port = &ibdev->port[port_num - 1];
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
323 spin_unlock(&port->mp.mpi_lock);
326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
387 struct mlx5_ib_dev *dev = to_mdev(device);
388 struct mlx5_core_dev *mdev;
389 struct net_device *ndev, *upper;
390 enum ib_mtu ndev_ib_mtu;
391 bool put_mdev = true;
397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
411 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper,
416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
434 props->qkey_viol_cntr = qkey_viol_cntr;
436 /* If this is a stub query for an unaffiliated port stop here */
440 ndev = mlx5_ib_get_netdev(device, port_num);
444 if (mlx5_lag_is_active(dev->mdev)) {
446 upper = netdev_master_upper_dev_get_rcu(ndev);
455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
467 mlx5_ib_put_native_port_mdev(dev, port_num);
471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
486 if (is_vlan_dev(attr->ndev)) {
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
494 roce_version = MLX5_ROCE_VERSION_1;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
513 static int mlx5_ib_add_gid(const union ib_gid *gid,
514 const struct ib_gid_attr *attr,
515 __always_unused void **context)
517 return set_roce_addr(to_mdev(attr->device), attr->port_num,
518 attr->index, gid, attr);
521 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
522 __always_unused void **context)
524 return set_roce_addr(to_mdev(attr->device), attr->port_num,
525 attr->index, NULL, NULL);
528 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
531 struct ib_gid_attr attr;
534 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
539 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
542 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
545 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
546 int index, enum ib_gid_type *gid_type)
548 struct ib_gid_attr attr;
552 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
558 *gid_type = attr.gid_type;
563 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
565 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
566 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
571 MLX5_VPORT_ACCESS_METHOD_MAD,
572 MLX5_VPORT_ACCESS_METHOD_HCA,
573 MLX5_VPORT_ACCESS_METHOD_NIC,
576 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
578 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
579 return MLX5_VPORT_ACCESS_METHOD_MAD;
581 if (mlx5_ib_port_link_layer(ibdev, 1) ==
582 IB_LINK_LAYER_ETHERNET)
583 return MLX5_VPORT_ACCESS_METHOD_NIC;
585 return MLX5_VPORT_ACCESS_METHOD_HCA;
588 static void get_atomic_caps(struct mlx5_ib_dev *dev,
590 struct ib_device_attr *props)
593 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
594 u8 atomic_req_8B_endianness_mode =
595 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
597 /* Check if HW supports 8 bytes standard atomic operations and capable
598 * of host endianness respond
600 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
601 if (((atomic_operations & tmp) == tmp) &&
602 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
603 (atomic_req_8B_endianness_mode)) {
604 props->atomic_cap = IB_ATOMIC_HCA;
606 props->atomic_cap = IB_ATOMIC_NONE;
610 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
611 struct ib_device_attr *props)
613 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
615 get_atomic_caps(dev, atomic_size_qp, props);
618 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
619 struct ib_device_attr *props)
621 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
623 get_atomic_caps(dev, atomic_size_qp, props);
626 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
628 struct ib_device_attr props = {};
630 get_atomic_caps_dc(dev, &props);
631 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
633 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
634 __be64 *sys_image_guid)
636 struct mlx5_ib_dev *dev = to_mdev(ibdev);
637 struct mlx5_core_dev *mdev = dev->mdev;
641 switch (mlx5_get_vport_access_method(ibdev)) {
642 case MLX5_VPORT_ACCESS_METHOD_MAD:
643 return mlx5_query_mad_ifc_system_image_guid(ibdev,
646 case MLX5_VPORT_ACCESS_METHOD_HCA:
647 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
650 case MLX5_VPORT_ACCESS_METHOD_NIC:
651 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
659 *sys_image_guid = cpu_to_be64(tmp);
665 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
668 struct mlx5_ib_dev *dev = to_mdev(ibdev);
669 struct mlx5_core_dev *mdev = dev->mdev;
671 switch (mlx5_get_vport_access_method(ibdev)) {
672 case MLX5_VPORT_ACCESS_METHOD_MAD:
673 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
675 case MLX5_VPORT_ACCESS_METHOD_HCA:
676 case MLX5_VPORT_ACCESS_METHOD_NIC:
677 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
686 static int mlx5_query_vendor_id(struct ib_device *ibdev,
689 struct mlx5_ib_dev *dev = to_mdev(ibdev);
691 switch (mlx5_get_vport_access_method(ibdev)) {
692 case MLX5_VPORT_ACCESS_METHOD_MAD:
693 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
695 case MLX5_VPORT_ACCESS_METHOD_HCA:
696 case MLX5_VPORT_ACCESS_METHOD_NIC:
697 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
704 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
710 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
711 case MLX5_VPORT_ACCESS_METHOD_MAD:
712 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
714 case MLX5_VPORT_ACCESS_METHOD_HCA:
715 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
718 case MLX5_VPORT_ACCESS_METHOD_NIC:
719 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
727 *node_guid = cpu_to_be64(tmp);
732 struct mlx5_reg_node_desc {
733 u8 desc[IB_DEVICE_NODE_DESC_MAX];
736 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
738 struct mlx5_reg_node_desc in;
740 if (mlx5_use_mad_ifc(dev))
741 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
743 memset(&in, 0, sizeof(in));
745 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
746 sizeof(struct mlx5_reg_node_desc),
747 MLX5_REG_NODE_DESC, 0, 0);
750 static int mlx5_ib_query_device(struct ib_device *ibdev,
751 struct ib_device_attr *props,
752 struct ib_udata *uhw)
754 struct mlx5_ib_dev *dev = to_mdev(ibdev);
755 struct mlx5_core_dev *mdev = dev->mdev;
760 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
761 bool raw_support = !mlx5_core_mp_enabled(mdev);
762 struct mlx5_ib_query_device_resp resp = {};
766 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
767 if (uhw->outlen && uhw->outlen < resp_len)
770 resp.response_length = resp_len;
772 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
775 memset(props, 0, sizeof(*props));
776 err = mlx5_query_system_image_guid(ibdev,
777 &props->sys_image_guid);
781 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
785 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
789 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
790 (fw_rev_min(dev->mdev) << 16) |
791 fw_rev_sub(dev->mdev);
792 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
793 IB_DEVICE_PORT_ACTIVE_EVENT |
794 IB_DEVICE_SYS_IMAGE_GUID |
795 IB_DEVICE_RC_RNR_NAK_GEN;
797 if (MLX5_CAP_GEN(mdev, pkv))
798 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
799 if (MLX5_CAP_GEN(mdev, qkv))
800 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
801 if (MLX5_CAP_GEN(mdev, apm))
802 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
803 if (MLX5_CAP_GEN(mdev, xrc))
804 props->device_cap_flags |= IB_DEVICE_XRC;
805 if (MLX5_CAP_GEN(mdev, imaicl)) {
806 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
807 IB_DEVICE_MEM_WINDOW_TYPE_2B;
808 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
809 /* We support 'Gappy' memory registration too */
810 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
812 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
813 if (MLX5_CAP_GEN(mdev, sho)) {
814 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
815 /* At this stage no support for signature handover */
816 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
817 IB_PROT_T10DIF_TYPE_2 |
818 IB_PROT_T10DIF_TYPE_3;
819 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
820 IB_GUARD_T10DIF_CSUM;
822 if (MLX5_CAP_GEN(mdev, block_lb_mc))
823 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
825 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
826 if (MLX5_CAP_ETH(mdev, csum_cap)) {
827 /* Legacy bit to support old userspace libraries */
828 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
829 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
832 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
833 props->raw_packet_caps |=
834 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
836 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
837 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
839 resp.tso_caps.max_tso = 1 << max_tso;
840 resp.tso_caps.supported_qpts |=
841 1 << IB_QPT_RAW_PACKET;
842 resp.response_length += sizeof(resp.tso_caps);
846 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
847 resp.rss_caps.rx_hash_function =
848 MLX5_RX_HASH_FUNC_TOEPLITZ;
849 resp.rss_caps.rx_hash_fields_mask =
850 MLX5_RX_HASH_SRC_IPV4 |
851 MLX5_RX_HASH_DST_IPV4 |
852 MLX5_RX_HASH_SRC_IPV6 |
853 MLX5_RX_HASH_DST_IPV6 |
854 MLX5_RX_HASH_SRC_PORT_TCP |
855 MLX5_RX_HASH_DST_PORT_TCP |
856 MLX5_RX_HASH_SRC_PORT_UDP |
857 MLX5_RX_HASH_DST_PORT_UDP |
859 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
860 MLX5_ACCEL_IPSEC_CAP_DEVICE)
861 resp.rss_caps.rx_hash_fields_mask |=
862 MLX5_RX_HASH_IPSEC_SPI;
863 resp.response_length += sizeof(resp.rss_caps);
866 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
867 resp.response_length += sizeof(resp.tso_caps);
868 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
869 resp.response_length += sizeof(resp.rss_caps);
872 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
873 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
874 props->device_cap_flags |= IB_DEVICE_UD_TSO;
877 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
878 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
880 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
882 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
883 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
884 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
886 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
887 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
889 /* Legacy bit to support old userspace libraries */
890 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
891 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
894 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
896 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
899 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
900 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
902 if (MLX5_CAP_GEN(mdev, end_pad))
903 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
905 props->vendor_part_id = mdev->pdev->device;
906 props->hw_ver = mdev->pdev->revision;
908 props->max_mr_size = ~0ull;
909 props->page_size_cap = ~(min_page_size - 1);
910 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
911 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
912 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
913 sizeof(struct mlx5_wqe_data_seg);
914 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
915 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
916 sizeof(struct mlx5_wqe_raddr_seg)) /
917 sizeof(struct mlx5_wqe_data_seg);
918 props->max_sge = min(max_rq_sg, max_sq_sg);
919 props->max_sge_rd = MLX5_MAX_SGE_RD;
920 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
921 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
922 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
923 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
924 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
925 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
926 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
927 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
928 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
929 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
930 props->max_srq_sge = max_rq_sg - 1;
931 props->max_fast_reg_page_list_len =
932 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
933 get_atomic_caps_qp(dev, props);
934 props->masked_atomic_cap = IB_ATOMIC_NONE;
935 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
936 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
937 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
938 props->max_mcast_grp;
939 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
940 props->max_ah = INT_MAX;
941 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
942 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
944 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
945 if (MLX5_CAP_GEN(mdev, pg))
946 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
947 props->odp_caps = dev->odp_caps;
950 if (MLX5_CAP_GEN(mdev, cd))
951 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
953 if (!mlx5_core_is_pf(mdev))
954 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
956 if (mlx5_ib_port_link_layer(ibdev, 1) ==
957 IB_LINK_LAYER_ETHERNET && raw_support) {
958 props->rss_caps.max_rwq_indirection_tables =
959 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
960 props->rss_caps.max_rwq_indirection_table_size =
961 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
962 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
963 props->max_wq_type_rq =
964 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
967 if (MLX5_CAP_GEN(mdev, tag_matching)) {
968 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
969 props->tm_caps.max_num_tags =
970 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
971 props->tm_caps.flags = IB_TM_CAP_RC;
972 props->tm_caps.max_ops =
973 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
974 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
977 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
978 props->cq_caps.max_cq_moderation_count =
980 props->cq_caps.max_cq_moderation_period =
984 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
985 resp.cqe_comp_caps.max_num =
986 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
987 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
988 resp.cqe_comp_caps.supported_format =
989 MLX5_IB_CQE_RES_FORMAT_HASH |
990 MLX5_IB_CQE_RES_FORMAT_CSUM;
991 resp.response_length += sizeof(resp.cqe_comp_caps);
994 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
996 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
997 MLX5_CAP_GEN(mdev, qos)) {
998 resp.packet_pacing_caps.qp_rate_limit_max =
999 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1000 resp.packet_pacing_caps.qp_rate_limit_min =
1001 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1002 resp.packet_pacing_caps.supported_qpts |=
1003 1 << IB_QPT_RAW_PACKET;
1004 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1005 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1006 resp.packet_pacing_caps.cap_flags |=
1007 MLX5_IB_PP_SUPPORT_BURST;
1009 resp.response_length += sizeof(resp.packet_pacing_caps);
1012 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1014 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1015 resp.mlx5_ib_support_multi_pkt_send_wqes =
1018 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1019 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1020 MLX5_IB_SUPPORT_EMPW;
1022 resp.response_length +=
1023 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1026 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1027 resp.response_length += sizeof(resp.flags);
1029 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1031 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1033 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1034 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1037 if (field_avail(typeof(resp), sw_parsing_caps,
1039 resp.response_length += sizeof(resp.sw_parsing_caps);
1040 if (MLX5_CAP_ETH(mdev, swp)) {
1041 resp.sw_parsing_caps.sw_parsing_offloads |=
1044 if (MLX5_CAP_ETH(mdev, swp_csum))
1045 resp.sw_parsing_caps.sw_parsing_offloads |=
1046 MLX5_IB_SW_PARSING_CSUM;
1048 if (MLX5_CAP_ETH(mdev, swp_lso))
1049 resp.sw_parsing_caps.sw_parsing_offloads |=
1050 MLX5_IB_SW_PARSING_LSO;
1052 if (resp.sw_parsing_caps.sw_parsing_offloads)
1053 resp.sw_parsing_caps.supported_qpts =
1054 BIT(IB_QPT_RAW_PACKET);
1058 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1060 resp.response_length += sizeof(resp.striding_rq_caps);
1061 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1062 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1063 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1064 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1065 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1066 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1067 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1068 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1069 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1070 resp.striding_rq_caps.supported_qpts =
1071 BIT(IB_QPT_RAW_PACKET);
1075 if (field_avail(typeof(resp), tunnel_offloads_caps,
1077 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1078 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1079 resp.tunnel_offloads_caps |=
1080 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1081 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1082 resp.tunnel_offloads_caps |=
1083 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1084 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1085 resp.tunnel_offloads_caps |=
1086 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1090 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1099 enum mlx5_ib_width {
1100 MLX5_IB_WIDTH_1X = 1 << 0,
1101 MLX5_IB_WIDTH_2X = 1 << 1,
1102 MLX5_IB_WIDTH_4X = 1 << 2,
1103 MLX5_IB_WIDTH_8X = 1 << 3,
1104 MLX5_IB_WIDTH_12X = 1 << 4
1107 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1110 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1113 if (active_width & MLX5_IB_WIDTH_1X) {
1114 *ib_width = IB_WIDTH_1X;
1115 } else if (active_width & MLX5_IB_WIDTH_2X) {
1116 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1119 } else if (active_width & MLX5_IB_WIDTH_4X) {
1120 *ib_width = IB_WIDTH_4X;
1121 } else if (active_width & MLX5_IB_WIDTH_8X) {
1122 *ib_width = IB_WIDTH_8X;
1123 } else if (active_width & MLX5_IB_WIDTH_12X) {
1124 *ib_width = IB_WIDTH_12X;
1126 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1134 static int mlx5_mtu_to_ib_mtu(int mtu)
1139 case 1024: return 3;
1140 case 2048: return 4;
1141 case 4096: return 5;
1143 pr_warn("invalid mtu\n");
1148 enum ib_max_vl_num {
1150 __IB_MAX_VL_0_1 = 2,
1151 __IB_MAX_VL_0_3 = 3,
1152 __IB_MAX_VL_0_7 = 4,
1153 __IB_MAX_VL_0_14 = 5,
1156 enum mlx5_vl_hw_cap {
1165 MLX5_VL_HW_0_14 = 15
1168 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1171 switch (vl_hw_cap) {
1173 *max_vl_num = __IB_MAX_VL_0;
1175 case MLX5_VL_HW_0_1:
1176 *max_vl_num = __IB_MAX_VL_0_1;
1178 case MLX5_VL_HW_0_3:
1179 *max_vl_num = __IB_MAX_VL_0_3;
1181 case MLX5_VL_HW_0_7:
1182 *max_vl_num = __IB_MAX_VL_0_7;
1184 case MLX5_VL_HW_0_14:
1185 *max_vl_num = __IB_MAX_VL_0_14;
1195 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1196 struct ib_port_attr *props)
1198 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1199 struct mlx5_core_dev *mdev = dev->mdev;
1200 struct mlx5_hca_vport_context *rep;
1204 u8 ib_link_width_oper;
1207 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1213 /* props being zeroed by the caller, avoid zeroing it here */
1215 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1219 props->lid = rep->lid;
1220 props->lmc = rep->lmc;
1221 props->sm_lid = rep->sm_lid;
1222 props->sm_sl = rep->sm_sl;
1223 props->state = rep->vport_state;
1224 props->phys_state = rep->port_physical_state;
1225 props->port_cap_flags = rep->cap_mask1;
1226 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1227 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1228 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1229 props->bad_pkey_cntr = rep->pkey_violation_counter;
1230 props->qkey_viol_cntr = rep->qkey_violation_counter;
1231 props->subnet_timeout = rep->subnet_timeout;
1232 props->init_type_reply = rep->init_type_reply;
1233 props->grh_required = rep->grh_required;
1235 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1239 err = translate_active_width(ibdev, ib_link_width_oper,
1240 &props->active_width);
1243 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1247 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1249 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1251 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1253 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1255 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1259 err = translate_max_vl_num(ibdev, vl_hw_cap,
1260 &props->max_vl_num);
1266 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1267 struct ib_port_attr *props)
1272 switch (mlx5_get_vport_access_method(ibdev)) {
1273 case MLX5_VPORT_ACCESS_METHOD_MAD:
1274 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1277 case MLX5_VPORT_ACCESS_METHOD_HCA:
1278 ret = mlx5_query_hca_port(ibdev, port, props);
1281 case MLX5_VPORT_ACCESS_METHOD_NIC:
1282 ret = mlx5_query_port_roce(ibdev, port, props);
1289 if (!ret && props) {
1290 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1291 struct mlx5_core_dev *mdev;
1292 bool put_mdev = true;
1294 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1296 /* If the port isn't affiliated yet query the master.
1297 * The master and slave will have the same values.
1303 count = mlx5_core_reserved_gids_count(mdev);
1305 mlx5_ib_put_native_port_mdev(dev, port);
1306 props->gid_tbl_len -= count;
1311 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1312 struct ib_port_attr *props)
1316 /* Only link layer == ethernet is valid for representors */
1317 ret = mlx5_query_port_roce(ibdev, port, props);
1321 /* We don't support GIDS */
1322 props->gid_tbl_len = 0;
1327 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1330 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1331 struct mlx5_core_dev *mdev = dev->mdev;
1333 switch (mlx5_get_vport_access_method(ibdev)) {
1334 case MLX5_VPORT_ACCESS_METHOD_MAD:
1335 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1337 case MLX5_VPORT_ACCESS_METHOD_HCA:
1338 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1346 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1347 u16 index, u16 *pkey)
1349 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1350 struct mlx5_core_dev *mdev;
1351 bool put_mdev = true;
1355 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1357 /* The port isn't affiliated yet, get the PKey from the master
1358 * port. For RoCE the PKey tables will be the same.
1365 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1368 mlx5_ib_put_native_port_mdev(dev, port);
1373 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1376 switch (mlx5_get_vport_access_method(ibdev)) {
1377 case MLX5_VPORT_ACCESS_METHOD_MAD:
1378 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1380 case MLX5_VPORT_ACCESS_METHOD_HCA:
1381 case MLX5_VPORT_ACCESS_METHOD_NIC:
1382 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1388 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1389 struct ib_device_modify *props)
1391 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1392 struct mlx5_reg_node_desc in;
1393 struct mlx5_reg_node_desc out;
1396 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1399 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1403 * If possible, pass node desc to FW, so it can generate
1404 * a 144 trap. If cmd fails, just ignore.
1406 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1407 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1408 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1412 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1417 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1420 struct mlx5_hca_vport_context ctx = {};
1421 struct mlx5_core_dev *mdev;
1425 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1429 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1433 if (~ctx.cap_mask1_perm & mask) {
1434 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1435 mask, ctx.cap_mask1_perm);
1440 ctx.cap_mask1 = value;
1441 ctx.cap_mask1_perm = mask;
1442 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1446 mlx5_ib_put_native_port_mdev(dev, port_num);
1451 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1452 struct ib_port_modify *props)
1454 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1455 struct ib_port_attr attr;
1460 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1461 IB_LINK_LAYER_INFINIBAND);
1463 /* CM layer calls ib_modify_port() regardless of the link layer. For
1464 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1469 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1470 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1471 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1472 return set_port_caps_atomic(dev, port, change_mask, value);
1475 mutex_lock(&dev->cap_mask_mutex);
1477 err = ib_query_port(ibdev, port, &attr);
1481 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1482 ~props->clr_port_cap_mask;
1484 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1487 mutex_unlock(&dev->cap_mask_mutex);
1491 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1493 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1494 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1497 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1499 /* Large page with non 4k uar support might limit the dynamic size */
1500 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1501 return MLX5_MIN_DYN_BFREGS;
1503 return MLX5_MAX_DYN_BFREGS;
1506 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1507 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1508 struct mlx5_bfreg_info *bfregi)
1510 int uars_per_sys_page;
1511 int bfregs_per_sys_page;
1512 int ref_bfregs = req->total_num_bfregs;
1514 if (req->total_num_bfregs == 0)
1517 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1518 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1520 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1523 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1524 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1525 /* This holds the required static allocation asked by the user */
1526 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1527 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1530 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1531 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1532 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1533 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1535 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1536 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1537 lib_uar_4k ? "yes" : "no", ref_bfregs,
1538 req->total_num_bfregs, bfregi->total_num_bfregs,
1539 bfregi->num_sys_pages);
1544 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1546 struct mlx5_bfreg_info *bfregi;
1550 bfregi = &context->bfregi;
1551 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1552 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1556 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1559 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1560 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1565 for (--i; i >= 0; i--)
1566 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1567 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1572 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1574 struct mlx5_bfreg_info *bfregi;
1578 bfregi = &context->bfregi;
1579 for (i = 0; i < bfregi->num_sys_pages; i++) {
1580 if (i < bfregi->num_static_sys_pages ||
1581 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1582 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1584 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1593 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1597 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1601 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1602 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1603 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1606 mutex_lock(&dev->lb_mutex);
1609 if (dev->user_td == 2)
1610 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1612 mutex_unlock(&dev->lb_mutex);
1616 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1618 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1620 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1621 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1622 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1625 mutex_lock(&dev->lb_mutex);
1628 if (dev->user_td < 2)
1629 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1631 mutex_unlock(&dev->lb_mutex);
1634 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1635 struct ib_udata *udata)
1637 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1638 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1639 struct mlx5_ib_alloc_ucontext_resp resp = {};
1640 struct mlx5_core_dev *mdev = dev->mdev;
1641 struct mlx5_ib_ucontext *context;
1642 struct mlx5_bfreg_info *bfregi;
1645 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1649 if (!dev->ib_active)
1650 return ERR_PTR(-EAGAIN);
1652 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1654 else if (udata->inlen >= min_req_v2)
1657 return ERR_PTR(-EINVAL);
1659 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1661 return ERR_PTR(err);
1664 return ERR_PTR(-EINVAL);
1666 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1667 return ERR_PTR(-EOPNOTSUPP);
1669 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1670 MLX5_NON_FP_BFREGS_PER_UAR);
1671 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1672 return ERR_PTR(-EINVAL);
1674 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1675 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1676 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1677 resp.cache_line_size = cache_line_size();
1678 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1679 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1680 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1681 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1682 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1683 resp.cqe_version = min_t(__u8,
1684 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1685 req.max_cqe_version);
1686 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1687 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1688 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1689 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1690 resp.response_length = min(offsetof(typeof(resp), response_length) +
1691 sizeof(resp.response_length), udata->outlen);
1693 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1694 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1695 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1696 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1697 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1698 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1699 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1700 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1701 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1702 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1705 context = kzalloc(sizeof(*context), GFP_KERNEL);
1707 return ERR_PTR(-ENOMEM);
1709 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1710 bfregi = &context->bfregi;
1712 /* updates req->total_num_bfregs */
1713 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1717 mutex_init(&bfregi->lock);
1718 bfregi->lib_uar_4k = lib_uar_4k;
1719 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1721 if (!bfregi->count) {
1726 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1727 sizeof(*bfregi->sys_pages),
1729 if (!bfregi->sys_pages) {
1734 err = allocate_uars(dev, context);
1738 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1739 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1742 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1743 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1748 INIT_LIST_HEAD(&context->vma_private_list);
1749 mutex_init(&context->vma_private_list_mutex);
1750 INIT_LIST_HEAD(&context->db_page_list);
1751 mutex_init(&context->db_page_mutex);
1753 resp.tot_bfregs = req.total_num_bfregs;
1754 resp.num_ports = dev->num_ports;
1756 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1757 resp.response_length += sizeof(resp.cqe_version);
1759 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1760 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1761 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1762 resp.response_length += sizeof(resp.cmds_supp_uhw);
1765 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1766 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1767 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1768 resp.eth_min_inline++;
1770 resp.response_length += sizeof(resp.eth_min_inline);
1773 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1774 if (mdev->clock_info)
1775 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1776 resp.response_length += sizeof(resp.clock_info_versions);
1780 * We don't want to expose information from the PCI bar that is located
1781 * after 4096 bytes, so if the arch only supports larger pages, let's
1782 * pretend we don't support reading the HCA's core clock. This is also
1783 * forced by mmap function.
1785 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1786 if (PAGE_SIZE <= 4096) {
1788 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1789 resp.hca_core_clock_offset =
1790 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1792 resp.response_length += sizeof(resp.hca_core_clock_offset);
1795 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1796 resp.response_length += sizeof(resp.log_uar_size);
1798 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1799 resp.response_length += sizeof(resp.num_uars_per_page);
1801 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1802 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1803 resp.response_length += sizeof(resp.num_dyn_bfregs);
1806 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1811 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1812 context->cqe_version = resp.cqe_version;
1813 context->lib_caps = req.lib_caps;
1814 print_lib_caps(dev, context->lib_caps);
1816 return &context->ibucontext;
1819 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1820 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1823 deallocate_uars(dev, context);
1826 kfree(bfregi->sys_pages);
1829 kfree(bfregi->count);
1834 return ERR_PTR(err);
1837 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1839 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1840 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1841 struct mlx5_bfreg_info *bfregi;
1843 bfregi = &context->bfregi;
1844 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1845 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1847 deallocate_uars(dev, context);
1848 kfree(bfregi->sys_pages);
1849 kfree(bfregi->count);
1855 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1858 int fw_uars_per_page;
1860 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1862 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1865 static int get_command(unsigned long offset)
1867 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1870 static int get_arg(unsigned long offset)
1872 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1875 static int get_index(unsigned long offset)
1877 return get_arg(offset);
1880 /* Index resides in an extra byte to enable larger values than 255 */
1881 static int get_extended_index(unsigned long offset)
1883 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1886 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1888 /* vma_open is called when a new VMA is created on top of our VMA. This
1889 * is done through either mremap flow or split_vma (usually due to
1890 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1891 * as this VMA is strongly hardware related. Therefore we set the
1892 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1893 * calling us again and trying to do incorrect actions. We assume that
1894 * the original VMA size is exactly a single page, and therefore all
1895 * "splitting" operation will not happen to it.
1897 area->vm_ops = NULL;
1900 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1902 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1904 /* It's guaranteed that all VMAs opened on a FD are closed before the
1905 * file itself is closed, therefore no sync is needed with the regular
1906 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1907 * However need a sync with accessing the vma as part of
1908 * mlx5_ib_disassociate_ucontext.
1909 * The close operation is usually called under mm->mmap_sem except when
1910 * process is exiting.
1911 * The exiting case is handled explicitly as part of
1912 * mlx5_ib_disassociate_ucontext.
1914 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1916 /* setting the vma context pointer to null in the mlx5_ib driver's
1917 * private data, to protect a race condition in
1918 * mlx5_ib_disassociate_ucontext().
1920 mlx5_ib_vma_priv_data->vma = NULL;
1921 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1922 list_del(&mlx5_ib_vma_priv_data->list);
1923 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1924 kfree(mlx5_ib_vma_priv_data);
1927 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1928 .open = mlx5_ib_vma_open,
1929 .close = mlx5_ib_vma_close
1932 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1933 struct mlx5_ib_ucontext *ctx)
1935 struct mlx5_ib_vma_private_data *vma_prv;
1936 struct list_head *vma_head = &ctx->vma_private_list;
1938 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1943 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1944 vma->vm_private_data = vma_prv;
1945 vma->vm_ops = &mlx5_ib_vm_ops;
1947 mutex_lock(&ctx->vma_private_list_mutex);
1948 list_add(&vma_prv->list, vma_head);
1949 mutex_unlock(&ctx->vma_private_list_mutex);
1954 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1957 struct vm_area_struct *vma;
1958 struct mlx5_ib_vma_private_data *vma_private, *n;
1959 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1960 struct task_struct *owning_process = NULL;
1961 struct mm_struct *owning_mm = NULL;
1963 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1964 if (!owning_process)
1967 owning_mm = get_task_mm(owning_process);
1969 pr_info("no mm, disassociate ucontext is pending task termination\n");
1971 put_task_struct(owning_process);
1972 usleep_range(1000, 2000);
1973 owning_process = get_pid_task(ibcontext->tgid,
1975 if (!owning_process ||
1976 owning_process->state == TASK_DEAD) {
1977 pr_info("disassociate ucontext done, task was terminated\n");
1978 /* in case task was dead need to release the
1982 put_task_struct(owning_process);
1988 /* need to protect from a race on closing the vma as part of
1989 * mlx5_ib_vma_close.
1991 down_write(&owning_mm->mmap_sem);
1992 mutex_lock(&context->vma_private_list_mutex);
1993 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1995 vma = vma_private->vma;
1996 ret = zap_vma_ptes(vma, vma->vm_start,
1998 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1999 /* context going to be destroyed, should
2000 * not access ops any more.
2002 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
2004 list_del(&vma_private->list);
2007 mutex_unlock(&context->vma_private_list_mutex);
2008 up_write(&owning_mm->mmap_sem);
2010 put_task_struct(owning_process);
2013 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2016 case MLX5_IB_MMAP_WC_PAGE:
2018 case MLX5_IB_MMAP_REGULAR_PAGE:
2019 return "best effort WC";
2020 case MLX5_IB_MMAP_NC_PAGE:
2022 case MLX5_IB_MMAP_DEVICE_MEM:
2023 return "Device Memory";
2029 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2030 struct vm_area_struct *vma,
2031 struct mlx5_ib_ucontext *context)
2036 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2039 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2042 if (vma->vm_flags & VM_WRITE)
2045 if (!dev->mdev->clock_info_page)
2048 pfn = page_to_pfn(dev->mdev->clock_info_page);
2049 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2054 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2056 (unsigned long long)pfn << PAGE_SHIFT);
2058 return mlx5_ib_set_vma_data(vma, context);
2061 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2062 struct vm_area_struct *vma,
2063 struct mlx5_ib_ucontext *context)
2065 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2068 phys_addr_t pfn, pa;
2070 u32 bfreg_dyn_idx = 0;
2072 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2073 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2074 bfregi->num_static_sys_pages;
2076 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2080 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2082 idx = get_index(vma->vm_pgoff);
2084 if (idx >= max_valid_idx) {
2085 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2086 idx, max_valid_idx);
2091 case MLX5_IB_MMAP_WC_PAGE:
2092 case MLX5_IB_MMAP_ALLOC_WC:
2093 /* Some architectures don't support WC memory */
2094 #if defined(CONFIG_X86)
2097 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2101 case MLX5_IB_MMAP_REGULAR_PAGE:
2102 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2103 prot = pgprot_writecombine(vma->vm_page_prot);
2105 case MLX5_IB_MMAP_NC_PAGE:
2106 prot = pgprot_noncached(vma->vm_page_prot);
2115 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2116 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2117 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2118 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2119 bfreg_dyn_idx, bfregi->total_num_bfregs);
2123 mutex_lock(&bfregi->lock);
2124 /* Fail if uar already allocated, first bfreg index of each
2125 * page holds its count.
2127 if (bfregi->count[bfreg_dyn_idx]) {
2128 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2129 mutex_unlock(&bfregi->lock);
2133 bfregi->count[bfreg_dyn_idx]++;
2134 mutex_unlock(&bfregi->lock);
2136 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2138 mlx5_ib_warn(dev, "UAR alloc failed\n");
2142 uar_index = bfregi->sys_pages[idx];
2145 pfn = uar_index2pfn(dev, uar_index);
2146 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2148 vma->vm_page_prot = prot;
2149 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2150 PAGE_SIZE, vma->vm_page_prot);
2152 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2153 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
2158 pa = pfn << PAGE_SHIFT;
2159 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2160 vma->vm_start, &pa);
2162 err = mlx5_ib_set_vma_data(vma, context);
2167 bfregi->sys_pages[idx] = uar_index;
2174 mlx5_cmd_free_uar(dev->mdev, idx);
2177 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2182 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2184 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2185 struct mlx5_ib_dev *dev = to_mdev(context->device);
2186 u16 page_idx = get_extended_index(vma->vm_pgoff);
2187 size_t map_size = vma->vm_end - vma->vm_start;
2188 u32 npages = map_size >> PAGE_SHIFT;
2192 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2196 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2197 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2200 prot = pgprot_writecombine(vma->vm_page_prot);
2201 vma->vm_page_prot = prot;
2203 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2207 return mlx5_ib_set_vma_data(vma, mctx);
2210 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2212 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2213 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2214 unsigned long command;
2217 command = get_command(vma->vm_pgoff);
2219 case MLX5_IB_MMAP_WC_PAGE:
2220 case MLX5_IB_MMAP_NC_PAGE:
2221 case MLX5_IB_MMAP_REGULAR_PAGE:
2222 case MLX5_IB_MMAP_ALLOC_WC:
2223 return uar_mmap(dev, command, vma, context);
2225 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2228 case MLX5_IB_MMAP_CORE_CLOCK:
2229 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2232 if (vma->vm_flags & VM_WRITE)
2235 /* Don't expose to user-space information it shouldn't have */
2236 if (PAGE_SIZE > 4096)
2239 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2240 pfn = (dev->mdev->iseg_base +
2241 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2243 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2244 PAGE_SIZE, vma->vm_page_prot))
2247 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2249 (unsigned long long)pfn << PAGE_SHIFT);
2251 case MLX5_IB_MMAP_CLOCK_INFO:
2252 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2254 case MLX5_IB_MMAP_DEVICE_MEM:
2255 return dm_mmap(ibcontext, vma);
2264 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2265 struct ib_ucontext *context,
2266 struct ib_dm_alloc_attr *attr,
2267 struct uverbs_attr_bundle *attrs)
2269 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2270 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2271 phys_addr_t memic_addr;
2272 struct mlx5_ib_dm *dm;
2277 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2279 return ERR_PTR(-ENOMEM);
2281 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2282 attr->length, act_size, attr->alignment);
2284 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2285 act_size, attr->alignment);
2289 start_offset = memic_addr & ~PAGE_MASK;
2290 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2291 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2294 err = uverbs_copy_to(attrs,
2295 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2296 &start_offset, sizeof(start_offset));
2300 err = uverbs_copy_to(attrs,
2301 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2302 &page_idx, sizeof(page_idx));
2306 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2307 DIV_ROUND_UP(act_size, PAGE_SIZE));
2309 dm->dev_addr = memic_addr;
2314 mlx5_cmd_dealloc_memic(memic, memic_addr,
2318 return ERR_PTR(err);
2321 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2323 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2324 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2325 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2329 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2333 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2334 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2336 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2338 DIV_ROUND_UP(act_size, PAGE_SIZE));
2345 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2346 struct ib_ucontext *context,
2347 struct ib_udata *udata)
2349 struct mlx5_ib_alloc_pd_resp resp;
2350 struct mlx5_ib_pd *pd;
2353 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2355 return ERR_PTR(-ENOMEM);
2357 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2360 return ERR_PTR(err);
2365 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2366 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2368 return ERR_PTR(-EFAULT);
2375 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2377 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2378 struct mlx5_ib_pd *mpd = to_mpd(pd);
2380 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2387 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2388 MATCH_CRITERIA_ENABLE_MISC_BIT,
2389 MATCH_CRITERIA_ENABLE_INNER_BIT
2392 #define HEADER_IS_ZERO(match_criteria, headers) \
2393 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2394 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2396 static u8 get_match_criteria_enable(u32 *match_criteria)
2398 u8 match_criteria_enable;
2400 match_criteria_enable =
2401 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2402 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2403 match_criteria_enable |=
2404 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2405 MATCH_CRITERIA_ENABLE_MISC_BIT;
2406 match_criteria_enable |=
2407 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2408 MATCH_CRITERIA_ENABLE_INNER_BIT;
2410 return match_criteria_enable;
2413 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2415 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2416 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2419 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2423 MLX5_SET(fte_match_set_misc,
2424 misc_c, inner_ipv6_flow_label, mask);
2425 MLX5_SET(fte_match_set_misc,
2426 misc_v, inner_ipv6_flow_label, val);
2428 MLX5_SET(fte_match_set_misc,
2429 misc_c, outer_ipv6_flow_label, mask);
2430 MLX5_SET(fte_match_set_misc,
2431 misc_v, outer_ipv6_flow_label, val);
2435 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2437 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2438 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2439 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2440 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2443 #define LAST_ETH_FIELD vlan_tag
2444 #define LAST_IB_FIELD sl
2445 #define LAST_IPV4_FIELD tos
2446 #define LAST_IPV6_FIELD traffic_class
2447 #define LAST_TCP_UDP_FIELD src_port
2448 #define LAST_TUNNEL_FIELD tunnel_id
2449 #define LAST_FLOW_TAG_FIELD tag_id
2450 #define LAST_DROP_FIELD size
2452 /* Field is the last supported field */
2453 #define FIELDS_NOT_SUPPORTED(filter, field)\
2454 memchr_inv((void *)&filter.field +\
2455 sizeof(filter.field), 0,\
2457 offsetof(typeof(filter), field) -\
2458 sizeof(filter.field))
2460 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2461 const struct ib_flow_attr *flow_attr,
2462 struct mlx5_flow_act *action)
2464 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2466 switch (maction->ib_action.type) {
2467 case IB_FLOW_ACTION_ESP:
2468 /* Currently only AES_GCM keymat is supported by the driver */
2469 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2470 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2471 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2472 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2479 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2480 u32 *match_v, const union ib_flow_spec *ib_spec,
2481 const struct ib_flow_attr *flow_attr,
2482 struct mlx5_flow_act *action)
2484 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2486 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2493 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2494 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2496 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2498 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2499 ft_field_support.inner_ip_version);
2501 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2503 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2505 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2506 ft_field_support.outer_ip_version);
2509 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2510 case IB_FLOW_SPEC_ETH:
2511 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2514 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2516 ib_spec->eth.mask.dst_mac);
2517 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2519 ib_spec->eth.val.dst_mac);
2521 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2523 ib_spec->eth.mask.src_mac);
2524 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2526 ib_spec->eth.val.src_mac);
2528 if (ib_spec->eth.mask.vlan_tag) {
2529 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2531 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2534 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2535 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2536 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2537 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2539 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2541 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2542 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2544 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2546 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2548 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2549 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2551 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2553 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2554 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2555 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2556 ethertype, ntohs(ib_spec->eth.val.ether_type));
2558 case IB_FLOW_SPEC_IPV4:
2559 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2563 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2565 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2566 ip_version, MLX5_FS_IPV4_VERSION);
2568 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2570 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2571 ethertype, ETH_P_IP);
2574 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2575 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2576 &ib_spec->ipv4.mask.src_ip,
2577 sizeof(ib_spec->ipv4.mask.src_ip));
2578 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2579 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2580 &ib_spec->ipv4.val.src_ip,
2581 sizeof(ib_spec->ipv4.val.src_ip));
2582 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2583 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2584 &ib_spec->ipv4.mask.dst_ip,
2585 sizeof(ib_spec->ipv4.mask.dst_ip));
2586 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2587 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2588 &ib_spec->ipv4.val.dst_ip,
2589 sizeof(ib_spec->ipv4.val.dst_ip));
2591 set_tos(headers_c, headers_v,
2592 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2594 set_proto(headers_c, headers_v,
2595 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2597 case IB_FLOW_SPEC_IPV6:
2598 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2602 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2604 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2605 ip_version, MLX5_FS_IPV6_VERSION);
2607 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2609 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2610 ethertype, ETH_P_IPV6);
2613 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2614 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2615 &ib_spec->ipv6.mask.src_ip,
2616 sizeof(ib_spec->ipv6.mask.src_ip));
2617 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2618 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2619 &ib_spec->ipv6.val.src_ip,
2620 sizeof(ib_spec->ipv6.val.src_ip));
2621 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2622 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2623 &ib_spec->ipv6.mask.dst_ip,
2624 sizeof(ib_spec->ipv6.mask.dst_ip));
2625 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2626 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2627 &ib_spec->ipv6.val.dst_ip,
2628 sizeof(ib_spec->ipv6.val.dst_ip));
2630 set_tos(headers_c, headers_v,
2631 ib_spec->ipv6.mask.traffic_class,
2632 ib_spec->ipv6.val.traffic_class);
2634 set_proto(headers_c, headers_v,
2635 ib_spec->ipv6.mask.next_hdr,
2636 ib_spec->ipv6.val.next_hdr);
2638 set_flow_label(misc_params_c, misc_params_v,
2639 ntohl(ib_spec->ipv6.mask.flow_label),
2640 ntohl(ib_spec->ipv6.val.flow_label),
2641 ib_spec->type & IB_FLOW_SPEC_INNER);
2643 case IB_FLOW_SPEC_ESP:
2644 if (ib_spec->esp.mask.seq)
2647 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2648 ntohl(ib_spec->esp.mask.spi));
2649 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2650 ntohl(ib_spec->esp.val.spi));
2652 case IB_FLOW_SPEC_TCP:
2653 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2654 LAST_TCP_UDP_FIELD))
2657 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2659 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2662 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2663 ntohs(ib_spec->tcp_udp.mask.src_port));
2664 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2665 ntohs(ib_spec->tcp_udp.val.src_port));
2667 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2668 ntohs(ib_spec->tcp_udp.mask.dst_port));
2669 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2670 ntohs(ib_spec->tcp_udp.val.dst_port));
2672 case IB_FLOW_SPEC_UDP:
2673 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2674 LAST_TCP_UDP_FIELD))
2677 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2679 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2682 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2683 ntohs(ib_spec->tcp_udp.mask.src_port));
2684 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2685 ntohs(ib_spec->tcp_udp.val.src_port));
2687 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2688 ntohs(ib_spec->tcp_udp.mask.dst_port));
2689 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2690 ntohs(ib_spec->tcp_udp.val.dst_port));
2692 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2693 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2697 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2698 ntohl(ib_spec->tunnel.mask.tunnel_id));
2699 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2700 ntohl(ib_spec->tunnel.val.tunnel_id));
2702 case IB_FLOW_SPEC_ACTION_TAG:
2703 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2704 LAST_FLOW_TAG_FIELD))
2706 if (ib_spec->flow_tag.tag_id >= BIT(24))
2709 action->flow_tag = ib_spec->flow_tag.tag_id;
2710 action->has_flow_tag = true;
2712 case IB_FLOW_SPEC_ACTION_DROP:
2713 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2716 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2718 case IB_FLOW_SPEC_ACTION_HANDLE:
2719 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2730 /* If a flow could catch both multicast and unicast packets,
2731 * it won't fall into the multicast flow steering table and this rule
2732 * could steal other multicast packets.
2734 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2736 union ib_flow_spec *flow_spec;
2738 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2739 ib_attr->num_of_specs < 1)
2742 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2743 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2744 struct ib_flow_spec_ipv4 *ipv4_spec;
2746 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2747 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2753 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2754 struct ib_flow_spec_eth *eth_spec;
2756 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2757 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2758 is_multicast_ether_addr(eth_spec->val.dst_mac);
2770 static enum valid_spec
2771 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2772 const struct mlx5_flow_spec *spec,
2773 const struct mlx5_flow_act *flow_act,
2776 const u32 *match_c = spec->match_criteria;
2778 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2779 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2780 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2781 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2784 * Currently only crypto is supported in egress, when regular egress
2785 * rules would be supported, always return VALID_SPEC_NA.
2788 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2790 return is_crypto && is_ipsec &&
2791 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2792 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2795 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2796 const struct mlx5_flow_spec *spec,
2797 const struct mlx5_flow_act *flow_act,
2800 /* We curretly only support ipsec egress flow */
2801 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2804 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2805 const struct ib_flow_attr *flow_attr,
2808 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2809 int match_ipv = check_inner ?
2810 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2811 ft_field_support.inner_ip_version) :
2812 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2813 ft_field_support.outer_ip_version);
2814 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2815 bool ipv4_spec_valid, ipv6_spec_valid;
2816 unsigned int ip_spec_type = 0;
2817 bool has_ethertype = false;
2818 unsigned int spec_index;
2819 bool mask_valid = true;
2823 /* Validate that ethertype is correct */
2824 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2825 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2826 ib_spec->eth.mask.ether_type) {
2827 mask_valid = (ib_spec->eth.mask.ether_type ==
2829 has_ethertype = true;
2830 eth_type = ntohs(ib_spec->eth.val.ether_type);
2831 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2832 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2833 ip_spec_type = ib_spec->type;
2835 ib_spec = (void *)ib_spec + ib_spec->size;
2838 type_valid = (!has_ethertype) || (!ip_spec_type);
2839 if (!type_valid && mask_valid) {
2840 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2841 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2842 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2843 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2845 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2846 (((eth_type == ETH_P_MPLS_UC) ||
2847 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2853 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2854 const struct ib_flow_attr *flow_attr)
2856 return is_valid_ethertype(mdev, flow_attr, false) &&
2857 is_valid_ethertype(mdev, flow_attr, true);
2860 static void put_flow_table(struct mlx5_ib_dev *dev,
2861 struct mlx5_ib_flow_prio *prio, bool ft_added)
2863 prio->refcount -= !!ft_added;
2864 if (!prio->refcount) {
2865 mlx5_destroy_flow_table(prio->flow_table);
2866 prio->flow_table = NULL;
2870 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2872 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2873 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2874 struct mlx5_ib_flow_handler,
2876 struct mlx5_ib_flow_handler *iter, *tmp;
2878 mutex_lock(&dev->flow_db->lock);
2880 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2881 mlx5_del_flow_rules(iter->rule);
2882 put_flow_table(dev, iter->prio, true);
2883 list_del(&iter->list);
2887 mlx5_del_flow_rules(handler->rule);
2888 put_flow_table(dev, handler->prio, true);
2889 mutex_unlock(&dev->flow_db->lock);
2896 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2904 enum flow_table_type {
2909 #define MLX5_FS_MAX_TYPES 6
2910 #define MLX5_FS_MAX_ENTRIES BIT(16)
2911 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2912 struct ib_flow_attr *flow_attr,
2913 enum flow_table_type ft_type)
2915 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2916 struct mlx5_flow_namespace *ns = NULL;
2917 struct mlx5_ib_flow_prio *prio;
2918 struct mlx5_flow_table *ft;
2925 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2927 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2928 if (ft_type == MLX5_IB_FT_TX)
2930 else if (flow_is_multicast_only(flow_attr) &&
2932 priority = MLX5_IB_FLOW_MCAST_PRIO;
2934 priority = ib_prio_to_core_prio(flow_attr->priority,
2936 ns = mlx5_get_flow_namespace(dev->mdev,
2937 ft_type == MLX5_IB_FT_TX ?
2938 MLX5_FLOW_NAMESPACE_EGRESS :
2939 MLX5_FLOW_NAMESPACE_BYPASS);
2940 num_entries = MLX5_FS_MAX_ENTRIES;
2941 num_groups = MLX5_FS_MAX_TYPES;
2942 prio = &dev->flow_db->prios[priority];
2943 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2944 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2945 ns = mlx5_get_flow_namespace(dev->mdev,
2946 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2947 build_leftovers_ft_param(&priority,
2950 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2951 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2952 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2953 allow_sniffer_and_nic_rx_shared_tir))
2954 return ERR_PTR(-ENOTSUPP);
2956 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2957 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2958 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2960 prio = &dev->flow_db->sniffer[ft_type];
2967 return ERR_PTR(-ENOTSUPP);
2969 if (num_entries > max_table_size)
2970 return ERR_PTR(-ENOMEM);
2972 ft = prio->flow_table;
2974 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2981 prio->flow_table = ft;
2987 return err ? ERR_PTR(err) : prio;
2990 static void set_underlay_qp(struct mlx5_ib_dev *dev,
2991 struct mlx5_flow_spec *spec,
2994 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2995 spec->match_criteria,
2997 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3001 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3002 ft_field_support.bth_dst_qp)) {
3003 MLX5_SET(fte_match_set_misc,
3004 misc_params_v, bth_dst_qp, underlay_qpn);
3005 MLX5_SET(fte_match_set_misc,
3006 misc_params_c, bth_dst_qp, 0xffffff);
3010 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3011 struct mlx5_ib_flow_prio *ft_prio,
3012 const struct ib_flow_attr *flow_attr,
3013 struct mlx5_flow_destination *dst,
3016 struct mlx5_flow_table *ft = ft_prio->flow_table;
3017 struct mlx5_ib_flow_handler *handler;
3018 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3019 struct mlx5_flow_spec *spec;
3020 struct mlx5_flow_destination *rule_dst = dst;
3021 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3022 unsigned int spec_index;
3025 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3027 if (!is_valid_attr(dev->mdev, flow_attr))
3028 return ERR_PTR(-EINVAL);
3030 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3031 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3032 if (!handler || !spec) {
3037 INIT_LIST_HEAD(&handler->list);
3039 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3040 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3042 ib_flow, flow_attr, &flow_act);
3046 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3049 if (!flow_is_multicast_only(flow_attr))
3050 set_underlay_qp(dev, spec, underlay_qpn);
3055 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3057 MLX5_SET(fte_match_set_misc, misc, source_port,
3059 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3061 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3064 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3067 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3072 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3077 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3080 dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3081 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3084 if (flow_act.has_flow_tag &&
3085 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3086 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3087 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3088 flow_act.flow_tag, flow_attr->type);
3092 handler->rule = mlx5_add_flow_rules(ft, spec,
3094 rule_dst, dest_num);
3096 if (IS_ERR(handler->rule)) {
3097 err = PTR_ERR(handler->rule);
3101 ft_prio->refcount++;
3102 handler->prio = ft_prio;
3104 ft_prio->flow_table = ft;
3109 return err ? ERR_PTR(err) : handler;
3112 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3113 struct mlx5_ib_flow_prio *ft_prio,
3114 const struct ib_flow_attr *flow_attr,
3115 struct mlx5_flow_destination *dst)
3117 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
3120 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3121 struct mlx5_ib_flow_prio *ft_prio,
3122 struct ib_flow_attr *flow_attr,
3123 struct mlx5_flow_destination *dst)
3125 struct mlx5_ib_flow_handler *handler_dst = NULL;
3126 struct mlx5_ib_flow_handler *handler = NULL;
3128 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3129 if (!IS_ERR(handler)) {
3130 handler_dst = create_flow_rule(dev, ft_prio,
3132 if (IS_ERR(handler_dst)) {
3133 mlx5_del_flow_rules(handler->rule);
3134 ft_prio->refcount--;
3136 handler = handler_dst;
3138 list_add(&handler_dst->list, &handler->list);
3149 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3150 struct mlx5_ib_flow_prio *ft_prio,
3151 struct ib_flow_attr *flow_attr,
3152 struct mlx5_flow_destination *dst)
3154 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3155 struct mlx5_ib_flow_handler *handler = NULL;
3158 struct ib_flow_attr flow_attr;
3159 struct ib_flow_spec_eth eth_flow;
3160 } leftovers_specs[] = {
3164 .size = sizeof(leftovers_specs[0])
3167 .type = IB_FLOW_SPEC_ETH,
3168 .size = sizeof(struct ib_flow_spec_eth),
3169 .mask = {.dst_mac = {0x1} },
3170 .val = {.dst_mac = {0x1} }
3176 .size = sizeof(leftovers_specs[0])
3179 .type = IB_FLOW_SPEC_ETH,
3180 .size = sizeof(struct ib_flow_spec_eth),
3181 .mask = {.dst_mac = {0x1} },
3182 .val = {.dst_mac = {} }
3187 handler = create_flow_rule(dev, ft_prio,
3188 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3190 if (!IS_ERR(handler) &&
3191 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3192 handler_ucast = create_flow_rule(dev, ft_prio,
3193 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3195 if (IS_ERR(handler_ucast)) {
3196 mlx5_del_flow_rules(handler->rule);
3197 ft_prio->refcount--;
3199 handler = handler_ucast;
3201 list_add(&handler_ucast->list, &handler->list);
3208 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3209 struct mlx5_ib_flow_prio *ft_rx,
3210 struct mlx5_ib_flow_prio *ft_tx,
3211 struct mlx5_flow_destination *dst)
3213 struct mlx5_ib_flow_handler *handler_rx;
3214 struct mlx5_ib_flow_handler *handler_tx;
3216 static const struct ib_flow_attr flow_attr = {
3218 .size = sizeof(flow_attr)
3221 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3222 if (IS_ERR(handler_rx)) {
3223 err = PTR_ERR(handler_rx);
3227 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3228 if (IS_ERR(handler_tx)) {
3229 err = PTR_ERR(handler_tx);
3233 list_add(&handler_tx->list, &handler_rx->list);
3238 mlx5_del_flow_rules(handler_rx->rule);
3242 return ERR_PTR(err);
3245 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3246 struct ib_flow_attr *flow_attr,
3249 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3250 struct mlx5_ib_qp *mqp = to_mqp(qp);
3251 struct mlx5_ib_flow_handler *handler = NULL;
3252 struct mlx5_flow_destination *dst = NULL;
3253 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3254 struct mlx5_ib_flow_prio *ft_prio;
3255 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3259 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
3260 return ERR_PTR(-ENOMEM);
3262 if (domain != IB_FLOW_DOMAIN_USER ||
3263 flow_attr->port > dev->num_ports ||
3264 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3265 IB_FLOW_ATTR_FLAGS_EGRESS)))
3266 return ERR_PTR(-EINVAL);
3269 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3270 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
3271 return ERR_PTR(-EINVAL);
3273 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3275 return ERR_PTR(-ENOMEM);
3277 mutex_lock(&dev->flow_db->lock);
3279 ft_prio = get_flow_table(dev, flow_attr,
3280 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3281 if (IS_ERR(ft_prio)) {
3282 err = PTR_ERR(ft_prio);
3285 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3286 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3287 if (IS_ERR(ft_prio_tx)) {
3288 err = PTR_ERR(ft_prio_tx);
3295 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3297 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3298 if (mqp->flags & MLX5_IB_QP_RSS)
3299 dst->tir_num = mqp->rss_qp.tirn;
3301 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3304 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3305 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3306 handler = create_dont_trap_rule(dev, ft_prio,
3309 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3310 mqp->underlay_qpn : 0;
3311 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3314 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3315 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3316 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3318 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3319 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3325 if (IS_ERR(handler)) {
3326 err = PTR_ERR(handler);
3331 mutex_unlock(&dev->flow_db->lock);
3334 return &handler->ibflow;
3337 put_flow_table(dev, ft_prio, false);
3339 put_flow_table(dev, ft_prio_tx, false);
3341 mutex_unlock(&dev->flow_db->lock);
3344 return ERR_PTR(err);
3347 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3351 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3352 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3357 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3358 static struct ib_flow_action *
3359 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3360 const struct ib_flow_action_attrs_esp *attr,
3361 struct uverbs_attr_bundle *attrs)
3363 struct mlx5_ib_dev *mdev = to_mdev(device);
3364 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3365 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3366 struct mlx5_ib_flow_action *action;
3371 if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3372 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3373 return ERR_PTR(-EFAULT);
3375 if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3376 return ERR_PTR(-EOPNOTSUPP);
3378 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3380 /* We current only support a subset of the standard features. Only a
3381 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3382 * (with overlap). Full offload mode isn't supported.
3384 if (!attr->keymat || attr->replay || attr->encap ||
3385 attr->spi || attr->seq || attr->tfc_pad ||
3386 attr->hard_limit_pkts ||
3387 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3388 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3389 return ERR_PTR(-EOPNOTSUPP);
3391 if (attr->keymat->protocol !=
3392 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3393 return ERR_PTR(-EOPNOTSUPP);
3395 aes_gcm = &attr->keymat->keymat.aes_gcm;
3397 if (aes_gcm->icv_len != 16 ||
3398 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3399 return ERR_PTR(-EOPNOTSUPP);
3401 action = kmalloc(sizeof(*action), GFP_KERNEL);
3403 return ERR_PTR(-ENOMEM);
3405 action->esp_aes_gcm.ib_flags = attr->flags;
3406 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3407 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3408 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3409 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3410 sizeof(accel_attrs.keymat.aes_gcm.salt));
3411 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3412 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3413 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3414 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3415 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3417 accel_attrs.esn = attr->esn;
3418 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3419 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3420 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3421 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3423 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3424 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3426 action->esp_aes_gcm.ctx =
3427 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3428 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3429 err = PTR_ERR(action->esp_aes_gcm.ctx);
3433 action->esp_aes_gcm.ib_flags = attr->flags;
3435 return &action->ib_action;
3439 return ERR_PTR(err);
3443 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3444 const struct ib_flow_action_attrs_esp *attr,
3445 struct uverbs_attr_bundle *attrs)
3447 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3448 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3451 if (attr->keymat || attr->replay || attr->encap ||
3452 attr->spi || attr->seq || attr->tfc_pad ||
3453 attr->hard_limit_pkts ||
3454 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3455 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3456 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3459 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3462 if (!(maction->esp_aes_gcm.ib_flags &
3463 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3464 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3465 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3468 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3469 sizeof(accel_attrs));
3471 accel_attrs.esn = attr->esn;
3472 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3473 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3475 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3477 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3482 maction->esp_aes_gcm.ib_flags &=
3483 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3484 maction->esp_aes_gcm.ib_flags |=
3485 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3490 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3492 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3494 switch (action->type) {
3495 case IB_FLOW_ACTION_ESP:
3497 * We only support aes_gcm by now, so we implicitly know this is
3498 * the underline crypto.
3500 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3511 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3513 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3514 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
3517 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3518 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3522 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
3524 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3525 ibqp->qp_num, gid->raw);
3530 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3532 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3535 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
3537 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3538 ibqp->qp_num, gid->raw);
3543 static int init_node_data(struct mlx5_ib_dev *dev)
3547 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
3551 dev->mdev->rev_id = dev->mdev->pdev->revision;
3553 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
3556 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3559 struct mlx5_ib_dev *dev =
3560 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3562 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
3565 static ssize_t show_reg_pages(struct device *device,
3566 struct device_attribute *attr, char *buf)
3568 struct mlx5_ib_dev *dev =
3569 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3571 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
3574 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3577 struct mlx5_ib_dev *dev =
3578 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3579 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
3582 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3585 struct mlx5_ib_dev *dev =
3586 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3587 return sprintf(buf, "%x\n", dev->mdev->rev_id);
3590 static ssize_t show_board(struct device *device, struct device_attribute *attr,
3593 struct mlx5_ib_dev *dev =
3594 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3595 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
3596 dev->mdev->board_id);
3599 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
3600 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3601 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3602 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3603 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3605 static struct device_attribute *mlx5_class_attributes[] = {
3610 &dev_attr_reg_pages,
3613 static void pkey_change_handler(struct work_struct *work)
3615 struct mlx5_ib_port_resources *ports =
3616 container_of(work, struct mlx5_ib_port_resources,
3619 mutex_lock(&ports->devr->mutex);
3620 mlx5_ib_gsi_pkey_change(ports->gsi);
3621 mutex_unlock(&ports->devr->mutex);
3624 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3626 struct mlx5_ib_qp *mqp;
3627 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3628 struct mlx5_core_cq *mcq;
3629 struct list_head cq_armed_list;
3630 unsigned long flags_qp;
3631 unsigned long flags_cq;
3632 unsigned long flags;
3634 INIT_LIST_HEAD(&cq_armed_list);
3636 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3637 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3638 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3639 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3640 if (mqp->sq.tail != mqp->sq.head) {
3641 send_mcq = to_mcq(mqp->ibqp.send_cq);
3642 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3643 if (send_mcq->mcq.comp &&
3644 mqp->ibqp.send_cq->comp_handler) {
3645 if (!send_mcq->mcq.reset_notify_added) {
3646 send_mcq->mcq.reset_notify_added = 1;
3647 list_add_tail(&send_mcq->mcq.reset_notify,
3651 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3653 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3654 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3655 /* no handling is needed for SRQ */
3656 if (!mqp->ibqp.srq) {
3657 if (mqp->rq.tail != mqp->rq.head) {
3658 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3659 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3660 if (recv_mcq->mcq.comp &&
3661 mqp->ibqp.recv_cq->comp_handler) {
3662 if (!recv_mcq->mcq.reset_notify_added) {
3663 recv_mcq->mcq.reset_notify_added = 1;
3664 list_add_tail(&recv_mcq->mcq.reset_notify,
3668 spin_unlock_irqrestore(&recv_mcq->lock,
3672 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3674 /*At that point all inflight post send were put to be executed as of we
3675 * lock/unlock above locks Now need to arm all involved CQs.
3677 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3680 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3683 static void delay_drop_handler(struct work_struct *work)
3686 struct mlx5_ib_delay_drop *delay_drop =
3687 container_of(work, struct mlx5_ib_delay_drop,
3690 atomic_inc(&delay_drop->events_cnt);
3692 mutex_lock(&delay_drop->lock);
3693 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3694 delay_drop->timeout);
3696 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3697 delay_drop->timeout);
3698 delay_drop->activate = false;
3700 mutex_unlock(&delay_drop->lock);
3703 static void mlx5_ib_handle_event(struct work_struct *_work)
3705 struct mlx5_ib_event_work *work =
3706 container_of(_work, struct mlx5_ib_event_work, work);
3707 struct mlx5_ib_dev *ibdev;
3708 struct ib_event ibev;
3710 u8 port = (u8)work->param;
3712 if (mlx5_core_is_mp_slave(work->dev)) {
3713 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3717 ibdev = work->context;
3720 switch (work->event) {
3721 case MLX5_DEV_EVENT_SYS_ERROR:
3722 ibev.event = IB_EVENT_DEVICE_FATAL;
3723 mlx5_ib_handle_internal_error(ibdev);
3727 case MLX5_DEV_EVENT_PORT_UP:
3728 case MLX5_DEV_EVENT_PORT_DOWN:
3729 case MLX5_DEV_EVENT_PORT_INITIALIZED:
3730 /* In RoCE, port up/down events are handled in
3731 * mlx5_netdev_event().
3733 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3734 IB_LINK_LAYER_ETHERNET)
3737 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
3738 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3741 case MLX5_DEV_EVENT_LID_CHANGE:
3742 ibev.event = IB_EVENT_LID_CHANGE;
3745 case MLX5_DEV_EVENT_PKEY_CHANGE:
3746 ibev.event = IB_EVENT_PKEY_CHANGE;
3747 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
3750 case MLX5_DEV_EVENT_GUID_CHANGE:
3751 ibev.event = IB_EVENT_GID_CHANGE;
3754 case MLX5_DEV_EVENT_CLIENT_REREG:
3755 ibev.event = IB_EVENT_CLIENT_REREGISTER;
3757 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3758 schedule_work(&ibdev->delay_drop.delay_drop_work);
3764 ibev.device = &ibdev->ib_dev;
3765 ibev.element.port_num = port;
3767 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
3768 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
3772 if (ibdev->ib_active)
3773 ib_dispatch_event(&ibev);
3776 ibdev->ib_active = false;
3781 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3782 enum mlx5_dev_event event, unsigned long param)
3784 struct mlx5_ib_event_work *work;
3786 work = kmalloc(sizeof(*work), GFP_ATOMIC);
3790 INIT_WORK(&work->work, mlx5_ib_handle_event);
3792 work->param = param;
3793 work->context = context;
3794 work->event = event;
3796 queue_work(mlx5_ib_event_wq, &work->work);
3799 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3801 struct mlx5_hca_vport_context vport_ctx;
3805 for (port = 1; port <= dev->num_ports; port++) {
3806 dev->mdev->port_caps[port - 1].has_smi = false;
3807 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3808 MLX5_CAP_PORT_TYPE_IB) {
3809 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3810 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3814 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3818 dev->mdev->port_caps[port - 1].has_smi =
3821 dev->mdev->port_caps[port - 1].has_smi = true;
3828 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3832 for (port = 1; port <= dev->num_ports; port++)
3833 mlx5_query_ext_port_caps(dev, port);
3836 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
3838 struct ib_device_attr *dprops = NULL;
3839 struct ib_port_attr *pprops = NULL;
3841 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
3843 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3847 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3851 err = set_has_smi_cap(dev);
3855 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3857 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3861 memset(pprops, 0, sizeof(*pprops));
3862 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3864 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3869 dev->mdev->port_caps[port - 1].pkey_table_len =
3871 dev->mdev->port_caps[port - 1].gid_table_len =
3872 pprops->gid_tbl_len;
3873 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3874 port, dprops->max_pkeys, pprops->gid_tbl_len);
3883 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3887 err = mlx5_mr_cache_cleanup(dev);
3889 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3892 mlx5_ib_destroy_qp(dev->umrc.qp);
3894 ib_free_cq(dev->umrc.cq);
3896 ib_dealloc_pd(dev->umrc.pd);
3903 static int create_umr_res(struct mlx5_ib_dev *dev)
3905 struct ib_qp_init_attr *init_attr = NULL;
3906 struct ib_qp_attr *attr = NULL;
3912 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3913 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3914 if (!attr || !init_attr) {
3919 pd = ib_alloc_pd(&dev->ib_dev, 0);
3921 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3926 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3928 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3933 init_attr->send_cq = cq;
3934 init_attr->recv_cq = cq;
3935 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3936 init_attr->cap.max_send_wr = MAX_UMR_WR;
3937 init_attr->cap.max_send_sge = 1;
3938 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3939 init_attr->port_num = 1;
3940 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3942 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3946 qp->device = &dev->ib_dev;
3949 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3950 qp->send_cq = init_attr->send_cq;
3951 qp->recv_cq = init_attr->recv_cq;
3953 attr->qp_state = IB_QPS_INIT;
3955 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3958 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3962 memset(attr, 0, sizeof(*attr));
3963 attr->qp_state = IB_QPS_RTR;
3964 attr->path_mtu = IB_MTU_256;
3966 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3968 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3972 memset(attr, 0, sizeof(*attr));
3973 attr->qp_state = IB_QPS_RTS;
3974 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3976 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3984 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3985 ret = mlx5_mr_cache_init(dev);
3987 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3997 mlx5_ib_destroy_qp(qp);
3998 dev->umrc.qp = NULL;
4002 dev->umrc.cq = NULL;
4006 dev->umrc.pd = NULL;
4014 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4016 switch (umr_fence_cap) {
4017 case MLX5_CAP_UMR_FENCE_NONE:
4018 return MLX5_FENCE_MODE_NONE;
4019 case MLX5_CAP_UMR_FENCE_SMALL:
4020 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4022 return MLX5_FENCE_MODE_STRONG_ORDERING;
4026 static int create_dev_resources(struct mlx5_ib_resources *devr)
4028 struct ib_srq_init_attr attr;
4029 struct mlx5_ib_dev *dev;
4030 struct ib_cq_init_attr cq_attr = {.cqe = 1};
4034 dev = container_of(devr, struct mlx5_ib_dev, devr);
4036 mutex_init(&devr->mutex);
4038 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4039 if (IS_ERR(devr->p0)) {
4040 ret = PTR_ERR(devr->p0);
4043 devr->p0->device = &dev->ib_dev;
4044 devr->p0->uobject = NULL;
4045 atomic_set(&devr->p0->usecnt, 0);
4047 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4048 if (IS_ERR(devr->c0)) {
4049 ret = PTR_ERR(devr->c0);
4052 devr->c0->device = &dev->ib_dev;
4053 devr->c0->uobject = NULL;
4054 devr->c0->comp_handler = NULL;
4055 devr->c0->event_handler = NULL;
4056 devr->c0->cq_context = NULL;
4057 atomic_set(&devr->c0->usecnt, 0);
4059 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4060 if (IS_ERR(devr->x0)) {
4061 ret = PTR_ERR(devr->x0);
4064 devr->x0->device = &dev->ib_dev;
4065 devr->x0->inode = NULL;
4066 atomic_set(&devr->x0->usecnt, 0);
4067 mutex_init(&devr->x0->tgt_qp_mutex);
4068 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4070 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4071 if (IS_ERR(devr->x1)) {
4072 ret = PTR_ERR(devr->x1);
4075 devr->x1->device = &dev->ib_dev;
4076 devr->x1->inode = NULL;
4077 atomic_set(&devr->x1->usecnt, 0);
4078 mutex_init(&devr->x1->tgt_qp_mutex);
4079 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4081 memset(&attr, 0, sizeof(attr));
4082 attr.attr.max_sge = 1;
4083 attr.attr.max_wr = 1;
4084 attr.srq_type = IB_SRQT_XRC;
4085 attr.ext.cq = devr->c0;
4086 attr.ext.xrc.xrcd = devr->x0;
4088 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4089 if (IS_ERR(devr->s0)) {
4090 ret = PTR_ERR(devr->s0);
4093 devr->s0->device = &dev->ib_dev;
4094 devr->s0->pd = devr->p0;
4095 devr->s0->uobject = NULL;
4096 devr->s0->event_handler = NULL;
4097 devr->s0->srq_context = NULL;
4098 devr->s0->srq_type = IB_SRQT_XRC;
4099 devr->s0->ext.xrc.xrcd = devr->x0;
4100 devr->s0->ext.cq = devr->c0;
4101 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4102 atomic_inc(&devr->s0->ext.cq->usecnt);
4103 atomic_inc(&devr->p0->usecnt);
4104 atomic_set(&devr->s0->usecnt, 0);
4106 memset(&attr, 0, sizeof(attr));
4107 attr.attr.max_sge = 1;
4108 attr.attr.max_wr = 1;
4109 attr.srq_type = IB_SRQT_BASIC;
4110 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4111 if (IS_ERR(devr->s1)) {
4112 ret = PTR_ERR(devr->s1);
4115 devr->s1->device = &dev->ib_dev;
4116 devr->s1->pd = devr->p0;
4117 devr->s1->uobject = NULL;
4118 devr->s1->event_handler = NULL;
4119 devr->s1->srq_context = NULL;
4120 devr->s1->srq_type = IB_SRQT_BASIC;
4121 devr->s1->ext.cq = devr->c0;
4122 atomic_inc(&devr->p0->usecnt);
4123 atomic_set(&devr->s1->usecnt, 0);
4125 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4126 INIT_WORK(&devr->ports[port].pkey_change_work,
4127 pkey_change_handler);
4128 devr->ports[port].devr = devr;
4134 mlx5_ib_destroy_srq(devr->s0);
4136 mlx5_ib_dealloc_xrcd(devr->x1);
4138 mlx5_ib_dealloc_xrcd(devr->x0);
4140 mlx5_ib_destroy_cq(devr->c0);
4142 mlx5_ib_dealloc_pd(devr->p0);
4147 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4149 struct mlx5_ib_dev *dev =
4150 container_of(devr, struct mlx5_ib_dev, devr);
4153 mlx5_ib_destroy_srq(devr->s1);
4154 mlx5_ib_destroy_srq(devr->s0);
4155 mlx5_ib_dealloc_xrcd(devr->x0);
4156 mlx5_ib_dealloc_xrcd(devr->x1);
4157 mlx5_ib_destroy_cq(devr->c0);
4158 mlx5_ib_dealloc_pd(devr->p0);
4160 /* Make sure no change P_Key work items are still executing */
4161 for (port = 0; port < dev->num_ports; ++port)
4162 cancel_work_sync(&devr->ports[port].pkey_change_work);
4165 static u32 get_core_cap_flags(struct ib_device *ibdev)
4167 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4168 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4169 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4170 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4171 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4174 if (ll == IB_LINK_LAYER_INFINIBAND)
4175 return RDMA_CORE_PORT_IBA_IB;
4178 ret = RDMA_CORE_PORT_RAW_PACKET;
4180 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4183 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4186 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4187 ret |= RDMA_CORE_PORT_IBA_ROCE;
4189 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4190 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4195 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4196 struct ib_port_immutable *immutable)
4198 struct ib_port_attr attr;
4199 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4200 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4203 immutable->core_cap_flags = get_core_cap_flags(ibdev);
4205 err = ib_query_port(ibdev, port_num, &attr);
4209 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4210 immutable->gid_tbl_len = attr.gid_tbl_len;
4211 immutable->core_cap_flags = get_core_cap_flags(ibdev);
4212 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4213 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4218 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4219 struct ib_port_immutable *immutable)
4221 struct ib_port_attr attr;
4224 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4226 err = ib_query_port(ibdev, port_num, &attr);
4230 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4231 immutable->gid_tbl_len = attr.gid_tbl_len;
4232 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4237 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4239 struct mlx5_ib_dev *dev =
4240 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4241 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4242 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4243 fw_rev_sub(dev->mdev));
4246 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4248 struct mlx5_core_dev *mdev = dev->mdev;
4249 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4250 MLX5_FLOW_NAMESPACE_LAG);
4251 struct mlx5_flow_table *ft;
4254 if (!ns || !mlx5_lag_is_active(mdev))
4257 err = mlx5_cmd_create_vport_lag(mdev);
4261 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4264 goto err_destroy_vport_lag;
4267 dev->flow_db->lag_demux_ft = ft;
4270 err_destroy_vport_lag:
4271 mlx5_cmd_destroy_vport_lag(mdev);
4275 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4277 struct mlx5_core_dev *mdev = dev->mdev;
4279 if (dev->flow_db->lag_demux_ft) {
4280 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4281 dev->flow_db->lag_demux_ft = NULL;
4283 mlx5_cmd_destroy_vport_lag(mdev);
4287 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4291 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4292 err = register_netdevice_notifier(&dev->roce[port_num].nb);
4294 dev->roce[port_num].nb.notifier_call = NULL;
4301 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4303 if (dev->roce[port_num].nb.notifier_call) {
4304 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4305 dev->roce[port_num].nb.notifier_call = NULL;
4309 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
4313 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4314 err = mlx5_nic_vport_enable_roce(dev->mdev);
4319 err = mlx5_eth_lag_init(dev);
4321 goto err_disable_roce;
4326 if (MLX5_CAP_GEN(dev->mdev, roce))
4327 mlx5_nic_vport_disable_roce(dev->mdev);
4332 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4334 mlx5_eth_lag_cleanup(dev);
4335 if (MLX5_CAP_GEN(dev->mdev, roce))
4336 mlx5_nic_vport_disable_roce(dev->mdev);
4339 struct mlx5_ib_counter {
4344 #define INIT_Q_COUNTER(_name) \
4345 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4347 static const struct mlx5_ib_counter basic_q_cnts[] = {
4348 INIT_Q_COUNTER(rx_write_requests),
4349 INIT_Q_COUNTER(rx_read_requests),
4350 INIT_Q_COUNTER(rx_atomic_requests),
4351 INIT_Q_COUNTER(out_of_buffer),
4354 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4355 INIT_Q_COUNTER(out_of_sequence),
4358 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4359 INIT_Q_COUNTER(duplicate_request),
4360 INIT_Q_COUNTER(rnr_nak_retry_err),
4361 INIT_Q_COUNTER(packet_seq_err),
4362 INIT_Q_COUNTER(implied_nak_seq_err),
4363 INIT_Q_COUNTER(local_ack_timeout_err),
4366 #define INIT_CONG_COUNTER(_name) \
4367 { .name = #_name, .offset = \
4368 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4370 static const struct mlx5_ib_counter cong_cnts[] = {
4371 INIT_CONG_COUNTER(rp_cnp_ignored),
4372 INIT_CONG_COUNTER(rp_cnp_handled),
4373 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4374 INIT_CONG_COUNTER(np_cnp_sent),
4377 static const struct mlx5_ib_counter extended_err_cnts[] = {
4378 INIT_Q_COUNTER(resp_local_length_error),
4379 INIT_Q_COUNTER(resp_cqe_error),
4380 INIT_Q_COUNTER(req_cqe_error),
4381 INIT_Q_COUNTER(req_remote_invalid_request),
4382 INIT_Q_COUNTER(req_remote_access_errors),
4383 INIT_Q_COUNTER(resp_remote_access_errors),
4384 INIT_Q_COUNTER(resp_cqe_flush_error),
4385 INIT_Q_COUNTER(req_cqe_flush_error),
4388 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4392 for (i = 0; i < dev->num_ports; i++) {
4393 if (dev->port[i].cnts.set_id)
4394 mlx5_core_dealloc_q_counter(dev->mdev,
4395 dev->port[i].cnts.set_id);
4396 kfree(dev->port[i].cnts.names);
4397 kfree(dev->port[i].cnts.offsets);
4401 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4402 struct mlx5_ib_counters *cnts)
4406 num_counters = ARRAY_SIZE(basic_q_cnts);
4408 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4409 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4411 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4412 num_counters += ARRAY_SIZE(retrans_q_cnts);
4414 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4415 num_counters += ARRAY_SIZE(extended_err_cnts);
4417 cnts->num_q_counters = num_counters;
4419 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4420 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4421 num_counters += ARRAY_SIZE(cong_cnts);
4424 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4428 cnts->offsets = kcalloc(num_counters,
4429 sizeof(cnts->offsets), GFP_KERNEL);
4441 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4448 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4449 names[j] = basic_q_cnts[i].name;
4450 offsets[j] = basic_q_cnts[i].offset;
4453 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4454 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4455 names[j] = out_of_seq_q_cnts[i].name;
4456 offsets[j] = out_of_seq_q_cnts[i].offset;
4460 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4461 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4462 names[j] = retrans_q_cnts[i].name;
4463 offsets[j] = retrans_q_cnts[i].offset;
4467 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4468 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4469 names[j] = extended_err_cnts[i].name;
4470 offsets[j] = extended_err_cnts[i].offset;
4474 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4475 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4476 names[j] = cong_cnts[i].name;
4477 offsets[j] = cong_cnts[i].offset;
4482 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
4487 for (i = 0; i < dev->num_ports; i++) {
4488 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4492 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4493 dev->port[i].cnts.offsets);
4495 err = mlx5_core_alloc_q_counter(dev->mdev,
4496 &dev->port[i].cnts.set_id);
4499 "couldn't allocate queue counter for port %d, err %d\n",
4503 dev->port[i].cnts.set_id_valid = true;
4509 mlx5_ib_dealloc_counters(dev);
4513 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4516 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4517 struct mlx5_ib_port *port = &dev->port[port_num - 1];
4519 /* We support only per port stats */
4523 return rdma_alloc_hw_stats_struct(port->cnts.names,
4524 port->cnts.num_q_counters +
4525 port->cnts.num_cong_counters,
4526 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4529 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
4530 struct mlx5_ib_port *port,
4531 struct rdma_hw_stats *stats)
4533 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4538 out = kvzalloc(outlen, GFP_KERNEL);
4542 ret = mlx5_core_query_q_counter(mdev,
4543 port->cnts.set_id, 0,
4548 for (i = 0; i < port->cnts.num_q_counters; i++) {
4549 val = *(__be32 *)(out + port->cnts.offsets[i]);
4550 stats->value[i] = (u64)be32_to_cpu(val);
4558 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4559 struct rdma_hw_stats *stats,
4560 u8 port_num, int index)
4562 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4563 struct mlx5_ib_port *port = &dev->port[port_num - 1];
4564 struct mlx5_core_dev *mdev;
4565 int ret, num_counters;
4571 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4573 /* q_counters are per IB device, query the master mdev */
4574 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
4578 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4579 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4582 /* If port is not affiliated yet, its in down state
4583 * which doesn't have any counters yet, so it would be
4584 * zero. So no need to read from the HCA.
4588 ret = mlx5_lag_query_cong_counters(dev->mdev,
4590 port->cnts.num_q_counters,
4591 port->cnts.num_cong_counters,
4592 port->cnts.offsets +
4593 port->cnts.num_q_counters);
4595 mlx5_ib_put_native_port_mdev(dev, port_num);
4601 return num_counters;
4604 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4606 return mlx5_rdma_netdev_free(netdev);
4609 static struct net_device*
4610 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4612 enum rdma_netdev_t type,
4614 unsigned char name_assign_type,
4615 void (*setup)(struct net_device *))
4617 struct net_device *netdev;
4618 struct rdma_netdev *rn;
4620 if (type != RDMA_NETDEV_IPOIB)
4621 return ERR_PTR(-EOPNOTSUPP);
4623 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4625 if (likely(!IS_ERR_OR_NULL(netdev))) {
4626 rn = netdev_priv(netdev);
4627 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4632 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4634 if (!dev->delay_drop.dbg)
4636 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4637 kfree(dev->delay_drop.dbg);
4638 dev->delay_drop.dbg = NULL;
4641 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4643 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4646 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4647 delay_drop_debugfs_cleanup(dev);
4650 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4651 size_t count, loff_t *pos)
4653 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4657 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4658 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4661 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4662 size_t count, loff_t *pos)
4664 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4668 if (kstrtouint_from_user(buf, count, 0, &var))
4671 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4674 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4677 delay_drop->timeout = timeout;
4682 static const struct file_operations fops_delay_drop_timeout = {
4683 .owner = THIS_MODULE,
4684 .open = simple_open,
4685 .write = delay_drop_timeout_write,
4686 .read = delay_drop_timeout_read,
4689 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4691 struct mlx5_ib_dbg_delay_drop *dbg;
4693 if (!mlx5_debugfs_root)
4696 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4700 dev->delay_drop.dbg = dbg;
4703 debugfs_create_dir("delay_drop",
4704 dev->mdev->priv.dbg_root);
4705 if (!dbg->dir_debugfs)
4708 dbg->events_cnt_debugfs =
4709 debugfs_create_atomic_t("num_timeout_events", 0400,
4711 &dev->delay_drop.events_cnt);
4712 if (!dbg->events_cnt_debugfs)
4715 dbg->rqs_cnt_debugfs =
4716 debugfs_create_atomic_t("num_rqs", 0400,
4718 &dev->delay_drop.rqs_cnt);
4719 if (!dbg->rqs_cnt_debugfs)
4722 dbg->timeout_debugfs =
4723 debugfs_create_file("timeout", 0600,
4726 &fops_delay_drop_timeout);
4727 if (!dbg->timeout_debugfs)
4733 delay_drop_debugfs_cleanup(dev);
4737 static void init_delay_drop(struct mlx5_ib_dev *dev)
4739 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4742 mutex_init(&dev->delay_drop.lock);
4743 dev->delay_drop.dev = dev;
4744 dev->delay_drop.activate = false;
4745 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4746 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4747 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4748 atomic_set(&dev->delay_drop.events_cnt, 0);
4750 if (delay_drop_debugfs_init(dev))
4751 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
4754 static const struct cpumask *
4755 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
4757 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4759 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
4762 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4763 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4764 struct mlx5_ib_multiport_info *mpi)
4766 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4767 struct mlx5_ib_port *port = &ibdev->port[port_num];
4772 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4774 spin_lock(&port->mp.mpi_lock);
4776 spin_unlock(&port->mp.mpi_lock);
4781 spin_unlock(&port->mp.mpi_lock);
4782 mlx5_remove_netdev_notifier(ibdev, port_num);
4783 spin_lock(&port->mp.mpi_lock);
4785 comps = mpi->mdev_refcnt;
4787 mpi->unaffiliate = true;
4788 init_completion(&mpi->unref_comp);
4789 spin_unlock(&port->mp.mpi_lock);
4791 for (i = 0; i < comps; i++)
4792 wait_for_completion(&mpi->unref_comp);
4794 spin_lock(&port->mp.mpi_lock);
4795 mpi->unaffiliate = false;
4798 port->mp.mpi = NULL;
4800 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4802 spin_unlock(&port->mp.mpi_lock);
4804 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4806 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4807 /* Log an error, still needed to cleanup the pointers and add
4808 * it back to the list.
4811 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4814 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4817 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4818 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4819 struct mlx5_ib_multiport_info *mpi)
4821 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4824 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4825 if (ibdev->port[port_num].mp.mpi) {
4826 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4828 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4832 ibdev->port[port_num].mp.mpi = mpi;
4834 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4836 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4840 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4844 err = mlx5_add_netdev_notifier(ibdev, port_num);
4846 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4851 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4858 mlx5_ib_unbind_slave_port(ibdev, mpi);
4862 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4864 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4865 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4867 struct mlx5_ib_multiport_info *mpi;
4871 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4874 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4875 &dev->sys_image_guid);
4879 err = mlx5_nic_vport_enable_roce(dev->mdev);
4883 mutex_lock(&mlx5_ib_multiport_mutex);
4884 for (i = 0; i < dev->num_ports; i++) {
4887 /* build a stub multiport info struct for the native port. */
4888 if (i == port_num) {
4889 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4891 mutex_unlock(&mlx5_ib_multiport_mutex);
4892 mlx5_nic_vport_disable_roce(dev->mdev);
4896 mpi->is_master = true;
4897 mpi->mdev = dev->mdev;
4898 mpi->sys_image_guid = dev->sys_image_guid;
4899 dev->port[i].mp.mpi = mpi;
4905 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4907 if (dev->sys_image_guid == mpi->sys_image_guid &&
4908 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4909 bound = mlx5_ib_bind_slave_port(dev, mpi);
4913 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4914 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4915 list_del(&mpi->list);
4920 get_port_caps(dev, i + 1);
4921 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4926 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4927 mutex_unlock(&mlx5_ib_multiport_mutex);
4931 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4933 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4934 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4938 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4941 mutex_lock(&mlx5_ib_multiport_mutex);
4942 for (i = 0; i < dev->num_ports; i++) {
4943 if (dev->port[i].mp.mpi) {
4944 /* Destroy the native port stub */
4945 if (i == port_num) {
4946 kfree(dev->port[i].mp.mpi);
4947 dev->port[i].mp.mpi = NULL;
4949 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4950 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4955 mlx5_ib_dbg(dev, "removing from devlist\n");
4956 list_del(&dev->ib_dev_list);
4957 mutex_unlock(&mlx5_ib_multiport_mutex);
4959 mlx5_nic_vport_disable_roce(dev->mdev);
4962 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
4963 UVERBS_METHOD_DM_ALLOC,
4964 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
4965 UVERBS_ATTR_TYPE(u64),
4966 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
4967 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
4968 UVERBS_ATTR_TYPE(u16),
4969 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4971 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
4972 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
4973 &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4974 UVERBS_ATTR_TYPE(u64),
4975 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4978 static int populate_specs_root(struct mlx5_ib_dev *dev)
4980 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
4981 uverbs_default_get_objects()};
4982 size_t num_trees = 1;
4984 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
4985 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4986 default_root[num_trees++] = &mlx5_ib_flow_action;
4988 if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
4989 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4990 default_root[num_trees++] = &mlx5_ib_dm;
4992 dev->ib_dev.specs_root =
4993 uverbs_alloc_spec_tree(num_trees, default_root);
4995 return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
4998 static void depopulate_specs_root(struct mlx5_ib_dev *dev)
5000 uverbs_free_spec_tree(dev->ib_dev.specs_root);
5003 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5005 mlx5_ib_cleanup_multiport_master(dev);
5006 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5007 cleanup_srcu_struct(&dev->mr_srcu);
5012 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5014 struct mlx5_core_dev *mdev = dev->mdev;
5019 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5024 for (i = 0; i < dev->num_ports; i++) {
5025 spin_lock_init(&dev->port[i].mp.mpi_lock);
5026 rwlock_init(&dev->roce[i].netdev_lock);
5029 err = mlx5_ib_init_multiport_master(dev);
5033 if (!mlx5_core_mp_enabled(mdev)) {
5034 for (i = 1; i <= dev->num_ports; i++) {
5035 err = get_port_caps(dev, i);
5040 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5045 if (mlx5_use_mad_ifc(dev))
5046 get_ext_port_caps(dev);
5048 if (!mlx5_lag_is_active(mdev))
5051 name = "mlx5_bond_%d";
5053 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5054 dev->ib_dev.owner = THIS_MODULE;
5055 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
5056 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
5057 dev->ib_dev.phys_port_cnt = dev->num_ports;
5058 dev->ib_dev.num_comp_vectors =
5059 dev->mdev->priv.eq_table.num_comp_vectors;
5060 dev->ib_dev.dev.parent = &mdev->pdev->dev;
5062 mutex_init(&dev->cap_mask_mutex);
5063 INIT_LIST_HEAD(&dev->qp_list);
5064 spin_lock_init(&dev->reset_flow_resource_lock);
5066 spin_lock_init(&dev->memic.memic_lock);
5067 dev->memic.dev = mdev;
5069 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5070 err = init_srcu_struct(&dev->mr_srcu);
5077 mlx5_ib_cleanup_multiport_master(dev);
5085 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5087 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5092 mutex_init(&dev->flow_db->lock);
5097 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5099 struct mlx5_ib_dev *nic_dev;
5101 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5106 dev->flow_db = nic_dev->flow_db;
5111 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5113 kfree(dev->flow_db);
5116 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5118 struct mlx5_core_dev *mdev = dev->mdev;
5121 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5122 dev->ib_dev.uverbs_cmd_mask =
5123 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5124 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5125 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5126 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5127 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
5128 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5129 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
5130 (1ull << IB_USER_VERBS_CMD_REG_MR) |
5131 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
5132 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5133 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5134 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5135 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5136 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5137 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5138 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5139 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5140 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5141 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5142 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5143 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5144 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5145 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5146 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5147 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5148 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5149 dev->ib_dev.uverbs_ex_cmd_mask =
5150 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5151 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
5152 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
5153 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5154 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5156 dev->ib_dev.query_device = mlx5_ib_query_device;
5157 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
5158 dev->ib_dev.query_gid = mlx5_ib_query_gid;
5159 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5160 dev->ib_dev.del_gid = mlx5_ib_del_gid;
5161 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5162 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5163 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5164 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5165 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5166 dev->ib_dev.mmap = mlx5_ib_mmap;
5167 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5168 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5169 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5170 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5171 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5172 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5173 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5174 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5175 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5176 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5177 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5178 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5179 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5180 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
5181 dev->ib_dev.post_send = mlx5_ib_post_send;
5182 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5183 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5184 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5185 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5186 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5187 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5188 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5189 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5190 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
5191 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
5192 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5193 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5194 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5195 dev->ib_dev.process_mad = mlx5_ib_process_mad;
5196 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
5197 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
5198 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
5199 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
5200 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5201 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
5202 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
5204 if (mlx5_core_is_pf(mdev)) {
5205 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5206 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5207 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5208 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5211 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5213 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5215 if (MLX5_CAP_GEN(mdev, imaicl)) {
5216 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5217 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5218 dev->ib_dev.uverbs_cmd_mask |=
5219 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5220 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5223 if (MLX5_CAP_GEN(mdev, xrc)) {
5224 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5225 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5226 dev->ib_dev.uverbs_cmd_mask |=
5227 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5228 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5231 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5232 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5233 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5234 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5237 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5238 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5239 dev->ib_dev.uverbs_ex_cmd_mask |=
5240 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5241 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5242 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5243 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5244 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5245 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5247 err = init_node_data(dev);
5251 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5252 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5253 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5254 mutex_init(&dev->lb_mutex);
5259 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5261 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5262 dev->ib_dev.query_port = mlx5_ib_query_port;
5267 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5269 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5270 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5275 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
5280 for (i = 0; i < dev->num_ports; i++) {
5281 dev->roce[i].dev = dev;
5282 dev->roce[i].native_port_num = i + 1;
5283 dev->roce[i].last_port_state = IB_PORT_DOWN;
5286 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5287 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5288 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5289 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5290 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5291 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5293 dev->ib_dev.uverbs_ex_cmd_mask |=
5294 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5295 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5296 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5297 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5298 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5300 return mlx5_add_netdev_notifier(dev, port_num);
5303 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5305 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5307 mlx5_remove_netdev_notifier(dev, port_num);
5310 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5312 struct mlx5_core_dev *mdev = dev->mdev;
5313 enum rdma_link_layer ll;
5318 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5319 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5320 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5322 if (ll == IB_LINK_LAYER_ETHERNET)
5323 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5328 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5330 mlx5_ib_stage_common_roce_cleanup(dev);
5333 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5335 struct mlx5_core_dev *mdev = dev->mdev;
5336 enum rdma_link_layer ll;
5341 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5342 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5343 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5345 if (ll == IB_LINK_LAYER_ETHERNET) {
5346 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5350 err = mlx5_enable_eth(dev, port_num);
5357 mlx5_ib_stage_common_roce_cleanup(dev);
5362 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5364 struct mlx5_core_dev *mdev = dev->mdev;
5365 enum rdma_link_layer ll;
5369 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5370 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5371 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5373 if (ll == IB_LINK_LAYER_ETHERNET) {
5374 mlx5_disable_eth(dev);
5375 mlx5_ib_stage_common_roce_cleanup(dev);
5379 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
5381 return create_dev_resources(&dev->devr);
5384 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
5386 destroy_dev_resources(&dev->devr);
5389 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5391 mlx5_ib_internal_fill_odp_caps(dev);
5393 return mlx5_ib_odp_init_one(dev);
5396 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
5398 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5399 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
5400 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
5402 return mlx5_ib_alloc_counters(dev);
5408 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
5410 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5411 mlx5_ib_dealloc_counters(dev);
5414 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5416 return mlx5_ib_init_cong_debugfs(dev,
5417 mlx5_core_native_port_num(dev->mdev) - 1);
5420 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5422 mlx5_ib_cleanup_cong_debugfs(dev,
5423 mlx5_core_native_port_num(dev->mdev) - 1);
5426 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5428 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
5429 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
5432 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5434 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5437 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
5441 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5445 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5447 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5452 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
5454 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5455 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5458 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5460 return populate_specs_root(dev);
5463 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
5465 return ib_register_device(&dev->ib_dev, NULL);
5468 static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5470 depopulate_specs_root(dev);
5473 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
5475 destroy_umrc_res(dev);
5478 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
5480 ib_unregister_device(&dev->ib_dev);
5483 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
5485 return create_umr_res(dev);
5488 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5490 init_delay_drop(dev);
5495 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5497 cancel_delay_drop(dev);
5500 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
5505 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
5506 err = device_create_file(&dev->ib_dev.dev,
5507 mlx5_class_attributes[i]);
5515 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5517 mlx5_ib_register_vport_reps(dev);
5522 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5524 mlx5_ib_unregister_vport_reps(dev);
5527 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5528 const struct mlx5_ib_profile *profile,
5531 /* Number of stages to cleanup */
5534 if (profile->stage[stage].cleanup)
5535 profile->stage[stage].cleanup(dev);
5538 ib_dealloc_device((struct ib_device *)dev);
5541 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5543 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5544 const struct mlx5_ib_profile *profile)
5549 printk_once(KERN_INFO "%s", mlx5_version);
5551 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5552 if (profile->stage[i].init) {
5553 err = profile->stage[i].init(dev);
5559 dev->profile = profile;
5560 dev->ib_active = true;
5565 __mlx5_ib_remove(dev, profile, i);
5570 static const struct mlx5_ib_profile pf_profile = {
5571 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5572 mlx5_ib_stage_init_init,
5573 mlx5_ib_stage_init_cleanup),
5574 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5575 mlx5_ib_stage_flow_db_init,
5576 mlx5_ib_stage_flow_db_cleanup),
5577 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5578 mlx5_ib_stage_caps_init,
5580 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5581 mlx5_ib_stage_non_default_cb,
5583 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5584 mlx5_ib_stage_roce_init,
5585 mlx5_ib_stage_roce_cleanup),
5586 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5587 mlx5_ib_stage_dev_res_init,
5588 mlx5_ib_stage_dev_res_cleanup),
5589 STAGE_CREATE(MLX5_IB_STAGE_ODP,
5590 mlx5_ib_stage_odp_init,
5592 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5593 mlx5_ib_stage_counters_init,
5594 mlx5_ib_stage_counters_cleanup),
5595 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
5596 mlx5_ib_stage_cong_debugfs_init,
5597 mlx5_ib_stage_cong_debugfs_cleanup),
5598 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5599 mlx5_ib_stage_uar_init,
5600 mlx5_ib_stage_uar_cleanup),
5601 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5602 mlx5_ib_stage_bfrag_init,
5603 mlx5_ib_stage_bfrag_cleanup),
5604 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5606 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
5607 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5608 mlx5_ib_stage_populate_specs,
5609 mlx5_ib_stage_depopulate_specs),
5610 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5611 mlx5_ib_stage_ib_reg_init,
5612 mlx5_ib_stage_ib_reg_cleanup),
5613 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5614 mlx5_ib_stage_post_ib_reg_umr_init,
5616 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
5617 mlx5_ib_stage_delay_drop_init,
5618 mlx5_ib_stage_delay_drop_cleanup),
5619 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5620 mlx5_ib_stage_class_attr_init,
5624 static const struct mlx5_ib_profile nic_rep_profile = {
5625 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5626 mlx5_ib_stage_init_init,
5627 mlx5_ib_stage_init_cleanup),
5628 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5629 mlx5_ib_stage_flow_db_init,
5630 mlx5_ib_stage_flow_db_cleanup),
5631 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5632 mlx5_ib_stage_caps_init,
5634 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5635 mlx5_ib_stage_rep_non_default_cb,
5637 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5638 mlx5_ib_stage_rep_roce_init,
5639 mlx5_ib_stage_rep_roce_cleanup),
5640 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5641 mlx5_ib_stage_dev_res_init,
5642 mlx5_ib_stage_dev_res_cleanup),
5643 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5644 mlx5_ib_stage_counters_init,
5645 mlx5_ib_stage_counters_cleanup),
5646 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5647 mlx5_ib_stage_uar_init,
5648 mlx5_ib_stage_uar_cleanup),
5649 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5650 mlx5_ib_stage_bfrag_init,
5651 mlx5_ib_stage_bfrag_cleanup),
5652 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5654 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
5655 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5656 mlx5_ib_stage_populate_specs,
5657 mlx5_ib_stage_depopulate_specs),
5658 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5659 mlx5_ib_stage_ib_reg_init,
5660 mlx5_ib_stage_ib_reg_cleanup),
5661 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5662 mlx5_ib_stage_post_ib_reg_umr_init,
5664 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5665 mlx5_ib_stage_class_attr_init,
5667 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
5668 mlx5_ib_stage_rep_reg_init,
5669 mlx5_ib_stage_rep_reg_cleanup),
5672 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5674 struct mlx5_ib_multiport_info *mpi;
5675 struct mlx5_ib_dev *dev;
5679 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5685 err = mlx5_query_nic_vport_system_image_guid(mdev,
5686 &mpi->sys_image_guid);
5692 mutex_lock(&mlx5_ib_multiport_mutex);
5693 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5694 if (dev->sys_image_guid == mpi->sys_image_guid)
5695 bound = mlx5_ib_bind_slave_port(dev, mpi);
5698 rdma_roce_rescan_device(&dev->ib_dev);
5704 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5705 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5707 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5709 mutex_unlock(&mlx5_ib_multiport_mutex);
5714 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5716 enum rdma_link_layer ll;
5717 struct mlx5_ib_dev *dev;
5720 printk_once(KERN_INFO "%s", mlx5_version);
5722 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5723 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5725 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5726 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5728 return mlx5_ib_add_slave_port(mdev, port_num);
5731 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
5736 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
5737 MLX5_CAP_GEN(mdev, num_vhca_ports));
5739 if (MLX5_VPORT_MANAGER(mdev) &&
5740 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5741 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
5743 return __mlx5_ib_add(dev, &nic_rep_profile);
5746 return __mlx5_ib_add(dev, &pf_profile);
5749 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
5751 struct mlx5_ib_multiport_info *mpi;
5752 struct mlx5_ib_dev *dev;
5754 if (mlx5_core_is_mp_slave(mdev)) {
5756 mutex_lock(&mlx5_ib_multiport_mutex);
5758 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5759 list_del(&mpi->list);
5760 mutex_unlock(&mlx5_ib_multiport_mutex);
5765 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
5768 static struct mlx5_interface mlx5_ib_interface = {
5770 .remove = mlx5_ib_remove,
5771 .event = mlx5_ib_event,
5772 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5773 .pfault = mlx5_ib_pfault,
5775 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
5778 unsigned long mlx5_ib_get_xlt_emergency_page(void)
5780 mutex_lock(&xlt_emergency_page_mutex);
5781 return xlt_emergency_page;
5784 void mlx5_ib_put_xlt_emergency_page(void)
5786 mutex_unlock(&xlt_emergency_page_mutex);
5789 static int __init mlx5_ib_init(void)
5793 xlt_emergency_page = __get_free_page(GFP_KERNEL);
5794 if (!xlt_emergency_page)
5797 mutex_init(&xlt_emergency_page_mutex);
5799 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5800 if (!mlx5_ib_event_wq) {
5801 free_page(xlt_emergency_page);
5807 err = mlx5_register_interface(&mlx5_ib_interface);
5812 static void __exit mlx5_ib_cleanup(void)
5814 mlx5_unregister_interface(&mlx5_ib_interface);
5815 destroy_workqueue(mlx5_ib_event_wq);
5816 mutex_destroy(&xlt_emergency_page_mutex);
5817 free_page(xlt_emergency_page);
5820 module_init(mlx5_ib_init);
5821 module_exit(mlx5_ib_cleanup);