2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/bitmap.h>
42 #if defined(CONFIG_X86)
45 #include <linux/sched.h>
46 #include <linux/sched/mm.h>
47 #include <linux/sched/task.h>
48 #include <linux/delay.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_cache.h>
52 #include <linux/mlx5/port.h>
53 #include <linux/mlx5/vport.h>
54 #include <linux/mlx5/fs.h>
55 #include <linux/list.h>
56 #include <rdma/ib_smi.h>
57 #include <rdma/ib_umem.h>
59 #include <linux/etherdevice.h>
63 #include <linux/mlx5/fs_helpers.h>
64 #include <linux/mlx5/accel.h>
65 #include <rdma/uverbs_std_types.h>
66 #include <rdma/mlx5_user_ioctl_verbs.h>
67 #include <rdma/mlx5_user_ioctl_cmds.h>
69 #define UVERBS_MODULE_NAME mlx5_ib
70 #include <rdma/uverbs_named_ioctl.h>
72 #define DRIVER_NAME "mlx5_ib"
73 #define DRIVER_VERSION "5.0-0"
75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77 MODULE_LICENSE("Dual BSD/GPL");
79 static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
83 struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
87 enum mlx5_dev_event event;
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
95 static struct workqueue_struct *mlx5_ib_event_wq;
96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97 static LIST_HEAD(mlx5_ib_dev_list);
99 * This mutex should be held when accessing either of the above lists
101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
103 /* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
106 static unsigned long xlt_emergency_page;
107 static struct mutex xlt_emergency_page_mutex;
109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
111 struct mlx5_ib_dev *dev;
113 mutex_lock(&mlx5_ib_multiport_mutex);
115 mutex_unlock(&mlx5_ib_multiport_mutex);
119 static enum rdma_link_layer
120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
122 switch (port_type_cap) {
123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
128 return IB_LINK_LAYER_UNSPECIFIED;
132 static enum rdma_link_layer
133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
141 static int get_port_state(struct ib_device *ibdev,
143 enum ib_port_state *state)
145 struct ib_port_attr attr;
148 memset(&attr, 0, sizeof(attr));
149 ret = ibdev->query_port(ibdev, port_num, &attr);
155 static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
172 write_lock(&roce->netdev_lock);
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
183 roce->netdev = (event == NETDEV_UNREGISTER) ?
186 write_unlock(&roce->netdev_lock);
192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
193 struct net_device *upper = NULL;
196 upper = netdev_master_upper_dev_get(lag_ndev);
200 if ((upper == ndev || (!upper && ndev == roce->netdev))
201 && ibdev->ib_active) {
202 struct ib_event ibev = { };
203 enum ib_port_state port_state;
205 if (get_port_state(&ibdev->ib_dev, port_num,
209 if (roce->last_port_state == port_state)
212 roce->last_port_state = port_state;
213 ibev.device = &ibdev->ib_dev;
214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
221 ibev.element.port_num = port_num;
222 ib_dispatch_event(&ibev);
231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
240 struct mlx5_core_dev *mdev;
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
246 ndev = mlx5_lag_get_roce_netdev(mdev);
250 /* Ensure ndev does not disappear before we invoke dev_hold()
252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
276 *native_port_num = ib_port_num;
281 *native_port_num = 1;
283 port = &ibdev->port[ib_port_num - 1];
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
297 spin_unlock(&port->mp.mpi_lock);
302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
312 port = &ibdev->port[port_num - 1];
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
323 spin_unlock(&port->mp.mpi_lock);
326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
387 struct mlx5_ib_dev *dev = to_mdev(device);
388 struct mlx5_core_dev *mdev;
389 struct net_device *ndev, *upper;
390 enum ib_mtu ndev_ib_mtu;
391 bool put_mdev = true;
397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
411 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper,
416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->ip_gids = true;
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
434 props->qkey_viol_cntr = qkey_viol_cntr;
436 /* If this is a stub query for an unaffiliated port stop here */
440 ndev = mlx5_ib_get_netdev(device, port_num);
444 if (mlx5_lag_is_active(dev->mdev)) {
446 upper = netdev_master_upper_dev_get_rcu(ndev);
455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
467 mlx5_ib_put_native_port_mdev(dev, port_num);
471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
486 if (is_vlan_dev(attr->ndev)) {
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
494 roce_version = MLX5_ROCE_VERSION_1;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
513 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
514 __always_unused void **context)
516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
517 attr->index, &attr->gid, attr);
520 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
527 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
549 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
561 static void get_atomic_caps(struct mlx5_ib_dev *dev,
563 struct ib_device_attr *props)
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
567 u8 atomic_req_8B_endianness_mode =
568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
579 props->atomic_cap = IB_ATOMIC_NONE;
583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
588 get_atomic_caps(dev, atomic_size_qp, props);
591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
596 get_atomic_caps(dev, atomic_size_qp, props);
599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
601 struct ib_device_attr props = {};
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
606 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
632 *sys_image_guid = cpu_to_be64(tmp);
638 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
659 static int mlx5_query_vendor_id(struct ib_device *ibdev,
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
700 *node_guid = cpu_to_be64(tmp);
705 struct mlx5_reg_node_desc {
706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
711 struct mlx5_reg_node_desc in;
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
716 memset(&in, 0, sizeof(in));
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
723 static int mlx5_ib_query_device(struct ib_device *ibdev,
724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
728 struct mlx5_core_dev *mdev = dev->mdev;
733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
734 bool raw_support = !mlx5_core_mp_enabled(mdev);
735 struct mlx5_ib_query_device_resp resp = {};
739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
743 resp.response_length = resp_len;
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
768 IB_DEVICE_RC_RNR_NAK_GEN;
770 if (MLX5_CAP_GEN(mdev, pkv))
771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
772 if (MLX5_CAP_GEN(mdev, qkv))
773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
774 if (MLX5_CAP_GEN(mdev, apm))
775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
776 if (MLX5_CAP_GEN(mdev, xrc))
777 props->device_cap_flags |= IB_DEVICE_XRC;
778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
786 if (MLX5_CAP_GEN(mdev, sho)) {
787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
830 MLX5_RX_HASH_DST_PORT_UDP |
832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
836 resp.response_length += sizeof(resp.rss_caps);
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
862 /* Legacy bit to support old userspace libraries */
863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
881 props->max_mr_size = ~0ull;
882 props->page_size_cap = ~(min_page_size - 1);
883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
893 props->max_sge_rd = MLX5_MAX_SGE_RD;
894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
904 props->max_srq_sge = max_rq_sg - 1;
905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
907 get_atomic_caps_qp(dev, props);
908 props->masked_atomic_cap = IB_ATOMIC_NONE;
909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
914 props->max_ah = INT_MAX;
915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
919 if (MLX5_CAP_GEN(mdev, pg))
920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
931 IB_LINK_LAYER_ETHERNET && raw_support) {
932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
954 props->cq_caps.max_cq_moderation_period =
958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
959 resp.response_length += sizeof(resp.cqe_comp_caps);
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
991 resp.response_length += sizeof(resp.packet_pacing_caps);
994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1019 if (field_avail(typeof(resp), sw_parsing_caps,
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1089 enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1097 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1103 if (active_width & MLX5_IB_WIDTH_1X) {
1104 *ib_width = IB_WIDTH_1X;
1105 } else if (active_width & MLX5_IB_WIDTH_2X) {
1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1109 } else if (active_width & MLX5_IB_WIDTH_4X) {
1110 *ib_width = IB_WIDTH_4X;
1111 } else if (active_width & MLX5_IB_WIDTH_8X) {
1112 *ib_width = IB_WIDTH_8X;
1113 } else if (active_width & MLX5_IB_WIDTH_12X) {
1114 *ib_width = IB_WIDTH_12X;
1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1124 static int mlx5_mtu_to_ib_mtu(int mtu)
1129 case 1024: return 3;
1130 case 2048: return 4;
1131 case 4096: return 5;
1133 pr_warn("invalid mtu\n");
1138 enum ib_max_vl_num {
1140 __IB_MAX_VL_0_1 = 2,
1141 __IB_MAX_VL_0_3 = 3,
1142 __IB_MAX_VL_0_7 = 4,
1143 __IB_MAX_VL_0_14 = 5,
1146 enum mlx5_vl_hw_cap {
1155 MLX5_VL_HW_0_14 = 15
1158 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1161 switch (vl_hw_cap) {
1163 *max_vl_num = __IB_MAX_VL_0;
1165 case MLX5_VL_HW_0_1:
1166 *max_vl_num = __IB_MAX_VL_0_1;
1168 case MLX5_VL_HW_0_3:
1169 *max_vl_num = __IB_MAX_VL_0_3;
1171 case MLX5_VL_HW_0_7:
1172 *max_vl_num = __IB_MAX_VL_0_7;
1174 case MLX5_VL_HW_0_14:
1175 *max_vl_num = __IB_MAX_VL_0_14;
1185 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1186 struct ib_port_attr *props)
1188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1189 struct mlx5_core_dev *mdev = dev->mdev;
1190 struct mlx5_hca_vport_context *rep;
1194 u8 ib_link_width_oper;
1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1203 /* props being zeroed by the caller, avoid zeroing it here */
1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1209 props->lid = rep->lid;
1210 props->lmc = rep->lmc;
1211 props->sm_lid = rep->sm_lid;
1212 props->sm_sl = rep->sm_sl;
1213 props->state = rep->vport_state;
1214 props->phys_state = rep->port_physical_state;
1215 props->port_cap_flags = rep->cap_mask1;
1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1219 props->bad_pkey_cntr = rep->pkey_violation_counter;
1220 props->qkey_viol_cntr = rep->qkey_violation_counter;
1221 props->subnet_timeout = rep->subnet_timeout;
1222 props->init_type_reply = rep->init_type_reply;
1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1228 err = translate_active_width(ibdev, ib_link_width_oper,
1229 &props->active_width);
1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1248 err = translate_max_vl_num(ibdev, vl_hw_cap,
1249 &props->max_vl_num);
1255 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1256 struct ib_port_attr *props)
1261 switch (mlx5_get_vport_access_method(ibdev)) {
1262 case MLX5_VPORT_ACCESS_METHOD_MAD:
1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1266 case MLX5_VPORT_ACCESS_METHOD_HCA:
1267 ret = mlx5_query_hca_port(ibdev, port, props);
1270 case MLX5_VPORT_ACCESS_METHOD_NIC:
1271 ret = mlx5_query_port_roce(ibdev, port, props);
1278 if (!ret && props) {
1279 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1280 struct mlx5_core_dev *mdev;
1281 bool put_mdev = true;
1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1285 /* If the port isn't affiliated yet query the master.
1286 * The master and slave will have the same values.
1292 count = mlx5_core_reserved_gids_count(mdev);
1294 mlx5_ib_put_native_port_mdev(dev, port);
1295 props->gid_tbl_len -= count;
1300 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1301 struct ib_port_attr *props)
1305 /* Only link layer == ethernet is valid for representors */
1306 ret = mlx5_query_port_roce(ibdev, port, props);
1310 /* We don't support GIDS */
1311 props->gid_tbl_len = 0;
1316 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1319 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1320 struct mlx5_core_dev *mdev = dev->mdev;
1322 switch (mlx5_get_vport_access_method(ibdev)) {
1323 case MLX5_VPORT_ACCESS_METHOD_MAD:
1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1326 case MLX5_VPORT_ACCESS_METHOD_HCA:
1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1335 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1336 u16 index, u16 *pkey)
1338 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1339 struct mlx5_core_dev *mdev;
1340 bool put_mdev = true;
1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1346 /* The port isn't affiliated yet, get the PKey from the master
1347 * port. For RoCE the PKey tables will be the same.
1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1357 mlx5_ib_put_native_port_mdev(dev, port);
1362 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1365 switch (mlx5_get_vport_access_method(ibdev)) {
1366 case MLX5_VPORT_ACCESS_METHOD_MAD:
1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1369 case MLX5_VPORT_ACCESS_METHOD_HCA:
1370 case MLX5_VPORT_ACCESS_METHOD_NIC:
1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1377 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1378 struct ib_device_modify *props)
1380 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1381 struct mlx5_reg_node_desc in;
1382 struct mlx5_reg_node_desc out;
1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1392 * If possible, pass node desc to FW, so it can generate
1393 * a 144 trap. If cmd fails, just ignore.
1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1406 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1409 struct mlx5_hca_vport_context ctx = {};
1410 struct mlx5_core_dev *mdev;
1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1422 if (~ctx.cap_mask1_perm & mask) {
1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1424 mask, ctx.cap_mask1_perm);
1429 ctx.cap_mask1 = value;
1430 ctx.cap_mask1_perm = mask;
1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1435 mlx5_ib_put_native_port_mdev(dev, port_num);
1440 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1441 struct ib_port_modify *props)
1443 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1444 struct ib_port_attr attr;
1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1450 IB_LINK_LAYER_INFINIBAND);
1452 /* CM layer calls ib_modify_port() regardless of the link layer. For
1453 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1461 return set_port_caps_atomic(dev, port, change_mask, value);
1464 mutex_lock(&dev->cap_mask_mutex);
1466 err = ib_query_port(ibdev, port, &attr);
1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1471 ~props->clr_port_cap_mask;
1473 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1476 mutex_unlock(&dev->cap_mask_mutex);
1480 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1486 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1488 /* Large page with non 4k uar support might limit the dynamic size */
1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1490 return MLX5_MIN_DYN_BFREGS;
1492 return MLX5_MAX_DYN_BFREGS;
1495 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1496 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1497 struct mlx5_bfreg_info *bfregi)
1499 int uars_per_sys_page;
1500 int bfregs_per_sys_page;
1501 int ref_bfregs = req->total_num_bfregs;
1503 if (req->total_num_bfregs == 0)
1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1514 /* This holds the required static allocation asked by the user */
1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1526 lib_uar_4k ? "yes" : "no", ref_bfregs,
1527 req->total_num_bfregs, bfregi->total_num_bfregs,
1528 bfregi->num_sys_pages);
1533 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1535 struct mlx5_bfreg_info *bfregi;
1539 bfregi = &context->bfregi;
1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1554 for (--i; i >= 0; i--)
1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1561 static void deallocate_uars(struct mlx5_ib_dev *dev,
1562 struct mlx5_ib_ucontext *context)
1564 struct mlx5_bfreg_info *bfregi;
1567 bfregi = &context->bfregi;
1568 for (i = 0; i < bfregi->num_sys_pages; i++)
1569 if (i < bfregi->num_static_sys_pages ||
1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1574 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1578 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1581 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1585 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1586 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1587 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1590 mutex_lock(&dev->lb_mutex);
1593 if (dev->user_td == 2)
1594 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1596 mutex_unlock(&dev->lb_mutex);
1600 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1602 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1605 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1607 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1608 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1609 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1612 mutex_lock(&dev->lb_mutex);
1615 if (dev->user_td < 2)
1616 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1618 mutex_unlock(&dev->lb_mutex);
1621 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1622 struct ib_udata *udata)
1624 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1625 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1626 struct mlx5_ib_alloc_ucontext_resp resp = {};
1627 struct mlx5_core_dev *mdev = dev->mdev;
1628 struct mlx5_ib_ucontext *context;
1629 struct mlx5_bfreg_info *bfregi;
1632 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1637 if (!dev->ib_active)
1638 return ERR_PTR(-EAGAIN);
1640 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1642 else if (udata->inlen >= min_req_v2)
1645 return ERR_PTR(-EINVAL);
1647 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1649 return ERR_PTR(err);
1651 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1652 return ERR_PTR(-EOPNOTSUPP);
1654 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1655 return ERR_PTR(-EOPNOTSUPP);
1657 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1658 MLX5_NON_FP_BFREGS_PER_UAR);
1659 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1660 return ERR_PTR(-EINVAL);
1662 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1663 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1664 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1665 resp.cache_line_size = cache_line_size();
1666 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1667 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1668 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1669 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1670 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1671 resp.cqe_version = min_t(__u8,
1672 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1673 req.max_cqe_version);
1674 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1675 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1676 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1677 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1678 resp.response_length = min(offsetof(typeof(resp), response_length) +
1679 sizeof(resp.response_length), udata->outlen);
1681 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1682 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1683 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1684 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1685 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1686 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1687 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1688 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1689 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1690 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1693 context = kzalloc(sizeof(*context), GFP_KERNEL);
1695 return ERR_PTR(-ENOMEM);
1697 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1698 bfregi = &context->bfregi;
1700 /* updates req->total_num_bfregs */
1701 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1705 mutex_init(&bfregi->lock);
1706 bfregi->lib_uar_4k = lib_uar_4k;
1707 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1709 if (!bfregi->count) {
1714 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1715 sizeof(*bfregi->sys_pages),
1717 if (!bfregi->sys_pages) {
1722 err = allocate_uars(dev, context);
1726 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1727 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1730 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1734 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1735 /* Block DEVX on Infiniband as of SELinux */
1736 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1741 err = mlx5_ib_devx_create(dev, context);
1746 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1747 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1752 INIT_LIST_HEAD(&context->vma_private_list);
1753 mutex_init(&context->vma_private_list_mutex);
1754 INIT_LIST_HEAD(&context->db_page_list);
1755 mutex_init(&context->db_page_mutex);
1757 resp.tot_bfregs = req.total_num_bfregs;
1758 resp.num_ports = dev->num_ports;
1760 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1761 resp.response_length += sizeof(resp.cqe_version);
1763 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1764 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1765 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1766 resp.response_length += sizeof(resp.cmds_supp_uhw);
1769 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1770 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1771 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1772 resp.eth_min_inline++;
1774 resp.response_length += sizeof(resp.eth_min_inline);
1777 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1778 if (mdev->clock_info)
1779 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1780 resp.response_length += sizeof(resp.clock_info_versions);
1784 * We don't want to expose information from the PCI bar that is located
1785 * after 4096 bytes, so if the arch only supports larger pages, let's
1786 * pretend we don't support reading the HCA's core clock. This is also
1787 * forced by mmap function.
1789 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1790 if (PAGE_SIZE <= 4096) {
1792 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1793 resp.hca_core_clock_offset =
1794 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1796 resp.response_length += sizeof(resp.hca_core_clock_offset);
1799 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1800 resp.response_length += sizeof(resp.log_uar_size);
1802 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1803 resp.response_length += sizeof(resp.num_uars_per_page);
1805 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1806 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1807 resp.response_length += sizeof(resp.num_dyn_bfregs);
1810 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1811 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1812 resp.dump_fill_mkey = dump_fill_mkey;
1814 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1816 resp.response_length += sizeof(resp.dump_fill_mkey);
1819 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1824 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1825 context->cqe_version = resp.cqe_version;
1826 context->lib_caps = req.lib_caps;
1827 print_lib_caps(dev, context->lib_caps);
1829 return &context->ibucontext;
1832 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1833 mlx5_ib_devx_destroy(dev, context);
1835 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1838 deallocate_uars(dev, context);
1841 kfree(bfregi->sys_pages);
1844 kfree(bfregi->count);
1849 return ERR_PTR(err);
1852 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1854 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1855 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1856 struct mlx5_bfreg_info *bfregi;
1858 if (context->devx_uid)
1859 mlx5_ib_devx_destroy(dev, context);
1861 bfregi = &context->bfregi;
1862 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1864 deallocate_uars(dev, context);
1865 kfree(bfregi->sys_pages);
1866 kfree(bfregi->count);
1872 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1875 int fw_uars_per_page;
1877 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1879 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1882 static int get_command(unsigned long offset)
1884 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1887 static int get_arg(unsigned long offset)
1889 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1892 static int get_index(unsigned long offset)
1894 return get_arg(offset);
1897 /* Index resides in an extra byte to enable larger values than 255 */
1898 static int get_extended_index(unsigned long offset)
1900 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1903 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1905 /* vma_open is called when a new VMA is created on top of our VMA. This
1906 * is done through either mremap flow or split_vma (usually due to
1907 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1908 * as this VMA is strongly hardware related. Therefore we set the
1909 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1910 * calling us again and trying to do incorrect actions. We assume that
1911 * the original VMA size is exactly a single page, and therefore all
1912 * "splitting" operation will not happen to it.
1914 area->vm_ops = NULL;
1917 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1919 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1921 /* It's guaranteed that all VMAs opened on a FD are closed before the
1922 * file itself is closed, therefore no sync is needed with the regular
1923 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1924 * However need a sync with accessing the vma as part of
1925 * mlx5_ib_disassociate_ucontext.
1926 * The close operation is usually called under mm->mmap_sem except when
1927 * process is exiting.
1928 * The exiting case is handled explicitly as part of
1929 * mlx5_ib_disassociate_ucontext.
1931 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1933 /* setting the vma context pointer to null in the mlx5_ib driver's
1934 * private data, to protect a race condition in
1935 * mlx5_ib_disassociate_ucontext().
1937 mlx5_ib_vma_priv_data->vma = NULL;
1938 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1939 list_del(&mlx5_ib_vma_priv_data->list);
1940 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1941 kfree(mlx5_ib_vma_priv_data);
1944 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1945 .open = mlx5_ib_vma_open,
1946 .close = mlx5_ib_vma_close
1949 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1950 struct mlx5_ib_ucontext *ctx)
1952 struct mlx5_ib_vma_private_data *vma_prv;
1953 struct list_head *vma_head = &ctx->vma_private_list;
1955 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1960 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1961 vma->vm_private_data = vma_prv;
1962 vma->vm_ops = &mlx5_ib_vm_ops;
1964 mutex_lock(&ctx->vma_private_list_mutex);
1965 list_add(&vma_prv->list, vma_head);
1966 mutex_unlock(&ctx->vma_private_list_mutex);
1971 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1973 struct vm_area_struct *vma;
1974 struct mlx5_ib_vma_private_data *vma_private, *n;
1975 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1977 mutex_lock(&context->vma_private_list_mutex);
1978 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1980 vma = vma_private->vma;
1981 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
1982 /* context going to be destroyed, should
1983 * not access ops any more.
1985 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1987 list_del(&vma_private->list);
1990 mutex_unlock(&context->vma_private_list_mutex);
1993 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1996 case MLX5_IB_MMAP_WC_PAGE:
1998 case MLX5_IB_MMAP_REGULAR_PAGE:
1999 return "best effort WC";
2000 case MLX5_IB_MMAP_NC_PAGE:
2002 case MLX5_IB_MMAP_DEVICE_MEM:
2003 return "Device Memory";
2009 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2010 struct vm_area_struct *vma,
2011 struct mlx5_ib_ucontext *context)
2016 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2019 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2022 if (vma->vm_flags & VM_WRITE)
2025 if (!dev->mdev->clock_info_page)
2028 pfn = page_to_pfn(dev->mdev->clock_info_page);
2029 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2034 return mlx5_ib_set_vma_data(vma, context);
2037 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2038 struct vm_area_struct *vma,
2039 struct mlx5_ib_ucontext *context)
2041 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2046 u32 bfreg_dyn_idx = 0;
2048 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2049 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2050 bfregi->num_static_sys_pages;
2052 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2056 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2058 idx = get_index(vma->vm_pgoff);
2060 if (idx >= max_valid_idx) {
2061 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2062 idx, max_valid_idx);
2067 case MLX5_IB_MMAP_WC_PAGE:
2068 case MLX5_IB_MMAP_ALLOC_WC:
2069 /* Some architectures don't support WC memory */
2070 #if defined(CONFIG_X86)
2073 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2077 case MLX5_IB_MMAP_REGULAR_PAGE:
2078 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2079 prot = pgprot_writecombine(vma->vm_page_prot);
2081 case MLX5_IB_MMAP_NC_PAGE:
2082 prot = pgprot_noncached(vma->vm_page_prot);
2091 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2092 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2093 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2094 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2095 bfreg_dyn_idx, bfregi->total_num_bfregs);
2099 mutex_lock(&bfregi->lock);
2100 /* Fail if uar already allocated, first bfreg index of each
2101 * page holds its count.
2103 if (bfregi->count[bfreg_dyn_idx]) {
2104 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2105 mutex_unlock(&bfregi->lock);
2109 bfregi->count[bfreg_dyn_idx]++;
2110 mutex_unlock(&bfregi->lock);
2112 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2114 mlx5_ib_warn(dev, "UAR alloc failed\n");
2118 uar_index = bfregi->sys_pages[idx];
2121 pfn = uar_index2pfn(dev, uar_index);
2122 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2124 vma->vm_page_prot = prot;
2125 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2126 PAGE_SIZE, vma->vm_page_prot);
2129 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2130 err, mmap_cmd2str(cmd));
2135 err = mlx5_ib_set_vma_data(vma, context);
2140 bfregi->sys_pages[idx] = uar_index;
2147 mlx5_cmd_free_uar(dev->mdev, idx);
2150 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2155 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2157 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2158 struct mlx5_ib_dev *dev = to_mdev(context->device);
2159 u16 page_idx = get_extended_index(vma->vm_pgoff);
2160 size_t map_size = vma->vm_end - vma->vm_start;
2161 u32 npages = map_size >> PAGE_SHIFT;
2165 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2169 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2170 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2173 prot = pgprot_writecombine(vma->vm_page_prot);
2174 vma->vm_page_prot = prot;
2176 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2180 return mlx5_ib_set_vma_data(vma, mctx);
2183 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2185 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2186 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2187 unsigned long command;
2190 command = get_command(vma->vm_pgoff);
2192 case MLX5_IB_MMAP_WC_PAGE:
2193 case MLX5_IB_MMAP_NC_PAGE:
2194 case MLX5_IB_MMAP_REGULAR_PAGE:
2195 case MLX5_IB_MMAP_ALLOC_WC:
2196 return uar_mmap(dev, command, vma, context);
2198 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2201 case MLX5_IB_MMAP_CORE_CLOCK:
2202 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2205 if (vma->vm_flags & VM_WRITE)
2208 /* Don't expose to user-space information it shouldn't have */
2209 if (PAGE_SIZE > 4096)
2212 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2213 pfn = (dev->mdev->iseg_base +
2214 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2216 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2217 PAGE_SIZE, vma->vm_page_prot))
2220 case MLX5_IB_MMAP_CLOCK_INFO:
2221 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2223 case MLX5_IB_MMAP_DEVICE_MEM:
2224 return dm_mmap(ibcontext, vma);
2233 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2234 struct ib_ucontext *context,
2235 struct ib_dm_alloc_attr *attr,
2236 struct uverbs_attr_bundle *attrs)
2238 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2239 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2240 phys_addr_t memic_addr;
2241 struct mlx5_ib_dm *dm;
2246 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2248 return ERR_PTR(-ENOMEM);
2250 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2251 attr->length, act_size, attr->alignment);
2253 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2254 act_size, attr->alignment);
2258 start_offset = memic_addr & ~PAGE_MASK;
2259 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2260 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2263 err = uverbs_copy_to(attrs,
2264 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2265 &start_offset, sizeof(start_offset));
2269 err = uverbs_copy_to(attrs,
2270 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2271 &page_idx, sizeof(page_idx));
2275 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2276 DIV_ROUND_UP(act_size, PAGE_SIZE));
2278 dm->dev_addr = memic_addr;
2283 mlx5_cmd_dealloc_memic(memic, memic_addr,
2287 return ERR_PTR(err);
2290 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2292 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2293 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2294 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2298 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2302 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2303 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2305 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2307 DIV_ROUND_UP(act_size, PAGE_SIZE));
2314 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2315 struct ib_ucontext *context,
2316 struct ib_udata *udata)
2318 struct mlx5_ib_alloc_pd_resp resp;
2319 struct mlx5_ib_pd *pd;
2322 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2324 return ERR_PTR(-ENOMEM);
2326 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2329 return ERR_PTR(err);
2334 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2335 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2337 return ERR_PTR(-EFAULT);
2344 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2346 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2347 struct mlx5_ib_pd *mpd = to_mpd(pd);
2349 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2356 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2357 MATCH_CRITERIA_ENABLE_MISC_BIT,
2358 MATCH_CRITERIA_ENABLE_INNER_BIT,
2359 MATCH_CRITERIA_ENABLE_MISC2_BIT
2362 #define HEADER_IS_ZERO(match_criteria, headers) \
2363 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2364 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2366 static u8 get_match_criteria_enable(u32 *match_criteria)
2368 u8 match_criteria_enable;
2370 match_criteria_enable =
2371 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2372 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2373 match_criteria_enable |=
2374 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2375 MATCH_CRITERIA_ENABLE_MISC_BIT;
2376 match_criteria_enable |=
2377 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2378 MATCH_CRITERIA_ENABLE_INNER_BIT;
2379 match_criteria_enable |=
2380 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2381 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2383 return match_criteria_enable;
2386 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2388 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2389 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2392 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2396 MLX5_SET(fte_match_set_misc,
2397 misc_c, inner_ipv6_flow_label, mask);
2398 MLX5_SET(fte_match_set_misc,
2399 misc_v, inner_ipv6_flow_label, val);
2401 MLX5_SET(fte_match_set_misc,
2402 misc_c, outer_ipv6_flow_label, mask);
2403 MLX5_SET(fte_match_set_misc,
2404 misc_v, outer_ipv6_flow_label, val);
2408 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2410 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2411 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2412 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2413 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2416 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2418 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2419 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2422 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2423 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2426 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2427 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2430 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2431 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2437 #define LAST_ETH_FIELD vlan_tag
2438 #define LAST_IB_FIELD sl
2439 #define LAST_IPV4_FIELD tos
2440 #define LAST_IPV6_FIELD traffic_class
2441 #define LAST_TCP_UDP_FIELD src_port
2442 #define LAST_TUNNEL_FIELD tunnel_id
2443 #define LAST_FLOW_TAG_FIELD tag_id
2444 #define LAST_DROP_FIELD size
2445 #define LAST_COUNTERS_FIELD counters
2447 /* Field is the last supported field */
2448 #define FIELDS_NOT_SUPPORTED(filter, field)\
2449 memchr_inv((void *)&filter.field +\
2450 sizeof(filter.field), 0,\
2452 offsetof(typeof(filter), field) -\
2453 sizeof(filter.field))
2455 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2456 const struct ib_flow_attr *flow_attr,
2457 struct mlx5_flow_act *action)
2459 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2461 switch (maction->ib_action.type) {
2462 case IB_FLOW_ACTION_ESP:
2463 /* Currently only AES_GCM keymat is supported by the driver */
2464 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2465 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2466 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2467 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2474 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2475 u32 *match_v, const union ib_flow_spec *ib_spec,
2476 const struct ib_flow_attr *flow_attr,
2477 struct mlx5_flow_act *action, u32 prev_type)
2479 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2481 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2483 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2485 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2492 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2493 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2495 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2497 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2498 ft_field_support.inner_ip_version);
2500 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2502 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2504 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2505 ft_field_support.outer_ip_version);
2508 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2509 case IB_FLOW_SPEC_ETH:
2510 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2513 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2515 ib_spec->eth.mask.dst_mac);
2516 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2518 ib_spec->eth.val.dst_mac);
2520 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2522 ib_spec->eth.mask.src_mac);
2523 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2525 ib_spec->eth.val.src_mac);
2527 if (ib_spec->eth.mask.vlan_tag) {
2528 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2530 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2533 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2534 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2535 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2536 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2538 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2540 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2541 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2543 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2545 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2547 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2548 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2550 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2552 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2553 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2554 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2555 ethertype, ntohs(ib_spec->eth.val.ether_type));
2557 case IB_FLOW_SPEC_IPV4:
2558 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2562 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2564 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2565 ip_version, MLX5_FS_IPV4_VERSION);
2567 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2569 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2570 ethertype, ETH_P_IP);
2573 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2574 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2575 &ib_spec->ipv4.mask.src_ip,
2576 sizeof(ib_spec->ipv4.mask.src_ip));
2577 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2578 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2579 &ib_spec->ipv4.val.src_ip,
2580 sizeof(ib_spec->ipv4.val.src_ip));
2581 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2582 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2583 &ib_spec->ipv4.mask.dst_ip,
2584 sizeof(ib_spec->ipv4.mask.dst_ip));
2585 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2586 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2587 &ib_spec->ipv4.val.dst_ip,
2588 sizeof(ib_spec->ipv4.val.dst_ip));
2590 set_tos(headers_c, headers_v,
2591 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2593 set_proto(headers_c, headers_v,
2594 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2596 case IB_FLOW_SPEC_IPV6:
2597 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2601 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2603 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2604 ip_version, MLX5_FS_IPV6_VERSION);
2606 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2608 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2609 ethertype, ETH_P_IPV6);
2612 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2613 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2614 &ib_spec->ipv6.mask.src_ip,
2615 sizeof(ib_spec->ipv6.mask.src_ip));
2616 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2617 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2618 &ib_spec->ipv6.val.src_ip,
2619 sizeof(ib_spec->ipv6.val.src_ip));
2620 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2621 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2622 &ib_spec->ipv6.mask.dst_ip,
2623 sizeof(ib_spec->ipv6.mask.dst_ip));
2624 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2625 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2626 &ib_spec->ipv6.val.dst_ip,
2627 sizeof(ib_spec->ipv6.val.dst_ip));
2629 set_tos(headers_c, headers_v,
2630 ib_spec->ipv6.mask.traffic_class,
2631 ib_spec->ipv6.val.traffic_class);
2633 set_proto(headers_c, headers_v,
2634 ib_spec->ipv6.mask.next_hdr,
2635 ib_spec->ipv6.val.next_hdr);
2637 set_flow_label(misc_params_c, misc_params_v,
2638 ntohl(ib_spec->ipv6.mask.flow_label),
2639 ntohl(ib_spec->ipv6.val.flow_label),
2640 ib_spec->type & IB_FLOW_SPEC_INNER);
2642 case IB_FLOW_SPEC_ESP:
2643 if (ib_spec->esp.mask.seq)
2646 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2647 ntohl(ib_spec->esp.mask.spi));
2648 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2649 ntohl(ib_spec->esp.val.spi));
2651 case IB_FLOW_SPEC_TCP:
2652 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2653 LAST_TCP_UDP_FIELD))
2656 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2661 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2662 ntohs(ib_spec->tcp_udp.mask.src_port));
2663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2664 ntohs(ib_spec->tcp_udp.val.src_port));
2666 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2667 ntohs(ib_spec->tcp_udp.mask.dst_port));
2668 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2669 ntohs(ib_spec->tcp_udp.val.dst_port));
2671 case IB_FLOW_SPEC_UDP:
2672 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2673 LAST_TCP_UDP_FIELD))
2676 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2678 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2681 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2682 ntohs(ib_spec->tcp_udp.mask.src_port));
2683 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2684 ntohs(ib_spec->tcp_udp.val.src_port));
2686 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2687 ntohs(ib_spec->tcp_udp.mask.dst_port));
2688 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2689 ntohs(ib_spec->tcp_udp.val.dst_port));
2691 case IB_FLOW_SPEC_GRE:
2692 if (ib_spec->gre.mask.c_ks_res0_ver)
2695 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2697 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2700 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2701 ntohs(ib_spec->gre.mask.protocol));
2702 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2703 ntohs(ib_spec->gre.val.protocol));
2705 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2707 &ib_spec->gre.mask.key,
2708 sizeof(ib_spec->gre.mask.key));
2709 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2711 &ib_spec->gre.val.key,
2712 sizeof(ib_spec->gre.val.key));
2714 case IB_FLOW_SPEC_MPLS:
2715 switch (prev_type) {
2716 case IB_FLOW_SPEC_UDP:
2717 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2718 ft_field_support.outer_first_mpls_over_udp),
2719 &ib_spec->mpls.mask.tag))
2722 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2723 outer_first_mpls_over_udp),
2724 &ib_spec->mpls.val.tag,
2725 sizeof(ib_spec->mpls.val.tag));
2726 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2727 outer_first_mpls_over_udp),
2728 &ib_spec->mpls.mask.tag,
2729 sizeof(ib_spec->mpls.mask.tag));
2731 case IB_FLOW_SPEC_GRE:
2732 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2733 ft_field_support.outer_first_mpls_over_gre),
2734 &ib_spec->mpls.mask.tag))
2737 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2738 outer_first_mpls_over_gre),
2739 &ib_spec->mpls.val.tag,
2740 sizeof(ib_spec->mpls.val.tag));
2741 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2742 outer_first_mpls_over_gre),
2743 &ib_spec->mpls.mask.tag,
2744 sizeof(ib_spec->mpls.mask.tag));
2747 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2748 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2749 ft_field_support.inner_first_mpls),
2750 &ib_spec->mpls.mask.tag))
2753 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2755 &ib_spec->mpls.val.tag,
2756 sizeof(ib_spec->mpls.val.tag));
2757 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2759 &ib_spec->mpls.mask.tag,
2760 sizeof(ib_spec->mpls.mask.tag));
2762 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2763 ft_field_support.outer_first_mpls),
2764 &ib_spec->mpls.mask.tag))
2767 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2769 &ib_spec->mpls.val.tag,
2770 sizeof(ib_spec->mpls.val.tag));
2771 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2773 &ib_spec->mpls.mask.tag,
2774 sizeof(ib_spec->mpls.mask.tag));
2778 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2779 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2783 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2784 ntohl(ib_spec->tunnel.mask.tunnel_id));
2785 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2786 ntohl(ib_spec->tunnel.val.tunnel_id));
2788 case IB_FLOW_SPEC_ACTION_TAG:
2789 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2790 LAST_FLOW_TAG_FIELD))
2792 if (ib_spec->flow_tag.tag_id >= BIT(24))
2795 action->flow_tag = ib_spec->flow_tag.tag_id;
2796 action->flags |= FLOW_ACT_HAS_TAG;
2798 case IB_FLOW_SPEC_ACTION_DROP:
2799 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2802 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2804 case IB_FLOW_SPEC_ACTION_HANDLE:
2805 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2809 case IB_FLOW_SPEC_ACTION_COUNT:
2810 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2811 LAST_COUNTERS_FIELD))
2814 /* for now support only one counters spec per flow */
2815 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2818 action->counters = ib_spec->flow_count.counters;
2819 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2828 /* If a flow could catch both multicast and unicast packets,
2829 * it won't fall into the multicast flow steering table and this rule
2830 * could steal other multicast packets.
2832 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2834 union ib_flow_spec *flow_spec;
2836 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2837 ib_attr->num_of_specs < 1)
2840 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2841 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2842 struct ib_flow_spec_ipv4 *ipv4_spec;
2844 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2845 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2851 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2852 struct ib_flow_spec_eth *eth_spec;
2854 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2855 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2856 is_multicast_ether_addr(eth_spec->val.dst_mac);
2868 static enum valid_spec
2869 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2870 const struct mlx5_flow_spec *spec,
2871 const struct mlx5_flow_act *flow_act,
2874 const u32 *match_c = spec->match_criteria;
2876 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2877 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2878 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2879 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2882 * Currently only crypto is supported in egress, when regular egress
2883 * rules would be supported, always return VALID_SPEC_NA.
2886 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2888 return is_crypto && is_ipsec &&
2889 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ?
2890 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2893 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2894 const struct mlx5_flow_spec *spec,
2895 const struct mlx5_flow_act *flow_act,
2898 /* We curretly only support ipsec egress flow */
2899 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2902 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2903 const struct ib_flow_attr *flow_attr,
2906 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2907 int match_ipv = check_inner ?
2908 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2909 ft_field_support.inner_ip_version) :
2910 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2911 ft_field_support.outer_ip_version);
2912 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2913 bool ipv4_spec_valid, ipv6_spec_valid;
2914 unsigned int ip_spec_type = 0;
2915 bool has_ethertype = false;
2916 unsigned int spec_index;
2917 bool mask_valid = true;
2921 /* Validate that ethertype is correct */
2922 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2923 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2924 ib_spec->eth.mask.ether_type) {
2925 mask_valid = (ib_spec->eth.mask.ether_type ==
2927 has_ethertype = true;
2928 eth_type = ntohs(ib_spec->eth.val.ether_type);
2929 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2930 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2931 ip_spec_type = ib_spec->type;
2933 ib_spec = (void *)ib_spec + ib_spec->size;
2936 type_valid = (!has_ethertype) || (!ip_spec_type);
2937 if (!type_valid && mask_valid) {
2938 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2939 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2940 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2941 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2943 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2944 (((eth_type == ETH_P_MPLS_UC) ||
2945 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2951 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2952 const struct ib_flow_attr *flow_attr)
2954 return is_valid_ethertype(mdev, flow_attr, false) &&
2955 is_valid_ethertype(mdev, flow_attr, true);
2958 static void put_flow_table(struct mlx5_ib_dev *dev,
2959 struct mlx5_ib_flow_prio *prio, bool ft_added)
2961 prio->refcount -= !!ft_added;
2962 if (!prio->refcount) {
2963 mlx5_destroy_flow_table(prio->flow_table);
2964 prio->flow_table = NULL;
2968 static void counters_clear_description(struct ib_counters *counters)
2970 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2972 mutex_lock(&mcounters->mcntrs_mutex);
2973 kfree(mcounters->counters_data);
2974 mcounters->counters_data = NULL;
2975 mcounters->cntrs_max_index = 0;
2976 mutex_unlock(&mcounters->mcntrs_mutex);
2979 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2981 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2982 struct mlx5_ib_flow_handler,
2984 struct mlx5_ib_flow_handler *iter, *tmp;
2985 struct mlx5_ib_dev *dev = handler->dev;
2987 mutex_lock(&dev->flow_db->lock);
2989 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2990 mlx5_del_flow_rules(iter->rule);
2991 put_flow_table(dev, iter->prio, true);
2992 list_del(&iter->list);
2996 mlx5_del_flow_rules(handler->rule);
2997 put_flow_table(dev, handler->prio, true);
2998 if (handler->ibcounters &&
2999 atomic_read(&handler->ibcounters->usecnt) == 1)
3000 counters_clear_description(handler->ibcounters);
3002 mutex_unlock(&dev->flow_db->lock);
3003 if (handler->flow_matcher)
3004 atomic_dec(&handler->flow_matcher->usecnt);
3010 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3018 enum flow_table_type {
3023 #define MLX5_FS_MAX_TYPES 6
3024 #define MLX5_FS_MAX_ENTRIES BIT(16)
3026 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3027 struct mlx5_ib_flow_prio *prio,
3029 int num_entries, int num_groups)
3031 struct mlx5_flow_table *ft;
3033 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3038 return ERR_CAST(ft);
3040 prio->flow_table = ft;
3045 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3046 struct ib_flow_attr *flow_attr,
3047 enum flow_table_type ft_type)
3049 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3050 struct mlx5_flow_namespace *ns = NULL;
3051 struct mlx5_ib_flow_prio *prio;
3052 struct mlx5_flow_table *ft;
3058 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3060 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3061 if (ft_type == MLX5_IB_FT_TX)
3063 else if (flow_is_multicast_only(flow_attr) &&
3065 priority = MLX5_IB_FLOW_MCAST_PRIO;
3067 priority = ib_prio_to_core_prio(flow_attr->priority,
3069 ns = mlx5_get_flow_namespace(dev->mdev,
3070 ft_type == MLX5_IB_FT_TX ?
3071 MLX5_FLOW_NAMESPACE_EGRESS :
3072 MLX5_FLOW_NAMESPACE_BYPASS);
3073 num_entries = MLX5_FS_MAX_ENTRIES;
3074 num_groups = MLX5_FS_MAX_TYPES;
3075 prio = &dev->flow_db->prios[priority];
3076 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3077 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3078 ns = mlx5_get_flow_namespace(dev->mdev,
3079 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3080 build_leftovers_ft_param(&priority,
3083 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3084 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3085 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3086 allow_sniffer_and_nic_rx_shared_tir))
3087 return ERR_PTR(-ENOTSUPP);
3089 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3090 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3091 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3093 prio = &dev->flow_db->sniffer[ft_type];
3100 return ERR_PTR(-ENOTSUPP);
3102 if (num_entries > max_table_size)
3103 return ERR_PTR(-ENOMEM);
3105 ft = prio->flow_table;
3107 return _get_prio(ns, prio, priority, num_entries, num_groups);
3112 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3113 struct mlx5_flow_spec *spec,
3116 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3117 spec->match_criteria,
3119 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3123 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3124 ft_field_support.bth_dst_qp)) {
3125 MLX5_SET(fte_match_set_misc,
3126 misc_params_v, bth_dst_qp, underlay_qpn);
3127 MLX5_SET(fte_match_set_misc,
3128 misc_params_c, bth_dst_qp, 0xffffff);
3132 static int read_flow_counters(struct ib_device *ibdev,
3133 struct mlx5_read_counters_attr *read_attr)
3135 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3136 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3138 return mlx5_fc_query(dev->mdev, fc,
3139 &read_attr->out[IB_COUNTER_PACKETS],
3140 &read_attr->out[IB_COUNTER_BYTES]);
3143 /* flow counters currently expose two counters packets and bytes */
3144 #define FLOW_COUNTERS_NUM 2
3145 static int counters_set_description(struct ib_counters *counters,
3146 enum mlx5_ib_counters_type counters_type,
3147 struct mlx5_ib_flow_counters_desc *desc_data,
3150 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3151 u32 cntrs_max_index = 0;
3154 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3157 /* init the fields for the object */
3158 mcounters->type = counters_type;
3159 mcounters->read_counters = read_flow_counters;
3160 mcounters->counters_num = FLOW_COUNTERS_NUM;
3161 mcounters->ncounters = ncounters;
3162 /* each counter entry have both description and index pair */
3163 for (i = 0; i < ncounters; i++) {
3164 if (desc_data[i].description > IB_COUNTER_BYTES)
3167 if (cntrs_max_index <= desc_data[i].index)
3168 cntrs_max_index = desc_data[i].index + 1;
3171 mutex_lock(&mcounters->mcntrs_mutex);
3172 mcounters->counters_data = desc_data;
3173 mcounters->cntrs_max_index = cntrs_max_index;
3174 mutex_unlock(&mcounters->mcntrs_mutex);
3179 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3180 static int flow_counters_set_data(struct ib_counters *ibcounters,
3181 struct mlx5_ib_create_flow *ucmd)
3183 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3184 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3185 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3186 bool hw_hndl = false;
3189 if (ucmd && ucmd->ncounters_data != 0) {
3190 cntrs_data = ucmd->data;
3191 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3194 desc_data = kcalloc(cntrs_data->ncounters,
3200 if (copy_from_user(desc_data,
3201 u64_to_user_ptr(cntrs_data->counters_data),
3202 sizeof(*desc_data) * cntrs_data->ncounters)) {
3208 if (!mcounters->hw_cntrs_hndl) {
3209 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3210 to_mdev(ibcounters->device)->mdev, false);
3211 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3212 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3219 /* counters already bound to at least one flow */
3220 if (mcounters->cntrs_max_index) {
3225 ret = counters_set_description(ibcounters,
3226 MLX5_IB_COUNTERS_FLOW,
3228 cntrs_data->ncounters);
3232 } else if (!mcounters->cntrs_max_index) {
3233 /* counters not bound yet, must have udata passed */
3242 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3243 mcounters->hw_cntrs_hndl);
3244 mcounters->hw_cntrs_hndl = NULL;
3251 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3252 struct mlx5_ib_flow_prio *ft_prio,
3253 const struct ib_flow_attr *flow_attr,
3254 struct mlx5_flow_destination *dst,
3256 struct mlx5_ib_create_flow *ucmd)
3258 struct mlx5_flow_table *ft = ft_prio->flow_table;
3259 struct mlx5_ib_flow_handler *handler;
3260 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3261 struct mlx5_flow_spec *spec;
3262 struct mlx5_flow_destination dest_arr[2] = {};
3263 struct mlx5_flow_destination *rule_dst = dest_arr;
3264 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3265 unsigned int spec_index;
3269 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3271 if (!is_valid_attr(dev->mdev, flow_attr))
3272 return ERR_PTR(-EINVAL);
3274 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3275 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3276 if (!handler || !spec) {
3281 INIT_LIST_HEAD(&handler->list);
3283 memcpy(&dest_arr[0], dst, sizeof(*dst));
3287 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3288 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3290 ib_flow, flow_attr, &flow_act,
3295 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3296 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3299 if (!flow_is_multicast_only(flow_attr))
3300 set_underlay_qp(dev, spec, underlay_qpn);
3305 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3307 MLX5_SET(fte_match_set_misc, misc, source_port,
3309 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3311 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3314 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3317 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3322 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3323 struct mlx5_ib_mcounters *mcounters;
3325 err = flow_counters_set_data(flow_act.counters, ucmd);
3329 mcounters = to_mcounters(flow_act.counters);
3330 handler->ibcounters = flow_act.counters;
3331 dest_arr[dest_num].type =
3332 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3333 dest_arr[dest_num].counter_id =
3334 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3338 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3339 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3345 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3348 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3349 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3352 if ((flow_act.flags & FLOW_ACT_HAS_TAG) &&
3353 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3354 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3355 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3356 flow_act.flow_tag, flow_attr->type);
3360 handler->rule = mlx5_add_flow_rules(ft, spec,
3362 rule_dst, dest_num);
3364 if (IS_ERR(handler->rule)) {
3365 err = PTR_ERR(handler->rule);
3369 ft_prio->refcount++;
3370 handler->prio = ft_prio;
3373 ft_prio->flow_table = ft;
3375 if (err && handler) {
3376 if (handler->ibcounters &&
3377 atomic_read(&handler->ibcounters->usecnt) == 1)
3378 counters_clear_description(handler->ibcounters);
3382 return err ? ERR_PTR(err) : handler;
3385 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3386 struct mlx5_ib_flow_prio *ft_prio,
3387 const struct ib_flow_attr *flow_attr,
3388 struct mlx5_flow_destination *dst)
3390 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3393 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3394 struct mlx5_ib_flow_prio *ft_prio,
3395 struct ib_flow_attr *flow_attr,
3396 struct mlx5_flow_destination *dst)
3398 struct mlx5_ib_flow_handler *handler_dst = NULL;
3399 struct mlx5_ib_flow_handler *handler = NULL;
3401 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3402 if (!IS_ERR(handler)) {
3403 handler_dst = create_flow_rule(dev, ft_prio,
3405 if (IS_ERR(handler_dst)) {
3406 mlx5_del_flow_rules(handler->rule);
3407 ft_prio->refcount--;
3409 handler = handler_dst;
3411 list_add(&handler_dst->list, &handler->list);
3422 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3423 struct mlx5_ib_flow_prio *ft_prio,
3424 struct ib_flow_attr *flow_attr,
3425 struct mlx5_flow_destination *dst)
3427 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3428 struct mlx5_ib_flow_handler *handler = NULL;
3431 struct ib_flow_attr flow_attr;
3432 struct ib_flow_spec_eth eth_flow;
3433 } leftovers_specs[] = {
3437 .size = sizeof(leftovers_specs[0])
3440 .type = IB_FLOW_SPEC_ETH,
3441 .size = sizeof(struct ib_flow_spec_eth),
3442 .mask = {.dst_mac = {0x1} },
3443 .val = {.dst_mac = {0x1} }
3449 .size = sizeof(leftovers_specs[0])
3452 .type = IB_FLOW_SPEC_ETH,
3453 .size = sizeof(struct ib_flow_spec_eth),
3454 .mask = {.dst_mac = {0x1} },
3455 .val = {.dst_mac = {} }
3460 handler = create_flow_rule(dev, ft_prio,
3461 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3463 if (!IS_ERR(handler) &&
3464 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3465 handler_ucast = create_flow_rule(dev, ft_prio,
3466 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3468 if (IS_ERR(handler_ucast)) {
3469 mlx5_del_flow_rules(handler->rule);
3470 ft_prio->refcount--;
3472 handler = handler_ucast;
3474 list_add(&handler_ucast->list, &handler->list);
3481 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3482 struct mlx5_ib_flow_prio *ft_rx,
3483 struct mlx5_ib_flow_prio *ft_tx,
3484 struct mlx5_flow_destination *dst)
3486 struct mlx5_ib_flow_handler *handler_rx;
3487 struct mlx5_ib_flow_handler *handler_tx;
3489 static const struct ib_flow_attr flow_attr = {
3491 .size = sizeof(flow_attr)
3494 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3495 if (IS_ERR(handler_rx)) {
3496 err = PTR_ERR(handler_rx);
3500 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3501 if (IS_ERR(handler_tx)) {
3502 err = PTR_ERR(handler_tx);
3506 list_add(&handler_tx->list, &handler_rx->list);
3511 mlx5_del_flow_rules(handler_rx->rule);
3515 return ERR_PTR(err);
3518 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3519 struct ib_flow_attr *flow_attr,
3521 struct ib_udata *udata)
3523 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3524 struct mlx5_ib_qp *mqp = to_mqp(qp);
3525 struct mlx5_ib_flow_handler *handler = NULL;
3526 struct mlx5_flow_destination *dst = NULL;
3527 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3528 struct mlx5_ib_flow_prio *ft_prio;
3529 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3530 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3531 size_t min_ucmd_sz, required_ucmd_sz;
3535 if (udata && udata->inlen) {
3536 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3537 sizeof(ucmd_hdr.reserved);
3538 if (udata->inlen < min_ucmd_sz)
3539 return ERR_PTR(-EOPNOTSUPP);
3541 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3543 return ERR_PTR(err);
3545 /* currently supports only one counters data */
3546 if (ucmd_hdr.ncounters_data > 1)
3547 return ERR_PTR(-EINVAL);
3549 required_ucmd_sz = min_ucmd_sz +
3550 sizeof(struct mlx5_ib_flow_counters_data) *
3551 ucmd_hdr.ncounters_data;
3552 if (udata->inlen > required_ucmd_sz &&
3553 !ib_is_udata_cleared(udata, required_ucmd_sz,
3554 udata->inlen - required_ucmd_sz))
3555 return ERR_PTR(-EOPNOTSUPP);
3557 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3559 return ERR_PTR(-ENOMEM);
3561 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3566 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3571 if (domain != IB_FLOW_DOMAIN_USER ||
3572 flow_attr->port > dev->num_ports ||
3573 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3574 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3580 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3581 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3586 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3592 mutex_lock(&dev->flow_db->lock);
3594 ft_prio = get_flow_table(dev, flow_attr,
3595 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3596 if (IS_ERR(ft_prio)) {
3597 err = PTR_ERR(ft_prio);
3600 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3601 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3602 if (IS_ERR(ft_prio_tx)) {
3603 err = PTR_ERR(ft_prio_tx);
3610 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3612 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3613 if (mqp->flags & MLX5_IB_QP_RSS)
3614 dst->tir_num = mqp->rss_qp.tirn;
3616 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3619 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3620 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3621 handler = create_dont_trap_rule(dev, ft_prio,
3624 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3625 mqp->underlay_qpn : 0;
3626 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3627 dst, underlay_qpn, ucmd);
3629 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3630 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3631 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3633 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3634 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3640 if (IS_ERR(handler)) {
3641 err = PTR_ERR(handler);
3646 mutex_unlock(&dev->flow_db->lock);
3650 return &handler->ibflow;
3653 put_flow_table(dev, ft_prio, false);
3655 put_flow_table(dev, ft_prio_tx, false);
3657 mutex_unlock(&dev->flow_db->lock);
3661 return ERR_PTR(err);
3664 static struct mlx5_ib_flow_prio *_get_flow_table(struct mlx5_ib_dev *dev,
3665 int priority, bool mcast)
3668 struct mlx5_flow_namespace *ns = NULL;
3669 struct mlx5_ib_flow_prio *prio;
3671 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3673 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3674 return ERR_PTR(-ENOMEM);
3677 priority = MLX5_IB_FLOW_MCAST_PRIO;
3679 priority = ib_prio_to_core_prio(priority, false);
3681 ns = mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS);
3683 return ERR_PTR(-ENOTSUPP);
3685 prio = &dev->flow_db->prios[priority];
3687 if (prio->flow_table)
3690 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3694 static struct mlx5_ib_flow_handler *
3695 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3696 struct mlx5_ib_flow_prio *ft_prio,
3697 struct mlx5_flow_destination *dst,
3698 struct mlx5_ib_flow_matcher *fs_matcher,
3699 void *cmd_in, int inlen)
3701 struct mlx5_ib_flow_handler *handler;
3702 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3703 struct mlx5_flow_spec *spec;
3704 struct mlx5_flow_table *ft = ft_prio->flow_table;
3707 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3708 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3709 if (!handler || !spec) {
3714 INIT_LIST_HEAD(&handler->list);
3716 memcpy(spec->match_value, cmd_in, inlen);
3717 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3718 fs_matcher->mask_len);
3719 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3721 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3722 handler->rule = mlx5_add_flow_rules(ft, spec,
3725 if (IS_ERR(handler->rule)) {
3726 err = PTR_ERR(handler->rule);
3730 ft_prio->refcount++;
3731 handler->prio = ft_prio;
3733 ft_prio->flow_table = ft;
3739 return err ? ERR_PTR(err) : handler;
3742 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3746 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3747 void *dmac, *dmac_mask;
3748 void *ipv4, *ipv4_mask;
3750 if (!(fs_matcher->match_criteria_enable &
3751 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3754 match_c = fs_matcher->matcher_mask.match_params;
3755 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3757 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3760 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3762 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3765 if (is_multicast_ether_addr(dmac) &&
3766 is_multicast_ether_addr(dmac_mask))
3769 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3770 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3772 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3773 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3775 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3776 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3782 struct mlx5_ib_flow_handler *
3783 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3784 struct mlx5_ib_flow_matcher *fs_matcher,
3785 void *cmd_in, int inlen, int dest_id,
3788 struct mlx5_flow_destination *dst;
3789 struct mlx5_ib_flow_prio *ft_prio;
3790 int priority = fs_matcher->priority;
3791 struct mlx5_ib_flow_handler *handler;
3795 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3796 return ERR_PTR(-EOPNOTSUPP);
3798 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3799 return ERR_PTR(-ENOMEM);
3801 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3803 return ERR_PTR(-ENOMEM);
3805 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3806 mutex_lock(&dev->flow_db->lock);
3808 ft_prio = _get_flow_table(dev, priority, mcast);
3809 if (IS_ERR(ft_prio)) {
3810 err = PTR_ERR(ft_prio);
3814 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3815 dst->type = dest_type;
3816 dst->tir_num = dest_id;
3818 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3819 dst->ft_num = dest_id;
3822 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, cmd_in,
3825 if (IS_ERR(handler)) {
3826 err = PTR_ERR(handler);
3830 mutex_unlock(&dev->flow_db->lock);
3831 atomic_inc(&fs_matcher->usecnt);
3832 handler->flow_matcher = fs_matcher;
3839 put_flow_table(dev, ft_prio, false);
3841 mutex_unlock(&dev->flow_db->lock);
3844 return ERR_PTR(err);
3847 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3851 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3852 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3857 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3858 static struct ib_flow_action *
3859 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3860 const struct ib_flow_action_attrs_esp *attr,
3861 struct uverbs_attr_bundle *attrs)
3863 struct mlx5_ib_dev *mdev = to_mdev(device);
3864 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3865 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3866 struct mlx5_ib_flow_action *action;
3871 err = uverbs_get_flags64(
3872 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3873 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3875 return ERR_PTR(err);
3877 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3879 /* We current only support a subset of the standard features. Only a
3880 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3881 * (with overlap). Full offload mode isn't supported.
3883 if (!attr->keymat || attr->replay || attr->encap ||
3884 attr->spi || attr->seq || attr->tfc_pad ||
3885 attr->hard_limit_pkts ||
3886 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3887 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3888 return ERR_PTR(-EOPNOTSUPP);
3890 if (attr->keymat->protocol !=
3891 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3892 return ERR_PTR(-EOPNOTSUPP);
3894 aes_gcm = &attr->keymat->keymat.aes_gcm;
3896 if (aes_gcm->icv_len != 16 ||
3897 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3898 return ERR_PTR(-EOPNOTSUPP);
3900 action = kmalloc(sizeof(*action), GFP_KERNEL);
3902 return ERR_PTR(-ENOMEM);
3904 action->esp_aes_gcm.ib_flags = attr->flags;
3905 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3906 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3907 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3908 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3909 sizeof(accel_attrs.keymat.aes_gcm.salt));
3910 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3911 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3912 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3913 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3914 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3916 accel_attrs.esn = attr->esn;
3917 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3918 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3919 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3920 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3922 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3923 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3925 action->esp_aes_gcm.ctx =
3926 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3927 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3928 err = PTR_ERR(action->esp_aes_gcm.ctx);
3932 action->esp_aes_gcm.ib_flags = attr->flags;
3934 return &action->ib_action;
3938 return ERR_PTR(err);
3942 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3943 const struct ib_flow_action_attrs_esp *attr,
3944 struct uverbs_attr_bundle *attrs)
3946 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3947 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3950 if (attr->keymat || attr->replay || attr->encap ||
3951 attr->spi || attr->seq || attr->tfc_pad ||
3952 attr->hard_limit_pkts ||
3953 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3954 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3955 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3958 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3961 if (!(maction->esp_aes_gcm.ib_flags &
3962 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3963 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3964 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3967 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3968 sizeof(accel_attrs));
3970 accel_attrs.esn = attr->esn;
3971 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3972 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3974 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3976 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3981 maction->esp_aes_gcm.ib_flags &=
3982 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3983 maction->esp_aes_gcm.ib_flags |=
3984 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3989 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3991 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3993 switch (action->type) {
3994 case IB_FLOW_ACTION_ESP:
3996 * We only support aes_gcm by now, so we implicitly know this is
3997 * the underline crypto.
3999 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4010 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4012 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4013 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4016 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4017 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4021 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
4023 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4024 ibqp->qp_num, gid->raw);
4029 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4031 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4034 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
4036 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4037 ibqp->qp_num, gid->raw);
4042 static int init_node_data(struct mlx5_ib_dev *dev)
4046 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4050 dev->mdev->rev_id = dev->mdev->pdev->revision;
4052 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4055 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
4058 struct mlx5_ib_dev *dev =
4059 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4061 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4064 static ssize_t show_reg_pages(struct device *device,
4065 struct device_attribute *attr, char *buf)
4067 struct mlx5_ib_dev *dev =
4068 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4070 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4073 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
4076 struct mlx5_ib_dev *dev =
4077 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4078 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4081 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
4084 struct mlx5_ib_dev *dev =
4085 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4086 return sprintf(buf, "%x\n", dev->mdev->rev_id);
4089 static ssize_t show_board(struct device *device, struct device_attribute *attr,
4092 struct mlx5_ib_dev *dev =
4093 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4094 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4095 dev->mdev->board_id);
4098 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
4099 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
4100 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
4101 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
4102 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
4104 static struct device_attribute *mlx5_class_attributes[] = {
4109 &dev_attr_reg_pages,
4112 static void pkey_change_handler(struct work_struct *work)
4114 struct mlx5_ib_port_resources *ports =
4115 container_of(work, struct mlx5_ib_port_resources,
4118 mutex_lock(&ports->devr->mutex);
4119 mlx5_ib_gsi_pkey_change(ports->gsi);
4120 mutex_unlock(&ports->devr->mutex);
4123 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4125 struct mlx5_ib_qp *mqp;
4126 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4127 struct mlx5_core_cq *mcq;
4128 struct list_head cq_armed_list;
4129 unsigned long flags_qp;
4130 unsigned long flags_cq;
4131 unsigned long flags;
4133 INIT_LIST_HEAD(&cq_armed_list);
4135 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4136 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4137 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4138 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4139 if (mqp->sq.tail != mqp->sq.head) {
4140 send_mcq = to_mcq(mqp->ibqp.send_cq);
4141 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4142 if (send_mcq->mcq.comp &&
4143 mqp->ibqp.send_cq->comp_handler) {
4144 if (!send_mcq->mcq.reset_notify_added) {
4145 send_mcq->mcq.reset_notify_added = 1;
4146 list_add_tail(&send_mcq->mcq.reset_notify,
4150 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4152 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4153 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4154 /* no handling is needed for SRQ */
4155 if (!mqp->ibqp.srq) {
4156 if (mqp->rq.tail != mqp->rq.head) {
4157 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4158 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4159 if (recv_mcq->mcq.comp &&
4160 mqp->ibqp.recv_cq->comp_handler) {
4161 if (!recv_mcq->mcq.reset_notify_added) {
4162 recv_mcq->mcq.reset_notify_added = 1;
4163 list_add_tail(&recv_mcq->mcq.reset_notify,
4167 spin_unlock_irqrestore(&recv_mcq->lock,
4171 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4173 /*At that point all inflight post send were put to be executed as of we
4174 * lock/unlock above locks Now need to arm all involved CQs.
4176 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4179 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4182 static void delay_drop_handler(struct work_struct *work)
4185 struct mlx5_ib_delay_drop *delay_drop =
4186 container_of(work, struct mlx5_ib_delay_drop,
4189 atomic_inc(&delay_drop->events_cnt);
4191 mutex_lock(&delay_drop->lock);
4192 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4193 delay_drop->timeout);
4195 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4196 delay_drop->timeout);
4197 delay_drop->activate = false;
4199 mutex_unlock(&delay_drop->lock);
4202 static void mlx5_ib_handle_event(struct work_struct *_work)
4204 struct mlx5_ib_event_work *work =
4205 container_of(_work, struct mlx5_ib_event_work, work);
4206 struct mlx5_ib_dev *ibdev;
4207 struct ib_event ibev;
4209 u8 port = (u8)work->param;
4211 if (mlx5_core_is_mp_slave(work->dev)) {
4212 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4216 ibdev = work->context;
4219 switch (work->event) {
4220 case MLX5_DEV_EVENT_SYS_ERROR:
4221 ibev.event = IB_EVENT_DEVICE_FATAL;
4222 mlx5_ib_handle_internal_error(ibdev);
4226 case MLX5_DEV_EVENT_PORT_UP:
4227 case MLX5_DEV_EVENT_PORT_DOWN:
4228 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4229 /* In RoCE, port up/down events are handled in
4230 * mlx5_netdev_event().
4232 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4233 IB_LINK_LAYER_ETHERNET)
4236 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
4237 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4240 case MLX5_DEV_EVENT_LID_CHANGE:
4241 ibev.event = IB_EVENT_LID_CHANGE;
4244 case MLX5_DEV_EVENT_PKEY_CHANGE:
4245 ibev.event = IB_EVENT_PKEY_CHANGE;
4246 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4249 case MLX5_DEV_EVENT_GUID_CHANGE:
4250 ibev.event = IB_EVENT_GID_CHANGE;
4253 case MLX5_DEV_EVENT_CLIENT_REREG:
4254 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4256 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4257 schedule_work(&ibdev->delay_drop.delay_drop_work);
4263 ibev.device = &ibdev->ib_dev;
4264 ibev.element.port_num = port;
4266 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
4267 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
4271 if (ibdev->ib_active)
4272 ib_dispatch_event(&ibev);
4275 ibdev->ib_active = false;
4280 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4281 enum mlx5_dev_event event, unsigned long param)
4283 struct mlx5_ib_event_work *work;
4285 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4289 INIT_WORK(&work->work, mlx5_ib_handle_event);
4291 work->param = param;
4292 work->context = context;
4293 work->event = event;
4295 queue_work(mlx5_ib_event_wq, &work->work);
4298 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4300 struct mlx5_hca_vport_context vport_ctx;
4304 for (port = 1; port <= dev->num_ports; port++) {
4305 dev->mdev->port_caps[port - 1].has_smi = false;
4306 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4307 MLX5_CAP_PORT_TYPE_IB) {
4308 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4309 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4313 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4317 dev->mdev->port_caps[port - 1].has_smi =
4320 dev->mdev->port_caps[port - 1].has_smi = true;
4327 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4331 for (port = 1; port <= dev->num_ports; port++)
4332 mlx5_query_ext_port_caps(dev, port);
4335 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4337 struct ib_device_attr *dprops = NULL;
4338 struct ib_port_attr *pprops = NULL;
4340 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4342 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4346 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4350 err = set_has_smi_cap(dev);
4354 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4356 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4360 memset(pprops, 0, sizeof(*pprops));
4361 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4363 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4368 dev->mdev->port_caps[port - 1].pkey_table_len =
4370 dev->mdev->port_caps[port - 1].gid_table_len =
4371 pprops->gid_tbl_len;
4372 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4373 port, dprops->max_pkeys, pprops->gid_tbl_len);
4382 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4386 err = mlx5_mr_cache_cleanup(dev);
4388 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4391 mlx5_ib_destroy_qp(dev->umrc.qp);
4393 ib_free_cq(dev->umrc.cq);
4395 ib_dealloc_pd(dev->umrc.pd);
4402 static int create_umr_res(struct mlx5_ib_dev *dev)
4404 struct ib_qp_init_attr *init_attr = NULL;
4405 struct ib_qp_attr *attr = NULL;
4411 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4412 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4413 if (!attr || !init_attr) {
4418 pd = ib_alloc_pd(&dev->ib_dev, 0);
4420 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4425 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4427 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4432 init_attr->send_cq = cq;
4433 init_attr->recv_cq = cq;
4434 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4435 init_attr->cap.max_send_wr = MAX_UMR_WR;
4436 init_attr->cap.max_send_sge = 1;
4437 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4438 init_attr->port_num = 1;
4439 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4441 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4445 qp->device = &dev->ib_dev;
4448 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4449 qp->send_cq = init_attr->send_cq;
4450 qp->recv_cq = init_attr->recv_cq;
4452 attr->qp_state = IB_QPS_INIT;
4454 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4457 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4461 memset(attr, 0, sizeof(*attr));
4462 attr->qp_state = IB_QPS_RTR;
4463 attr->path_mtu = IB_MTU_256;
4465 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4467 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4471 memset(attr, 0, sizeof(*attr));
4472 attr->qp_state = IB_QPS_RTS;
4473 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4475 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4483 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4484 ret = mlx5_mr_cache_init(dev);
4486 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4496 mlx5_ib_destroy_qp(qp);
4497 dev->umrc.qp = NULL;
4501 dev->umrc.cq = NULL;
4505 dev->umrc.pd = NULL;
4513 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4515 switch (umr_fence_cap) {
4516 case MLX5_CAP_UMR_FENCE_NONE:
4517 return MLX5_FENCE_MODE_NONE;
4518 case MLX5_CAP_UMR_FENCE_SMALL:
4519 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4521 return MLX5_FENCE_MODE_STRONG_ORDERING;
4525 static int create_dev_resources(struct mlx5_ib_resources *devr)
4527 struct ib_srq_init_attr attr;
4528 struct mlx5_ib_dev *dev;
4529 struct ib_cq_init_attr cq_attr = {.cqe = 1};
4533 dev = container_of(devr, struct mlx5_ib_dev, devr);
4535 mutex_init(&devr->mutex);
4537 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4538 if (IS_ERR(devr->p0)) {
4539 ret = PTR_ERR(devr->p0);
4542 devr->p0->device = &dev->ib_dev;
4543 devr->p0->uobject = NULL;
4544 atomic_set(&devr->p0->usecnt, 0);
4546 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4547 if (IS_ERR(devr->c0)) {
4548 ret = PTR_ERR(devr->c0);
4551 devr->c0->device = &dev->ib_dev;
4552 devr->c0->uobject = NULL;
4553 devr->c0->comp_handler = NULL;
4554 devr->c0->event_handler = NULL;
4555 devr->c0->cq_context = NULL;
4556 atomic_set(&devr->c0->usecnt, 0);
4558 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4559 if (IS_ERR(devr->x0)) {
4560 ret = PTR_ERR(devr->x0);
4563 devr->x0->device = &dev->ib_dev;
4564 devr->x0->inode = NULL;
4565 atomic_set(&devr->x0->usecnt, 0);
4566 mutex_init(&devr->x0->tgt_qp_mutex);
4567 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4569 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4570 if (IS_ERR(devr->x1)) {
4571 ret = PTR_ERR(devr->x1);
4574 devr->x1->device = &dev->ib_dev;
4575 devr->x1->inode = NULL;
4576 atomic_set(&devr->x1->usecnt, 0);
4577 mutex_init(&devr->x1->tgt_qp_mutex);
4578 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4580 memset(&attr, 0, sizeof(attr));
4581 attr.attr.max_sge = 1;
4582 attr.attr.max_wr = 1;
4583 attr.srq_type = IB_SRQT_XRC;
4584 attr.ext.cq = devr->c0;
4585 attr.ext.xrc.xrcd = devr->x0;
4587 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4588 if (IS_ERR(devr->s0)) {
4589 ret = PTR_ERR(devr->s0);
4592 devr->s0->device = &dev->ib_dev;
4593 devr->s0->pd = devr->p0;
4594 devr->s0->uobject = NULL;
4595 devr->s0->event_handler = NULL;
4596 devr->s0->srq_context = NULL;
4597 devr->s0->srq_type = IB_SRQT_XRC;
4598 devr->s0->ext.xrc.xrcd = devr->x0;
4599 devr->s0->ext.cq = devr->c0;
4600 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4601 atomic_inc(&devr->s0->ext.cq->usecnt);
4602 atomic_inc(&devr->p0->usecnt);
4603 atomic_set(&devr->s0->usecnt, 0);
4605 memset(&attr, 0, sizeof(attr));
4606 attr.attr.max_sge = 1;
4607 attr.attr.max_wr = 1;
4608 attr.srq_type = IB_SRQT_BASIC;
4609 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4610 if (IS_ERR(devr->s1)) {
4611 ret = PTR_ERR(devr->s1);
4614 devr->s1->device = &dev->ib_dev;
4615 devr->s1->pd = devr->p0;
4616 devr->s1->uobject = NULL;
4617 devr->s1->event_handler = NULL;
4618 devr->s1->srq_context = NULL;
4619 devr->s1->srq_type = IB_SRQT_BASIC;
4620 devr->s1->ext.cq = devr->c0;
4621 atomic_inc(&devr->p0->usecnt);
4622 atomic_set(&devr->s1->usecnt, 0);
4624 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4625 INIT_WORK(&devr->ports[port].pkey_change_work,
4626 pkey_change_handler);
4627 devr->ports[port].devr = devr;
4633 mlx5_ib_destroy_srq(devr->s0);
4635 mlx5_ib_dealloc_xrcd(devr->x1);
4637 mlx5_ib_dealloc_xrcd(devr->x0);
4639 mlx5_ib_destroy_cq(devr->c0);
4641 mlx5_ib_dealloc_pd(devr->p0);
4646 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4648 struct mlx5_ib_dev *dev =
4649 container_of(devr, struct mlx5_ib_dev, devr);
4652 mlx5_ib_destroy_srq(devr->s1);
4653 mlx5_ib_destroy_srq(devr->s0);
4654 mlx5_ib_dealloc_xrcd(devr->x0);
4655 mlx5_ib_dealloc_xrcd(devr->x1);
4656 mlx5_ib_destroy_cq(devr->c0);
4657 mlx5_ib_dealloc_pd(devr->p0);
4659 /* Make sure no change P_Key work items are still executing */
4660 for (port = 0; port < dev->num_ports; ++port)
4661 cancel_work_sync(&devr->ports[port].pkey_change_work);
4664 static u32 get_core_cap_flags(struct ib_device *ibdev,
4665 struct mlx5_hca_vport_context *rep)
4667 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4668 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4669 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4670 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4671 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4674 if (rep->grh_required)
4675 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4677 if (ll == IB_LINK_LAYER_INFINIBAND)
4678 return ret | RDMA_CORE_PORT_IBA_IB;
4681 ret |= RDMA_CORE_PORT_RAW_PACKET;
4683 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4686 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4689 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4690 ret |= RDMA_CORE_PORT_IBA_ROCE;
4692 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4693 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4698 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4699 struct ib_port_immutable *immutable)
4701 struct ib_port_attr attr;
4702 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4703 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4704 struct mlx5_hca_vport_context rep = {0};
4707 err = ib_query_port(ibdev, port_num, &attr);
4711 if (ll == IB_LINK_LAYER_INFINIBAND) {
4712 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4718 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4719 immutable->gid_tbl_len = attr.gid_tbl_len;
4720 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
4721 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4722 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4727 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4728 struct ib_port_immutable *immutable)
4730 struct ib_port_attr attr;
4733 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4735 err = ib_query_port(ibdev, port_num, &attr);
4739 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4740 immutable->gid_tbl_len = attr.gid_tbl_len;
4741 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4746 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4748 struct mlx5_ib_dev *dev =
4749 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4750 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4751 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4752 fw_rev_sub(dev->mdev));
4755 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4757 struct mlx5_core_dev *mdev = dev->mdev;
4758 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4759 MLX5_FLOW_NAMESPACE_LAG);
4760 struct mlx5_flow_table *ft;
4763 if (!ns || !mlx5_lag_is_active(mdev))
4766 err = mlx5_cmd_create_vport_lag(mdev);
4770 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4773 goto err_destroy_vport_lag;
4776 dev->flow_db->lag_demux_ft = ft;
4779 err_destroy_vport_lag:
4780 mlx5_cmd_destroy_vport_lag(mdev);
4784 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4786 struct mlx5_core_dev *mdev = dev->mdev;
4788 if (dev->flow_db->lag_demux_ft) {
4789 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4790 dev->flow_db->lag_demux_ft = NULL;
4792 mlx5_cmd_destroy_vport_lag(mdev);
4796 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4800 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4801 err = register_netdevice_notifier(&dev->roce[port_num].nb);
4803 dev->roce[port_num].nb.notifier_call = NULL;
4810 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4812 if (dev->roce[port_num].nb.notifier_call) {
4813 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4814 dev->roce[port_num].nb.notifier_call = NULL;
4818 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
4822 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4823 err = mlx5_nic_vport_enable_roce(dev->mdev);
4828 err = mlx5_eth_lag_init(dev);
4830 goto err_disable_roce;
4835 if (MLX5_CAP_GEN(dev->mdev, roce))
4836 mlx5_nic_vport_disable_roce(dev->mdev);
4841 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4843 mlx5_eth_lag_cleanup(dev);
4844 if (MLX5_CAP_GEN(dev->mdev, roce))
4845 mlx5_nic_vport_disable_roce(dev->mdev);
4848 struct mlx5_ib_counter {
4853 #define INIT_Q_COUNTER(_name) \
4854 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4856 static const struct mlx5_ib_counter basic_q_cnts[] = {
4857 INIT_Q_COUNTER(rx_write_requests),
4858 INIT_Q_COUNTER(rx_read_requests),
4859 INIT_Q_COUNTER(rx_atomic_requests),
4860 INIT_Q_COUNTER(out_of_buffer),
4863 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4864 INIT_Q_COUNTER(out_of_sequence),
4867 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4868 INIT_Q_COUNTER(duplicate_request),
4869 INIT_Q_COUNTER(rnr_nak_retry_err),
4870 INIT_Q_COUNTER(packet_seq_err),
4871 INIT_Q_COUNTER(implied_nak_seq_err),
4872 INIT_Q_COUNTER(local_ack_timeout_err),
4875 #define INIT_CONG_COUNTER(_name) \
4876 { .name = #_name, .offset = \
4877 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4879 static const struct mlx5_ib_counter cong_cnts[] = {
4880 INIT_CONG_COUNTER(rp_cnp_ignored),
4881 INIT_CONG_COUNTER(rp_cnp_handled),
4882 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4883 INIT_CONG_COUNTER(np_cnp_sent),
4886 static const struct mlx5_ib_counter extended_err_cnts[] = {
4887 INIT_Q_COUNTER(resp_local_length_error),
4888 INIT_Q_COUNTER(resp_cqe_error),
4889 INIT_Q_COUNTER(req_cqe_error),
4890 INIT_Q_COUNTER(req_remote_invalid_request),
4891 INIT_Q_COUNTER(req_remote_access_errors),
4892 INIT_Q_COUNTER(resp_remote_access_errors),
4893 INIT_Q_COUNTER(resp_cqe_flush_error),
4894 INIT_Q_COUNTER(req_cqe_flush_error),
4897 #define INIT_EXT_PPCNT_COUNTER(_name) \
4898 { .name = #_name, .offset = \
4899 MLX5_BYTE_OFF(ppcnt_reg, \
4900 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4902 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4903 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4906 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4910 for (i = 0; i < dev->num_ports; i++) {
4911 if (dev->port[i].cnts.set_id_valid)
4912 mlx5_core_dealloc_q_counter(dev->mdev,
4913 dev->port[i].cnts.set_id);
4914 kfree(dev->port[i].cnts.names);
4915 kfree(dev->port[i].cnts.offsets);
4919 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4920 struct mlx5_ib_counters *cnts)
4924 num_counters = ARRAY_SIZE(basic_q_cnts);
4926 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4927 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4929 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4930 num_counters += ARRAY_SIZE(retrans_q_cnts);
4932 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4933 num_counters += ARRAY_SIZE(extended_err_cnts);
4935 cnts->num_q_counters = num_counters;
4937 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4938 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4939 num_counters += ARRAY_SIZE(cong_cnts);
4941 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4942 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4943 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4945 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4949 cnts->offsets = kcalloc(num_counters,
4950 sizeof(cnts->offsets), GFP_KERNEL);
4962 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4969 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4970 names[j] = basic_q_cnts[i].name;
4971 offsets[j] = basic_q_cnts[i].offset;
4974 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4975 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4976 names[j] = out_of_seq_q_cnts[i].name;
4977 offsets[j] = out_of_seq_q_cnts[i].offset;
4981 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4982 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4983 names[j] = retrans_q_cnts[i].name;
4984 offsets[j] = retrans_q_cnts[i].offset;
4988 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4989 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4990 names[j] = extended_err_cnts[i].name;
4991 offsets[j] = extended_err_cnts[i].offset;
4995 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4996 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4997 names[j] = cong_cnts[i].name;
4998 offsets[j] = cong_cnts[i].offset;
5002 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5003 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5004 names[j] = ext_ppcnt_cnts[i].name;
5005 offsets[j] = ext_ppcnt_cnts[i].offset;
5010 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5015 for (i = 0; i < dev->num_ports; i++) {
5016 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5020 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5021 dev->port[i].cnts.offsets);
5023 err = mlx5_core_alloc_q_counter(dev->mdev,
5024 &dev->port[i].cnts.set_id);
5027 "couldn't allocate queue counter for port %d, err %d\n",
5031 dev->port[i].cnts.set_id_valid = true;
5037 mlx5_ib_dealloc_counters(dev);
5041 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5044 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5045 struct mlx5_ib_port *port = &dev->port[port_num - 1];
5047 /* We support only per port stats */
5051 return rdma_alloc_hw_stats_struct(port->cnts.names,
5052 port->cnts.num_q_counters +
5053 port->cnts.num_cong_counters +
5054 port->cnts.num_ext_ppcnt_counters,
5055 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5058 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5059 struct mlx5_ib_port *port,
5060 struct rdma_hw_stats *stats)
5062 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5067 out = kvzalloc(outlen, GFP_KERNEL);
5071 ret = mlx5_core_query_q_counter(mdev,
5072 port->cnts.set_id, 0,
5077 for (i = 0; i < port->cnts.num_q_counters; i++) {
5078 val = *(__be32 *)(out + port->cnts.offsets[i]);
5079 stats->value[i] = (u64)be32_to_cpu(val);
5087 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5088 struct mlx5_ib_port *port,
5089 struct rdma_hw_stats *stats)
5091 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5092 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5096 out = kvzalloc(sz, GFP_KERNEL);
5100 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5104 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5105 stats->value[i + offset] =
5106 be64_to_cpup((__be64 *)(out +
5107 port->cnts.offsets[i + offset]));
5115 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5116 struct rdma_hw_stats *stats,
5117 u8 port_num, int index)
5119 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5120 struct mlx5_ib_port *port = &dev->port[port_num - 1];
5121 struct mlx5_core_dev *mdev;
5122 int ret, num_counters;
5128 num_counters = port->cnts.num_q_counters +
5129 port->cnts.num_cong_counters +
5130 port->cnts.num_ext_ppcnt_counters;
5132 /* q_counters are per IB device, query the master mdev */
5133 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5137 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5138 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5143 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5144 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5147 /* If port is not affiliated yet, its in down state
5148 * which doesn't have any counters yet, so it would be
5149 * zero. So no need to read from the HCA.
5153 ret = mlx5_lag_query_cong_counters(dev->mdev,
5155 port->cnts.num_q_counters,
5156 port->cnts.num_cong_counters,
5157 port->cnts.offsets +
5158 port->cnts.num_q_counters);
5160 mlx5_ib_put_native_port_mdev(dev, port_num);
5166 return num_counters;
5169 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5170 enum rdma_netdev_t type,
5171 struct rdma_netdev_alloc_params *params)
5173 if (type != RDMA_NETDEV_IPOIB)
5176 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5179 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5181 if (!dev->delay_drop.dbg)
5183 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5184 kfree(dev->delay_drop.dbg);
5185 dev->delay_drop.dbg = NULL;
5188 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5190 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5193 cancel_work_sync(&dev->delay_drop.delay_drop_work);
5194 delay_drop_debugfs_cleanup(dev);
5197 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5198 size_t count, loff_t *pos)
5200 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5204 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5205 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5208 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5209 size_t count, loff_t *pos)
5211 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5215 if (kstrtouint_from_user(buf, count, 0, &var))
5218 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5221 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5224 delay_drop->timeout = timeout;
5229 static const struct file_operations fops_delay_drop_timeout = {
5230 .owner = THIS_MODULE,
5231 .open = simple_open,
5232 .write = delay_drop_timeout_write,
5233 .read = delay_drop_timeout_read,
5236 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5238 struct mlx5_ib_dbg_delay_drop *dbg;
5240 if (!mlx5_debugfs_root)
5243 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5247 dev->delay_drop.dbg = dbg;
5250 debugfs_create_dir("delay_drop",
5251 dev->mdev->priv.dbg_root);
5252 if (!dbg->dir_debugfs)
5255 dbg->events_cnt_debugfs =
5256 debugfs_create_atomic_t("num_timeout_events", 0400,
5258 &dev->delay_drop.events_cnt);
5259 if (!dbg->events_cnt_debugfs)
5262 dbg->rqs_cnt_debugfs =
5263 debugfs_create_atomic_t("num_rqs", 0400,
5265 &dev->delay_drop.rqs_cnt);
5266 if (!dbg->rqs_cnt_debugfs)
5269 dbg->timeout_debugfs =
5270 debugfs_create_file("timeout", 0600,
5273 &fops_delay_drop_timeout);
5274 if (!dbg->timeout_debugfs)
5280 delay_drop_debugfs_cleanup(dev);
5284 static void init_delay_drop(struct mlx5_ib_dev *dev)
5286 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5289 mutex_init(&dev->delay_drop.lock);
5290 dev->delay_drop.dev = dev;
5291 dev->delay_drop.activate = false;
5292 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5293 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5294 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5295 atomic_set(&dev->delay_drop.events_cnt, 0);
5297 if (delay_drop_debugfs_init(dev))
5298 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5301 static const struct cpumask *
5302 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
5304 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5306 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
5309 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5310 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5311 struct mlx5_ib_multiport_info *mpi)
5313 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5314 struct mlx5_ib_port *port = &ibdev->port[port_num];
5319 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5321 spin_lock(&port->mp.mpi_lock);
5323 spin_unlock(&port->mp.mpi_lock);
5328 spin_unlock(&port->mp.mpi_lock);
5329 mlx5_remove_netdev_notifier(ibdev, port_num);
5330 spin_lock(&port->mp.mpi_lock);
5332 comps = mpi->mdev_refcnt;
5334 mpi->unaffiliate = true;
5335 init_completion(&mpi->unref_comp);
5336 spin_unlock(&port->mp.mpi_lock);
5338 for (i = 0; i < comps; i++)
5339 wait_for_completion(&mpi->unref_comp);
5341 spin_lock(&port->mp.mpi_lock);
5342 mpi->unaffiliate = false;
5345 port->mp.mpi = NULL;
5347 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5349 spin_unlock(&port->mp.mpi_lock);
5351 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5353 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5354 /* Log an error, still needed to cleanup the pointers and add
5355 * it back to the list.
5358 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5361 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5364 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5365 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5366 struct mlx5_ib_multiport_info *mpi)
5368 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5371 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5372 if (ibdev->port[port_num].mp.mpi) {
5373 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5375 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5379 ibdev->port[port_num].mp.mpi = mpi;
5381 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5383 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5387 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5391 err = mlx5_add_netdev_notifier(ibdev, port_num);
5393 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5398 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5405 mlx5_ib_unbind_slave_port(ibdev, mpi);
5409 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5411 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5412 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5414 struct mlx5_ib_multiport_info *mpi;
5418 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5421 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5422 &dev->sys_image_guid);
5426 err = mlx5_nic_vport_enable_roce(dev->mdev);
5430 mutex_lock(&mlx5_ib_multiport_mutex);
5431 for (i = 0; i < dev->num_ports; i++) {
5434 /* build a stub multiport info struct for the native port. */
5435 if (i == port_num) {
5436 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5438 mutex_unlock(&mlx5_ib_multiport_mutex);
5439 mlx5_nic_vport_disable_roce(dev->mdev);
5443 mpi->is_master = true;
5444 mpi->mdev = dev->mdev;
5445 mpi->sys_image_guid = dev->sys_image_guid;
5446 dev->port[i].mp.mpi = mpi;
5452 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5454 if (dev->sys_image_guid == mpi->sys_image_guid &&
5455 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5456 bound = mlx5_ib_bind_slave_port(dev, mpi);
5460 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5461 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5462 list_del(&mpi->list);
5467 get_port_caps(dev, i + 1);
5468 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5473 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5474 mutex_unlock(&mlx5_ib_multiport_mutex);
5478 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5480 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5481 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5485 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5488 mutex_lock(&mlx5_ib_multiport_mutex);
5489 for (i = 0; i < dev->num_ports; i++) {
5490 if (dev->port[i].mp.mpi) {
5491 /* Destroy the native port stub */
5492 if (i == port_num) {
5493 kfree(dev->port[i].mp.mpi);
5494 dev->port[i].mp.mpi = NULL;
5496 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5497 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5502 mlx5_ib_dbg(dev, "removing from devlist\n");
5503 list_del(&dev->ib_dev_list);
5504 mutex_unlock(&mlx5_ib_multiport_mutex);
5506 mlx5_nic_vport_disable_roce(dev->mdev);
5509 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5512 UVERBS_METHOD_DM_ALLOC,
5513 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5514 UVERBS_ATTR_TYPE(u64),
5516 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5517 UVERBS_ATTR_TYPE(u16),
5520 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5521 mlx5_ib_flow_action,
5522 UVERBS_OBJECT_FLOW_ACTION,
5523 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5524 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5525 enum mlx5_ib_uapi_flow_action_flags));
5527 static int populate_specs_root(struct mlx5_ib_dev *dev)
5529 const struct uverbs_object_tree_def **trees = dev->driver_trees;
5530 size_t num_trees = 0;
5532 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
5533 MLX5_ACCEL_IPSEC_CAP_DEVICE)
5534 trees[num_trees++] = &mlx5_ib_flow_action;
5536 if (MLX5_CAP_DEV_MEM(dev->mdev, memic))
5537 trees[num_trees++] = &mlx5_ib_dm;
5539 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5540 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX)
5541 trees[num_trees++] = mlx5_ib_get_devx_tree();
5543 num_trees += mlx5_ib_get_flow_trees(trees + num_trees);
5545 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees));
5546 trees[num_trees] = NULL;
5547 dev->ib_dev.driver_specs = trees;
5552 static int mlx5_ib_read_counters(struct ib_counters *counters,
5553 struct ib_counters_read_attr *read_attr,
5554 struct uverbs_attr_bundle *attrs)
5556 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5557 struct mlx5_read_counters_attr mread_attr = {};
5558 struct mlx5_ib_flow_counters_desc *desc;
5561 mutex_lock(&mcounters->mcntrs_mutex);
5562 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5567 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5569 if (!mread_attr.out) {
5574 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5575 mread_attr.flags = read_attr->flags;
5576 ret = mcounters->read_counters(counters->device, &mread_attr);
5580 /* do the pass over the counters data array to assign according to the
5581 * descriptions and indexing pairs
5583 desc = mcounters->counters_data;
5584 for (i = 0; i < mcounters->ncounters; i++)
5585 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5588 kfree(mread_attr.out);
5590 mutex_unlock(&mcounters->mcntrs_mutex);
5594 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5596 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5598 counters_clear_description(counters);
5599 if (mcounters->hw_cntrs_hndl)
5600 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5601 mcounters->hw_cntrs_hndl);
5608 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5609 struct uverbs_attr_bundle *attrs)
5611 struct mlx5_ib_mcounters *mcounters;
5613 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5615 return ERR_PTR(-ENOMEM);
5617 mutex_init(&mcounters->mcntrs_mutex);
5619 return &mcounters->ibcntrs;
5622 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5624 mlx5_ib_cleanup_multiport_master(dev);
5625 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5626 cleanup_srcu_struct(&dev->mr_srcu);
5631 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5633 struct mlx5_core_dev *mdev = dev->mdev;
5638 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5643 for (i = 0; i < dev->num_ports; i++) {
5644 spin_lock_init(&dev->port[i].mp.mpi_lock);
5645 rwlock_init(&dev->roce[i].netdev_lock);
5648 err = mlx5_ib_init_multiport_master(dev);
5652 if (!mlx5_core_mp_enabled(mdev)) {
5653 for (i = 1; i <= dev->num_ports; i++) {
5654 err = get_port_caps(dev, i);
5659 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5664 if (mlx5_use_mad_ifc(dev))
5665 get_ext_port_caps(dev);
5667 if (!mlx5_lag_is_active(mdev))
5670 name = "mlx5_bond_%d";
5672 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5673 dev->ib_dev.owner = THIS_MODULE;
5674 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
5675 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
5676 dev->ib_dev.phys_port_cnt = dev->num_ports;
5677 dev->ib_dev.num_comp_vectors =
5678 dev->mdev->priv.eq_table.num_comp_vectors;
5679 dev->ib_dev.dev.parent = &mdev->pdev->dev;
5681 mutex_init(&dev->cap_mask_mutex);
5682 INIT_LIST_HEAD(&dev->qp_list);
5683 spin_lock_init(&dev->reset_flow_resource_lock);
5685 spin_lock_init(&dev->memic.memic_lock);
5686 dev->memic.dev = mdev;
5688 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5689 err = init_srcu_struct(&dev->mr_srcu);
5696 mlx5_ib_cleanup_multiport_master(dev);
5704 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5706 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5711 mutex_init(&dev->flow_db->lock);
5716 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5718 struct mlx5_ib_dev *nic_dev;
5720 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5725 dev->flow_db = nic_dev->flow_db;
5730 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5732 kfree(dev->flow_db);
5735 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5737 struct mlx5_core_dev *mdev = dev->mdev;
5740 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5741 dev->ib_dev.uverbs_cmd_mask =
5742 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5743 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5744 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5745 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5746 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
5747 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5748 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
5749 (1ull << IB_USER_VERBS_CMD_REG_MR) |
5750 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
5751 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5752 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5753 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5754 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5755 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5756 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5757 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5758 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5759 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5760 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5761 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5762 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5763 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5764 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5765 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5766 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5767 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5768 dev->ib_dev.uverbs_ex_cmd_mask =
5769 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5770 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
5771 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
5772 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5773 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5775 dev->ib_dev.query_device = mlx5_ib_query_device;
5776 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
5777 dev->ib_dev.query_gid = mlx5_ib_query_gid;
5778 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5779 dev->ib_dev.del_gid = mlx5_ib_del_gid;
5780 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5781 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5782 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5783 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5784 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5785 dev->ib_dev.mmap = mlx5_ib_mmap;
5786 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5787 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5788 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5789 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5790 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5791 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5792 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5793 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5794 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5795 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5796 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5797 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5798 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5799 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
5800 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5801 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
5802 dev->ib_dev.post_send = mlx5_ib_post_send;
5803 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5804 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5805 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5806 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5807 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5808 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5809 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5810 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5811 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
5812 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
5813 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5814 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5815 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5816 dev->ib_dev.process_mad = mlx5_ib_process_mad;
5817 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
5818 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
5819 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
5820 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
5821 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5822 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
5823 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
5824 dev->ib_dev.rdma_netdev_get_params = mlx5_ib_rn_get_params;
5826 if (mlx5_core_is_pf(mdev)) {
5827 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5828 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5829 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5830 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5833 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5835 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5837 if (MLX5_CAP_GEN(mdev, imaicl)) {
5838 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5839 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5840 dev->ib_dev.uverbs_cmd_mask |=
5841 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5842 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5845 if (MLX5_CAP_GEN(mdev, xrc)) {
5846 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5847 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5848 dev->ib_dev.uverbs_cmd_mask |=
5849 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5850 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5853 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5854 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5855 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5856 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5859 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5860 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5861 dev->ib_dev.uverbs_ex_cmd_mask |=
5862 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5863 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5864 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5865 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5866 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5867 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5868 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5869 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
5870 dev->ib_dev.read_counters = mlx5_ib_read_counters;
5872 err = init_node_data(dev);
5876 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5877 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5878 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5879 mutex_init(&dev->lb_mutex);
5884 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5886 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5887 dev->ib_dev.query_port = mlx5_ib_query_port;
5892 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5894 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5895 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5900 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
5905 for (i = 0; i < dev->num_ports; i++) {
5906 dev->roce[i].dev = dev;
5907 dev->roce[i].native_port_num = i + 1;
5908 dev->roce[i].last_port_state = IB_PORT_DOWN;
5911 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5912 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5913 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5914 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5915 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5916 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5918 dev->ib_dev.uverbs_ex_cmd_mask |=
5919 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5920 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5921 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5922 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5923 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5925 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5927 return mlx5_add_netdev_notifier(dev, port_num);
5930 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5932 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5934 mlx5_remove_netdev_notifier(dev, port_num);
5937 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5939 struct mlx5_core_dev *mdev = dev->mdev;
5940 enum rdma_link_layer ll;
5944 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5945 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5947 if (ll == IB_LINK_LAYER_ETHERNET)
5948 err = mlx5_ib_stage_common_roce_init(dev);
5953 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5955 mlx5_ib_stage_common_roce_cleanup(dev);
5958 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5960 struct mlx5_core_dev *mdev = dev->mdev;
5961 enum rdma_link_layer ll;
5965 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5966 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5968 if (ll == IB_LINK_LAYER_ETHERNET) {
5969 err = mlx5_ib_stage_common_roce_init(dev);
5973 err = mlx5_enable_eth(dev);
5980 mlx5_ib_stage_common_roce_cleanup(dev);
5985 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5987 struct mlx5_core_dev *mdev = dev->mdev;
5988 enum rdma_link_layer ll;
5991 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5992 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5994 if (ll == IB_LINK_LAYER_ETHERNET) {
5995 mlx5_disable_eth(dev);
5996 mlx5_ib_stage_common_roce_cleanup(dev);
6000 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6002 return create_dev_resources(&dev->devr);
6005 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6007 destroy_dev_resources(&dev->devr);
6010 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6012 mlx5_ib_internal_fill_odp_caps(dev);
6014 return mlx5_ib_odp_init_one(dev);
6017 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6019 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6020 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
6021 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
6023 return mlx5_ib_alloc_counters(dev);
6029 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6031 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6032 mlx5_ib_dealloc_counters(dev);
6035 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6037 return mlx5_ib_init_cong_debugfs(dev,
6038 mlx5_core_native_port_num(dev->mdev) - 1);
6041 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6043 mlx5_ib_cleanup_cong_debugfs(dev,
6044 mlx5_core_native_port_num(dev->mdev) - 1);
6047 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6049 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6050 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6053 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6055 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6058 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6062 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6066 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6068 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6073 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6075 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6076 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6079 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6081 return populate_specs_root(dev);
6084 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6086 return ib_register_device(&dev->ib_dev, NULL);
6089 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6091 destroy_umrc_res(dev);
6094 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6096 ib_unregister_device(&dev->ib_dev);
6099 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6101 return create_umr_res(dev);
6104 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6106 init_delay_drop(dev);
6111 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6113 cancel_delay_drop(dev);
6116 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
6121 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
6122 err = device_create_file(&dev->ib_dev.dev,
6123 mlx5_class_attributes[i]);
6131 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6133 mlx5_ib_register_vport_reps(dev);
6138 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6140 mlx5_ib_unregister_vport_reps(dev);
6143 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6144 const struct mlx5_ib_profile *profile,
6147 /* Number of stages to cleanup */
6150 if (profile->stage[stage].cleanup)
6151 profile->stage[stage].cleanup(dev);
6154 ib_dealloc_device((struct ib_device *)dev);
6157 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6158 const struct mlx5_ib_profile *profile)
6163 printk_once(KERN_INFO "%s", mlx5_version);
6165 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6166 if (profile->stage[i].init) {
6167 err = profile->stage[i].init(dev);
6173 dev->profile = profile;
6174 dev->ib_active = true;
6179 __mlx5_ib_remove(dev, profile, i);
6184 static const struct mlx5_ib_profile pf_profile = {
6185 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6186 mlx5_ib_stage_init_init,
6187 mlx5_ib_stage_init_cleanup),
6188 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6189 mlx5_ib_stage_flow_db_init,
6190 mlx5_ib_stage_flow_db_cleanup),
6191 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6192 mlx5_ib_stage_caps_init,
6194 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6195 mlx5_ib_stage_non_default_cb,
6197 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6198 mlx5_ib_stage_roce_init,
6199 mlx5_ib_stage_roce_cleanup),
6200 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6201 mlx5_ib_stage_dev_res_init,
6202 mlx5_ib_stage_dev_res_cleanup),
6203 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6204 mlx5_ib_stage_odp_init,
6206 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6207 mlx5_ib_stage_counters_init,
6208 mlx5_ib_stage_counters_cleanup),
6209 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6210 mlx5_ib_stage_cong_debugfs_init,
6211 mlx5_ib_stage_cong_debugfs_cleanup),
6212 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6213 mlx5_ib_stage_uar_init,
6214 mlx5_ib_stage_uar_cleanup),
6215 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6216 mlx5_ib_stage_bfrag_init,
6217 mlx5_ib_stage_bfrag_cleanup),
6218 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6220 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6221 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6222 mlx5_ib_stage_populate_specs,
6224 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6225 mlx5_ib_stage_ib_reg_init,
6226 mlx5_ib_stage_ib_reg_cleanup),
6227 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6228 mlx5_ib_stage_post_ib_reg_umr_init,
6230 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6231 mlx5_ib_stage_delay_drop_init,
6232 mlx5_ib_stage_delay_drop_cleanup),
6233 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6234 mlx5_ib_stage_class_attr_init,
6238 static const struct mlx5_ib_profile nic_rep_profile = {
6239 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6240 mlx5_ib_stage_init_init,
6241 mlx5_ib_stage_init_cleanup),
6242 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6243 mlx5_ib_stage_flow_db_init,
6244 mlx5_ib_stage_flow_db_cleanup),
6245 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6246 mlx5_ib_stage_caps_init,
6248 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6249 mlx5_ib_stage_rep_non_default_cb,
6251 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6252 mlx5_ib_stage_rep_roce_init,
6253 mlx5_ib_stage_rep_roce_cleanup),
6254 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6255 mlx5_ib_stage_dev_res_init,
6256 mlx5_ib_stage_dev_res_cleanup),
6257 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6258 mlx5_ib_stage_counters_init,
6259 mlx5_ib_stage_counters_cleanup),
6260 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6261 mlx5_ib_stage_uar_init,
6262 mlx5_ib_stage_uar_cleanup),
6263 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6264 mlx5_ib_stage_bfrag_init,
6265 mlx5_ib_stage_bfrag_cleanup),
6266 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6268 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6269 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6270 mlx5_ib_stage_populate_specs,
6272 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6273 mlx5_ib_stage_ib_reg_init,
6274 mlx5_ib_stage_ib_reg_cleanup),
6275 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6276 mlx5_ib_stage_post_ib_reg_umr_init,
6278 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6279 mlx5_ib_stage_class_attr_init,
6281 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6282 mlx5_ib_stage_rep_reg_init,
6283 mlx5_ib_stage_rep_reg_cleanup),
6286 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6288 struct mlx5_ib_multiport_info *mpi;
6289 struct mlx5_ib_dev *dev;
6293 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6299 err = mlx5_query_nic_vport_system_image_guid(mdev,
6300 &mpi->sys_image_guid);
6306 mutex_lock(&mlx5_ib_multiport_mutex);
6307 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6308 if (dev->sys_image_guid == mpi->sys_image_guid)
6309 bound = mlx5_ib_bind_slave_port(dev, mpi);
6312 rdma_roce_rescan_device(&dev->ib_dev);
6318 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6319 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6321 mutex_unlock(&mlx5_ib_multiport_mutex);
6326 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6328 enum rdma_link_layer ll;
6329 struct mlx5_ib_dev *dev;
6332 printk_once(KERN_INFO "%s", mlx5_version);
6334 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6335 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6337 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6338 return mlx5_ib_add_slave_port(mdev);
6340 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6345 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6346 MLX5_CAP_GEN(mdev, num_vhca_ports));
6348 if (MLX5_ESWITCH_MANAGER(mdev) &&
6349 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6350 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6352 return __mlx5_ib_add(dev, &nic_rep_profile);
6355 return __mlx5_ib_add(dev, &pf_profile);
6358 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6360 struct mlx5_ib_multiport_info *mpi;
6361 struct mlx5_ib_dev *dev;
6363 if (mlx5_core_is_mp_slave(mdev)) {
6365 mutex_lock(&mlx5_ib_multiport_mutex);
6367 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6368 list_del(&mpi->list);
6369 mutex_unlock(&mlx5_ib_multiport_mutex);
6374 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6377 static struct mlx5_interface mlx5_ib_interface = {
6379 .remove = mlx5_ib_remove,
6380 .event = mlx5_ib_event,
6381 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6382 .pfault = mlx5_ib_pfault,
6384 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
6387 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6389 mutex_lock(&xlt_emergency_page_mutex);
6390 return xlt_emergency_page;
6393 void mlx5_ib_put_xlt_emergency_page(void)
6395 mutex_unlock(&xlt_emergency_page_mutex);
6398 static int __init mlx5_ib_init(void)
6402 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6403 if (!xlt_emergency_page)
6406 mutex_init(&xlt_emergency_page_mutex);
6408 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6409 if (!mlx5_ib_event_wq) {
6410 free_page(xlt_emergency_page);
6416 err = mlx5_register_interface(&mlx5_ib_interface);
6421 static void __exit mlx5_ib_cleanup(void)
6423 mlx5_unregister_interface(&mlx5_ib_interface);
6424 destroy_workqueue(mlx5_ib_event_wq);
6425 mutex_destroy(&xlt_emergency_page_mutex);
6426 free_page(xlt_emergency_page);
6429 module_init(mlx5_ib_init);
6430 module_exit(mlx5_ib_cleanup);