drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #if defined(CONFIG_X86)
  42 #include <asm/pat.h>
  43 #endif
  44 #include <linux/sched.h>
  45 #include <linux/sched/mm.h>
  46 #include <linux/sched/task.h>
  47 #include <linux/delay.h>
  48 #include <rdma/ib_user_verbs.h>
  49 #include <rdma/ib_addr.h>
  50 #include <rdma/ib_cache.h>
  51 #include <linux/mlx5/port.h>
  52 #include <linux/mlx5/vport.h>
  53 #include <linux/mlx5/fs.h>
  54 #include <linux/list.h>
  55 #include <rdma/ib_smi.h>
  56 #include <rdma/ib_umem.h>
  57 #include <linux/in.h>
  58 #include <linux/etherdevice.h>
  59 #include "mlx5_ib.h"
  60 #include "cmd.h"
  61
  62 #define DRIVER_NAME "mlx5_ib"
  63 #define DRIVER_VERSION "5.0-0"
  64
  65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  67 MODULE_LICENSE("Dual BSD/GPL");
  68
  69 static char mlx5_version[] =
  70         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  71         DRIVER_VERSION "\n";
  72
  73 struct mlx5_ib_event_work {
  74         struct work_struct      work;
  75         struct mlx5_core_dev    *dev;
  76         void                    *context;
  77         enum mlx5_dev_event     event;
  78         unsigned long           param;
  79 };
  80
  81 enum {
  82         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  83 };
  84
  85 static struct workqueue_struct *mlx5_ib_event_wq;
  86 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  87 static LIST_HEAD(mlx5_ib_dev_list);
  88 /*
  89  * This mutex should be held when accessing either of the above lists
  90  */
  91 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  92
  93 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  94 {
  95         struct mlx5_ib_dev *dev;
  96
  97         mutex_lock(&mlx5_ib_multiport_mutex);
  98         dev = mpi->ibdev;
  99         mutex_unlock(&mlx5_ib_multiport_mutex);
 100         return dev;
 101 }
 102
 103 static enum rdma_link_layer
 104 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 105 {
 106         switch (port_type_cap) {
 107         case MLX5_CAP_PORT_TYPE_IB:
 108                 return IB_LINK_LAYER_INFINIBAND;
 109         case MLX5_CAP_PORT_TYPE_ETH:
 110                 return IB_LINK_LAYER_ETHERNET;
 111         default:
 112                 return IB_LINK_LAYER_UNSPECIFIED;
 113         }
 114 }
 115
 116 static enum rdma_link_layer
 117 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 118 {
 119         struct mlx5_ib_dev *dev = to_mdev(device);
 120         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 121
 122         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 123 }
 124
 125 static int get_port_state(struct ib_device *ibdev,
 126                           u8 port_num,
 127                           enum ib_port_state *state)
 128 {
 129         struct ib_port_attr attr;
 130         int ret;
 131
 132         memset(&attr, 0, sizeof(attr));
 133         ret = mlx5_ib_query_port(ibdev, port_num, &attr);
 134         if (!ret)
 135                 *state = attr.state;
 136         return ret;
 137 }
 138
 139 static int mlx5_netdev_event(struct notifier_block *this,
 140                              unsigned long event, void *ptr)
 141 {
 142         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 143         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 144         u8 port_num = roce->native_port_num;
 145         struct mlx5_core_dev *mdev;
 146         struct mlx5_ib_dev *ibdev;
 147
 148         ibdev = roce->dev;
 149         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 150         if (!mdev)
 151                 return NOTIFY_DONE;
 152
 153         switch (event) {
 154         case NETDEV_REGISTER:
 155         case NETDEV_UNREGISTER:
 156                 write_lock(&roce->netdev_lock);
 157
 158                 if (ndev->dev.parent == &mdev->pdev->dev)
 159                         roce->netdev = (event == NETDEV_UNREGISTER) ?
 160                                         NULL : ndev;
 161                 write_unlock(&roce->netdev_lock);
 162                 break;
 163
 164         case NETDEV_CHANGE:
 165         case NETDEV_UP:
 166         case NETDEV_DOWN: {
 167                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 168                 struct net_device *upper = NULL;
 169
 170                 if (lag_ndev) {
 171                         upper = netdev_master_upper_dev_get(lag_ndev);
 172                         dev_put(lag_ndev);
 173                 }
 174
 175                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 176                     && ibdev->ib_active) {
 177                         struct ib_event ibev = { };
 178                         enum ib_port_state port_state;
 179
 180                         if (get_port_state(&ibdev->ib_dev, port_num,
 181                                            &port_state))
 182                                 goto done;
 183
 184                         if (roce->last_port_state == port_state)
 185                                 goto done;
 186
 187                         roce->last_port_state = port_state;
 188                         ibev.device = &ibdev->ib_dev;
 189                         if (port_state == IB_PORT_DOWN)
 190                                 ibev.event = IB_EVENT_PORT_ERR;
 191                         else if (port_state == IB_PORT_ACTIVE)
 192                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 193                         else
 194                                 goto done;
 195
 196                         ibev.element.port_num = port_num;
 197                         ib_dispatch_event(&ibev);
 198                 }
 199                 break;
 200         }
 201
 202         default:
 203                 break;
 204         }
 205 done:
 206         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 207         return NOTIFY_DONE;
 208 }
 209
 210 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 211                                              u8 port_num)
 212 {
 213         struct mlx5_ib_dev *ibdev = to_mdev(device);
 214         struct net_device *ndev;
 215         struct mlx5_core_dev *mdev;
 216
 217         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 218         if (!mdev)
 219                 return NULL;
 220
 221         ndev = mlx5_lag_get_roce_netdev(mdev);
 222         if (ndev)
 223                 goto out;
 224
 225         /* Ensure ndev does not disappear before we invoke dev_hold()
 226          */
 227         read_lock(&ibdev->roce[port_num - 1].netdev_lock);
 228         ndev = ibdev->roce[port_num - 1].netdev;
 229         if (ndev)
 230                 dev_hold(ndev);
 231         read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
 232
 233 out:
 234         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 235         return ndev;
 236 }
 237
 238 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 239                                                    u8 ib_port_num,
 240                                                    u8 *native_port_num)
 241 {
 242         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 243                                                           ib_port_num);
 244         struct mlx5_core_dev *mdev = NULL;
 245         struct mlx5_ib_multiport_info *mpi;
 246         struct mlx5_ib_port *port;
 247
 248         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 249             ll != IB_LINK_LAYER_ETHERNET) {
 250                 if (native_port_num)
 251                         *native_port_num = ib_port_num;
 252                 return ibdev->mdev;
 253         }
 254
 255         if (native_port_num)
 256                 *native_port_num = 1;
 257
 258         port = &ibdev->port[ib_port_num - 1];
 259         if (!port)
 260                 return NULL;
 261
 262         spin_lock(&port->mp.mpi_lock);
 263         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 264         if (mpi && !mpi->unaffiliate) {
 265                 mdev = mpi->mdev;
 266                 /* If it's the master no need to refcount, it'll exist
 267                  * as long as the ib_dev exists.
 268                  */
 269                 if (!mpi->is_master)
 270                         mpi->mdev_refcnt++;
 271         }
 272         spin_unlock(&port->mp.mpi_lock);
 273
 274         return mdev;
 275 }
 276
 277 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 278 {
 279         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 280                                                           port_num);
 281         struct mlx5_ib_multiport_info *mpi;
 282         struct mlx5_ib_port *port;
 283
 284         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 285                 return;
 286
 287         port = &ibdev->port[port_num - 1];
 288
 289         spin_lock(&port->mp.mpi_lock);
 290         mpi = ibdev->port[port_num - 1].mp.mpi;
 291         if (mpi->is_master)
 292                 goto out;
 293
 294         mpi->mdev_refcnt--;
 295         if (mpi->unaffiliate)
 296                 complete(&mpi->unref_comp);
 297 out:
 298         spin_unlock(&port->mp.mpi_lock);
 299 }
 300
 301 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 302                                     u8 *active_width)
 303 {
 304         switch (eth_proto_oper) {
 305         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 306         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 307         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 308         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 309                 *active_width = IB_WIDTH_1X;
 310                 *active_speed = IB_SPEED_SDR;
 311                 break;
 312         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 313         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 314         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 315         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 316         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 317         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 318         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 319                 *active_width = IB_WIDTH_1X;
 320                 *active_speed = IB_SPEED_QDR;
 321                 break;
 322         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 323         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 324         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 325                 *active_width = IB_WIDTH_1X;
 326                 *active_speed = IB_SPEED_EDR;
 327                 break;
 328         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 329         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 330         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 331         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 332                 *active_width = IB_WIDTH_4X;
 333                 *active_speed = IB_SPEED_QDR;
 334                 break;
 335         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 336         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 337         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 338                 *active_width = IB_WIDTH_1X;
 339                 *active_speed = IB_SPEED_HDR;
 340                 break;
 341         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 342                 *active_width = IB_WIDTH_4X;
 343                 *active_speed = IB_SPEED_FDR;
 344                 break;
 345         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 346         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 347         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 348         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 349                 *active_width = IB_WIDTH_4X;
 350                 *active_speed = IB_SPEED_EDR;
 351                 break;
 352         default:
 353                 return -EINVAL;
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 360                                 struct ib_port_attr *props)
 361 {
 362         struct mlx5_ib_dev *dev = to_mdev(device);
 363         struct mlx5_core_dev *mdev;
 364         struct net_device *ndev, *upper;
 365         enum ib_mtu ndev_ib_mtu;
 366         bool put_mdev = true;
 367         u16 qkey_viol_cntr;
 368         u32 eth_prot_oper;
 369         u8 mdev_port_num;
 370         int err;
 371
 372         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 373         if (!mdev) {
 374                 /* This means the port isn't affiliated yet. Get the
 375                  * info for the master port instead.
 376                  */
 377                 put_mdev = false;
 378                 mdev = dev->mdev;
 379                 mdev_port_num = 1;
 380                 port_num = 1;
 381         }
 382
 383         /* Possible bad flows are checked before filling out props so in case
 384          * of an error it will still be zeroed out.
 385          */
 386         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
 387                                              mdev_port_num);
 388         if (err)
 389                 goto out;
 390
 391         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 392                                  &props->active_width);
 393
 394         props->port_cap_flags  |= IB_PORT_CM_SUP;
 395         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 396
 397         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 398                                                 roce_address_table_size);
 399         props->max_mtu          = IB_MTU_4096;
 400         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 401         props->pkey_tbl_len     = 1;
 402         props->state            = IB_PORT_DOWN;
 403         props->phys_state       = 3;
 404
 405         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 406         props->qkey_viol_cntr = qkey_viol_cntr;
 407
 408         /* If this is a stub query for an unaffiliated port stop here */
 409         if (!put_mdev)
 410                 goto out;
 411
 412         ndev = mlx5_ib_get_netdev(device, port_num);
 413         if (!ndev)
 414                 goto out;
 415
 416         if (mlx5_lag_is_active(dev->mdev)) {
 417                 rcu_read_lock();
 418                 upper = netdev_master_upper_dev_get_rcu(ndev);
 419                 if (upper) {
 420                         dev_put(ndev);
 421                         ndev = upper;
 422                         dev_hold(ndev);
 423                 }
 424                 rcu_read_unlock();
 425         }
 426
 427         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 428                 props->state      = IB_PORT_ACTIVE;
 429                 props->phys_state = 5;
 430         }
 431
 432         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 433
 434         dev_put(ndev);
 435
 436         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 437 out:
 438         if (put_mdev)
 439                 mlx5_ib_put_native_port_mdev(dev, port_num);
 440         return err;
 441 }
 442
 443 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 444                          unsigned int index, const union ib_gid *gid,
 445                          const struct ib_gid_attr *attr)
 446 {
 447         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 448         u8 roce_version = 0;
 449         u8 roce_l3_type = 0;
 450         bool vlan = false;
 451         u8 mac[ETH_ALEN];
 452         u16 vlan_id = 0;
 453
 454         if (gid) {
 455                 gid_type = attr->gid_type;
 456                 ether_addr_copy(mac, attr->ndev->dev_addr);
 457
 458                 if (is_vlan_dev(attr->ndev)) {
 459                         vlan = true;
 460                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 461                 }
 462         }
 463
 464         switch (gid_type) {
 465         case IB_GID_TYPE_IB:
 466                 roce_version = MLX5_ROCE_VERSION_1;
 467                 break;
 468         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 469                 roce_version = MLX5_ROCE_VERSION_2;
 470                 if (ipv6_addr_v4mapped((void *)gid))
 471                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 472                 else
 473                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 474                 break;
 475
 476         default:
 477                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 478         }
 479
 480         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 481                                       roce_l3_type, gid->raw, mac, vlan,
 482                                       vlan_id, port_num);
 483 }
 484
 485 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 486                            unsigned int index, const union ib_gid *gid,
 487                            const struct ib_gid_attr *attr,
 488                            __always_unused void **context)
 489 {
 490         return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
 491 }
 492
 493 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 494                            unsigned int index, __always_unused void **context)
 495 {
 496         return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
 497 }
 498
 499 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 500                                int index)
 501 {
 502         struct ib_gid_attr attr;
 503         union ib_gid gid;
 504
 505         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 506                 return 0;
 507
 508         if (!attr.ndev)
 509                 return 0;
 510
 511         dev_put(attr.ndev);
 512
 513         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 514                 return 0;
 515
 516         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 517 }
 518
 519 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 520                            int index, enum ib_gid_type *gid_type)
 521 {
 522         struct ib_gid_attr attr;
 523         union ib_gid gid;
 524         int ret;
 525
 526         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 527         if (ret)
 528                 return ret;
 529
 530         if (!attr.ndev)
 531                 return -ENODEV;
 532
 533         dev_put(attr.ndev);
 534
 535         *gid_type = attr.gid_type;
 536
 537         return 0;
 538 }
 539
 540 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 541 {
 542         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 543                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 544         return 0;
 545 }
 546
 547 enum {
 548         MLX5_VPORT_ACCESS_METHOD_MAD,
 549         MLX5_VPORT_ACCESS_METHOD_HCA,
 550         MLX5_VPORT_ACCESS_METHOD_NIC,
 551 };
 552
 553 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 554 {
 555         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 556                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 557
 558         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 559             IB_LINK_LAYER_ETHERNET)
 560                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 561
 562         return MLX5_VPORT_ACCESS_METHOD_HCA;
 563 }
 564
 565 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 566                             u8 atomic_size_qp,
 567                             struct ib_device_attr *props)
 568 {
 569         u8 tmp;
 570         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 571         u8 atomic_req_8B_endianness_mode =
 572                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 573
 574         /* Check if HW supports 8 bytes standard atomic operations and capable
 575          * of host endianness respond
 576          */
 577         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 578         if (((atomic_operations & tmp) == tmp) &&
 579             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 580             (atomic_req_8B_endianness_mode)) {
 581                 props->atomic_cap = IB_ATOMIC_HCA;
 582         } else {
 583                 props->atomic_cap = IB_ATOMIC_NONE;
 584         }
 585 }
 586
 587 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 588                                struct ib_device_attr *props)
 589 {
 590         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 591
 592         get_atomic_caps(dev, atomic_size_qp, props);
 593 }
 594
 595 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 596                                struct ib_device_attr *props)
 597 {
 598         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 599
 600         get_atomic_caps(dev, atomic_size_qp, props);
 601 }
 602
 603 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 604 {
 605         struct ib_device_attr props = {};
 606
 607         get_atomic_caps_dc(dev, &props);
 608         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 609 }
 610 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 611                                         __be64 *sys_image_guid)
 612 {
 613         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 614         struct mlx5_core_dev *mdev = dev->mdev;
 615         u64 tmp;
 616         int err;
 617
 618         switch (mlx5_get_vport_access_method(ibdev)) {
 619         case MLX5_VPORT_ACCESS_METHOD_MAD:
 620                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 621                                                             sys_image_guid);
 622
 623         case MLX5_VPORT_ACCESS_METHOD_HCA:
 624                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 625                 break;
 626
 627         case MLX5_VPORT_ACCESS_METHOD_NIC:
 628                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 629                 break;
 630
 631         default:
 632                 return -EINVAL;
 633         }
 634
 635         if (!err)
 636                 *sys_image_guid = cpu_to_be64(tmp);
 637
 638         return err;
 639
 640 }
 641
 642 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 643                                 u16 *max_pkeys)
 644 {
 645         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 646         struct mlx5_core_dev *mdev = dev->mdev;
 647
 648         switch (mlx5_get_vport_access_method(ibdev)) {
 649         case MLX5_VPORT_ACCESS_METHOD_MAD:
 650                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 651
 652         case MLX5_VPORT_ACCESS_METHOD_HCA:
 653         case MLX5_VPORT_ACCESS_METHOD_NIC:
 654                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 655                                                 pkey_table_size));
 656                 return 0;
 657
 658         default:
 659                 return -EINVAL;
 660         }
 661 }
 662
 663 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 664                                 u32 *vendor_id)
 665 {
 666         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 667
 668         switch (mlx5_get_vport_access_method(ibdev)) {
 669         case MLX5_VPORT_ACCESS_METHOD_MAD:
 670                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 671
 672         case MLX5_VPORT_ACCESS_METHOD_HCA:
 673         case MLX5_VPORT_ACCESS_METHOD_NIC:
 674                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 675
 676         default:
 677                 return -EINVAL;
 678         }
 679 }
 680
 681 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 682                                 __be64 *node_guid)
 683 {
 684         u64 tmp;
 685         int err;
 686
 687         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 688         case MLX5_VPORT_ACCESS_METHOD_MAD:
 689                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 690
 691         case MLX5_VPORT_ACCESS_METHOD_HCA:
 692                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 693                 break;
 694
 695         case MLX5_VPORT_ACCESS_METHOD_NIC:
 696                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 697                 break;
 698
 699         default:
 700                 return -EINVAL;
 701         }
 702
 703         if (!err)
 704                 *node_guid = cpu_to_be64(tmp);
 705
 706         return err;
 707 }
 708
 709 struct mlx5_reg_node_desc {
 710         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 711 };
 712
 713 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 714 {
 715         struct mlx5_reg_node_desc in;
 716
 717         if (mlx5_use_mad_ifc(dev))
 718                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 719
 720         memset(&in, 0, sizeof(in));
 721
 722         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 723                                     sizeof(struct mlx5_reg_node_desc),
 724                                     MLX5_REG_NODE_DESC, 0, 0);
 725 }
 726
 727 static int mlx5_ib_query_device(struct ib_device *ibdev,
 728                                 struct ib_device_attr *props,
 729                                 struct ib_udata *uhw)
 730 {
 731         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 732         struct mlx5_core_dev *mdev = dev->mdev;
 733         int err = -ENOMEM;
 734         int max_sq_desc;
 735         int max_rq_sg;
 736         int max_sq_sg;
 737         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 738         bool raw_support = !mlx5_core_mp_enabled(mdev);
 739         struct mlx5_ib_query_device_resp resp = {};
 740         size_t resp_len;
 741         u64 max_tso;
 742
 743         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 744         if (uhw->outlen && uhw->outlen < resp_len)
 745                 return -EINVAL;
 746         else
 747                 resp.response_length = resp_len;
 748
 749         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 750                 return -EINVAL;
 751
 752         memset(props, 0, sizeof(*props));
 753         err = mlx5_query_system_image_guid(ibdev,
 754                                            &props->sys_image_guid);
 755         if (err)
 756                 return err;
 757
 758         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 759         if (err)
 760                 return err;
 761
 762         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 763         if (err)
 764                 return err;
 765
 766         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 767                 (fw_rev_min(dev->mdev) << 16) |
 768                 fw_rev_sub(dev->mdev);
 769         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 770                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 771                 IB_DEVICE_SYS_IMAGE_GUID                |
 772                 IB_DEVICE_RC_RNR_NAK_GEN;
 773
 774         if (MLX5_CAP_GEN(mdev, pkv))
 775                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 776         if (MLX5_CAP_GEN(mdev, qkv))
 777                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 778         if (MLX5_CAP_GEN(mdev, apm))
 779                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 780         if (MLX5_CAP_GEN(mdev, xrc))
 781                 props->device_cap_flags |= IB_DEVICE_XRC;
 782         if (MLX5_CAP_GEN(mdev, imaicl)) {
 783                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 784                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 785                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 786                 /* We support 'Gappy' memory registration too */
 787                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 788         }
 789         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 790         if (MLX5_CAP_GEN(mdev, sho)) {
 791                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 792                 /* At this stage no support for signature handover */
 793                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 794                                       IB_PROT_T10DIF_TYPE_2 |
 795                                       IB_PROT_T10DIF_TYPE_3;
 796                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 797                                        IB_GUARD_T10DIF_CSUM;
 798         }
 799         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 800                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 801
 802         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 803                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 804                         /* Legacy bit to support old userspace libraries */
 805                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 806                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 807                 }
 808
 809                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 810                         props->raw_packet_caps |=
 811                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 812
 813                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 814                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 815                         if (max_tso) {
 816                                 resp.tso_caps.max_tso = 1 << max_tso;
 817                                 resp.tso_caps.supported_qpts |=
 818                                         1 << IB_QPT_RAW_PACKET;
 819                                 resp.response_length += sizeof(resp.tso_caps);
 820                         }
 821                 }
 822
 823                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 824                         resp.rss_caps.rx_hash_function =
 825                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 826                         resp.rss_caps.rx_hash_fields_mask =
 827                                                 MLX5_RX_HASH_SRC_IPV4 |
 828                                                 MLX5_RX_HASH_DST_IPV4 |
 829                                                 MLX5_RX_HASH_SRC_IPV6 |
 830                                                 MLX5_RX_HASH_DST_IPV6 |
 831                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 832                                                 MLX5_RX_HASH_DST_PORT_TCP |
 833                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 834                                                 MLX5_RX_HASH_DST_PORT_UDP |
 835                                                 MLX5_RX_HASH_INNER;
 836                         resp.response_length += sizeof(resp.rss_caps);
 837                 }
 838         } else {
 839                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 840                         resp.response_length += sizeof(resp.tso_caps);
 841                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 842                         resp.response_length += sizeof(resp.rss_caps);
 843         }
 844
 845         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 846                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 847                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 848         }
 849
 850         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 851             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 852             raw_support)
 853                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 854
 855         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 856             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 857                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 858
 859         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 860             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 861             raw_support) {
 862                 /* Legacy bit to support old userspace libraries */
 863                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 864                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 865         }
 866
 867         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 868                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 869
 870         if (MLX5_CAP_GEN(mdev, end_pad))
 871                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 872
 873         props->vendor_part_id      = mdev->pdev->device;
 874         props->hw_ver              = mdev->pdev->revision;
 875
 876         props->max_mr_size         = ~0ull;
 877         props->page_size_cap       = ~(min_page_size - 1);
 878         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 879         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 880         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 881                      sizeof(struct mlx5_wqe_data_seg);
 882         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 883         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 884                      sizeof(struct mlx5_wqe_raddr_seg)) /
 885                 sizeof(struct mlx5_wqe_data_seg);
 886         props->max_sge = min(max_rq_sg, max_sq_sg);
 887         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 888         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 889         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 890         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 891         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 892         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 893         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 894         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 895         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 896         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 897         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 898         props->max_srq_sge         = max_rq_sg - 1;
 899         props->max_fast_reg_page_list_len =
 900                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 901         get_atomic_caps_qp(dev, props);
 902         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 903         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 904         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 905         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 906                                            props->max_mcast_grp;
 907         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 908         props->max_ah = INT_MAX;
 909         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 910         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 911
 912 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 913         if (MLX5_CAP_GEN(mdev, pg))
 914                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 915         props->odp_caps = dev->odp_caps;
 916 #endif
 917
 918         if (MLX5_CAP_GEN(mdev, cd))
 919                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 920
 921         if (!mlx5_core_is_pf(mdev))
 922                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 923
 924         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 925             IB_LINK_LAYER_ETHERNET && raw_support) {
 926                 props->rss_caps.max_rwq_indirection_tables =
 927                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 928                 props->rss_caps.max_rwq_indirection_table_size =
 929                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 930                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 931                 props->max_wq_type_rq =
 932                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 933         }
 934
 935         if (MLX5_CAP_GEN(mdev, tag_matching)) {
 936                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
 937                 props->tm_caps.max_num_tags =
 938                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
 939                 props->tm_caps.flags = IB_TM_CAP_RC;
 940                 props->tm_caps.max_ops =
 941                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 942                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 943         }
 944
 945         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
 946                 props->cq_caps.max_cq_moderation_count =
 947                                                 MLX5_MAX_CQ_COUNT;
 948                 props->cq_caps.max_cq_moderation_period =
 949                                                 MLX5_MAX_CQ_PERIOD;
 950         }
 951
 952         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 953                 resp.cqe_comp_caps.max_num =
 954                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 955                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 956                 resp.cqe_comp_caps.supported_format =
 957                         MLX5_IB_CQE_RES_FORMAT_HASH |
 958                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 959                 resp.response_length += sizeof(resp.cqe_comp_caps);
 960         }
 961
 962         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
 963             raw_support) {
 964                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 965                     MLX5_CAP_GEN(mdev, qos)) {
 966                         resp.packet_pacing_caps.qp_rate_limit_max =
 967                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 968                         resp.packet_pacing_caps.qp_rate_limit_min =
 969                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 970                         resp.packet_pacing_caps.supported_qpts |=
 971                                 1 << IB_QPT_RAW_PACKET;
 972                 }
 973                 resp.response_length += sizeof(resp.packet_pacing_caps);
 974         }
 975
 976         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 977                         uhw->outlen)) {
 978                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
 979                         resp.mlx5_ib_support_multi_pkt_send_wqes =
 980                                 MLX5_IB_ALLOW_MPW;
 981
 982                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
 983                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
 984                                 MLX5_IB_SUPPORT_EMPW;
 985
 986                 resp.response_length +=
 987                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
 988         }
 989
 990         if (field_avail(typeof(resp), flags, uhw->outlen)) {
 991                 resp.response_length += sizeof(resp.flags);
 992
 993                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
 994                         resp.flags |=
 995                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
 996
 997                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
 998                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
 999         }
1000
1001         if (field_avail(typeof(resp), sw_parsing_caps,
1002                         uhw->outlen)) {
1003                 resp.response_length += sizeof(resp.sw_parsing_caps);
1004                 if (MLX5_CAP_ETH(mdev, swp)) {
1005                         resp.sw_parsing_caps.sw_parsing_offloads |=
1006                                 MLX5_IB_SW_PARSING;
1007
1008                         if (MLX5_CAP_ETH(mdev, swp_csum))
1009                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1010                                         MLX5_IB_SW_PARSING_CSUM;
1011
1012                         if (MLX5_CAP_ETH(mdev, swp_lso))
1013                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1014                                         MLX5_IB_SW_PARSING_LSO;
1015
1016                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1017                                 resp.sw_parsing_caps.supported_qpts =
1018                                         BIT(IB_QPT_RAW_PACKET);
1019                 }
1020         }
1021
1022         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1023             raw_support) {
1024                 resp.response_length += sizeof(resp.striding_rq_caps);
1025                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1026                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1027                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1028                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1029                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1030                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1031                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1032                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1033                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1034                         resp.striding_rq_caps.supported_qpts =
1035                                 BIT(IB_QPT_RAW_PACKET);
1036                 }
1037         }
1038
1039         if (field_avail(typeof(resp), tunnel_offloads_caps,
1040                         uhw->outlen)) {
1041                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1042                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1043                         resp.tunnel_offloads_caps |=
1044                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1045                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1046                         resp.tunnel_offloads_caps |=
1047                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1048                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1049                         resp.tunnel_offloads_caps |=
1050                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1051         }
1052
1053         if (uhw->outlen) {
1054                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1055
1056                 if (err)
1057                         return err;
1058         }
1059
1060         return 0;
1061 }
1062
1063 enum mlx5_ib_width {
1064         MLX5_IB_WIDTH_1X        = 1 << 0,
1065         MLX5_IB_WIDTH_2X        = 1 << 1,
1066         MLX5_IB_WIDTH_4X        = 1 << 2,
1067         MLX5_IB_WIDTH_8X        = 1 << 3,
1068         MLX5_IB_WIDTH_12X       = 1 << 4
1069 };
1070
1071 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1072                                   u8 *ib_width)
1073 {
1074         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1075         int err = 0;
1076
1077         if (active_width & MLX5_IB_WIDTH_1X) {
1078                 *ib_width = IB_WIDTH_1X;
1079         } else if (active_width & MLX5_IB_WIDTH_2X) {
1080                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1081                             (int)active_width);
1082                 err = -EINVAL;
1083         } else if (active_width & MLX5_IB_WIDTH_4X) {
1084                 *ib_width = IB_WIDTH_4X;
1085         } else if (active_width & MLX5_IB_WIDTH_8X) {
1086                 *ib_width = IB_WIDTH_8X;
1087         } else if (active_width & MLX5_IB_WIDTH_12X) {
1088                 *ib_width = IB_WIDTH_12X;
1089         } else {
1090                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1091                             (int)active_width);
1092                 err = -EINVAL;
1093         }
1094
1095         return err;
1096 }
1097
1098 static int mlx5_mtu_to_ib_mtu(int mtu)
1099 {
1100         switch (mtu) {
1101         case 256: return 1;
1102         case 512: return 2;
1103         case 1024: return 3;
1104         case 2048: return 4;
1105         case 4096: return 5;
1106         default:
1107                 pr_warn("invalid mtu\n");
1108                 return -1;
1109         }
1110 }
1111
1112 enum ib_max_vl_num {
1113         __IB_MAX_VL_0           = 1,
1114         __IB_MAX_VL_0_1         = 2,
1115         __IB_MAX_VL_0_3         = 3,
1116         __IB_MAX_VL_0_7         = 4,
1117         __IB_MAX_VL_0_14        = 5,
1118 };
1119
1120 enum mlx5_vl_hw_cap {
1121         MLX5_VL_HW_0    = 1,
1122         MLX5_VL_HW_0_1  = 2,
1123         MLX5_VL_HW_0_2  = 3,
1124         MLX5_VL_HW_0_3  = 4,
1125         MLX5_VL_HW_0_4  = 5,
1126         MLX5_VL_HW_0_5  = 6,
1127         MLX5_VL_HW_0_6  = 7,
1128         MLX5_VL_HW_0_7  = 8,
1129         MLX5_VL_HW_0_14 = 15
1130 };
1131
1132 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1133                                 u8 *max_vl_num)
1134 {
1135         switch (vl_hw_cap) {
1136         case MLX5_VL_HW_0:
1137                 *max_vl_num = __IB_MAX_VL_0;
1138                 break;
1139         case MLX5_VL_HW_0_1:
1140                 *max_vl_num = __IB_MAX_VL_0_1;
1141                 break;
1142         case MLX5_VL_HW_0_3:
1143                 *max_vl_num = __IB_MAX_VL_0_3;
1144                 break;
1145         case MLX5_VL_HW_0_7:
1146                 *max_vl_num = __IB_MAX_VL_0_7;
1147                 break;
1148         case MLX5_VL_HW_0_14:
1149                 *max_vl_num = __IB_MAX_VL_0_14;
1150                 break;
1151
1152         default:
1153                 return -EINVAL;
1154         }
1155
1156         return 0;
1157 }
1158
1159 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1160                                struct ib_port_attr *props)
1161 {
1162         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1163         struct mlx5_core_dev *mdev = dev->mdev;
1164         struct mlx5_hca_vport_context *rep;
1165         u16 max_mtu;
1166         u16 oper_mtu;
1167         int err;
1168         u8 ib_link_width_oper;
1169         u8 vl_hw_cap;
1170
1171         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1172         if (!rep) {
1173                 err = -ENOMEM;
1174                 goto out;
1175         }
1176
1177         /* props being zeroed by the caller, avoid zeroing it here */
1178
1179         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1180         if (err)
1181                 goto out;
1182
1183         props->lid              = rep->lid;
1184         props->lmc              = rep->lmc;
1185         props->sm_lid           = rep->sm_lid;
1186         props->sm_sl            = rep->sm_sl;
1187         props->state            = rep->vport_state;
1188         props->phys_state       = rep->port_physical_state;
1189         props->port_cap_flags   = rep->cap_mask1;
1190         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1191         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1192         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1193         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1194         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1195         props->subnet_timeout   = rep->subnet_timeout;
1196         props->init_type_reply  = rep->init_type_reply;
1197         props->grh_required     = rep->grh_required;
1198
1199         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1200         if (err)
1201                 goto out;
1202
1203         err = translate_active_width(ibdev, ib_link_width_oper,
1204                                      &props->active_width);
1205         if (err)
1206                 goto out;
1207         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1208         if (err)
1209                 goto out;
1210
1211         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1212
1213         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1214
1215         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1216
1217         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1218
1219         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1220         if (err)
1221                 goto out;
1222
1223         err = translate_max_vl_num(ibdev, vl_hw_cap,
1224                                    &props->max_vl_num);
1225 out:
1226         kfree(rep);
1227         return err;
1228 }
1229
1230 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1231                        struct ib_port_attr *props)
1232 {
1233         unsigned int count;
1234         int ret;
1235
1236         switch (mlx5_get_vport_access_method(ibdev)) {
1237         case MLX5_VPORT_ACCESS_METHOD_MAD:
1238                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1239                 break;
1240
1241         case MLX5_VPORT_ACCESS_METHOD_HCA:
1242                 ret = mlx5_query_hca_port(ibdev, port, props);
1243                 break;
1244
1245         case MLX5_VPORT_ACCESS_METHOD_NIC:
1246                 ret = mlx5_query_port_roce(ibdev, port, props);
1247                 break;
1248
1249         default:
1250                 ret = -EINVAL;
1251         }
1252
1253         if (!ret && props) {
1254                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1255                 struct mlx5_core_dev *mdev;
1256                 bool put_mdev = true;
1257
1258                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1259                 if (!mdev) {
1260                         /* If the port isn't affiliated yet query the master.
1261                          * The master and slave will have the same values.
1262                          */
1263                         mdev = dev->mdev;
1264                         port = 1;
1265                         put_mdev = false;
1266                 }
1267                 count = mlx5_core_reserved_gids_count(mdev);
1268                 if (put_mdev)
1269                         mlx5_ib_put_native_port_mdev(dev, port);
1270                 props->gid_tbl_len -= count;
1271         }
1272         return ret;
1273 }
1274
1275 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1276                              union ib_gid *gid)
1277 {
1278         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1279         struct mlx5_core_dev *mdev = dev->mdev;
1280
1281         switch (mlx5_get_vport_access_method(ibdev)) {
1282         case MLX5_VPORT_ACCESS_METHOD_MAD:
1283                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1284
1285         case MLX5_VPORT_ACCESS_METHOD_HCA:
1286                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1287
1288         default:
1289                 return -EINVAL;
1290         }
1291
1292 }
1293
1294 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1295                                    u16 index, u16 *pkey)
1296 {
1297         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1298         struct mlx5_core_dev *mdev;
1299         bool put_mdev = true;
1300         u8 mdev_port_num;
1301         int err;
1302
1303         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1304         if (!mdev) {
1305                 /* The port isn't affiliated yet, get the PKey from the master
1306                  * port. For RoCE the PKey tables will be the same.
1307                  */
1308                 put_mdev = false;
1309                 mdev = dev->mdev;
1310                 mdev_port_num = 1;
1311         }
1312
1313         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1314                                         index, pkey);
1315         if (put_mdev)
1316                 mlx5_ib_put_native_port_mdev(dev, port);
1317
1318         return err;
1319 }
1320
1321 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1322                               u16 *pkey)
1323 {
1324         switch (mlx5_get_vport_access_method(ibdev)) {
1325         case MLX5_VPORT_ACCESS_METHOD_MAD:
1326                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1327
1328         case MLX5_VPORT_ACCESS_METHOD_HCA:
1329         case MLX5_VPORT_ACCESS_METHOD_NIC:
1330                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1331         default:
1332                 return -EINVAL;
1333         }
1334 }
1335
1336 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1337                                  struct ib_device_modify *props)
1338 {
1339         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1340         struct mlx5_reg_node_desc in;
1341         struct mlx5_reg_node_desc out;
1342         int err;
1343
1344         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1345                 return -EOPNOTSUPP;
1346
1347         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1348                 return 0;
1349
1350         /*
1351          * If possible, pass node desc to FW, so it can generate
1352          * a 144 trap.  If cmd fails, just ignore.
1353          */
1354         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1355         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1356                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1357         if (err)
1358                 return err;
1359
1360         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1361
1362         return err;
1363 }
1364
1365 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1366                                 u32 value)
1367 {
1368         struct mlx5_hca_vport_context ctx = {};
1369         struct mlx5_core_dev *mdev;
1370         u8 mdev_port_num;
1371         int err;
1372
1373         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1374         if (!mdev)
1375                 return -ENODEV;
1376
1377         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1378         if (err)
1379                 goto out;
1380
1381         if (~ctx.cap_mask1_perm & mask) {
1382                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1383                              mask, ctx.cap_mask1_perm);
1384                 err = -EINVAL;
1385                 goto out;
1386         }
1387
1388         ctx.cap_mask1 = value;
1389         ctx.cap_mask1_perm = mask;
1390         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1391                                                  0, &ctx);
1392
1393 out:
1394         mlx5_ib_put_native_port_mdev(dev, port_num);
1395
1396         return err;
1397 }
1398
1399 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1400                                struct ib_port_modify *props)
1401 {
1402         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1403         struct ib_port_attr attr;
1404         u32 tmp;
1405         int err;
1406         u32 change_mask;
1407         u32 value;
1408         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1409                       IB_LINK_LAYER_INFINIBAND);
1410
1411         /* CM layer calls ib_modify_port() regardless of the link layer. For
1412          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1413          */
1414         if (!is_ib)
1415                 return 0;
1416
1417         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1418                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1419                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1420                 return set_port_caps_atomic(dev, port, change_mask, value);
1421         }
1422
1423         mutex_lock(&dev->cap_mask_mutex);
1424
1425         err = ib_query_port(ibdev, port, &attr);
1426         if (err)
1427                 goto out;
1428
1429         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1430                 ~props->clr_port_cap_mask;
1431
1432         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1433
1434 out:
1435         mutex_unlock(&dev->cap_mask_mutex);
1436         return err;
1437 }
1438
1439 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1440 {
1441         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1442                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1443 }
1444
1445 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1446 {
1447         /* Large page with non 4k uar support might limit the dynamic size */
1448         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1449                 return MLX5_MIN_DYN_BFREGS;
1450
1451         return MLX5_MAX_DYN_BFREGS;
1452 }
1453
1454 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1455                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1456                              struct mlx5_bfreg_info *bfregi)
1457 {
1458         int uars_per_sys_page;
1459         int bfregs_per_sys_page;
1460         int ref_bfregs = req->total_num_bfregs;
1461
1462         if (req->total_num_bfregs == 0)
1463                 return -EINVAL;
1464
1465         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1466         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1467
1468         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1469                 return -ENOMEM;
1470
1471         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1472         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1473         /* This holds the required static allocation asked by the user */
1474         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1475         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1476                 return -EINVAL;
1477
1478         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1479         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1480         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1481         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1482
1483         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1484                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1485                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1486                     req->total_num_bfregs, bfregi->total_num_bfregs,
1487                     bfregi->num_sys_pages);
1488
1489         return 0;
1490 }
1491
1492 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1493 {
1494         struct mlx5_bfreg_info *bfregi;
1495         int err;
1496         int i;
1497
1498         bfregi = &context->bfregi;
1499         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1500                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1501                 if (err)
1502                         goto error;
1503
1504                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1505         }
1506
1507         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1508                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1509
1510         return 0;
1511
1512 error:
1513         for (--i; i >= 0; i--)
1514                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1515                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1516
1517         return err;
1518 }
1519
1520 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1521 {
1522         struct mlx5_bfreg_info *bfregi;
1523         int err;
1524         int i;
1525
1526         bfregi = &context->bfregi;
1527         for (i = 0; i < bfregi->num_sys_pages; i++) {
1528                 if (i < bfregi->num_static_sys_pages ||
1529                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1530                         err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1531                         if (err) {
1532                                 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1533                                 return err;
1534                         }
1535                 }
1536         }
1537
1538         return 0;
1539 }
1540
1541 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1542 {
1543         int err;
1544
1545         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1546         if (err)
1547                 return err;
1548
1549         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1550             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1551              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1552                 return err;
1553
1554         mutex_lock(&dev->lb_mutex);
1555         dev->user_td++;
1556
1557         if (dev->user_td == 2)
1558                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1559
1560         mutex_unlock(&dev->lb_mutex);
1561         return err;
1562 }
1563
1564 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1565 {
1566         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1567
1568         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1569             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1570              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1571                 return;
1572
1573         mutex_lock(&dev->lb_mutex);
1574         dev->user_td--;
1575
1576         if (dev->user_td < 2)
1577                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1578
1579         mutex_unlock(&dev->lb_mutex);
1580 }
1581
1582 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1583                                                   struct ib_udata *udata)
1584 {
1585         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1586         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1587         struct mlx5_ib_alloc_ucontext_resp resp = {};
1588         struct mlx5_core_dev *mdev = dev->mdev;
1589         struct mlx5_ib_ucontext *context;
1590         struct mlx5_bfreg_info *bfregi;
1591         int ver;
1592         int err;
1593         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1594                                      max_cqe_version);
1595         bool lib_uar_4k;
1596
1597         if (!dev->ib_active)
1598                 return ERR_PTR(-EAGAIN);
1599
1600         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1601                 ver = 0;
1602         else if (udata->inlen >= min_req_v2)
1603                 ver = 2;
1604         else
1605                 return ERR_PTR(-EINVAL);
1606
1607         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1608         if (err)
1609                 return ERR_PTR(err);
1610
1611         if (req.flags)
1612                 return ERR_PTR(-EINVAL);
1613
1614         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1615                 return ERR_PTR(-EOPNOTSUPP);
1616
1617         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1618                                     MLX5_NON_FP_BFREGS_PER_UAR);
1619         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1620                 return ERR_PTR(-EINVAL);
1621
1622         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1623         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1624                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1625         resp.cache_line_size = cache_line_size();
1626         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1627         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1628         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1629         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1630         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1631         resp.cqe_version = min_t(__u8,
1632                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1633                                  req.max_cqe_version);
1634         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1635                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1636         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1637                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1638         resp.response_length = min(offsetof(typeof(resp), response_length) +
1639                                    sizeof(resp.response_length), udata->outlen);
1640
1641         context = kzalloc(sizeof(*context), GFP_KERNEL);
1642         if (!context)
1643                 return ERR_PTR(-ENOMEM);
1644
1645         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1646         bfregi = &context->bfregi;
1647
1648         /* updates req->total_num_bfregs */
1649         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1650         if (err)
1651                 goto out_ctx;
1652
1653         mutex_init(&bfregi->lock);
1654         bfregi->lib_uar_4k = lib_uar_4k;
1655         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1656                                 GFP_KERNEL);
1657         if (!bfregi->count) {
1658                 err = -ENOMEM;
1659                 goto out_ctx;
1660         }
1661
1662         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1663                                     sizeof(*bfregi->sys_pages),
1664                                     GFP_KERNEL);
1665         if (!bfregi->sys_pages) {
1666                 err = -ENOMEM;
1667                 goto out_count;
1668         }
1669
1670         err = allocate_uars(dev, context);
1671         if (err)
1672                 goto out_sys_pages;
1673
1674 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1675         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1676 #endif
1677
1678         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1679         if (!context->upd_xlt_page) {
1680                 err = -ENOMEM;
1681                 goto out_uars;
1682         }
1683         mutex_init(&context->upd_xlt_page_mutex);
1684
1685         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1686                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1687                 if (err)
1688                         goto out_page;
1689         }
1690
1691         INIT_LIST_HEAD(&context->vma_private_list);
1692         mutex_init(&context->vma_private_list_mutex);
1693         INIT_LIST_HEAD(&context->db_page_list);
1694         mutex_init(&context->db_page_mutex);
1695
1696         resp.tot_bfregs = req.total_num_bfregs;
1697         resp.num_ports = dev->num_ports;
1698
1699         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1700                 resp.response_length += sizeof(resp.cqe_version);
1701
1702         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1703                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1704                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1705                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1706         }
1707
1708         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1709                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1710                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1711                         resp.eth_min_inline++;
1712                 }
1713                 resp.response_length += sizeof(resp.eth_min_inline);
1714         }
1715
1716         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1717                 if (mdev->clock_info)
1718                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1719                 resp.response_length += sizeof(resp.clock_info_versions);
1720         }
1721
1722         /*
1723          * We don't want to expose information from the PCI bar that is located
1724          * after 4096 bytes, so if the arch only supports larger pages, let's
1725          * pretend we don't support reading the HCA's core clock. This is also
1726          * forced by mmap function.
1727          */
1728         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1729                 if (PAGE_SIZE <= 4096) {
1730                         resp.comp_mask |=
1731                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1732                         resp.hca_core_clock_offset =
1733                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1734                 }
1735                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1736         }
1737
1738         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1739                 resp.response_length += sizeof(resp.log_uar_size);
1740
1741         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1742                 resp.response_length += sizeof(resp.num_uars_per_page);
1743
1744         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1745                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1746                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1747         }
1748
1749         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1750         if (err)
1751                 goto out_td;
1752
1753         bfregi->ver = ver;
1754         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1755         context->cqe_version = resp.cqe_version;
1756         context->lib_caps = req.lib_caps;
1757         print_lib_caps(dev, context->lib_caps);
1758
1759         return &context->ibucontext;
1760
1761 out_td:
1762         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1763                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1764
1765 out_page:
1766         free_page(context->upd_xlt_page);
1767
1768 out_uars:
1769         deallocate_uars(dev, context);
1770
1771 out_sys_pages:
1772         kfree(bfregi->sys_pages);
1773
1774 out_count:
1775         kfree(bfregi->count);
1776
1777 out_ctx:
1778         kfree(context);
1779
1780         return ERR_PTR(err);
1781 }
1782
1783 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1784 {
1785         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1786         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1787         struct mlx5_bfreg_info *bfregi;
1788
1789         bfregi = &context->bfregi;
1790         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1791                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1792
1793         free_page(context->upd_xlt_page);
1794         deallocate_uars(dev, context);
1795         kfree(bfregi->sys_pages);
1796         kfree(bfregi->count);
1797         kfree(context);
1798
1799         return 0;
1800 }
1801
1802 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1803                                  int uar_idx)
1804 {
1805         int fw_uars_per_page;
1806
1807         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1808
1809         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1810 }
1811
1812 static int get_command(unsigned long offset)
1813 {
1814         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1815 }
1816
1817 static int get_arg(unsigned long offset)
1818 {
1819         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1820 }
1821
1822 static int get_index(unsigned long offset)
1823 {
1824         return get_arg(offset);
1825 }
1826
1827 /* Index resides in an extra byte to enable larger values than 255 */
1828 static int get_extended_index(unsigned long offset)
1829 {
1830         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1831 }
1832
1833 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1834 {
1835         /* vma_open is called when a new VMA is created on top of our VMA.  This
1836          * is done through either mremap flow or split_vma (usually due to
1837          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1838          * as this VMA is strongly hardware related.  Therefore we set the
1839          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1840          * calling us again and trying to do incorrect actions.  We assume that
1841          * the original VMA size is exactly a single page, and therefore all
1842          * "splitting" operation will not happen to it.
1843          */
1844         area->vm_ops = NULL;
1845 }
1846
1847 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1848 {
1849         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1850
1851         /* It's guaranteed that all VMAs opened on a FD are closed before the
1852          * file itself is closed, therefore no sync is needed with the regular
1853          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1854          * However need a sync with accessing the vma as part of
1855          * mlx5_ib_disassociate_ucontext.
1856          * The close operation is usually called under mm->mmap_sem except when
1857          * process is exiting.
1858          * The exiting case is handled explicitly as part of
1859          * mlx5_ib_disassociate_ucontext.
1860          */
1861         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1862
1863         /* setting the vma context pointer to null in the mlx5_ib driver's
1864          * private data, to protect a race condition in
1865          * mlx5_ib_disassociate_ucontext().
1866          */
1867         mlx5_ib_vma_priv_data->vma = NULL;
1868         mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1869         list_del(&mlx5_ib_vma_priv_data->list);
1870         mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1871         kfree(mlx5_ib_vma_priv_data);
1872 }
1873
1874 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1875         .open = mlx5_ib_vma_open,
1876         .close = mlx5_ib_vma_close
1877 };
1878
1879 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1880                                 struct mlx5_ib_ucontext *ctx)
1881 {
1882         struct mlx5_ib_vma_private_data *vma_prv;
1883         struct list_head *vma_head = &ctx->vma_private_list;
1884
1885         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1886         if (!vma_prv)
1887                 return -ENOMEM;
1888
1889         vma_prv->vma = vma;
1890         vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1891         vma->vm_private_data = vma_prv;
1892         vma->vm_ops =  &mlx5_ib_vm_ops;
1893
1894         mutex_lock(&ctx->vma_private_list_mutex);
1895         list_add(&vma_prv->list, vma_head);
1896         mutex_unlock(&ctx->vma_private_list_mutex);
1897
1898         return 0;
1899 }
1900
1901 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1902 {
1903         int ret;
1904         struct vm_area_struct *vma;
1905         struct mlx5_ib_vma_private_data *vma_private, *n;
1906         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1907         struct task_struct *owning_process  = NULL;
1908         struct mm_struct   *owning_mm       = NULL;
1909
1910         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1911         if (!owning_process)
1912                 return;
1913
1914         owning_mm = get_task_mm(owning_process);
1915         if (!owning_mm) {
1916                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1917                 while (1) {
1918                         put_task_struct(owning_process);
1919                         usleep_range(1000, 2000);
1920                         owning_process = get_pid_task(ibcontext->tgid,
1921                                                       PIDTYPE_PID);
1922                         if (!owning_process ||
1923                             owning_process->state == TASK_DEAD) {
1924                                 pr_info("disassociate ucontext done, task was terminated\n");
1925                                 /* in case task was dead need to release the
1926                                  * task struct.
1927                                  */
1928                                 if (owning_process)
1929                                         put_task_struct(owning_process);
1930                                 return;
1931                         }
1932                 }
1933         }
1934
1935         /* need to protect from a race on closing the vma as part of
1936          * mlx5_ib_vma_close.
1937          */
1938         down_write(&owning_mm->mmap_sem);
1939         mutex_lock(&context->vma_private_list_mutex);
1940         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1941                                  list) {
1942                 vma = vma_private->vma;
1943                 ret = zap_vma_ptes(vma, vma->vm_start,
1944                                    PAGE_SIZE);
1945                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1946                 /* context going to be destroyed, should
1947                  * not access ops any more.
1948                  */
1949                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1950                 vma->vm_ops = NULL;
1951                 list_del(&vma_private->list);
1952                 kfree(vma_private);
1953         }
1954         mutex_unlock(&context->vma_private_list_mutex);
1955         up_write(&owning_mm->mmap_sem);
1956         mmput(owning_mm);
1957         put_task_struct(owning_process);
1958 }
1959
1960 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1961 {
1962         switch (cmd) {
1963         case MLX5_IB_MMAP_WC_PAGE:
1964                 return "WC";
1965         case MLX5_IB_MMAP_REGULAR_PAGE:
1966                 return "best effort WC";
1967         case MLX5_IB_MMAP_NC_PAGE:
1968                 return "NC";
1969         default:
1970                 return NULL;
1971         }
1972 }
1973
1974 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1975                                         struct vm_area_struct *vma,
1976                                         struct mlx5_ib_ucontext *context)
1977 {
1978         phys_addr_t pfn;
1979         int err;
1980
1981         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1982                 return -EINVAL;
1983
1984         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1985                 return -EOPNOTSUPP;
1986
1987         if (vma->vm_flags & VM_WRITE)
1988                 return -EPERM;
1989
1990         if (!dev->mdev->clock_info_page)
1991                 return -EOPNOTSUPP;
1992
1993         pfn = page_to_pfn(dev->mdev->clock_info_page);
1994         err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
1995                               vma->vm_page_prot);
1996         if (err)
1997                 return err;
1998
1999         mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2000                     vma->vm_start,
2001                     (unsigned long long)pfn << PAGE_SHIFT);
2002
2003         return mlx5_ib_set_vma_data(vma, context);
2004 }
2005
2006 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2007                     struct vm_area_struct *vma,
2008                     struct mlx5_ib_ucontext *context)
2009 {
2010         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2011         int err;
2012         unsigned long idx;
2013         phys_addr_t pfn, pa;
2014         pgprot_t prot;
2015         u32 bfreg_dyn_idx = 0;
2016         u32 uar_index;
2017         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2018         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2019                                 bfregi->num_static_sys_pages;
2020
2021         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2022                 return -EINVAL;
2023
2024         if (dyn_uar)
2025                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2026         else
2027                 idx = get_index(vma->vm_pgoff);
2028
2029         if (idx >= max_valid_idx) {
2030                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2031                              idx, max_valid_idx);
2032                 return -EINVAL;
2033         }
2034
2035         switch (cmd) {
2036         case MLX5_IB_MMAP_WC_PAGE:
2037         case MLX5_IB_MMAP_ALLOC_WC:
2038 /* Some architectures don't support WC memory */
2039 #if defined(CONFIG_X86)
2040                 if (!pat_enabled())
2041                         return -EPERM;
2042 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2043                         return -EPERM;
2044 #endif
2045         /* fall through */
2046         case MLX5_IB_MMAP_REGULAR_PAGE:
2047                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2048                 prot = pgprot_writecombine(vma->vm_page_prot);
2049                 break;
2050         case MLX5_IB_MMAP_NC_PAGE:
2051                 prot = pgprot_noncached(vma->vm_page_prot);
2052                 break;
2053         default:
2054                 return -EINVAL;
2055         }
2056
2057         if (dyn_uar) {
2058                 int uars_per_page;
2059
2060                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2061                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2062                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2063                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2064                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2065                         return -EINVAL;
2066                 }
2067
2068                 mutex_lock(&bfregi->lock);
2069                 /* Fail if uar already allocated, first bfreg index of each
2070                  * page holds its count.
2071                  */
2072                 if (bfregi->count[bfreg_dyn_idx]) {
2073                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2074                         mutex_unlock(&bfregi->lock);
2075                         return -EINVAL;
2076                 }
2077
2078                 bfregi->count[bfreg_dyn_idx]++;
2079                 mutex_unlock(&bfregi->lock);
2080
2081                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2082                 if (err) {
2083                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2084                         goto free_bfreg;
2085                 }
2086         } else {
2087                 uar_index = bfregi->sys_pages[idx];
2088         }
2089
2090         pfn = uar_index2pfn(dev, uar_index);
2091         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2092
2093         vma->vm_page_prot = prot;
2094         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2095                                  PAGE_SIZE, vma->vm_page_prot);
2096         if (err) {
2097                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2098                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
2099                 err = -EAGAIN;
2100                 goto err;
2101         }
2102
2103         pa = pfn << PAGE_SHIFT;
2104         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2105                     vma->vm_start, &pa);
2106
2107         err = mlx5_ib_set_vma_data(vma, context);
2108         if (err)
2109                 goto err;
2110
2111         if (dyn_uar)
2112                 bfregi->sys_pages[idx] = uar_index;
2113         return 0;
2114
2115 err:
2116         if (!dyn_uar)
2117                 return err;
2118
2119         mlx5_cmd_free_uar(dev->mdev, idx);
2120
2121 free_bfreg:
2122         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2123
2124         return err;
2125 }
2126
2127 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2128 {
2129         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2130         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2131         unsigned long command;
2132         phys_addr_t pfn;
2133
2134         command = get_command(vma->vm_pgoff);
2135         switch (command) {
2136         case MLX5_IB_MMAP_WC_PAGE:
2137         case MLX5_IB_MMAP_NC_PAGE:
2138         case MLX5_IB_MMAP_REGULAR_PAGE:
2139         case MLX5_IB_MMAP_ALLOC_WC:
2140                 return uar_mmap(dev, command, vma, context);
2141
2142         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2143                 return -ENOSYS;
2144
2145         case MLX5_IB_MMAP_CORE_CLOCK:
2146                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2147                         return -EINVAL;
2148
2149                 if (vma->vm_flags & VM_WRITE)
2150                         return -EPERM;
2151
2152                 /* Don't expose to user-space information it shouldn't have */
2153                 if (PAGE_SIZE > 4096)
2154                         return -EOPNOTSUPP;
2155
2156                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2157                 pfn = (dev->mdev->iseg_base +
2158                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2159                         PAGE_SHIFT;
2160                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2161                                        PAGE_SIZE, vma->vm_page_prot))
2162                         return -EAGAIN;
2163
2164                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2165                             vma->vm_start,
2166                             (unsigned long long)pfn << PAGE_SHIFT);
2167                 break;
2168         case MLX5_IB_MMAP_CLOCK_INFO:
2169                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2170
2171         default:
2172                 return -EINVAL;
2173         }
2174
2175         return 0;
2176 }
2177
2178 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2179                                       struct ib_ucontext *context,
2180                                       struct ib_udata *udata)
2181 {
2182         struct mlx5_ib_alloc_pd_resp resp;
2183         struct mlx5_ib_pd *pd;
2184         int err;
2185
2186         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2187         if (!pd)
2188                 return ERR_PTR(-ENOMEM);
2189
2190         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2191         if (err) {
2192                 kfree(pd);
2193                 return ERR_PTR(err);
2194         }
2195
2196         if (context) {
2197                 resp.pdn = pd->pdn;
2198                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2199                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2200                         kfree(pd);
2201                         return ERR_PTR(-EFAULT);
2202                 }
2203         }
2204
2205         return &pd->ibpd;
2206 }
2207
2208 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2209 {
2210         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2211         struct mlx5_ib_pd *mpd = to_mpd(pd);
2212
2213         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2214         kfree(mpd);
2215
2216         return 0;
2217 }
2218
2219 enum {
2220         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2221         MATCH_CRITERIA_ENABLE_MISC_BIT,
2222         MATCH_CRITERIA_ENABLE_INNER_BIT
2223 };
2224
2225 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2226         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2227                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2228
2229 static u8 get_match_criteria_enable(u32 *match_criteria)
2230 {
2231         u8 match_criteria_enable;
2232
2233         match_criteria_enable =
2234                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2235                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2236         match_criteria_enable |=
2237                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2238                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2239         match_criteria_enable |=
2240                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2241                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2242
2243         return match_criteria_enable;
2244 }
2245
2246 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2247 {
2248         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2249         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2250 }
2251
2252 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2253                            bool inner)
2254 {
2255         if (inner) {
2256                 MLX5_SET(fte_match_set_misc,
2257                          misc_c, inner_ipv6_flow_label, mask);
2258                 MLX5_SET(fte_match_set_misc,
2259                          misc_v, inner_ipv6_flow_label, val);
2260         } else {
2261                 MLX5_SET(fte_match_set_misc,
2262                          misc_c, outer_ipv6_flow_label, mask);
2263                 MLX5_SET(fte_match_set_misc,
2264                          misc_v, outer_ipv6_flow_label, val);
2265         }
2266 }
2267
2268 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2269 {
2270         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2271         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2272         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2273         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2274 }
2275
2276 #define LAST_ETH_FIELD vlan_tag
2277 #define LAST_IB_FIELD sl
2278 #define LAST_IPV4_FIELD tos
2279 #define LAST_IPV6_FIELD traffic_class
2280 #define LAST_TCP_UDP_FIELD src_port
2281 #define LAST_TUNNEL_FIELD tunnel_id
2282 #define LAST_FLOW_TAG_FIELD tag_id
2283 #define LAST_DROP_FIELD size
2284
2285 /* Field is the last supported field */
2286 #define FIELDS_NOT_SUPPORTED(filter, field)\
2287         memchr_inv((void *)&filter.field  +\
2288                    sizeof(filter.field), 0,\
2289                    sizeof(filter) -\
2290                    offsetof(typeof(filter), field) -\
2291                    sizeof(filter.field))
2292
2293 #define IPV4_VERSION 4
2294 #define IPV6_VERSION 6
2295 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2296                            u32 *match_v, const union ib_flow_spec *ib_spec,
2297                            u32 *tag_id, bool *is_drop)
2298 {
2299         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2300                                            misc_parameters);
2301         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2302                                            misc_parameters);
2303         void *headers_c;
2304         void *headers_v;
2305         int match_ipv;
2306
2307         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2308                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2309                                          inner_headers);
2310                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2311                                          inner_headers);
2312                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2313                                         ft_field_support.inner_ip_version);
2314         } else {
2315                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2316                                          outer_headers);
2317                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2318                                          outer_headers);
2319                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2320                                         ft_field_support.outer_ip_version);
2321         }
2322
2323         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2324         case IB_FLOW_SPEC_ETH:
2325                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2326                         return -EOPNOTSUPP;
2327
2328                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2329                                              dmac_47_16),
2330                                 ib_spec->eth.mask.dst_mac);
2331                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2332                                              dmac_47_16),
2333                                 ib_spec->eth.val.dst_mac);
2334
2335                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2336                                              smac_47_16),
2337                                 ib_spec->eth.mask.src_mac);
2338                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2339                                              smac_47_16),
2340                                 ib_spec->eth.val.src_mac);
2341
2342                 if (ib_spec->eth.mask.vlan_tag) {
2343                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2344                                  cvlan_tag, 1);
2345                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2346                                  cvlan_tag, 1);
2347
2348                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2349                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2350                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2351                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2352
2353                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2354                                  first_cfi,
2355                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2356                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2357                                  first_cfi,
2358                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2359
2360                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2361                                  first_prio,
2362                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2363                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2364                                  first_prio,
2365                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2366                 }
2367                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2368                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2369                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2370                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2371                 break;
2372         case IB_FLOW_SPEC_IPV4:
2373                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2374                         return -EOPNOTSUPP;
2375
2376                 if (match_ipv) {
2377                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2378                                  ip_version, 0xf);
2379                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2380                                  ip_version, IPV4_VERSION);
2381                 } else {
2382                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2383                                  ethertype, 0xffff);
2384                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2385                                  ethertype, ETH_P_IP);
2386                 }
2387
2388                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2389                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2390                        &ib_spec->ipv4.mask.src_ip,
2391                        sizeof(ib_spec->ipv4.mask.src_ip));
2392                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2393                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2394                        &ib_spec->ipv4.val.src_ip,
2395                        sizeof(ib_spec->ipv4.val.src_ip));
2396                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2397                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2398                        &ib_spec->ipv4.mask.dst_ip,
2399                        sizeof(ib_spec->ipv4.mask.dst_ip));
2400                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2401                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2402                        &ib_spec->ipv4.val.dst_ip,
2403                        sizeof(ib_spec->ipv4.val.dst_ip));
2404
2405                 set_tos(headers_c, headers_v,
2406                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2407
2408                 set_proto(headers_c, headers_v,
2409                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2410                 break;
2411         case IB_FLOW_SPEC_IPV6:
2412                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2413                         return -EOPNOTSUPP;
2414
2415                 if (match_ipv) {
2416                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2417                                  ip_version, 0xf);
2418                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2419                                  ip_version, IPV6_VERSION);
2420                 } else {
2421                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2422                                  ethertype, 0xffff);
2423                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2424                                  ethertype, ETH_P_IPV6);
2425                 }
2426
2427                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2428                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2429                        &ib_spec->ipv6.mask.src_ip,
2430                        sizeof(ib_spec->ipv6.mask.src_ip));
2431                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2432                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2433                        &ib_spec->ipv6.val.src_ip,
2434                        sizeof(ib_spec->ipv6.val.src_ip));
2435                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2436                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2437                        &ib_spec->ipv6.mask.dst_ip,
2438                        sizeof(ib_spec->ipv6.mask.dst_ip));
2439                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2440                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2441                        &ib_spec->ipv6.val.dst_ip,
2442                        sizeof(ib_spec->ipv6.val.dst_ip));
2443
2444                 set_tos(headers_c, headers_v,
2445                         ib_spec->ipv6.mask.traffic_class,
2446                         ib_spec->ipv6.val.traffic_class);
2447
2448                 set_proto(headers_c, headers_v,
2449                           ib_spec->ipv6.mask.next_hdr,
2450                           ib_spec->ipv6.val.next_hdr);
2451
2452                 set_flow_label(misc_params_c, misc_params_v,
2453                                ntohl(ib_spec->ipv6.mask.flow_label),
2454                                ntohl(ib_spec->ipv6.val.flow_label),
2455                                ib_spec->type & IB_FLOW_SPEC_INNER);
2456
2457                 break;
2458         case IB_FLOW_SPEC_TCP:
2459                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2460                                          LAST_TCP_UDP_FIELD))
2461                         return -EOPNOTSUPP;
2462
2463                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2464                          0xff);
2465                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2466                          IPPROTO_TCP);
2467
2468                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2469                          ntohs(ib_spec->tcp_udp.mask.src_port));
2470                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2471                          ntohs(ib_spec->tcp_udp.val.src_port));
2472
2473                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2474                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2475                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2476                          ntohs(ib_spec->tcp_udp.val.dst_port));
2477                 break;
2478         case IB_FLOW_SPEC_UDP:
2479                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2480                                          LAST_TCP_UDP_FIELD))
2481                         return -EOPNOTSUPP;
2482
2483                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2484                          0xff);
2485                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2486                          IPPROTO_UDP);
2487
2488                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2489                          ntohs(ib_spec->tcp_udp.mask.src_port));
2490                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2491                          ntohs(ib_spec->tcp_udp.val.src_port));
2492
2493                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2494                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2495                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2496                          ntohs(ib_spec->tcp_udp.val.dst_port));
2497                 break;
2498         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2499                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2500                                          LAST_TUNNEL_FIELD))
2501                         return -EOPNOTSUPP;
2502
2503                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2504                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2505                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2506                          ntohl(ib_spec->tunnel.val.tunnel_id));
2507                 break;
2508         case IB_FLOW_SPEC_ACTION_TAG:
2509                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2510                                          LAST_FLOW_TAG_FIELD))
2511                         return -EOPNOTSUPP;
2512                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2513                         return -EINVAL;
2514
2515                 *tag_id = ib_spec->flow_tag.tag_id;
2516                 break;
2517         case IB_FLOW_SPEC_ACTION_DROP:
2518                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2519                                          LAST_DROP_FIELD))
2520                         return -EOPNOTSUPP;
2521                 *is_drop = true;
2522                 break;
2523         default:
2524                 return -EINVAL;
2525         }
2526
2527         return 0;
2528 }
2529
2530 /* If a flow could catch both multicast and unicast packets,
2531  * it won't fall into the multicast flow steering table and this rule
2532  * could steal other multicast packets.
2533  */
2534 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2535 {
2536         union ib_flow_spec *flow_spec;
2537
2538         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2539             ib_attr->num_of_specs < 1)
2540                 return false;
2541
2542         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2543         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2544                 struct ib_flow_spec_ipv4 *ipv4_spec;
2545
2546                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2547                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2548                         return true;
2549
2550                 return false;
2551         }
2552
2553         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2554                 struct ib_flow_spec_eth *eth_spec;
2555
2556                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2557                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2558                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2559         }
2560
2561         return false;
2562 }
2563
2564 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2565                                const struct ib_flow_attr *flow_attr,
2566                                bool check_inner)
2567 {
2568         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2569         int match_ipv = check_inner ?
2570                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2571                                         ft_field_support.inner_ip_version) :
2572                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2573                                         ft_field_support.outer_ip_version);
2574         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2575         bool ipv4_spec_valid, ipv6_spec_valid;
2576         unsigned int ip_spec_type = 0;
2577         bool has_ethertype = false;
2578         unsigned int spec_index;
2579         bool mask_valid = true;
2580         u16 eth_type = 0;
2581         bool type_valid;
2582
2583         /* Validate that ethertype is correct */
2584         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2585                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2586                     ib_spec->eth.mask.ether_type) {
2587                         mask_valid = (ib_spec->eth.mask.ether_type ==
2588                                       htons(0xffff));
2589                         has_ethertype = true;
2590                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2591                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2592                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2593                         ip_spec_type = ib_spec->type;
2594                 }
2595                 ib_spec = (void *)ib_spec + ib_spec->size;
2596         }
2597
2598         type_valid = (!has_ethertype) || (!ip_spec_type);
2599         if (!type_valid && mask_valid) {
2600                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2601                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2602                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2603                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2604
2605                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2606                              (((eth_type == ETH_P_MPLS_UC) ||
2607                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2608         }
2609
2610         return type_valid;
2611 }
2612
2613 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2614                           const struct ib_flow_attr *flow_attr)
2615 {
2616         return is_valid_ethertype(mdev, flow_attr, false) &&
2617                is_valid_ethertype(mdev, flow_attr, true);
2618 }
2619
2620 static void put_flow_table(struct mlx5_ib_dev *dev,
2621                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2622 {
2623         prio->refcount -= !!ft_added;
2624         if (!prio->refcount) {
2625                 mlx5_destroy_flow_table(prio->flow_table);
2626                 prio->flow_table = NULL;
2627         }
2628 }
2629
2630 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2631 {
2632         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2633         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2634                                                           struct mlx5_ib_flow_handler,
2635                                                           ibflow);
2636         struct mlx5_ib_flow_handler *iter, *tmp;
2637
2638         mutex_lock(&dev->flow_db.lock);
2639
2640         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2641                 mlx5_del_flow_rules(iter->rule);
2642                 put_flow_table(dev, iter->prio, true);
2643                 list_del(&iter->list);
2644                 kfree(iter);
2645         }
2646
2647         mlx5_del_flow_rules(handler->rule);
2648         put_flow_table(dev, handler->prio, true);
2649         mutex_unlock(&dev->flow_db.lock);
2650
2651         kfree(handler);
2652
2653         return 0;
2654 }
2655
2656 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2657 {
2658         priority *= 2;
2659         if (!dont_trap)
2660                 priority++;
2661         return priority;
2662 }
2663
2664 enum flow_table_type {
2665         MLX5_IB_FT_RX,
2666         MLX5_IB_FT_TX
2667 };
2668
2669 #define MLX5_FS_MAX_TYPES        6
2670 #define MLX5_FS_MAX_ENTRIES      BIT(16)
2671 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2672                                                 struct ib_flow_attr *flow_attr,
2673                                                 enum flow_table_type ft_type)
2674 {
2675         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2676         struct mlx5_flow_namespace *ns = NULL;
2677         struct mlx5_ib_flow_prio *prio;
2678         struct mlx5_flow_table *ft;
2679         int max_table_size;
2680         int num_entries;
2681         int num_groups;
2682         int priority;
2683         int err = 0;
2684
2685         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2686                                                        log_max_ft_size));
2687         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2688                 if (flow_is_multicast_only(flow_attr) &&
2689                     !dont_trap)
2690                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2691                 else
2692                         priority = ib_prio_to_core_prio(flow_attr->priority,
2693                                                         dont_trap);
2694                 ns = mlx5_get_flow_namespace(dev->mdev,
2695                                              MLX5_FLOW_NAMESPACE_BYPASS);
2696                 num_entries = MLX5_FS_MAX_ENTRIES;
2697                 num_groups = MLX5_FS_MAX_TYPES;
2698                 prio = &dev->flow_db.prios[priority];
2699         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2700                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2701                 ns = mlx5_get_flow_namespace(dev->mdev,
2702                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2703                 build_leftovers_ft_param(&priority,
2704                                          &num_entries,
2705                                          &num_groups);
2706                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2707         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2708                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2709                                         allow_sniffer_and_nic_rx_shared_tir))
2710                         return ERR_PTR(-ENOTSUPP);
2711
2712                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2713                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2714                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2715
2716                 prio = &dev->flow_db.sniffer[ft_type];
2717                 priority = 0;
2718                 num_entries = 1;
2719                 num_groups = 1;
2720         }
2721
2722         if (!ns)
2723                 return ERR_PTR(-ENOTSUPP);
2724
2725         if (num_entries > max_table_size)
2726                 return ERR_PTR(-ENOMEM);
2727
2728         ft = prio->flow_table;
2729         if (!ft) {
2730                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2731                                                          num_entries,
2732                                                          num_groups,
2733                                                          0, 0);
2734
2735                 if (!IS_ERR(ft)) {
2736                         prio->refcount = 0;
2737                         prio->flow_table = ft;
2738                 } else {
2739                         err = PTR_ERR(ft);
2740                 }
2741         }
2742
2743         return err ? ERR_PTR(err) : prio;
2744 }
2745
2746 static void set_underlay_qp(struct mlx5_ib_dev *dev,
2747                             struct mlx5_flow_spec *spec,
2748                             u32 underlay_qpn)
2749 {
2750         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2751                                            spec->match_criteria,
2752                                            misc_parameters);
2753         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2754                                            misc_parameters);
2755
2756         if (underlay_qpn &&
2757             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2758                                       ft_field_support.bth_dst_qp)) {
2759                 MLX5_SET(fte_match_set_misc,
2760                          misc_params_v, bth_dst_qp, underlay_qpn);
2761                 MLX5_SET(fte_match_set_misc,
2762                          misc_params_c, bth_dst_qp, 0xffffff);
2763         }
2764 }
2765
2766 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2767                                                       struct mlx5_ib_flow_prio *ft_prio,
2768                                                       const struct ib_flow_attr *flow_attr,
2769                                                       struct mlx5_flow_destination *dst,
2770                                                       u32 underlay_qpn)
2771 {
2772         struct mlx5_flow_table  *ft = ft_prio->flow_table;
2773         struct mlx5_ib_flow_handler *handler;
2774         struct mlx5_flow_act flow_act = {0};
2775         struct mlx5_flow_spec *spec;
2776         struct mlx5_flow_destination *rule_dst = dst;
2777         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2778         unsigned int spec_index;
2779         u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2780         bool is_drop = false;
2781         int err = 0;
2782         int dest_num = 1;
2783
2784         if (!is_valid_attr(dev->mdev, flow_attr))
2785                 return ERR_PTR(-EINVAL);
2786
2787         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2788         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2789         if (!handler || !spec) {
2790                 err = -ENOMEM;
2791                 goto free;
2792         }
2793
2794         INIT_LIST_HEAD(&handler->list);
2795
2796         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2797                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2798                                       spec->match_value,
2799                                       ib_flow, &flow_tag, &is_drop);
2800                 if (err < 0)
2801                         goto free;
2802
2803                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2804         }
2805
2806         if (!flow_is_multicast_only(flow_attr))
2807                 set_underlay_qp(dev, spec, underlay_qpn);
2808
2809         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2810         if (is_drop) {
2811                 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2812                 rule_dst = NULL;
2813                 dest_num = 0;
2814         } else {
2815                 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2816                     MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2817         }
2818
2819         if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2820             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2821              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2822                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2823                              flow_tag, flow_attr->type);
2824                 err = -EINVAL;
2825                 goto free;
2826         }
2827         flow_act.flow_tag = flow_tag;
2828         handler->rule = mlx5_add_flow_rules(ft, spec,
2829                                             &flow_act,
2830                                             rule_dst, dest_num);
2831
2832         if (IS_ERR(handler->rule)) {
2833                 err = PTR_ERR(handler->rule);
2834                 goto free;
2835         }
2836
2837         ft_prio->refcount++;
2838         handler->prio = ft_prio;
2839
2840         ft_prio->flow_table = ft;
2841 free:
2842         if (err)
2843                 kfree(handler);
2844         kvfree(spec);
2845         return err ? ERR_PTR(err) : handler;
2846 }
2847
2848 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2849                                                      struct mlx5_ib_flow_prio *ft_prio,
2850                                                      const struct ib_flow_attr *flow_attr,
2851                                                      struct mlx5_flow_destination *dst)
2852 {
2853         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2854 }
2855
2856 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2857                                                           struct mlx5_ib_flow_prio *ft_prio,
2858                                                           struct ib_flow_attr *flow_attr,
2859                                                           struct mlx5_flow_destination *dst)
2860 {
2861         struct mlx5_ib_flow_handler *handler_dst = NULL;
2862         struct mlx5_ib_flow_handler *handler = NULL;
2863
2864         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2865         if (!IS_ERR(handler)) {
2866                 handler_dst = create_flow_rule(dev, ft_prio,
2867                                                flow_attr, dst);
2868                 if (IS_ERR(handler_dst)) {
2869                         mlx5_del_flow_rules(handler->rule);
2870                         ft_prio->refcount--;
2871                         kfree(handler);
2872                         handler = handler_dst;
2873                 } else {
2874                         list_add(&handler_dst->list, &handler->list);
2875                 }
2876         }
2877
2878         return handler;
2879 }
2880 enum {
2881         LEFTOVERS_MC,
2882         LEFTOVERS_UC,
2883 };
2884
2885 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2886                                                           struct mlx5_ib_flow_prio *ft_prio,
2887                                                           struct ib_flow_attr *flow_attr,
2888                                                           struct mlx5_flow_destination *dst)
2889 {
2890         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2891         struct mlx5_ib_flow_handler *handler = NULL;
2892
2893         static struct {
2894                 struct ib_flow_attr     flow_attr;
2895                 struct ib_flow_spec_eth eth_flow;
2896         } leftovers_specs[] = {
2897                 [LEFTOVERS_MC] = {
2898                         .flow_attr = {
2899                                 .num_of_specs = 1,
2900                                 .size = sizeof(leftovers_specs[0])
2901                         },
2902                         .eth_flow = {
2903                                 .type = IB_FLOW_SPEC_ETH,
2904                                 .size = sizeof(struct ib_flow_spec_eth),
2905                                 .mask = {.dst_mac = {0x1} },
2906                                 .val =  {.dst_mac = {0x1} }
2907                         }
2908                 },
2909                 [LEFTOVERS_UC] = {
2910                         .flow_attr = {
2911                                 .num_of_specs = 1,
2912                                 .size = sizeof(leftovers_specs[0])
2913                         },
2914                         .eth_flow = {
2915                                 .type = IB_FLOW_SPEC_ETH,
2916                                 .size = sizeof(struct ib_flow_spec_eth),
2917                                 .mask = {.dst_mac = {0x1} },
2918                                 .val = {.dst_mac = {} }
2919                         }
2920                 }
2921         };
2922
2923         handler = create_flow_rule(dev, ft_prio,
2924                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2925                                    dst);
2926         if (!IS_ERR(handler) &&
2927             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2928                 handler_ucast = create_flow_rule(dev, ft_prio,
2929                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2930                                                  dst);
2931                 if (IS_ERR(handler_ucast)) {
2932                         mlx5_del_flow_rules(handler->rule);
2933                         ft_prio->refcount--;
2934                         kfree(handler);
2935                         handler = handler_ucast;
2936                 } else {
2937                         list_add(&handler_ucast->list, &handler->list);
2938                 }
2939         }
2940
2941         return handler;
2942 }
2943
2944 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2945                                                         struct mlx5_ib_flow_prio *ft_rx,
2946                                                         struct mlx5_ib_flow_prio *ft_tx,
2947                                                         struct mlx5_flow_destination *dst)
2948 {
2949         struct mlx5_ib_flow_handler *handler_rx;
2950         struct mlx5_ib_flow_handler *handler_tx;
2951         int err;
2952         static const struct ib_flow_attr flow_attr  = {
2953                 .num_of_specs = 0,
2954                 .size = sizeof(flow_attr)
2955         };
2956
2957         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2958         if (IS_ERR(handler_rx)) {
2959                 err = PTR_ERR(handler_rx);
2960                 goto err;
2961         }
2962
2963         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2964         if (IS_ERR(handler_tx)) {
2965                 err = PTR_ERR(handler_tx);
2966                 goto err_tx;
2967         }
2968
2969         list_add(&handler_tx->list, &handler_rx->list);
2970
2971         return handler_rx;
2972
2973 err_tx:
2974         mlx5_del_flow_rules(handler_rx->rule);
2975         ft_rx->refcount--;
2976         kfree(handler_rx);
2977 err:
2978         return ERR_PTR(err);
2979 }
2980
2981 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2982                                            struct ib_flow_attr *flow_attr,
2983                                            int domain)
2984 {
2985         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2986         struct mlx5_ib_qp *mqp = to_mqp(qp);
2987         struct mlx5_ib_flow_handler *handler = NULL;
2988         struct mlx5_flow_destination *dst = NULL;
2989         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2990         struct mlx5_ib_flow_prio *ft_prio;
2991         int err;
2992         int underlay_qpn;
2993
2994         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2995                 return ERR_PTR(-ENOMEM);
2996
2997         if (domain != IB_FLOW_DOMAIN_USER ||
2998             flow_attr->port > dev->num_ports ||
2999             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
3000                 return ERR_PTR(-EINVAL);
3001
3002         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3003         if (!dst)
3004                 return ERR_PTR(-ENOMEM);
3005
3006         mutex_lock(&dev->flow_db.lock);
3007
3008         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
3009         if (IS_ERR(ft_prio)) {
3010                 err = PTR_ERR(ft_prio);
3011                 goto unlock;
3012         }
3013         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3014                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3015                 if (IS_ERR(ft_prio_tx)) {
3016                         err = PTR_ERR(ft_prio_tx);
3017                         ft_prio_tx = NULL;
3018                         goto destroy_ft;
3019                 }
3020         }
3021
3022         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3023         if (mqp->flags & MLX5_IB_QP_RSS)
3024                 dst->tir_num = mqp->rss_qp.tirn;
3025         else
3026                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3027
3028         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3029                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3030                         handler = create_dont_trap_rule(dev, ft_prio,
3031                                                         flow_attr, dst);
3032                 } else {
3033                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3034                                         mqp->underlay_qpn : 0;
3035                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3036                                                     dst, underlay_qpn);
3037                 }
3038         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3039                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3040                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3041                                                 dst);
3042         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3043                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3044         } else {
3045                 err = -EINVAL;
3046                 goto destroy_ft;
3047         }
3048
3049         if (IS_ERR(handler)) {
3050                 err = PTR_ERR(handler);
3051                 handler = NULL;
3052                 goto destroy_ft;
3053         }
3054
3055         mutex_unlock(&dev->flow_db.lock);
3056         kfree(dst);
3057
3058         return &handler->ibflow;
3059
3060 destroy_ft:
3061         put_flow_table(dev, ft_prio, false);
3062         if (ft_prio_tx)
3063                 put_flow_table(dev, ft_prio_tx, false);
3064 unlock:
3065         mutex_unlock(&dev->flow_db.lock);
3066         kfree(dst);
3067         kfree(handler);
3068         return ERR_PTR(err);
3069 }
3070
3071 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3072 {
3073         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3074         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
3075         int err;
3076
3077         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3078                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3079                 return -EOPNOTSUPP;
3080         }
3081
3082         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
3083         if (err)
3084                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3085                              ibqp->qp_num, gid->raw);
3086
3087         return err;
3088 }
3089
3090 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3091 {
3092         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3093         int err;
3094
3095         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
3096         if (err)
3097                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3098                              ibqp->qp_num, gid->raw);
3099
3100         return err;
3101 }
3102
3103 static int init_node_data(struct mlx5_ib_dev *dev)
3104 {
3105         int err;
3106
3107         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
3108         if (err)
3109                 return err;
3110
3111         dev->mdev->rev_id = dev->mdev->pdev->revision;
3112
3113         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
3114 }
3115
3116 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3117                              char *buf)
3118 {
3119         struct mlx5_ib_dev *dev =
3120                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3121
3122         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
3123 }
3124
3125 static ssize_t show_reg_pages(struct device *device,
3126                               struct device_attribute *attr, char *buf)
3127 {
3128         struct mlx5_ib_dev *dev =
3129                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3130
3131         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
3132 }
3133
3134 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3135                         char *buf)
3136 {
3137         struct mlx5_ib_dev *dev =
3138                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3139         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
3140 }
3141
3142 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3143                         char *buf)
3144 {
3145         struct mlx5_ib_dev *dev =
3146                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3147         return sprintf(buf, "%x\n", dev->mdev->rev_id);
3148 }
3149
3150 static ssize_t show_board(struct device *device, struct device_attribute *attr,
3151                           char *buf)
3152 {
3153         struct mlx5_ib_dev *dev =
3154                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3155         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
3156                        dev->mdev->board_id);
3157 }
3158
3159 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
3160 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
3161 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
3162 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3163 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3164
3165 static struct device_attribute *mlx5_class_attributes[] = {
3166         &dev_attr_hw_rev,
3167         &dev_attr_hca_type,
3168         &dev_attr_board_id,
3169         &dev_attr_fw_pages,
3170         &dev_attr_reg_pages,
3171 };
3172
3173 static void pkey_change_handler(struct work_struct *work)
3174 {
3175         struct mlx5_ib_port_resources *ports =
3176                 container_of(work, struct mlx5_ib_port_resources,
3177                              pkey_change_work);
3178
3179         mutex_lock(&ports->devr->mutex);
3180         mlx5_ib_gsi_pkey_change(ports->gsi);
3181         mutex_unlock(&ports->devr->mutex);
3182 }
3183
3184 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3185 {
3186         struct mlx5_ib_qp *mqp;
3187         struct mlx5_ib_cq *send_mcq, *recv_mcq;
3188         struct mlx5_core_cq *mcq;
3189         struct list_head cq_armed_list;
3190         unsigned long flags_qp;
3191         unsigned long flags_cq;
3192         unsigned long flags;
3193
3194         INIT_LIST_HEAD(&cq_armed_list);
3195
3196         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3197         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3198         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3199                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3200                 if (mqp->sq.tail != mqp->sq.head) {
3201                         send_mcq = to_mcq(mqp->ibqp.send_cq);
3202                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
3203                         if (send_mcq->mcq.comp &&
3204                             mqp->ibqp.send_cq->comp_handler) {
3205                                 if (!send_mcq->mcq.reset_notify_added) {
3206                                         send_mcq->mcq.reset_notify_added = 1;
3207                                         list_add_tail(&send_mcq->mcq.reset_notify,
3208                                                       &cq_armed_list);
3209                                 }
3210                         }
3211                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3212                 }
3213                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3214                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3215                 /* no handling is needed for SRQ */
3216                 if (!mqp->ibqp.srq) {
3217                         if (mqp->rq.tail != mqp->rq.head) {
3218                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3219                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3220                                 if (recv_mcq->mcq.comp &&
3221                                     mqp->ibqp.recv_cq->comp_handler) {
3222                                         if (!recv_mcq->mcq.reset_notify_added) {
3223                                                 recv_mcq->mcq.reset_notify_added = 1;
3224                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
3225                                                               &cq_armed_list);
3226                                         }
3227                                 }
3228                                 spin_unlock_irqrestore(&recv_mcq->lock,
3229                                                        flags_cq);
3230                         }
3231                 }
3232                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3233         }
3234         /*At that point all inflight post send were put to be executed as of we
3235          * lock/unlock above locks Now need to arm all involved CQs.
3236          */
3237         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3238                 mcq->comp(mcq);
3239         }
3240         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3241 }
3242
3243 static void delay_drop_handler(struct work_struct *work)
3244 {
3245         int err;
3246         struct mlx5_ib_delay_drop *delay_drop =
3247                 container_of(work, struct mlx5_ib_delay_drop,
3248                              delay_drop_work);
3249
3250         atomic_inc(&delay_drop->events_cnt);
3251
3252         mutex_lock(&delay_drop->lock);
3253         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3254                                        delay_drop->timeout);
3255         if (err) {
3256                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3257                              delay_drop->timeout);
3258                 delay_drop->activate = false;
3259         }
3260         mutex_unlock(&delay_drop->lock);
3261 }
3262
3263 static void mlx5_ib_handle_event(struct work_struct *_work)
3264 {
3265         struct mlx5_ib_event_work *work =
3266                 container_of(_work, struct mlx5_ib_event_work, work);
3267         struct mlx5_ib_dev *ibdev;
3268         struct ib_event ibev;
3269         bool fatal = false;
3270         u8 port = (u8)work->param;
3271
3272         if (mlx5_core_is_mp_slave(work->dev)) {
3273                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3274                 if (!ibdev)
3275                         goto out;
3276         } else {
3277                 ibdev = work->context;
3278         }
3279
3280         switch (work->event) {
3281         case MLX5_DEV_EVENT_SYS_ERROR:
3282                 ibev.event = IB_EVENT_DEVICE_FATAL;
3283                 mlx5_ib_handle_internal_error(ibdev);
3284                 fatal = true;
3285                 break;
3286
3287         case MLX5_DEV_EVENT_PORT_UP:
3288         case MLX5_DEV_EVENT_PORT_DOWN:
3289         case MLX5_DEV_EVENT_PORT_INITIALIZED:
3290                 /* In RoCE, port up/down events are handled in
3291                  * mlx5_netdev_event().
3292                  */
3293                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3294                         IB_LINK_LAYER_ETHERNET)
3295                         goto out;
3296
3297                 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
3298                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3299                 break;
3300
3301         case MLX5_DEV_EVENT_LID_CHANGE:
3302                 ibev.event = IB_EVENT_LID_CHANGE;
3303                 break;
3304
3305         case MLX5_DEV_EVENT_PKEY_CHANGE:
3306                 ibev.event = IB_EVENT_PKEY_CHANGE;
3307                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
3308                 break;
3309
3310         case MLX5_DEV_EVENT_GUID_CHANGE:
3311                 ibev.event = IB_EVENT_GID_CHANGE;
3312                 break;
3313
3314         case MLX5_DEV_EVENT_CLIENT_REREG:
3315                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
3316                 break;
3317         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3318                 schedule_work(&ibdev->delay_drop.delay_drop_work);
3319                 goto out;
3320         default:
3321                 goto out;
3322         }
3323
3324         ibev.device           = &ibdev->ib_dev;
3325         ibev.element.port_num = port;
3326
3327         if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
3328                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
3329                 goto out;
3330         }
3331
3332         if (ibdev->ib_active)
3333                 ib_dispatch_event(&ibev);
3334
3335         if (fatal)
3336                 ibdev->ib_active = false;
3337 out:
3338         kfree(work);
3339 }
3340
3341 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3342                           enum mlx5_dev_event event, unsigned long param)
3343 {
3344         struct mlx5_ib_event_work *work;
3345
3346         work = kmalloc(sizeof(*work), GFP_ATOMIC);
3347         if (!work)
3348                 return;
3349
3350         INIT_WORK(&work->work, mlx5_ib_handle_event);
3351         work->dev = dev;
3352         work->param = param;
3353         work->context = context;
3354         work->event = event;
3355
3356         queue_work(mlx5_ib_event_wq, &work->work);
3357 }
3358
3359 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3360 {
3361         struct mlx5_hca_vport_context vport_ctx;
3362         int err;
3363         int port;
3364
3365         for (port = 1; port <= dev->num_ports; port++) {
3366                 dev->mdev->port_caps[port - 1].has_smi = false;
3367                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3368                     MLX5_CAP_PORT_TYPE_IB) {
3369                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3370                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3371                                                                    port, 0,
3372                                                                    &vport_ctx);
3373                                 if (err) {
3374                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3375                                                     port, err);
3376                                         return err;
3377                                 }
3378                                 dev->mdev->port_caps[port - 1].has_smi =
3379                                         vport_ctx.has_smi;
3380                         } else {
3381                                 dev->mdev->port_caps[port - 1].has_smi = true;
3382                         }
3383                 }
3384         }
3385         return 0;
3386 }
3387
3388 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3389 {
3390         int port;
3391
3392         for (port = 1; port <= dev->num_ports; port++)
3393                 mlx5_query_ext_port_caps(dev, port);
3394 }
3395
3396 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
3397 {
3398         struct ib_device_attr *dprops = NULL;
3399         struct ib_port_attr *pprops = NULL;
3400         int err = -ENOMEM;
3401         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
3402
3403         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3404         if (!pprops)
3405                 goto out;
3406
3407         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3408         if (!dprops)
3409                 goto out;
3410
3411         err = set_has_smi_cap(dev);
3412         if (err)
3413                 goto out;
3414
3415         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3416         if (err) {
3417                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3418                 goto out;
3419         }
3420
3421         memset(pprops, 0, sizeof(*pprops));
3422         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3423         if (err) {
3424                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3425                              port, err);
3426                 goto out;
3427         }
3428
3429         dev->mdev->port_caps[port - 1].pkey_table_len =
3430                                         dprops->max_pkeys;
3431         dev->mdev->port_caps[port - 1].gid_table_len =
3432                                         pprops->gid_tbl_len;
3433         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3434                     port, dprops->max_pkeys, pprops->gid_tbl_len);
3435
3436 out:
3437         kfree(pprops);
3438         kfree(dprops);
3439
3440         return err;
3441 }
3442
3443 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3444 {
3445         int err;
3446
3447         err = mlx5_mr_cache_cleanup(dev);
3448         if (err)
3449                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3450
3451         if (dev->umrc.qp)
3452                 mlx5_ib_destroy_qp(dev->umrc.qp);
3453         if (dev->umrc.cq)
3454                 ib_free_cq(dev->umrc.cq);
3455         if (dev->umrc.pd)
3456                 ib_dealloc_pd(dev->umrc.pd);
3457 }
3458
3459 enum {
3460         MAX_UMR_WR = 128,
3461 };
3462
3463 static int create_umr_res(struct mlx5_ib_dev *dev)
3464 {
3465         struct ib_qp_init_attr *init_attr = NULL;
3466         struct ib_qp_attr *attr = NULL;
3467         struct ib_pd *pd;
3468         struct ib_cq *cq;
3469         struct ib_qp *qp;
3470         int ret;
3471
3472         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3473         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3474         if (!attr || !init_attr) {
3475                 ret = -ENOMEM;
3476                 goto error_0;
3477         }
3478
3479         pd = ib_alloc_pd(&dev->ib_dev, 0);
3480         if (IS_ERR(pd)) {
3481                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3482                 ret = PTR_ERR(pd);
3483                 goto error_0;
3484         }
3485
3486         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3487         if (IS_ERR(cq)) {
3488                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3489                 ret = PTR_ERR(cq);
3490                 goto error_2;
3491         }
3492
3493         init_attr->send_cq = cq;
3494         init_attr->recv_cq = cq;
3495         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3496         init_attr->cap.max_send_wr = MAX_UMR_WR;
3497         init_attr->cap.max_send_sge = 1;
3498         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3499         init_attr->port_num = 1;
3500         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3501         if (IS_ERR(qp)) {
3502                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3503                 ret = PTR_ERR(qp);
3504                 goto error_3;
3505         }
3506         qp->device     = &dev->ib_dev;
3507         qp->real_qp    = qp;
3508         qp->uobject    = NULL;
3509         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
3510         qp->send_cq    = init_attr->send_cq;
3511         qp->recv_cq    = init_attr->recv_cq;
3512
3513         attr->qp_state = IB_QPS_INIT;
3514         attr->port_num = 1;
3515         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3516                                 IB_QP_PORT, NULL);
3517         if (ret) {
3518                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3519                 goto error_4;
3520         }
3521
3522         memset(attr, 0, sizeof(*attr));
3523         attr->qp_state = IB_QPS_RTR;
3524         attr->path_mtu = IB_MTU_256;
3525
3526         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3527         if (ret) {
3528                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3529                 goto error_4;
3530         }
3531
3532         memset(attr, 0, sizeof(*attr));
3533         attr->qp_state = IB_QPS_RTS;
3534         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3535         if (ret) {
3536                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3537                 goto error_4;
3538         }
3539
3540         dev->umrc.qp = qp;
3541         dev->umrc.cq = cq;
3542         dev->umrc.pd = pd;
3543
3544         sema_init(&dev->umrc.sem, MAX_UMR_WR);
3545         ret = mlx5_mr_cache_init(dev);
3546         if (ret) {
3547                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3548                 goto error_4;
3549         }
3550
3551         kfree(attr);
3552         kfree(init_attr);
3553
3554         return 0;
3555
3556 error_4:
3557         mlx5_ib_destroy_qp(qp);
3558         dev->umrc.qp = NULL;
3559
3560 error_3:
3561         ib_free_cq(cq);
3562         dev->umrc.cq = NULL;
3563
3564 error_2:
3565         ib_dealloc_pd(pd);
3566         dev->umrc.pd = NULL;
3567
3568 error_0:
3569         kfree(attr);
3570         kfree(init_attr);
3571         return ret;
3572 }
3573
3574 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3575 {
3576         switch (umr_fence_cap) {
3577         case MLX5_CAP_UMR_FENCE_NONE:
3578                 return MLX5_FENCE_MODE_NONE;
3579         case MLX5_CAP_UMR_FENCE_SMALL:
3580                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3581         default:
3582                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3583         }
3584 }
3585
3586 static int create_dev_resources(struct mlx5_ib_resources *devr)
3587 {
3588         struct ib_srq_init_attr attr;
3589         struct mlx5_ib_dev *dev;
3590         struct ib_cq_init_attr cq_attr = {.cqe = 1};
3591         int port;
3592         int ret = 0;
3593
3594         dev = container_of(devr, struct mlx5_ib_dev, devr);
3595
3596         mutex_init(&devr->mutex);
3597
3598         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3599         if (IS_ERR(devr->p0)) {
3600                 ret = PTR_ERR(devr->p0);
3601                 goto error0;
3602         }
3603         devr->p0->device  = &dev->ib_dev;
3604         devr->p0->uobject = NULL;
3605         atomic_set(&devr->p0->usecnt, 0);
3606
3607         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3608         if (IS_ERR(devr->c0)) {
3609                 ret = PTR_ERR(devr->c0);
3610                 goto error1;
3611         }
3612         devr->c0->device        = &dev->ib_dev;
3613         devr->c0->uobject       = NULL;
3614         devr->c0->comp_handler  = NULL;
3615         devr->c0->event_handler = NULL;
3616         devr->c0->cq_context    = NULL;
3617         atomic_set(&devr->c0->usecnt, 0);
3618
3619         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3620         if (IS_ERR(devr->x0)) {
3621                 ret = PTR_ERR(devr->x0);
3622                 goto error2;
3623         }
3624         devr->x0->device = &dev->ib_dev;
3625         devr->x0->inode = NULL;
3626         atomic_set(&devr->x0->usecnt, 0);
3627         mutex_init(&devr->x0->tgt_qp_mutex);
3628         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3629
3630         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3631         if (IS_ERR(devr->x1)) {
3632                 ret = PTR_ERR(devr->x1);
3633                 goto error3;
3634         }
3635         devr->x1->device = &dev->ib_dev;
3636         devr->x1->inode = NULL;
3637         atomic_set(&devr->x1->usecnt, 0);
3638         mutex_init(&devr->x1->tgt_qp_mutex);
3639         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3640
3641         memset(&attr, 0, sizeof(attr));
3642         attr.attr.max_sge = 1;
3643         attr.attr.max_wr = 1;
3644         attr.srq_type = IB_SRQT_XRC;
3645         attr.ext.cq = devr->c0;
3646         attr.ext.xrc.xrcd = devr->x0;
3647
3648         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3649         if (IS_ERR(devr->s0)) {
3650                 ret = PTR_ERR(devr->s0);
3651                 goto error4;
3652         }
3653         devr->s0->device        = &dev->ib_dev;
3654         devr->s0->pd            = devr->p0;
3655         devr->s0->uobject       = NULL;
3656         devr->s0->event_handler = NULL;
3657         devr->s0->srq_context   = NULL;
3658         devr->s0->srq_type      = IB_SRQT_XRC;
3659         devr->s0->ext.xrc.xrcd  = devr->x0;
3660         devr->s0->ext.cq        = devr->c0;
3661         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3662         atomic_inc(&devr->s0->ext.cq->usecnt);
3663         atomic_inc(&devr->p0->usecnt);
3664         atomic_set(&devr->s0->usecnt, 0);
3665
3666         memset(&attr, 0, sizeof(attr));
3667         attr.attr.max_sge = 1;
3668         attr.attr.max_wr = 1;
3669         attr.srq_type = IB_SRQT_BASIC;
3670         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3671         if (IS_ERR(devr->s1)) {
3672                 ret = PTR_ERR(devr->s1);
3673                 goto error5;
3674         }
3675         devr->s1->device        = &dev->ib_dev;
3676         devr->s1->pd            = devr->p0;
3677         devr->s1->uobject       = NULL;
3678         devr->s1->event_handler = NULL;
3679         devr->s1->srq_context   = NULL;
3680         devr->s1->srq_type      = IB_SRQT_BASIC;
3681         devr->s1->ext.cq        = devr->c0;
3682         atomic_inc(&devr->p0->usecnt);
3683         atomic_set(&devr->s1->usecnt, 0);
3684
3685         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3686                 INIT_WORK(&devr->ports[port].pkey_change_work,
3687                           pkey_change_handler);
3688                 devr->ports[port].devr = devr;
3689         }
3690
3691         return 0;
3692
3693 error5:
3694         mlx5_ib_destroy_srq(devr->s0);
3695 error4:
3696         mlx5_ib_dealloc_xrcd(devr->x1);
3697 error3:
3698         mlx5_ib_dealloc_xrcd(devr->x0);
3699 error2:
3700         mlx5_ib_destroy_cq(devr->c0);
3701 error1:
3702         mlx5_ib_dealloc_pd(devr->p0);
3703 error0:
3704         return ret;
3705 }
3706
3707 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3708 {
3709         struct mlx5_ib_dev *dev =
3710                 container_of(devr, struct mlx5_ib_dev, devr);
3711         int port;
3712
3713         mlx5_ib_destroy_srq(devr->s1);
3714         mlx5_ib_destroy_srq(devr->s0);
3715         mlx5_ib_dealloc_xrcd(devr->x0);
3716         mlx5_ib_dealloc_xrcd(devr->x1);
3717         mlx5_ib_destroy_cq(devr->c0);
3718         mlx5_ib_dealloc_pd(devr->p0);
3719
3720         /* Make sure no change P_Key work items are still executing */
3721         for (port = 0; port < dev->num_ports; ++port)
3722                 cancel_work_sync(&devr->ports[port].pkey_change_work);
3723 }
3724
3725 static u32 get_core_cap_flags(struct ib_device *ibdev)
3726 {
3727         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3728         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3729         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3730         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3731         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3732         u32 ret = 0;
3733
3734         if (ll == IB_LINK_LAYER_INFINIBAND)
3735                 return RDMA_CORE_PORT_IBA_IB;
3736
3737         if (raw_support)
3738                 ret = RDMA_CORE_PORT_RAW_PACKET;
3739
3740         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3741                 return ret;
3742
3743         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3744                 return ret;
3745
3746         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3747                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3748
3749         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3750                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3751
3752         return ret;
3753 }
3754
3755 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3756                                struct ib_port_immutable *immutable)
3757 {
3758         struct ib_port_attr attr;
3759         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3760         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3761         int err;
3762
3763         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3764
3765         err = ib_query_port(ibdev, port_num, &attr);
3766         if (err)
3767                 return err;
3768
3769         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3770         immutable->gid_tbl_len = attr.gid_tbl_len;
3771         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3772         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3773                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3774
3775         return 0;
3776 }
3777
3778 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3779 {
3780         struct mlx5_ib_dev *dev =
3781                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3782         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3783                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3784                  fw_rev_sub(dev->mdev));
3785 }
3786
3787 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3788 {
3789         struct mlx5_core_dev *mdev = dev->mdev;
3790         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3791                                                                  MLX5_FLOW_NAMESPACE_LAG);
3792         struct mlx5_flow_table *ft;
3793         int err;
3794
3795         if (!ns || !mlx5_lag_is_active(mdev))
3796                 return 0;
3797
3798         err = mlx5_cmd_create_vport_lag(mdev);
3799         if (err)
3800                 return err;
3801
3802         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3803         if (IS_ERR(ft)) {
3804                 err = PTR_ERR(ft);
3805                 goto err_destroy_vport_lag;
3806         }
3807
3808         dev->flow_db.lag_demux_ft = ft;
3809         return 0;
3810
3811 err_destroy_vport_lag:
3812         mlx5_cmd_destroy_vport_lag(mdev);
3813         return err;
3814 }
3815
3816 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3817 {
3818         struct mlx5_core_dev *mdev = dev->mdev;
3819
3820         if (dev->flow_db.lag_demux_ft) {
3821                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3822                 dev->flow_db.lag_demux_ft = NULL;
3823
3824                 mlx5_cmd_destroy_vport_lag(mdev);
3825         }
3826 }
3827
3828 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3829 {
3830         int err;
3831
3832         dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
3833         err = register_netdevice_notifier(&dev->roce[port_num].nb);
3834         if (err) {
3835                 dev->roce[port_num].nb.notifier_call = NULL;
3836                 return err;
3837         }
3838
3839         return 0;
3840 }
3841
3842 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3843 {
3844         if (dev->roce[port_num].nb.notifier_call) {
3845                 unregister_netdevice_notifier(&dev->roce[port_num].nb);
3846                 dev->roce[port_num].nb.notifier_call = NULL;
3847         }
3848 }
3849
3850 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
3851 {
3852         int err;
3853
3854         err = mlx5_add_netdev_notifier(dev, port_num);
3855         if (err)
3856                 return err;
3857
3858         if (MLX5_CAP_GEN(dev->mdev, roce)) {
3859                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3860                 if (err)
3861                         goto err_unregister_netdevice_notifier;
3862         }
3863
3864         err = mlx5_eth_lag_init(dev);
3865         if (err)
3866                 goto err_disable_roce;
3867
3868         return 0;
3869
3870 err_disable_roce:
3871         if (MLX5_CAP_GEN(dev->mdev, roce))
3872                 mlx5_nic_vport_disable_roce(dev->mdev);
3873
3874 err_unregister_netdevice_notifier:
3875         mlx5_remove_netdev_notifier(dev, port_num);
3876         return err;
3877 }
3878
3879 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3880 {
3881         mlx5_eth_lag_cleanup(dev);
3882         if (MLX5_CAP_GEN(dev->mdev, roce))
3883                 mlx5_nic_vport_disable_roce(dev->mdev);
3884 }
3885
3886 struct mlx5_ib_counter {
3887         const char *name;
3888         size_t offset;
3889 };
3890
3891 #define INIT_Q_COUNTER(_name)           \
3892         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3893
3894 static const struct mlx5_ib_counter basic_q_cnts[] = {
3895         INIT_Q_COUNTER(rx_write_requests),
3896         INIT_Q_COUNTER(rx_read_requests),
3897         INIT_Q_COUNTER(rx_atomic_requests),
3898         INIT_Q_COUNTER(out_of_buffer),
3899 };
3900
3901 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3902         INIT_Q_COUNTER(out_of_sequence),
3903 };
3904
3905 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3906         INIT_Q_COUNTER(duplicate_request),
3907         INIT_Q_COUNTER(rnr_nak_retry_err),
3908         INIT_Q_COUNTER(packet_seq_err),
3909         INIT_Q_COUNTER(implied_nak_seq_err),
3910         INIT_Q_COUNTER(local_ack_timeout_err),
3911 };
3912
3913 #define INIT_CONG_COUNTER(_name)                \
3914         { .name = #_name, .offset =     \
3915                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3916
3917 static const struct mlx5_ib_counter cong_cnts[] = {
3918         INIT_CONG_COUNTER(rp_cnp_ignored),
3919         INIT_CONG_COUNTER(rp_cnp_handled),
3920         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3921         INIT_CONG_COUNTER(np_cnp_sent),
3922 };
3923
3924 static const struct mlx5_ib_counter extended_err_cnts[] = {
3925         INIT_Q_COUNTER(resp_local_length_error),
3926         INIT_Q_COUNTER(resp_cqe_error),
3927         INIT_Q_COUNTER(req_cqe_error),
3928         INIT_Q_COUNTER(req_remote_invalid_request),
3929         INIT_Q_COUNTER(req_remote_access_errors),
3930         INIT_Q_COUNTER(resp_remote_access_errors),
3931         INIT_Q_COUNTER(resp_cqe_flush_error),
3932         INIT_Q_COUNTER(req_cqe_flush_error),
3933 };
3934
3935 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3936 {
3937         int i;
3938
3939         for (i = 0; i < dev->num_ports; i++) {
3940                 if (dev->port[i].cnts.set_id)
3941                         mlx5_core_dealloc_q_counter(dev->mdev,
3942                                                     dev->port[i].cnts.set_id);
3943                 kfree(dev->port[i].cnts.names);
3944                 kfree(dev->port[i].cnts.offsets);
3945         }
3946 }
3947
3948 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3949                                     struct mlx5_ib_counters *cnts)
3950 {
3951         u32 num_counters;
3952
3953         num_counters = ARRAY_SIZE(basic_q_cnts);
3954
3955         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3956                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3957
3958         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3959                 num_counters += ARRAY_SIZE(retrans_q_cnts);
3960
3961         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3962                 num_counters += ARRAY_SIZE(extended_err_cnts);
3963
3964         cnts->num_q_counters = num_counters;
3965
3966         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3967                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3968                 num_counters += ARRAY_SIZE(cong_cnts);
3969         }
3970
3971         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3972         if (!cnts->names)
3973                 return -ENOMEM;
3974
3975         cnts->offsets = kcalloc(num_counters,
3976                                 sizeof(cnts->offsets), GFP_KERNEL);
3977         if (!cnts->offsets)
3978                 goto err_names;
3979
3980         return 0;
3981
3982 err_names:
3983         kfree(cnts->names);
3984         cnts->names = NULL;
3985         return -ENOMEM;
3986 }
3987
3988 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3989                                   const char **names,
3990                                   size_t *offsets)
3991 {
3992         int i;
3993         int j = 0;
3994
3995         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3996                 names[j] = basic_q_cnts[i].name;
3997                 offsets[j] = basic_q_cnts[i].offset;
3998         }
3999
4000         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4001                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4002                         names[j] = out_of_seq_q_cnts[i].name;
4003                         offsets[j] = out_of_seq_q_cnts[i].offset;
4004                 }
4005         }
4006
4007         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4008                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4009                         names[j] = retrans_q_cnts[i].name;
4010                         offsets[j] = retrans_q_cnts[i].offset;
4011                 }
4012         }
4013
4014         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4015                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4016                         names[j] = extended_err_cnts[i].name;
4017                         offsets[j] = extended_err_cnts[i].offset;
4018                 }
4019         }
4020
4021         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4022                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4023                         names[j] = cong_cnts[i].name;
4024                         offsets[j] = cong_cnts[i].offset;
4025                 }
4026         }
4027 }
4028
4029 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
4030 {
4031         int err = 0;
4032         int i;
4033
4034         for (i = 0; i < dev->num_ports; i++) {
4035                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4036                 if (err)
4037                         goto err_alloc;
4038
4039                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4040                                       dev->port[i].cnts.offsets);
4041
4042                 err = mlx5_core_alloc_q_counter(dev->mdev,
4043                                                 &dev->port[i].cnts.set_id);
4044                 if (err) {
4045                         mlx5_ib_warn(dev,
4046                                      "couldn't allocate queue counter for port %d, err %d\n",
4047                                      i + 1, err);
4048                         goto err_alloc;
4049                 }
4050                 dev->port[i].cnts.set_id_valid = true;
4051         }
4052
4053         return 0;
4054
4055 err_alloc:
4056         mlx5_ib_dealloc_counters(dev);
4057         return err;
4058 }
4059
4060 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4061                                                     u8 port_num)
4062 {
4063         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4064         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4065
4066         /* We support only per port stats */
4067         if (port_num == 0)
4068                 return NULL;
4069
4070         return rdma_alloc_hw_stats_struct(port->cnts.names,
4071                                           port->cnts.num_q_counters +
4072                                           port->cnts.num_cong_counters,
4073                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
4074 }
4075
4076 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
4077                                     struct mlx5_ib_port *port,
4078                                     struct rdma_hw_stats *stats)
4079 {
4080         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4081         void *out;
4082         __be32 val;
4083         int ret, i;
4084
4085         out = kvzalloc(outlen, GFP_KERNEL);
4086         if (!out)
4087                 return -ENOMEM;
4088
4089         ret = mlx5_core_query_q_counter(mdev,
4090                                         port->cnts.set_id, 0,
4091                                         out, outlen);
4092         if (ret)
4093                 goto free;
4094
4095         for (i = 0; i < port->cnts.num_q_counters; i++) {
4096                 val = *(__be32 *)(out + port->cnts.offsets[i]);
4097                 stats->value[i] = (u64)be32_to_cpu(val);
4098         }
4099
4100 free:
4101         kvfree(out);
4102         return ret;
4103 }
4104
4105 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4106                                 struct rdma_hw_stats *stats,
4107                                 u8 port_num, int index)
4108 {
4109         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4110         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4111         struct mlx5_core_dev *mdev;
4112         int ret, num_counters;
4113         u8 mdev_port_num;
4114
4115         if (!stats)
4116                 return -EINVAL;
4117
4118         num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4119
4120         /* q_counters are per IB device, query the master mdev */
4121         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
4122         if (ret)
4123                 return ret;
4124
4125         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4126                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4127                                                     &mdev_port_num);
4128                 if (!mdev) {
4129                         /* If port is not affiliated yet, its in down state
4130                          * which doesn't have any counters yet, so it would be
4131                          * zero. So no need to read from the HCA.
4132                          */
4133                         goto done;
4134                 }
4135                 ret = mlx5_lag_query_cong_counters(dev->mdev,
4136                                                    stats->value +
4137                                                    port->cnts.num_q_counters,
4138                                                    port->cnts.num_cong_counters,
4139                                                    port->cnts.offsets +
4140                                                    port->cnts.num_q_counters);
4141
4142                 mlx5_ib_put_native_port_mdev(dev, port_num);
4143                 if (ret)
4144                         return ret;
4145         }
4146
4147 done:
4148         return num_counters;
4149 }
4150
4151 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4152 {
4153         return mlx5_rdma_netdev_free(netdev);
4154 }
4155
4156 static struct net_device*
4157 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4158                           u8 port_num,
4159                           enum rdma_netdev_t type,
4160                           const char *name,
4161                           unsigned char name_assign_type,
4162                           void (*setup)(struct net_device *))
4163 {
4164         struct net_device *netdev;
4165         struct rdma_netdev *rn;
4166
4167         if (type != RDMA_NETDEV_IPOIB)
4168                 return ERR_PTR(-EOPNOTSUPP);
4169
4170         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4171                                         name, setup);
4172         if (likely(!IS_ERR_OR_NULL(netdev))) {
4173                 rn = netdev_priv(netdev);
4174                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4175         }
4176         return netdev;
4177 }
4178
4179 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4180 {
4181         if (!dev->delay_drop.dbg)
4182                 return;
4183         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4184         kfree(dev->delay_drop.dbg);
4185         dev->delay_drop.dbg = NULL;
4186 }
4187
4188 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4189 {
4190         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4191                 return;
4192
4193         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4194         delay_drop_debugfs_cleanup(dev);
4195 }
4196
4197 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4198                                        size_t count, loff_t *pos)
4199 {
4200         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4201         char lbuf[20];
4202         int len;
4203
4204         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4205         return simple_read_from_buffer(buf, count, pos, lbuf, len);
4206 }
4207
4208 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4209                                         size_t count, loff_t *pos)
4210 {
4211         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4212         u32 timeout;
4213         u32 var;
4214
4215         if (kstrtouint_from_user(buf, count, 0, &var))
4216                 return -EFAULT;
4217
4218         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4219                         1000);
4220         if (timeout != var)
4221                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4222                             timeout);
4223
4224         delay_drop->timeout = timeout;
4225
4226         return count;
4227 }
4228
4229 static const struct file_operations fops_delay_drop_timeout = {
4230         .owner  = THIS_MODULE,
4231         .open   = simple_open,
4232         .write  = delay_drop_timeout_write,
4233         .read   = delay_drop_timeout_read,
4234 };
4235
4236 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4237 {
4238         struct mlx5_ib_dbg_delay_drop *dbg;
4239
4240         if (!mlx5_debugfs_root)
4241                 return 0;
4242
4243         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4244         if (!dbg)
4245                 return -ENOMEM;
4246
4247         dev->delay_drop.dbg = dbg;
4248
4249         dbg->dir_debugfs =
4250                 debugfs_create_dir("delay_drop",
4251                                    dev->mdev->priv.dbg_root);
4252         if (!dbg->dir_debugfs)
4253                 goto out_debugfs;
4254
4255         dbg->events_cnt_debugfs =
4256                 debugfs_create_atomic_t("num_timeout_events", 0400,
4257                                         dbg->dir_debugfs,
4258                                         &dev->delay_drop.events_cnt);
4259         if (!dbg->events_cnt_debugfs)
4260                 goto out_debugfs;
4261
4262         dbg->rqs_cnt_debugfs =
4263                 debugfs_create_atomic_t("num_rqs", 0400,
4264                                         dbg->dir_debugfs,
4265                                         &dev->delay_drop.rqs_cnt);
4266         if (!dbg->rqs_cnt_debugfs)
4267                 goto out_debugfs;
4268
4269         dbg->timeout_debugfs =
4270                 debugfs_create_file("timeout", 0600,
4271                                     dbg->dir_debugfs,
4272                                     &dev->delay_drop,
4273                                     &fops_delay_drop_timeout);
4274         if (!dbg->timeout_debugfs)
4275                 goto out_debugfs;
4276
4277         return 0;
4278
4279 out_debugfs:
4280         delay_drop_debugfs_cleanup(dev);
4281         return -ENOMEM;
4282 }
4283
4284 static void init_delay_drop(struct mlx5_ib_dev *dev)
4285 {
4286         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4287                 return;
4288
4289         mutex_init(&dev->delay_drop.lock);
4290         dev->delay_drop.dev = dev;
4291         dev->delay_drop.activate = false;
4292         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4293         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4294         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4295         atomic_set(&dev->delay_drop.events_cnt, 0);
4296
4297         if (delay_drop_debugfs_init(dev))
4298                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
4299 }
4300
4301 static const struct cpumask *
4302 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
4303 {
4304         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4305
4306         return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4307 }
4308
4309 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4310 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4311                                       struct mlx5_ib_multiport_info *mpi)
4312 {
4313         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4314         struct mlx5_ib_port *port = &ibdev->port[port_num];
4315         int comps;
4316         int err;
4317         int i;
4318
4319         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4320
4321         spin_lock(&port->mp.mpi_lock);
4322         if (!mpi->ibdev) {
4323                 spin_unlock(&port->mp.mpi_lock);
4324                 return;
4325         }
4326         mpi->ibdev = NULL;
4327
4328         spin_unlock(&port->mp.mpi_lock);
4329         mlx5_remove_netdev_notifier(ibdev, port_num);
4330         spin_lock(&port->mp.mpi_lock);
4331
4332         comps = mpi->mdev_refcnt;
4333         if (comps) {
4334                 mpi->unaffiliate = true;
4335                 init_completion(&mpi->unref_comp);
4336                 spin_unlock(&port->mp.mpi_lock);
4337
4338                 for (i = 0; i < comps; i++)
4339                         wait_for_completion(&mpi->unref_comp);
4340
4341                 spin_lock(&port->mp.mpi_lock);
4342                 mpi->unaffiliate = false;
4343         }
4344
4345         port->mp.mpi = NULL;
4346
4347         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4348
4349         spin_unlock(&port->mp.mpi_lock);
4350
4351         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4352
4353         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4354         /* Log an error, still needed to cleanup the pointers and add
4355          * it back to the list.
4356          */
4357         if (err)
4358                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4359                             port_num + 1);
4360
4361         ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4362 }
4363
4364 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4365 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4366                                     struct mlx5_ib_multiport_info *mpi)
4367 {
4368         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4369         int err;
4370
4371         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4372         if (ibdev->port[port_num].mp.mpi) {
4373                 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4374                              port_num + 1);
4375                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4376                 return false;
4377         }
4378
4379         ibdev->port[port_num].mp.mpi = mpi;
4380         mpi->ibdev = ibdev;
4381         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4382
4383         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4384         if (err)
4385                 goto unbind;
4386
4387         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4388         if (err)
4389                 goto unbind;
4390
4391         err = mlx5_add_netdev_notifier(ibdev, port_num);
4392         if (err) {
4393                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4394                             port_num + 1);
4395                 goto unbind;
4396         }
4397
4398         err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4399         if (err)
4400                 goto unbind;
4401
4402         return true;
4403
4404 unbind:
4405         mlx5_ib_unbind_slave_port(ibdev, mpi);
4406         return false;
4407 }
4408
4409 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4410 {
4411         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4412         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4413                                                           port_num + 1);
4414         struct mlx5_ib_multiport_info *mpi;
4415         int err;
4416         int i;
4417
4418         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4419                 return 0;
4420
4421         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4422                                                      &dev->sys_image_guid);
4423         if (err)
4424                 return err;
4425
4426         err = mlx5_nic_vport_enable_roce(dev->mdev);
4427         if (err)
4428                 return err;
4429
4430         mutex_lock(&mlx5_ib_multiport_mutex);
4431         for (i = 0; i < dev->num_ports; i++) {
4432                 bool bound = false;
4433
4434                 /* build a stub multiport info struct for the native port. */
4435                 if (i == port_num) {
4436                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4437                         if (!mpi) {
4438                                 mutex_unlock(&mlx5_ib_multiport_mutex);
4439                                 mlx5_nic_vport_disable_roce(dev->mdev);
4440                                 return -ENOMEM;
4441                         }
4442
4443                         mpi->is_master = true;
4444                         mpi->mdev = dev->mdev;
4445                         mpi->sys_image_guid = dev->sys_image_guid;
4446                         dev->port[i].mp.mpi = mpi;
4447                         mpi->ibdev = dev;
4448                         mpi = NULL;
4449                         continue;
4450                 }
4451
4452                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4453                                     list) {
4454                         if (dev->sys_image_guid == mpi->sys_image_guid &&
4455                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4456                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
4457                         }
4458
4459                         if (bound) {
4460                                 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4461                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4462                                 list_del(&mpi->list);
4463                                 break;
4464                         }
4465                 }
4466                 if (!bound) {
4467                         get_port_caps(dev, i + 1);
4468                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
4469                                     i + 1);
4470                 }
4471         }
4472
4473         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4474         mutex_unlock(&mlx5_ib_multiport_mutex);
4475         return err;
4476 }
4477
4478 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4479 {
4480         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4481         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4482                                                           port_num + 1);
4483         int i;
4484
4485         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4486                 return;
4487
4488         mutex_lock(&mlx5_ib_multiport_mutex);
4489         for (i = 0; i < dev->num_ports; i++) {
4490                 if (dev->port[i].mp.mpi) {
4491                         /* Destroy the native port stub */
4492                         if (i == port_num) {
4493                                 kfree(dev->port[i].mp.mpi);
4494                                 dev->port[i].mp.mpi = NULL;
4495                         } else {
4496                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4497                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4498                         }
4499                 }
4500         }
4501
4502         mlx5_ib_dbg(dev, "removing from devlist\n");
4503         list_del(&dev->ib_dev_list);
4504         mutex_unlock(&mlx5_ib_multiport_mutex);
4505
4506         mlx5_nic_vport_disable_roce(dev->mdev);
4507 }
4508
4509 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
4510 {
4511         mlx5_ib_cleanup_multiport_master(dev);
4512 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4513         cleanup_srcu_struct(&dev->mr_srcu);
4514 #endif
4515         kfree(dev->port);
4516 }
4517
4518 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4519 {
4520         struct mlx5_core_dev *mdev = dev->mdev;
4521         const char *name;
4522         int err;
4523         int i;
4524
4525         dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
4526                             GFP_KERNEL);
4527         if (!dev->port)
4528                 return -ENOMEM;
4529
4530         for (i = 0; i < dev->num_ports; i++) {
4531                 spin_lock_init(&dev->port[i].mp.mpi_lock);
4532                 rwlock_init(&dev->roce[i].netdev_lock);
4533         }
4534
4535         err = mlx5_ib_init_multiport_master(dev);
4536         if (err)
4537                 goto err_free_port;
4538
4539         if (!mlx5_core_mp_enabled(mdev)) {
4540                 int i;
4541
4542                 for (i = 1; i <= dev->num_ports; i++) {
4543                         err = get_port_caps(dev, i);
4544                         if (err)
4545                                 break;
4546                 }
4547         } else {
4548                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
4549         }
4550         if (err)
4551                 goto err_mp;
4552
4553         if (mlx5_use_mad_ifc(dev))
4554                 get_ext_port_caps(dev);
4555
4556         if (!mlx5_lag_is_active(mdev))
4557                 name = "mlx5_%d";
4558         else
4559                 name = "mlx5_bond_%d";
4560
4561         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
4562         dev->ib_dev.owner               = THIS_MODULE;
4563         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
4564         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
4565         dev->ib_dev.phys_port_cnt       = dev->num_ports;
4566         dev->ib_dev.num_comp_vectors    =
4567                 dev->mdev->priv.eq_table.num_comp_vectors;
4568         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
4569
4570         mutex_init(&dev->flow_db.lock);
4571         mutex_init(&dev->cap_mask_mutex);
4572         INIT_LIST_HEAD(&dev->qp_list);
4573         spin_lock_init(&dev->reset_flow_resource_lock);
4574
4575 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4576         err = init_srcu_struct(&dev->mr_srcu);
4577         if (err)
4578                 goto err_free_port;
4579 #endif
4580
4581         return 0;
4582 err_mp:
4583         mlx5_ib_cleanup_multiport_master(dev);
4584
4585 err_free_port:
4586         kfree(dev->port);
4587
4588         return -ENOMEM;
4589 }
4590
4591 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4592 {
4593         struct mlx5_core_dev *mdev = dev->mdev;
4594         int err;
4595
4596         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
4597         dev->ib_dev.uverbs_cmd_mask     =
4598                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
4599                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
4600                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
4601                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
4602                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
4603                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
4604                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
4605                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
4606                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
4607                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
4608                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4609                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
4610                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
4611                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
4612                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
4613                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
4614                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
4615                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
4616                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
4617                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
4618                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
4619                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
4620                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
4621                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
4622                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
4623                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
4624         dev->ib_dev.uverbs_ex_cmd_mask =
4625                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
4626                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
4627                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
4628                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
4629                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
4630
4631         dev->ib_dev.query_device        = mlx5_ib_query_device;
4632         dev->ib_dev.query_port          = mlx5_ib_query_port;
4633         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
4634         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
4635         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
4636         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
4637         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
4638         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
4639         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
4640         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
4641         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
4642         dev->ib_dev.mmap                = mlx5_ib_mmap;
4643         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
4644         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
4645         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
4646         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
4647         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
4648         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
4649         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
4650         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
4651         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
4652         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
4653         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
4654         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
4655         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
4656         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
4657         dev->ib_dev.post_send           = mlx5_ib_post_send;
4658         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
4659         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
4660         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
4661         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
4662         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
4663         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
4664         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
4665         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
4666         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
4667         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
4668         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
4669         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
4670         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
4671         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
4672         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
4673         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
4674         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
4675         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
4676         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
4677         dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
4678         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
4679                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
4680
4681         if (mlx5_core_is_pf(mdev)) {
4682                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
4683                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
4684                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
4685                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
4686         }
4687
4688         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4689
4690         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4691
4692         if (MLX5_CAP_GEN(mdev, imaicl)) {
4693                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
4694                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
4695                 dev->ib_dev.uverbs_cmd_mask |=
4696                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
4697                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4698         }
4699
4700         if (MLX5_CAP_GEN(mdev, xrc)) {
4701                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4702                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4703                 dev->ib_dev.uverbs_cmd_mask |=
4704                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4705                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4706         }
4707
4708         dev->ib_dev.create_flow = mlx5_ib_create_flow;
4709         dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4710         dev->ib_dev.uverbs_ex_cmd_mask |=
4711                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4712                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4713
4714         err = init_node_data(dev);
4715         if (err)
4716                 return err;
4717
4718         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4719             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4720              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4721                 mutex_init(&dev->lb_mutex);
4722
4723         return 0;
4724 }
4725
4726 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
4727 {
4728         struct mlx5_core_dev *mdev = dev->mdev;
4729         enum rdma_link_layer ll;
4730         int port_type_cap;
4731         u8 port_num;
4732         int err;
4733         int i;
4734
4735         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4736         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4737         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4738
4739         if (ll == IB_LINK_LAYER_ETHERNET) {
4740                 for (i = 0; i < dev->num_ports; i++) {
4741                         dev->roce[i].dev = dev;
4742                         dev->roce[i].native_port_num = i + 1;
4743                         dev->roce[i].last_port_state = IB_PORT_DOWN;
4744                 }
4745
4746                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
4747                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
4748                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
4749                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
4750                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4751                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4752                 dev->ib_dev.uverbs_ex_cmd_mask |=
4753                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4754                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4755                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4756                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4757                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
4758                 err = mlx5_enable_eth(dev, port_num);
4759                 if (err)
4760                         return err;
4761         }
4762
4763         return 0;
4764 }
4765
4766 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
4767 {
4768         struct mlx5_core_dev *mdev = dev->mdev;
4769         enum rdma_link_layer ll;
4770         int port_type_cap;
4771         u8 port_num;
4772
4773         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4774         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4775         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4776
4777         if (ll == IB_LINK_LAYER_ETHERNET) {
4778                 mlx5_disable_eth(dev);
4779                 mlx5_remove_netdev_notifier(dev, port_num);
4780         }
4781 }
4782
4783 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
4784 {
4785         return create_dev_resources(&dev->devr);
4786 }
4787
4788 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
4789 {
4790         destroy_dev_resources(&dev->devr);
4791 }
4792
4793 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
4794 {
4795         mlx5_ib_internal_fill_odp_caps(dev);
4796
4797         return mlx5_ib_odp_init_one(dev);
4798 }
4799
4800 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
4801 {
4802         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4803                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
4804                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
4805
4806                 return mlx5_ib_alloc_counters(dev);
4807         }
4808
4809         return 0;
4810 }
4811
4812 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
4813 {
4814         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4815                 mlx5_ib_dealloc_counters(dev);
4816 }
4817
4818 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4819 {
4820         return mlx5_ib_init_cong_debugfs(dev,
4821                                          mlx5_core_native_port_num(dev->mdev) - 1);
4822 }
4823
4824 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4825 {
4826         mlx5_ib_cleanup_cong_debugfs(dev,
4827                                      mlx5_core_native_port_num(dev->mdev) - 1);
4828 }
4829
4830 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4831 {
4832         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4833         if (!dev->mdev->priv.uar)
4834                 return -ENOMEM;
4835         return 0;
4836 }
4837
4838 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4839 {
4840         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4841 }
4842
4843 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4844 {
4845         int err;
4846
4847         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4848         if (err)
4849                 return err;
4850
4851         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4852         if (err)
4853                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4854
4855         return err;
4856 }
4857
4858 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4859 {
4860         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4861         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4862 }
4863
4864 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4865 {
4866         return ib_register_device(&dev->ib_dev, NULL);
4867 }
4868
4869 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4870 {
4871         destroy_umrc_res(dev);
4872 }
4873
4874 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4875 {
4876         ib_unregister_device(&dev->ib_dev);
4877 }
4878
4879 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4880 {
4881         return create_umr_res(dev);
4882 }
4883
4884 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4885 {
4886         init_delay_drop(dev);
4887
4888         return 0;
4889 }
4890
4891 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4892 {
4893         cancel_delay_drop(dev);
4894 }
4895
4896 static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
4897 {
4898         int err;
4899         int i;
4900
4901         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
4902                 err = device_create_file(&dev->ib_dev.dev,
4903                                          mlx5_class_attributes[i]);
4904                 if (err)
4905                         return err;
4906         }
4907
4908         return 0;
4909 }
4910
4911 static void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4912                              const struct mlx5_ib_profile *profile,
4913                              int stage)
4914 {
4915         /* Number of stages to cleanup */
4916         while (stage) {
4917                 stage--;
4918                 if (profile->stage[stage].cleanup)
4919                         profile->stage[stage].cleanup(dev);
4920         }
4921
4922         ib_dealloc_device((struct ib_device *)dev);
4923 }
4924
4925 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
4926
4927 static void *__mlx5_ib_add(struct mlx5_core_dev *mdev,
4928                            const struct mlx5_ib_profile *profile)
4929 {
4930         struct mlx5_ib_dev *dev;
4931         int err;
4932         int i;
4933
4934         printk_once(KERN_INFO "%s", mlx5_version);
4935
4936         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
4937         if (!dev)
4938                 return NULL;
4939
4940         dev->mdev = mdev;
4941         dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4942                              MLX5_CAP_GEN(mdev, num_vhca_ports));
4943
4944         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4945                 if (profile->stage[i].init) {
4946                         err = profile->stage[i].init(dev);
4947                         if (err)
4948                                 goto err_out;
4949                 }
4950         }
4951
4952         dev->profile = profile;
4953         dev->ib_active = true;
4954
4955         return dev;
4956
4957 err_out:
4958         __mlx5_ib_remove(dev, profile, i);
4959
4960         return NULL;
4961 }
4962
4963 static const struct mlx5_ib_profile pf_profile = {
4964         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4965                      mlx5_ib_stage_init_init,
4966                      mlx5_ib_stage_init_cleanup),
4967         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4968                      mlx5_ib_stage_caps_init,
4969                      NULL),
4970         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4971                      mlx5_ib_stage_roce_init,
4972                      mlx5_ib_stage_roce_cleanup),
4973         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4974                      mlx5_ib_stage_dev_res_init,
4975                      mlx5_ib_stage_dev_res_cleanup),
4976         STAGE_CREATE(MLX5_IB_STAGE_ODP,
4977                      mlx5_ib_stage_odp_init,
4978                      NULL),
4979         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4980                      mlx5_ib_stage_counters_init,
4981                      mlx5_ib_stage_counters_cleanup),
4982         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4983                      mlx5_ib_stage_cong_debugfs_init,
4984                      mlx5_ib_stage_cong_debugfs_cleanup),
4985         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4986                      mlx5_ib_stage_uar_init,
4987                      mlx5_ib_stage_uar_cleanup),
4988         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4989                      mlx5_ib_stage_bfrag_init,
4990                      mlx5_ib_stage_bfrag_cleanup),
4991         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4992                      NULL,
4993                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4994         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4995                      mlx5_ib_stage_ib_reg_init,
4996                      mlx5_ib_stage_ib_reg_cleanup),
4997         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4998                      mlx5_ib_stage_post_ib_reg_umr_init,
4999                      NULL),
5000         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
5001                      mlx5_ib_stage_delay_drop_init,
5002                      mlx5_ib_stage_delay_drop_cleanup),
5003         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5004                      mlx5_ib_stage_class_attr_init,
5005                      NULL),
5006 };
5007
5008 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5009 {
5010         struct mlx5_ib_multiport_info *mpi;
5011         struct mlx5_ib_dev *dev;
5012         bool bound = false;
5013         int err;
5014
5015         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5016         if (!mpi)
5017                 return NULL;
5018
5019         mpi->mdev = mdev;
5020
5021         err = mlx5_query_nic_vport_system_image_guid(mdev,
5022                                                      &mpi->sys_image_guid);
5023         if (err) {
5024                 kfree(mpi);
5025                 return NULL;
5026         }
5027
5028         mutex_lock(&mlx5_ib_multiport_mutex);
5029         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5030                 if (dev->sys_image_guid == mpi->sys_image_guid)
5031                         bound = mlx5_ib_bind_slave_port(dev, mpi);
5032
5033                 if (bound) {
5034                         rdma_roce_rescan_device(&dev->ib_dev);
5035                         break;
5036                 }
5037         }
5038
5039         if (!bound) {
5040                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5041                 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5042         } else {
5043                 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5044         }
5045         mutex_unlock(&mlx5_ib_multiport_mutex);
5046
5047         return mpi;
5048 }
5049
5050 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5051 {
5052         enum rdma_link_layer ll;
5053         int port_type_cap;
5054
5055         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5056         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5057
5058         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5059                 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5060
5061                 return mlx5_ib_add_slave_port(mdev, port_num);
5062         }
5063
5064         return __mlx5_ib_add(mdev, &pf_profile);
5065 }
5066
5067 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
5068 {
5069         struct mlx5_ib_multiport_info *mpi;
5070         struct mlx5_ib_dev *dev;
5071
5072         if (mlx5_core_is_mp_slave(mdev)) {
5073                 mpi = context;
5074                 mutex_lock(&mlx5_ib_multiport_mutex);
5075                 if (mpi->ibdev)
5076                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5077                 list_del(&mpi->list);
5078                 mutex_unlock(&mlx5_ib_multiport_mutex);
5079                 return;
5080         }
5081
5082         dev = context;
5083         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
5084 }
5085
5086 static struct mlx5_interface mlx5_ib_interface = {
5087         .add            = mlx5_ib_add,
5088         .remove         = mlx5_ib_remove,
5089         .event          = mlx5_ib_event,
5090 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5091         .pfault         = mlx5_ib_pfault,
5092 #endif
5093         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
5094 };
5095
5096 static int __init mlx5_ib_init(void)
5097 {
5098         int err;
5099
5100         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5101         if (!mlx5_ib_event_wq)
5102                 return -ENOMEM;
5103
5104         mlx5_ib_odp_init();
5105
5106         err = mlx5_register_interface(&mlx5_ib_interface);
5107
5108         return err;
5109 }
5110
5111 static void __exit mlx5_ib_cleanup(void)
5112 {
5113         mlx5_unregister_interface(&mlx5_ib_interface);
5114         destroy_workqueue(mlx5_ib_event_wq);
5115 }
5116
5117 module_init(mlx5_ib_init);
5118 module_exit(mlx5_ib_cleanup);