2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
56 #include <linux/mlx5/vport.h>
59 #define DRIVER_NAME "mlx5_ib"
60 #define DRIVER_VERSION "2.2-1"
61 #define DRIVER_RELDATE "Feb 2014"
63 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
64 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
65 MODULE_LICENSE("Dual BSD/GPL");
66 MODULE_VERSION(DRIVER_VERSION);
68 static char mlx5_version[] =
69 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
70 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
73 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
76 static enum rdma_link_layer
77 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
79 switch (port_type_cap) {
80 case MLX5_CAP_PORT_TYPE_IB:
81 return IB_LINK_LAYER_INFINIBAND;
82 case MLX5_CAP_PORT_TYPE_ETH:
83 return IB_LINK_LAYER_ETHERNET;
85 return IB_LINK_LAYER_UNSPECIFIED;
89 static enum rdma_link_layer
90 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
92 struct mlx5_ib_dev *dev = to_mdev(device);
93 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
95 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
98 static int mlx5_netdev_event(struct notifier_block *this,
99 unsigned long event, void *ptr)
101 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
102 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
106 case NETDEV_REGISTER:
107 case NETDEV_UNREGISTER:
108 write_lock(&ibdev->roce.netdev_lock);
109 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
110 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
112 write_unlock(&ibdev->roce.netdev_lock);
117 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
118 struct net_device *upper = NULL;
121 upper = netdev_master_upper_dev_get(lag_ndev);
125 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
126 && ibdev->ib_active) {
127 struct ib_event ibev = { };
129 ibev.device = &ibdev->ib_dev;
130 ibev.event = (event == NETDEV_UP) ?
131 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
132 ibev.element.port_num = 1;
133 ib_dispatch_event(&ibev);
145 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
148 struct mlx5_ib_dev *ibdev = to_mdev(device);
149 struct net_device *ndev;
151 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
155 /* Ensure ndev does not disappear before we invoke dev_hold()
157 read_lock(&ibdev->roce.netdev_lock);
158 ndev = ibdev->roce.netdev;
161 read_unlock(&ibdev->roce.netdev_lock);
166 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
167 struct ib_port_attr *props)
169 struct mlx5_ib_dev *dev = to_mdev(device);
170 struct net_device *ndev, *upper;
171 enum ib_mtu ndev_ib_mtu;
174 /* props being zeroed by the caller, avoid zeroing it here */
176 props->port_cap_flags |= IB_PORT_CM_SUP;
177 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
179 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
180 roce_address_table_size);
181 props->max_mtu = IB_MTU_4096;
182 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
183 props->pkey_tbl_len = 1;
184 props->state = IB_PORT_DOWN;
185 props->phys_state = 3;
187 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
188 props->qkey_viol_cntr = qkey_viol_cntr;
190 ndev = mlx5_ib_get_netdev(device, port_num);
194 if (mlx5_lag_is_active(dev->mdev)) {
196 upper = netdev_master_upper_dev_get_rcu(ndev);
205 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
206 props->state = IB_PORT_ACTIVE;
207 props->phys_state = 5;
210 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
214 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
216 props->active_width = IB_WIDTH_4X; /* TODO */
217 props->active_speed = IB_SPEED_QDR; /* TODO */
222 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
223 const struct ib_gid_attr *attr,
226 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
227 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
229 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
235 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
237 if (is_vlan_dev(attr->ndev)) {
238 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
239 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
242 switch (attr->gid_type) {
244 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
246 case IB_GID_TYPE_ROCE_UDP_ENCAP:
247 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
254 if (attr->gid_type != IB_GID_TYPE_IB) {
255 if (ipv6_addr_v4mapped((void *)gid))
256 MLX5_SET_RA(mlx5_addr, roce_l3_type,
257 MLX5_ROCE_L3_TYPE_IPV4);
259 MLX5_SET_RA(mlx5_addr, roce_l3_type,
260 MLX5_ROCE_L3_TYPE_IPV6);
263 if ((attr->gid_type == IB_GID_TYPE_IB) ||
264 !ipv6_addr_v4mapped((void *)gid))
265 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
267 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
270 static int set_roce_addr(struct ib_device *device, u8 port_num,
272 const union ib_gid *gid,
273 const struct ib_gid_attr *attr)
275 struct mlx5_ib_dev *dev = to_mdev(device);
276 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
277 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
278 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
279 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
281 if (ll != IB_LINK_LAYER_ETHERNET)
284 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
286 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
287 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
288 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
291 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
292 unsigned int index, const union ib_gid *gid,
293 const struct ib_gid_attr *attr,
294 __always_unused void **context)
296 return set_roce_addr(device, port_num, index, gid, attr);
299 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
300 unsigned int index, __always_unused void **context)
302 return set_roce_addr(device, port_num, index, NULL, NULL);
305 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
308 struct ib_gid_attr attr;
311 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
319 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
322 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
325 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
326 int index, enum ib_gid_type *gid_type)
328 struct ib_gid_attr attr;
332 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
341 *gid_type = attr.gid_type;
346 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
348 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
349 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
354 MLX5_VPORT_ACCESS_METHOD_MAD,
355 MLX5_VPORT_ACCESS_METHOD_HCA,
356 MLX5_VPORT_ACCESS_METHOD_NIC,
359 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
361 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
362 return MLX5_VPORT_ACCESS_METHOD_MAD;
364 if (mlx5_ib_port_link_layer(ibdev, 1) ==
365 IB_LINK_LAYER_ETHERNET)
366 return MLX5_VPORT_ACCESS_METHOD_NIC;
368 return MLX5_VPORT_ACCESS_METHOD_HCA;
371 static void get_atomic_caps(struct mlx5_ib_dev *dev,
372 struct ib_device_attr *props)
375 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
376 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
377 u8 atomic_req_8B_endianness_mode =
378 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
380 /* Check if HW supports 8 bytes standard atomic operations and capable
381 * of host endianness respond
383 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
384 if (((atomic_operations & tmp) == tmp) &&
385 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
386 (atomic_req_8B_endianness_mode)) {
387 props->atomic_cap = IB_ATOMIC_HCA;
389 props->atomic_cap = IB_ATOMIC_NONE;
393 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
394 __be64 *sys_image_guid)
396 struct mlx5_ib_dev *dev = to_mdev(ibdev);
397 struct mlx5_core_dev *mdev = dev->mdev;
401 switch (mlx5_get_vport_access_method(ibdev)) {
402 case MLX5_VPORT_ACCESS_METHOD_MAD:
403 return mlx5_query_mad_ifc_system_image_guid(ibdev,
406 case MLX5_VPORT_ACCESS_METHOD_HCA:
407 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
410 case MLX5_VPORT_ACCESS_METHOD_NIC:
411 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
419 *sys_image_guid = cpu_to_be64(tmp);
425 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
428 struct mlx5_ib_dev *dev = to_mdev(ibdev);
429 struct mlx5_core_dev *mdev = dev->mdev;
431 switch (mlx5_get_vport_access_method(ibdev)) {
432 case MLX5_VPORT_ACCESS_METHOD_MAD:
433 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
435 case MLX5_VPORT_ACCESS_METHOD_HCA:
436 case MLX5_VPORT_ACCESS_METHOD_NIC:
437 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
446 static int mlx5_query_vendor_id(struct ib_device *ibdev,
449 struct mlx5_ib_dev *dev = to_mdev(ibdev);
451 switch (mlx5_get_vport_access_method(ibdev)) {
452 case MLX5_VPORT_ACCESS_METHOD_MAD:
453 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
455 case MLX5_VPORT_ACCESS_METHOD_HCA:
456 case MLX5_VPORT_ACCESS_METHOD_NIC:
457 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
464 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
470 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
471 case MLX5_VPORT_ACCESS_METHOD_MAD:
472 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
474 case MLX5_VPORT_ACCESS_METHOD_HCA:
475 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
478 case MLX5_VPORT_ACCESS_METHOD_NIC:
479 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
487 *node_guid = cpu_to_be64(tmp);
492 struct mlx5_reg_node_desc {
493 u8 desc[IB_DEVICE_NODE_DESC_MAX];
496 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
498 struct mlx5_reg_node_desc in;
500 if (mlx5_use_mad_ifc(dev))
501 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
503 memset(&in, 0, sizeof(in));
505 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
506 sizeof(struct mlx5_reg_node_desc),
507 MLX5_REG_NODE_DESC, 0, 0);
510 static int mlx5_ib_query_device(struct ib_device *ibdev,
511 struct ib_device_attr *props,
512 struct ib_udata *uhw)
514 struct mlx5_ib_dev *dev = to_mdev(ibdev);
515 struct mlx5_core_dev *mdev = dev->mdev;
520 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
521 struct mlx5_ib_query_device_resp resp = {};
525 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
526 if (uhw->outlen && uhw->outlen < resp_len)
529 resp.response_length = resp_len;
531 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
534 memset(props, 0, sizeof(*props));
535 err = mlx5_query_system_image_guid(ibdev,
536 &props->sys_image_guid);
540 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
544 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
548 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
549 (fw_rev_min(dev->mdev) << 16) |
550 fw_rev_sub(dev->mdev);
551 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
552 IB_DEVICE_PORT_ACTIVE_EVENT |
553 IB_DEVICE_SYS_IMAGE_GUID |
554 IB_DEVICE_RC_RNR_NAK_GEN;
556 if (MLX5_CAP_GEN(mdev, pkv))
557 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
558 if (MLX5_CAP_GEN(mdev, qkv))
559 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
560 if (MLX5_CAP_GEN(mdev, apm))
561 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
562 if (MLX5_CAP_GEN(mdev, xrc))
563 props->device_cap_flags |= IB_DEVICE_XRC;
564 if (MLX5_CAP_GEN(mdev, imaicl)) {
565 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
566 IB_DEVICE_MEM_WINDOW_TYPE_2B;
567 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
568 /* We support 'Gappy' memory registration too */
569 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
571 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
572 if (MLX5_CAP_GEN(mdev, sho)) {
573 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
574 /* At this stage no support for signature handover */
575 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
576 IB_PROT_T10DIF_TYPE_2 |
577 IB_PROT_T10DIF_TYPE_3;
578 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
579 IB_GUARD_T10DIF_CSUM;
581 if (MLX5_CAP_GEN(mdev, block_lb_mc))
582 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
584 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
585 if (MLX5_CAP_ETH(mdev, csum_cap)) {
586 /* Legacy bit to support old userspace libraries */
587 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
588 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
591 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
592 props->raw_packet_caps |=
593 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
595 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
596 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
598 resp.tso_caps.max_tso = 1 << max_tso;
599 resp.tso_caps.supported_qpts |=
600 1 << IB_QPT_RAW_PACKET;
601 resp.response_length += sizeof(resp.tso_caps);
605 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
606 resp.rss_caps.rx_hash_function =
607 MLX5_RX_HASH_FUNC_TOEPLITZ;
608 resp.rss_caps.rx_hash_fields_mask =
609 MLX5_RX_HASH_SRC_IPV4 |
610 MLX5_RX_HASH_DST_IPV4 |
611 MLX5_RX_HASH_SRC_IPV6 |
612 MLX5_RX_HASH_DST_IPV6 |
613 MLX5_RX_HASH_SRC_PORT_TCP |
614 MLX5_RX_HASH_DST_PORT_TCP |
615 MLX5_RX_HASH_SRC_PORT_UDP |
616 MLX5_RX_HASH_DST_PORT_UDP;
617 resp.response_length += sizeof(resp.rss_caps);
620 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
621 resp.response_length += sizeof(resp.tso_caps);
622 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
623 resp.response_length += sizeof(resp.rss_caps);
626 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
627 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
628 props->device_cap_flags |= IB_DEVICE_UD_TSO;
631 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
632 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
633 /* Legacy bit to support old userspace libraries */
634 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
635 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
638 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
639 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
641 props->vendor_part_id = mdev->pdev->device;
642 props->hw_ver = mdev->pdev->revision;
644 props->max_mr_size = ~0ull;
645 props->page_size_cap = ~(min_page_size - 1);
646 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
647 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
648 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
649 sizeof(struct mlx5_wqe_data_seg);
650 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
651 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
652 sizeof(struct mlx5_wqe_raddr_seg)) /
653 sizeof(struct mlx5_wqe_data_seg);
654 props->max_sge = min(max_rq_sg, max_sq_sg);
655 props->max_sge_rd = MLX5_MAX_SGE_RD;
656 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
657 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
658 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
659 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
660 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
661 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
662 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
663 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
664 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
665 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
666 props->max_srq_sge = max_rq_sg - 1;
667 props->max_fast_reg_page_list_len =
668 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
669 get_atomic_caps(dev, props);
670 props->masked_atomic_cap = IB_ATOMIC_NONE;
671 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
672 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
673 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
674 props->max_mcast_grp;
675 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
676 props->max_ah = INT_MAX;
677 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
678 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
680 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
681 if (MLX5_CAP_GEN(mdev, pg))
682 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
683 props->odp_caps = dev->odp_caps;
686 if (MLX5_CAP_GEN(mdev, cd))
687 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
689 if (!mlx5_core_is_pf(mdev))
690 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
692 if (mlx5_ib_port_link_layer(ibdev, 1) ==
693 IB_LINK_LAYER_ETHERNET) {
694 props->rss_caps.max_rwq_indirection_tables =
695 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
696 props->rss_caps.max_rwq_indirection_table_size =
697 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
698 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
699 props->max_wq_type_rq =
700 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
703 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
704 resp.cqe_comp_caps.max_num =
705 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
706 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
707 resp.cqe_comp_caps.supported_format =
708 MLX5_IB_CQE_RES_FORMAT_HASH |
709 MLX5_IB_CQE_RES_FORMAT_CSUM;
710 resp.response_length += sizeof(resp.cqe_comp_caps);
713 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
714 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
715 MLX5_CAP_GEN(mdev, qos)) {
716 resp.packet_pacing_caps.qp_rate_limit_max =
717 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
718 resp.packet_pacing_caps.qp_rate_limit_min =
719 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
720 resp.packet_pacing_caps.supported_qpts |=
721 1 << IB_QPT_RAW_PACKET;
723 resp.response_length += sizeof(resp.packet_pacing_caps);
726 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
728 resp.mlx5_ib_support_multi_pkt_send_wqes =
729 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
730 resp.response_length +=
731 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
734 if (field_avail(typeof(resp), reserved, uhw->outlen))
735 resp.response_length += sizeof(resp.reserved);
738 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
748 MLX5_IB_WIDTH_1X = 1 << 0,
749 MLX5_IB_WIDTH_2X = 1 << 1,
750 MLX5_IB_WIDTH_4X = 1 << 2,
751 MLX5_IB_WIDTH_8X = 1 << 3,
752 MLX5_IB_WIDTH_12X = 1 << 4
755 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
758 struct mlx5_ib_dev *dev = to_mdev(ibdev);
761 if (active_width & MLX5_IB_WIDTH_1X) {
762 *ib_width = IB_WIDTH_1X;
763 } else if (active_width & MLX5_IB_WIDTH_2X) {
764 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
767 } else if (active_width & MLX5_IB_WIDTH_4X) {
768 *ib_width = IB_WIDTH_4X;
769 } else if (active_width & MLX5_IB_WIDTH_8X) {
770 *ib_width = IB_WIDTH_8X;
771 } else if (active_width & MLX5_IB_WIDTH_12X) {
772 *ib_width = IB_WIDTH_12X;
774 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
782 static int mlx5_mtu_to_ib_mtu(int mtu)
791 pr_warn("invalid mtu\n");
801 __IB_MAX_VL_0_14 = 5,
804 enum mlx5_vl_hw_cap {
816 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
821 *max_vl_num = __IB_MAX_VL_0;
824 *max_vl_num = __IB_MAX_VL_0_1;
827 *max_vl_num = __IB_MAX_VL_0_3;
830 *max_vl_num = __IB_MAX_VL_0_7;
832 case MLX5_VL_HW_0_14:
833 *max_vl_num = __IB_MAX_VL_0_14;
843 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
844 struct ib_port_attr *props)
846 struct mlx5_ib_dev *dev = to_mdev(ibdev);
847 struct mlx5_core_dev *mdev = dev->mdev;
848 struct mlx5_hca_vport_context *rep;
852 u8 ib_link_width_oper;
855 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
861 /* props being zeroed by the caller, avoid zeroing it here */
863 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
867 props->lid = rep->lid;
868 props->lmc = rep->lmc;
869 props->sm_lid = rep->sm_lid;
870 props->sm_sl = rep->sm_sl;
871 props->state = rep->vport_state;
872 props->phys_state = rep->port_physical_state;
873 props->port_cap_flags = rep->cap_mask1;
874 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
875 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
876 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
877 props->bad_pkey_cntr = rep->pkey_violation_counter;
878 props->qkey_viol_cntr = rep->qkey_violation_counter;
879 props->subnet_timeout = rep->subnet_timeout;
880 props->init_type_reply = rep->init_type_reply;
881 props->grh_required = rep->grh_required;
883 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
887 err = translate_active_width(ibdev, ib_link_width_oper,
888 &props->active_width);
891 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
895 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
897 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
899 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
901 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
903 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
907 err = translate_max_vl_num(ibdev, vl_hw_cap,
914 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
915 struct ib_port_attr *props)
917 switch (mlx5_get_vport_access_method(ibdev)) {
918 case MLX5_VPORT_ACCESS_METHOD_MAD:
919 return mlx5_query_mad_ifc_port(ibdev, port, props);
921 case MLX5_VPORT_ACCESS_METHOD_HCA:
922 return mlx5_query_hca_port(ibdev, port, props);
924 case MLX5_VPORT_ACCESS_METHOD_NIC:
925 return mlx5_query_port_roce(ibdev, port, props);
932 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
935 struct mlx5_ib_dev *dev = to_mdev(ibdev);
936 struct mlx5_core_dev *mdev = dev->mdev;
938 switch (mlx5_get_vport_access_method(ibdev)) {
939 case MLX5_VPORT_ACCESS_METHOD_MAD:
940 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
942 case MLX5_VPORT_ACCESS_METHOD_HCA:
943 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
951 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
954 struct mlx5_ib_dev *dev = to_mdev(ibdev);
955 struct mlx5_core_dev *mdev = dev->mdev;
957 switch (mlx5_get_vport_access_method(ibdev)) {
958 case MLX5_VPORT_ACCESS_METHOD_MAD:
959 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
961 case MLX5_VPORT_ACCESS_METHOD_HCA:
962 case MLX5_VPORT_ACCESS_METHOD_NIC:
963 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
970 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
971 struct ib_device_modify *props)
973 struct mlx5_ib_dev *dev = to_mdev(ibdev);
974 struct mlx5_reg_node_desc in;
975 struct mlx5_reg_node_desc out;
978 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
981 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
985 * If possible, pass node desc to FW, so it can generate
986 * a 144 trap. If cmd fails, just ignore.
988 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
989 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
990 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
994 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
999 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1002 struct mlx5_hca_vport_context ctx = {};
1005 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1010 if (~ctx.cap_mask1_perm & mask) {
1011 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1012 mask, ctx.cap_mask1_perm);
1016 ctx.cap_mask1 = value;
1017 ctx.cap_mask1_perm = mask;
1018 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1024 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1025 struct ib_port_modify *props)
1027 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1028 struct ib_port_attr attr;
1033 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1034 IB_LINK_LAYER_INFINIBAND);
1036 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1037 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1038 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1039 return set_port_caps_atomic(dev, port, change_mask, value);
1042 mutex_lock(&dev->cap_mask_mutex);
1044 err = ib_query_port(ibdev, port, &attr);
1048 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1049 ~props->clr_port_cap_mask;
1051 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1054 mutex_unlock(&dev->cap_mask_mutex);
1058 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1060 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1061 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1064 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1065 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1068 int uars_per_sys_page;
1069 int bfregs_per_sys_page;
1070 int ref_bfregs = req->total_num_bfregs;
1072 if (req->total_num_bfregs == 0)
1075 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1076 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1078 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1081 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1082 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1083 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1084 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1086 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1089 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1090 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1091 lib_uar_4k ? "yes" : "no", ref_bfregs,
1092 req->total_num_bfregs, *num_sys_pages);
1097 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1099 struct mlx5_bfreg_info *bfregi;
1103 bfregi = &context->bfregi;
1104 for (i = 0; i < bfregi->num_sys_pages; i++) {
1105 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1109 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1114 for (--i; i >= 0; i--)
1115 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1116 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1121 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1123 struct mlx5_bfreg_info *bfregi;
1127 bfregi = &context->bfregi;
1128 for (i = 0; i < bfregi->num_sys_pages; i++) {
1129 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1131 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1138 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1139 struct ib_udata *udata)
1141 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1142 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1143 struct mlx5_ib_alloc_ucontext_resp resp = {};
1144 struct mlx5_ib_ucontext *context;
1145 struct mlx5_bfreg_info *bfregi;
1149 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1153 if (!dev->ib_active)
1154 return ERR_PTR(-EAGAIN);
1156 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1157 return ERR_PTR(-EINVAL);
1159 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1160 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1162 else if (reqlen >= min_req_v2)
1165 return ERR_PTR(-EINVAL);
1167 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1169 return ERR_PTR(err);
1172 return ERR_PTR(-EINVAL);
1174 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1175 return ERR_PTR(-EOPNOTSUPP);
1177 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1178 MLX5_NON_FP_BFREGS_PER_UAR);
1179 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1180 return ERR_PTR(-EINVAL);
1182 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1183 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1184 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1185 resp.cache_line_size = cache_line_size();
1186 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1187 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1188 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1189 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1190 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1191 resp.cqe_version = min_t(__u8,
1192 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1193 req.max_cqe_version);
1194 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1195 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1196 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1197 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1198 resp.response_length = min(offsetof(typeof(resp), response_length) +
1199 sizeof(resp.response_length), udata->outlen);
1201 context = kzalloc(sizeof(*context), GFP_KERNEL);
1203 return ERR_PTR(-ENOMEM);
1205 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1206 bfregi = &context->bfregi;
1208 /* updates req->total_num_bfregs */
1209 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1213 mutex_init(&bfregi->lock);
1214 bfregi->lib_uar_4k = lib_uar_4k;
1215 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1217 if (!bfregi->count) {
1222 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1223 sizeof(*bfregi->sys_pages),
1225 if (!bfregi->sys_pages) {
1230 err = allocate_uars(dev, context);
1234 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1235 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1238 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1239 if (!context->upd_xlt_page) {
1243 mutex_init(&context->upd_xlt_page_mutex);
1245 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1246 err = mlx5_core_alloc_transport_domain(dev->mdev,
1252 INIT_LIST_HEAD(&context->vma_private_list);
1253 INIT_LIST_HEAD(&context->db_page_list);
1254 mutex_init(&context->db_page_mutex);
1256 resp.tot_bfregs = req.total_num_bfregs;
1257 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1259 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1260 resp.response_length += sizeof(resp.cqe_version);
1262 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1263 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1264 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1265 resp.response_length += sizeof(resp.cmds_supp_uhw);
1268 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1269 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1270 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1271 resp.eth_min_inline++;
1273 resp.response_length += sizeof(resp.eth_min_inline);
1277 * We don't want to expose information from the PCI bar that is located
1278 * after 4096 bytes, so if the arch only supports larger pages, let's
1279 * pretend we don't support reading the HCA's core clock. This is also
1280 * forced by mmap function.
1282 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1283 if (PAGE_SIZE <= 4096) {
1285 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1286 resp.hca_core_clock_offset =
1287 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1289 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1290 sizeof(resp.reserved2);
1293 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1294 resp.response_length += sizeof(resp.log_uar_size);
1296 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1297 resp.response_length += sizeof(resp.num_uars_per_page);
1299 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1304 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1305 context->cqe_version = resp.cqe_version;
1306 context->lib_caps = req.lib_caps;
1307 print_lib_caps(dev, context->lib_caps);
1309 return &context->ibucontext;
1312 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1313 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1316 free_page(context->upd_xlt_page);
1319 deallocate_uars(dev, context);
1322 kfree(bfregi->sys_pages);
1325 kfree(bfregi->count);
1330 return ERR_PTR(err);
1333 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1335 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1336 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1337 struct mlx5_bfreg_info *bfregi;
1339 bfregi = &context->bfregi;
1340 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1341 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1343 free_page(context->upd_xlt_page);
1344 deallocate_uars(dev, context);
1345 kfree(bfregi->sys_pages);
1346 kfree(bfregi->count);
1352 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1353 struct mlx5_bfreg_info *bfregi,
1356 int fw_uars_per_page;
1358 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1360 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1361 bfregi->sys_pages[idx] / fw_uars_per_page;
1364 static int get_command(unsigned long offset)
1366 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1369 static int get_arg(unsigned long offset)
1371 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1374 static int get_index(unsigned long offset)
1376 return get_arg(offset);
1379 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1381 /* vma_open is called when a new VMA is created on top of our VMA. This
1382 * is done through either mremap flow or split_vma (usually due to
1383 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1384 * as this VMA is strongly hardware related. Therefore we set the
1385 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1386 * calling us again and trying to do incorrect actions. We assume that
1387 * the original VMA size is exactly a single page, and therefore all
1388 * "splitting" operation will not happen to it.
1390 area->vm_ops = NULL;
1393 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1395 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1397 /* It's guaranteed that all VMAs opened on a FD are closed before the
1398 * file itself is closed, therefore no sync is needed with the regular
1399 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1400 * However need a sync with accessing the vma as part of
1401 * mlx5_ib_disassociate_ucontext.
1402 * The close operation is usually called under mm->mmap_sem except when
1403 * process is exiting.
1404 * The exiting case is handled explicitly as part of
1405 * mlx5_ib_disassociate_ucontext.
1407 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1409 /* setting the vma context pointer to null in the mlx5_ib driver's
1410 * private data, to protect a race condition in
1411 * mlx5_ib_disassociate_ucontext().
1413 mlx5_ib_vma_priv_data->vma = NULL;
1414 list_del(&mlx5_ib_vma_priv_data->list);
1415 kfree(mlx5_ib_vma_priv_data);
1418 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1419 .open = mlx5_ib_vma_open,
1420 .close = mlx5_ib_vma_close
1423 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1424 struct mlx5_ib_ucontext *ctx)
1426 struct mlx5_ib_vma_private_data *vma_prv;
1427 struct list_head *vma_head = &ctx->vma_private_list;
1429 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1434 vma->vm_private_data = vma_prv;
1435 vma->vm_ops = &mlx5_ib_vm_ops;
1437 list_add(&vma_prv->list, vma_head);
1442 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1445 struct vm_area_struct *vma;
1446 struct mlx5_ib_vma_private_data *vma_private, *n;
1447 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1448 struct task_struct *owning_process = NULL;
1449 struct mm_struct *owning_mm = NULL;
1451 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1452 if (!owning_process)
1455 owning_mm = get_task_mm(owning_process);
1457 pr_info("no mm, disassociate ucontext is pending task termination\n");
1459 put_task_struct(owning_process);
1460 usleep_range(1000, 2000);
1461 owning_process = get_pid_task(ibcontext->tgid,
1463 if (!owning_process ||
1464 owning_process->state == TASK_DEAD) {
1465 pr_info("disassociate ucontext done, task was terminated\n");
1466 /* in case task was dead need to release the
1470 put_task_struct(owning_process);
1476 /* need to protect from a race on closing the vma as part of
1477 * mlx5_ib_vma_close.
1479 down_read(&owning_mm->mmap_sem);
1480 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1482 vma = vma_private->vma;
1483 ret = zap_vma_ptes(vma, vma->vm_start,
1485 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1486 /* context going to be destroyed, should
1487 * not access ops any more.
1490 list_del(&vma_private->list);
1493 up_read(&owning_mm->mmap_sem);
1495 put_task_struct(owning_process);
1498 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1501 case MLX5_IB_MMAP_WC_PAGE:
1503 case MLX5_IB_MMAP_REGULAR_PAGE:
1504 return "best effort WC";
1505 case MLX5_IB_MMAP_NC_PAGE:
1512 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1513 struct vm_area_struct *vma,
1514 struct mlx5_ib_ucontext *context)
1516 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1519 phys_addr_t pfn, pa;
1523 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1526 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1527 idx = get_index(vma->vm_pgoff);
1528 if (idx % uars_per_page ||
1529 idx * uars_per_page >= bfregi->num_sys_pages) {
1530 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1535 case MLX5_IB_MMAP_WC_PAGE:
1536 /* Some architectures don't support WC memory */
1537 #if defined(CONFIG_X86)
1540 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1544 case MLX5_IB_MMAP_REGULAR_PAGE:
1545 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1546 prot = pgprot_writecombine(vma->vm_page_prot);
1548 case MLX5_IB_MMAP_NC_PAGE:
1549 prot = pgprot_noncached(vma->vm_page_prot);
1555 pfn = uar_index2pfn(dev, bfregi, idx);
1556 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1558 vma->vm_page_prot = prot;
1559 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1560 PAGE_SIZE, vma->vm_page_prot);
1562 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1563 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1567 pa = pfn << PAGE_SHIFT;
1568 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1569 vma->vm_start, &pa);
1571 return mlx5_ib_set_vma_data(vma, context);
1574 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1576 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1577 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1578 unsigned long command;
1581 command = get_command(vma->vm_pgoff);
1583 case MLX5_IB_MMAP_WC_PAGE:
1584 case MLX5_IB_MMAP_NC_PAGE:
1585 case MLX5_IB_MMAP_REGULAR_PAGE:
1586 return uar_mmap(dev, command, vma, context);
1588 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1591 case MLX5_IB_MMAP_CORE_CLOCK:
1592 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1595 if (vma->vm_flags & VM_WRITE)
1598 /* Don't expose to user-space information it shouldn't have */
1599 if (PAGE_SIZE > 4096)
1602 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1603 pfn = (dev->mdev->iseg_base +
1604 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1606 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1607 PAGE_SIZE, vma->vm_page_prot))
1610 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1612 (unsigned long long)pfn << PAGE_SHIFT);
1622 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1623 struct ib_ucontext *context,
1624 struct ib_udata *udata)
1626 struct mlx5_ib_alloc_pd_resp resp;
1627 struct mlx5_ib_pd *pd;
1630 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1632 return ERR_PTR(-ENOMEM);
1634 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1637 return ERR_PTR(err);
1642 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1643 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1645 return ERR_PTR(-EFAULT);
1652 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1654 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1655 struct mlx5_ib_pd *mpd = to_mpd(pd);
1657 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1664 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1665 MATCH_CRITERIA_ENABLE_MISC_BIT,
1666 MATCH_CRITERIA_ENABLE_INNER_BIT
1669 #define HEADER_IS_ZERO(match_criteria, headers) \
1670 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1671 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1673 static u8 get_match_criteria_enable(u32 *match_criteria)
1675 u8 match_criteria_enable;
1677 match_criteria_enable =
1678 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1679 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1680 match_criteria_enable |=
1681 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1682 MATCH_CRITERIA_ENABLE_MISC_BIT;
1683 match_criteria_enable |=
1684 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1685 MATCH_CRITERIA_ENABLE_INNER_BIT;
1687 return match_criteria_enable;
1690 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1692 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1693 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1696 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1700 MLX5_SET(fte_match_set_misc,
1701 misc_c, inner_ipv6_flow_label, mask);
1702 MLX5_SET(fte_match_set_misc,
1703 misc_v, inner_ipv6_flow_label, val);
1705 MLX5_SET(fte_match_set_misc,
1706 misc_c, outer_ipv6_flow_label, mask);
1707 MLX5_SET(fte_match_set_misc,
1708 misc_v, outer_ipv6_flow_label, val);
1712 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1714 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1715 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1716 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1717 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1720 #define LAST_ETH_FIELD vlan_tag
1721 #define LAST_IB_FIELD sl
1722 #define LAST_IPV4_FIELD tos
1723 #define LAST_IPV6_FIELD traffic_class
1724 #define LAST_TCP_UDP_FIELD src_port
1725 #define LAST_TUNNEL_FIELD tunnel_id
1726 #define LAST_FLOW_TAG_FIELD tag_id
1728 /* Field is the last supported field */
1729 #define FIELDS_NOT_SUPPORTED(filter, field)\
1730 memchr_inv((void *)&filter.field +\
1731 sizeof(filter.field), 0,\
1733 offsetof(typeof(filter), field) -\
1734 sizeof(filter.field))
1736 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1737 const union ib_flow_spec *ib_spec, u32 *tag_id)
1739 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1741 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1746 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1747 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1749 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1752 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1754 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1758 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1759 case IB_FLOW_SPEC_ETH:
1760 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1763 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1765 ib_spec->eth.mask.dst_mac);
1766 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1768 ib_spec->eth.val.dst_mac);
1770 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1772 ib_spec->eth.mask.src_mac);
1773 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1775 ib_spec->eth.val.src_mac);
1777 if (ib_spec->eth.mask.vlan_tag) {
1778 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1780 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1783 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1784 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1785 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1786 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1788 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1790 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1791 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1793 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1795 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1797 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1798 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1800 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1802 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1803 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1804 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1805 ethertype, ntohs(ib_spec->eth.val.ether_type));
1807 case IB_FLOW_SPEC_IPV4:
1808 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1811 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1813 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1814 ethertype, ETH_P_IP);
1816 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1817 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1818 &ib_spec->ipv4.mask.src_ip,
1819 sizeof(ib_spec->ipv4.mask.src_ip));
1820 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1821 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1822 &ib_spec->ipv4.val.src_ip,
1823 sizeof(ib_spec->ipv4.val.src_ip));
1824 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1825 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1826 &ib_spec->ipv4.mask.dst_ip,
1827 sizeof(ib_spec->ipv4.mask.dst_ip));
1828 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1829 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1830 &ib_spec->ipv4.val.dst_ip,
1831 sizeof(ib_spec->ipv4.val.dst_ip));
1833 set_tos(headers_c, headers_v,
1834 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1836 set_proto(headers_c, headers_v,
1837 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1839 case IB_FLOW_SPEC_IPV6:
1840 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1843 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1845 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1846 ethertype, ETH_P_IPV6);
1848 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1849 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1850 &ib_spec->ipv6.mask.src_ip,
1851 sizeof(ib_spec->ipv6.mask.src_ip));
1852 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1853 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1854 &ib_spec->ipv6.val.src_ip,
1855 sizeof(ib_spec->ipv6.val.src_ip));
1856 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1857 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1858 &ib_spec->ipv6.mask.dst_ip,
1859 sizeof(ib_spec->ipv6.mask.dst_ip));
1860 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1861 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1862 &ib_spec->ipv6.val.dst_ip,
1863 sizeof(ib_spec->ipv6.val.dst_ip));
1865 set_tos(headers_c, headers_v,
1866 ib_spec->ipv6.mask.traffic_class,
1867 ib_spec->ipv6.val.traffic_class);
1869 set_proto(headers_c, headers_v,
1870 ib_spec->ipv6.mask.next_hdr,
1871 ib_spec->ipv6.val.next_hdr);
1873 set_flow_label(misc_params_c, misc_params_v,
1874 ntohl(ib_spec->ipv6.mask.flow_label),
1875 ntohl(ib_spec->ipv6.val.flow_label),
1876 ib_spec->type & IB_FLOW_SPEC_INNER);
1879 case IB_FLOW_SPEC_TCP:
1880 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1881 LAST_TCP_UDP_FIELD))
1884 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1886 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1889 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
1890 ntohs(ib_spec->tcp_udp.mask.src_port));
1891 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1892 ntohs(ib_spec->tcp_udp.val.src_port));
1894 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
1895 ntohs(ib_spec->tcp_udp.mask.dst_port));
1896 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1897 ntohs(ib_spec->tcp_udp.val.dst_port));
1899 case IB_FLOW_SPEC_UDP:
1900 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1901 LAST_TCP_UDP_FIELD))
1904 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1906 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1909 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
1910 ntohs(ib_spec->tcp_udp.mask.src_port));
1911 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1912 ntohs(ib_spec->tcp_udp.val.src_port));
1914 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
1915 ntohs(ib_spec->tcp_udp.mask.dst_port));
1916 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1917 ntohs(ib_spec->tcp_udp.val.dst_port));
1919 case IB_FLOW_SPEC_VXLAN_TUNNEL:
1920 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1924 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1925 ntohl(ib_spec->tunnel.mask.tunnel_id));
1926 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1927 ntohl(ib_spec->tunnel.val.tunnel_id));
1929 case IB_FLOW_SPEC_ACTION_TAG:
1930 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
1931 LAST_FLOW_TAG_FIELD))
1933 if (ib_spec->flow_tag.tag_id >= BIT(24))
1936 *tag_id = ib_spec->flow_tag.tag_id;
1945 /* If a flow could catch both multicast and unicast packets,
1946 * it won't fall into the multicast flow steering table and this rule
1947 * could steal other multicast packets.
1949 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1951 struct ib_flow_spec_eth *eth_spec;
1953 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1954 ib_attr->size < sizeof(struct ib_flow_attr) +
1955 sizeof(struct ib_flow_spec_eth) ||
1956 ib_attr->num_of_specs < 1)
1959 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1960 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1961 eth_spec->size != sizeof(*eth_spec))
1964 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1965 is_multicast_ether_addr(eth_spec->val.dst_mac);
1968 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1970 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1971 bool has_ipv4_spec = false;
1972 bool eth_type_ipv4 = true;
1973 unsigned int spec_index;
1975 /* Validate that ethertype is correct */
1976 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1977 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1978 ib_spec->eth.mask.ether_type) {
1979 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1980 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1981 eth_type_ipv4 = false;
1982 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1983 has_ipv4_spec = true;
1985 ib_spec = (void *)ib_spec + ib_spec->size;
1987 return !has_ipv4_spec || eth_type_ipv4;
1990 static void put_flow_table(struct mlx5_ib_dev *dev,
1991 struct mlx5_ib_flow_prio *prio, bool ft_added)
1993 prio->refcount -= !!ft_added;
1994 if (!prio->refcount) {
1995 mlx5_destroy_flow_table(prio->flow_table);
1996 prio->flow_table = NULL;
2000 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2002 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2003 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2004 struct mlx5_ib_flow_handler,
2006 struct mlx5_ib_flow_handler *iter, *tmp;
2008 mutex_lock(&dev->flow_db.lock);
2010 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2011 mlx5_del_flow_rules(iter->rule);
2012 put_flow_table(dev, iter->prio, true);
2013 list_del(&iter->list);
2017 mlx5_del_flow_rules(handler->rule);
2018 put_flow_table(dev, handler->prio, true);
2019 mutex_unlock(&dev->flow_db.lock);
2026 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2034 enum flow_table_type {
2039 #define MLX5_FS_MAX_TYPES 10
2040 #define MLX5_FS_MAX_ENTRIES 32000UL
2041 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2042 struct ib_flow_attr *flow_attr,
2043 enum flow_table_type ft_type)
2045 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2046 struct mlx5_flow_namespace *ns = NULL;
2047 struct mlx5_ib_flow_prio *prio;
2048 struct mlx5_flow_table *ft;
2054 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2055 if (flow_is_multicast_only(flow_attr) &&
2057 priority = MLX5_IB_FLOW_MCAST_PRIO;
2059 priority = ib_prio_to_core_prio(flow_attr->priority,
2061 ns = mlx5_get_flow_namespace(dev->mdev,
2062 MLX5_FLOW_NAMESPACE_BYPASS);
2063 num_entries = MLX5_FS_MAX_ENTRIES;
2064 num_groups = MLX5_FS_MAX_TYPES;
2065 prio = &dev->flow_db.prios[priority];
2066 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2067 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2068 ns = mlx5_get_flow_namespace(dev->mdev,
2069 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2070 build_leftovers_ft_param(&priority,
2073 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2074 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2075 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2076 allow_sniffer_and_nic_rx_shared_tir))
2077 return ERR_PTR(-ENOTSUPP);
2079 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2080 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2081 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2083 prio = &dev->flow_db.sniffer[ft_type];
2090 return ERR_PTR(-ENOTSUPP);
2092 ft = prio->flow_table;
2094 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2101 prio->flow_table = ft;
2107 return err ? ERR_PTR(err) : prio;
2110 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2111 struct mlx5_ib_flow_prio *ft_prio,
2112 const struct ib_flow_attr *flow_attr,
2113 struct mlx5_flow_destination *dst)
2115 struct mlx5_flow_table *ft = ft_prio->flow_table;
2116 struct mlx5_ib_flow_handler *handler;
2117 struct mlx5_flow_act flow_act = {0};
2118 struct mlx5_flow_spec *spec;
2119 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2120 unsigned int spec_index;
2121 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2124 if (!is_valid_attr(flow_attr))
2125 return ERR_PTR(-EINVAL);
2127 spec = mlx5_vzalloc(sizeof(*spec));
2128 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2129 if (!handler || !spec) {
2134 INIT_LIST_HEAD(&handler->list);
2136 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2137 err = parse_flow_attr(spec->match_criteria,
2138 spec->match_value, ib_flow, &flow_tag);
2142 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2145 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2146 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2147 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2149 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2150 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2151 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2152 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2153 flow_tag, flow_attr->type);
2157 flow_act.flow_tag = flow_tag;
2158 handler->rule = mlx5_add_flow_rules(ft, spec,
2162 if (IS_ERR(handler->rule)) {
2163 err = PTR_ERR(handler->rule);
2167 ft_prio->refcount++;
2168 handler->prio = ft_prio;
2170 ft_prio->flow_table = ft;
2175 return err ? ERR_PTR(err) : handler;
2178 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2179 struct mlx5_ib_flow_prio *ft_prio,
2180 struct ib_flow_attr *flow_attr,
2181 struct mlx5_flow_destination *dst)
2183 struct mlx5_ib_flow_handler *handler_dst = NULL;
2184 struct mlx5_ib_flow_handler *handler = NULL;
2186 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2187 if (!IS_ERR(handler)) {
2188 handler_dst = create_flow_rule(dev, ft_prio,
2190 if (IS_ERR(handler_dst)) {
2191 mlx5_del_flow_rules(handler->rule);
2192 ft_prio->refcount--;
2194 handler = handler_dst;
2196 list_add(&handler_dst->list, &handler->list);
2207 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2208 struct mlx5_ib_flow_prio *ft_prio,
2209 struct ib_flow_attr *flow_attr,
2210 struct mlx5_flow_destination *dst)
2212 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2213 struct mlx5_ib_flow_handler *handler = NULL;
2216 struct ib_flow_attr flow_attr;
2217 struct ib_flow_spec_eth eth_flow;
2218 } leftovers_specs[] = {
2222 .size = sizeof(leftovers_specs[0])
2225 .type = IB_FLOW_SPEC_ETH,
2226 .size = sizeof(struct ib_flow_spec_eth),
2227 .mask = {.dst_mac = {0x1} },
2228 .val = {.dst_mac = {0x1} }
2234 .size = sizeof(leftovers_specs[0])
2237 .type = IB_FLOW_SPEC_ETH,
2238 .size = sizeof(struct ib_flow_spec_eth),
2239 .mask = {.dst_mac = {0x1} },
2240 .val = {.dst_mac = {} }
2245 handler = create_flow_rule(dev, ft_prio,
2246 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2248 if (!IS_ERR(handler) &&
2249 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2250 handler_ucast = create_flow_rule(dev, ft_prio,
2251 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2253 if (IS_ERR(handler_ucast)) {
2254 mlx5_del_flow_rules(handler->rule);
2255 ft_prio->refcount--;
2257 handler = handler_ucast;
2259 list_add(&handler_ucast->list, &handler->list);
2266 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2267 struct mlx5_ib_flow_prio *ft_rx,
2268 struct mlx5_ib_flow_prio *ft_tx,
2269 struct mlx5_flow_destination *dst)
2271 struct mlx5_ib_flow_handler *handler_rx;
2272 struct mlx5_ib_flow_handler *handler_tx;
2274 static const struct ib_flow_attr flow_attr = {
2276 .size = sizeof(flow_attr)
2279 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2280 if (IS_ERR(handler_rx)) {
2281 err = PTR_ERR(handler_rx);
2285 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2286 if (IS_ERR(handler_tx)) {
2287 err = PTR_ERR(handler_tx);
2291 list_add(&handler_tx->list, &handler_rx->list);
2296 mlx5_del_flow_rules(handler_rx->rule);
2300 return ERR_PTR(err);
2303 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2304 struct ib_flow_attr *flow_attr,
2307 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2308 struct mlx5_ib_qp *mqp = to_mqp(qp);
2309 struct mlx5_ib_flow_handler *handler = NULL;
2310 struct mlx5_flow_destination *dst = NULL;
2311 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2312 struct mlx5_ib_flow_prio *ft_prio;
2315 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2316 return ERR_PTR(-ENOSPC);
2318 if (domain != IB_FLOW_DOMAIN_USER ||
2319 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2320 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2321 return ERR_PTR(-EINVAL);
2323 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2325 return ERR_PTR(-ENOMEM);
2327 mutex_lock(&dev->flow_db.lock);
2329 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2330 if (IS_ERR(ft_prio)) {
2331 err = PTR_ERR(ft_prio);
2334 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2335 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2336 if (IS_ERR(ft_prio_tx)) {
2337 err = PTR_ERR(ft_prio_tx);
2343 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2344 if (mqp->flags & MLX5_IB_QP_RSS)
2345 dst->tir_num = mqp->rss_qp.tirn;
2347 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2349 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2350 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2351 handler = create_dont_trap_rule(dev, ft_prio,
2354 handler = create_flow_rule(dev, ft_prio, flow_attr,
2357 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2358 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2359 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2361 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2362 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2368 if (IS_ERR(handler)) {
2369 err = PTR_ERR(handler);
2374 mutex_unlock(&dev->flow_db.lock);
2377 return &handler->ibflow;
2380 put_flow_table(dev, ft_prio, false);
2382 put_flow_table(dev, ft_prio_tx, false);
2384 mutex_unlock(&dev->flow_db.lock);
2387 return ERR_PTR(err);
2390 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2392 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2395 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2397 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2398 ibqp->qp_num, gid->raw);
2403 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2405 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2408 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2410 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2411 ibqp->qp_num, gid->raw);
2416 static int init_node_data(struct mlx5_ib_dev *dev)
2420 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2424 dev->mdev->rev_id = dev->mdev->pdev->revision;
2426 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2429 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2432 struct mlx5_ib_dev *dev =
2433 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2435 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2438 static ssize_t show_reg_pages(struct device *device,
2439 struct device_attribute *attr, char *buf)
2441 struct mlx5_ib_dev *dev =
2442 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2444 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2447 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2450 struct mlx5_ib_dev *dev =
2451 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2452 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2455 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2458 struct mlx5_ib_dev *dev =
2459 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2460 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2463 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2466 struct mlx5_ib_dev *dev =
2467 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2468 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2469 dev->mdev->board_id);
2472 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2473 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2474 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2475 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2476 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2478 static struct device_attribute *mlx5_class_attributes[] = {
2483 &dev_attr_reg_pages,
2486 static void pkey_change_handler(struct work_struct *work)
2488 struct mlx5_ib_port_resources *ports =
2489 container_of(work, struct mlx5_ib_port_resources,
2492 mutex_lock(&ports->devr->mutex);
2493 mlx5_ib_gsi_pkey_change(ports->gsi);
2494 mutex_unlock(&ports->devr->mutex);
2497 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2499 struct mlx5_ib_qp *mqp;
2500 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2501 struct mlx5_core_cq *mcq;
2502 struct list_head cq_armed_list;
2503 unsigned long flags_qp;
2504 unsigned long flags_cq;
2505 unsigned long flags;
2507 INIT_LIST_HEAD(&cq_armed_list);
2509 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2510 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2511 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2512 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2513 if (mqp->sq.tail != mqp->sq.head) {
2514 send_mcq = to_mcq(mqp->ibqp.send_cq);
2515 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2516 if (send_mcq->mcq.comp &&
2517 mqp->ibqp.send_cq->comp_handler) {
2518 if (!send_mcq->mcq.reset_notify_added) {
2519 send_mcq->mcq.reset_notify_added = 1;
2520 list_add_tail(&send_mcq->mcq.reset_notify,
2524 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2526 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2527 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2528 /* no handling is needed for SRQ */
2529 if (!mqp->ibqp.srq) {
2530 if (mqp->rq.tail != mqp->rq.head) {
2531 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2532 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2533 if (recv_mcq->mcq.comp &&
2534 mqp->ibqp.recv_cq->comp_handler) {
2535 if (!recv_mcq->mcq.reset_notify_added) {
2536 recv_mcq->mcq.reset_notify_added = 1;
2537 list_add_tail(&recv_mcq->mcq.reset_notify,
2541 spin_unlock_irqrestore(&recv_mcq->lock,
2545 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2547 /*At that point all inflight post send were put to be executed as of we
2548 * lock/unlock above locks Now need to arm all involved CQs.
2550 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2553 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2556 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2557 enum mlx5_dev_event event, unsigned long param)
2559 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2560 struct ib_event ibev;
2565 case MLX5_DEV_EVENT_SYS_ERROR:
2566 ibev.event = IB_EVENT_DEVICE_FATAL;
2567 mlx5_ib_handle_internal_error(ibdev);
2571 case MLX5_DEV_EVENT_PORT_UP:
2572 case MLX5_DEV_EVENT_PORT_DOWN:
2573 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2576 /* In RoCE, port up/down events are handled in
2577 * mlx5_netdev_event().
2579 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2580 IB_LINK_LAYER_ETHERNET)
2583 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2584 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2587 case MLX5_DEV_EVENT_LID_CHANGE:
2588 ibev.event = IB_EVENT_LID_CHANGE;
2592 case MLX5_DEV_EVENT_PKEY_CHANGE:
2593 ibev.event = IB_EVENT_PKEY_CHANGE;
2596 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2599 case MLX5_DEV_EVENT_GUID_CHANGE:
2600 ibev.event = IB_EVENT_GID_CHANGE;
2604 case MLX5_DEV_EVENT_CLIENT_REREG:
2605 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2612 ibev.device = &ibdev->ib_dev;
2613 ibev.element.port_num = port;
2615 if (port < 1 || port > ibdev->num_ports) {
2616 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2620 if (ibdev->ib_active)
2621 ib_dispatch_event(&ibev);
2624 ibdev->ib_active = false;
2627 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2629 struct mlx5_hca_vport_context vport_ctx;
2633 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2634 dev->mdev->port_caps[port - 1].has_smi = false;
2635 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2636 MLX5_CAP_PORT_TYPE_IB) {
2637 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2638 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2642 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2646 dev->mdev->port_caps[port - 1].has_smi =
2649 dev->mdev->port_caps[port - 1].has_smi = true;
2656 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2660 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2661 mlx5_query_ext_port_caps(dev, port);
2664 static int get_port_caps(struct mlx5_ib_dev *dev)
2666 struct ib_device_attr *dprops = NULL;
2667 struct ib_port_attr *pprops = NULL;
2670 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2672 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2676 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2680 err = set_has_smi_cap(dev);
2684 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2686 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2690 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2691 memset(pprops, 0, sizeof(*pprops));
2692 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2694 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2698 dev->mdev->port_caps[port - 1].pkey_table_len =
2700 dev->mdev->port_caps[port - 1].gid_table_len =
2701 pprops->gid_tbl_len;
2702 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2703 dprops->max_pkeys, pprops->gid_tbl_len);
2713 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2717 err = mlx5_mr_cache_cleanup(dev);
2719 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2721 mlx5_ib_destroy_qp(dev->umrc.qp);
2722 ib_free_cq(dev->umrc.cq);
2723 ib_dealloc_pd(dev->umrc.pd);
2730 static int create_umr_res(struct mlx5_ib_dev *dev)
2732 struct ib_qp_init_attr *init_attr = NULL;
2733 struct ib_qp_attr *attr = NULL;
2739 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2740 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2741 if (!attr || !init_attr) {
2746 pd = ib_alloc_pd(&dev->ib_dev, 0);
2748 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2753 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2755 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2760 init_attr->send_cq = cq;
2761 init_attr->recv_cq = cq;
2762 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2763 init_attr->cap.max_send_wr = MAX_UMR_WR;
2764 init_attr->cap.max_send_sge = 1;
2765 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2766 init_attr->port_num = 1;
2767 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2769 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2773 qp->device = &dev->ib_dev;
2776 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2778 attr->qp_state = IB_QPS_INIT;
2780 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2783 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2787 memset(attr, 0, sizeof(*attr));
2788 attr->qp_state = IB_QPS_RTR;
2789 attr->path_mtu = IB_MTU_256;
2791 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2793 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2797 memset(attr, 0, sizeof(*attr));
2798 attr->qp_state = IB_QPS_RTS;
2799 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2801 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2809 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2810 ret = mlx5_mr_cache_init(dev);
2812 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2822 mlx5_ib_destroy_qp(qp);
2836 static int create_dev_resources(struct mlx5_ib_resources *devr)
2838 struct ib_srq_init_attr attr;
2839 struct mlx5_ib_dev *dev;
2840 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2844 dev = container_of(devr, struct mlx5_ib_dev, devr);
2846 mutex_init(&devr->mutex);
2848 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2849 if (IS_ERR(devr->p0)) {
2850 ret = PTR_ERR(devr->p0);
2853 devr->p0->device = &dev->ib_dev;
2854 devr->p0->uobject = NULL;
2855 atomic_set(&devr->p0->usecnt, 0);
2857 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2858 if (IS_ERR(devr->c0)) {
2859 ret = PTR_ERR(devr->c0);
2862 devr->c0->device = &dev->ib_dev;
2863 devr->c0->uobject = NULL;
2864 devr->c0->comp_handler = NULL;
2865 devr->c0->event_handler = NULL;
2866 devr->c0->cq_context = NULL;
2867 atomic_set(&devr->c0->usecnt, 0);
2869 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2870 if (IS_ERR(devr->x0)) {
2871 ret = PTR_ERR(devr->x0);
2874 devr->x0->device = &dev->ib_dev;
2875 devr->x0->inode = NULL;
2876 atomic_set(&devr->x0->usecnt, 0);
2877 mutex_init(&devr->x0->tgt_qp_mutex);
2878 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2880 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2881 if (IS_ERR(devr->x1)) {
2882 ret = PTR_ERR(devr->x1);
2885 devr->x1->device = &dev->ib_dev;
2886 devr->x1->inode = NULL;
2887 atomic_set(&devr->x1->usecnt, 0);
2888 mutex_init(&devr->x1->tgt_qp_mutex);
2889 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2891 memset(&attr, 0, sizeof(attr));
2892 attr.attr.max_sge = 1;
2893 attr.attr.max_wr = 1;
2894 attr.srq_type = IB_SRQT_XRC;
2895 attr.ext.xrc.cq = devr->c0;
2896 attr.ext.xrc.xrcd = devr->x0;
2898 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2899 if (IS_ERR(devr->s0)) {
2900 ret = PTR_ERR(devr->s0);
2903 devr->s0->device = &dev->ib_dev;
2904 devr->s0->pd = devr->p0;
2905 devr->s0->uobject = NULL;
2906 devr->s0->event_handler = NULL;
2907 devr->s0->srq_context = NULL;
2908 devr->s0->srq_type = IB_SRQT_XRC;
2909 devr->s0->ext.xrc.xrcd = devr->x0;
2910 devr->s0->ext.xrc.cq = devr->c0;
2911 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2912 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2913 atomic_inc(&devr->p0->usecnt);
2914 atomic_set(&devr->s0->usecnt, 0);
2916 memset(&attr, 0, sizeof(attr));
2917 attr.attr.max_sge = 1;
2918 attr.attr.max_wr = 1;
2919 attr.srq_type = IB_SRQT_BASIC;
2920 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2921 if (IS_ERR(devr->s1)) {
2922 ret = PTR_ERR(devr->s1);
2925 devr->s1->device = &dev->ib_dev;
2926 devr->s1->pd = devr->p0;
2927 devr->s1->uobject = NULL;
2928 devr->s1->event_handler = NULL;
2929 devr->s1->srq_context = NULL;
2930 devr->s1->srq_type = IB_SRQT_BASIC;
2931 devr->s1->ext.xrc.cq = devr->c0;
2932 atomic_inc(&devr->p0->usecnt);
2933 atomic_set(&devr->s0->usecnt, 0);
2935 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2936 INIT_WORK(&devr->ports[port].pkey_change_work,
2937 pkey_change_handler);
2938 devr->ports[port].devr = devr;
2944 mlx5_ib_destroy_srq(devr->s0);
2946 mlx5_ib_dealloc_xrcd(devr->x1);
2948 mlx5_ib_dealloc_xrcd(devr->x0);
2950 mlx5_ib_destroy_cq(devr->c0);
2952 mlx5_ib_dealloc_pd(devr->p0);
2957 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2959 struct mlx5_ib_dev *dev =
2960 container_of(devr, struct mlx5_ib_dev, devr);
2963 mlx5_ib_destroy_srq(devr->s1);
2964 mlx5_ib_destroy_srq(devr->s0);
2965 mlx5_ib_dealloc_xrcd(devr->x0);
2966 mlx5_ib_dealloc_xrcd(devr->x1);
2967 mlx5_ib_destroy_cq(devr->c0);
2968 mlx5_ib_dealloc_pd(devr->p0);
2970 /* Make sure no change P_Key work items are still executing */
2971 for (port = 0; port < dev->num_ports; ++port)
2972 cancel_work_sync(&devr->ports[port].pkey_change_work);
2975 static u32 get_core_cap_flags(struct ib_device *ibdev)
2977 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2978 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2979 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2980 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2983 if (ll == IB_LINK_LAYER_INFINIBAND)
2984 return RDMA_CORE_PORT_IBA_IB;
2986 ret = RDMA_CORE_PORT_RAW_PACKET;
2988 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2991 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2994 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2995 ret |= RDMA_CORE_PORT_IBA_ROCE;
2997 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2998 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3003 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3004 struct ib_port_immutable *immutable)
3006 struct ib_port_attr attr;
3007 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3008 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3011 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3013 err = ib_query_port(ibdev, port_num, &attr);
3017 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3018 immutable->gid_tbl_len = attr.gid_tbl_len;
3019 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3020 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3021 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3026 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3029 struct mlx5_ib_dev *dev =
3030 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3031 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3032 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3035 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3037 struct mlx5_core_dev *mdev = dev->mdev;
3038 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3039 MLX5_FLOW_NAMESPACE_LAG);
3040 struct mlx5_flow_table *ft;
3043 if (!ns || !mlx5_lag_is_active(mdev))
3046 err = mlx5_cmd_create_vport_lag(mdev);
3050 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3053 goto err_destroy_vport_lag;
3056 dev->flow_db.lag_demux_ft = ft;
3059 err_destroy_vport_lag:
3060 mlx5_cmd_destroy_vport_lag(mdev);
3064 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3066 struct mlx5_core_dev *mdev = dev->mdev;
3068 if (dev->flow_db.lag_demux_ft) {
3069 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3070 dev->flow_db.lag_demux_ft = NULL;
3072 mlx5_cmd_destroy_vport_lag(mdev);
3076 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3080 dev->roce.nb.notifier_call = mlx5_netdev_event;
3081 err = register_netdevice_notifier(&dev->roce.nb);
3083 dev->roce.nb.notifier_call = NULL;
3090 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3092 if (dev->roce.nb.notifier_call) {
3093 unregister_netdevice_notifier(&dev->roce.nb);
3094 dev->roce.nb.notifier_call = NULL;
3098 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3102 err = mlx5_add_netdev_notifier(dev);
3106 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3107 err = mlx5_nic_vport_enable_roce(dev->mdev);
3109 goto err_unregister_netdevice_notifier;
3112 err = mlx5_eth_lag_init(dev);
3114 goto err_disable_roce;
3119 if (MLX5_CAP_GEN(dev->mdev, roce))
3120 mlx5_nic_vport_disable_roce(dev->mdev);
3122 err_unregister_netdevice_notifier:
3123 mlx5_remove_netdev_notifier(dev);
3127 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3129 mlx5_eth_lag_cleanup(dev);
3130 if (MLX5_CAP_GEN(dev->mdev, roce))
3131 mlx5_nic_vport_disable_roce(dev->mdev);
3134 struct mlx5_ib_q_counter {
3139 #define INIT_Q_COUNTER(_name) \
3140 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3142 static const struct mlx5_ib_q_counter basic_q_cnts[] = {
3143 INIT_Q_COUNTER(rx_write_requests),
3144 INIT_Q_COUNTER(rx_read_requests),
3145 INIT_Q_COUNTER(rx_atomic_requests),
3146 INIT_Q_COUNTER(out_of_buffer),
3149 static const struct mlx5_ib_q_counter out_of_seq_q_cnts[] = {
3150 INIT_Q_COUNTER(out_of_sequence),
3153 static const struct mlx5_ib_q_counter retrans_q_cnts[] = {
3154 INIT_Q_COUNTER(duplicate_request),
3155 INIT_Q_COUNTER(rnr_nak_retry_err),
3156 INIT_Q_COUNTER(packet_seq_err),
3157 INIT_Q_COUNTER(implied_nak_seq_err),
3158 INIT_Q_COUNTER(local_ack_timeout_err),
3161 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
3165 for (i = 0; i < dev->num_ports; i++) {
3166 mlx5_core_dealloc_q_counter(dev->mdev,
3167 dev->port[i].q_cnts.set_id);
3168 kfree(dev->port[i].q_cnts.names);
3169 kfree(dev->port[i].q_cnts.offsets);
3173 static int __mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev,
3174 const char ***names,
3180 num_counters = ARRAY_SIZE(basic_q_cnts);
3182 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3183 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3185 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3186 num_counters += ARRAY_SIZE(retrans_q_cnts);
3188 *names = kcalloc(num_counters, sizeof(**names), GFP_KERNEL);
3192 *offsets = kcalloc(num_counters, sizeof(**offsets), GFP_KERNEL);
3196 *num = num_counters;
3205 static void mlx5_ib_fill_q_counters(struct mlx5_ib_dev *dev,
3212 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3213 names[j] = basic_q_cnts[i].name;
3214 offsets[j] = basic_q_cnts[i].offset;
3217 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3218 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3219 names[j] = out_of_seq_q_cnts[i].name;
3220 offsets[j] = out_of_seq_q_cnts[i].offset;
3224 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3225 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3226 names[j] = retrans_q_cnts[i].name;
3227 offsets[j] = retrans_q_cnts[i].offset;
3232 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
3237 for (i = 0; i < dev->num_ports; i++) {
3238 struct mlx5_ib_port *port = &dev->port[i];
3240 ret = mlx5_core_alloc_q_counter(dev->mdev,
3241 &port->q_cnts.set_id);
3244 "couldn't allocate queue counter for port %d, err %d\n",
3246 goto dealloc_counters;
3249 ret = __mlx5_ib_alloc_q_counters(dev,
3250 &port->q_cnts.names,
3251 &port->q_cnts.offsets,
3252 &port->q_cnts.num_counters);
3254 goto dealloc_counters;
3256 mlx5_ib_fill_q_counters(dev, port->q_cnts.names,
3257 port->q_cnts.offsets);
3264 mlx5_core_dealloc_q_counter(dev->mdev,
3265 dev->port[i].q_cnts.set_id);
3270 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3273 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3274 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3276 /* We support only per port stats */
3280 return rdma_alloc_hw_stats_struct(port->q_cnts.names,
3281 port->q_cnts.num_counters,
3282 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3285 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3286 struct rdma_hw_stats *stats,
3287 u8 port_num, int index)
3289 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3290 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3291 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3300 out = mlx5_vzalloc(outlen);
3304 ret = mlx5_core_query_q_counter(dev->mdev,
3305 port->q_cnts.set_id, 0,
3310 for (i = 0; i < port->q_cnts.num_counters; i++) {
3311 val = *(__be32 *)(out + port->q_cnts.offsets[i]);
3312 stats->value[i] = (u64)be32_to_cpu(val);
3317 return port->q_cnts.num_counters;
3320 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3322 struct mlx5_ib_dev *dev;
3323 enum rdma_link_layer ll;
3329 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3330 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3332 printk_once(KERN_INFO "%s", mlx5_version);
3334 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3340 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3345 rwlock_init(&dev->roce.netdev_lock);
3346 err = get_port_caps(dev);
3350 if (mlx5_use_mad_ifc(dev))
3351 get_ext_port_caps(dev);
3353 if (!mlx5_lag_is_active(mdev))
3356 name = "mlx5_bond_%d";
3358 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3359 dev->ib_dev.owner = THIS_MODULE;
3360 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3361 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3362 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3363 dev->ib_dev.phys_port_cnt = dev->num_ports;
3364 dev->ib_dev.num_comp_vectors =
3365 dev->mdev->priv.eq_table.num_comp_vectors;
3366 dev->ib_dev.dma_device = &mdev->pdev->dev;
3368 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3369 dev->ib_dev.uverbs_cmd_mask =
3370 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3371 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3372 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3373 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3374 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3375 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3376 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
3377 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3378 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3379 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3380 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3381 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3382 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3383 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3384 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3385 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3386 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3387 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3388 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3389 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3390 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3391 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3392 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3393 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3394 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3395 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3396 dev->ib_dev.uverbs_ex_cmd_mask =
3397 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3398 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3399 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3400 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3402 dev->ib_dev.query_device = mlx5_ib_query_device;
3403 dev->ib_dev.query_port = mlx5_ib_query_port;
3404 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3405 if (ll == IB_LINK_LAYER_ETHERNET)
3406 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3407 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3408 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3409 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3410 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3411 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3412 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3413 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3414 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3415 dev->ib_dev.mmap = mlx5_ib_mmap;
3416 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3417 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3418 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3419 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3420 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3421 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3422 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3423 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3424 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3425 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3426 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3427 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3428 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3429 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3430 dev->ib_dev.post_send = mlx5_ib_post_send;
3431 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3432 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3433 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3434 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3435 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3436 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3437 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3438 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3439 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3440 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3441 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3442 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3443 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3444 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3445 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3446 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3447 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3448 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3449 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3450 if (mlx5_core_is_pf(mdev)) {
3451 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3452 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3453 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3454 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3457 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3459 mlx5_ib_internal_fill_odp_caps(dev);
3461 if (MLX5_CAP_GEN(mdev, imaicl)) {
3462 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3463 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3464 dev->ib_dev.uverbs_cmd_mask |=
3465 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3466 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3469 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3470 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3471 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3474 if (MLX5_CAP_GEN(mdev, xrc)) {
3475 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3476 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3477 dev->ib_dev.uverbs_cmd_mask |=
3478 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3479 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3482 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3483 IB_LINK_LAYER_ETHERNET) {
3484 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3485 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3486 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3487 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3488 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3489 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3490 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3491 dev->ib_dev.uverbs_ex_cmd_mask |=
3492 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3493 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3494 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3495 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3496 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3497 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3498 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3500 err = init_node_data(dev);
3504 mutex_init(&dev->flow_db.lock);
3505 mutex_init(&dev->cap_mask_mutex);
3506 INIT_LIST_HEAD(&dev->qp_list);
3507 spin_lock_init(&dev->reset_flow_resource_lock);
3509 if (ll == IB_LINK_LAYER_ETHERNET) {
3510 err = mlx5_enable_eth(dev);
3515 err = create_dev_resources(&dev->devr);
3517 goto err_disable_eth;
3519 err = mlx5_ib_odp_init_one(dev);
3523 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3524 err = mlx5_ib_alloc_q_counters(dev);
3529 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3530 if (!dev->mdev->priv.uar)
3533 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3537 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3541 err = ib_register_device(&dev->ib_dev, NULL);
3545 err = create_umr_res(dev);
3549 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3550 err = device_create_file(&dev->ib_dev.dev,
3551 mlx5_class_attributes[i]);
3556 dev->ib_active = true;
3561 destroy_umrc_res(dev);
3564 ib_unregister_device(&dev->ib_dev);
3567 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3570 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3573 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3576 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3577 mlx5_ib_dealloc_q_counters(dev);
3580 mlx5_ib_odp_remove_one(dev);
3583 destroy_dev_resources(&dev->devr);
3586 if (ll == IB_LINK_LAYER_ETHERNET) {
3587 mlx5_disable_eth(dev);
3588 mlx5_remove_netdev_notifier(dev);
3595 ib_dealloc_device((struct ib_device *)dev);
3600 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3602 struct mlx5_ib_dev *dev = context;
3603 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3605 mlx5_remove_netdev_notifier(dev);
3606 ib_unregister_device(&dev->ib_dev);
3607 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3608 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3609 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
3610 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3611 mlx5_ib_dealloc_q_counters(dev);
3612 destroy_umrc_res(dev);
3613 mlx5_ib_odp_remove_one(dev);
3614 destroy_dev_resources(&dev->devr);
3615 if (ll == IB_LINK_LAYER_ETHERNET)
3616 mlx5_disable_eth(dev);
3618 ib_dealloc_device(&dev->ib_dev);
3621 static struct mlx5_interface mlx5_ib_interface = {
3623 .remove = mlx5_ib_remove,
3624 .event = mlx5_ib_event,
3625 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3626 .pfault = mlx5_ib_pfault,
3628 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3631 static int __init mlx5_ib_init(void)
3637 err = mlx5_register_interface(&mlx5_ib_interface);
3642 static void __exit mlx5_ib_cleanup(void)
3644 mlx5_unregister_interface(&mlx5_ib_interface);
3647 module_init(mlx5_ib_init);
3648 module_exit(mlx5_ib_cleanup);