drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/mlx5/eswitch.h>
  56 #include <linux/list.h>
  57 #include <rdma/ib_smi.h>
  58 #include <rdma/ib_umem.h>
  59 #include <linux/in.h>
  60 #include <linux/etherdevice.h>
  61 #include "mlx5_ib.h"
  62 #include "ib_rep.h"
  63 #include "cmd.h"
  64 #include "srq.h"
  65 #include <linux/mlx5/fs_helpers.h>
  66 #include <linux/mlx5/accel.h>
  67 #include <rdma/uverbs_std_types.h>
  68 #include <rdma/mlx5_user_ioctl_verbs.h>
  69 #include <rdma/mlx5_user_ioctl_cmds.h>
  70
  71 #define UVERBS_MODULE_NAME mlx5_ib
  72 #include <rdma/uverbs_named_ioctl.h>
  73
  74 #define DRIVER_NAME "mlx5_ib"
  75 #define DRIVER_VERSION "5.0-0"
  76
  77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  78 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  79 MODULE_LICENSE("Dual BSD/GPL");
  80
  81 static char mlx5_version[] =
  82         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  83         DRIVER_VERSION "\n";
  84
  85 struct mlx5_ib_event_work {
  86         struct work_struct      work;
  87         union {
  88                 struct mlx5_ib_dev            *dev;
  89                 struct mlx5_ib_multiport_info *mpi;
  90         };
  91         bool                    is_slave;
  92         unsigned int            event;
  93         void                    *param;
  94 };
  95
  96 enum {
  97         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  98 };
  99
 100 static struct workqueue_struct *mlx5_ib_event_wq;
 101 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
 102 static LIST_HEAD(mlx5_ib_dev_list);
 103 /*
 104  * This mutex should be held when accessing either of the above lists
 105  */
 106 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 107
 108 /* We can't use an array for xlt_emergency_page because dma_map_single
 109  * doesn't work on kernel modules memory
 110  */
 111 static unsigned long xlt_emergency_page;
 112 static struct mutex xlt_emergency_page_mutex;
 113
 114 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 115 {
 116         struct mlx5_ib_dev *dev;
 117
 118         mutex_lock(&mlx5_ib_multiport_mutex);
 119         dev = mpi->ibdev;
 120         mutex_unlock(&mlx5_ib_multiport_mutex);
 121         return dev;
 122 }
 123
 124 static enum rdma_link_layer
 125 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 126 {
 127         switch (port_type_cap) {
 128         case MLX5_CAP_PORT_TYPE_IB:
 129                 return IB_LINK_LAYER_INFINIBAND;
 130         case MLX5_CAP_PORT_TYPE_ETH:
 131                 return IB_LINK_LAYER_ETHERNET;
 132         default:
 133                 return IB_LINK_LAYER_UNSPECIFIED;
 134         }
 135 }
 136
 137 static enum rdma_link_layer
 138 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 139 {
 140         struct mlx5_ib_dev *dev = to_mdev(device);
 141         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 142
 143         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 144 }
 145
 146 static int get_port_state(struct ib_device *ibdev,
 147                           u8 port_num,
 148                           enum ib_port_state *state)
 149 {
 150         struct ib_port_attr attr;
 151         int ret;
 152
 153         memset(&attr, 0, sizeof(attr));
 154         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 155         if (!ret)
 156                 *state = attr.state;
 157         return ret;
 158 }
 159
 160 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 161                                            struct net_device *ndev,
 162                                            u8 *port_num)
 163 {
 164         struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
 165         struct net_device *rep_ndev;
 166         struct mlx5_ib_port *port;
 167         int i;
 168
 169         for (i = 0; i < dev->num_ports; i++) {
 170                 port  = &dev->port[i];
 171                 if (!port->rep)
 172                         continue;
 173
 174                 read_lock(&port->roce.netdev_lock);
 175                 rep_ndev = mlx5_ib_get_rep_netdev(esw,
 176                                                   port->rep->vport);
 177                 if (rep_ndev == ndev) {
 178                         read_unlock(&port->roce.netdev_lock);
 179                         *port_num = i + 1;
 180                         return &port->roce;
 181                 }
 182                 read_unlock(&port->roce.netdev_lock);
 183         }
 184
 185         return NULL;
 186 }
 187
 188 static int mlx5_netdev_event(struct notifier_block *this,
 189                              unsigned long event, void *ptr)
 190 {
 191         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 192         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 193         u8 port_num = roce->native_port_num;
 194         struct mlx5_core_dev *mdev;
 195         struct mlx5_ib_dev *ibdev;
 196
 197         ibdev = roce->dev;
 198         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 199         if (!mdev)
 200                 return NOTIFY_DONE;
 201
 202         switch (event) {
 203         case NETDEV_REGISTER:
 204                 /* Should already be registered during the load */
 205                 if (ibdev->is_rep)
 206                         break;
 207                 write_lock(&roce->netdev_lock);
 208                 if (ndev->dev.parent == mdev->device)
 209                         roce->netdev = ndev;
 210                 write_unlock(&roce->netdev_lock);
 211                 break;
 212
 213         case NETDEV_UNREGISTER:
 214                 /* In case of reps, ib device goes away before the netdevs */
 215                 write_lock(&roce->netdev_lock);
 216                 if (roce->netdev == ndev)
 217                         roce->netdev = NULL;
 218                 write_unlock(&roce->netdev_lock);
 219                 break;
 220
 221         case NETDEV_CHANGE:
 222         case NETDEV_UP:
 223         case NETDEV_DOWN: {
 224                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 225                 struct net_device *upper = NULL;
 226
 227                 if (lag_ndev) {
 228                         upper = netdev_master_upper_dev_get(lag_ndev);
 229                         dev_put(lag_ndev);
 230                 }
 231
 232                 if (ibdev->is_rep)
 233                         roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
 234                 if (!roce)
 235                         return NOTIFY_DONE;
 236                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 237                     && ibdev->ib_active) {
 238                         struct ib_event ibev = { };
 239                         enum ib_port_state port_state;
 240
 241                         if (get_port_state(&ibdev->ib_dev, port_num,
 242                                            &port_state))
 243                                 goto done;
 244
 245                         if (roce->last_port_state == port_state)
 246                                 goto done;
 247
 248                         roce->last_port_state = port_state;
 249                         ibev.device = &ibdev->ib_dev;
 250                         if (port_state == IB_PORT_DOWN)
 251                                 ibev.event = IB_EVENT_PORT_ERR;
 252                         else if (port_state == IB_PORT_ACTIVE)
 253                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 254                         else
 255                                 goto done;
 256
 257                         ibev.element.port_num = port_num;
 258                         ib_dispatch_event(&ibev);
 259                 }
 260                 break;
 261         }
 262
 263         default:
 264                 break;
 265         }
 266 done:
 267         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 268         return NOTIFY_DONE;
 269 }
 270
 271 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 272                                              u8 port_num)
 273 {
 274         struct mlx5_ib_dev *ibdev = to_mdev(device);
 275         struct net_device *ndev;
 276         struct mlx5_core_dev *mdev;
 277
 278         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 279         if (!mdev)
 280                 return NULL;
 281
 282         ndev = mlx5_lag_get_roce_netdev(mdev);
 283         if (ndev)
 284                 goto out;
 285
 286         /* Ensure ndev does not disappear before we invoke dev_hold()
 287          */
 288         read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
 289         ndev = ibdev->port[port_num - 1].roce.netdev;
 290         if (ndev)
 291                 dev_hold(ndev);
 292         read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
 293
 294 out:
 295         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 296         return ndev;
 297 }
 298
 299 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 300                                                    u8 ib_port_num,
 301                                                    u8 *native_port_num)
 302 {
 303         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 304                                                           ib_port_num);
 305         struct mlx5_core_dev *mdev = NULL;
 306         struct mlx5_ib_multiport_info *mpi;
 307         struct mlx5_ib_port *port;
 308
 309         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 310             ll != IB_LINK_LAYER_ETHERNET) {
 311                 if (native_port_num)
 312                         *native_port_num = ib_port_num;
 313                 return ibdev->mdev;
 314         }
 315
 316         if (native_port_num)
 317                 *native_port_num = 1;
 318
 319         port = &ibdev->port[ib_port_num - 1];
 320         if (!port)
 321                 return NULL;
 322
 323         spin_lock(&port->mp.mpi_lock);
 324         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 325         if (mpi && !mpi->unaffiliate) {
 326                 mdev = mpi->mdev;
 327                 /* If it's the master no need to refcount, it'll exist
 328                  * as long as the ib_dev exists.
 329                  */
 330                 if (!mpi->is_master)
 331                         mpi->mdev_refcnt++;
 332         }
 333         spin_unlock(&port->mp.mpi_lock);
 334
 335         return mdev;
 336 }
 337
 338 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 339 {
 340         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 341                                                           port_num);
 342         struct mlx5_ib_multiport_info *mpi;
 343         struct mlx5_ib_port *port;
 344
 345         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 346                 return;
 347
 348         port = &ibdev->port[port_num - 1];
 349
 350         spin_lock(&port->mp.mpi_lock);
 351         mpi = ibdev->port[port_num - 1].mp.mpi;
 352         if (mpi->is_master)
 353                 goto out;
 354
 355         mpi->mdev_refcnt--;
 356         if (mpi->unaffiliate)
 357                 complete(&mpi->unref_comp);
 358 out:
 359         spin_unlock(&port->mp.mpi_lock);
 360 }
 361
 362 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 363                                            u8 *active_width)
 364 {
 365         switch (eth_proto_oper) {
 366         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 367         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 368         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 369         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 370                 *active_width = IB_WIDTH_1X;
 371                 *active_speed = IB_SPEED_SDR;
 372                 break;
 373         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 374         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 375         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 376         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 377         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 378         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 379         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 380                 *active_width = IB_WIDTH_1X;
 381                 *active_speed = IB_SPEED_QDR;
 382                 break;
 383         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 384         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 385         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 386                 *active_width = IB_WIDTH_1X;
 387                 *active_speed = IB_SPEED_EDR;
 388                 break;
 389         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 390         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 391         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 392         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 393                 *active_width = IB_WIDTH_4X;
 394                 *active_speed = IB_SPEED_QDR;
 395                 break;
 396         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 397         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 398         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 399                 *active_width = IB_WIDTH_1X;
 400                 *active_speed = IB_SPEED_HDR;
 401                 break;
 402         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 403                 *active_width = IB_WIDTH_4X;
 404                 *active_speed = IB_SPEED_FDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 407         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 408         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 409         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 410                 *active_width = IB_WIDTH_4X;
 411                 *active_speed = IB_SPEED_EDR;
 412                 break;
 413         default:
 414                 return -EINVAL;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 421                                         u8 *active_width)
 422 {
 423         switch (eth_proto_oper) {
 424         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 425         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 426                 *active_width = IB_WIDTH_1X;
 427                 *active_speed = IB_SPEED_SDR;
 428                 break;
 429         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 430                 *active_width = IB_WIDTH_1X;
 431                 *active_speed = IB_SPEED_DDR;
 432                 break;
 433         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 434                 *active_width = IB_WIDTH_1X;
 435                 *active_speed = IB_SPEED_QDR;
 436                 break;
 437         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 438                 *active_width = IB_WIDTH_4X;
 439                 *active_speed = IB_SPEED_QDR;
 440                 break;
 441         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 442                 *active_width = IB_WIDTH_1X;
 443                 *active_speed = IB_SPEED_EDR;
 444                 break;
 445         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 446                 *active_width = IB_WIDTH_2X;
 447                 *active_speed = IB_SPEED_EDR;
 448                 break;
 449         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 450                 *active_width = IB_WIDTH_1X;
 451                 *active_speed = IB_SPEED_HDR;
 452                 break;
 453         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 454                 *active_width = IB_WIDTH_4X;
 455                 *active_speed = IB_SPEED_EDR;
 456                 break;
 457         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 458                 *active_width = IB_WIDTH_2X;
 459                 *active_speed = IB_SPEED_HDR;
 460                 break;
 461         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 462                 *active_width = IB_WIDTH_4X;
 463                 *active_speed = IB_SPEED_HDR;
 464                 break;
 465         default:
 466                 return -EINVAL;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 473                                     u8 *active_width, bool ext)
 474 {
 475         return ext ?
 476                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 477                                              active_width) :
 478                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 479                                                 active_width);
 480 }
 481
 482 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 483                                 struct ib_port_attr *props)
 484 {
 485         struct mlx5_ib_dev *dev = to_mdev(device);
 486         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 487         struct mlx5_core_dev *mdev;
 488         struct net_device *ndev, *upper;
 489         enum ib_mtu ndev_ib_mtu;
 490         bool put_mdev = true;
 491         u16 qkey_viol_cntr;
 492         u32 eth_prot_oper;
 493         u8 mdev_port_num;
 494         bool ext;
 495         int err;
 496
 497         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 498         if (!mdev) {
 499                 /* This means the port isn't affiliated yet. Get the
 500                  * info for the master port instead.
 501                  */
 502                 put_mdev = false;
 503                 mdev = dev->mdev;
 504                 mdev_port_num = 1;
 505                 port_num = 1;
 506         }
 507
 508         /* Possible bad flows are checked before filling out props so in case
 509          * of an error it will still be zeroed out.
 510          * Use native port in case of reps
 511          */
 512         if (dev->is_rep)
 513                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 514                                            1);
 515         else
 516                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 517                                            mdev_port_num);
 518         if (err)
 519                 goto out;
 520         ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
 521         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 522
 523         props->active_width     = IB_WIDTH_4X;
 524         props->active_speed     = IB_SPEED_QDR;
 525
 526         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 527                                  &props->active_width, ext);
 528
 529         props->port_cap_flags |= IB_PORT_CM_SUP;
 530         props->ip_gids = true;
 531
 532         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 533                                                 roce_address_table_size);
 534         props->max_mtu          = IB_MTU_4096;
 535         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 536         props->pkey_tbl_len     = 1;
 537         props->state            = IB_PORT_DOWN;
 538         props->phys_state       = 3;
 539
 540         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 541         props->qkey_viol_cntr = qkey_viol_cntr;
 542
 543         /* If this is a stub query for an unaffiliated port stop here */
 544         if (!put_mdev)
 545                 goto out;
 546
 547         ndev = mlx5_ib_get_netdev(device, port_num);
 548         if (!ndev)
 549                 goto out;
 550
 551         if (dev->lag_active) {
 552                 rcu_read_lock();
 553                 upper = netdev_master_upper_dev_get_rcu(ndev);
 554                 if (upper) {
 555                         dev_put(ndev);
 556                         ndev = upper;
 557                         dev_hold(ndev);
 558                 }
 559                 rcu_read_unlock();
 560         }
 561
 562         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 563                 props->state      = IB_PORT_ACTIVE;
 564                 props->phys_state = 5;
 565         }
 566
 567         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 568
 569         dev_put(ndev);
 570
 571         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 572 out:
 573         if (put_mdev)
 574                 mlx5_ib_put_native_port_mdev(dev, port_num);
 575         return err;
 576 }
 577
 578 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 579                          unsigned int index, const union ib_gid *gid,
 580                          const struct ib_gid_attr *attr)
 581 {
 582         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 583         u16 vlan_id = 0xffff;
 584         u8 roce_version = 0;
 585         u8 roce_l3_type = 0;
 586         u8 mac[ETH_ALEN];
 587         int ret;
 588
 589         if (gid) {
 590                 gid_type = attr->gid_type;
 591                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 592                 if (ret)
 593                         return ret;
 594         }
 595
 596         switch (gid_type) {
 597         case IB_GID_TYPE_IB:
 598                 roce_version = MLX5_ROCE_VERSION_1;
 599                 break;
 600         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 601                 roce_version = MLX5_ROCE_VERSION_2;
 602                 if (ipv6_addr_v4mapped((void *)gid))
 603                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 604                 else
 605                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 606                 break;
 607
 608         default:
 609                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 610         }
 611
 612         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 613                                       roce_l3_type, gid->raw, mac,
 614                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 615                                       port_num);
 616 }
 617
 618 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 619                            __always_unused void **context)
 620 {
 621         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 622                              attr->index, &attr->gid, attr);
 623 }
 624
 625 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 626                            __always_unused void **context)
 627 {
 628         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 629                              attr->index, NULL, NULL);
 630 }
 631
 632 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
 633                                const struct ib_gid_attr *attr)
 634 {
 635         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 636                 return 0;
 637
 638         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 639 }
 640
 641 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 642 {
 643         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 644                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 645         return 0;
 646 }
 647
 648 enum {
 649         MLX5_VPORT_ACCESS_METHOD_MAD,
 650         MLX5_VPORT_ACCESS_METHOD_HCA,
 651         MLX5_VPORT_ACCESS_METHOD_NIC,
 652 };
 653
 654 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 655 {
 656         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 657                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 658
 659         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 660             IB_LINK_LAYER_ETHERNET)
 661                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 662
 663         return MLX5_VPORT_ACCESS_METHOD_HCA;
 664 }
 665
 666 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 667                             u8 atomic_size_qp,
 668                             struct ib_device_attr *props)
 669 {
 670         u8 tmp;
 671         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 672         u8 atomic_req_8B_endianness_mode =
 673                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 674
 675         /* Check if HW supports 8 bytes standard atomic operations and capable
 676          * of host endianness respond
 677          */
 678         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 679         if (((atomic_operations & tmp) == tmp) &&
 680             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 681             (atomic_req_8B_endianness_mode)) {
 682                 props->atomic_cap = IB_ATOMIC_HCA;
 683         } else {
 684                 props->atomic_cap = IB_ATOMIC_NONE;
 685         }
 686 }
 687
 688 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 689                                struct ib_device_attr *props)
 690 {
 691         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 692
 693         get_atomic_caps(dev, atomic_size_qp, props);
 694 }
 695
 696 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 697                                struct ib_device_attr *props)
 698 {
 699         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 700
 701         get_atomic_caps(dev, atomic_size_qp, props);
 702 }
 703
 704 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 705 {
 706         struct ib_device_attr props = {};
 707
 708         get_atomic_caps_dc(dev, &props);
 709         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 710 }
 711 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 712                                         __be64 *sys_image_guid)
 713 {
 714         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 715         struct mlx5_core_dev *mdev = dev->mdev;
 716         u64 tmp;
 717         int err;
 718
 719         switch (mlx5_get_vport_access_method(ibdev)) {
 720         case MLX5_VPORT_ACCESS_METHOD_MAD:
 721                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 722                                                             sys_image_guid);
 723
 724         case MLX5_VPORT_ACCESS_METHOD_HCA:
 725                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 726                 break;
 727
 728         case MLX5_VPORT_ACCESS_METHOD_NIC:
 729                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 730                 break;
 731
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         if (!err)
 737                 *sys_image_guid = cpu_to_be64(tmp);
 738
 739         return err;
 740
 741 }
 742
 743 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 744                                 u16 *max_pkeys)
 745 {
 746         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 747         struct mlx5_core_dev *mdev = dev->mdev;
 748
 749         switch (mlx5_get_vport_access_method(ibdev)) {
 750         case MLX5_VPORT_ACCESS_METHOD_MAD:
 751                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 752
 753         case MLX5_VPORT_ACCESS_METHOD_HCA:
 754         case MLX5_VPORT_ACCESS_METHOD_NIC:
 755                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 756                                                 pkey_table_size));
 757                 return 0;
 758
 759         default:
 760                 return -EINVAL;
 761         }
 762 }
 763
 764 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 765                                 u32 *vendor_id)
 766 {
 767         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 768
 769         switch (mlx5_get_vport_access_method(ibdev)) {
 770         case MLX5_VPORT_ACCESS_METHOD_MAD:
 771                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 772
 773         case MLX5_VPORT_ACCESS_METHOD_HCA:
 774         case MLX5_VPORT_ACCESS_METHOD_NIC:
 775                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 776
 777         default:
 778                 return -EINVAL;
 779         }
 780 }
 781
 782 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 783                                 __be64 *node_guid)
 784 {
 785         u64 tmp;
 786         int err;
 787
 788         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 789         case MLX5_VPORT_ACCESS_METHOD_MAD:
 790                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 791
 792         case MLX5_VPORT_ACCESS_METHOD_HCA:
 793                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 794                 break;
 795
 796         case MLX5_VPORT_ACCESS_METHOD_NIC:
 797                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 798                 break;
 799
 800         default:
 801                 return -EINVAL;
 802         }
 803
 804         if (!err)
 805                 *node_guid = cpu_to_be64(tmp);
 806
 807         return err;
 808 }
 809
 810 struct mlx5_reg_node_desc {
 811         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 812 };
 813
 814 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 815 {
 816         struct mlx5_reg_node_desc in;
 817
 818         if (mlx5_use_mad_ifc(dev))
 819                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 820
 821         memset(&in, 0, sizeof(in));
 822
 823         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 824                                     sizeof(struct mlx5_reg_node_desc),
 825                                     MLX5_REG_NODE_DESC, 0, 0);
 826 }
 827
 828 static int mlx5_ib_query_device(struct ib_device *ibdev,
 829                                 struct ib_device_attr *props,
 830                                 struct ib_udata *uhw)
 831 {
 832         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 833         struct mlx5_core_dev *mdev = dev->mdev;
 834         int err = -ENOMEM;
 835         int max_sq_desc;
 836         int max_rq_sg;
 837         int max_sq_sg;
 838         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 839         bool raw_support = !mlx5_core_mp_enabled(mdev);
 840         struct mlx5_ib_query_device_resp resp = {};
 841         size_t resp_len;
 842         u64 max_tso;
 843
 844         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 845         if (uhw->outlen && uhw->outlen < resp_len)
 846                 return -EINVAL;
 847         else
 848                 resp.response_length = resp_len;
 849
 850         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 851                 return -EINVAL;
 852
 853         memset(props, 0, sizeof(*props));
 854         err = mlx5_query_system_image_guid(ibdev,
 855                                            &props->sys_image_guid);
 856         if (err)
 857                 return err;
 858
 859         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 860         if (err)
 861                 return err;
 862
 863         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 864         if (err)
 865                 return err;
 866
 867         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 868                 (fw_rev_min(dev->mdev) << 16) |
 869                 fw_rev_sub(dev->mdev);
 870         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 871                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 872                 IB_DEVICE_SYS_IMAGE_GUID                |
 873                 IB_DEVICE_RC_RNR_NAK_GEN;
 874
 875         if (MLX5_CAP_GEN(mdev, pkv))
 876                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 877         if (MLX5_CAP_GEN(mdev, qkv))
 878                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 879         if (MLX5_CAP_GEN(mdev, apm))
 880                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 881         if (MLX5_CAP_GEN(mdev, xrc))
 882                 props->device_cap_flags |= IB_DEVICE_XRC;
 883         if (MLX5_CAP_GEN(mdev, imaicl)) {
 884                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 885                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 886                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 887                 /* We support 'Gappy' memory registration too */
 888                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 889         }
 890         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 891         if (MLX5_CAP_GEN(mdev, sho)) {
 892                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 893                 /* At this stage no support for signature handover */
 894                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 895                                       IB_PROT_T10DIF_TYPE_2 |
 896                                       IB_PROT_T10DIF_TYPE_3;
 897                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 898                                        IB_GUARD_T10DIF_CSUM;
 899         }
 900         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 901                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 902
 903         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 904                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 905                         /* Legacy bit to support old userspace libraries */
 906                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 907                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 908                 }
 909
 910                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 911                         props->raw_packet_caps |=
 912                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 913
 914                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 915                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 916                         if (max_tso) {
 917                                 resp.tso_caps.max_tso = 1 << max_tso;
 918                                 resp.tso_caps.supported_qpts |=
 919                                         1 << IB_QPT_RAW_PACKET;
 920                                 resp.response_length += sizeof(resp.tso_caps);
 921                         }
 922                 }
 923
 924                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 925                         resp.rss_caps.rx_hash_function =
 926                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 927                         resp.rss_caps.rx_hash_fields_mask =
 928                                                 MLX5_RX_HASH_SRC_IPV4 |
 929                                                 MLX5_RX_HASH_DST_IPV4 |
 930                                                 MLX5_RX_HASH_SRC_IPV6 |
 931                                                 MLX5_RX_HASH_DST_IPV6 |
 932                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 933                                                 MLX5_RX_HASH_DST_PORT_TCP |
 934                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 935                                                 MLX5_RX_HASH_DST_PORT_UDP |
 936                                                 MLX5_RX_HASH_INNER;
 937                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 938                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 939                                 resp.rss_caps.rx_hash_fields_mask |=
 940                                         MLX5_RX_HASH_IPSEC_SPI;
 941                         resp.response_length += sizeof(resp.rss_caps);
 942                 }
 943         } else {
 944                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 945                         resp.response_length += sizeof(resp.tso_caps);
 946                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 947                         resp.response_length += sizeof(resp.rss_caps);
 948         }
 949
 950         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 951                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 952                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 953         }
 954
 955         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 956             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 957             raw_support)
 958                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 959
 960         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 961             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 962                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 963
 964         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 965             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 966             raw_support) {
 967                 /* Legacy bit to support old userspace libraries */
 968                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 969                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 970         }
 971
 972         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 973                 props->max_dm_size =
 974                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 975         }
 976
 977         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 978                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 979
 980         if (MLX5_CAP_GEN(mdev, end_pad))
 981                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 982
 983         props->vendor_part_id      = mdev->pdev->device;
 984         props->hw_ver              = mdev->pdev->revision;
 985
 986         props->max_mr_size         = ~0ull;
 987         props->page_size_cap       = ~(min_page_size - 1);
 988         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 989         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 990         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 991                      sizeof(struct mlx5_wqe_data_seg);
 992         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 993         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 994                      sizeof(struct mlx5_wqe_raddr_seg)) /
 995                 sizeof(struct mlx5_wqe_data_seg);
 996         props->max_send_sge = max_sq_sg;
 997         props->max_recv_sge = max_rq_sg;
 998         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 999         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
1000         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
1001         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
1008         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
1009         props->max_srq_sge         = max_rq_sg - 1;
1010         props->max_fast_reg_page_list_len =
1011                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
1012         get_atomic_caps_qp(dev, props);
1013         props->masked_atomic_cap   = IB_ATOMIC_NONE;
1014         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1015         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1016         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1017                                            props->max_mcast_grp;
1018         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
1019         props->max_ah = INT_MAX;
1020         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1021         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1022
1023         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1024                 if (MLX5_CAP_GEN(mdev, pg))
1025                         props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1026                 props->odp_caps = dev->odp_caps;
1027         }
1028
1029         if (MLX5_CAP_GEN(mdev, cd))
1030                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1031
1032         if (!mlx5_core_is_pf(mdev))
1033                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1034
1035         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1036             IB_LINK_LAYER_ETHERNET && raw_support) {
1037                 props->rss_caps.max_rwq_indirection_tables =
1038                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1039                 props->rss_caps.max_rwq_indirection_table_size =
1040                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1041                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1042                 props->max_wq_type_rq =
1043                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1044         }
1045
1046         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1047                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1048                 props->tm_caps.max_num_tags =
1049                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1050                 props->tm_caps.flags = IB_TM_CAP_RC;
1051                 props->tm_caps.max_ops =
1052                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1053                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1054         }
1055
1056         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1057                 props->cq_caps.max_cq_moderation_count =
1058                                                 MLX5_MAX_CQ_COUNT;
1059                 props->cq_caps.max_cq_moderation_period =
1060                                                 MLX5_MAX_CQ_PERIOD;
1061         }
1062
1063         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
1064                 resp.response_length += sizeof(resp.cqe_comp_caps);
1065
1066                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1067                         resp.cqe_comp_caps.max_num =
1068                                 MLX5_CAP_GEN(dev->mdev,
1069                                              cqe_compression_max_num);
1070
1071                         resp.cqe_comp_caps.supported_format =
1072                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1073                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1074
1075                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1076                                 resp.cqe_comp_caps.supported_format |=
1077                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1078                 }
1079         }
1080
1081         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1082             raw_support) {
1083                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1084                     MLX5_CAP_GEN(mdev, qos)) {
1085                         resp.packet_pacing_caps.qp_rate_limit_max =
1086                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1087                         resp.packet_pacing_caps.qp_rate_limit_min =
1088                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1089                         resp.packet_pacing_caps.supported_qpts |=
1090                                 1 << IB_QPT_RAW_PACKET;
1091                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1092                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1093                                 resp.packet_pacing_caps.cap_flags |=
1094                                         MLX5_IB_PP_SUPPORT_BURST;
1095                 }
1096                 resp.response_length += sizeof(resp.packet_pacing_caps);
1097         }
1098
1099         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1100                         uhw->outlen)) {
1101                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1102                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1103                                 MLX5_IB_ALLOW_MPW;
1104
1105                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1106                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1107                                 MLX5_IB_SUPPORT_EMPW;
1108
1109                 resp.response_length +=
1110                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1111         }
1112
1113         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1114                 resp.response_length += sizeof(resp.flags);
1115
1116                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1117                         resp.flags |=
1118                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1119
1120                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1121                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1122                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1123                         resp.flags |=
1124                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1125
1126                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1127         }
1128
1129         if (field_avail(typeof(resp), sw_parsing_caps,
1130                         uhw->outlen)) {
1131                 resp.response_length += sizeof(resp.sw_parsing_caps);
1132                 if (MLX5_CAP_ETH(mdev, swp)) {
1133                         resp.sw_parsing_caps.sw_parsing_offloads |=
1134                                 MLX5_IB_SW_PARSING;
1135
1136                         if (MLX5_CAP_ETH(mdev, swp_csum))
1137                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1138                                         MLX5_IB_SW_PARSING_CSUM;
1139
1140                         if (MLX5_CAP_ETH(mdev, swp_lso))
1141                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1142                                         MLX5_IB_SW_PARSING_LSO;
1143
1144                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1145                                 resp.sw_parsing_caps.supported_qpts =
1146                                         BIT(IB_QPT_RAW_PACKET);
1147                 }
1148         }
1149
1150         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1151             raw_support) {
1152                 resp.response_length += sizeof(resp.striding_rq_caps);
1153                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1154                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1155                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1156                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1157                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1158                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1159                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1160                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1161                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1162                         resp.striding_rq_caps.supported_qpts =
1163                                 BIT(IB_QPT_RAW_PACKET);
1164                 }
1165         }
1166
1167         if (field_avail(typeof(resp), tunnel_offloads_caps,
1168                         uhw->outlen)) {
1169                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1170                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1171                         resp.tunnel_offloads_caps |=
1172                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1173                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1174                         resp.tunnel_offloads_caps |=
1175                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1176                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1177                         resp.tunnel_offloads_caps |=
1178                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1179                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1180                     MLX5_FLEX_PROTO_CW_MPLS_GRE)
1181                         resp.tunnel_offloads_caps |=
1182                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1183                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1184                     MLX5_FLEX_PROTO_CW_MPLS_UDP)
1185                         resp.tunnel_offloads_caps |=
1186                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1187         }
1188
1189         if (uhw->outlen) {
1190                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1191
1192                 if (err)
1193                         return err;
1194         }
1195
1196         return 0;
1197 }
1198
1199 enum mlx5_ib_width {
1200         MLX5_IB_WIDTH_1X        = 1 << 0,
1201         MLX5_IB_WIDTH_2X        = 1 << 1,
1202         MLX5_IB_WIDTH_4X        = 1 << 2,
1203         MLX5_IB_WIDTH_8X        = 1 << 3,
1204         MLX5_IB_WIDTH_12X       = 1 << 4
1205 };
1206
1207 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1208                                   u8 *ib_width)
1209 {
1210         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1211
1212         if (active_width & MLX5_IB_WIDTH_1X)
1213                 *ib_width = IB_WIDTH_1X;
1214         else if (active_width & MLX5_IB_WIDTH_2X)
1215                 *ib_width = IB_WIDTH_2X;
1216         else if (active_width & MLX5_IB_WIDTH_4X)
1217                 *ib_width = IB_WIDTH_4X;
1218         else if (active_width & MLX5_IB_WIDTH_8X)
1219                 *ib_width = IB_WIDTH_8X;
1220         else if (active_width & MLX5_IB_WIDTH_12X)
1221                 *ib_width = IB_WIDTH_12X;
1222         else {
1223                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1224                             (int)active_width);
1225                 *ib_width = IB_WIDTH_4X;
1226         }
1227
1228         return;
1229 }
1230
1231 static int mlx5_mtu_to_ib_mtu(int mtu)
1232 {
1233         switch (mtu) {
1234         case 256: return 1;
1235         case 512: return 2;
1236         case 1024: return 3;
1237         case 2048: return 4;
1238         case 4096: return 5;
1239         default:
1240                 pr_warn("invalid mtu\n");
1241                 return -1;
1242         }
1243 }
1244
1245 enum ib_max_vl_num {
1246         __IB_MAX_VL_0           = 1,
1247         __IB_MAX_VL_0_1         = 2,
1248         __IB_MAX_VL_0_3         = 3,
1249         __IB_MAX_VL_0_7         = 4,
1250         __IB_MAX_VL_0_14        = 5,
1251 };
1252
1253 enum mlx5_vl_hw_cap {
1254         MLX5_VL_HW_0    = 1,
1255         MLX5_VL_HW_0_1  = 2,
1256         MLX5_VL_HW_0_2  = 3,
1257         MLX5_VL_HW_0_3  = 4,
1258         MLX5_VL_HW_0_4  = 5,
1259         MLX5_VL_HW_0_5  = 6,
1260         MLX5_VL_HW_0_6  = 7,
1261         MLX5_VL_HW_0_7  = 8,
1262         MLX5_VL_HW_0_14 = 15
1263 };
1264
1265 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1266                                 u8 *max_vl_num)
1267 {
1268         switch (vl_hw_cap) {
1269         case MLX5_VL_HW_0:
1270                 *max_vl_num = __IB_MAX_VL_0;
1271                 break;
1272         case MLX5_VL_HW_0_1:
1273                 *max_vl_num = __IB_MAX_VL_0_1;
1274                 break;
1275         case MLX5_VL_HW_0_3:
1276                 *max_vl_num = __IB_MAX_VL_0_3;
1277                 break;
1278         case MLX5_VL_HW_0_7:
1279                 *max_vl_num = __IB_MAX_VL_0_7;
1280                 break;
1281         case MLX5_VL_HW_0_14:
1282                 *max_vl_num = __IB_MAX_VL_0_14;
1283                 break;
1284
1285         default:
1286                 return -EINVAL;
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1293                                struct ib_port_attr *props)
1294 {
1295         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1296         struct mlx5_core_dev *mdev = dev->mdev;
1297         struct mlx5_hca_vport_context *rep;
1298         u16 max_mtu;
1299         u16 oper_mtu;
1300         int err;
1301         u8 ib_link_width_oper;
1302         u8 vl_hw_cap;
1303
1304         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1305         if (!rep) {
1306                 err = -ENOMEM;
1307                 goto out;
1308         }
1309
1310         /* props being zeroed by the caller, avoid zeroing it here */
1311
1312         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1313         if (err)
1314                 goto out;
1315
1316         props->lid              = rep->lid;
1317         props->lmc              = rep->lmc;
1318         props->sm_lid           = rep->sm_lid;
1319         props->sm_sl            = rep->sm_sl;
1320         props->state            = rep->vport_state;
1321         props->phys_state       = rep->port_physical_state;
1322         props->port_cap_flags   = rep->cap_mask1;
1323         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1324         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1325         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1326         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1327         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1328         props->subnet_timeout   = rep->subnet_timeout;
1329         props->init_type_reply  = rep->init_type_reply;
1330
1331         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1332                 props->port_cap_flags2 = rep->cap_mask2;
1333
1334         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1335         if (err)
1336                 goto out;
1337
1338         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1339
1340         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1341         if (err)
1342                 goto out;
1343
1344         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1345
1346         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1347
1348         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1349
1350         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1351
1352         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1353         if (err)
1354                 goto out;
1355
1356         err = translate_max_vl_num(ibdev, vl_hw_cap,
1357                                    &props->max_vl_num);
1358 out:
1359         kfree(rep);
1360         return err;
1361 }
1362
1363 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1364                        struct ib_port_attr *props)
1365 {
1366         unsigned int count;
1367         int ret;
1368
1369         switch (mlx5_get_vport_access_method(ibdev)) {
1370         case MLX5_VPORT_ACCESS_METHOD_MAD:
1371                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1372                 break;
1373
1374         case MLX5_VPORT_ACCESS_METHOD_HCA:
1375                 ret = mlx5_query_hca_port(ibdev, port, props);
1376                 break;
1377
1378         case MLX5_VPORT_ACCESS_METHOD_NIC:
1379                 ret = mlx5_query_port_roce(ibdev, port, props);
1380                 break;
1381
1382         default:
1383                 ret = -EINVAL;
1384         }
1385
1386         if (!ret && props) {
1387                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1388                 struct mlx5_core_dev *mdev;
1389                 bool put_mdev = true;
1390
1391                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1392                 if (!mdev) {
1393                         /* If the port isn't affiliated yet query the master.
1394                          * The master and slave will have the same values.
1395                          */
1396                         mdev = dev->mdev;
1397                         port = 1;
1398                         put_mdev = false;
1399                 }
1400                 count = mlx5_core_reserved_gids_count(mdev);
1401                 if (put_mdev)
1402                         mlx5_ib_put_native_port_mdev(dev, port);
1403                 props->gid_tbl_len -= count;
1404         }
1405         return ret;
1406 }
1407
1408 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1409                                   struct ib_port_attr *props)
1410 {
1411         int ret;
1412
1413         /* Only link layer == ethernet is valid for representors
1414          * and we always use port 1
1415          */
1416         ret = mlx5_query_port_roce(ibdev, port, props);
1417         if (ret || !props)
1418                 return ret;
1419
1420         /* We don't support GIDS */
1421         props->gid_tbl_len = 0;
1422
1423         return ret;
1424 }
1425
1426 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1427                              union ib_gid *gid)
1428 {
1429         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1430         struct mlx5_core_dev *mdev = dev->mdev;
1431
1432         switch (mlx5_get_vport_access_method(ibdev)) {
1433         case MLX5_VPORT_ACCESS_METHOD_MAD:
1434                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1435
1436         case MLX5_VPORT_ACCESS_METHOD_HCA:
1437                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1438
1439         default:
1440                 return -EINVAL;
1441         }
1442
1443 }
1444
1445 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1446                                    u16 index, u16 *pkey)
1447 {
1448         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1449         struct mlx5_core_dev *mdev;
1450         bool put_mdev = true;
1451         u8 mdev_port_num;
1452         int err;
1453
1454         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1455         if (!mdev) {
1456                 /* The port isn't affiliated yet, get the PKey from the master
1457                  * port. For RoCE the PKey tables will be the same.
1458                  */
1459                 put_mdev = false;
1460                 mdev = dev->mdev;
1461                 mdev_port_num = 1;
1462         }
1463
1464         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1465                                         index, pkey);
1466         if (put_mdev)
1467                 mlx5_ib_put_native_port_mdev(dev, port);
1468
1469         return err;
1470 }
1471
1472 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1473                               u16 *pkey)
1474 {
1475         switch (mlx5_get_vport_access_method(ibdev)) {
1476         case MLX5_VPORT_ACCESS_METHOD_MAD:
1477                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1478
1479         case MLX5_VPORT_ACCESS_METHOD_HCA:
1480         case MLX5_VPORT_ACCESS_METHOD_NIC:
1481                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1482         default:
1483                 return -EINVAL;
1484         }
1485 }
1486
1487 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1488                                  struct ib_device_modify *props)
1489 {
1490         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1491         struct mlx5_reg_node_desc in;
1492         struct mlx5_reg_node_desc out;
1493         int err;
1494
1495         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1496                 return -EOPNOTSUPP;
1497
1498         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1499                 return 0;
1500
1501         /*
1502          * If possible, pass node desc to FW, so it can generate
1503          * a 144 trap.  If cmd fails, just ignore.
1504          */
1505         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1506         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1507                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1508         if (err)
1509                 return err;
1510
1511         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1512
1513         return err;
1514 }
1515
1516 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1517                                 u32 value)
1518 {
1519         struct mlx5_hca_vport_context ctx = {};
1520         struct mlx5_core_dev *mdev;
1521         u8 mdev_port_num;
1522         int err;
1523
1524         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1525         if (!mdev)
1526                 return -ENODEV;
1527
1528         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1529         if (err)
1530                 goto out;
1531
1532         if (~ctx.cap_mask1_perm & mask) {
1533                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1534                              mask, ctx.cap_mask1_perm);
1535                 err = -EINVAL;
1536                 goto out;
1537         }
1538
1539         ctx.cap_mask1 = value;
1540         ctx.cap_mask1_perm = mask;
1541         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1542                                                  0, &ctx);
1543
1544 out:
1545         mlx5_ib_put_native_port_mdev(dev, port_num);
1546
1547         return err;
1548 }
1549
1550 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1551                                struct ib_port_modify *props)
1552 {
1553         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1554         struct ib_port_attr attr;
1555         u32 tmp;
1556         int err;
1557         u32 change_mask;
1558         u32 value;
1559         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1560                       IB_LINK_LAYER_INFINIBAND);
1561
1562         /* CM layer calls ib_modify_port() regardless of the link layer. For
1563          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1564          */
1565         if (!is_ib)
1566                 return 0;
1567
1568         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1569                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1570                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1571                 return set_port_caps_atomic(dev, port, change_mask, value);
1572         }
1573
1574         mutex_lock(&dev->cap_mask_mutex);
1575
1576         err = ib_query_port(ibdev, port, &attr);
1577         if (err)
1578                 goto out;
1579
1580         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1581                 ~props->clr_port_cap_mask;
1582
1583         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1584
1585 out:
1586         mutex_unlock(&dev->cap_mask_mutex);
1587         return err;
1588 }
1589
1590 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1591 {
1592         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1593                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1594 }
1595
1596 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1597 {
1598         /* Large page with non 4k uar support might limit the dynamic size */
1599         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1600                 return MLX5_MIN_DYN_BFREGS;
1601
1602         return MLX5_MAX_DYN_BFREGS;
1603 }
1604
1605 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1606                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1607                              struct mlx5_bfreg_info *bfregi)
1608 {
1609         int uars_per_sys_page;
1610         int bfregs_per_sys_page;
1611         int ref_bfregs = req->total_num_bfregs;
1612
1613         if (req->total_num_bfregs == 0)
1614                 return -EINVAL;
1615
1616         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1617         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1618
1619         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1620                 return -ENOMEM;
1621
1622         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1623         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1624         /* This holds the required static allocation asked by the user */
1625         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1626         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1627                 return -EINVAL;
1628
1629         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1630         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1631         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1632         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1633
1634         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1635                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1636                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1637                     req->total_num_bfregs, bfregi->total_num_bfregs,
1638                     bfregi->num_sys_pages);
1639
1640         return 0;
1641 }
1642
1643 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1644 {
1645         struct mlx5_bfreg_info *bfregi;
1646         int err;
1647         int i;
1648
1649         bfregi = &context->bfregi;
1650         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1651                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1652                 if (err)
1653                         goto error;
1654
1655                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1656         }
1657
1658         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1659                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1660
1661         return 0;
1662
1663 error:
1664         for (--i; i >= 0; i--)
1665                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1666                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1667
1668         return err;
1669 }
1670
1671 static void deallocate_uars(struct mlx5_ib_dev *dev,
1672                             struct mlx5_ib_ucontext *context)
1673 {
1674         struct mlx5_bfreg_info *bfregi;
1675         int i;
1676
1677         bfregi = &context->bfregi;
1678         for (i = 0; i < bfregi->num_sys_pages; i++)
1679                 if (i < bfregi->num_static_sys_pages ||
1680                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1681                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1682 }
1683
1684 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1685 {
1686         int err = 0;
1687
1688         mutex_lock(&dev->lb.mutex);
1689         if (td)
1690                 dev->lb.user_td++;
1691         if (qp)
1692                 dev->lb.qps++;
1693
1694         if (dev->lb.user_td == 2 ||
1695             dev->lb.qps == 1) {
1696                 if (!dev->lb.enabled) {
1697                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1698                         dev->lb.enabled = true;
1699                 }
1700         }
1701
1702         mutex_unlock(&dev->lb.mutex);
1703
1704         return err;
1705 }
1706
1707 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1708 {
1709         mutex_lock(&dev->lb.mutex);
1710         if (td)
1711                 dev->lb.user_td--;
1712         if (qp)
1713                 dev->lb.qps--;
1714
1715         if (dev->lb.user_td == 1 &&
1716             dev->lb.qps == 0) {
1717                 if (dev->lb.enabled) {
1718                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1719                         dev->lb.enabled = false;
1720                 }
1721         }
1722
1723         mutex_unlock(&dev->lb.mutex);
1724 }
1725
1726 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1727                                           u16 uid)
1728 {
1729         int err;
1730
1731         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1732                 return 0;
1733
1734         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1735         if (err)
1736                 return err;
1737
1738         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1739             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1740              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1741                 return err;
1742
1743         return mlx5_ib_enable_lb(dev, true, false);
1744 }
1745
1746 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1747                                              u16 uid)
1748 {
1749         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1750                 return;
1751
1752         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1753
1754         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1755             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1756              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1757                 return;
1758
1759         mlx5_ib_disable_lb(dev, true, false);
1760 }
1761
1762 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1763                                   struct ib_udata *udata)
1764 {
1765         struct ib_device *ibdev = uctx->device;
1766         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1767         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1768         struct mlx5_ib_alloc_ucontext_resp resp = {};
1769         struct mlx5_core_dev *mdev = dev->mdev;
1770         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1771         struct mlx5_bfreg_info *bfregi;
1772         int ver;
1773         int err;
1774         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1775                                      max_cqe_version);
1776         u32 dump_fill_mkey;
1777         bool lib_uar_4k;
1778
1779         if (!dev->ib_active)
1780                 return -EAGAIN;
1781
1782         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1783                 ver = 0;
1784         else if (udata->inlen >= min_req_v2)
1785                 ver = 2;
1786         else
1787                 return -EINVAL;
1788
1789         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1790         if (err)
1791                 return err;
1792
1793         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1794                 return -EOPNOTSUPP;
1795
1796         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1797                 return -EOPNOTSUPP;
1798
1799         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1800                                     MLX5_NON_FP_BFREGS_PER_UAR);
1801         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1802                 return -EINVAL;
1803
1804         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1805         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1806                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1807         resp.cache_line_size = cache_line_size();
1808         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1809         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1810         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1811         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1812         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1813         resp.cqe_version = min_t(__u8,
1814                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1815                                  req.max_cqe_version);
1816         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1817                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1818         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1819                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1820         resp.response_length = min(offsetof(typeof(resp), response_length) +
1821                                    sizeof(resp.response_length), udata->outlen);
1822
1823         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1824                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1825                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1826                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1827                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1828                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1829                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1830                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1831                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1832                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1833         }
1834
1835         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1836         bfregi = &context->bfregi;
1837
1838         /* updates req->total_num_bfregs */
1839         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1840         if (err)
1841                 goto out_ctx;
1842
1843         mutex_init(&bfregi->lock);
1844         bfregi->lib_uar_4k = lib_uar_4k;
1845         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1846                                 GFP_KERNEL);
1847         if (!bfregi->count) {
1848                 err = -ENOMEM;
1849                 goto out_ctx;
1850         }
1851
1852         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1853                                     sizeof(*bfregi->sys_pages),
1854                                     GFP_KERNEL);
1855         if (!bfregi->sys_pages) {
1856                 err = -ENOMEM;
1857                 goto out_count;
1858         }
1859
1860         err = allocate_uars(dev, context);
1861         if (err)
1862                 goto out_sys_pages;
1863
1864         if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING)
1865                 context->ibucontext.invalidate_range =
1866                         &mlx5_ib_invalidate_range;
1867
1868         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1869                 err = mlx5_ib_devx_create(dev, true);
1870                 if (err < 0)
1871                         goto out_uars;
1872                 context->devx_uid = err;
1873         }
1874
1875         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1876                                              context->devx_uid);
1877         if (err)
1878                 goto out_devx;
1879
1880         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1881                 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1882                 if (err)
1883                         goto out_mdev;
1884         }
1885
1886         INIT_LIST_HEAD(&context->db_page_list);
1887         mutex_init(&context->db_page_mutex);
1888
1889         resp.tot_bfregs = req.total_num_bfregs;
1890         resp.num_ports = dev->num_ports;
1891
1892         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1893                 resp.response_length += sizeof(resp.cqe_version);
1894
1895         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1896                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1897                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1898                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1899         }
1900
1901         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1902                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1903                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1904                         resp.eth_min_inline++;
1905                 }
1906                 resp.response_length += sizeof(resp.eth_min_inline);
1907         }
1908
1909         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1910                 if (mdev->clock_info)
1911                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1912                 resp.response_length += sizeof(resp.clock_info_versions);
1913         }
1914
1915         /*
1916          * We don't want to expose information from the PCI bar that is located
1917          * after 4096 bytes, so if the arch only supports larger pages, let's
1918          * pretend we don't support reading the HCA's core clock. This is also
1919          * forced by mmap function.
1920          */
1921         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1922                 if (PAGE_SIZE <= 4096) {
1923                         resp.comp_mask |=
1924                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1925                         resp.hca_core_clock_offset =
1926                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1927                 }
1928                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1929         }
1930
1931         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1932                 resp.response_length += sizeof(resp.log_uar_size);
1933
1934         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1935                 resp.response_length += sizeof(resp.num_uars_per_page);
1936
1937         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1938                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1939                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1940         }
1941
1942         if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1943                 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1944                         resp.dump_fill_mkey = dump_fill_mkey;
1945                         resp.comp_mask |=
1946                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1947                 }
1948                 resp.response_length += sizeof(resp.dump_fill_mkey);
1949         }
1950
1951         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1952         if (err)
1953                 goto out_mdev;
1954
1955         bfregi->ver = ver;
1956         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1957         context->cqe_version = resp.cqe_version;
1958         context->lib_caps = req.lib_caps;
1959         print_lib_caps(dev, context->lib_caps);
1960
1961         if (dev->lag_active) {
1962                 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1963
1964                 atomic_set(&context->tx_port_affinity,
1965                            atomic_add_return(
1966                                    1, &dev->port[port].roce.tx_port_affinity));
1967         }
1968
1969         return 0;
1970
1971 out_mdev:
1972         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1973 out_devx:
1974         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1975                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1976
1977 out_uars:
1978         deallocate_uars(dev, context);
1979
1980 out_sys_pages:
1981         kfree(bfregi->sys_pages);
1982
1983 out_count:
1984         kfree(bfregi->count);
1985
1986 out_ctx:
1987         return err;
1988 }
1989
1990 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1991 {
1992         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1993         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1994         struct mlx5_bfreg_info *bfregi;
1995
1996         /* All umem's must be destroyed before destroying the ucontext. */
1997         mutex_lock(&ibcontext->per_mm_list_lock);
1998         WARN_ON(!list_empty(&ibcontext->per_mm_list));
1999         mutex_unlock(&ibcontext->per_mm_list_lock);
2000
2001         bfregi = &context->bfregi;
2002         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2003
2004         if (context->devx_uid)
2005                 mlx5_ib_devx_destroy(dev, context->devx_uid);
2006
2007         deallocate_uars(dev, context);
2008         kfree(bfregi->sys_pages);
2009         kfree(bfregi->count);
2010 }
2011
2012 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2013                                  int uar_idx)
2014 {
2015         int fw_uars_per_page;
2016
2017         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2018
2019         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2020 }
2021
2022 static int get_command(unsigned long offset)
2023 {
2024         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2025 }
2026
2027 static int get_arg(unsigned long offset)
2028 {
2029         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2030 }
2031
2032 static int get_index(unsigned long offset)
2033 {
2034         return get_arg(offset);
2035 }
2036
2037 /* Index resides in an extra byte to enable larger values than 255 */
2038 static int get_extended_index(unsigned long offset)
2039 {
2040         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2041 }
2042
2043
2044 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2045 {
2046 }
2047
2048 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2049 {
2050         switch (cmd) {
2051         case MLX5_IB_MMAP_WC_PAGE:
2052                 return "WC";
2053         case MLX5_IB_MMAP_REGULAR_PAGE:
2054                 return "best effort WC";
2055         case MLX5_IB_MMAP_NC_PAGE:
2056                 return "NC";
2057         case MLX5_IB_MMAP_DEVICE_MEM:
2058                 return "Device Memory";
2059         default:
2060                 return NULL;
2061         }
2062 }
2063
2064 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2065                                         struct vm_area_struct *vma,
2066                                         struct mlx5_ib_ucontext *context)
2067 {
2068         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2069             !(vma->vm_flags & VM_SHARED))
2070                 return -EINVAL;
2071
2072         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2073                 return -EOPNOTSUPP;
2074
2075         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2076                 return -EPERM;
2077         vma->vm_flags &= ~VM_MAYWRITE;
2078
2079         if (!dev->mdev->clock_info)
2080                 return -EOPNOTSUPP;
2081
2082         return vm_insert_page(vma, vma->vm_start,
2083                               virt_to_page(dev->mdev->clock_info));
2084 }
2085
2086 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2087                     struct vm_area_struct *vma,
2088                     struct mlx5_ib_ucontext *context)
2089 {
2090         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2091         int err;
2092         unsigned long idx;
2093         phys_addr_t pfn;
2094         pgprot_t prot;
2095         u32 bfreg_dyn_idx = 0;
2096         u32 uar_index;
2097         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2098         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2099                                 bfregi->num_static_sys_pages;
2100
2101         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2102                 return -EINVAL;
2103
2104         if (dyn_uar)
2105                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2106         else
2107                 idx = get_index(vma->vm_pgoff);
2108
2109         if (idx >= max_valid_idx) {
2110                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2111                              idx, max_valid_idx);
2112                 return -EINVAL;
2113         }
2114
2115         switch (cmd) {
2116         case MLX5_IB_MMAP_WC_PAGE:
2117         case MLX5_IB_MMAP_ALLOC_WC:
2118 /* Some architectures don't support WC memory */
2119 #if defined(CONFIG_X86)
2120                 if (!pat_enabled())
2121                         return -EPERM;
2122 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2123                         return -EPERM;
2124 #endif
2125         /* fall through */
2126         case MLX5_IB_MMAP_REGULAR_PAGE:
2127                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2128                 prot = pgprot_writecombine(vma->vm_page_prot);
2129                 break;
2130         case MLX5_IB_MMAP_NC_PAGE:
2131                 prot = pgprot_noncached(vma->vm_page_prot);
2132                 break;
2133         default:
2134                 return -EINVAL;
2135         }
2136
2137         if (dyn_uar) {
2138                 int uars_per_page;
2139
2140                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2141                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2142                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2143                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2144                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2145                         return -EINVAL;
2146                 }
2147
2148                 mutex_lock(&bfregi->lock);
2149                 /* Fail if uar already allocated, first bfreg index of each
2150                  * page holds its count.
2151                  */
2152                 if (bfregi->count[bfreg_dyn_idx]) {
2153                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2154                         mutex_unlock(&bfregi->lock);
2155                         return -EINVAL;
2156                 }
2157
2158                 bfregi->count[bfreg_dyn_idx]++;
2159                 mutex_unlock(&bfregi->lock);
2160
2161                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2162                 if (err) {
2163                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2164                         goto free_bfreg;
2165                 }
2166         } else {
2167                 uar_index = bfregi->sys_pages[idx];
2168         }
2169
2170         pfn = uar_index2pfn(dev, uar_index);
2171         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2172
2173         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2174                                 prot);
2175         if (err) {
2176                 mlx5_ib_err(dev,
2177                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2178                             err, mmap_cmd2str(cmd));
2179                 goto err;
2180         }
2181
2182         if (dyn_uar)
2183                 bfregi->sys_pages[idx] = uar_index;
2184         return 0;
2185
2186 err:
2187         if (!dyn_uar)
2188                 return err;
2189
2190         mlx5_cmd_free_uar(dev->mdev, idx);
2191
2192 free_bfreg:
2193         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2194
2195         return err;
2196 }
2197
2198 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2199 {
2200         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2201         struct mlx5_ib_dev *dev = to_mdev(context->device);
2202         u16 page_idx = get_extended_index(vma->vm_pgoff);
2203         size_t map_size = vma->vm_end - vma->vm_start;
2204         u32 npages = map_size >> PAGE_SHIFT;
2205         phys_addr_t pfn;
2206
2207         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2208             page_idx + npages)
2209                 return -EINVAL;
2210
2211         pfn = ((dev->mdev->bar_addr +
2212               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2213               PAGE_SHIFT) +
2214               page_idx;
2215         return rdma_user_mmap_io(context, vma, pfn, map_size,
2216                                  pgprot_writecombine(vma->vm_page_prot));
2217 }
2218
2219 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2220 {
2221         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2222         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2223         unsigned long command;
2224         phys_addr_t pfn;
2225
2226         command = get_command(vma->vm_pgoff);
2227         switch (command) {
2228         case MLX5_IB_MMAP_WC_PAGE:
2229         case MLX5_IB_MMAP_NC_PAGE:
2230         case MLX5_IB_MMAP_REGULAR_PAGE:
2231         case MLX5_IB_MMAP_ALLOC_WC:
2232                 return uar_mmap(dev, command, vma, context);
2233
2234         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2235                 return -ENOSYS;
2236
2237         case MLX5_IB_MMAP_CORE_CLOCK:
2238                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2239                         return -EINVAL;
2240
2241                 if (vma->vm_flags & VM_WRITE)
2242                         return -EPERM;
2243                 vma->vm_flags &= ~VM_MAYWRITE;
2244
2245                 /* Don't expose to user-space information it shouldn't have */
2246                 if (PAGE_SIZE > 4096)
2247                         return -EOPNOTSUPP;
2248
2249                 pfn = (dev->mdev->iseg_base +
2250                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2251                         PAGE_SHIFT;
2252                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2253                                          PAGE_SIZE,
2254                                          pgprot_noncached(vma->vm_page_prot));
2255         case MLX5_IB_MMAP_CLOCK_INFO:
2256                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2257
2258         case MLX5_IB_MMAP_DEVICE_MEM:
2259                 return dm_mmap(ibcontext, vma);
2260
2261         default:
2262                 return -EINVAL;
2263         }
2264
2265         return 0;
2266 }
2267
2268 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2269                                         u32 type)
2270 {
2271         switch (type) {
2272         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2273                 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2274                         return -EOPNOTSUPP;
2275                 break;
2276         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2277                 if (!capable(CAP_SYS_RAWIO) ||
2278                     !capable(CAP_NET_RAW))
2279                         return -EPERM;
2280
2281                 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2282                       MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2283                         return -EOPNOTSUPP;
2284                 break;
2285         }
2286
2287         return 0;
2288 }
2289
2290 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2291                                  struct mlx5_ib_dm *dm,
2292                                  struct ib_dm_alloc_attr *attr,
2293                                  struct uverbs_attr_bundle *attrs)
2294 {
2295         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2296         u64 start_offset;
2297         u32 page_idx;
2298         int err;
2299
2300         dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2301
2302         err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2303                                    dm->size, attr->alignment);
2304         if (err)
2305                 return err;
2306
2307         page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2308                     MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
2309                     PAGE_SHIFT;
2310
2311         err = uverbs_copy_to(attrs,
2312                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2313                              &page_idx, sizeof(page_idx));
2314         if (err)
2315                 goto err_dealloc;
2316
2317         start_offset = dm->dev_addr & ~PAGE_MASK;
2318         err = uverbs_copy_to(attrs,
2319                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2320                              &start_offset, sizeof(start_offset));
2321         if (err)
2322                 goto err_dealloc;
2323
2324         bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2325                    DIV_ROUND_UP(dm->size, PAGE_SIZE));
2326
2327         return 0;
2328
2329 err_dealloc:
2330         mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2331
2332         return err;
2333 }
2334
2335 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2336                                   struct mlx5_ib_dm *dm,
2337                                   struct ib_dm_alloc_attr *attr,
2338                                   struct uverbs_attr_bundle *attrs,
2339                                   int type)
2340 {
2341         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2342         u64 act_size;
2343         int err;
2344
2345         /* Allocation size must a multiple of the basic block size
2346          * and a power of 2.
2347          */
2348         act_size = roundup(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dm_db->dev));
2349         act_size = roundup_pow_of_two(act_size);
2350
2351         dm->size = act_size;
2352         err = mlx5_cmd_alloc_sw_icm(dm_db, type, act_size,
2353                                     to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2354                                     &dm->icm_dm.obj_id);
2355         if (err)
2356                 return err;
2357
2358         err = uverbs_copy_to(attrs,
2359                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2360                              &dm->dev_addr, sizeof(dm->dev_addr));
2361         if (err)
2362                 mlx5_cmd_dealloc_sw_icm(dm_db, type, dm->size,
2363                                         to_mucontext(ctx)->devx_uid,
2364                                         dm->dev_addr, dm->icm_dm.obj_id);
2365
2366         return err;
2367 }
2368
2369 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2370                                struct ib_ucontext *context,
2371                                struct ib_dm_alloc_attr *attr,
2372                                struct uverbs_attr_bundle *attrs)
2373 {
2374         struct mlx5_ib_dm *dm;
2375         enum mlx5_ib_uapi_dm_type type;
2376         int err;
2377
2378         err = uverbs_get_const_default(&type, attrs,
2379                                        MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2380                                        MLX5_IB_UAPI_DM_TYPE_MEMIC);
2381         if (err)
2382                 return ERR_PTR(err);
2383
2384         mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2385                     type, attr->length, attr->alignment);
2386
2387         err = check_dm_type_support(to_mdev(ibdev), type);
2388         if (err)
2389                 return ERR_PTR(err);
2390
2391         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2392         if (!dm)
2393                 return ERR_PTR(-ENOMEM);
2394
2395         dm->type = type;
2396
2397         switch (type) {
2398         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2399                 err = handle_alloc_dm_memic(context, dm,
2400                                             attr,
2401                                             attrs);
2402                 break;
2403         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2404         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2405                 err = handle_alloc_dm_sw_icm(context, dm, attr, attrs, type);
2406                 break;
2407         default:
2408                 err = -EOPNOTSUPP;
2409         }
2410
2411         if (err)
2412                 goto err_free;
2413
2414         return &dm->ibdm;
2415
2416 err_free:
2417         kfree(dm);
2418         return ERR_PTR(err);
2419 }
2420
2421 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2422 {
2423         struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2424                 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2425         struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
2426         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2427         u32 page_idx;
2428         int ret;
2429
2430         switch (dm->type) {
2431         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2432                 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2433                 if (ret)
2434                         return ret;
2435
2436                 page_idx = (dm->dev_addr -
2437                             pci_resource_start(dm_db->dev->pdev, 0) -
2438                             MLX5_CAP64_DEV_MEM(dm_db->dev,
2439                                                memic_bar_start_addr)) >>
2440                            PAGE_SHIFT;
2441                 bitmap_clear(ctx->dm_pages, page_idx,
2442                              DIV_ROUND_UP(dm->size, PAGE_SIZE));
2443                 break;
2444         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2445         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2446                 ret = mlx5_cmd_dealloc_sw_icm(dm_db, dm->type, dm->size,
2447                                               ctx->devx_uid, dm->dev_addr,
2448                                               dm->icm_dm.obj_id);
2449                 if (ret)
2450                         return ret;
2451                 break;
2452         default:
2453                 return -EOPNOTSUPP;
2454         }
2455
2456         kfree(dm);
2457
2458         return 0;
2459 }
2460
2461 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2462 {
2463         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2464         struct ib_device *ibdev = ibpd->device;
2465         struct mlx5_ib_alloc_pd_resp resp;
2466         int err;
2467         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2468         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)]   = {};
2469         u16 uid = 0;
2470         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2471                 udata, struct mlx5_ib_ucontext, ibucontext);
2472
2473         uid = context ? context->devx_uid : 0;
2474         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2475         MLX5_SET(alloc_pd_in, in, uid, uid);
2476         err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2477                             out, sizeof(out));
2478         if (err)
2479                 return err;
2480
2481         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2482         pd->uid = uid;
2483         if (udata) {
2484                 resp.pdn = pd->pdn;
2485                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2486                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2487                         return -EFAULT;
2488                 }
2489         }
2490
2491         return 0;
2492 }
2493
2494 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2495 {
2496         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2497         struct mlx5_ib_pd *mpd = to_mpd(pd);
2498
2499         mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2500 }
2501
2502 enum {
2503         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2504         MATCH_CRITERIA_ENABLE_MISC_BIT,
2505         MATCH_CRITERIA_ENABLE_INNER_BIT,
2506         MATCH_CRITERIA_ENABLE_MISC2_BIT
2507 };
2508
2509 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2510         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2511                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2512
2513 static u8 get_match_criteria_enable(u32 *match_criteria)
2514 {
2515         u8 match_criteria_enable;
2516
2517         match_criteria_enable =
2518                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2519                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2520         match_criteria_enable |=
2521                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2522                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2523         match_criteria_enable |=
2524                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2525                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2526         match_criteria_enable |=
2527                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2528                 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2529
2530         return match_criteria_enable;
2531 }
2532
2533 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2534 {
2535         u8 entry_mask;
2536         u8 entry_val;
2537         int err = 0;
2538
2539         if (!mask)
2540                 goto out;
2541
2542         entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2543                               ip_protocol);
2544         entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2545                              ip_protocol);
2546         if (!entry_mask) {
2547                 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2548                 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2549                 goto out;
2550         }
2551         /* Don't override existing ip protocol */
2552         if (mask != entry_mask || val != entry_val)
2553                 err = -EINVAL;
2554 out:
2555         return err;
2556 }
2557
2558 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2559                            bool inner)
2560 {
2561         if (inner) {
2562                 MLX5_SET(fte_match_set_misc,
2563                          misc_c, inner_ipv6_flow_label, mask);
2564                 MLX5_SET(fte_match_set_misc,
2565                          misc_v, inner_ipv6_flow_label, val);
2566         } else {
2567                 MLX5_SET(fte_match_set_misc,
2568                          misc_c, outer_ipv6_flow_label, mask);
2569                 MLX5_SET(fte_match_set_misc,
2570                          misc_v, outer_ipv6_flow_label, val);
2571         }
2572 }
2573
2574 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2575 {
2576         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2577         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2578         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2579         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2580 }
2581
2582 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2583 {
2584         if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2585             !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2586                 return -EOPNOTSUPP;
2587
2588         if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2589             !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2590                 return -EOPNOTSUPP;
2591
2592         if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2593             !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2594                 return -EOPNOTSUPP;
2595
2596         if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2597             !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2598                 return -EOPNOTSUPP;
2599
2600         return 0;
2601 }
2602
2603 #define LAST_ETH_FIELD vlan_tag
2604 #define LAST_IB_FIELD sl
2605 #define LAST_IPV4_FIELD tos
2606 #define LAST_IPV6_FIELD traffic_class
2607 #define LAST_TCP_UDP_FIELD src_port
2608 #define LAST_TUNNEL_FIELD tunnel_id
2609 #define LAST_FLOW_TAG_FIELD tag_id
2610 #define LAST_DROP_FIELD size
2611 #define LAST_COUNTERS_FIELD counters
2612
2613 /* Field is the last supported field */
2614 #define FIELDS_NOT_SUPPORTED(filter, field)\
2615         memchr_inv((void *)&filter.field  +\
2616                    sizeof(filter.field), 0,\
2617                    sizeof(filter) -\
2618                    offsetof(typeof(filter), field) -\
2619                    sizeof(filter.field))
2620
2621 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2622                            bool is_egress,
2623                            struct mlx5_flow_act *action)
2624 {
2625
2626         switch (maction->ib_action.type) {
2627         case IB_FLOW_ACTION_ESP:
2628                 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2629                                       MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2630                         return -EINVAL;
2631                 /* Currently only AES_GCM keymat is supported by the driver */
2632                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2633                 action->action |= is_egress ?
2634                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2635                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2636                 return 0;
2637         case IB_FLOW_ACTION_UNSPECIFIED:
2638                 if (maction->flow_action_raw.sub_type ==
2639                     MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2640                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2641                                 return -EINVAL;
2642                         action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2643                         action->modify_id = maction->flow_action_raw.action_id;
2644                         return 0;
2645                 }
2646                 if (maction->flow_action_raw.sub_type ==
2647                     MLX5_IB_FLOW_ACTION_DECAP) {
2648                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2649                                 return -EINVAL;
2650                         action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2651                         return 0;
2652                 }
2653                 if (maction->flow_action_raw.sub_type ==
2654                     MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2655                         if (action->action &
2656                             MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2657                                 return -EINVAL;
2658                         action->action |=
2659                                 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2660                         action->reformat_id =
2661                                 maction->flow_action_raw.action_id;
2662                         return 0;
2663                 }
2664                 /* fall through */
2665         default:
2666                 return -EOPNOTSUPP;
2667         }
2668 }
2669
2670 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2671                            u32 *match_v, const union ib_flow_spec *ib_spec,
2672                            const struct ib_flow_attr *flow_attr,
2673                            struct mlx5_flow_act *action, u32 prev_type)
2674 {
2675         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2676                                            misc_parameters);
2677         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2678                                            misc_parameters);
2679         void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2680                                             misc_parameters_2);
2681         void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2682                                             misc_parameters_2);
2683         void *headers_c;
2684         void *headers_v;
2685         int match_ipv;
2686         int ret;
2687
2688         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2689                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2690                                          inner_headers);
2691                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2692                                          inner_headers);
2693                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2694                                         ft_field_support.inner_ip_version);
2695         } else {
2696                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2697                                          outer_headers);
2698                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2699                                          outer_headers);
2700                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2701                                         ft_field_support.outer_ip_version);
2702         }
2703
2704         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2705         case IB_FLOW_SPEC_ETH:
2706                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2707                         return -EOPNOTSUPP;
2708
2709                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2710                                              dmac_47_16),
2711                                 ib_spec->eth.mask.dst_mac);
2712                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2713                                              dmac_47_16),
2714                                 ib_spec->eth.val.dst_mac);
2715
2716                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2717                                              smac_47_16),
2718                                 ib_spec->eth.mask.src_mac);
2719                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2720                                              smac_47_16),
2721                                 ib_spec->eth.val.src_mac);
2722
2723                 if (ib_spec->eth.mask.vlan_tag) {
2724                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2725                                  cvlan_tag, 1);
2726                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2727                                  cvlan_tag, 1);
2728
2729                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2730                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2731                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2732                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2733
2734                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2735                                  first_cfi,
2736                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2737                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2738                                  first_cfi,
2739                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2740
2741                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2742                                  first_prio,
2743                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2744                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2745                                  first_prio,
2746                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2747                 }
2748                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2749                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2750                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2751                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2752                 break;
2753         case IB_FLOW_SPEC_IPV4:
2754                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2755                         return -EOPNOTSUPP;
2756
2757                 if (match_ipv) {
2758                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2759                                  ip_version, 0xf);
2760                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2761                                  ip_version, MLX5_FS_IPV4_VERSION);
2762                 } else {
2763                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2764                                  ethertype, 0xffff);
2765                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2766                                  ethertype, ETH_P_IP);
2767                 }
2768
2769                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2770                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2771                        &ib_spec->ipv4.mask.src_ip,
2772                        sizeof(ib_spec->ipv4.mask.src_ip));
2773                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2774                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2775                        &ib_spec->ipv4.val.src_ip,
2776                        sizeof(ib_spec->ipv4.val.src_ip));
2777                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2778                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2779                        &ib_spec->ipv4.mask.dst_ip,
2780                        sizeof(ib_spec->ipv4.mask.dst_ip));
2781                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2782                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2783                        &ib_spec->ipv4.val.dst_ip,
2784                        sizeof(ib_spec->ipv4.val.dst_ip));
2785
2786                 set_tos(headers_c, headers_v,
2787                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2788
2789                 if (set_proto(headers_c, headers_v,
2790                               ib_spec->ipv4.mask.proto,
2791                               ib_spec->ipv4.val.proto))
2792                         return -EINVAL;
2793                 break;
2794         case IB_FLOW_SPEC_IPV6:
2795                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2796                         return -EOPNOTSUPP;
2797
2798                 if (match_ipv) {
2799                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2800                                  ip_version, 0xf);
2801                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2802                                  ip_version, MLX5_FS_IPV6_VERSION);
2803                 } else {
2804                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2805                                  ethertype, 0xffff);
2806                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2807                                  ethertype, ETH_P_IPV6);
2808                 }
2809
2810                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2811                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2812                        &ib_spec->ipv6.mask.src_ip,
2813                        sizeof(ib_spec->ipv6.mask.src_ip));
2814                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2815                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2816                        &ib_spec->ipv6.val.src_ip,
2817                        sizeof(ib_spec->ipv6.val.src_ip));
2818                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2819                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2820                        &ib_spec->ipv6.mask.dst_ip,
2821                        sizeof(ib_spec->ipv6.mask.dst_ip));
2822                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2823                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2824                        &ib_spec->ipv6.val.dst_ip,
2825                        sizeof(ib_spec->ipv6.val.dst_ip));
2826
2827                 set_tos(headers_c, headers_v,
2828                         ib_spec->ipv6.mask.traffic_class,
2829                         ib_spec->ipv6.val.traffic_class);
2830
2831                 if (set_proto(headers_c, headers_v,
2832                               ib_spec->ipv6.mask.next_hdr,
2833                               ib_spec->ipv6.val.next_hdr))
2834                         return -EINVAL;
2835
2836                 set_flow_label(misc_params_c, misc_params_v,
2837                                ntohl(ib_spec->ipv6.mask.flow_label),
2838                                ntohl(ib_spec->ipv6.val.flow_label),
2839                                ib_spec->type & IB_FLOW_SPEC_INNER);
2840                 break;
2841         case IB_FLOW_SPEC_ESP:
2842                 if (ib_spec->esp.mask.seq)
2843                         return -EOPNOTSUPP;
2844
2845                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2846                          ntohl(ib_spec->esp.mask.spi));
2847                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2848                          ntohl(ib_spec->esp.val.spi));
2849                 break;
2850         case IB_FLOW_SPEC_TCP:
2851                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2852                                          LAST_TCP_UDP_FIELD))
2853                         return -EOPNOTSUPP;
2854
2855                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2856                         return -EINVAL;
2857
2858                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2859                          ntohs(ib_spec->tcp_udp.mask.src_port));
2860                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2861                          ntohs(ib_spec->tcp_udp.val.src_port));
2862
2863                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2864                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2865                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2866                          ntohs(ib_spec->tcp_udp.val.dst_port));
2867                 break;
2868         case IB_FLOW_SPEC_UDP:
2869                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2870                                          LAST_TCP_UDP_FIELD))
2871                         return -EOPNOTSUPP;
2872
2873                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2874                         return -EINVAL;
2875
2876                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2877                          ntohs(ib_spec->tcp_udp.mask.src_port));
2878                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2879                          ntohs(ib_spec->tcp_udp.val.src_port));
2880
2881                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2882                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2883                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2884                          ntohs(ib_spec->tcp_udp.val.dst_port));
2885                 break;
2886         case IB_FLOW_SPEC_GRE:
2887                 if (ib_spec->gre.mask.c_ks_res0_ver)
2888                         return -EOPNOTSUPP;
2889
2890                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2891                         return -EINVAL;
2892
2893                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2894                          0xff);
2895                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2896                          IPPROTO_GRE);
2897
2898                 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2899                          ntohs(ib_spec->gre.mask.protocol));
2900                 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2901                          ntohs(ib_spec->gre.val.protocol));
2902
2903                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2904                                     gre_key.nvgre.hi),
2905                        &ib_spec->gre.mask.key,
2906                        sizeof(ib_spec->gre.mask.key));
2907                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2908                                     gre_key.nvgre.hi),
2909                        &ib_spec->gre.val.key,
2910                        sizeof(ib_spec->gre.val.key));
2911                 break;
2912         case IB_FLOW_SPEC_MPLS:
2913                 switch (prev_type) {
2914                 case IB_FLOW_SPEC_UDP:
2915                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2916                                                    ft_field_support.outer_first_mpls_over_udp),
2917                                                    &ib_spec->mpls.mask.tag))
2918                                 return -EOPNOTSUPP;
2919
2920                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2921                                             outer_first_mpls_over_udp),
2922                                &ib_spec->mpls.val.tag,
2923                                sizeof(ib_spec->mpls.val.tag));
2924                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2925                                             outer_first_mpls_over_udp),
2926                                &ib_spec->mpls.mask.tag,
2927                                sizeof(ib_spec->mpls.mask.tag));
2928                         break;
2929                 case IB_FLOW_SPEC_GRE:
2930                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2931                                                    ft_field_support.outer_first_mpls_over_gre),
2932                                                    &ib_spec->mpls.mask.tag))
2933                                 return -EOPNOTSUPP;
2934
2935                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2936                                             outer_first_mpls_over_gre),
2937                                &ib_spec->mpls.val.tag,
2938                                sizeof(ib_spec->mpls.val.tag));
2939                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2940                                             outer_first_mpls_over_gre),
2941                                &ib_spec->mpls.mask.tag,
2942                                sizeof(ib_spec->mpls.mask.tag));
2943                         break;
2944                 default:
2945                         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2946                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2947                                                            ft_field_support.inner_first_mpls),
2948                                                            &ib_spec->mpls.mask.tag))
2949                                         return -EOPNOTSUPP;
2950
2951                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2952                                                     inner_first_mpls),
2953                                        &ib_spec->mpls.val.tag,
2954                                        sizeof(ib_spec->mpls.val.tag));
2955                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2956                                                     inner_first_mpls),
2957                                        &ib_spec->mpls.mask.tag,
2958                                        sizeof(ib_spec->mpls.mask.tag));
2959                         } else {
2960                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2961                                                            ft_field_support.outer_first_mpls),
2962                                                            &ib_spec->mpls.mask.tag))
2963                                         return -EOPNOTSUPP;
2964
2965                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2966                                                     outer_first_mpls),
2967                                        &ib_spec->mpls.val.tag,
2968                                        sizeof(ib_spec->mpls.val.tag));
2969                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2970                                                     outer_first_mpls),
2971                                        &ib_spec->mpls.mask.tag,
2972                                        sizeof(ib_spec->mpls.mask.tag));
2973                         }
2974                 }
2975                 break;
2976         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2977                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2978                                          LAST_TUNNEL_FIELD))
2979                         return -EOPNOTSUPP;
2980
2981                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2982                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2983                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2984                          ntohl(ib_spec->tunnel.val.tunnel_id));
2985                 break;
2986         case IB_FLOW_SPEC_ACTION_TAG:
2987                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2988                                          LAST_FLOW_TAG_FIELD))
2989                         return -EOPNOTSUPP;
2990                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2991                         return -EINVAL;
2992
2993                 action->flow_tag = ib_spec->flow_tag.tag_id;
2994                 action->flags |= FLOW_ACT_HAS_TAG;
2995                 break;
2996         case IB_FLOW_SPEC_ACTION_DROP:
2997                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2998                                          LAST_DROP_FIELD))
2999                         return -EOPNOTSUPP;
3000                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3001                 break;
3002         case IB_FLOW_SPEC_ACTION_HANDLE:
3003                 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3004                         flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
3005                 if (ret)
3006                         return ret;
3007                 break;
3008         case IB_FLOW_SPEC_ACTION_COUNT:
3009                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3010                                          LAST_COUNTERS_FIELD))
3011                         return -EOPNOTSUPP;
3012
3013                 /* for now support only one counters spec per flow */
3014                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3015                         return -EINVAL;
3016
3017                 action->counters = ib_spec->flow_count.counters;
3018                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3019                 break;
3020         default:
3021                 return -EINVAL;
3022         }
3023
3024         return 0;
3025 }
3026
3027 /* If a flow could catch both multicast and unicast packets,
3028  * it won't fall into the multicast flow steering table and this rule
3029  * could steal other multicast packets.
3030  */
3031 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
3032 {
3033         union ib_flow_spec *flow_spec;
3034
3035         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
3036             ib_attr->num_of_specs < 1)
3037                 return false;
3038
3039         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3040         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3041                 struct ib_flow_spec_ipv4 *ipv4_spec;
3042
3043                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3044                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3045                         return true;
3046
3047                 return false;
3048         }
3049
3050         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3051                 struct ib_flow_spec_eth *eth_spec;
3052
3053                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3054                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3055                        is_multicast_ether_addr(eth_spec->val.dst_mac);
3056         }
3057
3058         return false;
3059 }
3060
3061 enum valid_spec {
3062         VALID_SPEC_INVALID,
3063         VALID_SPEC_VALID,
3064         VALID_SPEC_NA,
3065 };
3066
3067 static enum valid_spec
3068 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3069                      const struct mlx5_flow_spec *spec,
3070                      const struct mlx5_flow_act *flow_act,
3071                      bool egress)
3072 {
3073         const u32 *match_c = spec->match_criteria;
3074         bool is_crypto =
3075                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3076                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3077         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3078         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3079
3080         /*
3081          * Currently only crypto is supported in egress, when regular egress
3082          * rules would be supported, always return VALID_SPEC_NA.
3083          */
3084         if (!is_crypto)
3085                 return VALID_SPEC_NA;
3086
3087         return is_crypto && is_ipsec &&
3088                 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ?
3089                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3090 }
3091
3092 static bool is_valid_spec(struct mlx5_core_dev *mdev,
3093                           const struct mlx5_flow_spec *spec,
3094                           const struct mlx5_flow_act *flow_act,
3095                           bool egress)
3096 {
3097         /* We curretly only support ipsec egress flow */
3098         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3099 }
3100
3101 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3102                                const struct ib_flow_attr *flow_attr,
3103                                bool check_inner)
3104 {
3105         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
3106         int match_ipv = check_inner ?
3107                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3108                                         ft_field_support.inner_ip_version) :
3109                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3110                                         ft_field_support.outer_ip_version);
3111         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3112         bool ipv4_spec_valid, ipv6_spec_valid;
3113         unsigned int ip_spec_type = 0;
3114         bool has_ethertype = false;
3115         unsigned int spec_index;
3116         bool mask_valid = true;
3117         u16 eth_type = 0;
3118         bool type_valid;
3119
3120         /* Validate that ethertype is correct */
3121         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3122                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
3123                     ib_spec->eth.mask.ether_type) {
3124                         mask_valid = (ib_spec->eth.mask.ether_type ==
3125                                       htons(0xffff));
3126                         has_ethertype = true;
3127                         eth_type = ntohs(ib_spec->eth.val.ether_type);
3128                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3129                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3130                         ip_spec_type = ib_spec->type;
3131                 }
3132                 ib_spec = (void *)ib_spec + ib_spec->size;
3133         }
3134
3135         type_valid = (!has_ethertype) || (!ip_spec_type);
3136         if (!type_valid && mask_valid) {
3137                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3138                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3139                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3140                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
3141
3142                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3143                              (((eth_type == ETH_P_MPLS_UC) ||
3144                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
3145         }
3146
3147         return type_valid;
3148 }
3149
3150 static bool is_valid_attr(struct mlx5_core_dev *mdev,
3151                           const struct ib_flow_attr *flow_attr)
3152 {
3153         return is_valid_ethertype(mdev, flow_attr, false) &&
3154                is_valid_ethertype(mdev, flow_attr, true);
3155 }
3156
3157 static void put_flow_table(struct mlx5_ib_dev *dev,
3158                            struct mlx5_ib_flow_prio *prio, bool ft_added)
3159 {
3160         prio->refcount -= !!ft_added;
3161         if (!prio->refcount) {
3162                 mlx5_destroy_flow_table(prio->flow_table);
3163                 prio->flow_table = NULL;
3164         }
3165 }
3166
3167 static void counters_clear_description(struct ib_counters *counters)
3168 {
3169         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3170
3171         mutex_lock(&mcounters->mcntrs_mutex);
3172         kfree(mcounters->counters_data);
3173         mcounters->counters_data = NULL;
3174         mcounters->cntrs_max_index = 0;
3175         mutex_unlock(&mcounters->mcntrs_mutex);
3176 }
3177
3178 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3179 {
3180         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3181                                                           struct mlx5_ib_flow_handler,
3182                                                           ibflow);
3183         struct mlx5_ib_flow_handler *iter, *tmp;
3184         struct mlx5_ib_dev *dev = handler->dev;
3185
3186         mutex_lock(&dev->flow_db->lock);
3187
3188         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3189                 mlx5_del_flow_rules(iter->rule);
3190                 put_flow_table(dev, iter->prio, true);
3191                 list_del(&iter->list);
3192                 kfree(iter);
3193         }
3194
3195         mlx5_del_flow_rules(handler->rule);
3196         put_flow_table(dev, handler->prio, true);
3197         if (handler->ibcounters &&
3198             atomic_read(&handler->ibcounters->usecnt) == 1)
3199                 counters_clear_description(handler->ibcounters);
3200
3201         mutex_unlock(&dev->flow_db->lock);
3202         if (handler->flow_matcher)
3203                 atomic_dec(&handler->flow_matcher->usecnt);
3204         kfree(handler);
3205
3206         return 0;
3207 }
3208
3209 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3210 {
3211         priority *= 2;
3212         if (!dont_trap)
3213                 priority++;
3214         return priority;
3215 }
3216
3217 enum flow_table_type {
3218         MLX5_IB_FT_RX,
3219         MLX5_IB_FT_TX
3220 };
3221
3222 #define MLX5_FS_MAX_TYPES        6
3223 #define MLX5_FS_MAX_ENTRIES      BIT(16)
3224
3225 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3226                                            struct mlx5_ib_flow_prio *prio,
3227                                            int priority,
3228                                            int num_entries, int num_groups,
3229                                            u32 flags)
3230 {
3231         struct mlx5_flow_table *ft;
3232
3233         ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3234                                                  num_entries,
3235                                                  num_groups,
3236                                                  0, flags);
3237         if (IS_ERR(ft))
3238                 return ERR_CAST(ft);
3239
3240         prio->flow_table = ft;
3241         prio->refcount = 0;
3242         return prio;
3243 }
3244
3245 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3246                                                 struct ib_flow_attr *flow_attr,
3247                                                 enum flow_table_type ft_type)
3248 {
3249         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3250         struct mlx5_flow_namespace *ns = NULL;
3251         struct mlx5_ib_flow_prio *prio;
3252         struct mlx5_flow_table *ft;
3253         int max_table_size;
3254         int num_entries;
3255         int num_groups;
3256         bool esw_encap;
3257         u32 flags = 0;
3258         int priority;
3259
3260         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3261                                                        log_max_ft_size));
3262         esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3263                 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3264         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3265                 enum mlx5_flow_namespace_type fn_type;
3266
3267                 if (flow_is_multicast_only(flow_attr) &&
3268                     !dont_trap)
3269                         priority = MLX5_IB_FLOW_MCAST_PRIO;
3270                 else
3271                         priority = ib_prio_to_core_prio(flow_attr->priority,
3272                                                         dont_trap);
3273                 if (ft_type == MLX5_IB_FT_RX) {
3274                         fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3275                         prio = &dev->flow_db->prios[priority];
3276                         if (!dev->is_rep && !esw_encap &&
3277                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3278                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3279                         if (!dev->is_rep && !esw_encap &&
3280                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3281                                         reformat_l3_tunnel_to_l2))
3282                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3283                 } else {
3284                         max_table_size =
3285                                 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3286                                                               log_max_ft_size));
3287                         fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3288                         prio = &dev->flow_db->egress_prios[priority];
3289                         if (!dev->is_rep && !esw_encap &&
3290                             MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3291                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3292                 }
3293                 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3294                 num_entries = MLX5_FS_MAX_ENTRIES;
3295                 num_groups = MLX5_FS_MAX_TYPES;
3296         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3297                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3298                 ns = mlx5_get_flow_namespace(dev->mdev,
3299                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
3300                 build_leftovers_ft_param(&priority,
3301                                          &num_entries,
3302                                          &num_groups);
3303                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3304         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3305                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3306                                         allow_sniffer_and_nic_rx_shared_tir))
3307                         return ERR_PTR(-ENOTSUPP);
3308
3309                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3310                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3311                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3312
3313                 prio = &dev->flow_db->sniffer[ft_type];
3314                 priority = 0;
3315                 num_entries = 1;
3316                 num_groups = 1;
3317         }
3318
3319         if (!ns)
3320                 return ERR_PTR(-ENOTSUPP);
3321
3322         max_table_size = min_t(int, num_entries, max_table_size);
3323
3324         ft = prio->flow_table;
3325         if (!ft)
3326                 return _get_prio(ns, prio, priority, max_table_size, num_groups,
3327                                  flags);
3328
3329         return prio;
3330 }
3331
3332 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3333                             struct mlx5_flow_spec *spec,
3334                             u32 underlay_qpn)
3335 {
3336         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3337                                            spec->match_criteria,
3338                                            misc_parameters);
3339         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3340                                            misc_parameters);
3341
3342         if (underlay_qpn &&
3343             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3344                                       ft_field_support.bth_dst_qp)) {
3345                 MLX5_SET(fte_match_set_misc,
3346                          misc_params_v, bth_dst_qp, underlay_qpn);
3347                 MLX5_SET(fte_match_set_misc,
3348                          misc_params_c, bth_dst_qp, 0xffffff);
3349         }
3350 }
3351
3352 static int read_flow_counters(struct ib_device *ibdev,
3353                               struct mlx5_read_counters_attr *read_attr)
3354 {
3355         struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3356         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3357
3358         return mlx5_fc_query(dev->mdev, fc,
3359                              &read_attr->out[IB_COUNTER_PACKETS],
3360                              &read_attr->out[IB_COUNTER_BYTES]);
3361 }
3362
3363 /* flow counters currently expose two counters packets and bytes */
3364 #define FLOW_COUNTERS_NUM 2
3365 static int counters_set_description(struct ib_counters *counters,
3366                                     enum mlx5_ib_counters_type counters_type,
3367                                     struct mlx5_ib_flow_counters_desc *desc_data,
3368                                     u32 ncounters)
3369 {
3370         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3371         u32 cntrs_max_index = 0;
3372         int i;
3373
3374         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3375                 return -EINVAL;
3376
3377         /* init the fields for the object */
3378         mcounters->type = counters_type;
3379         mcounters->read_counters = read_flow_counters;
3380         mcounters->counters_num = FLOW_COUNTERS_NUM;
3381         mcounters->ncounters = ncounters;
3382         /* each counter entry have both description and index pair */
3383         for (i = 0; i < ncounters; i++) {
3384                 if (desc_data[i].description > IB_COUNTER_BYTES)
3385                         return -EINVAL;
3386
3387                 if (cntrs_max_index <= desc_data[i].index)
3388                         cntrs_max_index = desc_data[i].index + 1;
3389         }
3390
3391         mutex_lock(&mcounters->mcntrs_mutex);
3392         mcounters->counters_data = desc_data;
3393         mcounters->cntrs_max_index = cntrs_max_index;
3394         mutex_unlock(&mcounters->mcntrs_mutex);
3395
3396         return 0;
3397 }
3398
3399 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3400 static int flow_counters_set_data(struct ib_counters *ibcounters,
3401                                   struct mlx5_ib_create_flow *ucmd)
3402 {
3403         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3404         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3405         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3406         bool hw_hndl = false;
3407         int ret = 0;
3408
3409         if (ucmd && ucmd->ncounters_data != 0) {
3410                 cntrs_data = ucmd->data;
3411                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3412                         return -EINVAL;
3413
3414                 desc_data = kcalloc(cntrs_data->ncounters,
3415                                     sizeof(*desc_data),
3416                                     GFP_KERNEL);
3417                 if (!desc_data)
3418                         return  -ENOMEM;
3419
3420                 if (copy_from_user(desc_data,
3421                                    u64_to_user_ptr(cntrs_data->counters_data),
3422                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3423                         ret = -EFAULT;
3424                         goto free;
3425                 }
3426         }
3427
3428         if (!mcounters->hw_cntrs_hndl) {
3429                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3430                         to_mdev(ibcounters->device)->mdev, false);
3431                 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3432                         ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3433                         goto free;
3434                 }
3435                 hw_hndl = true;
3436         }
3437
3438         if (desc_data) {
3439                 /* counters already bound to at least one flow */
3440                 if (mcounters->cntrs_max_index) {
3441                         ret = -EINVAL;
3442                         goto free_hndl;
3443                 }
3444
3445                 ret = counters_set_description(ibcounters,
3446                                                MLX5_IB_COUNTERS_FLOW,
3447                                                desc_data,
3448                                                cntrs_data->ncounters);
3449                 if (ret)
3450                         goto free_hndl;
3451
3452         } else if (!mcounters->cntrs_max_index) {
3453                 /* counters not bound yet, must have udata passed */
3454                 ret = -EINVAL;
3455                 goto free_hndl;
3456         }
3457
3458         return 0;
3459
3460 free_hndl:
3461         if (hw_hndl) {
3462                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3463                                 mcounters->hw_cntrs_hndl);
3464                 mcounters->hw_cntrs_hndl = NULL;
3465         }
3466 free:
3467         kfree(desc_data);
3468         return ret;
3469 }
3470
3471 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3472                                                       struct mlx5_ib_flow_prio *ft_prio,
3473                                                       const struct ib_flow_attr *flow_attr,
3474                                                       struct mlx5_flow_destination *dst,
3475                                                       u32 underlay_qpn,
3476                                                       struct mlx5_ib_create_flow *ucmd)
3477 {
3478         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3479         struct mlx5_ib_flow_handler *handler;
3480         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3481         struct mlx5_flow_spec *spec;
3482         struct mlx5_flow_destination dest_arr[2] = {};
3483         struct mlx5_flow_destination *rule_dst = dest_arr;
3484         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3485         unsigned int spec_index;
3486         u32 prev_type = 0;
3487         int err = 0;
3488         int dest_num = 0;
3489         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3490
3491         if (!is_valid_attr(dev->mdev, flow_attr))
3492                 return ERR_PTR(-EINVAL);
3493
3494         if (dev->is_rep && is_egress)
3495                 return ERR_PTR(-EINVAL);
3496
3497         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3498         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3499         if (!handler || !spec) {
3500                 err = -ENOMEM;
3501                 goto free;
3502         }
3503
3504         INIT_LIST_HEAD(&handler->list);
3505         if (dst) {
3506                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3507                 dest_num++;
3508         }
3509
3510         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3511                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3512                                       spec->match_value,
3513                                       ib_flow, flow_attr, &flow_act,
3514                                       prev_type);
3515                 if (err < 0)
3516                         goto free;
3517
3518                 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3519                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3520         }
3521
3522         if (!flow_is_multicast_only(flow_attr))
3523                 set_underlay_qp(dev, spec, underlay_qpn);
3524
3525         if (dev->is_rep) {
3526                 void *misc;
3527
3528                 if (!dev->port[flow_attr->port - 1].rep) {
3529                         err = -EINVAL;
3530                         goto free;
3531                 }
3532                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3533                                     misc_parameters);
3534                 MLX5_SET(fte_match_set_misc, misc, source_port,
3535                          dev->port[flow_attr->port - 1].rep->vport);
3536                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3537                                     misc_parameters);
3538                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3539         }
3540
3541         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3542
3543         if (is_egress &&
3544             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3545                 err = -EINVAL;
3546                 goto free;
3547         }
3548
3549         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3550                 struct mlx5_ib_mcounters *mcounters;
3551
3552                 err = flow_counters_set_data(flow_act.counters, ucmd);
3553                 if (err)
3554                         goto free;
3555
3556                 mcounters = to_mcounters(flow_act.counters);
3557                 handler->ibcounters = flow_act.counters;
3558                 dest_arr[dest_num].type =
3559                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3560                 dest_arr[dest_num].counter_id =
3561                         mlx5_fc_id(mcounters->hw_cntrs_hndl);
3562                 dest_num++;
3563         }
3564
3565         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3566                 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3567                         rule_dst = NULL;
3568                         dest_num = 0;
3569                 }
3570         } else {
3571                 if (is_egress)
3572                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3573                 else
3574                         flow_act.action |=
3575                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3576                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3577         }
3578
3579         if ((flow_act.flags & FLOW_ACT_HAS_TAG)  &&
3580             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3581              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3582                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3583                              flow_act.flow_tag, flow_attr->type);
3584                 err = -EINVAL;
3585                 goto free;
3586         }
3587         handler->rule = mlx5_add_flow_rules(ft, spec,
3588                                             &flow_act,
3589                                             rule_dst, dest_num);
3590
3591         if (IS_ERR(handler->rule)) {
3592                 err = PTR_ERR(handler->rule);
3593                 goto free;
3594         }
3595
3596         ft_prio->refcount++;
3597         handler->prio = ft_prio;
3598         handler->dev = dev;
3599
3600         ft_prio->flow_table = ft;
3601 free:
3602         if (err && handler) {
3603                 if (handler->ibcounters &&
3604                     atomic_read(&handler->ibcounters->usecnt) == 1)
3605                         counters_clear_description(handler->ibcounters);
3606                 kfree(handler);
3607         }
3608         kvfree(spec);
3609         return err ? ERR_PTR(err) : handler;
3610 }
3611
3612 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3613                                                      struct mlx5_ib_flow_prio *ft_prio,
3614                                                      const struct ib_flow_attr *flow_attr,
3615                                                      struct mlx5_flow_destination *dst)
3616 {
3617         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3618 }
3619
3620 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3621                                                           struct mlx5_ib_flow_prio *ft_prio,
3622                                                           struct ib_flow_attr *flow_attr,
3623                                                           struct mlx5_flow_destination *dst)
3624 {
3625         struct mlx5_ib_flow_handler *handler_dst = NULL;
3626         struct mlx5_ib_flow_handler *handler = NULL;
3627
3628         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3629         if (!IS_ERR(handler)) {
3630                 handler_dst = create_flow_rule(dev, ft_prio,
3631                                                flow_attr, dst);
3632                 if (IS_ERR(handler_dst)) {
3633                         mlx5_del_flow_rules(handler->rule);
3634                         ft_prio->refcount--;
3635                         kfree(handler);
3636                         handler = handler_dst;
3637                 } else {
3638                         list_add(&handler_dst->list, &handler->list);
3639                 }
3640         }
3641
3642         return handler;
3643 }
3644 enum {
3645         LEFTOVERS_MC,
3646         LEFTOVERS_UC,
3647 };
3648
3649 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3650                                                           struct mlx5_ib_flow_prio *ft_prio,
3651                                                           struct ib_flow_attr *flow_attr,
3652                                                           struct mlx5_flow_destination *dst)
3653 {
3654         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3655         struct mlx5_ib_flow_handler *handler = NULL;
3656
3657         static struct {
3658                 struct ib_flow_attr     flow_attr;
3659                 struct ib_flow_spec_eth eth_flow;
3660         } leftovers_specs[] = {
3661                 [LEFTOVERS_MC] = {
3662                         .flow_attr = {
3663                                 .num_of_specs = 1,
3664                                 .size = sizeof(leftovers_specs[0])
3665                         },
3666                         .eth_flow = {
3667                                 .type = IB_FLOW_SPEC_ETH,
3668                                 .size = sizeof(struct ib_flow_spec_eth),
3669                                 .mask = {.dst_mac = {0x1} },
3670                                 .val =  {.dst_mac = {0x1} }
3671                         }
3672                 },
3673                 [LEFTOVERS_UC] = {
3674                         .flow_attr = {
3675                                 .num_of_specs = 1,
3676                                 .size = sizeof(leftovers_specs[0])
3677                         },
3678                         .eth_flow = {
3679                                 .type = IB_FLOW_SPEC_ETH,
3680                                 .size = sizeof(struct ib_flow_spec_eth),
3681                                 .mask = {.dst_mac = {0x1} },
3682                                 .val = {.dst_mac = {} }
3683                         }
3684                 }
3685         };
3686
3687         handler = create_flow_rule(dev, ft_prio,
3688                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3689                                    dst);
3690         if (!IS_ERR(handler) &&
3691             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3692                 handler_ucast = create_flow_rule(dev, ft_prio,
3693                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3694                                                  dst);
3695                 if (IS_ERR(handler_ucast)) {
3696                         mlx5_del_flow_rules(handler->rule);
3697                         ft_prio->refcount--;
3698                         kfree(handler);
3699                         handler = handler_ucast;
3700                 } else {
3701                         list_add(&handler_ucast->list, &handler->list);
3702                 }
3703         }
3704
3705         return handler;
3706 }
3707
3708 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3709                                                         struct mlx5_ib_flow_prio *ft_rx,
3710                                                         struct mlx5_ib_flow_prio *ft_tx,
3711                                                         struct mlx5_flow_destination *dst)
3712 {
3713         struct mlx5_ib_flow_handler *handler_rx;
3714         struct mlx5_ib_flow_handler *handler_tx;
3715         int err;
3716         static const struct ib_flow_attr flow_attr  = {
3717                 .num_of_specs = 0,
3718                 .size = sizeof(flow_attr)
3719         };
3720
3721         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3722         if (IS_ERR(handler_rx)) {
3723                 err = PTR_ERR(handler_rx);
3724                 goto err;
3725         }
3726
3727         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3728         if (IS_ERR(handler_tx)) {
3729                 err = PTR_ERR(handler_tx);
3730                 goto err_tx;
3731         }
3732
3733         list_add(&handler_tx->list, &handler_rx->list);
3734
3735         return handler_rx;
3736
3737 err_tx:
3738         mlx5_del_flow_rules(handler_rx->rule);
3739         ft_rx->refcount--;
3740         kfree(handler_rx);
3741 err:
3742         return ERR_PTR(err);
3743 }
3744
3745 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3746                                            struct ib_flow_attr *flow_attr,
3747                                            int domain,
3748                                            struct ib_udata *udata)
3749 {
3750         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3751         struct mlx5_ib_qp *mqp = to_mqp(qp);
3752         struct mlx5_ib_flow_handler *handler = NULL;
3753         struct mlx5_flow_destination *dst = NULL;
3754         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3755         struct mlx5_ib_flow_prio *ft_prio;
3756         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3757         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3758         size_t min_ucmd_sz, required_ucmd_sz;
3759         int err;
3760         int underlay_qpn;
3761
3762         if (udata && udata->inlen) {
3763                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3764                                 sizeof(ucmd_hdr.reserved);
3765                 if (udata->inlen < min_ucmd_sz)
3766                         return ERR_PTR(-EOPNOTSUPP);
3767
3768                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3769                 if (err)
3770                         return ERR_PTR(err);
3771
3772                 /* currently supports only one counters data */
3773                 if (ucmd_hdr.ncounters_data > 1)
3774                         return ERR_PTR(-EINVAL);
3775
3776                 required_ucmd_sz = min_ucmd_sz +
3777                         sizeof(struct mlx5_ib_flow_counters_data) *
3778                         ucmd_hdr.ncounters_data;
3779                 if (udata->inlen > required_ucmd_sz &&
3780                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3781                                          udata->inlen - required_ucmd_sz))
3782                         return ERR_PTR(-EOPNOTSUPP);
3783
3784                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3785                 if (!ucmd)
3786                         return ERR_PTR(-ENOMEM);
3787
3788                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3789                 if (err)
3790                         goto free_ucmd;
3791         }
3792
3793         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3794                 err = -ENOMEM;
3795                 goto free_ucmd;
3796         }
3797
3798         if (domain != IB_FLOW_DOMAIN_USER ||
3799             flow_attr->port > dev->num_ports ||
3800             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3801                                   IB_FLOW_ATTR_FLAGS_EGRESS))) {
3802                 err = -EINVAL;
3803                 goto free_ucmd;
3804         }
3805
3806         if (is_egress &&
3807             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3808              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3809                 err = -EINVAL;
3810                 goto free_ucmd;
3811         }
3812
3813         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3814         if (!dst) {
3815                 err = -ENOMEM;
3816                 goto free_ucmd;
3817         }
3818
3819         mutex_lock(&dev->flow_db->lock);
3820
3821         ft_prio = get_flow_table(dev, flow_attr,
3822                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3823         if (IS_ERR(ft_prio)) {
3824                 err = PTR_ERR(ft_prio);
3825                 goto unlock;
3826         }
3827         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3828                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3829                 if (IS_ERR(ft_prio_tx)) {
3830                         err = PTR_ERR(ft_prio_tx);
3831                         ft_prio_tx = NULL;
3832                         goto destroy_ft;
3833                 }
3834         }
3835
3836         if (is_egress) {
3837                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3838         } else {
3839                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3840                 if (mqp->flags & MLX5_IB_QP_RSS)
3841                         dst->tir_num = mqp->rss_qp.tirn;
3842                 else
3843                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3844         }
3845
3846         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3847                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3848                         handler = create_dont_trap_rule(dev, ft_prio,
3849                                                         flow_attr, dst);
3850                 } else {
3851                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3852                                         mqp->underlay_qpn : 0;
3853                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3854                                                     dst, underlay_qpn, ucmd);
3855                 }
3856         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3857                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3858                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3859                                                 dst);
3860         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3861                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3862         } else {
3863                 err = -EINVAL;
3864                 goto destroy_ft;
3865         }
3866
3867         if (IS_ERR(handler)) {
3868                 err = PTR_ERR(handler);
3869                 handler = NULL;
3870                 goto destroy_ft;
3871         }
3872
3873         mutex_unlock(&dev->flow_db->lock);
3874         kfree(dst);
3875         kfree(ucmd);
3876
3877         return &handler->ibflow;
3878
3879 destroy_ft:
3880         put_flow_table(dev, ft_prio, false);
3881         if (ft_prio_tx)
3882                 put_flow_table(dev, ft_prio_tx, false);
3883 unlock:
3884         mutex_unlock(&dev->flow_db->lock);
3885         kfree(dst);
3886 free_ucmd:
3887         kfree(ucmd);
3888         return ERR_PTR(err);
3889 }
3890
3891 static struct mlx5_ib_flow_prio *
3892 _get_flow_table(struct mlx5_ib_dev *dev,
3893                 struct mlx5_ib_flow_matcher *fs_matcher,
3894                 bool mcast)
3895 {
3896         struct mlx5_flow_namespace *ns = NULL;
3897         struct mlx5_ib_flow_prio *prio = NULL;
3898         int max_table_size = 0;
3899         bool esw_encap;
3900         u32 flags = 0;
3901         int priority;
3902
3903         if (mcast)
3904                 priority = MLX5_IB_FLOW_MCAST_PRIO;
3905         else
3906                 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3907
3908         esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3909                 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3910         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3911                 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3912                                         log_max_ft_size));
3913                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
3914                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3915                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3916                                               reformat_l3_tunnel_to_l2) &&
3917                     !esw_encap)
3918                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3919         } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3920                 max_table_size = BIT(
3921                         MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
3922                 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
3923                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3924         } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3925                 max_table_size = BIT(
3926                         MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
3927                 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3928                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3929                 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3930                     esw_encap)
3931                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3932                 priority = FDB_BYPASS_PATH;
3933         }
3934
3935         max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
3936
3937         ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3938         if (!ns)
3939                 return ERR_PTR(-ENOTSUPP);
3940
3941         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3942                 prio = &dev->flow_db->prios[priority];
3943         else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
3944                 prio = &dev->flow_db->egress_prios[priority];
3945         else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3946                 prio = &dev->flow_db->fdb;
3947
3948         if (!prio)
3949                 return ERR_PTR(-EINVAL);
3950
3951         if (prio->flow_table)
3952                 return prio;
3953
3954         return _get_prio(ns, prio, priority, max_table_size,
3955                          MLX5_FS_MAX_TYPES, flags);
3956 }
3957
3958 static struct mlx5_ib_flow_handler *
3959 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3960                       struct mlx5_ib_flow_prio *ft_prio,
3961                       struct mlx5_flow_destination *dst,
3962                       struct mlx5_ib_flow_matcher  *fs_matcher,
3963                       struct mlx5_flow_act *flow_act,
3964                       void *cmd_in, int inlen,
3965                       int dst_num)
3966 {
3967         struct mlx5_ib_flow_handler *handler;
3968         struct mlx5_flow_spec *spec;
3969         struct mlx5_flow_table *ft = ft_prio->flow_table;
3970         int err = 0;
3971
3972         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3973         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3974         if (!handler || !spec) {
3975                 err = -ENOMEM;
3976                 goto free;
3977         }
3978
3979         INIT_LIST_HEAD(&handler->list);
3980
3981         memcpy(spec->match_value, cmd_in, inlen);
3982         memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3983                fs_matcher->mask_len);
3984         spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3985
3986         handler->rule = mlx5_add_flow_rules(ft, spec,
3987                                             flow_act, dst, dst_num);
3988
3989         if (IS_ERR(handler->rule)) {
3990                 err = PTR_ERR(handler->rule);
3991                 goto free;
3992         }
3993
3994         ft_prio->refcount++;
3995         handler->prio = ft_prio;
3996         handler->dev = dev;
3997         ft_prio->flow_table = ft;
3998
3999 free:
4000         if (err)
4001                 kfree(handler);
4002         kvfree(spec);
4003         return err ? ERR_PTR(err) : handler;
4004 }
4005
4006 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4007                                 void *match_v)
4008 {
4009         void *match_c;
4010         void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4011         void *dmac, *dmac_mask;
4012         void *ipv4, *ipv4_mask;
4013
4014         if (!(fs_matcher->match_criteria_enable &
4015               (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4016                 return false;
4017
4018         match_c = fs_matcher->matcher_mask.match_params;
4019         match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4020                                            outer_headers);
4021         match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4022                                            outer_headers);
4023
4024         dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4025                             dmac_47_16);
4026         dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4027                                  dmac_47_16);
4028
4029         if (is_multicast_ether_addr(dmac) &&
4030             is_multicast_ether_addr(dmac_mask))
4031                 return true;
4032
4033         ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4034                             dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4035
4036         ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4037                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4038
4039         if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4040             ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4041                 return true;
4042
4043         return false;
4044 }
4045
4046 struct mlx5_ib_flow_handler *
4047 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4048                         struct mlx5_ib_flow_matcher *fs_matcher,
4049                         struct mlx5_flow_act *flow_act,
4050                         u32 counter_id,
4051                         void *cmd_in, int inlen, int dest_id,
4052                         int dest_type)
4053 {
4054         struct mlx5_flow_destination *dst;
4055         struct mlx5_ib_flow_prio *ft_prio;
4056         struct mlx5_ib_flow_handler *handler;
4057         int dst_num = 0;
4058         bool mcast;
4059         int err;
4060
4061         if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4062                 return ERR_PTR(-EOPNOTSUPP);
4063
4064         if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4065                 return ERR_PTR(-ENOMEM);
4066
4067         dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
4068         if (!dst)
4069                 return ERR_PTR(-ENOMEM);
4070
4071         mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4072         mutex_lock(&dev->flow_db->lock);
4073
4074         ft_prio = _get_flow_table(dev, fs_matcher, mcast);
4075         if (IS_ERR(ft_prio)) {
4076                 err = PTR_ERR(ft_prio);
4077                 goto unlock;
4078         }
4079
4080         if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
4081                 dst[dst_num].type = dest_type;
4082                 dst[dst_num].tir_num = dest_id;
4083                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4084         } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
4085                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4086                 dst[dst_num].ft_num = dest_id;
4087                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4088         } else {
4089                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
4090                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
4091         }
4092
4093         dst_num++;
4094
4095         if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4096                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4097                 dst[dst_num].counter_id = counter_id;
4098                 dst_num++;
4099         }
4100
4101         handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
4102                                         cmd_in, inlen, dst_num);
4103
4104         if (IS_ERR(handler)) {
4105                 err = PTR_ERR(handler);
4106                 goto destroy_ft;
4107         }
4108
4109         mutex_unlock(&dev->flow_db->lock);
4110         atomic_inc(&fs_matcher->usecnt);
4111         handler->flow_matcher = fs_matcher;
4112
4113         kfree(dst);
4114
4115         return handler;
4116
4117 destroy_ft:
4118         put_flow_table(dev, ft_prio, false);
4119 unlock:
4120         mutex_unlock(&dev->flow_db->lock);
4121         kfree(dst);
4122
4123         return ERR_PTR(err);
4124 }
4125
4126 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4127 {
4128         u32 flags = 0;
4129
4130         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4131                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4132
4133         return flags;
4134 }
4135
4136 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4137 static struct ib_flow_action *
4138 mlx5_ib_create_flow_action_esp(struct ib_device *device,
4139                                const struct ib_flow_action_attrs_esp *attr,
4140                                struct uverbs_attr_bundle *attrs)
4141 {
4142         struct mlx5_ib_dev *mdev = to_mdev(device);
4143         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4144         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4145         struct mlx5_ib_flow_action *action;
4146         u64 action_flags;
4147         u64 flags;
4148         int err = 0;
4149
4150         err = uverbs_get_flags64(
4151                 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4152                 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4153         if (err)
4154                 return ERR_PTR(err);
4155
4156         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4157
4158         /* We current only support a subset of the standard features. Only a
4159          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4160          * (with overlap). Full offload mode isn't supported.
4161          */
4162         if (!attr->keymat || attr->replay || attr->encap ||
4163             attr->spi || attr->seq || attr->tfc_pad ||
4164             attr->hard_limit_pkts ||
4165             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4166                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4167                 return ERR_PTR(-EOPNOTSUPP);
4168
4169         if (attr->keymat->protocol !=
4170             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4171                 return ERR_PTR(-EOPNOTSUPP);
4172
4173         aes_gcm = &attr->keymat->keymat.aes_gcm;
4174
4175         if (aes_gcm->icv_len != 16 ||
4176             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4177                 return ERR_PTR(-EOPNOTSUPP);
4178
4179         action = kmalloc(sizeof(*action), GFP_KERNEL);
4180         if (!action)
4181                 return ERR_PTR(-ENOMEM);
4182
4183         action->esp_aes_gcm.ib_flags = attr->flags;
4184         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4185                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4186         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4187         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4188                sizeof(accel_attrs.keymat.aes_gcm.salt));
4189         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4190                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4191         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4192         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4193         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4194
4195         accel_attrs.esn = attr->esn;
4196         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4197                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4198         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4199                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4200
4201         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4202                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4203
4204         action->esp_aes_gcm.ctx =
4205                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4206         if (IS_ERR(action->esp_aes_gcm.ctx)) {
4207                 err = PTR_ERR(action->esp_aes_gcm.ctx);
4208                 goto err_parse;
4209         }
4210
4211         action->esp_aes_gcm.ib_flags = attr->flags;
4212
4213         return &action->ib_action;
4214
4215 err_parse:
4216         kfree(action);
4217         return ERR_PTR(err);
4218 }
4219
4220 static int
4221 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4222                                const struct ib_flow_action_attrs_esp *attr,
4223                                struct uverbs_attr_bundle *attrs)
4224 {
4225         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4226         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4227         int err = 0;
4228
4229         if (attr->keymat || attr->replay || attr->encap ||
4230             attr->spi || attr->seq || attr->tfc_pad ||
4231             attr->hard_limit_pkts ||
4232             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4233                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4234                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4235                 return -EOPNOTSUPP;
4236
4237         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4238          * be modified.
4239          */
4240         if (!(maction->esp_aes_gcm.ib_flags &
4241               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4242             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4243                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4244                 return -EINVAL;
4245
4246         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4247                sizeof(accel_attrs));
4248
4249         accel_attrs.esn = attr->esn;
4250         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4251                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4252         else
4253                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4254
4255         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4256                                          &accel_attrs);
4257         if (err)
4258                 return err;
4259
4260         maction->esp_aes_gcm.ib_flags &=
4261                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4262         maction->esp_aes_gcm.ib_flags |=
4263                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4264
4265         return 0;
4266 }
4267
4268 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4269 {
4270         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4271
4272         switch (action->type) {
4273         case IB_FLOW_ACTION_ESP:
4274                 /*
4275                  * We only support aes_gcm by now, so we implicitly know this is
4276                  * the underline crypto.
4277                  */
4278                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4279                 break;
4280         case IB_FLOW_ACTION_UNSPECIFIED:
4281                 mlx5_ib_destroy_flow_action_raw(maction);
4282                 break;
4283         default:
4284                 WARN_ON(true);
4285                 break;
4286         }
4287
4288         kfree(maction);
4289         return 0;
4290 }
4291
4292 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4293 {
4294         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4295         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4296         int err;
4297         u16 uid;
4298
4299         uid = ibqp->pd ?
4300                 to_mpd(ibqp->pd)->uid : 0;
4301
4302         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4303                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4304                 return -EOPNOTSUPP;
4305         }
4306
4307         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4308         if (err)
4309                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4310                              ibqp->qp_num, gid->raw);
4311
4312         return err;
4313 }
4314
4315 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4316 {
4317         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4318         int err;
4319         u16 uid;
4320
4321         uid = ibqp->pd ?
4322                 to_mpd(ibqp->pd)->uid : 0;
4323         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4324         if (err)
4325                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4326                              ibqp->qp_num, gid->raw);
4327
4328         return err;
4329 }
4330
4331 static int init_node_data(struct mlx5_ib_dev *dev)
4332 {
4333         int err;
4334
4335         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4336         if (err)
4337                 return err;
4338
4339         dev->mdev->rev_id = dev->mdev->pdev->revision;
4340
4341         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4342 }
4343
4344 static ssize_t fw_pages_show(struct device *device,
4345                              struct device_attribute *attr, char *buf)
4346 {
4347         struct mlx5_ib_dev *dev =
4348                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4349
4350         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4351 }
4352 static DEVICE_ATTR_RO(fw_pages);
4353
4354 static ssize_t reg_pages_show(struct device *device,
4355                               struct device_attribute *attr, char *buf)
4356 {
4357         struct mlx5_ib_dev *dev =
4358                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4359
4360         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4361 }
4362 static DEVICE_ATTR_RO(reg_pages);
4363
4364 static ssize_t hca_type_show(struct device *device,
4365                              struct device_attribute *attr, char *buf)
4366 {
4367         struct mlx5_ib_dev *dev =
4368                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4369
4370         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4371 }
4372 static DEVICE_ATTR_RO(hca_type);
4373
4374 static ssize_t hw_rev_show(struct device *device,
4375                            struct device_attribute *attr, char *buf)
4376 {
4377         struct mlx5_ib_dev *dev =
4378                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4379
4380         return sprintf(buf, "%x\n", dev->mdev->rev_id);
4381 }
4382 static DEVICE_ATTR_RO(hw_rev);
4383
4384 static ssize_t board_id_show(struct device *device,
4385                              struct device_attribute *attr, char *buf)
4386 {
4387         struct mlx5_ib_dev *dev =
4388                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4389
4390         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4391                        dev->mdev->board_id);
4392 }
4393 static DEVICE_ATTR_RO(board_id);
4394
4395 static struct attribute *mlx5_class_attributes[] = {
4396         &dev_attr_hw_rev.attr,
4397         &dev_attr_hca_type.attr,
4398         &dev_attr_board_id.attr,
4399         &dev_attr_fw_pages.attr,
4400         &dev_attr_reg_pages.attr,
4401         NULL,
4402 };
4403
4404 static const struct attribute_group mlx5_attr_group = {
4405         .attrs = mlx5_class_attributes,
4406 };
4407
4408 static void pkey_change_handler(struct work_struct *work)
4409 {
4410         struct mlx5_ib_port_resources *ports =
4411                 container_of(work, struct mlx5_ib_port_resources,
4412                              pkey_change_work);
4413
4414         mutex_lock(&ports->devr->mutex);
4415         mlx5_ib_gsi_pkey_change(ports->gsi);
4416         mutex_unlock(&ports->devr->mutex);
4417 }
4418
4419 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4420 {
4421         struct mlx5_ib_qp *mqp;
4422         struct mlx5_ib_cq *send_mcq, *recv_mcq;
4423         struct mlx5_core_cq *mcq;
4424         struct list_head cq_armed_list;
4425         unsigned long flags_qp;
4426         unsigned long flags_cq;
4427         unsigned long flags;
4428
4429         INIT_LIST_HEAD(&cq_armed_list);
4430
4431         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4432         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4433         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4434                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4435                 if (mqp->sq.tail != mqp->sq.head) {
4436                         send_mcq = to_mcq(mqp->ibqp.send_cq);
4437                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
4438                         if (send_mcq->mcq.comp &&
4439                             mqp->ibqp.send_cq->comp_handler) {
4440                                 if (!send_mcq->mcq.reset_notify_added) {
4441                                         send_mcq->mcq.reset_notify_added = 1;
4442                                         list_add_tail(&send_mcq->mcq.reset_notify,
4443                                                       &cq_armed_list);
4444                                 }
4445                         }
4446                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4447                 }
4448                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4449                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4450                 /* no handling is needed for SRQ */
4451                 if (!mqp->ibqp.srq) {
4452                         if (mqp->rq.tail != mqp->rq.head) {
4453                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4454                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4455                                 if (recv_mcq->mcq.comp &&
4456                                     mqp->ibqp.recv_cq->comp_handler) {
4457                                         if (!recv_mcq->mcq.reset_notify_added) {
4458                                                 recv_mcq->mcq.reset_notify_added = 1;
4459                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
4460                                                               &cq_armed_list);
4461                                         }
4462                                 }
4463                                 spin_unlock_irqrestore(&recv_mcq->lock,
4464                                                        flags_cq);
4465                         }
4466                 }
4467                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4468         }
4469         /*At that point all inflight post send were put to be executed as of we
4470          * lock/unlock above locks Now need to arm all involved CQs.
4471          */
4472         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4473                 mcq->comp(mcq);
4474         }
4475         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4476 }
4477
4478 static void delay_drop_handler(struct work_struct *work)
4479 {
4480         int err;
4481         struct mlx5_ib_delay_drop *delay_drop =
4482                 container_of(work, struct mlx5_ib_delay_drop,
4483                              delay_drop_work);
4484
4485         atomic_inc(&delay_drop->events_cnt);
4486
4487         mutex_lock(&delay_drop->lock);
4488         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4489                                        delay_drop->timeout);
4490         if (err) {
4491                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4492                              delay_drop->timeout);
4493                 delay_drop->activate = false;
4494         }
4495         mutex_unlock(&delay_drop->lock);
4496 }
4497
4498 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4499                                  struct ib_event *ibev)
4500 {
4501         u8 port = (eqe->data.port.port >> 4) & 0xf;
4502
4503         switch (eqe->sub_type) {
4504         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4505                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4506                                             IB_LINK_LAYER_ETHERNET)
4507                         schedule_work(&ibdev->delay_drop.delay_drop_work);
4508                 break;
4509         default: /* do nothing */
4510                 return;
4511         }
4512 }
4513
4514 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4515                               struct ib_event *ibev)
4516 {
4517         u8 port = (eqe->data.port.port >> 4) & 0xf;
4518
4519         ibev->element.port_num = port;
4520
4521         switch (eqe->sub_type) {
4522         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4523         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4524         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4525                 /* In RoCE, port up/down events are handled in
4526                  * mlx5_netdev_event().
4527                  */
4528                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4529                                             IB_LINK_LAYER_ETHERNET)
4530                         return -EINVAL;
4531
4532                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4533                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4534                 break;
4535
4536         case MLX5_PORT_CHANGE_SUBTYPE_LID:
4537                 ibev->event = IB_EVENT_LID_CHANGE;
4538                 break;
4539
4540         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4541                 ibev->event = IB_EVENT_PKEY_CHANGE;
4542                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4543                 break;
4544
4545         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4546                 ibev->event = IB_EVENT_GID_CHANGE;
4547                 break;
4548
4549         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4550                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4551                 break;
4552         default:
4553                 return -EINVAL;
4554         }
4555
4556         return 0;
4557 }
4558
4559 static void mlx5_ib_handle_event(struct work_struct *_work)
4560 {
4561         struct mlx5_ib_event_work *work =
4562                 container_of(_work, struct mlx5_ib_event_work, work);
4563         struct mlx5_ib_dev *ibdev;
4564         struct ib_event ibev;
4565         bool fatal = false;
4566
4567         if (work->is_slave) {
4568                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4569                 if (!ibdev)
4570                         goto out;
4571         } else {
4572                 ibdev = work->dev;
4573         }
4574
4575         switch (work->event) {
4576         case MLX5_DEV_EVENT_SYS_ERROR:
4577                 ibev.event = IB_EVENT_DEVICE_FATAL;
4578                 mlx5_ib_handle_internal_error(ibdev);
4579                 ibev.element.port_num  = (u8)(unsigned long)work->param;
4580                 fatal = true;
4581                 break;
4582         case MLX5_EVENT_TYPE_PORT_CHANGE:
4583                 if (handle_port_change(ibdev, work->param, &ibev))
4584                         goto out;
4585                 break;
4586         case MLX5_EVENT_TYPE_GENERAL_EVENT:
4587                 handle_general_event(ibdev, work->param, &ibev);
4588                 /* fall through */
4589         default:
4590                 goto out;
4591         }
4592
4593         ibev.device = &ibdev->ib_dev;
4594
4595         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4596                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
4597                 goto out;
4598         }
4599
4600         if (ibdev->ib_active)
4601                 ib_dispatch_event(&ibev);
4602
4603         if (fatal)
4604                 ibdev->ib_active = false;
4605 out:
4606         kfree(work);
4607 }
4608
4609 static int mlx5_ib_event(struct notifier_block *nb,
4610                          unsigned long event, void *param)
4611 {
4612         struct mlx5_ib_event_work *work;
4613
4614         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4615         if (!work)
4616                 return NOTIFY_DONE;
4617
4618         INIT_WORK(&work->work, mlx5_ib_handle_event);
4619         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4620         work->is_slave = false;
4621         work->param = param;
4622         work->event = event;
4623
4624         queue_work(mlx5_ib_event_wq, &work->work);
4625
4626         return NOTIFY_OK;
4627 }
4628
4629 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4630                                     unsigned long event, void *param)
4631 {
4632         struct mlx5_ib_event_work *work;
4633
4634         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4635         if (!work)
4636                 return NOTIFY_DONE;
4637
4638         INIT_WORK(&work->work, mlx5_ib_handle_event);
4639         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4640         work->is_slave = true;
4641         work->param = param;
4642         work->event = event;
4643         queue_work(mlx5_ib_event_wq, &work->work);
4644
4645         return NOTIFY_OK;
4646 }
4647
4648 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4649 {
4650         struct mlx5_hca_vport_context vport_ctx;
4651         int err;
4652         int port;
4653
4654         for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
4655                 dev->mdev->port_caps[port - 1].has_smi = false;
4656                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4657                     MLX5_CAP_PORT_TYPE_IB) {
4658                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4659                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4660                                                                    port, 0,
4661                                                                    &vport_ctx);
4662                                 if (err) {
4663                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4664                                                     port, err);
4665                                         return err;
4666                                 }
4667                                 dev->mdev->port_caps[port - 1].has_smi =
4668                                         vport_ctx.has_smi;
4669                         } else {
4670                                 dev->mdev->port_caps[port - 1].has_smi = true;
4671                         }
4672                 }
4673         }
4674         return 0;
4675 }
4676
4677 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4678 {
4679         int port;
4680
4681         for (port = 1; port <= dev->num_ports; port++)
4682                 mlx5_query_ext_port_caps(dev, port);
4683 }
4684
4685 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4686 {
4687         struct ib_device_attr *dprops = NULL;
4688         struct ib_port_attr *pprops = NULL;
4689         int err = -ENOMEM;
4690         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4691
4692         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4693         if (!pprops)
4694                 goto out;
4695
4696         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4697         if (!dprops)
4698                 goto out;
4699
4700         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4701         if (err) {
4702                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4703                 goto out;
4704         }
4705
4706         memset(pprops, 0, sizeof(*pprops));
4707         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4708         if (err) {
4709                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4710                              port, err);
4711                 goto out;
4712         }
4713
4714         dev->mdev->port_caps[port - 1].pkey_table_len =
4715                                         dprops->max_pkeys;
4716         dev->mdev->port_caps[port - 1].gid_table_len =
4717                                         pprops->gid_tbl_len;
4718         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4719                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4720
4721 out:
4722         kfree(pprops);
4723         kfree(dprops);
4724
4725         return err;
4726 }
4727
4728 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4729 {
4730         /* For representors use port 1, is this is the only native
4731          * port
4732          */
4733         if (dev->is_rep)
4734                 return __get_port_caps(dev, 1);
4735         return __get_port_caps(dev, port);
4736 }
4737
4738 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4739 {
4740         int err;
4741
4742         err = mlx5_mr_cache_cleanup(dev);
4743         if (err)
4744                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4745
4746         if (dev->umrc.qp)
4747                 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4748         if (dev->umrc.cq)
4749                 ib_free_cq(dev->umrc.cq);
4750         if (dev->umrc.pd)
4751                 ib_dealloc_pd(dev->umrc.pd);
4752 }
4753
4754 enum {
4755         MAX_UMR_WR = 128,
4756 };
4757
4758 static int create_umr_res(struct mlx5_ib_dev *dev)
4759 {
4760         struct ib_qp_init_attr *init_attr = NULL;
4761         struct ib_qp_attr *attr = NULL;
4762         struct ib_pd *pd;
4763         struct ib_cq *cq;
4764         struct ib_qp *qp;
4765         int ret;
4766
4767         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4768         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4769         if (!attr || !init_attr) {
4770                 ret = -ENOMEM;
4771                 goto error_0;
4772         }
4773
4774         pd = ib_alloc_pd(&dev->ib_dev, 0);
4775         if (IS_ERR(pd)) {
4776                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4777                 ret = PTR_ERR(pd);
4778                 goto error_0;
4779         }
4780
4781         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4782         if (IS_ERR(cq)) {
4783                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4784                 ret = PTR_ERR(cq);
4785                 goto error_2;
4786         }
4787
4788         init_attr->send_cq = cq;
4789         init_attr->recv_cq = cq;
4790         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4791         init_attr->cap.max_send_wr = MAX_UMR_WR;
4792         init_attr->cap.max_send_sge = 1;
4793         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4794         init_attr->port_num = 1;
4795         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4796         if (IS_ERR(qp)) {
4797                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4798                 ret = PTR_ERR(qp);
4799                 goto error_3;
4800         }
4801         qp->device     = &dev->ib_dev;
4802         qp->real_qp    = qp;
4803         qp->uobject    = NULL;
4804         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4805         qp->send_cq    = init_attr->send_cq;
4806         qp->recv_cq    = init_attr->recv_cq;
4807
4808         attr->qp_state = IB_QPS_INIT;
4809         attr->port_num = 1;
4810         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4811                                 IB_QP_PORT, NULL);
4812         if (ret) {
4813                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4814                 goto error_4;
4815         }
4816
4817         memset(attr, 0, sizeof(*attr));
4818         attr->qp_state = IB_QPS_RTR;
4819         attr->path_mtu = IB_MTU_256;
4820
4821         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4822         if (ret) {
4823                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4824                 goto error_4;
4825         }
4826
4827         memset(attr, 0, sizeof(*attr));
4828         attr->qp_state = IB_QPS_RTS;
4829         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4830         if (ret) {
4831                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4832                 goto error_4;
4833         }
4834
4835         dev->umrc.qp = qp;
4836         dev->umrc.cq = cq;
4837         dev->umrc.pd = pd;
4838
4839         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4840         ret = mlx5_mr_cache_init(dev);
4841         if (ret) {
4842                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4843                 goto error_4;
4844         }
4845
4846         kfree(attr);
4847         kfree(init_attr);
4848
4849         return 0;
4850
4851 error_4:
4852         mlx5_ib_destroy_qp(qp, NULL);
4853         dev->umrc.qp = NULL;
4854
4855 error_3:
4856         ib_free_cq(cq);
4857         dev->umrc.cq = NULL;
4858
4859 error_2:
4860         ib_dealloc_pd(pd);
4861         dev->umrc.pd = NULL;
4862
4863 error_0:
4864         kfree(attr);
4865         kfree(init_attr);
4866         return ret;
4867 }
4868
4869 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4870 {
4871         switch (umr_fence_cap) {
4872         case MLX5_CAP_UMR_FENCE_NONE:
4873                 return MLX5_FENCE_MODE_NONE;
4874         case MLX5_CAP_UMR_FENCE_SMALL:
4875                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4876         default:
4877                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4878         }
4879 }
4880
4881 static int create_dev_resources(struct mlx5_ib_resources *devr)
4882 {
4883         struct ib_srq_init_attr attr;
4884         struct mlx5_ib_dev *dev;
4885         struct ib_device *ibdev;
4886         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4887         int port;
4888         int ret = 0;
4889
4890         dev = container_of(devr, struct mlx5_ib_dev, devr);
4891         ibdev = &dev->ib_dev;
4892
4893         mutex_init(&devr->mutex);
4894
4895         devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4896         if (!devr->p0)
4897                 return -ENOMEM;
4898
4899         devr->p0->device  = ibdev;
4900         devr->p0->uobject = NULL;
4901         atomic_set(&devr->p0->usecnt, 0);
4902
4903         ret = mlx5_ib_alloc_pd(devr->p0, NULL);
4904         if (ret)
4905                 goto error0;
4906
4907         devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4908         if (!devr->c0) {
4909                 ret = -ENOMEM;
4910                 goto error1;
4911         }
4912
4913         devr->c0->device = &dev->ib_dev;
4914         atomic_set(&devr->c0->usecnt, 0);
4915
4916         ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4917         if (ret)
4918                 goto err_create_cq;
4919
4920         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4921         if (IS_ERR(devr->x0)) {
4922                 ret = PTR_ERR(devr->x0);
4923                 goto error2;
4924         }
4925         devr->x0->device = &dev->ib_dev;
4926         devr->x0->inode = NULL;
4927         atomic_set(&devr->x0->usecnt, 0);
4928         mutex_init(&devr->x0->tgt_qp_mutex);
4929         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4930
4931         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4932         if (IS_ERR(devr->x1)) {
4933                 ret = PTR_ERR(devr->x1);
4934                 goto error3;
4935         }
4936         devr->x1->device = &dev->ib_dev;
4937         devr->x1->inode = NULL;
4938         atomic_set(&devr->x1->usecnt, 0);
4939         mutex_init(&devr->x1->tgt_qp_mutex);
4940         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4941
4942         memset(&attr, 0, sizeof(attr));
4943         attr.attr.max_sge = 1;
4944         attr.attr.max_wr = 1;
4945         attr.srq_type = IB_SRQT_XRC;
4946         attr.ext.cq = devr->c0;
4947         attr.ext.xrc.xrcd = devr->x0;
4948
4949         devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4950         if (!devr->s0) {
4951                 ret = -ENOMEM;
4952                 goto error4;
4953         }
4954
4955         devr->s0->device        = &dev->ib_dev;
4956         devr->s0->pd            = devr->p0;
4957         devr->s0->srq_type      = IB_SRQT_XRC;
4958         devr->s0->ext.xrc.xrcd  = devr->x0;
4959         devr->s0->ext.cq        = devr->c0;
4960         ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
4961         if (ret)
4962                 goto err_create;
4963
4964         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4965         atomic_inc(&devr->s0->ext.cq->usecnt);
4966         atomic_inc(&devr->p0->usecnt);
4967         atomic_set(&devr->s0->usecnt, 0);
4968
4969         memset(&attr, 0, sizeof(attr));
4970         attr.attr.max_sge = 1;
4971         attr.attr.max_wr = 1;
4972         attr.srq_type = IB_SRQT_BASIC;
4973         devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4974         if (!devr->s1) {
4975                 ret = -ENOMEM;
4976                 goto error5;
4977         }
4978
4979         devr->s1->device        = &dev->ib_dev;
4980         devr->s1->pd            = devr->p0;
4981         devr->s1->srq_type      = IB_SRQT_BASIC;
4982         devr->s1->ext.cq        = devr->c0;
4983
4984         ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
4985         if (ret)
4986                 goto error6;
4987
4988         atomic_inc(&devr->p0->usecnt);
4989         atomic_set(&devr->s1->usecnt, 0);
4990
4991         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4992                 INIT_WORK(&devr->ports[port].pkey_change_work,
4993                           pkey_change_handler);
4994                 devr->ports[port].devr = devr;
4995         }
4996
4997         return 0;
4998
4999 error6:
5000         kfree(devr->s1);
5001 error5:
5002         mlx5_ib_destroy_srq(devr->s0, NULL);
5003 err_create:
5004         kfree(devr->s0);
5005 error4:
5006         mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5007 error3:
5008         mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5009 error2:
5010         mlx5_ib_destroy_cq(devr->c0, NULL);
5011 err_create_cq:
5012         kfree(devr->c0);
5013 error1:
5014         mlx5_ib_dealloc_pd(devr->p0, NULL);
5015 error0:
5016         kfree(devr->p0);
5017         return ret;
5018 }
5019
5020 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5021 {
5022         int port;
5023
5024         mlx5_ib_destroy_srq(devr->s1, NULL);
5025         kfree(devr->s1);
5026         mlx5_ib_destroy_srq(devr->s0, NULL);
5027         kfree(devr->s0);
5028         mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5029         mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5030         mlx5_ib_destroy_cq(devr->c0, NULL);
5031         kfree(devr->c0);
5032         mlx5_ib_dealloc_pd(devr->p0, NULL);
5033         kfree(devr->p0);
5034
5035         /* Make sure no change P_Key work items are still executing */
5036         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
5037                 cancel_work_sync(&devr->ports[port].pkey_change_work);
5038 }
5039
5040 static u32 get_core_cap_flags(struct ib_device *ibdev,
5041                               struct mlx5_hca_vport_context *rep)
5042 {
5043         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5044         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5045         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5046         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
5047         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
5048         u32 ret = 0;
5049
5050         if (rep->grh_required)
5051                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5052
5053         if (ll == IB_LINK_LAYER_INFINIBAND)
5054                 return ret | RDMA_CORE_PORT_IBA_IB;
5055
5056         if (raw_support)
5057                 ret |= RDMA_CORE_PORT_RAW_PACKET;
5058
5059         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
5060                 return ret;
5061
5062         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
5063                 return ret;
5064
5065         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5066                 ret |= RDMA_CORE_PORT_IBA_ROCE;
5067
5068         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5069                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5070
5071         return ret;
5072 }
5073
5074 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5075                                struct ib_port_immutable *immutable)
5076 {
5077         struct ib_port_attr attr;
5078         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5079         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
5080         struct mlx5_hca_vport_context rep = {0};
5081         int err;
5082
5083         err = ib_query_port(ibdev, port_num, &attr);
5084         if (err)
5085                 return err;
5086
5087         if (ll == IB_LINK_LAYER_INFINIBAND) {
5088                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5089                                                    &rep);
5090                 if (err)
5091                         return err;
5092         }
5093
5094         immutable->pkey_tbl_len = attr.pkey_tbl_len;
5095         immutable->gid_tbl_len = attr.gid_tbl_len;
5096         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
5097         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5098                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
5099
5100         return 0;
5101 }
5102
5103 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5104                                    struct ib_port_immutable *immutable)
5105 {
5106         struct ib_port_attr attr;
5107         int err;
5108
5109         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5110
5111         err = ib_query_port(ibdev, port_num, &attr);
5112         if (err)
5113                 return err;
5114
5115         immutable->pkey_tbl_len = attr.pkey_tbl_len;
5116         immutable->gid_tbl_len = attr.gid_tbl_len;
5117         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5118
5119         return 0;
5120 }
5121
5122 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
5123 {
5124         struct mlx5_ib_dev *dev =
5125                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
5126         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5127                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5128                  fw_rev_sub(dev->mdev));
5129 }
5130
5131 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
5132 {
5133         struct mlx5_core_dev *mdev = dev->mdev;
5134         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5135                                                                  MLX5_FLOW_NAMESPACE_LAG);
5136         struct mlx5_flow_table *ft;
5137         int err;
5138
5139         if (!ns || !mlx5_lag_is_roce(mdev))
5140                 return 0;
5141
5142         err = mlx5_cmd_create_vport_lag(mdev);
5143         if (err)
5144                 return err;
5145
5146         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5147         if (IS_ERR(ft)) {
5148                 err = PTR_ERR(ft);
5149                 goto err_destroy_vport_lag;
5150         }
5151
5152         dev->flow_db->lag_demux_ft = ft;
5153         dev->lag_active = true;
5154         return 0;
5155
5156 err_destroy_vport_lag:
5157         mlx5_cmd_destroy_vport_lag(mdev);
5158         return err;
5159 }
5160
5161 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
5162 {
5163         struct mlx5_core_dev *mdev = dev->mdev;
5164
5165         if (dev->lag_active) {
5166                 dev->lag_active = false;
5167
5168                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5169                 dev->flow_db->lag_demux_ft = NULL;
5170
5171                 mlx5_cmd_destroy_vport_lag(mdev);
5172         }
5173 }
5174
5175 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5176 {
5177         int err;
5178
5179         dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5180         err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
5181         if (err) {
5182                 dev->port[port_num].roce.nb.notifier_call = NULL;
5183                 return err;
5184         }
5185
5186         return 0;
5187 }
5188
5189 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5190 {
5191         if (dev->port[port_num].roce.nb.notifier_call) {
5192                 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5193                 dev->port[port_num].roce.nb.notifier_call = NULL;
5194         }
5195 }
5196
5197 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
5198 {
5199         int err;
5200
5201         if (MLX5_CAP_GEN(dev->mdev, roce)) {
5202                 err = mlx5_nic_vport_enable_roce(dev->mdev);
5203                 if (err)
5204                         return err;
5205         }
5206
5207         err = mlx5_eth_lag_init(dev);
5208         if (err)
5209                 goto err_disable_roce;
5210
5211         return 0;
5212
5213 err_disable_roce:
5214         if (MLX5_CAP_GEN(dev->mdev, roce))
5215                 mlx5_nic_vport_disable_roce(dev->mdev);
5216
5217         return err;
5218 }
5219
5220 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
5221 {
5222         mlx5_eth_lag_cleanup(dev);
5223         if (MLX5_CAP_GEN(dev->mdev, roce))
5224                 mlx5_nic_vport_disable_roce(dev->mdev);
5225 }
5226
5227 struct mlx5_ib_counter {
5228         const char *name;
5229         size_t offset;
5230 };
5231
5232 #define INIT_Q_COUNTER(_name)           \
5233         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5234
5235 static const struct mlx5_ib_counter basic_q_cnts[] = {
5236         INIT_Q_COUNTER(rx_write_requests),
5237         INIT_Q_COUNTER(rx_read_requests),
5238         INIT_Q_COUNTER(rx_atomic_requests),
5239         INIT_Q_COUNTER(out_of_buffer),
5240 };
5241
5242 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
5243         INIT_Q_COUNTER(out_of_sequence),
5244 };
5245
5246 static const struct mlx5_ib_counter retrans_q_cnts[] = {
5247         INIT_Q_COUNTER(duplicate_request),
5248         INIT_Q_COUNTER(rnr_nak_retry_err),
5249         INIT_Q_COUNTER(packet_seq_err),
5250         INIT_Q_COUNTER(implied_nak_seq_err),
5251         INIT_Q_COUNTER(local_ack_timeout_err),
5252 };
5253
5254 #define INIT_CONG_COUNTER(_name)                \
5255         { .name = #_name, .offset =     \
5256                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5257
5258 static const struct mlx5_ib_counter cong_cnts[] = {
5259         INIT_CONG_COUNTER(rp_cnp_ignored),
5260         INIT_CONG_COUNTER(rp_cnp_handled),
5261         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5262         INIT_CONG_COUNTER(np_cnp_sent),
5263 };
5264
5265 static const struct mlx5_ib_counter extended_err_cnts[] = {
5266         INIT_Q_COUNTER(resp_local_length_error),
5267         INIT_Q_COUNTER(resp_cqe_error),
5268         INIT_Q_COUNTER(req_cqe_error),
5269         INIT_Q_COUNTER(req_remote_invalid_request),
5270         INIT_Q_COUNTER(req_remote_access_errors),
5271         INIT_Q_COUNTER(resp_remote_access_errors),
5272         INIT_Q_COUNTER(resp_cqe_flush_error),
5273         INIT_Q_COUNTER(req_cqe_flush_error),
5274 };
5275
5276 #define INIT_EXT_PPCNT_COUNTER(_name)           \
5277         { .name = #_name, .offset =     \
5278         MLX5_BYTE_OFF(ppcnt_reg, \
5279                       counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5280
5281 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5282         INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5283 };
5284
5285 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
5286 {
5287         int i;
5288
5289         for (i = 0; i < dev->num_ports; i++) {
5290                 if (dev->port[i].cnts.set_id_valid)
5291                         mlx5_core_dealloc_q_counter(dev->mdev,
5292                                                     dev->port[i].cnts.set_id);
5293                 kfree(dev->port[i].cnts.names);
5294                 kfree(dev->port[i].cnts.offsets);
5295         }
5296 }
5297
5298 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5299                                     struct mlx5_ib_counters *cnts)
5300 {
5301         u32 num_counters;
5302
5303         num_counters = ARRAY_SIZE(basic_q_cnts);
5304
5305         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5306                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5307
5308         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5309                 num_counters += ARRAY_SIZE(retrans_q_cnts);
5310
5311         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5312                 num_counters += ARRAY_SIZE(extended_err_cnts);
5313
5314         cnts->num_q_counters = num_counters;
5315
5316         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5317                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5318                 num_counters += ARRAY_SIZE(cong_cnts);
5319         }
5320         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5321                 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5322                 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5323         }
5324         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5325         if (!cnts->names)
5326                 return -ENOMEM;
5327
5328         cnts->offsets = kcalloc(num_counters,
5329                                 sizeof(cnts->offsets), GFP_KERNEL);
5330         if (!cnts->offsets)
5331                 goto err_names;
5332
5333         return 0;
5334
5335 err_names:
5336         kfree(cnts->names);
5337         cnts->names = NULL;
5338         return -ENOMEM;
5339 }
5340
5341 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5342                                   const char **names,
5343                                   size_t *offsets)
5344 {
5345         int i;
5346         int j = 0;
5347
5348         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5349                 names[j] = basic_q_cnts[i].name;
5350                 offsets[j] = basic_q_cnts[i].offset;
5351         }
5352
5353         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5354                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5355                         names[j] = out_of_seq_q_cnts[i].name;
5356                         offsets[j] = out_of_seq_q_cnts[i].offset;
5357                 }
5358         }
5359
5360         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5361                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5362                         names[j] = retrans_q_cnts[i].name;
5363                         offsets[j] = retrans_q_cnts[i].offset;
5364                 }
5365         }
5366
5367         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5368                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5369                         names[j] = extended_err_cnts[i].name;
5370                         offsets[j] = extended_err_cnts[i].offset;
5371                 }
5372         }
5373
5374         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5375                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5376                         names[j] = cong_cnts[i].name;
5377                         offsets[j] = cong_cnts[i].offset;
5378                 }
5379         }
5380
5381         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5382                 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5383                         names[j] = ext_ppcnt_cnts[i].name;
5384                         offsets[j] = ext_ppcnt_cnts[i].offset;
5385                 }
5386         }
5387 }
5388
5389 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5390 {
5391         int err = 0;
5392         int i;
5393         bool is_shared;
5394
5395         is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
5396
5397         for (i = 0; i < dev->num_ports; i++) {
5398                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5399                 if (err)
5400                         goto err_alloc;
5401
5402                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5403                                       dev->port[i].cnts.offsets);
5404
5405                 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5406                                                &dev->port[i].cnts.set_id,
5407                                                is_shared ?
5408                                                MLX5_SHARED_RESOURCE_UID : 0);
5409                 if (err) {
5410                         mlx5_ib_warn(dev,
5411                                      "couldn't allocate queue counter for port %d, err %d\n",
5412                                      i + 1, err);
5413                         goto err_alloc;
5414                 }
5415                 dev->port[i].cnts.set_id_valid = true;
5416         }
5417
5418         return 0;
5419
5420 err_alloc:
5421         mlx5_ib_dealloc_counters(dev);
5422         return err;
5423 }
5424
5425 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5426                                                     u8 port_num)
5427 {
5428         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5429         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5430
5431         /* We support only per port stats */
5432         if (port_num == 0)
5433                 return NULL;
5434
5435         return rdma_alloc_hw_stats_struct(port->cnts.names,
5436                                           port->cnts.num_q_counters +
5437                                           port->cnts.num_cong_counters +
5438                                           port->cnts.num_ext_ppcnt_counters,
5439                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5440 }
5441
5442 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5443                                     struct mlx5_ib_port *port,
5444                                     struct rdma_hw_stats *stats)
5445 {
5446         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5447         void *out;
5448         __be32 val;
5449         int ret, i;
5450
5451         out = kvzalloc(outlen, GFP_KERNEL);
5452         if (!out)
5453                 return -ENOMEM;
5454
5455         ret = mlx5_core_query_q_counter(mdev,
5456                                         port->cnts.set_id, 0,
5457                                         out, outlen);
5458         if (ret)
5459                 goto free;
5460
5461         for (i = 0; i < port->cnts.num_q_counters; i++) {
5462                 val = *(__be32 *)(out + port->cnts.offsets[i]);
5463                 stats->value[i] = (u64)be32_to_cpu(val);
5464         }
5465
5466 free:
5467         kvfree(out);
5468         return ret;
5469 }
5470
5471 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5472                                           struct mlx5_ib_port *port,
5473                                           struct rdma_hw_stats *stats)
5474 {
5475         int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5476         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5477         int ret, i;
5478         void *out;
5479
5480         out = kvzalloc(sz, GFP_KERNEL);
5481         if (!out)
5482                 return -ENOMEM;
5483
5484         ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5485         if (ret)
5486                 goto free;
5487
5488         for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5489                 stats->value[i + offset] =
5490                         be64_to_cpup((__be64 *)(out +
5491                                     port->cnts.offsets[i + offset]));
5492         }
5493
5494 free:
5495         kvfree(out);
5496         return ret;
5497 }
5498
5499 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5500                                 struct rdma_hw_stats *stats,
5501                                 u8 port_num, int index)
5502 {
5503         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5504         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5505         struct mlx5_core_dev *mdev;
5506         int ret, num_counters;
5507         u8 mdev_port_num;
5508
5509         if (!stats)
5510                 return -EINVAL;
5511
5512         num_counters = port->cnts.num_q_counters +
5513                        port->cnts.num_cong_counters +
5514                        port->cnts.num_ext_ppcnt_counters;
5515
5516         /* q_counters are per IB device, query the master mdev */
5517         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5518         if (ret)
5519                 return ret;
5520
5521         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5522                 ret =  mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5523                 if (ret)
5524                         return ret;
5525         }
5526
5527         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5528                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5529                                                     &mdev_port_num);
5530                 if (!mdev) {
5531                         /* If port is not affiliated yet, its in down state
5532                          * which doesn't have any counters yet, so it would be
5533                          * zero. So no need to read from the HCA.
5534                          */
5535                         goto done;
5536                 }
5537                 ret = mlx5_lag_query_cong_counters(dev->mdev,
5538                                                    stats->value +
5539                                                    port->cnts.num_q_counters,
5540                                                    port->cnts.num_cong_counters,
5541                                                    port->cnts.offsets +
5542                                                    port->cnts.num_q_counters);
5543
5544                 mlx5_ib_put_native_port_mdev(dev, port_num);
5545                 if (ret)
5546                         return ret;
5547         }
5548
5549 done:
5550         return num_counters;
5551 }
5552
5553 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5554                                  enum rdma_netdev_t type,
5555                                  struct rdma_netdev_alloc_params *params)
5556 {
5557         if (type != RDMA_NETDEV_IPOIB)
5558                 return -EOPNOTSUPP;
5559
5560         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5561 }
5562
5563 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5564 {
5565         if (!dev->delay_drop.dbg)
5566                 return;
5567         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5568         kfree(dev->delay_drop.dbg);
5569         dev->delay_drop.dbg = NULL;
5570 }
5571
5572 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5573 {
5574         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5575                 return;
5576
5577         cancel_work_sync(&dev->delay_drop.delay_drop_work);
5578         delay_drop_debugfs_cleanup(dev);
5579 }
5580
5581 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5582                                        size_t count, loff_t *pos)
5583 {
5584         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5585         char lbuf[20];
5586         int len;
5587
5588         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5589         return simple_read_from_buffer(buf, count, pos, lbuf, len);
5590 }
5591
5592 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5593                                         size_t count, loff_t *pos)
5594 {
5595         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5596         u32 timeout;
5597         u32 var;
5598
5599         if (kstrtouint_from_user(buf, count, 0, &var))
5600                 return -EFAULT;
5601
5602         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5603                         1000);
5604         if (timeout != var)
5605                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5606                             timeout);
5607
5608         delay_drop->timeout = timeout;
5609
5610         return count;
5611 }
5612
5613 static const struct file_operations fops_delay_drop_timeout = {
5614         .owner  = THIS_MODULE,
5615         .open   = simple_open,
5616         .write  = delay_drop_timeout_write,
5617         .read   = delay_drop_timeout_read,
5618 };
5619
5620 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5621 {
5622         struct mlx5_ib_dbg_delay_drop *dbg;
5623
5624         if (!mlx5_debugfs_root)
5625                 return 0;
5626
5627         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5628         if (!dbg)
5629                 return -ENOMEM;
5630
5631         dev->delay_drop.dbg = dbg;
5632
5633         dbg->dir_debugfs =
5634                 debugfs_create_dir("delay_drop",
5635                                    dev->mdev->priv.dbg_root);
5636         if (!dbg->dir_debugfs)
5637                 goto out_debugfs;
5638
5639         dbg->events_cnt_debugfs =
5640                 debugfs_create_atomic_t("num_timeout_events", 0400,
5641                                         dbg->dir_debugfs,
5642                                         &dev->delay_drop.events_cnt);
5643         if (!dbg->events_cnt_debugfs)
5644                 goto out_debugfs;
5645
5646         dbg->rqs_cnt_debugfs =
5647                 debugfs_create_atomic_t("num_rqs", 0400,
5648                                         dbg->dir_debugfs,
5649                                         &dev->delay_drop.rqs_cnt);
5650         if (!dbg->rqs_cnt_debugfs)
5651                 goto out_debugfs;
5652
5653         dbg->timeout_debugfs =
5654                 debugfs_create_file("timeout", 0600,
5655                                     dbg->dir_debugfs,
5656                                     &dev->delay_drop,
5657                                     &fops_delay_drop_timeout);
5658         if (!dbg->timeout_debugfs)
5659                 goto out_debugfs;
5660
5661         return 0;
5662
5663 out_debugfs:
5664         delay_drop_debugfs_cleanup(dev);
5665         return -ENOMEM;
5666 }
5667
5668 static void init_delay_drop(struct mlx5_ib_dev *dev)
5669 {
5670         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5671                 return;
5672
5673         mutex_init(&dev->delay_drop.lock);
5674         dev->delay_drop.dev = dev;
5675         dev->delay_drop.activate = false;
5676         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5677         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5678         atomic_set(&dev->delay_drop.rqs_cnt, 0);
5679         atomic_set(&dev->delay_drop.events_cnt, 0);
5680
5681         if (delay_drop_debugfs_init(dev))
5682                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5683 }
5684
5685 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5686 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5687                                       struct mlx5_ib_multiport_info *mpi)
5688 {
5689         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5690         struct mlx5_ib_port *port = &ibdev->port[port_num];
5691         int comps;
5692         int err;
5693         int i;
5694
5695         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5696
5697         spin_lock(&port->mp.mpi_lock);
5698         if (!mpi->ibdev) {
5699                 spin_unlock(&port->mp.mpi_lock);
5700                 return;
5701         }
5702
5703         if (mpi->mdev_events.notifier_call)
5704                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5705         mpi->mdev_events.notifier_call = NULL;
5706
5707         mpi->ibdev = NULL;
5708
5709         spin_unlock(&port->mp.mpi_lock);
5710         mlx5_remove_netdev_notifier(ibdev, port_num);
5711         spin_lock(&port->mp.mpi_lock);
5712
5713         comps = mpi->mdev_refcnt;
5714         if (comps) {
5715                 mpi->unaffiliate = true;
5716                 init_completion(&mpi->unref_comp);
5717                 spin_unlock(&port->mp.mpi_lock);
5718
5719                 for (i = 0; i < comps; i++)
5720                         wait_for_completion(&mpi->unref_comp);
5721
5722                 spin_lock(&port->mp.mpi_lock);
5723                 mpi->unaffiliate = false;
5724         }
5725
5726         port->mp.mpi = NULL;
5727
5728         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5729
5730         spin_unlock(&port->mp.mpi_lock);
5731
5732         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5733
5734         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5735         /* Log an error, still needed to cleanup the pointers and add
5736          * it back to the list.
5737          */
5738         if (err)
5739                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5740                             port_num + 1);
5741
5742         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
5743 }
5744
5745 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5746 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5747                                     struct mlx5_ib_multiport_info *mpi)
5748 {
5749         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5750         int err;
5751
5752         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5753         if (ibdev->port[port_num].mp.mpi) {
5754                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5755                             port_num + 1);
5756                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5757                 return false;
5758         }
5759
5760         ibdev->port[port_num].mp.mpi = mpi;
5761         mpi->ibdev = ibdev;
5762         mpi->mdev_events.notifier_call = NULL;
5763         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5764
5765         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5766         if (err)
5767                 goto unbind;
5768
5769         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5770         if (err)
5771                 goto unbind;
5772
5773         err = mlx5_add_netdev_notifier(ibdev, port_num);
5774         if (err) {
5775                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5776                             port_num + 1);
5777                 goto unbind;
5778         }
5779
5780         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5781         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5782
5783         mlx5_ib_init_cong_debugfs(ibdev, port_num);
5784
5785         return true;
5786
5787 unbind:
5788         mlx5_ib_unbind_slave_port(ibdev, mpi);
5789         return false;
5790 }
5791
5792 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5793 {
5794         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5795         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5796                                                           port_num + 1);
5797         struct mlx5_ib_multiport_info *mpi;
5798         int err;
5799         int i;
5800
5801         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5802                 return 0;
5803
5804         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5805                                                      &dev->sys_image_guid);
5806         if (err)
5807                 return err;
5808
5809         err = mlx5_nic_vport_enable_roce(dev->mdev);
5810         if (err)
5811                 return err;
5812
5813         mutex_lock(&mlx5_ib_multiport_mutex);
5814         for (i = 0; i < dev->num_ports; i++) {
5815                 bool bound = false;
5816
5817                 /* build a stub multiport info struct for the native port. */
5818                 if (i == port_num) {
5819                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5820                         if (!mpi) {
5821                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5822                                 mlx5_nic_vport_disable_roce(dev->mdev);
5823                                 return -ENOMEM;
5824                         }
5825
5826                         mpi->is_master = true;
5827                         mpi->mdev = dev->mdev;
5828                         mpi->sys_image_guid = dev->sys_image_guid;
5829                         dev->port[i].mp.mpi = mpi;
5830                         mpi->ibdev = dev;
5831                         mpi = NULL;
5832                         continue;
5833                 }
5834
5835                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5836                                     list) {
5837                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5838                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5839                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5840                         }
5841
5842                         if (bound) {
5843                                 dev_dbg(mpi->mdev->device,
5844                                         "removing port from unaffiliated list.\n");
5845                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5846                                 list_del(&mpi->list);
5847                                 break;
5848                         }
5849                 }
5850                 if (!bound) {
5851                         get_port_caps(dev, i + 1);
5852                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5853                                     i + 1);
5854                 }
5855         }
5856
5857         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5858         mutex_unlock(&mlx5_ib_multiport_mutex);
5859         return err;
5860 }
5861
5862 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5863 {
5864         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5865         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5866                                                           port_num + 1);
5867         int i;
5868
5869         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5870                 return;
5871
5872         mutex_lock(&mlx5_ib_multiport_mutex);
5873         for (i = 0; i < dev->num_ports; i++) {
5874                 if (dev->port[i].mp.mpi) {
5875                         /* Destroy the native port stub */
5876                         if (i == port_num) {
5877                                 kfree(dev->port[i].mp.mpi);
5878                                 dev->port[i].mp.mpi = NULL;
5879                         } else {
5880                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5881                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5882                         }
5883                 }
5884         }
5885
5886         mlx5_ib_dbg(dev, "removing from devlist\n");
5887         list_del(&dev->ib_dev_list);
5888         mutex_unlock(&mlx5_ib_multiport_mutex);
5889
5890         mlx5_nic_vport_disable_roce(dev->mdev);
5891 }
5892
5893 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5894         mlx5_ib_dm,
5895         UVERBS_OBJECT_DM,
5896         UVERBS_METHOD_DM_ALLOC,
5897         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5898                             UVERBS_ATTR_TYPE(u64),
5899                             UA_MANDATORY),
5900         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5901                             UVERBS_ATTR_TYPE(u16),
5902                             UA_OPTIONAL),
5903         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
5904                              enum mlx5_ib_uapi_dm_type,
5905                              UA_OPTIONAL));
5906
5907 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5908         mlx5_ib_flow_action,
5909         UVERBS_OBJECT_FLOW_ACTION,
5910         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5911         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5912                              enum mlx5_ib_uapi_flow_action_flags));
5913
5914 static const struct uapi_definition mlx5_ib_defs[] = {
5915 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
5916         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
5917         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
5918 #endif
5919
5920         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
5921                                 &mlx5_ib_flow_action),
5922         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
5923         {}
5924 };
5925
5926 static int mlx5_ib_read_counters(struct ib_counters *counters,
5927                                  struct ib_counters_read_attr *read_attr,
5928                                  struct uverbs_attr_bundle *attrs)
5929 {
5930         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5931         struct mlx5_read_counters_attr mread_attr = {};
5932         struct mlx5_ib_flow_counters_desc *desc;
5933         int ret, i;
5934
5935         mutex_lock(&mcounters->mcntrs_mutex);
5936         if (mcounters->cntrs_max_index > read_attr->ncounters) {
5937                 ret = -EINVAL;
5938                 goto err_bound;
5939         }
5940
5941         mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5942                                  GFP_KERNEL);
5943         if (!mread_attr.out) {
5944                 ret = -ENOMEM;
5945                 goto err_bound;
5946         }
5947
5948         mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5949         mread_attr.flags = read_attr->flags;
5950         ret = mcounters->read_counters(counters->device, &mread_attr);
5951         if (ret)
5952                 goto err_read;
5953
5954         /* do the pass over the counters data array to assign according to the
5955          * descriptions and indexing pairs
5956          */
5957         desc = mcounters->counters_data;
5958         for (i = 0; i < mcounters->ncounters; i++)
5959                 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5960
5961 err_read:
5962         kfree(mread_attr.out);
5963 err_bound:
5964         mutex_unlock(&mcounters->mcntrs_mutex);
5965         return ret;
5966 }
5967
5968 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5969 {
5970         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5971
5972         counters_clear_description(counters);
5973         if (mcounters->hw_cntrs_hndl)
5974                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5975                                 mcounters->hw_cntrs_hndl);
5976
5977         kfree(mcounters);
5978
5979         return 0;
5980 }
5981
5982 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5983                                                    struct uverbs_attr_bundle *attrs)
5984 {
5985         struct mlx5_ib_mcounters *mcounters;
5986
5987         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5988         if (!mcounters)
5989                 return ERR_PTR(-ENOMEM);
5990
5991         mutex_init(&mcounters->mcntrs_mutex);
5992
5993         return &mcounters->ibcntrs;
5994 }
5995
5996 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5997 {
5998         struct mlx5_core_dev *mdev = dev->mdev;
5999
6000         mlx5_ib_cleanup_multiport_master(dev);
6001         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6002                 srcu_barrier(&dev->mr_srcu);
6003                 cleanup_srcu_struct(&dev->mr_srcu);
6004         }
6005
6006         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
6007
6008         WARN_ON(dev->dm.steering_sw_icm_alloc_blocks &&
6009                 !bitmap_empty(
6010                         dev->dm.steering_sw_icm_alloc_blocks,
6011                         BIT(MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size) -
6012                             MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6013
6014         kfree(dev->dm.steering_sw_icm_alloc_blocks);
6015
6016         WARN_ON(dev->dm.header_modify_sw_icm_alloc_blocks &&
6017                 !bitmap_empty(dev->dm.header_modify_sw_icm_alloc_blocks,
6018                               BIT(MLX5_CAP_DEV_MEM(
6019                                           mdev, log_header_modify_sw_icm_size) -
6020                                   MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6021
6022         kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6023 }
6024
6025 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
6026 {
6027         struct mlx5_core_dev *mdev = dev->mdev;
6028         u64 header_modify_icm_blocks = 0;
6029         u64 steering_icm_blocks = 0;
6030         int err;
6031         int i;
6032
6033         for (i = 0; i < dev->num_ports; i++) {
6034                 spin_lock_init(&dev->port[i].mp.mpi_lock);
6035                 rwlock_init(&dev->port[i].roce.netdev_lock);
6036                 dev->port[i].roce.dev = dev;
6037                 dev->port[i].roce.native_port_num = i + 1;
6038                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
6039         }
6040
6041         err = mlx5_ib_init_multiport_master(dev);
6042         if (err)
6043                 return err;
6044
6045         err = set_has_smi_cap(dev);
6046         if (err)
6047                 return err;
6048
6049         if (!mlx5_core_mp_enabled(mdev)) {
6050                 for (i = 1; i <= dev->num_ports; i++) {
6051                         err = get_port_caps(dev, i);
6052                         if (err)
6053                                 break;
6054                 }
6055         } else {
6056                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6057         }
6058         if (err)
6059                 goto err_mp;
6060
6061         if (mlx5_use_mad_ifc(dev))
6062                 get_ext_port_caps(dev);
6063
6064         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
6065         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
6066         dev->ib_dev.phys_port_cnt       = dev->num_ports;
6067         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
6068         dev->ib_dev.dev.parent          = mdev->device;
6069
6070         mutex_init(&dev->cap_mask_mutex);
6071         INIT_LIST_HEAD(&dev->qp_list);
6072         spin_lock_init(&dev->reset_flow_resource_lock);
6073
6074         if (MLX5_CAP_GEN_64(mdev, general_obj_types) &
6075             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) {
6076                 if (MLX5_CAP64_DEV_MEM(mdev, steering_sw_icm_start_address)) {
6077                         steering_icm_blocks =
6078                                 BIT(MLX5_CAP_DEV_MEM(mdev,
6079                                                      log_steering_sw_icm_size) -
6080                                     MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6081
6082                         dev->dm.steering_sw_icm_alloc_blocks =
6083                                 kcalloc(BITS_TO_LONGS(steering_icm_blocks),
6084                                         sizeof(unsigned long), GFP_KERNEL);
6085                         if (!dev->dm.steering_sw_icm_alloc_blocks)
6086                                 goto err_mp;
6087                 }
6088
6089                 if (MLX5_CAP64_DEV_MEM(mdev,
6090                                        header_modify_sw_icm_start_address)) {
6091                         header_modify_icm_blocks = BIT(
6092                                 MLX5_CAP_DEV_MEM(
6093                                         mdev, log_header_modify_sw_icm_size) -
6094                                 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6095
6096                         dev->dm.header_modify_sw_icm_alloc_blocks =
6097                                 kcalloc(BITS_TO_LONGS(header_modify_icm_blocks),
6098                                         sizeof(unsigned long), GFP_KERNEL);
6099                         if (!dev->dm.header_modify_sw_icm_alloc_blocks)
6100                                 goto err_dm;
6101                 }
6102         }
6103
6104         spin_lock_init(&dev->dm.lock);
6105         dev->dm.dev = mdev;
6106
6107         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6108                 err = init_srcu_struct(&dev->mr_srcu);
6109                 if (err)
6110                         goto err_dm;
6111         }
6112
6113         return 0;
6114
6115 err_dm:
6116         kfree(dev->dm.steering_sw_icm_alloc_blocks);
6117         kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6118
6119 err_mp:
6120         mlx5_ib_cleanup_multiport_master(dev);
6121
6122         return -ENOMEM;
6123 }
6124
6125 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6126 {
6127         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6128
6129         if (!dev->flow_db)
6130                 return -ENOMEM;
6131
6132         mutex_init(&dev->flow_db->lock);
6133
6134         return 0;
6135 }
6136
6137 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6138 {
6139         kfree(dev->flow_db);
6140 }
6141
6142 static const struct ib_device_ops mlx5_ib_dev_ops = {
6143         .owner = THIS_MODULE,
6144         .driver_id = RDMA_DRIVER_MLX5,
6145         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
6146
6147         .add_gid = mlx5_ib_add_gid,
6148         .alloc_mr = mlx5_ib_alloc_mr,
6149         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
6150         .alloc_pd = mlx5_ib_alloc_pd,
6151         .alloc_ucontext = mlx5_ib_alloc_ucontext,
6152         .attach_mcast = mlx5_ib_mcg_attach,
6153         .check_mr_status = mlx5_ib_check_mr_status,
6154         .create_ah = mlx5_ib_create_ah,
6155         .create_counters = mlx5_ib_create_counters,
6156         .create_cq = mlx5_ib_create_cq,
6157         .create_flow = mlx5_ib_create_flow,
6158         .create_qp = mlx5_ib_create_qp,
6159         .create_srq = mlx5_ib_create_srq,
6160         .dealloc_pd = mlx5_ib_dealloc_pd,
6161         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6162         .del_gid = mlx5_ib_del_gid,
6163         .dereg_mr = mlx5_ib_dereg_mr,
6164         .destroy_ah = mlx5_ib_destroy_ah,
6165         .destroy_counters = mlx5_ib_destroy_counters,
6166         .destroy_cq = mlx5_ib_destroy_cq,
6167         .destroy_flow = mlx5_ib_destroy_flow,
6168         .destroy_flow_action = mlx5_ib_destroy_flow_action,
6169         .destroy_qp = mlx5_ib_destroy_qp,
6170         .destroy_srq = mlx5_ib_destroy_srq,
6171         .detach_mcast = mlx5_ib_mcg_detach,
6172         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6173         .drain_rq = mlx5_ib_drain_rq,
6174         .drain_sq = mlx5_ib_drain_sq,
6175         .get_dev_fw_str = get_dev_fw_str,
6176         .get_dma_mr = mlx5_ib_get_dma_mr,
6177         .get_link_layer = mlx5_ib_port_link_layer,
6178         .map_mr_sg = mlx5_ib_map_mr_sg,
6179         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
6180         .mmap = mlx5_ib_mmap,
6181         .modify_cq = mlx5_ib_modify_cq,
6182         .modify_device = mlx5_ib_modify_device,
6183         .modify_port = mlx5_ib_modify_port,
6184         .modify_qp = mlx5_ib_modify_qp,
6185         .modify_srq = mlx5_ib_modify_srq,
6186         .poll_cq = mlx5_ib_poll_cq,
6187         .post_recv = mlx5_ib_post_recv,
6188         .post_send = mlx5_ib_post_send,
6189         .post_srq_recv = mlx5_ib_post_srq_recv,
6190         .process_mad = mlx5_ib_process_mad,
6191         .query_ah = mlx5_ib_query_ah,
6192         .query_device = mlx5_ib_query_device,
6193         .query_gid = mlx5_ib_query_gid,
6194         .query_pkey = mlx5_ib_query_pkey,
6195         .query_qp = mlx5_ib_query_qp,
6196         .query_srq = mlx5_ib_query_srq,
6197         .read_counters = mlx5_ib_read_counters,
6198         .reg_user_mr = mlx5_ib_reg_user_mr,
6199         .req_notify_cq = mlx5_ib_arm_cq,
6200         .rereg_user_mr = mlx5_ib_rereg_user_mr,
6201         .resize_cq = mlx5_ib_resize_cq,
6202
6203         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
6204         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
6205         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
6206         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
6207         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
6208 };
6209
6210 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6211         .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6212         .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6213 };
6214
6215 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6216         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6217 };
6218
6219 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6220         .get_vf_config = mlx5_ib_get_vf_config,
6221         .get_vf_stats = mlx5_ib_get_vf_stats,
6222         .set_vf_guid = mlx5_ib_set_vf_guid,
6223         .set_vf_link_state = mlx5_ib_set_vf_link_state,
6224 };
6225
6226 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6227         .alloc_mw = mlx5_ib_alloc_mw,
6228         .dealloc_mw = mlx5_ib_dealloc_mw,
6229 };
6230
6231 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6232         .alloc_xrcd = mlx5_ib_alloc_xrcd,
6233         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6234 };
6235
6236 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6237         .alloc_dm = mlx5_ib_alloc_dm,
6238         .dealloc_dm = mlx5_ib_dealloc_dm,
6239         .reg_dm_mr = mlx5_ib_reg_dm_mr,
6240 };
6241
6242 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
6243 {
6244         struct mlx5_core_dev *mdev = dev->mdev;
6245         int err;
6246
6247         dev->ib_dev.uverbs_cmd_mask     =
6248                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
6249                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
6250                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
6251                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
6252                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
6253                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
6254                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
6255                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
6256                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
6257                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
6258                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6259                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
6260                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
6261                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
6262                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
6263                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
6264                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
6265                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
6266                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
6267                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
6268                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
6269                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
6270                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
6271                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
6272                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
6273                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
6274         dev->ib_dev.uverbs_ex_cmd_mask =
6275                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
6276                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
6277                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
6278                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
6279                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ)        |
6280                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW)      |
6281                 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6282
6283         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6284             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
6285                 ib_set_device_ops(&dev->ib_dev,
6286                                   &mlx5_ib_dev_ipoib_enhanced_ops);
6287
6288         if (mlx5_core_is_pf(mdev))
6289                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
6290
6291         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6292
6293         if (MLX5_CAP_GEN(mdev, imaicl)) {
6294                 dev->ib_dev.uverbs_cmd_mask |=
6295                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
6296                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
6297                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
6298         }
6299
6300         if (MLX5_CAP_GEN(mdev, xrc)) {
6301                 dev->ib_dev.uverbs_cmd_mask |=
6302                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6303                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
6304                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
6305         }
6306
6307         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6308             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6309             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
6310                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
6311
6312         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
6313             MLX5_ACCEL_IPSEC_CAP_DEVICE)
6314                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
6315         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
6316
6317         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6318                 dev->ib_dev.driver_def = mlx5_ib_defs;
6319
6320         err = init_node_data(dev);
6321         if (err)
6322                 return err;
6323
6324         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
6325             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6326              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
6327                 mutex_init(&dev->lb.mutex);
6328
6329         return 0;
6330 }
6331
6332 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6333         .get_port_immutable = mlx5_port_immutable,
6334         .query_port = mlx5_ib_query_port,
6335 };
6336
6337 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6338 {
6339         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
6340         return 0;
6341 }
6342
6343 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6344         .get_port_immutable = mlx5_port_rep_immutable,
6345         .query_port = mlx5_ib_rep_query_port,
6346 };
6347
6348 static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
6349 {
6350         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
6351         return 0;
6352 }
6353
6354 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6355         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6356         .create_wq = mlx5_ib_create_wq,
6357         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6358         .destroy_wq = mlx5_ib_destroy_wq,
6359         .get_netdev = mlx5_ib_get_netdev,
6360         .modify_wq = mlx5_ib_modify_wq,
6361 };
6362
6363 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
6364 {
6365         u8 port_num;
6366
6367         dev->ib_dev.uverbs_ex_cmd_mask |=
6368                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6369                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6370                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6371                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6372                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6373         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
6374
6375         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6376
6377         /* Register only for native ports */
6378         return mlx5_add_netdev_notifier(dev, port_num);
6379 }
6380
6381 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6382 {
6383         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6384
6385         mlx5_remove_netdev_notifier(dev, port_num);
6386 }
6387
6388 static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6389 {
6390         struct mlx5_core_dev *mdev = dev->mdev;
6391         enum rdma_link_layer ll;
6392         int port_type_cap;
6393         int err = 0;
6394
6395         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6396         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6397
6398         if (ll == IB_LINK_LAYER_ETHERNET)
6399                 err = mlx5_ib_stage_common_roce_init(dev);
6400
6401         return err;
6402 }
6403
6404 static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6405 {
6406         mlx5_ib_stage_common_roce_cleanup(dev);
6407 }
6408
6409 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6410 {
6411         struct mlx5_core_dev *mdev = dev->mdev;
6412         enum rdma_link_layer ll;
6413         int port_type_cap;
6414         int err;
6415
6416         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6417         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6418
6419         if (ll == IB_LINK_LAYER_ETHERNET) {
6420                 err = mlx5_ib_stage_common_roce_init(dev);
6421                 if (err)
6422                         return err;
6423
6424                 err = mlx5_enable_eth(dev);
6425                 if (err)
6426                         goto cleanup;
6427         }
6428
6429         return 0;
6430 cleanup:
6431         mlx5_ib_stage_common_roce_cleanup(dev);
6432
6433         return err;
6434 }
6435
6436 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6437 {
6438         struct mlx5_core_dev *mdev = dev->mdev;
6439         enum rdma_link_layer ll;
6440         int port_type_cap;
6441
6442         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6443         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6444
6445         if (ll == IB_LINK_LAYER_ETHERNET) {
6446                 mlx5_disable_eth(dev);
6447                 mlx5_ib_stage_common_roce_cleanup(dev);
6448         }
6449 }
6450
6451 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6452 {
6453         return create_dev_resources(&dev->devr);
6454 }
6455
6456 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6457 {
6458         destroy_dev_resources(&dev->devr);
6459 }
6460
6461 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6462 {
6463         mlx5_ib_internal_fill_odp_caps(dev);
6464
6465         return mlx5_ib_odp_init_one(dev);
6466 }
6467
6468 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6469 {
6470         mlx5_ib_odp_cleanup_one(dev);
6471 }
6472
6473 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6474         .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6475         .get_hw_stats = mlx5_ib_get_hw_stats,
6476 };
6477
6478 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6479 {
6480         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6481                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
6482
6483                 return mlx5_ib_alloc_counters(dev);
6484         }
6485
6486         return 0;
6487 }
6488
6489 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6490 {
6491         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6492                 mlx5_ib_dealloc_counters(dev);
6493 }
6494
6495 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6496 {
6497         mlx5_ib_init_cong_debugfs(dev,
6498                                   mlx5_core_native_port_num(dev->mdev) - 1);
6499         return 0;
6500 }
6501
6502 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6503 {
6504         mlx5_ib_cleanup_cong_debugfs(dev,
6505                                      mlx5_core_native_port_num(dev->mdev) - 1);
6506 }
6507
6508 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6509 {
6510         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6511         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6512 }
6513
6514 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6515 {
6516         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6517 }
6518
6519 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6520 {
6521         int err;
6522
6523         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6524         if (err)
6525                 return err;
6526
6527         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6528         if (err)
6529                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6530
6531         return err;
6532 }
6533
6534 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6535 {
6536         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6537         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6538 }
6539
6540 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6541 {
6542         const char *name;
6543
6544         rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
6545         if (!mlx5_lag_is_roce(dev->mdev))
6546                 name = "mlx5_%d";
6547         else
6548                 name = "mlx5_bond_%d";
6549         return ib_register_device(&dev->ib_dev, name);
6550 }
6551
6552 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6553 {
6554         destroy_umrc_res(dev);
6555 }
6556
6557 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6558 {
6559         ib_unregister_device(&dev->ib_dev);
6560 }
6561
6562 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6563 {
6564         return create_umr_res(dev);
6565 }
6566
6567 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6568 {
6569         init_delay_drop(dev);
6570
6571         return 0;
6572 }
6573
6574 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6575 {
6576         cancel_delay_drop(dev);
6577 }
6578
6579 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6580 {
6581         dev->mdev_events.notifier_call = mlx5_ib_event;
6582         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6583         return 0;
6584 }
6585
6586 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6587 {
6588         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6589 }
6590
6591 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6592 {
6593         int uid;
6594
6595         uid = mlx5_ib_devx_create(dev, false);
6596         if (uid > 0)
6597                 dev->devx_whitelist_uid = uid;
6598
6599         return 0;
6600 }
6601 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6602 {
6603         if (dev->devx_whitelist_uid)
6604                 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6605 }
6606
6607 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6608                       const struct mlx5_ib_profile *profile,
6609                       int stage)
6610 {
6611         /* Number of stages to cleanup */
6612         while (stage) {
6613                 stage--;
6614                 if (profile->stage[stage].cleanup)
6615                         profile->stage[stage].cleanup(dev);
6616         }
6617
6618         kfree(dev->port);
6619         ib_dealloc_device(&dev->ib_dev);
6620 }
6621
6622 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6623                     const struct mlx5_ib_profile *profile)
6624 {
6625         int err;
6626         int i;
6627
6628         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6629                 if (profile->stage[i].init) {
6630                         err = profile->stage[i].init(dev);
6631                         if (err)
6632                                 goto err_out;
6633                 }
6634         }
6635
6636         dev->profile = profile;
6637         dev->ib_active = true;
6638
6639         return dev;
6640
6641 err_out:
6642         __mlx5_ib_remove(dev, profile, i);
6643
6644         return NULL;
6645 }
6646
6647 static const struct mlx5_ib_profile pf_profile = {
6648         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6649                      mlx5_ib_stage_init_init,
6650                      mlx5_ib_stage_init_cleanup),
6651         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6652                      mlx5_ib_stage_flow_db_init,
6653                      mlx5_ib_stage_flow_db_cleanup),
6654         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6655                      mlx5_ib_stage_caps_init,
6656                      NULL),
6657         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6658                      mlx5_ib_stage_non_default_cb,
6659                      NULL),
6660         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6661                      mlx5_ib_stage_roce_init,
6662                      mlx5_ib_stage_roce_cleanup),
6663         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6664                      mlx5_init_srq_table,
6665                      mlx5_cleanup_srq_table),
6666         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6667                      mlx5_ib_stage_dev_res_init,
6668                      mlx5_ib_stage_dev_res_cleanup),
6669         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6670                      mlx5_ib_stage_dev_notifier_init,
6671                      mlx5_ib_stage_dev_notifier_cleanup),
6672         STAGE_CREATE(MLX5_IB_STAGE_ODP,
6673                      mlx5_ib_stage_odp_init,
6674                      mlx5_ib_stage_odp_cleanup),
6675         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6676                      mlx5_ib_stage_counters_init,
6677                      mlx5_ib_stage_counters_cleanup),
6678         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6679                      mlx5_ib_stage_cong_debugfs_init,
6680                      mlx5_ib_stage_cong_debugfs_cleanup),
6681         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6682                      mlx5_ib_stage_uar_init,
6683                      mlx5_ib_stage_uar_cleanup),
6684         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6685                      mlx5_ib_stage_bfrag_init,
6686                      mlx5_ib_stage_bfrag_cleanup),
6687         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6688                      NULL,
6689                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6690         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6691                      mlx5_ib_stage_devx_init,
6692                      mlx5_ib_stage_devx_cleanup),
6693         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6694                      mlx5_ib_stage_ib_reg_init,
6695                      mlx5_ib_stage_ib_reg_cleanup),
6696         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6697                      mlx5_ib_stage_post_ib_reg_umr_init,
6698                      NULL),
6699         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6700                      mlx5_ib_stage_delay_drop_init,
6701                      mlx5_ib_stage_delay_drop_cleanup),
6702 };
6703
6704 const struct mlx5_ib_profile uplink_rep_profile = {
6705         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6706                      mlx5_ib_stage_init_init,
6707                      mlx5_ib_stage_init_cleanup),
6708         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6709                      mlx5_ib_stage_flow_db_init,
6710                      mlx5_ib_stage_flow_db_cleanup),
6711         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6712                      mlx5_ib_stage_caps_init,
6713                      NULL),
6714         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6715                      mlx5_ib_stage_rep_non_default_cb,
6716                      NULL),
6717         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6718                      mlx5_ib_stage_rep_roce_init,
6719                      mlx5_ib_stage_rep_roce_cleanup),
6720         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6721                      mlx5_init_srq_table,
6722                      mlx5_cleanup_srq_table),
6723         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6724                      mlx5_ib_stage_dev_res_init,
6725                      mlx5_ib_stage_dev_res_cleanup),
6726         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6727                      mlx5_ib_stage_dev_notifier_init,
6728                      mlx5_ib_stage_dev_notifier_cleanup),
6729         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6730                      mlx5_ib_stage_counters_init,
6731                      mlx5_ib_stage_counters_cleanup),
6732         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6733                      mlx5_ib_stage_uar_init,
6734                      mlx5_ib_stage_uar_cleanup),
6735         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6736                      mlx5_ib_stage_bfrag_init,
6737                      mlx5_ib_stage_bfrag_cleanup),
6738         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6739                      NULL,
6740                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6741         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6742                      mlx5_ib_stage_devx_init,
6743                      mlx5_ib_stage_devx_cleanup),
6744         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6745                      mlx5_ib_stage_ib_reg_init,
6746                      mlx5_ib_stage_ib_reg_cleanup),
6747         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6748                      mlx5_ib_stage_post_ib_reg_umr_init,
6749                      NULL),
6750 };
6751
6752 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6753 {
6754         struct mlx5_ib_multiport_info *mpi;
6755         struct mlx5_ib_dev *dev;
6756         bool bound = false;
6757         int err;
6758
6759         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6760         if (!mpi)
6761                 return NULL;
6762
6763         mpi->mdev = mdev;
6764
6765         err = mlx5_query_nic_vport_system_image_guid(mdev,
6766                                                      &mpi->sys_image_guid);
6767         if (err) {
6768                 kfree(mpi);
6769                 return NULL;
6770         }
6771
6772         mutex_lock(&mlx5_ib_multiport_mutex);
6773         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6774                 if (dev->sys_image_guid == mpi->sys_image_guid)
6775                         bound = mlx5_ib_bind_slave_port(dev, mpi);
6776
6777                 if (bound) {
6778                         rdma_roce_rescan_device(&dev->ib_dev);
6779                         break;
6780                 }
6781         }
6782
6783         if (!bound) {
6784                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6785                 dev_dbg(mdev->device,
6786                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
6787         }
6788         mutex_unlock(&mlx5_ib_multiport_mutex);
6789
6790         return mpi;
6791 }
6792
6793 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6794 {
6795         enum rdma_link_layer ll;
6796         struct mlx5_ib_dev *dev;
6797         int port_type_cap;
6798         int num_ports;
6799
6800         printk_once(KERN_INFO "%s", mlx5_version);
6801
6802         if (MLX5_ESWITCH_MANAGER(mdev) &&
6803             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6804                 if (!mlx5_core_mp_enabled(mdev))
6805                         mlx5_ib_register_vport_reps(mdev);
6806                 return mdev;
6807         }
6808
6809         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6810         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6811
6812         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6813                 return mlx5_ib_add_slave_port(mdev);
6814
6815         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6816                         MLX5_CAP_GEN(mdev, num_vhca_ports));
6817         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
6818         if (!dev)
6819                 return NULL;
6820         dev->port = kcalloc(num_ports, sizeof(*dev->port),
6821                              GFP_KERNEL);
6822         if (!dev->port) {
6823                 ib_dealloc_device((struct ib_device *)dev);
6824                 return NULL;
6825         }
6826
6827         dev->mdev = mdev;
6828         dev->num_ports = num_ports;
6829
6830         return __mlx5_ib_add(dev, &pf_profile);
6831 }
6832
6833 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6834 {
6835         struct mlx5_ib_multiport_info *mpi;
6836         struct mlx5_ib_dev *dev;
6837
6838         if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6839                 mlx5_ib_unregister_vport_reps(mdev);
6840                 return;
6841         }
6842
6843         if (mlx5_core_is_mp_slave(mdev)) {
6844                 mpi = context;
6845                 mutex_lock(&mlx5_ib_multiport_mutex);
6846                 if (mpi->ibdev)
6847                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6848                 list_del(&mpi->list);
6849                 mutex_unlock(&mlx5_ib_multiport_mutex);
6850                 return;
6851         }
6852
6853         dev = context;
6854         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6855 }
6856
6857 static struct mlx5_interface mlx5_ib_interface = {
6858         .add            = mlx5_ib_add,
6859         .remove         = mlx5_ib_remove,
6860         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6861 };
6862
6863 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6864 {
6865         mutex_lock(&xlt_emergency_page_mutex);
6866         return xlt_emergency_page;
6867 }
6868
6869 void mlx5_ib_put_xlt_emergency_page(void)
6870 {
6871         mutex_unlock(&xlt_emergency_page_mutex);
6872 }
6873
6874 static int __init mlx5_ib_init(void)
6875 {
6876         int err;
6877
6878         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6879         if (!xlt_emergency_page)
6880                 return -ENOMEM;
6881
6882         mutex_init(&xlt_emergency_page_mutex);
6883
6884         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6885         if (!mlx5_ib_event_wq) {
6886                 free_page(xlt_emergency_page);
6887                 return -ENOMEM;
6888         }
6889
6890         mlx5_ib_odp_init();
6891
6892         err = mlx5_register_interface(&mlx5_ib_interface);
6893
6894         return err;
6895 }
6896
6897 static void __exit mlx5_ib_cleanup(void)
6898 {
6899         mlx5_unregister_interface(&mlx5_ib_interface);
6900         destroy_workqueue(mlx5_ib_event_wq);
6901         mutex_destroy(&xlt_emergency_page_mutex);
6902         free_page(xlt_emergency_page);
6903 }
6904
6905 module_init(mlx5_ib_init);
6906 module_exit(mlx5_ib_cleanup);