drivers/infiniband/hw/mlx5/cq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/kref.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <rdma/ib_cache.h>
  37 #include "mlx5_ib.h"
  38 #include "srq.h"
  39
  40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
  41 {
  42         struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  43
  44         ibcq->comp_handler(ibcq, ibcq->cq_context);
  45 }
  46
  47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
  48 {
  49         struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
  50         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
  51         struct ib_cq *ibcq = &cq->ibcq;
  52         struct ib_event event;
  53
  54         if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
  55                 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
  56                              type, mcq->cqn);
  57                 return;
  58         }
  59
  60         if (ibcq->event_handler) {
  61                 event.device     = &dev->ib_dev;
  62                 event.event      = IB_EVENT_CQ_ERR;
  63                 event.element.cq = ibcq;
  64                 ibcq->event_handler(&event, ibcq->cq_context);
  65         }
  66 }
  67
  68 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
  69 {
  70         return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n);
  71 }
  72
  73 static u8 sw_ownership_bit(int n, int nent)
  74 {
  75         return (n & nent) ? 1 : 0;
  76 }
  77
  78 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
  79 {
  80         void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  81         struct mlx5_cqe64 *cqe64;
  82
  83         cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
  84
  85         if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) &&
  86             !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
  87                 return cqe;
  88         } else {
  89                 return NULL;
  90         }
  91 }
  92
  93 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
  94 {
  95         return get_sw_cqe(cq, cq->mcq.cons_index);
  96 }
  97
  98 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
  99 {
 100         switch (wq->wr_data[idx]) {
 101         case MLX5_IB_WR_UMR:
 102                 return 0;
 103
 104         case IB_WR_LOCAL_INV:
 105                 return IB_WC_LOCAL_INV;
 106
 107         case IB_WR_REG_MR:
 108                 return IB_WC_REG_MR;
 109
 110         default:
 111                 pr_warn("unknown completion status\n");
 112                 return 0;
 113         }
 114 }
 115
 116 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
 117                             struct mlx5_ib_wq *wq, int idx)
 118 {
 119         wc->wc_flags = 0;
 120         switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
 121         case MLX5_OPCODE_RDMA_WRITE_IMM:
 122                 wc->wc_flags |= IB_WC_WITH_IMM;
 123                 /* fall through */
 124         case MLX5_OPCODE_RDMA_WRITE:
 125                 wc->opcode    = IB_WC_RDMA_WRITE;
 126                 break;
 127         case MLX5_OPCODE_SEND_IMM:
 128                 wc->wc_flags |= IB_WC_WITH_IMM;
 129                 /* fall through */
 130         case MLX5_OPCODE_SEND:
 131         case MLX5_OPCODE_SEND_INVAL:
 132                 wc->opcode    = IB_WC_SEND;
 133                 break;
 134         case MLX5_OPCODE_RDMA_READ:
 135                 wc->opcode    = IB_WC_RDMA_READ;
 136                 wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
 137                 break;
 138         case MLX5_OPCODE_ATOMIC_CS:
 139                 wc->opcode    = IB_WC_COMP_SWAP;
 140                 wc->byte_len  = 8;
 141                 break;
 142         case MLX5_OPCODE_ATOMIC_FA:
 143                 wc->opcode    = IB_WC_FETCH_ADD;
 144                 wc->byte_len  = 8;
 145                 break;
 146         case MLX5_OPCODE_ATOMIC_MASKED_CS:
 147                 wc->opcode    = IB_WC_MASKED_COMP_SWAP;
 148                 wc->byte_len  = 8;
 149                 break;
 150         case MLX5_OPCODE_ATOMIC_MASKED_FA:
 151                 wc->opcode    = IB_WC_MASKED_FETCH_ADD;
 152                 wc->byte_len  = 8;
 153                 break;
 154         case MLX5_OPCODE_UMR:
 155                 wc->opcode = get_umr_comp(wq, idx);
 156                 break;
 157         }
 158 }
 159
 160 enum {
 161         MLX5_GRH_IN_BUFFER = 1,
 162         MLX5_GRH_IN_CQE    = 2,
 163 };
 164
 165 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
 166                              struct mlx5_ib_qp *qp)
 167 {
 168         enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
 169         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
 170         struct mlx5_ib_srq *srq;
 171         struct mlx5_ib_wq *wq;
 172         u16 wqe_ctr;
 173         u8  roce_packet_type;
 174         bool vlan_present;
 175         u8 g;
 176
 177         if (qp->ibqp.srq || qp->ibqp.xrcd) {
 178                 struct mlx5_core_srq *msrq = NULL;
 179
 180                 if (qp->ibqp.xrcd) {
 181                         msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn));
 182                         srq = to_mibsrq(msrq);
 183                 } else {
 184                         srq = to_msrq(qp->ibqp.srq);
 185                 }
 186                 if (srq) {
 187                         wqe_ctr = be16_to_cpu(cqe->wqe_counter);
 188                         wc->wr_id = srq->wrid[wqe_ctr];
 189                         mlx5_ib_free_srq_wqe(srq, wqe_ctr);
 190                         if (msrq)
 191                                 mlx5_core_res_put(&msrq->common);
 192                 }
 193         } else {
 194                 wq        = &qp->rq;
 195                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 196                 ++wq->tail;
 197         }
 198         wc->byte_len = be32_to_cpu(cqe->byte_cnt);
 199
 200         switch (get_cqe_opcode(cqe)) {
 201         case MLX5_CQE_RESP_WR_IMM:
 202                 wc->opcode      = IB_WC_RECV_RDMA_WITH_IMM;
 203                 wc->wc_flags    = IB_WC_WITH_IMM;
 204                 wc->ex.imm_data = cqe->imm_inval_pkey;
 205                 break;
 206         case MLX5_CQE_RESP_SEND:
 207                 wc->opcode   = IB_WC_RECV;
 208                 wc->wc_flags = IB_WC_IP_CSUM_OK;
 209                 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
 210                                (cqe->hds_ip_ext & CQE_L4_OK))))
 211                         wc->wc_flags = 0;
 212                 break;
 213         case MLX5_CQE_RESP_SEND_IMM:
 214                 wc->opcode      = IB_WC_RECV;
 215                 wc->wc_flags    = IB_WC_WITH_IMM;
 216                 wc->ex.imm_data = cqe->imm_inval_pkey;
 217                 break;
 218         case MLX5_CQE_RESP_SEND_INV:
 219                 wc->opcode      = IB_WC_RECV;
 220                 wc->wc_flags    = IB_WC_WITH_INVALIDATE;
 221                 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
 222                 break;
 223         }
 224         wc->src_qp         = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
 225         wc->dlid_path_bits = cqe->ml_path;
 226         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
 227         wc->wc_flags |= g ? IB_WC_GRH : 0;
 228         if (unlikely(is_qp1(qp->ibqp.qp_type))) {
 229                 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
 230
 231                 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
 232                                     &wc->pkey_index);
 233         } else {
 234                 wc->pkey_index = 0;
 235         }
 236
 237         if (ll != IB_LINK_LAYER_ETHERNET) {
 238                 wc->slid = be16_to_cpu(cqe->slid);
 239                 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
 240                 return;
 241         }
 242
 243         wc->slid = 0;
 244         vlan_present = cqe->l4_l3_hdr_type & 0x1;
 245         roce_packet_type   = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
 246         if (vlan_present) {
 247                 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
 248                 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
 249                 wc->wc_flags |= IB_WC_WITH_VLAN;
 250         } else {
 251                 wc->sl = 0;
 252         }
 253
 254         switch (roce_packet_type) {
 255         case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
 256                 wc->network_hdr_type = RDMA_NETWORK_IB;
 257                 break;
 258         case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
 259                 wc->network_hdr_type = RDMA_NETWORK_IPV6;
 260                 break;
 261         case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
 262                 wc->network_hdr_type = RDMA_NETWORK_IPV4;
 263                 break;
 264         }
 265         wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
 266 }
 267
 268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
 269 {
 270         mlx5_ib_warn(dev, "dump error cqe\n");
 271         mlx5_dump_err_cqe(dev->mdev, cqe);
 272 }
 273
 274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
 275                                   struct mlx5_err_cqe *cqe,
 276                                   struct ib_wc *wc)
 277 {
 278         int dump = 1;
 279
 280         switch (cqe->syndrome) {
 281         case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
 282                 wc->status = IB_WC_LOC_LEN_ERR;
 283                 break;
 284         case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
 285                 wc->status = IB_WC_LOC_QP_OP_ERR;
 286                 break;
 287         case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
 288                 wc->status = IB_WC_LOC_PROT_ERR;
 289                 break;
 290         case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
 291                 dump = 0;
 292                 wc->status = IB_WC_WR_FLUSH_ERR;
 293                 break;
 294         case MLX5_CQE_SYNDROME_MW_BIND_ERR:
 295                 wc->status = IB_WC_MW_BIND_ERR;
 296                 break;
 297         case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
 298                 wc->status = IB_WC_BAD_RESP_ERR;
 299                 break;
 300         case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
 301                 wc->status = IB_WC_LOC_ACCESS_ERR;
 302                 break;
 303         case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
 304                 wc->status = IB_WC_REM_INV_REQ_ERR;
 305                 break;
 306         case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
 307                 wc->status = IB_WC_REM_ACCESS_ERR;
 308                 break;
 309         case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
 310                 wc->status = IB_WC_REM_OP_ERR;
 311                 break;
 312         case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
 313                 wc->status = IB_WC_RETRY_EXC_ERR;
 314                 dump = 0;
 315                 break;
 316         case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
 317                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
 318                 dump = 0;
 319                 break;
 320         case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
 321                 wc->status = IB_WC_REM_ABORT_ERR;
 322                 break;
 323         default:
 324                 wc->status = IB_WC_GENERAL_ERR;
 325                 break;
 326         }
 327
 328         wc->vendor_err = cqe->vendor_err_synd;
 329         if (dump)
 330                 dump_cqe(dev, cqe);
 331 }
 332
 333 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
 334 {
 335         mlx5_frag_buf_free(dev->mdev, &buf->frag_buf);
 336 }
 337
 338 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
 339                              struct ib_sig_err *item)
 340 {
 341         u16 syndrome = be16_to_cpu(cqe->syndrome);
 342
 343 #define GUARD_ERR   (1 << 13)
 344 #define APPTAG_ERR  (1 << 12)
 345 #define REFTAG_ERR  (1 << 11)
 346
 347         if (syndrome & GUARD_ERR) {
 348                 item->err_type = IB_SIG_BAD_GUARD;
 349                 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
 350                 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
 351         } else
 352         if (syndrome & REFTAG_ERR) {
 353                 item->err_type = IB_SIG_BAD_REFTAG;
 354                 item->expected = be32_to_cpu(cqe->expected_reftag);
 355                 item->actual = be32_to_cpu(cqe->actual_reftag);
 356         } else
 357         if (syndrome & APPTAG_ERR) {
 358                 item->err_type = IB_SIG_BAD_APPTAG;
 359                 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
 360                 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
 361         } else {
 362                 pr_err("Got signature completion error with bad syndrome %04x\n",
 363                        syndrome);
 364         }
 365
 366         item->sig_err_offset = be64_to_cpu(cqe->err_offset);
 367         item->key = be32_to_cpu(cqe->mkey);
 368 }
 369
 370 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc,
 371                     int *npolled, int is_send)
 372 {
 373         struct mlx5_ib_wq *wq;
 374         unsigned int cur;
 375         int np;
 376         int i;
 377
 378         wq = (is_send) ? &qp->sq : &qp->rq;
 379         cur = wq->head - wq->tail;
 380         np = *npolled;
 381
 382         if (cur == 0)
 383                 return;
 384
 385         for (i = 0;  i < cur && np < num_entries; i++) {
 386                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 387                 wc->status = IB_WC_WR_FLUSH_ERR;
 388                 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
 389                 wq->tail++;
 390                 np++;
 391                 wc->qp = &qp->ibqp;
 392                 wc++;
 393         }
 394         *npolled = np;
 395 }
 396
 397 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
 398                                  struct ib_wc *wc, int *npolled)
 399 {
 400         struct mlx5_ib_qp *qp;
 401
 402         *npolled = 0;
 403         /* Find uncompleted WQEs belonging to that cq and return mmics ones */
 404         list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
 405                 sw_comp(qp, num_entries, wc + *npolled, npolled, true);
 406                 if (*npolled >= num_entries)
 407                         return;
 408         }
 409
 410         list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
 411                 sw_comp(qp, num_entries, wc + *npolled, npolled, false);
 412                 if (*npolled >= num_entries)
 413                         return;
 414         }
 415 }
 416
 417 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
 418                          struct mlx5_ib_qp **cur_qp,
 419                          struct ib_wc *wc)
 420 {
 421         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
 422         struct mlx5_err_cqe *err_cqe;
 423         struct mlx5_cqe64 *cqe64;
 424         struct mlx5_core_qp *mqp;
 425         struct mlx5_ib_wq *wq;
 426         struct mlx5_sig_err_cqe *sig_err_cqe;
 427         struct mlx5_core_mkey *mmkey;
 428         struct mlx5_ib_mr *mr;
 429         uint8_t opcode;
 430         uint32_t qpn;
 431         u16 wqe_ctr;
 432         void *cqe;
 433         int idx;
 434
 435 repoll:
 436         cqe = next_cqe_sw(cq);
 437         if (!cqe)
 438                 return -EAGAIN;
 439
 440         cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
 441
 442         ++cq->mcq.cons_index;
 443
 444         /* Make sure we read CQ entry contents after we've checked the
 445          * ownership bit.
 446          */
 447         rmb();
 448
 449         opcode = get_cqe_opcode(cqe64);
 450         if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
 451                 if (likely(cq->resize_buf)) {
 452                         free_cq_buf(dev, &cq->buf);
 453                         cq->buf = *cq->resize_buf;
 454                         kfree(cq->resize_buf);
 455                         cq->resize_buf = NULL;
 456                         goto repoll;
 457                 } else {
 458                         mlx5_ib_warn(dev, "unexpected resize cqe\n");
 459                 }
 460         }
 461
 462         qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
 463         if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
 464                 /* We do not have to take the QP table lock here,
 465                  * because CQs will be locked while QPs are removed
 466                  * from the table.
 467                  */
 468                 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
 469                 *cur_qp = to_mibqp(mqp);
 470         }
 471
 472         wc->qp  = &(*cur_qp)->ibqp;
 473         switch (opcode) {
 474         case MLX5_CQE_REQ:
 475                 wq = &(*cur_qp)->sq;
 476                 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 477                 idx = wqe_ctr & (wq->wqe_cnt - 1);
 478                 handle_good_req(wc, cqe64, wq, idx);
 479                 wc->wr_id = wq->wrid[idx];
 480                 wq->tail = wq->wqe_head[idx] + 1;
 481                 wc->status = IB_WC_SUCCESS;
 482                 break;
 483         case MLX5_CQE_RESP_WR_IMM:
 484         case MLX5_CQE_RESP_SEND:
 485         case MLX5_CQE_RESP_SEND_IMM:
 486         case MLX5_CQE_RESP_SEND_INV:
 487                 handle_responder(wc, cqe64, *cur_qp);
 488                 wc->status = IB_WC_SUCCESS;
 489                 break;
 490         case MLX5_CQE_RESIZE_CQ:
 491                 break;
 492         case MLX5_CQE_REQ_ERR:
 493         case MLX5_CQE_RESP_ERR:
 494                 err_cqe = (struct mlx5_err_cqe *)cqe64;
 495                 mlx5_handle_error_cqe(dev, err_cqe, wc);
 496                 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
 497                             opcode == MLX5_CQE_REQ_ERR ?
 498                             "Requestor" : "Responder", cq->mcq.cqn);
 499                 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
 500                             err_cqe->syndrome, err_cqe->vendor_err_synd);
 501                 if (opcode == MLX5_CQE_REQ_ERR) {
 502                         wq = &(*cur_qp)->sq;
 503                         wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 504                         idx = wqe_ctr & (wq->wqe_cnt - 1);
 505                         wc->wr_id = wq->wrid[idx];
 506                         wq->tail = wq->wqe_head[idx] + 1;
 507                 } else {
 508                         struct mlx5_ib_srq *srq;
 509
 510                         if ((*cur_qp)->ibqp.srq) {
 511                                 srq = to_msrq((*cur_qp)->ibqp.srq);
 512                                 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 513                                 wc->wr_id = srq->wrid[wqe_ctr];
 514                                 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
 515                         } else {
 516                                 wq = &(*cur_qp)->rq;
 517                                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 518                                 ++wq->tail;
 519                         }
 520                 }
 521                 break;
 522         case MLX5_CQE_SIG_ERR:
 523                 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
 524
 525                 read_lock(&dev->mdev->priv.mkey_table.lock);
 526                 mmkey = __mlx5_mr_lookup(dev->mdev,
 527                                          mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
 528                 mr = to_mibmr(mmkey);
 529                 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
 530                 mr->sig->sig_err_exists = true;
 531                 mr->sig->sigerr_count++;
 532
 533                 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
 534                              cq->mcq.cqn, mr->sig->err_item.key,
 535                              mr->sig->err_item.err_type,
 536                              mr->sig->err_item.sig_err_offset,
 537                              mr->sig->err_item.expected,
 538                              mr->sig->err_item.actual);
 539
 540                 read_unlock(&dev->mdev->priv.mkey_table.lock);
 541                 goto repoll;
 542         }
 543
 544         return 0;
 545 }
 546
 547 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
 548                         struct ib_wc *wc, bool is_fatal_err)
 549 {
 550         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
 551         struct mlx5_ib_wc *soft_wc, *next;
 552         int npolled = 0;
 553
 554         list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
 555                 if (npolled >= num_entries)
 556                         break;
 557
 558                 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
 559                             cq->mcq.cqn);
 560
 561                 if (unlikely(is_fatal_err)) {
 562                         soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
 563                         soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
 564                 }
 565                 wc[npolled++] = soft_wc->wc;
 566                 list_del(&soft_wc->list);
 567                 kfree(soft_wc);
 568         }
 569
 570         return npolled;
 571 }
 572
 573 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
 574 {
 575         struct mlx5_ib_cq *cq = to_mcq(ibcq);
 576         struct mlx5_ib_qp *cur_qp = NULL;
 577         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
 578         struct mlx5_core_dev *mdev = dev->mdev;
 579         unsigned long flags;
 580         int soft_polled = 0;
 581         int npolled;
 582
 583         spin_lock_irqsave(&cq->lock, flags);
 584         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 585                 /* make sure no soft wqe's are waiting */
 586                 if (unlikely(!list_empty(&cq->wc_list)))
 587                         soft_polled = poll_soft_wc(cq, num_entries, wc, true);
 588
 589                 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
 590                                      wc + soft_polled, &npolled);
 591                 goto out;
 592         }
 593
 594         if (unlikely(!list_empty(&cq->wc_list)))
 595                 soft_polled = poll_soft_wc(cq, num_entries, wc, false);
 596
 597         for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
 598                 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
 599                         break;
 600         }
 601
 602         if (npolled)
 603                 mlx5_cq_set_ci(&cq->mcq);
 604 out:
 605         spin_unlock_irqrestore(&cq->lock, flags);
 606
 607         return soft_polled + npolled;
 608 }
 609
 610 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
 611 {
 612         struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
 613         struct mlx5_ib_cq *cq = to_mcq(ibcq);
 614         void __iomem *uar_page = mdev->priv.uar->map;
 615         unsigned long irq_flags;
 616         int ret = 0;
 617
 618         spin_lock_irqsave(&cq->lock, irq_flags);
 619         if (cq->notify_flags != IB_CQ_NEXT_COMP)
 620                 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
 621
 622         if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
 623                 ret = 1;
 624         spin_unlock_irqrestore(&cq->lock, irq_flags);
 625
 626         mlx5_cq_arm(&cq->mcq,
 627                     (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
 628                     MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
 629                     uar_page, to_mcq(ibcq)->mcq.cons_index);
 630
 631         return ret;
 632 }
 633
 634 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev,
 635                              struct mlx5_ib_cq_buf *buf,
 636                              int nent,
 637                              int cqe_size)
 638 {
 639         struct mlx5_frag_buf *frag_buf = &buf->frag_buf;
 640         u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0);
 641         u8 log_wq_sz     = ilog2(cqe_size);
 642         int err;
 643
 644         err = mlx5_frag_buf_alloc_node(dev->mdev,
 645                                        nent * cqe_size,
 646                                        frag_buf,
 647                                        dev->mdev->priv.numa_node);
 648         if (err)
 649                 return err;
 650
 651         mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc);
 652
 653         buf->cqe_size = cqe_size;
 654         buf->nent = nent;
 655
 656         return 0;
 657 }
 658
 659 enum {
 660         MLX5_CQE_RES_FORMAT_HASH = 0,
 661         MLX5_CQE_RES_FORMAT_CSUM = 1,
 662         MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3,
 663 };
 664
 665 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format)
 666 {
 667         switch (format) {
 668         case MLX5_IB_CQE_RES_FORMAT_HASH:
 669                 return MLX5_CQE_RES_FORMAT_HASH;
 670         case MLX5_IB_CQE_RES_FORMAT_CSUM:
 671                 return MLX5_CQE_RES_FORMAT_CSUM;
 672         case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX:
 673                 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
 674                         return MLX5_CQE_RES_FORMAT_CSUM_STRIDX;
 675                 return -EOPNOTSUPP;
 676         default:
 677                 return -EINVAL;
 678         }
 679 }
 680
 681 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 682                           struct ib_ucontext *context, struct mlx5_ib_cq *cq,
 683                           int entries, u32 **cqb,
 684                           int *cqe_size, int *index, int *inlen)
 685 {
 686         struct mlx5_ib_create_cq ucmd = {};
 687         size_t ucmdlen;
 688         int page_shift;
 689         __be64 *pas;
 690         int npages;
 691         int ncont;
 692         void *cqc;
 693         int err;
 694
 695         ucmdlen = udata->inlen < sizeof(ucmd) ?
 696                   (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
 697
 698         if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
 699                 return -EFAULT;
 700
 701         if (ucmdlen == sizeof(ucmd) &&
 702             (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
 703                 return -EINVAL;
 704
 705         if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
 706                 return -EINVAL;
 707
 708         *cqe_size = ucmd.cqe_size;
 709
 710         cq->buf.umem =
 711                 ib_umem_get(udata, ucmd.buf_addr, entries * ucmd.cqe_size,
 712                             IB_ACCESS_LOCAL_WRITE, 1);
 713         if (IS_ERR(cq->buf.umem)) {
 714                 err = PTR_ERR(cq->buf.umem);
 715                 return err;
 716         }
 717
 718         err = mlx5_ib_db_map_user(to_mucontext(context), udata, ucmd.db_addr,
 719                                   &cq->db);
 720         if (err)
 721                 goto err_umem;
 722
 723         mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
 724                            &ncont, NULL);
 725         mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
 726                     ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
 727
 728         *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 729                  MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
 730         *cqb = kvzalloc(*inlen, GFP_KERNEL);
 731         if (!*cqb) {
 732                 err = -ENOMEM;
 733                 goto err_db;
 734         }
 735
 736         pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
 737         mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
 738
 739         cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
 740         MLX5_SET(cqc, cqc, log_page_size,
 741                  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 742
 743         *index = to_mucontext(context)->bfregi.sys_pages[0];
 744
 745         if (ucmd.cqe_comp_en == 1) {
 746                 int mini_cqe_format;
 747
 748                 if (!((*cqe_size == 128 &&
 749                        MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
 750                       (*cqe_size == 64  &&
 751                        MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
 752                         err = -EOPNOTSUPP;
 753                         mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
 754                                      *cqe_size);
 755                         goto err_cqb;
 756                 }
 757
 758                 mini_cqe_format =
 759                         mini_cqe_res_format_to_hw(dev,
 760                                                   ucmd.cqe_comp_res_format);
 761                 if (mini_cqe_format < 0) {
 762                         err = mini_cqe_format;
 763                         mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n",
 764                                     ucmd.cqe_comp_res_format, err);
 765                         goto err_cqb;
 766                 }
 767
 768                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
 769                 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format);
 770         }
 771
 772         if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
 773                 if (*cqe_size != 128 ||
 774                     !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
 775                         err = -EOPNOTSUPP;
 776                         mlx5_ib_warn(dev,
 777                                      "CQE padding is not supported for CQE size of %dB!\n",
 778                                      *cqe_size);
 779                         goto err_cqb;
 780                 }
 781
 782                 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
 783         }
 784
 785         MLX5_SET(create_cq_in, *cqb, uid, to_mucontext(context)->devx_uid);
 786         return 0;
 787
 788 err_cqb:
 789         kvfree(*cqb);
 790
 791 err_db:
 792         mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
 793
 794 err_umem:
 795         ib_umem_release(cq->buf.umem);
 796         return err;
 797 }
 798
 799 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
 800 {
 801         mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
 802         ib_umem_release(cq->buf.umem);
 803 }
 804
 805 static void init_cq_frag_buf(struct mlx5_ib_cq *cq,
 806                              struct mlx5_ib_cq_buf *buf)
 807 {
 808         int i;
 809         void *cqe;
 810         struct mlx5_cqe64 *cqe64;
 811
 812         for (i = 0; i < buf->nent; i++) {
 813                 cqe = get_cqe(cq, i);
 814                 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
 815                 cqe64->op_own = MLX5_CQE_INVALID << 4;
 816         }
 817 }
 818
 819 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
 820                             int entries, int cqe_size,
 821                             u32 **cqb, int *index, int *inlen)
 822 {
 823         __be64 *pas;
 824         void *cqc;
 825         int err;
 826
 827         err = mlx5_db_alloc(dev->mdev, &cq->db);
 828         if (err)
 829                 return err;
 830
 831         cq->mcq.set_ci_db  = cq->db.db;
 832         cq->mcq.arm_db     = cq->db.db + 1;
 833         cq->mcq.cqe_sz = cqe_size;
 834
 835         err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size);
 836         if (err)
 837                 goto err_db;
 838
 839         init_cq_frag_buf(cq, &cq->buf);
 840
 841         *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 842                  MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
 843                  cq->buf.frag_buf.npages;
 844         *cqb = kvzalloc(*inlen, GFP_KERNEL);
 845         if (!*cqb) {
 846                 err = -ENOMEM;
 847                 goto err_buf;
 848         }
 849
 850         pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
 851         mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas);
 852
 853         cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
 854         MLX5_SET(cqc, cqc, log_page_size,
 855                  cq->buf.frag_buf.page_shift -
 856                  MLX5_ADAPTER_PAGE_SHIFT);
 857
 858         *index = dev->mdev->priv.uar->index;
 859
 860         return 0;
 861
 862 err_buf:
 863         free_cq_buf(dev, &cq->buf);
 864
 865 err_db:
 866         mlx5_db_free(dev->mdev, &cq->db);
 867         return err;
 868 }
 869
 870 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
 871 {
 872         free_cq_buf(dev, &cq->buf);
 873         mlx5_db_free(dev->mdev, &cq->db);
 874 }
 875
 876 static void notify_soft_wc_handler(struct work_struct *work)
 877 {
 878         struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
 879                                              notify_work);
 880
 881         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 882 }
 883
 884 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
 885                                 const struct ib_cq_init_attr *attr,
 886                                 struct ib_ucontext *context,
 887                                 struct ib_udata *udata)
 888 {
 889         int entries = attr->cqe;
 890         int vector = attr->comp_vector;
 891         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 892         struct mlx5_ib_cq *cq;
 893         int uninitialized_var(index);
 894         int uninitialized_var(inlen);
 895         u32 *cqb = NULL;
 896         void *cqc;
 897         int cqe_size;
 898         unsigned int irqn;
 899         int eqn;
 900         int err;
 901
 902         if (entries < 0 ||
 903             (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
 904                 return ERR_PTR(-EINVAL);
 905
 906         if (check_cq_create_flags(attr->flags))
 907                 return ERR_PTR(-EOPNOTSUPP);
 908
 909         entries = roundup_pow_of_two(entries + 1);
 910         if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
 911                 return ERR_PTR(-EINVAL);
 912
 913         cq = kzalloc(sizeof(*cq), GFP_KERNEL);
 914         if (!cq)
 915                 return ERR_PTR(-ENOMEM);
 916
 917         cq->ibcq.cqe = entries - 1;
 918         mutex_init(&cq->resize_mutex);
 919         spin_lock_init(&cq->lock);
 920         cq->resize_buf = NULL;
 921         cq->resize_umem = NULL;
 922         cq->create_flags = attr->flags;
 923         INIT_LIST_HEAD(&cq->list_send_qp);
 924         INIT_LIST_HEAD(&cq->list_recv_qp);
 925
 926         if (context) {
 927                 err = create_cq_user(dev, udata, context, cq, entries,
 928                                      &cqb, &cqe_size, &index, &inlen);
 929                 if (err)
 930                         goto err_create;
 931         } else {
 932                 cqe_size = cache_line_size() == 128 ? 128 : 64;
 933                 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
 934                                        &index, &inlen);
 935                 if (err)
 936                         goto err_create;
 937
 938                 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
 939         }
 940
 941         err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
 942         if (err)
 943                 goto err_cqb;
 944
 945         cq->cqe_size = cqe_size;
 946
 947         cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
 948         MLX5_SET(cqc, cqc, cqe_sz,
 949                  cqe_sz_to_mlx_sz(cqe_size,
 950                                   cq->private_flags &
 951                                   MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
 952         MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
 953         MLX5_SET(cqc, cqc, uar_page, index);
 954         MLX5_SET(cqc, cqc, c_eqn, eqn);
 955         MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
 956         if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
 957                 MLX5_SET(cqc, cqc, oi, 1);
 958
 959         err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
 960         if (err)
 961                 goto err_cqb;
 962
 963         mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
 964         cq->mcq.irqn = irqn;
 965         if (context)
 966                 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
 967         else
 968                 cq->mcq.comp  = mlx5_ib_cq_comp;
 969         cq->mcq.event = mlx5_ib_cq_event;
 970
 971         INIT_LIST_HEAD(&cq->wc_list);
 972
 973         if (context)
 974                 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
 975                         err = -EFAULT;
 976                         goto err_cmd;
 977                 }
 978
 979
 980         kvfree(cqb);
 981         return &cq->ibcq;
 982
 983 err_cmd:
 984         mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
 985
 986 err_cqb:
 987         kvfree(cqb);
 988         if (context)
 989                 destroy_cq_user(cq, context);
 990         else
 991                 destroy_cq_kernel(dev, cq);
 992
 993 err_create:
 994         kfree(cq);
 995
 996         return ERR_PTR(err);
 997 }
 998
 999
1000 int mlx5_ib_destroy_cq(struct ib_cq *cq)
1001 {
1002         struct mlx5_ib_dev *dev = to_mdev(cq->device);
1003         struct mlx5_ib_cq *mcq = to_mcq(cq);
1004         struct ib_ucontext *context = NULL;
1005
1006         if (cq->uobject)
1007                 context = cq->uobject->context;
1008
1009         mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1010         if (context)
1011                 destroy_cq_user(mcq, context);
1012         else
1013                 destroy_cq_kernel(dev, mcq);
1014
1015         kfree(mcq);
1016
1017         return 0;
1018 }
1019
1020 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1021 {
1022         return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1023 }
1024
1025 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1026 {
1027         struct mlx5_cqe64 *cqe64, *dest64;
1028         void *cqe, *dest;
1029         u32 prod_index;
1030         int nfreed = 0;
1031         u8 owner_bit;
1032
1033         if (!cq)
1034                 return;
1035
1036         /* First we need to find the current producer index, so we
1037          * know where to start cleaning from.  It doesn't matter if HW
1038          * adds new entries after this loop -- the QP we're worried
1039          * about is already in RESET, so the new entries won't come
1040          * from our QP and therefore don't need to be checked.
1041          */
1042         for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1043                 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1044                         break;
1045
1046         /* Now sweep backwards through the CQ, removing CQ entries
1047          * that match our QP by copying older entries on top of them.
1048          */
1049         while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1050                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1051                 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1052                 if (is_equal_rsn(cqe64, rsn)) {
1053                         if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1054                                 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1055                         ++nfreed;
1056                 } else if (nfreed) {
1057                         dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1058                         dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1059                         owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1060                         memcpy(dest, cqe, cq->mcq.cqe_sz);
1061                         dest64->op_own = owner_bit |
1062                                 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1063                 }
1064         }
1065
1066         if (nfreed) {
1067                 cq->mcq.cons_index += nfreed;
1068                 /* Make sure update of buffer contents is done before
1069                  * updating consumer index.
1070                  */
1071                 wmb();
1072                 mlx5_cq_set_ci(&cq->mcq);
1073         }
1074 }
1075
1076 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1077 {
1078         if (!cq)
1079                 return;
1080
1081         spin_lock_irq(&cq->lock);
1082         __mlx5_ib_cq_clean(cq, qpn, srq);
1083         spin_unlock_irq(&cq->lock);
1084 }
1085
1086 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1087 {
1088         struct mlx5_ib_dev *dev = to_mdev(cq->device);
1089         struct mlx5_ib_cq *mcq = to_mcq(cq);
1090         int err;
1091
1092         if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1093                 return -EOPNOTSUPP;
1094
1095         if (cq_period > MLX5_MAX_CQ_PERIOD)
1096                 return -EINVAL;
1097
1098         err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1099                                              cq_period, cq_count);
1100         if (err)
1101                 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1102
1103         return err;
1104 }
1105
1106 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1107                        int entries, struct ib_udata *udata, int *npas,
1108                        int *page_shift, int *cqe_size)
1109 {
1110         struct mlx5_ib_resize_cq ucmd;
1111         struct ib_umem *umem;
1112         int err;
1113         int npages;
1114
1115         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1116         if (err)
1117                 return err;
1118
1119         if (ucmd.reserved0 || ucmd.reserved1)
1120                 return -EINVAL;
1121
1122         /* check multiplication overflow */
1123         if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1124                 return -EINVAL;
1125
1126         umem = ib_umem_get(udata, ucmd.buf_addr,
1127                            (size_t)ucmd.cqe_size * entries,
1128                            IB_ACCESS_LOCAL_WRITE, 1);
1129         if (IS_ERR(umem)) {
1130                 err = PTR_ERR(umem);
1131                 return err;
1132         }
1133
1134         mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1135                            npas, NULL);
1136
1137         cq->resize_umem = umem;
1138         *cqe_size = ucmd.cqe_size;
1139
1140         return 0;
1141 }
1142
1143 static void un_resize_user(struct mlx5_ib_cq *cq)
1144 {
1145         ib_umem_release(cq->resize_umem);
1146 }
1147
1148 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1149                          int entries, int cqe_size)
1150 {
1151         int err;
1152
1153         cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1154         if (!cq->resize_buf)
1155                 return -ENOMEM;
1156
1157         err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size);
1158         if (err)
1159                 goto ex;
1160
1161         init_cq_frag_buf(cq, cq->resize_buf);
1162
1163         return 0;
1164
1165 ex:
1166         kfree(cq->resize_buf);
1167         return err;
1168 }
1169
1170 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1171 {
1172         free_cq_buf(dev, cq->resize_buf);
1173         cq->resize_buf = NULL;
1174 }
1175
1176 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1177 {
1178         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1179         struct mlx5_cqe64 *scqe64;
1180         struct mlx5_cqe64 *dcqe64;
1181         void *start_cqe;
1182         void *scqe;
1183         void *dcqe;
1184         int ssize;
1185         int dsize;
1186         int i;
1187         u8 sw_own;
1188
1189         ssize = cq->buf.cqe_size;
1190         dsize = cq->resize_buf->cqe_size;
1191         if (ssize != dsize) {
1192                 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1193                 return -EINVAL;
1194         }
1195
1196         i = cq->mcq.cons_index;
1197         scqe = get_sw_cqe(cq, i);
1198         scqe64 = ssize == 64 ? scqe : scqe + 64;
1199         start_cqe = scqe;
1200         if (!scqe) {
1201                 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1202                 return -EINVAL;
1203         }
1204
1205         while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) {
1206                 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc,
1207                                              (i + 1) & cq->resize_buf->nent);
1208                 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1209                 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1210                 memcpy(dcqe, scqe, dsize);
1211                 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1212
1213                 ++i;
1214                 scqe = get_sw_cqe(cq, i);
1215                 scqe64 = ssize == 64 ? scqe : scqe + 64;
1216                 if (!scqe) {
1217                         mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1218                         return -EINVAL;
1219                 }
1220
1221                 if (scqe == start_cqe) {
1222                         pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1223                                 cq->mcq.cqn);
1224                         return -ENOMEM;
1225                 }
1226         }
1227         ++cq->mcq.cons_index;
1228         return 0;
1229 }
1230
1231 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1232 {
1233         struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1234         struct mlx5_ib_cq *cq = to_mcq(ibcq);
1235         void *cqc;
1236         u32 *in;
1237         int err;
1238         int npas;
1239         __be64 *pas;
1240         int page_shift;
1241         int inlen;
1242         int uninitialized_var(cqe_size);
1243         unsigned long flags;
1244
1245         if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1246                 pr_info("Firmware does not support resize CQ\n");
1247                 return -ENOSYS;
1248         }
1249
1250         if (entries < 1 ||
1251             entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1252                 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1253                              entries,
1254                              1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1255                 return -EINVAL;
1256         }
1257
1258         entries = roundup_pow_of_two(entries + 1);
1259         if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1260                 return -EINVAL;
1261
1262         if (entries == ibcq->cqe + 1)
1263                 return 0;
1264
1265         mutex_lock(&cq->resize_mutex);
1266         if (udata) {
1267                 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1268                                   &cqe_size);
1269         } else {
1270                 cqe_size = 64;
1271                 err = resize_kernel(dev, cq, entries, cqe_size);
1272                 if (!err) {
1273                         struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf;
1274
1275                         npas = frag_buf->npages;
1276                         page_shift = frag_buf->page_shift;
1277                 }
1278         }
1279
1280         if (err)
1281                 goto ex;
1282
1283         inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1284                 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1285
1286         in = kvzalloc(inlen, GFP_KERNEL);
1287         if (!in) {
1288                 err = -ENOMEM;
1289                 goto ex_resize;
1290         }
1291
1292         pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1293         if (udata)
1294                 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1295                                      pas, 0);
1296         else
1297                 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas);
1298
1299         MLX5_SET(modify_cq_in, in,
1300                  modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1301                  MLX5_MODIFY_CQ_MASK_LOG_SIZE  |
1302                  MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1303                  MLX5_MODIFY_CQ_MASK_PG_SIZE);
1304
1305         cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1306
1307         MLX5_SET(cqc, cqc, log_page_size,
1308                  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1309         MLX5_SET(cqc, cqc, cqe_sz,
1310                  cqe_sz_to_mlx_sz(cqe_size,
1311                                   cq->private_flags &
1312                                   MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1313         MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1314
1315         MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1316         MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1317
1318         err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1319         if (err)
1320                 goto ex_alloc;
1321
1322         if (udata) {
1323                 cq->ibcq.cqe = entries - 1;
1324                 ib_umem_release(cq->buf.umem);
1325                 cq->buf.umem = cq->resize_umem;
1326                 cq->resize_umem = NULL;
1327         } else {
1328                 struct mlx5_ib_cq_buf tbuf;
1329                 int resized = 0;
1330
1331                 spin_lock_irqsave(&cq->lock, flags);
1332                 if (cq->resize_buf) {
1333                         err = copy_resize_cqes(cq);
1334                         if (!err) {
1335                                 tbuf = cq->buf;
1336                                 cq->buf = *cq->resize_buf;
1337                                 kfree(cq->resize_buf);
1338                                 cq->resize_buf = NULL;
1339                                 resized = 1;
1340                         }
1341                 }
1342                 cq->ibcq.cqe = entries - 1;
1343                 spin_unlock_irqrestore(&cq->lock, flags);
1344                 if (resized)
1345                         free_cq_buf(dev, &tbuf);
1346         }
1347         mutex_unlock(&cq->resize_mutex);
1348
1349         kvfree(in);
1350         return 0;
1351
1352 ex_alloc:
1353         kvfree(in);
1354
1355 ex_resize:
1356         if (udata)
1357                 un_resize_user(cq);
1358         else
1359                 un_resize_kernel(dev, cq);
1360 ex:
1361         mutex_unlock(&cq->resize_mutex);
1362         return err;
1363 }
1364
1365 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq)
1366 {
1367         struct mlx5_ib_cq *cq;
1368
1369         if (!ibcq)
1370                 return 128;
1371
1372         cq = to_mcq(ibcq);
1373         return cq->cqe_size;
1374 }
1375
1376 /* Called from atomic context */
1377 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1378 {
1379         struct mlx5_ib_wc *soft_wc;
1380         struct mlx5_ib_cq *cq = to_mcq(ibcq);
1381         unsigned long flags;
1382
1383         soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1384         if (!soft_wc)
1385                 return -ENOMEM;
1386
1387         soft_wc->wc = *wc;
1388         spin_lock_irqsave(&cq->lock, flags);
1389         list_add_tail(&soft_wc->list, &cq->wc_list);
1390         if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1391             wc->status != IB_WC_SUCCESS) {
1392                 cq->notify_flags = 0;
1393                 schedule_work(&cq->notify_work);
1394         }
1395         spin_unlock_irqrestore(&cq->lock, flags);
1396
1397         return 0;
1398 }