drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/etherdevice.h>
  36 #include <net/ip.h>
  37 #include <linux/slab.h>
  38 #include <linux/netdevice.h>
  39
  40 #include <rdma/ib_cache.h>
  41 #include <rdma/ib_pack.h>
  42 #include <rdma/ib_addr.h>
  43 #include <rdma/ib_mad.h>
  44
  45 #include <linux/mlx4/driver.h>
  46 #include <linux/mlx4/qp.h>
  47
  48 #include "mlx4_ib.h"
  49 #include <rdma/mlx4-abi.h>
  50
  51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  52                              struct mlx4_ib_cq *recv_cq);
  53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  54                                struct mlx4_ib_cq *recv_cq);
  55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
  56
  57 enum {
  58         MLX4_IB_ACK_REQ_FREQ    = 8,
  59 };
  60
  61 enum {
  62         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  63         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  64         MLX4_IB_LINK_TYPE_IB            = 0,
  65         MLX4_IB_LINK_TYPE_ETH           = 1
  66 };
  67
  68 enum {
  69         /*
  70          * Largest possible UD header: send with GRH and immediate
  71          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  72          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  73          * biggest case)
  74          */
  75         MLX4_IB_UD_HEADER_SIZE          = 82,
  76         MLX4_IB_LSO_HEADER_SPARE        = 128,
  77 };
  78
  79 struct mlx4_ib_sqp {
  80         struct mlx4_ib_qp       qp;
  81         int                     pkey_index;
  82         u32                     qkey;
  83         u32                     send_psn;
  84         struct ib_ud_header     ud_header;
  85         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  86         struct ib_qp            *roce_v2_gsi;
  87 };
  88
  89 enum {
  90         MLX4_IB_MIN_SQ_STRIDE   = 6,
  91         MLX4_IB_CACHE_LINE_SIZE = 64,
  92 };
  93
  94 enum {
  95         MLX4_RAW_QP_MTU         = 7,
  96         MLX4_RAW_QP_MSGMAX      = 31,
  97 };
  98
  99 #ifndef ETH_ALEN
 100 #define ETH_ALEN        6
 101 #endif
 102
 103 static const __be32 mlx4_ib_opcode[] = {
 104         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 105         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 106         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 107         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 108         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 109         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 110         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 111         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 112         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 113         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 114         [IB_WR_REG_MR]                          = cpu_to_be32(MLX4_OPCODE_FMR),
 115         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 116         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 117 };
 118
 119 enum mlx4_ib_source_type {
 120         MLX4_IB_QP_SRC  = 0,
 121         MLX4_IB_RWQ_SRC = 1,
 122 };
 123
 124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 125 {
 126         return container_of(mqp, struct mlx4_ib_sqp, qp);
 127 }
 128
 129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 130 {
 131         if (!mlx4_is_master(dev->dev))
 132                 return 0;
 133
 134         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 135                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 136                 8 * MLX4_MFUNC_MAX;
 137 }
 138
 139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 140 {
 141         int proxy_sqp = 0;
 142         int real_sqp = 0;
 143         int i;
 144         /* PPF or Native -- real SQP */
 145         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 146                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 147                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 148         if (real_sqp)
 149                 return 1;
 150         /* VF or PF -- proxy SQP */
 151         if (mlx4_is_mfunc(dev->dev)) {
 152                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 153                         if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
 154                             qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
 155                                 proxy_sqp = 1;
 156                                 break;
 157                         }
 158                 }
 159         }
 160         if (proxy_sqp)
 161                 return 1;
 162
 163         return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
 164 }
 165
 166 /* used for INIT/CLOSE port logic */
 167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 168 {
 169         int proxy_qp0 = 0;
 170         int real_qp0 = 0;
 171         int i;
 172         /* PPF or Native -- real QP0 */
 173         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 174                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 175                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 176         if (real_qp0)
 177                 return 1;
 178         /* VF or PF -- proxy QP0 */
 179         if (mlx4_is_mfunc(dev->dev)) {
 180                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 181                         if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
 182                                 proxy_qp0 = 1;
 183                                 break;
 184                         }
 185                 }
 186         }
 187         return proxy_qp0;
 188 }
 189
 190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 191 {
 192         return mlx4_buf_offset(&qp->buf, offset);
 193 }
 194
 195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 196 {
 197         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 198 }
 199
 200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 201 {
 202         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 203 }
 204
 205 /*
 206  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 207  * first four bytes of every 64 byte chunk with
 208  *     0x7FFFFFF | (invalid_ownership_value << 31).
 209  *
 210  * When the max work request size is less than or equal to the WQE
 211  * basic block size, as an optimization, we can stamp all WQEs with
 212  * 0xffffffff, and skip the very first chunk of each WQE.
 213  */
 214 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 215 {
 216         __be32 *wqe;
 217         int i;
 218         int s;
 219         int ind;
 220         void *buf;
 221         __be32 stamp;
 222         struct mlx4_wqe_ctrl_seg *ctrl;
 223
 224         if (qp->sq_max_wqes_per_wr > 1) {
 225                 s = roundup(size, 1U << qp->sq.wqe_shift);
 226                 for (i = 0; i < s; i += 64) {
 227                         ind = (i >> qp->sq.wqe_shift) + n;
 228                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 229                                                        cpu_to_be32(0xffffffff);
 230                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 231                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 232                         *wqe = stamp;
 233                 }
 234         } else {
 235                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 236                 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
 237                 for (i = 64; i < s; i += 64) {
 238                         wqe = buf + i;
 239                         *wqe = cpu_to_be32(0xffffffff);
 240                 }
 241         }
 242 }
 243
 244 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 245 {
 246         struct mlx4_wqe_ctrl_seg *ctrl;
 247         struct mlx4_wqe_inline_seg *inl;
 248         void *wqe;
 249         int s;
 250
 251         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 252         s = sizeof(struct mlx4_wqe_ctrl_seg);
 253
 254         if (qp->ibqp.qp_type == IB_QPT_UD) {
 255                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 256                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 257                 memset(dgram, 0, sizeof *dgram);
 258                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 259                 s += sizeof(struct mlx4_wqe_datagram_seg);
 260         }
 261
 262         /* Pad the remainder of the WQE with an inline data segment. */
 263         if (size > s) {
 264                 inl = wqe + s;
 265                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 266         }
 267         ctrl->srcrb_flags = 0;
 268         ctrl->qpn_vlan.fence_size = size / 16;
 269         /*
 270          * Make sure descriptor is fully written before setting ownership bit
 271          * (because HW can start executing as soon as we do).
 272          */
 273         wmb();
 274
 275         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 276                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 277
 278         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 279 }
 280
 281 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 282 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 283 {
 284         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 285         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 286                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 287                 ind += s;
 288         }
 289         return ind;
 290 }
 291
 292 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 293 {
 294         struct ib_event event;
 295         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 296
 297         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 298                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 299
 300         if (ibqp->event_handler) {
 301                 event.device     = ibqp->device;
 302                 event.element.qp = ibqp;
 303                 switch (type) {
 304                 case MLX4_EVENT_TYPE_PATH_MIG:
 305                         event.event = IB_EVENT_PATH_MIG;
 306                         break;
 307                 case MLX4_EVENT_TYPE_COMM_EST:
 308                         event.event = IB_EVENT_COMM_EST;
 309                         break;
 310                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 311                         event.event = IB_EVENT_SQ_DRAINED;
 312                         break;
 313                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 314                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 315                         break;
 316                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 317                         event.event = IB_EVENT_QP_FATAL;
 318                         break;
 319                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 320                         event.event = IB_EVENT_PATH_MIG_ERR;
 321                         break;
 322                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 323                         event.event = IB_EVENT_QP_REQ_ERR;
 324                         break;
 325                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 326                         event.event = IB_EVENT_QP_ACCESS_ERR;
 327                         break;
 328                 default:
 329                         pr_warn("Unexpected event type %d "
 330                                "on QP %06x\n", type, qp->qpn);
 331                         return;
 332                 }
 333
 334                 ibqp->event_handler(&event, ibqp->qp_context);
 335         }
 336 }
 337
 338 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
 339 {
 340         pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
 341                             type, qp->qpn);
 342 }
 343
 344 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 345 {
 346         /*
 347          * UD WQEs must have a datagram segment.
 348          * RC and UC WQEs might have a remote address segment.
 349          * MLX WQEs need two extra inline data segments (for the UD
 350          * header and space for the ICRC).
 351          */
 352         switch (type) {
 353         case MLX4_IB_QPT_UD:
 354                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 355                         sizeof (struct mlx4_wqe_datagram_seg) +
 356                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 357         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 358         case MLX4_IB_QPT_PROXY_SMI:
 359         case MLX4_IB_QPT_PROXY_GSI:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 362         case MLX4_IB_QPT_TUN_SMI_OWNER:
 363         case MLX4_IB_QPT_TUN_GSI:
 364                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 365                         sizeof (struct mlx4_wqe_datagram_seg);
 366
 367         case MLX4_IB_QPT_UC:
 368                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 369                         sizeof (struct mlx4_wqe_raddr_seg);
 370         case MLX4_IB_QPT_RC:
 371                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 372                         sizeof (struct mlx4_wqe_masked_atomic_seg) +
 373                         sizeof (struct mlx4_wqe_raddr_seg);
 374         case MLX4_IB_QPT_SMI:
 375         case MLX4_IB_QPT_GSI:
 376                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 377                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 378                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 379                                            MLX4_INLINE_ALIGN) *
 380                               sizeof (struct mlx4_wqe_inline_seg),
 381                               sizeof (struct mlx4_wqe_data_seg)) +
 382                         ALIGN(4 +
 383                               sizeof (struct mlx4_wqe_inline_seg),
 384                               sizeof (struct mlx4_wqe_data_seg));
 385         default:
 386                 return sizeof (struct mlx4_wqe_ctrl_seg);
 387         }
 388 }
 389
 390 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 391                        int is_user, int has_rq, struct mlx4_ib_qp *qp,
 392                        u32 inl_recv_sz)
 393 {
 394         /* Sanity check RQ size before proceeding */
 395         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 396             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 397                 return -EINVAL;
 398
 399         if (!has_rq) {
 400                 if (cap->max_recv_wr || inl_recv_sz)
 401                         return -EINVAL;
 402
 403                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 404         } else {
 405                 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
 406                         sizeof(struct mlx4_wqe_data_seg);
 407                 u32 wqe_size;
 408
 409                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 410                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
 411                                 inl_recv_sz > max_inl_recv_sz))
 412                         return -EINVAL;
 413
 414                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 415                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 416                 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
 417                 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
 418         }
 419
 420         /* leave userspace return values as they were, so as not to break ABI */
 421         if (is_user) {
 422                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 423                 cap->max_recv_sge = qp->rq.max_gs;
 424         } else {
 425                 cap->max_recv_wr  = qp->rq.max_post =
 426                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 427                 cap->max_recv_sge = min(qp->rq.max_gs,
 428                                         min(dev->dev->caps.max_sq_sg,
 429                                             dev->dev->caps.max_rq_sg));
 430         }
 431
 432         return 0;
 433 }
 434
 435 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 436                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
 437                               bool shrink_wqe)
 438 {
 439         int s;
 440
 441         /* Sanity check SQ size before proceeding */
 442         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 443             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 444             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 445             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 446                 return -EINVAL;
 447
 448         /*
 449          * For MLX transport we need 2 extra S/G entries:
 450          * one for the header and one for the checksum at the end
 451          */
 452         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 453              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 454             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 455                 return -EINVAL;
 456
 457         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 458                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 459                 send_wqe_overhead(type, qp->flags);
 460
 461         if (s > dev->dev->caps.max_sq_desc_sz)
 462                 return -EINVAL;
 463
 464         /*
 465          * Hermon supports shrinking WQEs, such that a single work
 466          * request can include multiple units of 1 << wqe_shift.  This
 467          * way, work requests can differ in size, and do not have to
 468          * be a power of 2 in size, saving memory and speeding up send
 469          * WR posting.  Unfortunately, if we do this then the
 470          * wqe_index field in CQEs can't be used to look up the WR ID
 471          * anymore, so we do this only if selective signaling is off.
 472          *
 473          * Further, on 32-bit platforms, we can't use vmap() to make
 474          * the QP buffer virtually contiguous.  Thus we have to use
 475          * constant-sized WRs to make sure a WR is always fully within
 476          * a single page-sized chunk.
 477          *
 478          * Finally, we use NOP work requests to pad the end of the
 479          * work queue, to avoid wrap-around in the middle of WR.  We
 480          * set NEC bit to avoid getting completions with error for
 481          * these NOP WRs, but since NEC is only supported starting
 482          * with firmware 2.2.232, we use constant-sized WRs for older
 483          * firmware.
 484          *
 485          * And, since MLX QPs only support SEND, we use constant-sized
 486          * WRs in this case.
 487          *
 488          * We look for the smallest value of wqe_shift such that the
 489          * resulting number of wqes does not exceed device
 490          * capabilities.
 491          *
 492          * We set WQE size to at least 64 bytes, this way stamping
 493          * invalidates each WQE.
 494          */
 495         if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 496             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 497             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 498             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 499                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 500                 qp->sq.wqe_shift = ilog2(64);
 501         else
 502                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 503
 504         for (;;) {
 505                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 506
 507                 /*
 508                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 509                  * allow HW to prefetch.
 510                  */
 511                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 512                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 513                                                     qp->sq_max_wqes_per_wr +
 514                                                     qp->sq_spare_wqes);
 515
 516                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 517                         break;
 518
 519                 if (qp->sq_max_wqes_per_wr <= 1)
 520                         return -EINVAL;
 521
 522                 ++qp->sq.wqe_shift;
 523         }
 524
 525         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 526                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 527                          send_wqe_overhead(type, qp->flags)) /
 528                 sizeof (struct mlx4_wqe_data_seg);
 529
 530         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 531                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 532         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 533                 qp->rq.offset = 0;
 534                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 535         } else {
 536                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 537                 qp->sq.offset = 0;
 538         }
 539
 540         cap->max_send_wr  = qp->sq.max_post =
 541                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 542         cap->max_send_sge = min(qp->sq.max_gs,
 543                                 min(dev->dev->caps.max_sq_sg,
 544                                     dev->dev->caps.max_rq_sg));
 545         /* We don't support inline sends for kernel QPs (yet) */
 546         cap->max_inline_data = 0;
 547
 548         return 0;
 549 }
 550
 551 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 552                             struct mlx4_ib_qp *qp,
 553                             struct mlx4_ib_create_qp *ucmd)
 554 {
 555         /* Sanity check SQ size before proceeding */
 556         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 557             ucmd->log_sq_stride >
 558                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 559             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 560                 return -EINVAL;
 561
 562         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 563         qp->sq.wqe_shift = ucmd->log_sq_stride;
 564
 565         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 566                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 567
 568         return 0;
 569 }
 570
 571 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 572 {
 573         int i;
 574
 575         qp->sqp_proxy_rcv =
 576                 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
 577                               GFP_KERNEL);
 578         if (!qp->sqp_proxy_rcv)
 579                 return -ENOMEM;
 580         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 581                 qp->sqp_proxy_rcv[i].addr =
 582                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 583                                 GFP_KERNEL);
 584                 if (!qp->sqp_proxy_rcv[i].addr)
 585                         goto err;
 586                 qp->sqp_proxy_rcv[i].map =
 587                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 588                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 589                                           DMA_FROM_DEVICE);
 590                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 591                         kfree(qp->sqp_proxy_rcv[i].addr);
 592                         goto err;
 593                 }
 594         }
 595         return 0;
 596
 597 err:
 598         while (i > 0) {
 599                 --i;
 600                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 601                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 602                                     DMA_FROM_DEVICE);
 603                 kfree(qp->sqp_proxy_rcv[i].addr);
 604         }
 605         kfree(qp->sqp_proxy_rcv);
 606         qp->sqp_proxy_rcv = NULL;
 607         return -ENOMEM;
 608 }
 609
 610 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 611 {
 612         int i;
 613
 614         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 615                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 616                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 617                                     DMA_FROM_DEVICE);
 618                 kfree(qp->sqp_proxy_rcv[i].addr);
 619         }
 620         kfree(qp->sqp_proxy_rcv);
 621 }
 622
 623 static int qp_has_rq(struct ib_qp_init_attr *attr)
 624 {
 625         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 626                 return 0;
 627
 628         return !attr->srq;
 629 }
 630
 631 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 632 {
 633         int i;
 634         for (i = 0; i < dev->caps.num_ports; i++) {
 635                 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
 636                         return !!dev->caps.spec_qps[i].qp0_qkey;
 637         }
 638         return 0;
 639 }
 640
 641 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 642                                     struct mlx4_ib_qp *qp)
 643 {
 644         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 645         mlx4_counter_free(dev->dev, qp->counter_index->index);
 646         list_del(&qp->counter_index->list);
 647         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 648
 649         kfree(qp->counter_index);
 650         qp->counter_index = NULL;
 651 }
 652
 653 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
 654                       struct ib_qp_init_attr *init_attr,
 655                       struct mlx4_ib_create_qp_rss *ucmd)
 656 {
 657         rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
 658                 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
 659
 660         if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
 661             (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
 662                 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
 663                        MLX4_EN_RSS_KEY_SIZE);
 664         } else {
 665                 pr_debug("RX Hash function is not supported\n");
 666                 return (-EOPNOTSUPP);
 667         }
 668
 669         if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4      |
 670                                           MLX4_IB_RX_HASH_DST_IPV4      |
 671                                           MLX4_IB_RX_HASH_SRC_IPV6      |
 672                                           MLX4_IB_RX_HASH_DST_IPV6      |
 673                                           MLX4_IB_RX_HASH_SRC_PORT_TCP  |
 674                                           MLX4_IB_RX_HASH_DST_PORT_TCP  |
 675                                           MLX4_IB_RX_HASH_SRC_PORT_UDP  |
 676                                           MLX4_IB_RX_HASH_DST_PORT_UDP  |
 677                                           MLX4_IB_RX_HASH_INNER)) {
 678                 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
 679                          ucmd->rx_hash_fields_mask);
 680                 return (-EOPNOTSUPP);
 681         }
 682
 683         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
 684             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 685                 rss_ctx->flags = MLX4_RSS_IPV4;
 686         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
 687                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 688                 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
 689                 return (-EOPNOTSUPP);
 690         }
 691
 692         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
 693             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 694                 rss_ctx->flags |= MLX4_RSS_IPV6;
 695         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
 696                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 697                 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
 698                 return (-EOPNOTSUPP);
 699         }
 700
 701         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
 702             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 703                 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
 704                         pr_debug("RX Hash fields_mask for UDP is not supported\n");
 705                         return (-EOPNOTSUPP);
 706                 }
 707
 708                 if (rss_ctx->flags & MLX4_RSS_IPV4)
 709                         rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
 710                 if (rss_ctx->flags & MLX4_RSS_IPV6)
 711                         rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
 712                 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 713                         pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
 714                         return (-EOPNOTSUPP);
 715                 }
 716         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
 717                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 718                 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
 719                 return (-EOPNOTSUPP);
 720         }
 721
 722         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
 723             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 724                 if (rss_ctx->flags & MLX4_RSS_IPV4)
 725                         rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
 726                 if (rss_ctx->flags & MLX4_RSS_IPV6)
 727                         rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
 728                 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 729                         pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
 730                         return (-EOPNOTSUPP);
 731                 }
 732         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
 733                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 734                 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
 735                 return (-EOPNOTSUPP);
 736         }
 737
 738         if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
 739                 if (dev->dev->caps.tunnel_offload_mode ==
 740                     MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
 741                         /*
 742                          * Hash according to inner headers if exist, otherwise
 743                          * according to outer headers.
 744                          */
 745                         rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
 746                 } else {
 747                         pr_debug("RSS Hash for inner headers isn't supported\n");
 748                         return (-EOPNOTSUPP);
 749                 }
 750         }
 751
 752         return 0;
 753 }
 754
 755 static int create_qp_rss(struct mlx4_ib_dev *dev,
 756                          struct ib_qp_init_attr *init_attr,
 757                          struct mlx4_ib_create_qp_rss *ucmd,
 758                          struct mlx4_ib_qp *qp)
 759 {
 760         int qpn;
 761         int err;
 762
 763         qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
 764
 765         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
 766         if (err)
 767                 return err;
 768
 769         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 770         if (err)
 771                 goto err_qpn;
 772
 773         mutex_init(&qp->mutex);
 774
 775         INIT_LIST_HEAD(&qp->gid_list);
 776         INIT_LIST_HEAD(&qp->steering_rules);
 777
 778         qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
 779         qp->state = IB_QPS_RESET;
 780
 781         /* Set dummy send resources to be compatible with HV and PRM */
 782         qp->sq_no_prefetch = 1;
 783         qp->sq.wqe_cnt = 1;
 784         qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
 785         qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
 786         qp->mtt = (to_mqp(
 787                    (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
 788
 789         qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
 790         if (!qp->rss_ctx) {
 791                 err = -ENOMEM;
 792                 goto err_qp_alloc;
 793         }
 794
 795         err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
 796         if (err)
 797                 goto err;
 798
 799         return 0;
 800
 801 err:
 802         kfree(qp->rss_ctx);
 803
 804 err_qp_alloc:
 805         mlx4_qp_remove(dev->dev, &qp->mqp);
 806         mlx4_qp_free(dev->dev, &qp->mqp);
 807
 808 err_qpn:
 809         mlx4_qp_release_range(dev->dev, qpn, 1);
 810         return err;
 811 }
 812
 813 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
 814                                             struct ib_qp_init_attr *init_attr,
 815                                             struct ib_udata *udata)
 816 {
 817         struct mlx4_ib_qp *qp;
 818         struct mlx4_ib_create_qp_rss ucmd = {};
 819         size_t required_cmd_sz;
 820         int err;
 821
 822         if (!udata) {
 823                 pr_debug("RSS QP with NULL udata\n");
 824                 return ERR_PTR(-EINVAL);
 825         }
 826
 827         if (udata->outlen)
 828                 return ERR_PTR(-EOPNOTSUPP);
 829
 830         required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
 831                                         sizeof(ucmd.reserved1);
 832         if (udata->inlen < required_cmd_sz) {
 833                 pr_debug("invalid inlen\n");
 834                 return ERR_PTR(-EINVAL);
 835         }
 836
 837         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
 838                 pr_debug("copy failed\n");
 839                 return ERR_PTR(-EFAULT);
 840         }
 841
 842         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
 843                 return ERR_PTR(-EOPNOTSUPP);
 844
 845         if (ucmd.comp_mask || ucmd.reserved1)
 846                 return ERR_PTR(-EOPNOTSUPP);
 847
 848         if (udata->inlen > sizeof(ucmd) &&
 849             !ib_is_udata_cleared(udata, sizeof(ucmd),
 850                                  udata->inlen - sizeof(ucmd))) {
 851                 pr_debug("inlen is not supported\n");
 852                 return ERR_PTR(-EOPNOTSUPP);
 853         }
 854
 855         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
 856                 pr_debug("RSS QP with unsupported QP type %d\n",
 857                          init_attr->qp_type);
 858                 return ERR_PTR(-EOPNOTSUPP);
 859         }
 860
 861         if (init_attr->create_flags) {
 862                 pr_debug("RSS QP doesn't support create flags\n");
 863                 return ERR_PTR(-EOPNOTSUPP);
 864         }
 865
 866         if (init_attr->send_cq || init_attr->cap.max_send_wr) {
 867                 pr_debug("RSS QP with unsupported send attributes\n");
 868                 return ERR_PTR(-EOPNOTSUPP);
 869         }
 870
 871         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
 872         if (!qp)
 873                 return ERR_PTR(-ENOMEM);
 874
 875         qp->pri.vid = 0xFFFF;
 876         qp->alt.vid = 0xFFFF;
 877
 878         err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
 879         if (err) {
 880                 kfree(qp);
 881                 return ERR_PTR(err);
 882         }
 883
 884         qp->ibqp.qp_num = qp->mqp.qpn;
 885
 886         return &qp->ibqp;
 887 }
 888
 889 /*
 890  * This function allocates a WQN from a range which is consecutive and aligned
 891  * to its size. In case the range is full, then it creates a new range and
 892  * allocates WQN from it. The new range will be used for following allocations.
 893  */
 894 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
 895                              struct mlx4_ib_qp *qp, int range_size, int *wqn)
 896 {
 897         struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 898         struct mlx4_wqn_range *range;
 899         int err = 0;
 900
 901         mutex_lock(&context->wqn_ranges_mutex);
 902
 903         range = list_first_entry_or_null(&context->wqn_ranges_list,
 904                                          struct mlx4_wqn_range, list);
 905
 906         if (!range || (range->refcount == range->size) || range->dirty) {
 907                 range = kzalloc(sizeof(*range), GFP_KERNEL);
 908                 if (!range) {
 909                         err = -ENOMEM;
 910                         goto out;
 911                 }
 912
 913                 err = mlx4_qp_reserve_range(dev->dev, range_size,
 914                                             range_size, &range->base_wqn, 0,
 915                                             qp->mqp.usage);
 916                 if (err) {
 917                         kfree(range);
 918                         goto out;
 919                 }
 920
 921                 range->size = range_size;
 922                 list_add(&range->list, &context->wqn_ranges_list);
 923         } else if (range_size != 1) {
 924                 /*
 925                  * Requesting a new range (>1) when last range is still open, is
 926                  * not valid.
 927                  */
 928                 err = -EINVAL;
 929                 goto out;
 930         }
 931
 932         qp->wqn_range = range;
 933
 934         *wqn = range->base_wqn + range->refcount;
 935
 936         range->refcount++;
 937
 938 out:
 939         mutex_unlock(&context->wqn_ranges_mutex);
 940
 941         return err;
 942 }
 943
 944 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
 945                                 struct mlx4_ib_qp *qp, bool dirty_release)
 946 {
 947         struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 948         struct mlx4_wqn_range *range;
 949
 950         mutex_lock(&context->wqn_ranges_mutex);
 951
 952         range = qp->wqn_range;
 953
 954         range->refcount--;
 955         if (!range->refcount) {
 956                 mlx4_qp_release_range(dev->dev, range->base_wqn,
 957                                       range->size);
 958                 list_del(&range->list);
 959                 kfree(range);
 960         } else if (dirty_release) {
 961         /*
 962          * A range which one of its WQNs is destroyed, won't be able to be
 963          * reused for further WQN allocations.
 964          * The next created WQ will allocate a new range.
 965          */
 966                 range->dirty = 1;
 967         }
 968
 969         mutex_unlock(&context->wqn_ranges_mutex);
 970 }
 971
 972 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 973                             enum mlx4_ib_source_type src,
 974                             struct ib_qp_init_attr *init_attr,
 975                             struct ib_udata *udata, int sqpn,
 976                             struct mlx4_ib_qp **caller_qp)
 977 {
 978         int qpn;
 979         int err;
 980         struct ib_qp_cap backup_cap;
 981         struct mlx4_ib_sqp *sqp = NULL;
 982         struct mlx4_ib_qp *qp;
 983         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 984         struct mlx4_ib_cq *mcq;
 985         unsigned long flags;
 986         int range_size = 0;
 987
 988         /* When tunneling special qps, we use a plain UD qp */
 989         if (sqpn) {
 990                 if (mlx4_is_mfunc(dev->dev) &&
 991                     (!mlx4_is_master(dev->dev) ||
 992                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 993                         if (init_attr->qp_type == IB_QPT_GSI)
 994                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 995                         else {
 996                                 if (mlx4_is_master(dev->dev) ||
 997                                     qp0_enabled_vf(dev->dev, sqpn))
 998                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 999                                 else
1000                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
1001                         }
1002                 }
1003                 qpn = sqpn;
1004                 /* add extra sg entry for tunneling */
1005                 init_attr->cap.max_recv_sge++;
1006         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
1007                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
1008                         container_of(init_attr,
1009                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
1010                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
1011                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
1012                     !mlx4_is_master(dev->dev))
1013                         return -EINVAL;
1014                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1015                         qp_type = MLX4_IB_QPT_TUN_GSI;
1016                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1017                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1018                                              tnl_init->port))
1019                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1020                 else
1021                         qp_type = MLX4_IB_QPT_TUN_SMI;
1022                 /* we are definitely in the PPF here, since we are creating
1023                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1024                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1025                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1026                 sqpn = qpn;
1027         }
1028
1029         if (!*caller_qp) {
1030                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1031                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1032                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
1033                         sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1034                         if (!sqp)
1035                                 return -ENOMEM;
1036                         qp = &sqp->qp;
1037                         qp->pri.vid = 0xFFFF;
1038                         qp->alt.vid = 0xFFFF;
1039                 } else {
1040                         qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1041                         if (!qp)
1042                                 return -ENOMEM;
1043                         qp->pri.vid = 0xFFFF;
1044                         qp->alt.vid = 0xFFFF;
1045                 }
1046         } else
1047                 qp = *caller_qp;
1048
1049         qp->mlx4_ib_qp_type = qp_type;
1050
1051         mutex_init(&qp->mutex);
1052         spin_lock_init(&qp->sq.lock);
1053         spin_lock_init(&qp->rq.lock);
1054         INIT_LIST_HEAD(&qp->gid_list);
1055         INIT_LIST_HEAD(&qp->steering_rules);
1056
1057         qp->state        = IB_QPS_RESET;
1058         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1059                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1060
1061
1062         if (pd->uobject) {
1063                 union {
1064                         struct mlx4_ib_create_qp qp;
1065                         struct mlx4_ib_create_wq wq;
1066                 } ucmd;
1067                 size_t copy_len;
1068                 int shift;
1069                 int n;
1070
1071                 copy_len = (src == MLX4_IB_QP_SRC) ?
1072                            sizeof(struct mlx4_ib_create_qp) :
1073                            min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
1074
1075                 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
1076                         err = -EFAULT;
1077                         goto err;
1078                 }
1079
1080                 if (src == MLX4_IB_RWQ_SRC) {
1081                         if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
1082                             ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
1083                                 pr_debug("user command isn't supported\n");
1084                                 err = -EOPNOTSUPP;
1085                                 goto err;
1086                         }
1087
1088                         if (ucmd.wq.log_range_size >
1089                             ilog2(dev->dev->caps.max_rss_tbl_sz)) {
1090                                 pr_debug("WQN range size must be equal or smaller than %d\n",
1091                                          dev->dev->caps.max_rss_tbl_sz);
1092                                 err = -EOPNOTSUPP;
1093                                 goto err;
1094                         }
1095                         range_size = 1 << ucmd.wq.log_range_size;
1096                 } else {
1097                         qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
1098                 }
1099
1100                 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1101                         if (!(dev->dev->caps.flags &
1102                               MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
1103                                 pr_debug("scatter FCS is unsupported\n");
1104                                 err = -EOPNOTSUPP;
1105                                 goto err;
1106                         }
1107
1108                         qp->flags |= MLX4_IB_QP_SCATTER_FCS;
1109                 }
1110
1111                 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1112                                   qp_has_rq(init_attr), qp, qp->inl_recv_sz);
1113                 if (err)
1114                         goto err;
1115
1116                 if (src == MLX4_IB_QP_SRC) {
1117                         qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1118
1119                         err = set_user_sq_size(dev, qp,
1120                                                (struct mlx4_ib_create_qp *)
1121                                                &ucmd);
1122                         if (err)
1123                                 goto err;
1124                 } else {
1125                         qp->sq_no_prefetch = 1;
1126                         qp->sq.wqe_cnt = 1;
1127                         qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1128                         /* Allocated buffer expects to have at least that SQ
1129                          * size.
1130                          */
1131                         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1132                                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1133                 }
1134
1135                 qp->umem = ib_umem_get(pd->uobject->context,
1136                                 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1137                                 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
1138                 if (IS_ERR(qp->umem)) {
1139                         err = PTR_ERR(qp->umem);
1140                         goto err;
1141                 }
1142
1143                 n = ib_umem_page_count(qp->umem);
1144                 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1145                 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1146
1147                 if (err)
1148                         goto err_buf;
1149
1150                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1151                 if (err)
1152                         goto err_mtt;
1153
1154                 if (qp_has_rq(init_attr)) {
1155                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
1156                                 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1157                                 ucmd.wq.db_addr, &qp->db);
1158                         if (err)
1159                                 goto err_mtt;
1160                 }
1161                 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
1162         } else {
1163                 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1164                                   qp_has_rq(init_attr), qp, 0);
1165                 if (err)
1166                         goto err;
1167
1168                 qp->sq_no_prefetch = 0;
1169
1170                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1171                         qp->flags |= MLX4_IB_QP_LSO;
1172
1173                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1174                         if (dev->steering_support ==
1175                             MLX4_STEERING_MODE_DEVICE_MANAGED)
1176                                 qp->flags |= MLX4_IB_QP_NETIF;
1177                         else
1178                                 goto err;
1179                 }
1180
1181                 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
1182                 err = set_kernel_sq_size(dev, &init_attr->cap,
1183                                          qp_type, qp, true);
1184                 if (err)
1185                         goto err;
1186
1187                 if (qp_has_rq(init_attr)) {
1188                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
1189                         if (err)
1190                                 goto err;
1191
1192                         *qp->db.db = 0;
1193                 }
1194
1195                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
1196                                    &qp->buf)) {
1197                         memcpy(&init_attr->cap, &backup_cap,
1198                                sizeof(backup_cap));
1199                         err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
1200                                                  qp, false);
1201                         if (err)
1202                                 goto err_db;
1203
1204                         if (mlx4_buf_alloc(dev->dev, qp->buf_size,
1205                                            PAGE_SIZE * 2, &qp->buf)) {
1206                                 err = -ENOMEM;
1207                                 goto err_db;
1208                         }
1209                 }
1210
1211                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1212                                     &qp->mtt);
1213                 if (err)
1214                         goto err_buf;
1215
1216                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
1217                 if (err)
1218                         goto err_mtt;
1219
1220                 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1221                                              sizeof(u64), GFP_KERNEL);
1222                 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1223                                              sizeof(u64), GFP_KERNEL);
1224                 if (!qp->sq.wrid || !qp->rq.wrid) {
1225                         err = -ENOMEM;
1226                         goto err_wrid;
1227                 }
1228                 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
1229         }
1230
1231         if (sqpn) {
1232                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1233                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1234                         if (alloc_proxy_bufs(pd->device, qp)) {
1235                                 err = -ENOMEM;
1236                                 goto err_wrid;
1237                         }
1238                 }
1239         } else if (src == MLX4_IB_RWQ_SRC) {
1240                 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1241                                         range_size, &qpn);
1242                 if (err)
1243                         goto err_wrid;
1244         } else {
1245                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1246                  * otherwise, the WQE BlueFlame setup flow wrongly causes
1247                  * VLAN insertion. */
1248                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
1249                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
1250                                                     (init_attr->cap.max_send_wr ?
1251                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
1252                                                     (init_attr->cap.max_recv_wr ?
1253                                                      MLX4_RESERVE_A0_QP : 0),
1254                                                     qp->mqp.usage);
1255                 else
1256                         if (qp->flags & MLX4_IB_QP_NETIF)
1257                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1258                         else
1259                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
1260                                                             &qpn, 0, qp->mqp.usage);
1261                 if (err)
1262                         goto err_proxy;
1263         }
1264
1265         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1266                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1267
1268         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
1269         if (err)
1270                 goto err_qpn;
1271
1272         if (init_attr->qp_type == IB_QPT_XRC_TGT)
1273                 qp->mqp.qpn |= (1 << 23);
1274
1275         /*
1276          * Hardware wants QPN written in big-endian order (after
1277          * shifting) for send doorbell.  Precompute this value to save
1278          * a little bit when posting sends.
1279          */
1280         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1281
1282         qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1283                                                   mlx4_ib_wq_event;
1284
1285         if (!*caller_qp)
1286                 *caller_qp = qp;
1287
1288         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1289         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1290                          to_mcq(init_attr->recv_cq));
1291         /* Maintain device to QPs access, needed for further handling
1292          * via reset flow
1293          */
1294         list_add_tail(&qp->qps_list, &dev->qp_list);
1295         /* Maintain CQ to QPs access, needed for further handling
1296          * via reset flow
1297          */
1298         mcq = to_mcq(init_attr->send_cq);
1299         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1300         mcq = to_mcq(init_attr->recv_cq);
1301         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1302         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1303                            to_mcq(init_attr->recv_cq));
1304         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1305         return 0;
1306
1307 err_qpn:
1308         if (!sqpn) {
1309                 if (qp->flags & MLX4_IB_QP_NETIF)
1310                         mlx4_ib_steer_qp_free(dev, qpn, 1);
1311                 else if (src == MLX4_IB_RWQ_SRC)
1312                         mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1313                                             qp, 0);
1314                 else
1315                         mlx4_qp_release_range(dev->dev, qpn, 1);
1316         }
1317 err_proxy:
1318         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1319                 free_proxy_bufs(pd->device, qp);
1320 err_wrid:
1321         if (pd->uobject) {
1322                 if (qp_has_rq(init_attr))
1323                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
1324         } else {
1325                 kvfree(qp->sq.wrid);
1326                 kvfree(qp->rq.wrid);
1327         }
1328
1329 err_mtt:
1330         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1331
1332 err_buf:
1333         if (pd->uobject)
1334                 ib_umem_release(qp->umem);
1335         else
1336                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1337
1338 err_db:
1339         if (!pd->uobject && qp_has_rq(init_attr))
1340                 mlx4_db_free(dev->dev, &qp->db);
1341
1342 err:
1343         if (sqp)
1344                 kfree(sqp);
1345         else if (!*caller_qp)
1346                 kfree(qp);
1347         return err;
1348 }
1349
1350 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1351 {
1352         switch (state) {
1353         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
1354         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
1355         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
1356         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
1357         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
1358         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
1359         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
1360         default:                return -1;
1361         }
1362 }
1363
1364 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1365         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1366 {
1367         if (send_cq == recv_cq) {
1368                 spin_lock(&send_cq->lock);
1369                 __acquire(&recv_cq->lock);
1370         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1371                 spin_lock(&send_cq->lock);
1372                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1373         } else {
1374                 spin_lock(&recv_cq->lock);
1375                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1376         }
1377 }
1378
1379 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1380         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1381 {
1382         if (send_cq == recv_cq) {
1383                 __release(&recv_cq->lock);
1384                 spin_unlock(&send_cq->lock);
1385         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1386                 spin_unlock(&recv_cq->lock);
1387                 spin_unlock(&send_cq->lock);
1388         } else {
1389                 spin_unlock(&send_cq->lock);
1390                 spin_unlock(&recv_cq->lock);
1391         }
1392 }
1393
1394 static void del_gid_entries(struct mlx4_ib_qp *qp)
1395 {
1396         struct mlx4_ib_gid_entry *ge, *tmp;
1397
1398         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1399                 list_del(&ge->list);
1400                 kfree(ge);
1401         }
1402 }
1403
1404 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1405 {
1406         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1407                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1408         else
1409                 return to_mpd(qp->ibqp.pd);
1410 }
1411
1412 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
1413                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1414 {
1415         switch (qp->ibqp.qp_type) {
1416         case IB_QPT_XRC_TGT:
1417                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1418                 *recv_cq = *send_cq;
1419                 break;
1420         case IB_QPT_XRC_INI:
1421                 *send_cq = to_mcq(qp->ibqp.send_cq);
1422                 *recv_cq = *send_cq;
1423                 break;
1424         default:
1425                 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1426                                                      to_mcq(qp->ibwq.cq);
1427                 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1428                                                      *recv_cq;
1429                 break;
1430         }
1431 }
1432
1433 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1434 {
1435         if (qp->state != IB_QPS_RESET) {
1436                 int i;
1437
1438                 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1439                      i++) {
1440                         struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1441                         struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1442
1443                         mutex_lock(&wq->mutex);
1444
1445                         wq->rss_usecnt--;
1446
1447                         mutex_unlock(&wq->mutex);
1448                 }
1449
1450                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1451                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1452                         pr_warn("modify QP %06x to RESET failed.\n",
1453                                 qp->mqp.qpn);
1454         }
1455
1456         mlx4_qp_remove(dev->dev, &qp->mqp);
1457         mlx4_qp_free(dev->dev, &qp->mqp);
1458         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1459         del_gid_entries(qp);
1460         kfree(qp->rss_ctx);
1461 }
1462
1463 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1464                               enum mlx4_ib_source_type src, int is_user)
1465 {
1466         struct mlx4_ib_cq *send_cq, *recv_cq;
1467         unsigned long flags;
1468
1469         if (qp->state != IB_QPS_RESET) {
1470                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1471                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1472                         pr_warn("modify QP %06x to RESET failed.\n",
1473                                qp->mqp.qpn);
1474                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1475                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1476                         qp->pri.smac = 0;
1477                         qp->pri.smac_port = 0;
1478                 }
1479                 if (qp->alt.smac) {
1480                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1481                         qp->alt.smac = 0;
1482                 }
1483                 if (qp->pri.vid < 0x1000) {
1484                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1485                         qp->pri.vid = 0xFFFF;
1486                         qp->pri.candidate_vid = 0xFFFF;
1487                         qp->pri.update_vid = 0;
1488                 }
1489                 if (qp->alt.vid < 0x1000) {
1490                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1491                         qp->alt.vid = 0xFFFF;
1492                         qp->alt.candidate_vid = 0xFFFF;
1493                         qp->alt.update_vid = 0;
1494                 }
1495         }
1496
1497         get_cqs(qp, src, &send_cq, &recv_cq);
1498
1499         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1500         mlx4_ib_lock_cqs(send_cq, recv_cq);
1501
1502         /* del from lists under both locks above to protect reset flow paths */
1503         list_del(&qp->qps_list);
1504         list_del(&qp->cq_send_list);
1505         list_del(&qp->cq_recv_list);
1506         if (!is_user) {
1507                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1508                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1509                 if (send_cq != recv_cq)
1510                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1511         }
1512
1513         mlx4_qp_remove(dev->dev, &qp->mqp);
1514
1515         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1516         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1517
1518         mlx4_qp_free(dev->dev, &qp->mqp);
1519
1520         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1521                 if (qp->flags & MLX4_IB_QP_NETIF)
1522                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1523                 else if (src == MLX4_IB_RWQ_SRC)
1524                         mlx4_ib_release_wqn(to_mucontext(
1525                                             qp->ibwq.uobject->context), qp, 1);
1526                 else
1527                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1528         }
1529
1530         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1531
1532         if (is_user) {
1533                 if (qp->rq.wqe_cnt) {
1534                         struct mlx4_ib_ucontext *mcontext = !src ?
1535                                 to_mucontext(qp->ibqp.uobject->context) :
1536                                 to_mucontext(qp->ibwq.uobject->context);
1537                         mlx4_ib_db_unmap_user(mcontext, &qp->db);
1538                 }
1539                 ib_umem_release(qp->umem);
1540         } else {
1541                 kvfree(qp->sq.wrid);
1542                 kvfree(qp->rq.wrid);
1543                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1544                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1545                         free_proxy_bufs(&dev->ib_dev, qp);
1546                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1547                 if (qp->rq.wqe_cnt)
1548                         mlx4_db_free(dev->dev, &qp->db);
1549         }
1550
1551         del_gid_entries(qp);
1552 }
1553
1554 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1555 {
1556         /* Native or PPF */
1557         if (!mlx4_is_mfunc(dev->dev) ||
1558             (mlx4_is_master(dev->dev) &&
1559              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1560                 return  dev->dev->phys_caps.base_sqpn +
1561                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1562                         attr->port_num - 1;
1563         }
1564         /* PF or VF -- creating proxies */
1565         if (attr->qp_type == IB_QPT_SMI)
1566                 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
1567         else
1568                 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
1569 }
1570
1571 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1572                                         struct ib_qp_init_attr *init_attr,
1573                                         struct ib_udata *udata)
1574 {
1575         struct mlx4_ib_qp *qp = NULL;
1576         int err;
1577         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1578         u16 xrcdn = 0;
1579
1580         if (init_attr->rwq_ind_tbl)
1581                 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1582
1583         /*
1584          * We only support LSO, vendor flag1, and multicast loopback blocking,
1585          * and only for kernel UD QPs.
1586          */
1587         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1588                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1589                                         MLX4_IB_SRIOV_TUNNEL_QP |
1590                                         MLX4_IB_SRIOV_SQP |
1591                                         MLX4_IB_QP_NETIF |
1592                                         MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1593                 return ERR_PTR(-EINVAL);
1594
1595         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1596                 if (init_attr->qp_type != IB_QPT_UD)
1597                         return ERR_PTR(-EINVAL);
1598         }
1599
1600         if (init_attr->create_flags) {
1601                 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1602                         return ERR_PTR(-EINVAL);
1603
1604                 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1605                                                  MLX4_IB_QP_CREATE_ROCE_V2_GSI  |
1606                                                  MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1607                      init_attr->qp_type != IB_QPT_UD) ||
1608                     (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1609                      init_attr->qp_type > IB_QPT_GSI) ||
1610                     (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1611                      init_attr->qp_type != IB_QPT_GSI))
1612                         return ERR_PTR(-EINVAL);
1613         }
1614
1615         switch (init_attr->qp_type) {
1616         case IB_QPT_XRC_TGT:
1617                 pd = to_mxrcd(init_attr->xrcd)->pd;
1618                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1619                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1620                 /* fall through */
1621         case IB_QPT_XRC_INI:
1622                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1623                         return ERR_PTR(-ENOSYS);
1624                 init_attr->recv_cq = init_attr->send_cq;
1625                 /* fall through */
1626         case IB_QPT_RC:
1627         case IB_QPT_UC:
1628         case IB_QPT_RAW_PACKET:
1629                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1630                 if (!qp)
1631                         return ERR_PTR(-ENOMEM);
1632                 qp->pri.vid = 0xFFFF;
1633                 qp->alt.vid = 0xFFFF;
1634                 /* fall through */
1635         case IB_QPT_UD:
1636         {
1637                 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1638                                        init_attr, udata, 0, &qp);
1639                 if (err) {
1640                         kfree(qp);
1641                         return ERR_PTR(err);
1642                 }
1643
1644                 qp->ibqp.qp_num = qp->mqp.qpn;
1645                 qp->xrcdn = xrcdn;
1646
1647                 break;
1648         }
1649         case IB_QPT_SMI:
1650         case IB_QPT_GSI:
1651         {
1652                 int sqpn;
1653
1654                 /* Userspace is not allowed to create special QPs: */
1655                 if (udata)
1656                         return ERR_PTR(-EINVAL);
1657                 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1658                         int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1659                                                         1, 1, &sqpn, 0,
1660                                                         MLX4_RES_USAGE_DRIVER);
1661
1662                         if (res)
1663                                 return ERR_PTR(res);
1664                 } else {
1665                         sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1666                 }
1667
1668                 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1669                                        init_attr, udata, sqpn, &qp);
1670                 if (err)
1671                         return ERR_PTR(err);
1672
1673                 qp->port        = init_attr->port_num;
1674                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1675                         init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1676                 break;
1677         }
1678         default:
1679                 /* Don't support raw QPs */
1680                 return ERR_PTR(-EINVAL);
1681         }
1682
1683         return &qp->ibqp;
1684 }
1685
1686 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1687                                 struct ib_qp_init_attr *init_attr,
1688                                 struct ib_udata *udata) {
1689         struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1690         struct ib_qp *ibqp;
1691         struct mlx4_ib_dev *dev = to_mdev(device);
1692
1693         ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1694
1695         if (!IS_ERR(ibqp) &&
1696             (init_attr->qp_type == IB_QPT_GSI) &&
1697             !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1698                 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1699                 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1700
1701                 if (is_eth &&
1702                     dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1703                         init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1704                         sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1705
1706                         if (IS_ERR(sqp->roce_v2_gsi)) {
1707                                 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1708                                 sqp->roce_v2_gsi = NULL;
1709                         } else {
1710                                 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1711                                 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1712                         }
1713
1714                         init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1715                 }
1716         }
1717         return ibqp;
1718 }
1719
1720 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1721 {
1722         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1723         struct mlx4_ib_qp *mqp = to_mqp(qp);
1724
1725         if (is_qp0(dev, mqp))
1726                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1727
1728         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1729             dev->qp1_proxy[mqp->port - 1] == mqp) {
1730                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1731                 dev->qp1_proxy[mqp->port - 1] = NULL;
1732                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1733         }
1734
1735         if (mqp->counter_index)
1736                 mlx4_ib_free_qp_counter(dev, mqp);
1737
1738         if (qp->rwq_ind_tbl) {
1739                 destroy_qp_rss(dev, mqp);
1740         } else {
1741                 struct mlx4_ib_pd *pd;
1742
1743                 pd = get_pd(mqp);
1744                 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1745         }
1746
1747         if (is_sqp(dev, mqp))
1748                 kfree(to_msqp(mqp));
1749         else
1750                 kfree(mqp);
1751
1752         return 0;
1753 }
1754
1755 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1756 {
1757         struct mlx4_ib_qp *mqp = to_mqp(qp);
1758
1759         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1760                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1761
1762                 if (sqp->roce_v2_gsi)
1763                         ib_destroy_qp(sqp->roce_v2_gsi);
1764         }
1765
1766         return _mlx4_ib_destroy_qp(qp);
1767 }
1768
1769 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1770 {
1771         switch (type) {
1772         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1773         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1774         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1775         case MLX4_IB_QPT_XRC_INI:
1776         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1777         case MLX4_IB_QPT_SMI:
1778         case MLX4_IB_QPT_GSI:
1779         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1780
1781         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1782         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1783                                                 MLX4_QP_ST_MLX : -1);
1784         case MLX4_IB_QPT_PROXY_SMI:
1785         case MLX4_IB_QPT_TUN_SMI:
1786         case MLX4_IB_QPT_PROXY_GSI:
1787         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1788                                                 MLX4_QP_ST_UD : -1);
1789         default:                        return -1;
1790         }
1791 }
1792
1793 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1794                                    int attr_mask)
1795 {
1796         u8 dest_rd_atomic;
1797         u32 access_flags;
1798         u32 hw_access_flags = 0;
1799
1800         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1801                 dest_rd_atomic = attr->max_dest_rd_atomic;
1802         else
1803                 dest_rd_atomic = qp->resp_depth;
1804
1805         if (attr_mask & IB_QP_ACCESS_FLAGS)
1806                 access_flags = attr->qp_access_flags;
1807         else
1808                 access_flags = qp->atomic_rd_en;
1809
1810         if (!dest_rd_atomic)
1811                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1812
1813         if (access_flags & IB_ACCESS_REMOTE_READ)
1814                 hw_access_flags |= MLX4_QP_BIT_RRE;
1815         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1816                 hw_access_flags |= MLX4_QP_BIT_RAE;
1817         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1818                 hw_access_flags |= MLX4_QP_BIT_RWE;
1819
1820         return cpu_to_be32(hw_access_flags);
1821 }
1822
1823 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1824                             int attr_mask)
1825 {
1826         if (attr_mask & IB_QP_PKEY_INDEX)
1827                 sqp->pkey_index = attr->pkey_index;
1828         if (attr_mask & IB_QP_QKEY)
1829                 sqp->qkey = attr->qkey;
1830         if (attr_mask & IB_QP_SQ_PSN)
1831                 sqp->send_psn = attr->sq_psn;
1832 }
1833
1834 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1835 {
1836         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1837 }
1838
1839 static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1840                           const struct rdma_ah_attr *ah,
1841                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1842                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1843 {
1844         int vidx;
1845         int smac_index;
1846         int err;
1847
1848         path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1849         path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1850         if (rdma_ah_get_static_rate(ah)) {
1851                 path->static_rate = rdma_ah_get_static_rate(ah) +
1852                                     MLX4_STAT_RATE_OFFSET;
1853                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1854                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1855                         --path->static_rate;
1856         } else
1857                 path->static_rate = 0;
1858
1859         if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1860                 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1861                 int real_sgid_index =
1862                         mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
1863
1864                 if (real_sgid_index < 0)
1865                         return real_sgid_index;
1866                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1867                         pr_err("sgid_index (%u) too large. max is %d\n",
1868                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1869                         return -1;
1870                 }
1871
1872                 path->grh_mylmc |= 1 << 7;
1873                 path->mgid_index = real_sgid_index;
1874                 path->hop_limit  = grh->hop_limit;
1875                 path->tclass_flowlabel =
1876                         cpu_to_be32((grh->traffic_class << 20) |
1877                                     (grh->flow_label));
1878                 memcpy(path->rgid, grh->dgid.raw, 16);
1879         }
1880
1881         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
1882                 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
1883                         return -1;
1884
1885                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1886                         ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
1887
1888                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1889                 if (vlan_tag < 0x1000) {
1890                         if (smac_info->vid < 0x1000) {
1891                                 /* both valid vlan ids */
1892                                 if (smac_info->vid != vlan_tag) {
1893                                         /* different VIDs.  unreg old and reg new */
1894                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1895                                         if (err)
1896                                                 return err;
1897                                         smac_info->candidate_vid = vlan_tag;
1898                                         smac_info->candidate_vlan_index = vidx;
1899                                         smac_info->candidate_vlan_port = port;
1900                                         smac_info->update_vid = 1;
1901                                         path->vlan_index = vidx;
1902                                 } else {
1903                                         path->vlan_index = smac_info->vlan_index;
1904                                 }
1905                         } else {
1906                                 /* no current vlan tag in qp */
1907                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1908                                 if (err)
1909                                         return err;
1910                                 smac_info->candidate_vid = vlan_tag;
1911                                 smac_info->candidate_vlan_index = vidx;
1912                                 smac_info->candidate_vlan_port = port;
1913                                 smac_info->update_vid = 1;
1914                                 path->vlan_index = vidx;
1915                         }
1916                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1917                         path->fl = 1 << 6;
1918                 } else {
1919                         /* have current vlan tag. unregister it at modify-qp success */
1920                         if (smac_info->vid < 0x1000) {
1921                                 smac_info->candidate_vid = 0xFFFF;
1922                                 smac_info->update_vid = 1;
1923                         }
1924                 }
1925
1926                 /* get smac_index for RoCE use.
1927                  * If no smac was yet assigned, register one.
1928                  * If one was already assigned, but the new mac differs,
1929                  * unregister the old one and register the new one.
1930                 */
1931                 if ((!smac_info->smac && !smac_info->smac_port) ||
1932                     smac_info->smac != smac) {
1933                         /* register candidate now, unreg if needed, after success */
1934                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1935                         if (smac_index >= 0) {
1936                                 smac_info->candidate_smac_index = smac_index;
1937                                 smac_info->candidate_smac = smac;
1938                                 smac_info->candidate_smac_port = port;
1939                         } else {
1940                                 return -EINVAL;
1941                         }
1942                 } else {
1943                         smac_index = smac_info->smac_index;
1944                 }
1945                 memcpy(path->dmac, ah->roce.dmac, 6);
1946                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1947                 /* put MAC table smac index for IBoE */
1948                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1949         } else {
1950                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1951                         ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
1952         }
1953
1954         return 0;
1955 }
1956
1957 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1958                          enum ib_qp_attr_mask qp_attr_mask,
1959                          struct mlx4_ib_qp *mqp,
1960                          struct mlx4_qp_path *path, u8 port,
1961                          u16 vlan_id, u8 *smac)
1962 {
1963         return _mlx4_set_path(dev, &qp->ah_attr,
1964                               mlx4_mac_to_u64(smac),
1965                               vlan_id,
1966                               path, &mqp->pri, port);
1967 }
1968
1969 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1970                              const struct ib_qp_attr *qp,
1971                              enum ib_qp_attr_mask qp_attr_mask,
1972                              struct mlx4_ib_qp *mqp,
1973                              struct mlx4_qp_path *path, u8 port)
1974 {
1975         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1976                               0,
1977                               0xffff,
1978                               path, &mqp->alt, port);
1979 }
1980
1981 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1982 {
1983         struct mlx4_ib_gid_entry *ge, *tmp;
1984
1985         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1986                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1987                         ge->added = 1;
1988                         ge->port = qp->port;
1989                 }
1990         }
1991 }
1992
1993 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1994                                     struct mlx4_ib_qp *qp,
1995                                     struct mlx4_qp_context *context)
1996 {
1997         u64 u64_mac;
1998         int smac_index;
1999
2000         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2001
2002         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
2003         if (!qp->pri.smac && !qp->pri.smac_port) {
2004                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
2005                 if (smac_index >= 0) {
2006                         qp->pri.candidate_smac_index = smac_index;
2007                         qp->pri.candidate_smac = u64_mac;
2008                         qp->pri.candidate_smac_port = qp->port;
2009                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
2010                 } else {
2011                         return -ENOENT;
2012                 }
2013         }
2014         return 0;
2015 }
2016
2017 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
2018 {
2019         struct counter_index *new_counter_index;
2020         int err;
2021         u32 tmp_idx;
2022
2023         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
2024             IB_LINK_LAYER_ETHERNET ||
2025             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
2026             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
2027                 return 0;
2028
2029         err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
2030         if (err)
2031                 return err;
2032
2033         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
2034         if (!new_counter_index) {
2035                 mlx4_counter_free(dev->dev, tmp_idx);
2036                 return -ENOMEM;
2037         }
2038
2039         new_counter_index->index = tmp_idx;
2040         new_counter_index->allocated = 1;
2041         qp->counter_index = new_counter_index;
2042
2043         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
2044         list_add_tail(&new_counter_index->list,
2045                       &dev->counters_table[qp->port - 1].counters_list);
2046         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2047
2048         return 0;
2049 }
2050
2051 enum {
2052         MLX4_QPC_ROCE_MODE_1 = 0,
2053         MLX4_QPC_ROCE_MODE_2 = 2,
2054         MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2055 };
2056
2057 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2058 {
2059         switch (gid_type) {
2060         case IB_GID_TYPE_ROCE:
2061                 return MLX4_QPC_ROCE_MODE_1;
2062         case IB_GID_TYPE_ROCE_UDP_ENCAP:
2063                 return MLX4_QPC_ROCE_MODE_2;
2064         default:
2065                 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2066         }
2067 }
2068
2069 /*
2070  * Go over all RSS QP's childes (WQs) and apply their HW state according to
2071  * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2072  */
2073 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
2074 {
2075         int err = 0;
2076         int i;
2077
2078         for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2079                 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2080                 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2081
2082                 mutex_lock(&wq->mutex);
2083
2084                 /* Mlx4_ib restrictions:
2085                  * WQ's is associated to a port according to the RSS QP it is
2086                  * associates to.
2087                  * In case the WQ is associated to a different port by another
2088                  * RSS QP, return a failure.
2089                  */
2090                 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2091                         err = -EINVAL;
2092                         mutex_unlock(&wq->mutex);
2093                         break;
2094                 }
2095                 wq->port = port_num;
2096                 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2097                         err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
2098                         if (err) {
2099                                 mutex_unlock(&wq->mutex);
2100                                 break;
2101                         }
2102                 }
2103                 wq->rss_usecnt++;
2104
2105                 mutex_unlock(&wq->mutex);
2106         }
2107
2108         if (i && err) {
2109                 int j;
2110
2111                 for (j = (i - 1); j >= 0; j--) {
2112                         struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2113                         struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2114
2115                         mutex_lock(&wq->mutex);
2116
2117                         if ((wq->rss_usecnt == 1) &&
2118                             (ibwq->state == IB_WQS_RDY))
2119                                 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2120                                         pr_warn("failed to reverse WQN=0x%06x\n",
2121                                                 ibwq->wq_num);
2122                         wq->rss_usecnt--;
2123
2124                         mutex_unlock(&wq->mutex);
2125                 }
2126         }
2127
2128         return err;
2129 }
2130
2131 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2132 {
2133         int i;
2134
2135         for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2136                 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2137                 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2138
2139                 mutex_lock(&wq->mutex);
2140
2141                 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2142                         if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2143                                 pr_warn("failed to reverse WQN=%x\n",
2144                                         ibwq->wq_num);
2145                 wq->rss_usecnt--;
2146
2147                 mutex_unlock(&wq->mutex);
2148         }
2149 }
2150
2151 static void fill_qp_rss_context(struct mlx4_qp_context *context,
2152                                 struct mlx4_ib_qp *qp)
2153 {
2154         struct mlx4_rss_context *rss_context;
2155
2156         rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2157                         pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2158
2159         rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2160         rss_context->default_qpn =
2161                 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2162         if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2163                 rss_context->base_qpn_udp = rss_context->default_qpn;
2164         rss_context->flags = qp->rss_ctx->flags;
2165         /* Currently support just toeplitz */
2166         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2167
2168         memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2169                MLX4_EN_RSS_KEY_SIZE);
2170 }
2171
2172 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2173                                const struct ib_qp_attr *attr, int attr_mask,
2174                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2175 {
2176         struct ib_uobject *ibuobject;
2177         struct ib_srq  *ibsrq;
2178         const struct ib_gid_attr *gid_attr = NULL;
2179         struct ib_rwq_ind_table *rwq_ind_tbl;
2180         enum ib_qp_type qp_type;
2181         struct mlx4_ib_dev *dev;
2182         struct mlx4_ib_qp *qp;
2183         struct mlx4_ib_pd *pd;
2184         struct mlx4_ib_cq *send_cq, *recv_cq;
2185         struct mlx4_qp_context *context;
2186         enum mlx4_qp_optpar optpar = 0;
2187         int sqd_event;
2188         int steer_qp = 0;
2189         int err = -EINVAL;
2190         int counter_index;
2191
2192         if (src_type == MLX4_IB_RWQ_SRC) {
2193                 struct ib_wq *ibwq;
2194
2195                 ibwq        = (struct ib_wq *)src;
2196                 ibuobject   = ibwq->uobject;
2197                 ibsrq       = NULL;
2198                 rwq_ind_tbl = NULL;
2199                 qp_type     = IB_QPT_RAW_PACKET;
2200                 qp          = to_mqp((struct ib_qp *)ibwq);
2201                 dev         = to_mdev(ibwq->device);
2202                 pd          = to_mpd(ibwq->pd);
2203         } else {
2204                 struct ib_qp *ibqp;
2205
2206                 ibqp        = (struct ib_qp *)src;
2207                 ibuobject   = ibqp->uobject;
2208                 ibsrq       = ibqp->srq;
2209                 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2210                 qp_type     = ibqp->qp_type;
2211                 qp          = to_mqp(ibqp);
2212                 dev         = to_mdev(ibqp->device);
2213                 pd          = get_pd(qp);
2214         }
2215
2216         /* APM is not supported under RoCE */
2217         if (attr_mask & IB_QP_ALT_PATH &&
2218             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2219             IB_LINK_LAYER_ETHERNET)
2220                 return -ENOTSUPP;
2221
2222         context = kzalloc(sizeof *context, GFP_KERNEL);
2223         if (!context)
2224                 return -ENOMEM;
2225
2226         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2227                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2228
2229         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2230                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2231         else {
2232                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2233                 switch (attr->path_mig_state) {
2234                 case IB_MIG_MIGRATED:
2235                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2236                         break;
2237                 case IB_MIG_REARM:
2238                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2239                         break;
2240                 case IB_MIG_ARMED:
2241                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2242                         break;
2243                 }
2244         }
2245
2246         if (qp->inl_recv_sz)
2247                 context->param3 |= cpu_to_be32(1 << 25);
2248
2249         if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2250                 context->param3 |= cpu_to_be32(1 << 29);
2251
2252         if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
2253                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
2254         else if (qp_type == IB_QPT_RAW_PACKET)
2255                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
2256         else if (qp_type == IB_QPT_UD) {
2257                 if (qp->flags & MLX4_IB_QP_LSO)
2258                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
2259                                               ilog2(dev->dev->caps.max_gso_sz);
2260                 else
2261                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2262         } else if (attr_mask & IB_QP_PATH_MTU) {
2263                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2264                         pr_err("path MTU (%u) is invalid\n",
2265                                attr->path_mtu);
2266                         goto out;
2267                 }
2268                 context->mtu_msgmax = (attr->path_mtu << 5) |
2269                         ilog2(dev->dev->caps.max_msg_sz);
2270         }
2271
2272         if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2273                 if (qp->rq.wqe_cnt)
2274                         context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2275                 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2276         }
2277
2278         if (qp->sq.wqe_cnt)
2279                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
2280         context->sq_size_stride |= qp->sq.wqe_shift - 4;
2281
2282         if (new_state == IB_QPS_RESET && qp->counter_index)
2283                 mlx4_ib_free_qp_counter(dev, qp);
2284
2285         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2286                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
2287                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
2288                 if (qp_type == IB_QPT_RAW_PACKET)
2289                         context->param3 |= cpu_to_be32(1 << 30);
2290         }
2291
2292         if (ibuobject)
2293                 context->usr_page = cpu_to_be32(
2294                         mlx4_to_hw_uar_index(dev->dev,
2295                                              to_mucontext(ibuobject->context)
2296                                              ->uar.index));
2297         else
2298                 context->usr_page = cpu_to_be32(
2299                         mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
2300
2301         if (attr_mask & IB_QP_DEST_QPN)
2302                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2303
2304         if (attr_mask & IB_QP_PORT) {
2305                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2306                     !(attr_mask & IB_QP_AV)) {
2307                         mlx4_set_sched(&context->pri_path, attr->port_num);
2308                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2309                 }
2310         }
2311
2312         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2313                 err = create_qp_lb_counter(dev, qp);
2314                 if (err)
2315                         goto out;
2316
2317                 counter_index =
2318                         dev->counters_table[qp->port - 1].default_counter;
2319                 if (qp->counter_index)
2320                         counter_index = qp->counter_index->index;
2321
2322                 if (counter_index != -1) {
2323                         context->pri_path.counter_index = counter_index;
2324                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
2325                         if (qp->counter_index) {
2326                                 context->pri_path.fl |=
2327                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
2328                                 context->pri_path.vlan_control |=
2329                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2330                         }
2331                 } else
2332                         context->pri_path.counter_index =
2333                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
2334
2335                 if (qp->flags & MLX4_IB_QP_NETIF) {
2336                         mlx4_ib_steer_qp_reg(dev, qp, 1);
2337                         steer_qp = 1;
2338                 }
2339
2340                 if (qp_type == IB_QPT_GSI) {
2341                         enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2342                                 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2343                         u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2344
2345                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2346                 }
2347         }
2348
2349         if (attr_mask & IB_QP_PKEY_INDEX) {
2350                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2351                         context->pri_path.disable_pkey_check = 0x40;
2352                 context->pri_path.pkey_index = attr->pkey_index;
2353                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2354         }
2355
2356         if (attr_mask & IB_QP_AV) {
2357                 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
2358                         attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2359                 u16 vlan = 0xffff;
2360                 u8 smac[ETH_ALEN];
2361                 int is_eth =
2362                         rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2363                         rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
2364
2365                 if (is_eth) {
2366                         gid_attr = attr->ah_attr.grh.sgid_attr;
2367                         vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
2368                         memcpy(smac, gid_attr->ndev->dev_addr, ETH_ALEN);
2369                 }
2370
2371                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
2372                                   port_num, vlan, smac))
2373                         goto out;
2374
2375                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2376                            MLX4_QP_OPTPAR_SCHED_QUEUE);
2377
2378                 if (is_eth &&
2379                     (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2380                         u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
2381
2382                         if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2383                                 err = -EINVAL;
2384                                 goto out;
2385                         }
2386                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2387                 }
2388
2389         }
2390
2391         if (attr_mask & IB_QP_TIMEOUT) {
2392                 context->pri_path.ackto |= attr->timeout << 3;
2393                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2394         }
2395
2396         if (attr_mask & IB_QP_ALT_PATH) {
2397                 if (attr->alt_port_num == 0 ||
2398                     attr->alt_port_num > dev->dev->caps.num_ports)
2399                         goto out;
2400
2401                 if (attr->alt_pkey_index >=
2402                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
2403                         goto out;
2404
2405                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2406                                       &context->alt_path,
2407                                       attr->alt_port_num))
2408                         goto out;
2409
2410                 context->alt_path.pkey_index = attr->alt_pkey_index;
2411                 context->alt_path.ackto = attr->alt_timeout << 3;
2412                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2413         }
2414
2415         context->pd = cpu_to_be32(pd->pdn);
2416
2417         if (!rwq_ind_tbl) {
2418                 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2419                 get_cqs(qp, src_type, &send_cq, &recv_cq);
2420         } else { /* Set dummy CQs to be compatible with HV and PRM */
2421                 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2422                 recv_cq = send_cq;
2423         }
2424         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2425         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2426
2427         /* Set "fast registration enabled" for all kernel QPs */
2428         if (!ibuobject)
2429                 context->params1 |= cpu_to_be32(1 << 11);
2430
2431         if (attr_mask & IB_QP_RNR_RETRY) {
2432                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2433                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2434         }
2435
2436         if (attr_mask & IB_QP_RETRY_CNT) {
2437                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2438                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2439         }
2440
2441         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2442                 if (attr->max_rd_atomic)
2443                         context->params1 |=
2444                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2445                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2446         }
2447
2448         if (attr_mask & IB_QP_SQ_PSN)
2449                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2450
2451         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2452                 if (attr->max_dest_rd_atomic)
2453                         context->params2 |=
2454                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2455                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2456         }
2457
2458         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2459                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2460                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2461         }
2462
2463         if (ibsrq)
2464                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2465
2466         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2467                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2468                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2469         }
2470         if (attr_mask & IB_QP_RQ_PSN)
2471                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2472
2473         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
2474         if (attr_mask & IB_QP_QKEY) {
2475                 if (qp->mlx4_ib_qp_type &
2476                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2477                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2478                 else {
2479                         if (mlx4_is_mfunc(dev->dev) &&
2480                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2481                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2482                             MLX4_RESERVED_QKEY_BASE) {
2483                                 pr_err("Cannot use reserved QKEY"
2484                                        " 0x%x (range 0xffff0000..0xffffffff"
2485                                        " is reserved)\n", attr->qkey);
2486                                 err = -EINVAL;
2487                                 goto out;
2488                         }
2489                         context->qkey = cpu_to_be32(attr->qkey);
2490                 }
2491                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2492         }
2493
2494         if (ibsrq)
2495                 context->srqn = cpu_to_be32(1 << 24 |
2496                                             to_msrq(ibsrq)->msrq.srqn);
2497
2498         if (qp->rq.wqe_cnt &&
2499             cur_state == IB_QPS_RESET &&
2500             new_state == IB_QPS_INIT)
2501                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2502
2503         if (cur_state == IB_QPS_INIT &&
2504             new_state == IB_QPS_RTR  &&
2505             (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2506              qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
2507                 context->pri_path.sched_queue = (qp->port - 1) << 6;
2508                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2509                     qp->mlx4_ib_qp_type &
2510                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
2511                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
2512                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2513                                 context->pri_path.fl = 0x80;
2514                 } else {
2515                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2516                                 context->pri_path.fl = 0x80;
2517                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
2518                 }
2519                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2520                     IB_LINK_LAYER_ETHERNET) {
2521                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2522                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2523                                 context->pri_path.feup = 1 << 7; /* don't fsm */
2524                         /* handle smac_index */
2525                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2526                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2527                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
2528                                 err = handle_eth_ud_smac_index(dev, qp, context);
2529                                 if (err) {
2530                                         err = -EINVAL;
2531                                         goto out;
2532                                 }
2533                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2534                                         dev->qp1_proxy[qp->port - 1] = qp;
2535                         }
2536                 }
2537         }
2538
2539         if (qp_type == IB_QPT_RAW_PACKET) {
2540                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2541                                         MLX4_IB_LINK_TYPE_ETH;
2542                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2543                         /* set QP to receive both tunneled & non-tunneled packets */
2544                         if (!rwq_ind_tbl)
2545                                 context->srqn = cpu_to_be32(7 << 28);
2546                 }
2547         }
2548
2549         if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
2550                 int is_eth = rdma_port_get_link_layer(
2551                                 &dev->ib_dev, qp->port) ==
2552                                 IB_LINK_LAYER_ETHERNET;
2553                 if (is_eth) {
2554                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2555                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2556                 }
2557         }
2558
2559         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2560             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2561                 sqd_event = 1;
2562         else
2563                 sqd_event = 0;
2564
2565         if (!ibuobject &&
2566             cur_state == IB_QPS_RESET &&
2567             new_state == IB_QPS_INIT)
2568                 context->rlkey_roce_mode |= (1 << 4);
2569
2570         /*
2571          * Before passing a kernel QP to the HW, make sure that the
2572          * ownership bits of the send queue are set and the SQ
2573          * headroom is stamped so that the hardware doesn't start
2574          * processing stale work requests.
2575          */
2576         if (!ibuobject &&
2577             cur_state == IB_QPS_RESET &&
2578             new_state == IB_QPS_INIT) {
2579                 struct mlx4_wqe_ctrl_seg *ctrl;
2580                 int i;
2581
2582                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
2583                         ctrl = get_send_wqe(qp, i);
2584                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
2585                         if (qp->sq_max_wqes_per_wr == 1)
2586                                 ctrl->qpn_vlan.fence_size =
2587                                                 1 << (qp->sq.wqe_shift - 4);
2588
2589                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
2590                 }
2591         }
2592
2593         if (rwq_ind_tbl &&
2594             cur_state == IB_QPS_RESET &&
2595             new_state == IB_QPS_INIT) {
2596                 fill_qp_rss_context(context, qp);
2597                 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2598         }
2599
2600         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2601                              to_mlx4_state(new_state), context, optpar,
2602                              sqd_event, &qp->mqp);
2603         if (err)
2604                 goto out;
2605
2606         qp->state = new_state;
2607
2608         if (attr_mask & IB_QP_ACCESS_FLAGS)
2609                 qp->atomic_rd_en = attr->qp_access_flags;
2610         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2611                 qp->resp_depth = attr->max_dest_rd_atomic;
2612         if (attr_mask & IB_QP_PORT) {
2613                 qp->port = attr->port_num;
2614                 update_mcg_macs(dev, qp);
2615         }
2616         if (attr_mask & IB_QP_ALT_PATH)
2617                 qp->alt_port = attr->alt_port_num;
2618
2619         if (is_sqp(dev, qp))
2620                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2621
2622         /*
2623          * If we moved QP0 to RTR, bring the IB link up; if we moved
2624          * QP0 to RESET or ERROR, bring the link back down.
2625          */
2626         if (is_qp0(dev, qp)) {
2627                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2628                         if (mlx4_INIT_PORT(dev->dev, qp->port))
2629                                 pr_warn("INIT_PORT failed for port %d\n",
2630                                        qp->port);
2631
2632                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2633                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2634                         mlx4_CLOSE_PORT(dev->dev, qp->port);
2635         }
2636
2637         /*
2638          * If we moved a kernel QP to RESET, clean up all old CQ
2639          * entries and reinitialize the QP.
2640          */
2641         if (new_state == IB_QPS_RESET) {
2642                 if (!ibuobject) {
2643                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2644                                          ibsrq ? to_msrq(ibsrq) : NULL);
2645                         if (send_cq != recv_cq)
2646                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2647
2648                         qp->rq.head = 0;
2649                         qp->rq.tail = 0;
2650                         qp->sq.head = 0;
2651                         qp->sq.tail = 0;
2652                         qp->sq_next_wqe = 0;
2653                         if (qp->rq.wqe_cnt)
2654                                 *qp->db.db  = 0;
2655
2656                         if (qp->flags & MLX4_IB_QP_NETIF)
2657                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2658                 }
2659                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2660                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2661                         qp->pri.smac = 0;
2662                         qp->pri.smac_port = 0;
2663                 }
2664                 if (qp->alt.smac) {
2665                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2666                         qp->alt.smac = 0;
2667                 }
2668                 if (qp->pri.vid < 0x1000) {
2669                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2670                         qp->pri.vid = 0xFFFF;
2671                         qp->pri.candidate_vid = 0xFFFF;
2672                         qp->pri.update_vid = 0;
2673                 }
2674
2675                 if (qp->alt.vid < 0x1000) {
2676                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2677                         qp->alt.vid = 0xFFFF;
2678                         qp->alt.candidate_vid = 0xFFFF;
2679                         qp->alt.update_vid = 0;
2680                 }
2681         }
2682 out:
2683         if (err && qp->counter_index)
2684                 mlx4_ib_free_qp_counter(dev, qp);
2685         if (err && steer_qp)
2686                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2687         kfree(context);
2688         if (qp->pri.candidate_smac ||
2689             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2690                 if (err) {
2691                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2692                 } else {
2693                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2694                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2695                         qp->pri.smac = qp->pri.candidate_smac;
2696                         qp->pri.smac_index = qp->pri.candidate_smac_index;
2697                         qp->pri.smac_port = qp->pri.candidate_smac_port;
2698                 }
2699                 qp->pri.candidate_smac = 0;
2700                 qp->pri.candidate_smac_index = 0;
2701                 qp->pri.candidate_smac_port = 0;
2702         }
2703         if (qp->alt.candidate_smac) {
2704                 if (err) {
2705                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2706                 } else {
2707                         if (qp->alt.smac)
2708                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2709                         qp->alt.smac = qp->alt.candidate_smac;
2710                         qp->alt.smac_index = qp->alt.candidate_smac_index;
2711                         qp->alt.smac_port = qp->alt.candidate_smac_port;
2712                 }
2713                 qp->alt.candidate_smac = 0;
2714                 qp->alt.candidate_smac_index = 0;
2715                 qp->alt.candidate_smac_port = 0;
2716         }
2717
2718         if (qp->pri.update_vid) {
2719                 if (err) {
2720                         if (qp->pri.candidate_vid < 0x1000)
2721                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2722                                                      qp->pri.candidate_vid);
2723                 } else {
2724                         if (qp->pri.vid < 0x1000)
2725                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2726                                                      qp->pri.vid);
2727                         qp->pri.vid = qp->pri.candidate_vid;
2728                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2729                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
2730                 }
2731                 qp->pri.candidate_vid = 0xFFFF;
2732                 qp->pri.update_vid = 0;
2733         }
2734
2735         if (qp->alt.update_vid) {
2736                 if (err) {
2737                         if (qp->alt.candidate_vid < 0x1000)
2738                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2739                                                      qp->alt.candidate_vid);
2740                 } else {
2741                         if (qp->alt.vid < 0x1000)
2742                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2743                                                      qp->alt.vid);
2744                         qp->alt.vid = qp->alt.candidate_vid;
2745                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2746                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2747                 }
2748                 qp->alt.candidate_vid = 0xFFFF;
2749                 qp->alt.update_vid = 0;
2750         }
2751
2752         return err;
2753 }
2754
2755 enum {
2756         MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE       |
2757                                               IB_QP_PORT),
2758 };
2759
2760 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2761                               int attr_mask, struct ib_udata *udata)
2762 {
2763         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2764         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2765         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2766         enum ib_qp_state cur_state, new_state;
2767         int err = -EINVAL;
2768         mutex_lock(&qp->mutex);
2769
2770         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2771         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2772
2773         if (cur_state != new_state || cur_state != IB_QPS_RESET) {
2774                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2775                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2776         }
2777
2778         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2779                                 attr_mask, ll)) {
2780                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2781                          "for transition %d to %d. qp_type %d,"
2782                          " attr_mask 0x%x\n",
2783                          ibqp->qp_num, cur_state, new_state,
2784                          ibqp->qp_type, attr_mask);
2785                 goto out;
2786         }
2787
2788         if (ibqp->rwq_ind_tbl) {
2789                 if (!(((cur_state == IB_QPS_RESET) &&
2790                        (new_state == IB_QPS_INIT)) ||
2791                       ((cur_state == IB_QPS_INIT)  &&
2792                        (new_state == IB_QPS_RTR)))) {
2793                         pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2794                                  ibqp->qp_num, cur_state, new_state);
2795
2796                         err = -EOPNOTSUPP;
2797                         goto out;
2798                 }
2799
2800                 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2801                         pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2802                                  ibqp->qp_num, attr_mask, cur_state, new_state);
2803
2804                         err = -EOPNOTSUPP;
2805                         goto out;
2806                 }
2807         }
2808
2809         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2810                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2811                         if ((ibqp->qp_type == IB_QPT_RC) ||
2812                             (ibqp->qp_type == IB_QPT_UD) ||
2813                             (ibqp->qp_type == IB_QPT_UC) ||
2814                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2815                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2816                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2817                         }
2818                 } else {
2819                         /* no sense in changing port_num
2820                          * when ports are bonded */
2821                         attr_mask &= ~IB_QP_PORT;
2822                 }
2823         }
2824
2825         if ((attr_mask & IB_QP_PORT) &&
2826             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2827                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2828                          "for transition %d to %d. qp_type %d\n",
2829                          ibqp->qp_num, attr->port_num, cur_state,
2830                          new_state, ibqp->qp_type);
2831                 goto out;
2832         }
2833
2834         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2835             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2836              IB_LINK_LAYER_ETHERNET))
2837                 goto out;
2838
2839         if (attr_mask & IB_QP_PKEY_INDEX) {
2840                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2841                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2842                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2843                                  "for transition %d to %d. qp_type %d\n",
2844                                  ibqp->qp_num, attr->pkey_index, cur_state,
2845                                  new_state, ibqp->qp_type);
2846                         goto out;
2847                 }
2848         }
2849
2850         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2851             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2852                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2853                          "Transition %d to %d. qp_type %d\n",
2854                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2855                          new_state, ibqp->qp_type);
2856                 goto out;
2857         }
2858
2859         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2860             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2861                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2862                          "Transition %d to %d. qp_type %d\n",
2863                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2864                          new_state, ibqp->qp_type);
2865                 goto out;
2866         }
2867
2868         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2869                 err = 0;
2870                 goto out;
2871         }
2872
2873         if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2874                 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2875                 if (err)
2876                         goto out;
2877         }
2878
2879         err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2880                                   cur_state, new_state);
2881
2882         if (ibqp->rwq_ind_tbl && err)
2883                 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2884
2885         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2886                 attr->port_num = 1;
2887
2888 out:
2889         mutex_unlock(&qp->mutex);
2890         return err;
2891 }
2892
2893 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2894                       int attr_mask, struct ib_udata *udata)
2895 {
2896         struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2897         int ret;
2898
2899         ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2900
2901         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2902                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2903                 int err = 0;
2904
2905                 if (sqp->roce_v2_gsi)
2906                         err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2907                 if (err)
2908                         pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2909                                err);
2910         }
2911         return ret;
2912 }
2913
2914 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2915 {
2916         int i;
2917         for (i = 0; i < dev->caps.num_ports; i++) {
2918                 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2919                     qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2920                         *qkey = dev->caps.spec_qps[i].qp0_qkey;
2921                         return 0;
2922                 }
2923         }
2924         return -EINVAL;
2925 }
2926
2927 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2928                                   struct ib_ud_wr *wr,
2929                                   void *wqe, unsigned *mlx_seg_len)
2930 {
2931         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2932         struct ib_device *ib_dev = &mdev->ib_dev;
2933         struct mlx4_wqe_mlx_seg *mlx = wqe;
2934         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2935         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2936         u16 pkey;
2937         u32 qkey;
2938         int send_size;
2939         int header_size;
2940         int spc;
2941         int i;
2942
2943         if (wr->wr.opcode != IB_WR_SEND)
2944                 return -EINVAL;
2945
2946         send_size = 0;
2947
2948         for (i = 0; i < wr->wr.num_sge; ++i)
2949                 send_size += wr->wr.sg_list[i].length;
2950
2951         /* for proxy-qp0 sends, need to add in size of tunnel header */
2952         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2953         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2954                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2955
2956         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2957
2958         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2959                 sqp->ud_header.lrh.service_level =
2960                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2961                 sqp->ud_header.lrh.destination_lid =
2962                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2963                 sqp->ud_header.lrh.source_lid =
2964                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2965         }
2966
2967         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2968
2969         /* force loopback */
2970         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2971         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2972
2973         sqp->ud_header.lrh.virtual_lane    = 0;
2974         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2975         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2976         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2977         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2978                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2979         else
2980                 sqp->ud_header.bth.destination_qpn =
2981                         cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
2982
2983         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2984         if (mlx4_is_master(mdev->dev)) {
2985                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2986                         return -EINVAL;
2987         } else {
2988                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2989                         return -EINVAL;
2990         }
2991         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2992         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2993
2994         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2995         sqp->ud_header.immediate_present = 0;
2996
2997         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2998
2999         /*
3000          * Inline data segments may not cross a 64 byte boundary.  If
3001          * our UD header is bigger than the space available up to the
3002          * next 64 byte boundary in the WQE, use two inline data
3003          * segments to hold the UD header.
3004          */
3005         spc = MLX4_INLINE_ALIGN -
3006               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3007         if (header_size <= spc) {
3008                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3009                 memcpy(inl + 1, sqp->header_buf, header_size);
3010                 i = 1;
3011         } else {
3012                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3013                 memcpy(inl + 1, sqp->header_buf, spc);
3014
3015                 inl = (void *) (inl + 1) + spc;
3016                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3017                 /*
3018                  * Need a barrier here to make sure all the data is
3019                  * visible before the byte_count field is set.
3020                  * Otherwise the HCA prefetcher could grab the 64-byte
3021                  * chunk with this inline segment and get a valid (!=
3022                  * 0xffffffff) byte count but stale data, and end up
3023                  * generating a packet with bad headers.
3024                  *
3025                  * The first inline segment's byte_count field doesn't
3026                  * need a barrier, because it comes after a
3027                  * control/MLX segment and therefore is at an offset
3028                  * of 16 mod 64.
3029                  */
3030                 wmb();
3031                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3032                 i = 2;
3033         }
3034
3035         *mlx_seg_len =
3036         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3037         return 0;
3038 }
3039
3040 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
3041 {
3042         union sl2vl_tbl_to_u64 tmp_vltab;
3043         u8 vl;
3044
3045         if (sl > 15)
3046                 return 0xf;
3047         tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3048         vl = tmp_vltab.sl8[sl >> 1];
3049         if (sl & 1)
3050                 vl &= 0x0f;
3051         else
3052                 vl >>= 4;
3053         return vl;
3054 }
3055
3056 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3057                                 int index, union ib_gid *gid,
3058                                 enum ib_gid_type *gid_type)
3059 {
3060         struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3061         struct mlx4_port_gid_table *port_gid_table;
3062         unsigned long flags;
3063
3064         port_gid_table = &iboe->gids[port_num - 1];
3065         spin_lock_irqsave(&iboe->lock, flags);
3066         memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3067         *gid_type = port_gid_table->gids[index].gid_type;
3068         spin_unlock_irqrestore(&iboe->lock, flags);
3069         if (rdma_is_zero_gid(gid))
3070                 return -ENOENT;
3071
3072         return 0;
3073 }
3074
3075 #define MLX4_ROCEV2_QP1_SPORT 0xC000
3076 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
3077                             void *wqe, unsigned *mlx_seg_len)
3078 {
3079         struct ib_device *ib_dev = sqp->qp.ibqp.device;
3080         struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
3081         struct mlx4_wqe_mlx_seg *mlx = wqe;
3082         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
3083         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
3084         struct mlx4_ib_ah *ah = to_mah(wr->ah);
3085         union ib_gid sgid;
3086         u16 pkey;
3087         int send_size;
3088         int header_size;
3089         int spc;
3090         int i;
3091         int err = 0;
3092         u16 vlan = 0xffff;
3093         bool is_eth;
3094         bool is_vlan = false;
3095         bool is_grh;
3096         bool is_udp = false;
3097         int ip_version = 0;
3098
3099         send_size = 0;
3100         for (i = 0; i < wr->wr.num_sge; ++i)
3101                 send_size += wr->wr.sg_list[i].length;
3102
3103         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3104         is_grh = mlx4_ib_ah_grh_present(ah);
3105         if (is_eth) {
3106                 enum ib_gid_type gid_type;
3107                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3108                         /* When multi-function is enabled, the ib_core gid
3109                          * indexes don't necessarily match the hw ones, so
3110                          * we must use our own cache */
3111                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3112                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
3113                                                            ah->av.ib.gid_index, &sgid.raw[0]);
3114                         if (err)
3115                                 return err;
3116                 } else  {
3117                         err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3118                                             ah->av.ib.gid_index,
3119                                             &sgid, &gid_type);
3120                         if (!err) {
3121                                 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3122                                 if (is_udp) {
3123                                         if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3124                                                 ip_version = 4;
3125                                         else
3126                                                 ip_version = 6;
3127                                         is_grh = false;
3128                                 }
3129                         } else {
3130                                 return err;
3131                         }
3132                 }
3133                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
3134                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3135                         is_vlan = 1;
3136                 }
3137         }
3138         err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3139                           ip_version, is_udp, 0, &sqp->ud_header);
3140         if (err)
3141                 return err;
3142
3143         if (!is_eth) {
3144                 sqp->ud_header.lrh.service_level =
3145                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3146                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3147                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3148         }
3149
3150         if (is_grh || (ip_version == 6)) {
3151                 sqp->ud_header.grh.traffic_class =
3152                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3153                 sqp->ud_header.grh.flow_label    =
3154                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3155                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
3156                 if (is_eth) {
3157                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
3158                 } else {
3159                         if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3160                                 /* When multi-function is enabled, the ib_core gid
3161                                  * indexes don't necessarily match the hw ones, so
3162                                  * we must use our own cache
3163                                  */
3164                                 sqp->ud_header.grh.source_gid.global.subnet_prefix =
3165                                         cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3166                                                                     demux[sqp->qp.port - 1].
3167                                                                     subnet_prefix)));
3168                                 sqp->ud_header.grh.source_gid.global.interface_id =
3169                                         to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3170                                                        guid_cache[ah->av.ib.gid_index];
3171                         } else {
3172                                 sqp->ud_header.grh.source_gid =
3173                                         ah->ibah.sgid_attr->gid;
3174                         }
3175                 }
3176                 memcpy(sqp->ud_header.grh.destination_gid.raw,
3177                        ah->av.ib.dgid, 16);
3178         }
3179
3180         if (ip_version == 4) {
3181                 sqp->ud_header.ip4.tos =
3182                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3183                 sqp->ud_header.ip4.id = 0;
3184                 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3185                 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3186
3187                 memcpy(&sqp->ud_header.ip4.saddr,
3188                        sgid.raw + 12, 4);
3189                 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3190                 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3191         }
3192
3193         if (is_udp) {
3194                 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3195                 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3196                 sqp->ud_header.udp.csum = 0;
3197         }
3198
3199         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
3200
3201         if (!is_eth) {
3202                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3203                                           (sqp->ud_header.lrh.destination_lid ==
3204                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3205                                           (sqp->ud_header.lrh.service_level << 8));
3206                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3207                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
3208                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3209         }
3210
3211         switch (wr->wr.opcode) {
3212         case IB_WR_SEND:
3213                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
3214                 sqp->ud_header.immediate_present = 0;
3215                 break;
3216         case IB_WR_SEND_WITH_IMM:
3217                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3218                 sqp->ud_header.immediate_present = 1;
3219                 sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
3220                 break;
3221         default:
3222                 return -EINVAL;
3223         }
3224
3225         if (is_eth) {
3226                 struct in6_addr in6;
3227                 u16 ether_type;
3228                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3229
3230                 ether_type = (!is_udp) ? ETH_P_IBOE:
3231                         (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3232
3233                 mlx->sched_prio = cpu_to_be16(pcp);
3234
3235                 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
3236                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
3237                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3238                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3239                 memcpy(&in6, sgid.raw, sizeof(in6));
3240
3241
3242                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3243                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
3244                 if (!is_vlan) {
3245                         sqp->ud_header.eth.type = cpu_to_be16(ether_type);
3246                 } else {
3247                         sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
3248                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3249                 }
3250         } else {
3251                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 :
3252                                                         sl_to_vl(to_mdev(ib_dev),
3253                                                                  sqp->ud_header.lrh.service_level,
3254                                                                  sqp->qp.port);
3255                 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3256                         return -EINVAL;
3257                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3258                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3259         }
3260         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
3261         if (!sqp->qp.ibqp.qp_num)
3262                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
3263         else
3264                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
3265         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
3266         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
3267         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
3268         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3269                                                sqp->qkey : wr->remote_qkey);
3270         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3271
3272         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3273
3274         if (0) {
3275                 pr_err("built UD header of size %d:\n", header_size);
3276                 for (i = 0; i < header_size / 4; ++i) {
3277                         if (i % 8 == 0)
3278                                 pr_err("  [%02x] ", i * 4);
3279                         pr_cont(" %08x",
3280                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
3281                         if ((i + 1) % 8 == 0)
3282                                 pr_cont("\n");
3283                 }
3284                 pr_err("\n");
3285         }
3286
3287         /*
3288          * Inline data segments may not cross a 64 byte boundary.  If
3289          * our UD header is bigger than the space available up to the
3290          * next 64 byte boundary in the WQE, use two inline data
3291          * segments to hold the UD header.
3292          */
3293         spc = MLX4_INLINE_ALIGN -
3294                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3295         if (header_size <= spc) {
3296                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3297                 memcpy(inl + 1, sqp->header_buf, header_size);
3298                 i = 1;
3299         } else {
3300                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3301                 memcpy(inl + 1, sqp->header_buf, spc);
3302
3303                 inl = (void *) (inl + 1) + spc;
3304                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3305                 /*
3306                  * Need a barrier here to make sure all the data is
3307                  * visible before the byte_count field is set.
3308                  * Otherwise the HCA prefetcher could grab the 64-byte
3309                  * chunk with this inline segment and get a valid (!=
3310                  * 0xffffffff) byte count but stale data, and end up
3311                  * generating a packet with bad headers.
3312                  *
3313                  * The first inline segment's byte_count field doesn't
3314                  * need a barrier, because it comes after a
3315                  * control/MLX segment and therefore is at an offset
3316                  * of 16 mod 64.
3317                  */
3318                 wmb();
3319                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3320                 i = 2;
3321         }
3322
3323         *mlx_seg_len =
3324                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3325         return 0;
3326 }
3327
3328 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3329 {
3330         unsigned cur;
3331         struct mlx4_ib_cq *cq;
3332
3333         cur = wq->head - wq->tail;
3334         if (likely(cur + nreq < wq->max_post))
3335                 return 0;
3336
3337         cq = to_mcq(ib_cq);
3338         spin_lock(&cq->lock);
3339         cur = wq->head - wq->tail;
3340         spin_unlock(&cq->lock);
3341
3342         return cur + nreq >= wq->max_post;
3343 }
3344
3345 static __be32 convert_access(int acc)
3346 {
3347         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3348                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
3349                (acc & IB_ACCESS_REMOTE_WRITE  ?
3350                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3351                (acc & IB_ACCESS_REMOTE_READ   ?
3352                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
3353                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
3354                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3355 }
3356
3357 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3358                         struct ib_reg_wr *wr)
3359 {
3360         struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3361
3362         fseg->flags             = convert_access(wr->access);
3363         fseg->mem_key           = cpu_to_be32(wr->key);
3364         fseg->buf_list          = cpu_to_be64(mr->page_map);
3365         fseg->start_addr        = cpu_to_be64(mr->ibmr.iova);
3366         fseg->reg_len           = cpu_to_be64(mr->ibmr.length);
3367         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
3368         fseg->page_size         = cpu_to_be32(ilog2(mr->ibmr.page_size));
3369         fseg->reserved[0]       = 0;
3370         fseg->reserved[1]       = 0;
3371 }
3372
3373 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3374 {
3375         memset(iseg, 0, sizeof(*iseg));
3376         iseg->mem_key = cpu_to_be32(rkey);
3377 }
3378
3379 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3380                                           u64 remote_addr, u32 rkey)
3381 {
3382         rseg->raddr    = cpu_to_be64(remote_addr);
3383         rseg->rkey     = cpu_to_be32(rkey);
3384         rseg->reserved = 0;
3385 }
3386
3387 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3388                 struct ib_atomic_wr *wr)
3389 {
3390         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3391                 aseg->swap_add = cpu_to_be64(wr->swap);
3392                 aseg->compare  = cpu_to_be64(wr->compare_add);
3393         } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3394                 aseg->swap_add = cpu_to_be64(wr->compare_add);
3395                 aseg->compare  = cpu_to_be64(wr->compare_add_mask);
3396         } else {
3397                 aseg->swap_add = cpu_to_be64(wr->compare_add);
3398                 aseg->compare  = 0;
3399         }
3400
3401 }
3402
3403 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
3404                                   struct ib_atomic_wr *wr)
3405 {
3406         aseg->swap_add          = cpu_to_be64(wr->swap);
3407         aseg->swap_add_mask     = cpu_to_be64(wr->swap_mask);
3408         aseg->compare           = cpu_to_be64(wr->compare_add);
3409         aseg->compare_mask      = cpu_to_be64(wr->compare_add_mask);
3410 }
3411
3412 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
3413                              struct ib_ud_wr *wr)
3414 {
3415         memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3416         dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3417         dseg->qkey = cpu_to_be32(wr->remote_qkey);
3418         dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3419         memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
3420 }
3421
3422 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3423                                     struct mlx4_wqe_datagram_seg *dseg,
3424                                     struct ib_ud_wr *wr,
3425                                     enum mlx4_ib_qp_type qpt)
3426 {
3427         union mlx4_ext_av *av = &to_mah(wr->ah)->av;
3428         struct mlx4_av sqp_av = {0};
3429         int port = *((u8 *) &av->ib.port_pd) & 0x3;
3430
3431         /* force loopback */
3432         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3433         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3434         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3435                         cpu_to_be32(0xf0000000);
3436
3437         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
3438         if (qpt == MLX4_IB_QPT_PROXY_GSI)
3439                 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
3440         else
3441                 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
3442         /* Use QKEY from the QP context, which is set by master */
3443         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
3444 }
3445
3446 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
3447 {
3448         struct mlx4_wqe_inline_seg *inl = wqe;
3449         struct mlx4_ib_tunnel_header hdr;
3450         struct mlx4_ib_ah *ah = to_mah(wr->ah);
3451         int spc;
3452         int i;
3453
3454         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
3455         hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3456         hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3457         hdr.qkey = cpu_to_be32(wr->remote_qkey);
3458         memcpy(hdr.mac, ah->av.eth.mac, 6);
3459         hdr.vlan = ah->av.eth.vlan;
3460
3461         spc = MLX4_INLINE_ALIGN -
3462                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3463         if (sizeof (hdr) <= spc) {
3464                 memcpy(inl + 1, &hdr, sizeof (hdr));
3465                 wmb();
3466                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3467                 i = 1;
3468         } else {
3469                 memcpy(inl + 1, &hdr, spc);
3470                 wmb();
3471                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3472
3473                 inl = (void *) (inl + 1) + spc;
3474                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3475                 wmb();
3476                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3477                 i = 2;
3478         }
3479
3480         *mlx_seg_len =
3481                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3482 }
3483
3484 static void set_mlx_icrc_seg(void *dseg)
3485 {
3486         u32 *t = dseg;
3487         struct mlx4_wqe_inline_seg *iseg = dseg;
3488
3489         t[1] = 0;
3490
3491         /*
3492          * Need a barrier here before writing the byte_count field to
3493          * make sure that all the data is visible before the
3494          * byte_count field is set.  Otherwise, if the segment begins
3495          * a new cacheline, the HCA prefetcher could grab the 64-byte
3496          * chunk and get a valid (!= * 0xffffffff) byte count but
3497          * stale data, and end up sending the wrong data.
3498          */
3499         wmb();
3500
3501         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3502 }
3503
3504 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3505 {
3506         dseg->lkey       = cpu_to_be32(sg->lkey);
3507         dseg->addr       = cpu_to_be64(sg->addr);
3508
3509         /*
3510          * Need a barrier here before writing the byte_count field to
3511          * make sure that all the data is visible before the
3512          * byte_count field is set.  Otherwise, if the segment begins
3513          * a new cacheline, the HCA prefetcher could grab the 64-byte
3514          * chunk and get a valid (!= * 0xffffffff) byte count but
3515          * stale data, and end up sending the wrong data.
3516          */
3517         wmb();
3518
3519         dseg->byte_count = cpu_to_be32(sg->length);
3520 }
3521
3522 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3523 {
3524         dseg->byte_count = cpu_to_be32(sg->length);
3525         dseg->lkey       = cpu_to_be32(sg->lkey);
3526         dseg->addr       = cpu_to_be64(sg->addr);
3527 }
3528
3529 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
3530                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
3531                          __be32 *lso_hdr_sz, __be32 *blh)
3532 {
3533         unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
3534
3535         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3536                 *blh = cpu_to_be32(1 << 6);
3537
3538         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
3539                      wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
3540                 return -EINVAL;
3541
3542         memcpy(wqe->header, wr->header, wr->hlen);
3543
3544         *lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
3545         *lso_seg_len = halign;
3546         return 0;
3547 }
3548
3549 static __be32 send_ieth(struct ib_send_wr *wr)
3550 {
3551         switch (wr->opcode) {
3552         case IB_WR_SEND_WITH_IMM:
3553         case IB_WR_RDMA_WRITE_WITH_IMM:
3554                 return wr->ex.imm_data;
3555
3556         case IB_WR_SEND_WITH_INV:
3557                 return cpu_to_be32(wr->ex.invalidate_rkey);
3558
3559         default:
3560                 return 0;
3561         }
3562 }
3563
3564 static void add_zero_len_inline(void *wqe)
3565 {
3566         struct mlx4_wqe_inline_seg *inl = wqe;
3567         memset(wqe, 0, 16);
3568         inl->byte_count = cpu_to_be32(1 << 31);
3569 }
3570
3571 static int _mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3572                               struct ib_send_wr **bad_wr, bool drain)
3573 {
3574         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3575         void *wqe;
3576         struct mlx4_wqe_ctrl_seg *ctrl;
3577         struct mlx4_wqe_data_seg *dseg;
3578         unsigned long flags;
3579         int nreq;
3580         int err = 0;
3581         unsigned ind;
3582         int uninitialized_var(stamp);
3583         int uninitialized_var(size);
3584         unsigned uninitialized_var(seglen);
3585         __be32 dummy;
3586         __be32 *lso_wqe;
3587         __be32 uninitialized_var(lso_hdr_sz);
3588         __be32 blh;
3589         int i;
3590         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3591
3592         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3593                 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3594
3595                 if (sqp->roce_v2_gsi) {
3596                         struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
3597                         enum ib_gid_type gid_type;
3598                         union ib_gid gid;
3599
3600                         if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3601                                            ah->av.ib.gid_index,
3602                                            &gid, &gid_type))
3603                                 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3604                                                 to_mqp(sqp->roce_v2_gsi) : qp;
3605                         else
3606                                 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3607                                        ah->av.ib.gid_index);
3608                 }
3609         }
3610
3611         spin_lock_irqsave(&qp->sq.lock, flags);
3612         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3613             !drain) {
3614                 err = -EIO;
3615                 *bad_wr = wr;
3616                 nreq = 0;
3617                 goto out;
3618         }
3619
3620         ind = qp->sq_next_wqe;
3621
3622         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3623                 lso_wqe = &dummy;
3624                 blh = 0;
3625
3626                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3627                         err = -ENOMEM;
3628                         *bad_wr = wr;
3629                         goto out;
3630                 }
3631
3632                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3633                         err = -EINVAL;
3634                         *bad_wr = wr;
3635                         goto out;
3636                 }
3637
3638                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3639                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3640
3641                 ctrl->srcrb_flags =
3642                         (wr->send_flags & IB_SEND_SIGNALED ?
3643                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3644                         (wr->send_flags & IB_SEND_SOLICITED ?
3645                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3646                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
3647                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3648                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3649                         qp->sq_signal_bits;
3650
3651                 ctrl->imm = send_ieth(wr);
3652
3653                 wqe += sizeof *ctrl;
3654                 size = sizeof *ctrl / 16;
3655
3656                 switch (qp->mlx4_ib_qp_type) {
3657                 case MLX4_IB_QPT_RC:
3658                 case MLX4_IB_QPT_UC:
3659                         switch (wr->opcode) {
3660                         case IB_WR_ATOMIC_CMP_AND_SWP:
3661                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3662                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3663                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3664                                               atomic_wr(wr)->rkey);
3665                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3666
3667                                 set_atomic_seg(wqe, atomic_wr(wr));
3668                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
3669
3670                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3671                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3672
3673                                 break;
3674
3675                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3676                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3677                                               atomic_wr(wr)->rkey);
3678                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3679
3680                                 set_masked_atomic_seg(wqe, atomic_wr(wr));
3681                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
3682
3683                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3684                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3685
3686                                 break;
3687
3688                         case IB_WR_RDMA_READ:
3689                         case IB_WR_RDMA_WRITE:
3690                         case IB_WR_RDMA_WRITE_WITH_IMM:
3691                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3692                                               rdma_wr(wr)->rkey);
3693                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3694                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3695                                 break;
3696
3697                         case IB_WR_LOCAL_INV:
3698                                 ctrl->srcrb_flags |=
3699                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3700                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3701                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
3702                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3703                                 break;
3704
3705                         case IB_WR_REG_MR:
3706                                 ctrl->srcrb_flags |=
3707                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3708                                 set_reg_seg(wqe, reg_wr(wr));
3709                                 wqe  += sizeof(struct mlx4_wqe_fmr_seg);
3710                                 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3711                                 break;
3712
3713                         default:
3714                                 /* No extra segments required for sends */
3715                                 break;
3716                         }
3717                         break;
3718
3719                 case MLX4_IB_QPT_TUN_SMI_OWNER:
3720                         err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3721                                         ctrl, &seglen);
3722                         if (unlikely(err)) {
3723                                 *bad_wr = wr;
3724                                 goto out;
3725                         }
3726                         wqe  += seglen;
3727                         size += seglen / 16;
3728                         break;
3729                 case MLX4_IB_QPT_TUN_SMI:
3730                 case MLX4_IB_QPT_TUN_GSI:
3731                         /* this is a UD qp used in MAD responses to slaves. */
3732                         set_datagram_seg(wqe, ud_wr(wr));
3733                         /* set the forced-loopback bit in the data seg av */
3734                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3735                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3736                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3737                         break;
3738                 case MLX4_IB_QPT_UD:
3739                         set_datagram_seg(wqe, ud_wr(wr));
3740                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3741                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3742
3743                         if (wr->opcode == IB_WR_LSO) {
3744                                 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3745                                                 &lso_hdr_sz, &blh);
3746                                 if (unlikely(err)) {
3747                                         *bad_wr = wr;
3748                                         goto out;
3749                                 }
3750                                 lso_wqe = (__be32 *) wqe;
3751                                 wqe  += seglen;
3752                                 size += seglen / 16;
3753                         }
3754                         break;
3755
3756                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3757                         err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3758                                         ctrl, &seglen);
3759                         if (unlikely(err)) {
3760                                 *bad_wr = wr;
3761                                 goto out;
3762                         }
3763                         wqe  += seglen;
3764                         size += seglen / 16;
3765                         /* to start tunnel header on a cache-line boundary */
3766                         add_zero_len_inline(wqe);
3767                         wqe += 16;
3768                         size++;
3769                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3770                         wqe  += seglen;
3771                         size += seglen / 16;
3772                         break;
3773                 case MLX4_IB_QPT_PROXY_SMI:
3774                 case MLX4_IB_QPT_PROXY_GSI:
3775                         /* If we are tunneling special qps, this is a UD qp.
3776                          * In this case we first add a UD segment targeting
3777                          * the tunnel qp, and then add a header with address
3778                          * information */
3779                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3780                                                 ud_wr(wr),
3781                                                 qp->mlx4_ib_qp_type);
3782                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3783                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3784                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3785                         wqe  += seglen;
3786                         size += seglen / 16;
3787                         break;
3788
3789                 case MLX4_IB_QPT_SMI:
3790                 case MLX4_IB_QPT_GSI:
3791                         err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3792                                         &seglen);
3793                         if (unlikely(err)) {
3794                                 *bad_wr = wr;
3795                                 goto out;
3796                         }
3797                         wqe  += seglen;
3798                         size += seglen / 16;
3799                         break;
3800
3801                 default:
3802                         break;
3803                 }
3804
3805                 /*
3806                  * Write data segments in reverse order, so as to
3807                  * overwrite cacheline stamp last within each
3808                  * cacheline.  This avoids issues with WQE
3809                  * prefetching.
3810                  */
3811
3812                 dseg = wqe;
3813                 dseg += wr->num_sge - 1;
3814                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3815
3816                 /* Add one more inline data segment for ICRC for MLX sends */
3817                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3818                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3819                              qp->mlx4_ib_qp_type &
3820                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3821                         set_mlx_icrc_seg(dseg + 1);
3822                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
3823                 }
3824
3825                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3826                         set_data_seg(dseg, wr->sg_list + i);
3827
3828                 /*
3829                  * Possibly overwrite stamping in cacheline with LSO
3830                  * segment only after making sure all data segments
3831                  * are written.
3832                  */
3833                 wmb();
3834                 *lso_wqe = lso_hdr_sz;
3835
3836                 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3837                                              MLX4_WQE_CTRL_FENCE : 0) | size;
3838
3839                 /*
3840                  * Make sure descriptor is fully written before
3841                  * setting ownership bit (because HW can start
3842                  * executing as soon as we do).
3843                  */
3844                 wmb();
3845
3846                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3847                         *bad_wr = wr;
3848                         err = -EINVAL;
3849                         goto out;
3850                 }
3851
3852                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3853                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3854
3855                 stamp = ind + qp->sq_spare_wqes;
3856                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3857
3858                 /*
3859                  * We can improve latency by not stamping the last
3860                  * send queue WQE until after ringing the doorbell, so
3861                  * only stamp here if there are still more WQEs to post.
3862                  *
3863                  * Same optimization applies to padding with NOP wqe
3864                  * in case of WQE shrinking (used to prevent wrap-around
3865                  * in the middle of WR).
3866                  */
3867                 if (wr->next) {
3868                         stamp_send_wqe(qp, stamp, size * 16);
3869                         ind = pad_wraparound(qp, ind);
3870                 }
3871         }
3872
3873 out:
3874         if (likely(nreq)) {
3875                 qp->sq.head += nreq;
3876
3877                 /*
3878                  * Make sure that descriptors are written before
3879                  * doorbell record.
3880                  */
3881                 wmb();
3882
3883                 writel_relaxed(qp->doorbell_qpn,
3884                         to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3885
3886                 /*
3887                  * Make sure doorbells don't leak out of SQ spinlock
3888                  * and reach the HCA out of order.
3889                  */
3890                 mmiowb();
3891
3892                 stamp_send_wqe(qp, stamp, size * 16);
3893
3894                 ind = pad_wraparound(qp, ind);
3895                 qp->sq_next_wqe = ind;
3896         }
3897
3898         spin_unlock_irqrestore(&qp->sq.lock, flags);
3899
3900         return err;
3901 }
3902
3903 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3904                       struct ib_send_wr **bad_wr)
3905 {
3906         return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3907 }
3908
3909 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3910                               struct ib_recv_wr **bad_wr, bool drain)
3911 {
3912         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3913         struct mlx4_wqe_data_seg *scat;
3914         unsigned long flags;
3915         int err = 0;
3916         int nreq;
3917         int ind;
3918         int max_gs;
3919         int i;
3920         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3921
3922         max_gs = qp->rq.max_gs;
3923         spin_lock_irqsave(&qp->rq.lock, flags);
3924
3925         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3926             !drain) {
3927                 err = -EIO;
3928                 *bad_wr = wr;
3929                 nreq = 0;
3930                 goto out;
3931         }
3932
3933         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3934
3935         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3936                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3937                         err = -ENOMEM;
3938                         *bad_wr = wr;
3939                         goto out;
3940                 }
3941
3942                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3943                         err = -EINVAL;
3944                         *bad_wr = wr;
3945                         goto out;
3946                 }
3947
3948                 scat = get_recv_wqe(qp, ind);
3949
3950                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3951                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3952                         ib_dma_sync_single_for_device(ibqp->device,
3953                                                       qp->sqp_proxy_rcv[ind].map,
3954                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3955                                                       DMA_FROM_DEVICE);
3956                         scat->byte_count =
3957                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3958                         /* use dma lkey from upper layer entry */
3959                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3960                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3961                         scat++;
3962                         max_gs--;
3963                 }
3964
3965                 for (i = 0; i < wr->num_sge; ++i)
3966                         __set_data_seg(scat + i, wr->sg_list + i);
3967
3968                 if (i < max_gs) {
3969                         scat[i].byte_count = 0;
3970                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3971                         scat[i].addr       = 0;
3972                 }
3973
3974                 qp->rq.wrid[ind] = wr->wr_id;
3975
3976                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3977         }
3978
3979 out:
3980         if (likely(nreq)) {
3981                 qp->rq.head += nreq;
3982
3983                 /*
3984                  * Make sure that descriptors are written before
3985                  * doorbell record.
3986                  */
3987                 wmb();
3988
3989                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3990         }
3991
3992         spin_unlock_irqrestore(&qp->rq.lock, flags);
3993
3994         return err;
3995 }
3996
3997 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3998                       struct ib_recv_wr **bad_wr)
3999 {
4000         return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
4001 }
4002
4003 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
4004 {
4005         switch (mlx4_state) {
4006         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
4007         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
4008         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
4009         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
4010         case MLX4_QP_STATE_SQ_DRAINING:
4011         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
4012         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
4013         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
4014         default:                     return -1;
4015         }
4016 }
4017
4018 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
4019 {
4020         switch (mlx4_mig_state) {
4021         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
4022         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
4023         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4024         default: return -1;
4025         }
4026 }
4027
4028 static int to_ib_qp_access_flags(int mlx4_flags)
4029 {
4030         int ib_flags = 0;
4031
4032         if (mlx4_flags & MLX4_QP_BIT_RRE)
4033                 ib_flags |= IB_ACCESS_REMOTE_READ;
4034         if (mlx4_flags & MLX4_QP_BIT_RWE)
4035                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4036         if (mlx4_flags & MLX4_QP_BIT_RAE)
4037                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4038
4039         return ib_flags;
4040 }
4041
4042 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
4043                             struct rdma_ah_attr *ah_attr,
4044                             struct mlx4_qp_path *path)
4045 {
4046         struct mlx4_dev *dev = ibdev->dev;
4047         u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4048
4049         memset(ah_attr, 0, sizeof(*ah_attr));
4050         if (port_num == 0 || port_num > dev->caps.num_ports)
4051                 return;
4052         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
4053
4054         if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
4055                 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4056                                ((path->sched_queue & 4) << 1));
4057         else
4058                 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
4059         rdma_ah_set_port_num(ah_attr, port_num);
4060
4061         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4062         rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4063         rdma_ah_set_static_rate(ah_attr,
4064                                 path->static_rate ? path->static_rate - 5 : 0);
4065         if (path->grh_mylmc & (1 << 7)) {
4066                 rdma_ah_set_grh(ah_attr, NULL,
4067                                 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4068                                 path->mgid_index,
4069                                 path->hop_limit,
4070                                 (be32_to_cpu(path->tclass_flowlabel)
4071                                  >> 20) & 0xff);
4072                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4073         }
4074 }
4075
4076 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4077                      struct ib_qp_init_attr *qp_init_attr)
4078 {
4079         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4080         struct mlx4_ib_qp *qp = to_mqp(ibqp);
4081         struct mlx4_qp_context context;
4082         int mlx4_state;
4083         int err = 0;
4084
4085         if (ibqp->rwq_ind_tbl)
4086                 return -EOPNOTSUPP;
4087
4088         mutex_lock(&qp->mutex);
4089
4090         if (qp->state == IB_QPS_RESET) {
4091                 qp_attr->qp_state = IB_QPS_RESET;
4092                 goto done;
4093         }
4094
4095         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
4096         if (err) {
4097                 err = -EINVAL;
4098                 goto out;
4099         }
4100
4101         mlx4_state = be32_to_cpu(context.flags) >> 28;
4102
4103         qp->state                    = to_ib_qp_state(mlx4_state);
4104         qp_attr->qp_state            = qp->state;
4105         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
4106         qp_attr->path_mig_state      =
4107                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4108         qp_attr->qkey                = be32_to_cpu(context.qkey);
4109         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4110         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
4111         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
4112         qp_attr->qp_access_flags     =
4113                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4114
4115         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4116                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4117                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
4118                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
4119                 qp_attr->alt_port_num   =
4120                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4121         }
4122
4123         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
4124         if (qp_attr->qp_state == IB_QPS_INIT)
4125                 qp_attr->port_num = qp->port;
4126         else
4127                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
4128
4129         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4130         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4131
4132         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4133
4134         qp_attr->max_dest_rd_atomic =
4135                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4136         qp_attr->min_rnr_timer      =
4137                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4138         qp_attr->timeout            = context.pri_path.ackto >> 3;
4139         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
4140         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
4141         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
4142
4143 done:
4144         qp_attr->cur_qp_state        = qp_attr->qp_state;
4145         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4146         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4147
4148         if (!ibqp->uobject) {
4149                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
4150                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4151         } else {
4152                 qp_attr->cap.max_send_wr  = 0;
4153                 qp_attr->cap.max_send_sge = 0;
4154         }
4155
4156         /*
4157          * We don't support inline sends for kernel QPs (yet), and we
4158          * don't know what userspace's value should be.
4159          */
4160         qp_attr->cap.max_inline_data = 0;
4161
4162         qp_init_attr->cap            = qp_attr->cap;
4163
4164         qp_init_attr->create_flags = 0;
4165         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4166                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4167
4168         if (qp->flags & MLX4_IB_QP_LSO)
4169                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4170
4171         if (qp->flags & MLX4_IB_QP_NETIF)
4172                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4173
4174         qp_init_attr->sq_sig_type =
4175                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4176                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4177
4178 out:
4179         mutex_unlock(&qp->mutex);
4180         return err;
4181 }
4182
4183 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4184                                 struct ib_wq_init_attr *init_attr,
4185                                 struct ib_udata *udata)
4186 {
4187         struct mlx4_ib_dev *dev;
4188         struct ib_qp_init_attr ib_qp_init_attr;
4189         struct mlx4_ib_qp *qp;
4190         struct mlx4_ib_create_wq ucmd;
4191         int err, required_cmd_sz;
4192
4193         if (!(udata && pd->uobject))
4194                 return ERR_PTR(-EINVAL);
4195
4196         required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4197                           sizeof(ucmd.comp_mask);
4198         if (udata->inlen < required_cmd_sz) {
4199                 pr_debug("invalid inlen\n");
4200                 return ERR_PTR(-EINVAL);
4201         }
4202
4203         if (udata->inlen > sizeof(ucmd) &&
4204             !ib_is_udata_cleared(udata, sizeof(ucmd),
4205                                  udata->inlen - sizeof(ucmd))) {
4206                 pr_debug("inlen is not supported\n");
4207                 return ERR_PTR(-EOPNOTSUPP);
4208         }
4209
4210         if (udata->outlen)
4211                 return ERR_PTR(-EOPNOTSUPP);
4212
4213         dev = to_mdev(pd->device);
4214
4215         if (init_attr->wq_type != IB_WQT_RQ) {
4216                 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4217                 return ERR_PTR(-EOPNOTSUPP);
4218         }
4219
4220         if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) {
4221                 pr_debug("unsupported create_flags %u\n",
4222                          init_attr->create_flags);
4223                 return ERR_PTR(-EOPNOTSUPP);
4224         }
4225
4226         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4227         if (!qp)
4228                 return ERR_PTR(-ENOMEM);
4229
4230         qp->pri.vid = 0xFFFF;
4231         qp->alt.vid = 0xFFFF;
4232
4233         memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4234         ib_qp_init_attr.qp_context = init_attr->wq_context;
4235         ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4236         ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4237         ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4238         ib_qp_init_attr.recv_cq = init_attr->cq;
4239         ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4240
4241         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4242                 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4243
4244         err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4245                                udata, 0, &qp);
4246         if (err) {
4247                 kfree(qp);
4248                 return ERR_PTR(err);
4249         }
4250
4251         qp->ibwq.event_handler = init_attr->event_handler;
4252         qp->ibwq.wq_num = qp->mqp.qpn;
4253         qp->ibwq.state = IB_WQS_RESET;
4254
4255         return &qp->ibwq;
4256 }
4257
4258 static int ib_wq2qp_state(enum ib_wq_state state)
4259 {
4260         switch (state) {
4261         case IB_WQS_RESET:
4262                 return IB_QPS_RESET;
4263         case IB_WQS_RDY:
4264                 return IB_QPS_RTR;
4265         default:
4266                 return IB_QPS_ERR;
4267         }
4268 }
4269
4270 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4271 {
4272         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4273         enum ib_qp_state qp_cur_state;
4274         enum ib_qp_state qp_new_state;
4275         int attr_mask;
4276         int err;
4277
4278         /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4279          * the WQ logic state.
4280          */
4281         qp_cur_state = qp->state;
4282         qp_new_state = ib_wq2qp_state(new_state);
4283
4284         if (ib_wq2qp_state(new_state) == qp_cur_state)
4285                 return 0;
4286
4287         if (new_state == IB_WQS_RDY) {
4288                 struct ib_qp_attr attr = {};
4289
4290                 attr.port_num = qp->port;
4291                 attr_mask = IB_QP_PORT;
4292
4293                 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4294                                           attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4295                 if (err) {
4296                         pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4297                                  ibwq->wq_num);
4298                         return err;
4299                 }
4300
4301                 qp_cur_state = IB_QPS_INIT;
4302         }
4303
4304         attr_mask = 0;
4305         err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4306                                   qp_cur_state,  qp_new_state);
4307
4308         if (err && (qp_cur_state == IB_QPS_INIT)) {
4309                 qp_new_state = IB_QPS_RESET;
4310                 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4311                                         attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4312                         pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4313                                 ibwq->wq_num);
4314                         qp_new_state = IB_QPS_INIT;
4315                 }
4316         }
4317
4318         qp->state = qp_new_state;
4319
4320         return err;
4321 }
4322
4323 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4324                       u32 wq_attr_mask, struct ib_udata *udata)
4325 {
4326         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4327         struct mlx4_ib_modify_wq ucmd = {};
4328         size_t required_cmd_sz;
4329         enum ib_wq_state cur_state, new_state;
4330         int err = 0;
4331
4332         required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4333                                    sizeof(ucmd.reserved);
4334         if (udata->inlen < required_cmd_sz)
4335                 return -EINVAL;
4336
4337         if (udata->inlen > sizeof(ucmd) &&
4338             !ib_is_udata_cleared(udata, sizeof(ucmd),
4339                                  udata->inlen - sizeof(ucmd)))
4340                 return -EOPNOTSUPP;
4341
4342         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4343                 return -EFAULT;
4344
4345         if (ucmd.comp_mask || ucmd.reserved)
4346                 return -EOPNOTSUPP;
4347
4348         if (wq_attr_mask & IB_WQ_FLAGS)
4349                 return -EOPNOTSUPP;
4350
4351         cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4352                                                      ibwq->state;
4353         new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4354
4355         if (cur_state  < IB_WQS_RESET || cur_state  > IB_WQS_ERR ||
4356             new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4357                 return -EINVAL;
4358
4359         if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4360                 return -EINVAL;
4361
4362         if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4363                 return -EINVAL;
4364
4365         /* Need to protect against the parent RSS which also may modify WQ
4366          * state.
4367          */
4368         mutex_lock(&qp->mutex);
4369
4370         /* Can update HW state only if a RSS QP has already associated to this
4371          * WQ, so we can apply its port on the WQ.
4372          */
4373         if (qp->rss_usecnt)
4374                 err = _mlx4_ib_modify_wq(ibwq, new_state);
4375
4376         if (!err)
4377                 ibwq->state = new_state;
4378
4379         mutex_unlock(&qp->mutex);
4380
4381         return err;
4382 }
4383
4384 int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4385 {
4386         struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4387         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4388
4389         if (qp->counter_index)
4390                 mlx4_ib_free_qp_counter(dev, qp);
4391
4392         destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4393
4394         kfree(qp);
4395
4396         return 0;
4397 }
4398
4399 struct ib_rwq_ind_table
4400 *mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4401                               struct ib_rwq_ind_table_init_attr *init_attr,
4402                               struct ib_udata *udata)
4403 {
4404         struct ib_rwq_ind_table *rwq_ind_table;
4405         struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4406         unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4407         unsigned int base_wqn;
4408         size_t min_resp_len;
4409         int i;
4410         int err;
4411
4412         if (udata->inlen > 0 &&
4413             !ib_is_udata_cleared(udata, 0,
4414                                  udata->inlen))
4415                 return ERR_PTR(-EOPNOTSUPP);
4416
4417         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4418         if (udata->outlen && udata->outlen < min_resp_len)
4419                 return ERR_PTR(-EINVAL);
4420
4421         if (ind_tbl_size >
4422             device->attrs.rss_caps.max_rwq_indirection_table_size) {
4423                 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4424                          ind_tbl_size,
4425                          device->attrs.rss_caps.max_rwq_indirection_table_size);
4426                 return ERR_PTR(-EINVAL);
4427         }
4428
4429         base_wqn = init_attr->ind_tbl[0]->wq_num;
4430
4431         if (base_wqn % ind_tbl_size) {
4432                 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4433                          base_wqn);
4434                 return ERR_PTR(-EINVAL);
4435         }
4436
4437         for (i = 1; i < ind_tbl_size; i++) {
4438                 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4439                         pr_debug("indirection table's WQNs aren't consecutive\n");
4440                         return ERR_PTR(-EINVAL);
4441                 }
4442         }
4443
4444         rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4445         if (!rwq_ind_table)
4446                 return ERR_PTR(-ENOMEM);
4447
4448         if (udata->outlen) {
4449                 resp.response_length = offsetof(typeof(resp), response_length) +
4450                                         sizeof(resp.response_length);
4451                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4452                 if (err)
4453                         goto err;
4454         }
4455
4456         return rwq_ind_table;
4457
4458 err:
4459         kfree(rwq_ind_table);
4460         return ERR_PTR(err);
4461 }
4462
4463 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4464 {
4465         kfree(ib_rwq_ind_tbl);
4466         return 0;
4467 }
4468
4469 struct mlx4_ib_drain_cqe {
4470         struct ib_cqe cqe;
4471         struct completion done;
4472 };
4473
4474 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4475 {
4476         struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4477                                                      struct mlx4_ib_drain_cqe,
4478                                                      cqe);
4479
4480         complete(&cqe->done);
4481 }
4482
4483 /* This function returns only once the drained WR was completed */
4484 static void handle_drain_completion(struct ib_cq *cq,
4485                                     struct mlx4_ib_drain_cqe *sdrain,
4486                                     struct mlx4_ib_dev *dev)
4487 {
4488         struct mlx4_dev *mdev = dev->dev;
4489
4490         if (cq->poll_ctx == IB_POLL_DIRECT) {
4491                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4492                         ib_process_cq_direct(cq, -1);
4493                 return;
4494         }
4495
4496         if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4497                 struct mlx4_ib_cq *mcq = to_mcq(cq);
4498                 bool triggered = false;
4499                 unsigned long flags;
4500
4501                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4502                 /* Make sure that the CQ handler won't run if wasn't run yet */
4503                 if (!mcq->mcq.reset_notify_added)
4504                         mcq->mcq.reset_notify_added = 1;
4505                 else
4506                         triggered = true;
4507                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4508
4509                 if (triggered) {
4510                         /* Wait for any scheduled/running task to be ended */
4511                         switch (cq->poll_ctx) {
4512                         case IB_POLL_SOFTIRQ:
4513                                 irq_poll_disable(&cq->iop);
4514                                 irq_poll_enable(&cq->iop);
4515                                 break;
4516                         case IB_POLL_WORKQUEUE:
4517                                 cancel_work_sync(&cq->work);
4518                                 break;
4519                         default:
4520                                 WARN_ON_ONCE(1);
4521                         }
4522                 }
4523
4524                 /* Run the CQ handler - this makes sure that the drain WR will
4525                  * be processed if wasn't processed yet.
4526                  */
4527                 mcq->mcq.comp(&mcq->mcq);
4528         }
4529
4530         wait_for_completion(&sdrain->done);
4531 }
4532
4533 void mlx4_ib_drain_sq(struct ib_qp *qp)
4534 {
4535         struct ib_cq *cq = qp->send_cq;
4536         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4537         struct mlx4_ib_drain_cqe sdrain;
4538         struct ib_send_wr *bad_swr;
4539         struct ib_rdma_wr swr = {
4540                 .wr = {
4541                         .next = NULL,
4542                         { .wr_cqe       = &sdrain.cqe, },
4543                         .opcode = IB_WR_RDMA_WRITE,
4544                 },
4545         };
4546         int ret;
4547         struct mlx4_ib_dev *dev = to_mdev(qp->device);
4548         struct mlx4_dev *mdev = dev->dev;
4549
4550         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4551         if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4552                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4553                 return;
4554         }
4555
4556         sdrain.cqe.done = mlx4_ib_drain_qp_done;
4557         init_completion(&sdrain.done);
4558
4559         ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4560         if (ret) {
4561                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4562                 return;
4563         }
4564
4565         handle_drain_completion(cq, &sdrain, dev);
4566 }
4567
4568 void mlx4_ib_drain_rq(struct ib_qp *qp)
4569 {
4570         struct ib_cq *cq = qp->recv_cq;
4571         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4572         struct mlx4_ib_drain_cqe rdrain;
4573         struct ib_recv_wr rwr = {}, *bad_rwr;
4574         int ret;
4575         struct mlx4_ib_dev *dev = to_mdev(qp->device);
4576         struct mlx4_dev *mdev = dev->dev;
4577
4578         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4579         if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4580                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4581                 return;
4582         }
4583
4584         rwr.wr_cqe = &rdrain.cqe;
4585         rdrain.cqe.done = mlx4_ib_drain_qp_done;
4586         init_completion(&rdrain.done);
4587
4588         ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4589         if (ret) {
4590                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4591                 return;
4592         }
4593
4594         handle_drain_completion(cq, &rdrain, dev);
4595 }