drivers/infiniband/hw/i40iw/i40iw_type.h

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #ifndef I40IW_TYPE_H
  36 #define I40IW_TYPE_H
  37 #include "i40iw_user.h"
  38 #include "i40iw_hmc.h"
  39 #include "i40iw_vf.h"
  40 #include "i40iw_virtchnl.h"
  41
  42 struct i40iw_cqp_sq_wqe {
  43         u64 buf[I40IW_CQP_WQE_SIZE];
  44 };
  45
  46 struct i40iw_sc_aeqe {
  47         u64 buf[I40IW_AEQE_SIZE];
  48 };
  49
  50 struct i40iw_ceqe {
  51         u64 buf[I40IW_CEQE_SIZE];
  52 };
  53
  54 struct i40iw_cqp_ctx {
  55         u64 buf[I40IW_CQP_CTX_SIZE];
  56 };
  57
  58 struct i40iw_cq_shadow_area {
  59         u64 buf[I40IW_SHADOW_AREA_SIZE];
  60 };
  61
  62 struct i40iw_sc_dev;
  63 struct i40iw_hmc_info;
  64 struct i40iw_vsi_pestat;
  65
  66 struct i40iw_cqp_ops;
  67 struct i40iw_ccq_ops;
  68 struct i40iw_ceq_ops;
  69 struct i40iw_aeq_ops;
  70 struct i40iw_mr_ops;
  71 struct i40iw_cqp_misc_ops;
  72 struct i40iw_pd_ops;
  73 struct i40iw_priv_qp_ops;
  74 struct i40iw_priv_cq_ops;
  75 struct i40iw_hmc_ops;
  76 struct pci_dev;
  77
  78 enum i40iw_page_size {
  79         I40IW_PAGE_SIZE_4K,
  80         I40IW_PAGE_SIZE_2M
  81 };
  82
  83 enum i40iw_resource_indicator_type {
  84         I40IW_RSRC_INDICATOR_TYPE_ADAPTER = 0,
  85         I40IW_RSRC_INDICATOR_TYPE_CQ,
  86         I40IW_RSRC_INDICATOR_TYPE_QP,
  87         I40IW_RSRC_INDICATOR_TYPE_SRQ
  88 };
  89
  90 enum i40iw_hdrct_flags {
  91         DDP_LEN_FLAG = 0x80,
  92         DDP_HDR_FLAG = 0x40,
  93         RDMA_HDR_FLAG = 0x20
  94 };
  95
  96 enum i40iw_term_layers {
  97         LAYER_RDMA = 0,
  98         LAYER_DDP = 1,
  99         LAYER_MPA = 2
 100 };
 101
 102 enum i40iw_term_error_types {
 103         RDMAP_REMOTE_PROT = 1,
 104         RDMAP_REMOTE_OP = 2,
 105         DDP_CATASTROPHIC = 0,
 106         DDP_TAGGED_BUFFER = 1,
 107         DDP_UNTAGGED_BUFFER = 2,
 108         DDP_LLP = 3
 109 };
 110
 111 enum i40iw_term_rdma_errors {
 112         RDMAP_INV_STAG = 0x00,
 113         RDMAP_INV_BOUNDS = 0x01,
 114         RDMAP_ACCESS = 0x02,
 115         RDMAP_UNASSOC_STAG = 0x03,
 116         RDMAP_TO_WRAP = 0x04,
 117         RDMAP_INV_RDMAP_VER = 0x05,
 118         RDMAP_UNEXPECTED_OP = 0x06,
 119         RDMAP_CATASTROPHIC_LOCAL = 0x07,
 120         RDMAP_CATASTROPHIC_GLOBAL = 0x08,
 121         RDMAP_CANT_INV_STAG = 0x09,
 122         RDMAP_UNSPECIFIED = 0xff
 123 };
 124
 125 enum i40iw_term_ddp_errors {
 126         DDP_CATASTROPHIC_LOCAL = 0x00,
 127         DDP_TAGGED_INV_STAG = 0x00,
 128         DDP_TAGGED_BOUNDS = 0x01,
 129         DDP_TAGGED_UNASSOC_STAG = 0x02,
 130         DDP_TAGGED_TO_WRAP = 0x03,
 131         DDP_TAGGED_INV_DDP_VER = 0x04,
 132         DDP_UNTAGGED_INV_QN = 0x01,
 133         DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
 134         DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
 135         DDP_UNTAGGED_INV_MO = 0x04,
 136         DDP_UNTAGGED_INV_TOO_LONG = 0x05,
 137         DDP_UNTAGGED_INV_DDP_VER = 0x06
 138 };
 139
 140 enum i40iw_term_mpa_errors {
 141         MPA_CLOSED = 0x01,
 142         MPA_CRC = 0x02,
 143         MPA_MARKER = 0x03,
 144         MPA_REQ_RSP = 0x04,
 145 };
 146
 147 enum i40iw_flush_opcode {
 148         FLUSH_INVALID = 0,
 149         FLUSH_PROT_ERR,
 150         FLUSH_REM_ACCESS_ERR,
 151         FLUSH_LOC_QP_OP_ERR,
 152         FLUSH_REM_OP_ERR,
 153         FLUSH_LOC_LEN_ERR,
 154         FLUSH_GENERAL_ERR,
 155         FLUSH_FATAL_ERR
 156 };
 157
 158 enum i40iw_term_eventtypes {
 159         TERM_EVENT_QP_FATAL,
 160         TERM_EVENT_QP_ACCESS_ERR
 161 };
 162
 163 struct i40iw_terminate_hdr {
 164         u8 layer_etype;
 165         u8 error_code;
 166         u8 hdrct;
 167         u8 rsvd;
 168 };
 169
 170 enum i40iw_debug_flag {
 171         I40IW_DEBUG_NONE        = 0x00000000,
 172         I40IW_DEBUG_ERR         = 0x00000001,
 173         I40IW_DEBUG_INIT        = 0x00000002,
 174         I40IW_DEBUG_DEV         = 0x00000004,
 175         I40IW_DEBUG_CM          = 0x00000008,
 176         I40IW_DEBUG_VERBS       = 0x00000010,
 177         I40IW_DEBUG_PUDA        = 0x00000020,
 178         I40IW_DEBUG_ILQ         = 0x00000040,
 179         I40IW_DEBUG_IEQ         = 0x00000080,
 180         I40IW_DEBUG_QP          = 0x00000100,
 181         I40IW_DEBUG_CQ          = 0x00000200,
 182         I40IW_DEBUG_MR          = 0x00000400,
 183         I40IW_DEBUG_PBLE        = 0x00000800,
 184         I40IW_DEBUG_WQE         = 0x00001000,
 185         I40IW_DEBUG_AEQ         = 0x00002000,
 186         I40IW_DEBUG_CQP         = 0x00004000,
 187         I40IW_DEBUG_HMC         = 0x00008000,
 188         I40IW_DEBUG_USER        = 0x00010000,
 189         I40IW_DEBUG_VIRT        = 0x00020000,
 190         I40IW_DEBUG_DCB         = 0x00040000,
 191         I40IW_DEBUG_CQE         = 0x00800000,
 192         I40IW_DEBUG_ALL         = 0xFFFFFFFF
 193 };
 194
 195 enum i40iw_hw_stats_index_32b {
 196         I40IW_HW_STAT_INDEX_IP4RXDISCARD = 0,
 197         I40IW_HW_STAT_INDEX_IP4RXTRUNC,
 198         I40IW_HW_STAT_INDEX_IP4TXNOROUTE,
 199         I40IW_HW_STAT_INDEX_IP6RXDISCARD,
 200         I40IW_HW_STAT_INDEX_IP6RXTRUNC,
 201         I40IW_HW_STAT_INDEX_IP6TXNOROUTE,
 202         I40IW_HW_STAT_INDEX_TCPRTXSEG,
 203         I40IW_HW_STAT_INDEX_TCPRXOPTERR,
 204         I40IW_HW_STAT_INDEX_TCPRXPROTOERR,
 205         I40IW_HW_STAT_INDEX_MAX_32
 206 };
 207
 208 enum i40iw_hw_stats_index_64b {
 209         I40IW_HW_STAT_INDEX_IP4RXOCTS = 0,
 210         I40IW_HW_STAT_INDEX_IP4RXPKTS,
 211         I40IW_HW_STAT_INDEX_IP4RXFRAGS,
 212         I40IW_HW_STAT_INDEX_IP4RXMCPKTS,
 213         I40IW_HW_STAT_INDEX_IP4TXOCTS,
 214         I40IW_HW_STAT_INDEX_IP4TXPKTS,
 215         I40IW_HW_STAT_INDEX_IP4TXFRAGS,
 216         I40IW_HW_STAT_INDEX_IP4TXMCPKTS,
 217         I40IW_HW_STAT_INDEX_IP6RXOCTS,
 218         I40IW_HW_STAT_INDEX_IP6RXPKTS,
 219         I40IW_HW_STAT_INDEX_IP6RXFRAGS,
 220         I40IW_HW_STAT_INDEX_IP6RXMCPKTS,
 221         I40IW_HW_STAT_INDEX_IP6TXOCTS,
 222         I40IW_HW_STAT_INDEX_IP6TXPKTS,
 223         I40IW_HW_STAT_INDEX_IP6TXFRAGS,
 224         I40IW_HW_STAT_INDEX_IP6TXMCPKTS,
 225         I40IW_HW_STAT_INDEX_TCPRXSEGS,
 226         I40IW_HW_STAT_INDEX_TCPTXSEG,
 227         I40IW_HW_STAT_INDEX_RDMARXRDS,
 228         I40IW_HW_STAT_INDEX_RDMARXSNDS,
 229         I40IW_HW_STAT_INDEX_RDMARXWRS,
 230         I40IW_HW_STAT_INDEX_RDMATXRDS,
 231         I40IW_HW_STAT_INDEX_RDMATXSNDS,
 232         I40IW_HW_STAT_INDEX_RDMATXWRS,
 233         I40IW_HW_STAT_INDEX_RDMAVBND,
 234         I40IW_HW_STAT_INDEX_RDMAVINV,
 235         I40IW_HW_STAT_INDEX_MAX_64
 236 };
 237
 238 enum i40iw_feature_type {
 239         I40IW_FEATURE_FW_INFO = 0,
 240         I40IW_MAX_FEATURES
 241 };
 242
 243 struct i40iw_dev_hw_stats_offsets {
 244         u32 stats_offset_32[I40IW_HW_STAT_INDEX_MAX_32];
 245         u32 stats_offset_64[I40IW_HW_STAT_INDEX_MAX_64];
 246 };
 247
 248 struct i40iw_dev_hw_stats {
 249         u64 stats_value_32[I40IW_HW_STAT_INDEX_MAX_32];
 250         u64 stats_value_64[I40IW_HW_STAT_INDEX_MAX_64];
 251 };
 252
 253 struct i40iw_vsi_pestat {
 254         struct i40iw_hw *hw;
 255         struct i40iw_dev_hw_stats hw_stats;
 256         struct i40iw_dev_hw_stats last_read_hw_stats;
 257         struct i40iw_dev_hw_stats_offsets hw_stats_offsets;
 258         struct timer_list stats_timer;
 259         struct i40iw_sc_vsi *vsi;
 260         spinlock_t lock; /* rdma stats lock */
 261 };
 262
 263 struct i40iw_hw {
 264         u8 __iomem *hw_addr;
 265         struct pci_dev *pcidev;
 266         struct i40iw_hmc_info hmc;
 267 };
 268
 269 struct i40iw_pfpdu {
 270         struct list_head rxlist;
 271         u32 rcv_nxt;
 272         u32 fps;
 273         u32 max_fpdu_data;
 274         bool mode;
 275         bool mpa_crc_err;
 276         u64 total_ieq_bufs;
 277         u64 fpdu_processed;
 278         u64 bad_seq_num;
 279         u64 crc_err;
 280         u64 no_tx_bufs;
 281         u64 tx_err;
 282         u64 out_of_order;
 283         u64 pmode_count;
 284 };
 285
 286 struct i40iw_sc_pd {
 287         u32 size;
 288         struct i40iw_sc_dev *dev;
 289         u16 pd_id;
 290         int abi_ver;
 291 };
 292
 293 struct i40iw_cqp_quanta {
 294         u64 elem[I40IW_CQP_WQE_SIZE];
 295 };
 296
 297 struct i40iw_sc_cqp {
 298         u32 size;
 299         u64 sq_pa;
 300         u64 host_ctx_pa;
 301         void *back_cqp;
 302         struct i40iw_sc_dev *dev;
 303         enum i40iw_status_code (*process_cqp_sds)(struct i40iw_sc_dev *,
 304                                                   struct i40iw_update_sds_info *);
 305         struct i40iw_dma_mem sdbuf;
 306         struct i40iw_ring sq_ring;
 307         struct i40iw_cqp_quanta *sq_base;
 308         u64 *host_ctx;
 309         u64 *scratch_array;
 310         u32 cqp_id;
 311         u32 sq_size;
 312         u32 hw_sq_size;
 313         u8 struct_ver;
 314         u8 polarity;
 315         bool en_datacenter_tcp;
 316         u8 hmc_profile;
 317         u8 enabled_vf_count;
 318         u8 timeout_count;
 319 };
 320
 321 struct i40iw_sc_aeq {
 322         u32 size;
 323         u64 aeq_elem_pa;
 324         struct i40iw_sc_dev *dev;
 325         struct i40iw_sc_aeqe *aeqe_base;
 326         void *pbl_list;
 327         u32 elem_cnt;
 328         struct i40iw_ring aeq_ring;
 329         bool virtual_map;
 330         u8 pbl_chunk_size;
 331         u32 first_pm_pbl_idx;
 332         u8 polarity;
 333 };
 334
 335 struct i40iw_sc_ceq {
 336         u32 size;
 337         u64 ceq_elem_pa;
 338         struct i40iw_sc_dev *dev;
 339         struct i40iw_ceqe *ceqe_base;
 340         void *pbl_list;
 341         u32 ceq_id;
 342         u32 elem_cnt;
 343         struct i40iw_ring ceq_ring;
 344         bool virtual_map;
 345         u8 pbl_chunk_size;
 346         bool tph_en;
 347         u8 tph_val;
 348         u32 first_pm_pbl_idx;
 349         u8 polarity;
 350 };
 351
 352 struct i40iw_sc_cq {
 353         struct i40iw_cq_uk cq_uk;
 354         u64 cq_pa;
 355         u64 shadow_area_pa;
 356         struct i40iw_sc_dev *dev;
 357         struct i40iw_sc_vsi *vsi;
 358         void *pbl_list;
 359         void *back_cq;
 360         u32 ceq_id;
 361         u32 shadow_read_threshold;
 362         bool ceqe_mask;
 363         bool virtual_map;
 364         u8 pbl_chunk_size;
 365         u8 cq_type;
 366         bool ceq_id_valid;
 367         bool tph_en;
 368         u8 tph_val;
 369         u32 first_pm_pbl_idx;
 370         bool check_overflow;
 371 };
 372
 373 struct i40iw_sc_qp {
 374         struct i40iw_qp_uk qp_uk;
 375         u64 sq_pa;
 376         u64 rq_pa;
 377         u64 hw_host_ctx_pa;
 378         u64 shadow_area_pa;
 379         u64 q2_pa;
 380         struct i40iw_sc_dev *dev;
 381         struct i40iw_sc_vsi *vsi;
 382         struct i40iw_sc_pd *pd;
 383         u64 *hw_host_ctx;
 384         void *llp_stream_handle;
 385         void *back_qp;
 386         struct i40iw_pfpdu pfpdu;
 387         u8 *q2_buf;
 388         u64 qp_compl_ctx;
 389         u16 qs_handle;
 390         u8 sq_tph_val;
 391         u8 rq_tph_val;
 392         u8 qp_state;
 393         u8 qp_type;
 394         u8 hw_sq_size;
 395         u8 hw_rq_size;
 396         u8 src_mac_addr_idx;
 397         bool sq_tph_en;
 398         bool rq_tph_en;
 399         bool rcv_tph_en;
 400         bool xmit_tph_en;
 401         bool virtual_map;
 402         bool flush_sq;
 403         bool flush_rq;
 404         u8 user_pri;
 405         struct list_head list;
 406         bool on_qoslist;
 407         bool sq_flush;
 408         enum i40iw_flush_opcode flush_code;
 409         enum i40iw_term_eventtypes eventtype;
 410         u8 term_flags;
 411 };
 412
 413 struct i40iw_hmc_fpm_misc {
 414         u32 max_ceqs;
 415         u32 max_sds;
 416         u32 xf_block_size;
 417         u32 q1_block_size;
 418         u32 ht_multiplier;
 419         u32 timer_bucket;
 420 };
 421
 422 struct i40iw_vchnl_if {
 423         enum i40iw_status_code (*vchnl_recv)(struct i40iw_sc_dev *, u32, u8 *, u16);
 424         enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *dev, u32, u8 *, u16);
 425 };
 426
 427 #define I40IW_VCHNL_MAX_VF_MSG_SIZE 512
 428
 429 struct i40iw_vchnl_vf_msg_buffer {
 430         struct i40iw_virtchnl_op_buf vchnl_msg;
 431         char parm_buffer[I40IW_VCHNL_MAX_VF_MSG_SIZE - 1];
 432 };
 433
 434 struct i40iw_qos {
 435         struct list_head qplist;
 436         spinlock_t lock;        /* qos list */
 437         u16 qs_handle;
 438 };
 439
 440 struct i40iw_vfdev {
 441         struct i40iw_sc_dev *pf_dev;
 442         u8 *hmc_info_mem;
 443         struct i40iw_vsi_pestat pestat;
 444         struct i40iw_hmc_pble_info *pble_info;
 445         struct i40iw_hmc_info hmc_info;
 446         struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer;
 447         u64 fpm_query_buf_pa;
 448         u64 *fpm_query_buf;
 449         u32 vf_id;
 450         u32 msg_count;
 451         bool pf_hmc_initialized;
 452         u16 pmf_index;
 453         u16 iw_vf_idx;          /* VF Device table index */
 454         bool stats_initialized;
 455 };
 456
 457 #define I40IW_INVALID_FCN_ID 0xff
 458 struct i40iw_sc_vsi {
 459         struct i40iw_sc_dev *dev;
 460         void *back_vsi; /* Owned by OS */
 461         u32 ilq_count;
 462         struct i40iw_virt_mem ilq_mem;
 463         struct i40iw_puda_rsrc *ilq;
 464         u32 ieq_count;
 465         struct i40iw_virt_mem ieq_mem;
 466         struct i40iw_puda_rsrc *ieq;
 467         u16 exception_lan_queue;
 468         u16 mtu;
 469         u8 fcn_id;
 470         bool stats_fcn_id_alloc;
 471         struct i40iw_qos qos[I40IW_MAX_USER_PRIORITY];
 472         struct i40iw_vsi_pestat *pestat;
 473 };
 474
 475 struct i40iw_sc_dev {
 476         struct list_head cqp_cmd_head;  /* head of the CQP command list */
 477         spinlock_t cqp_lock; /* cqp list sync */
 478         struct i40iw_dev_uk dev_uk;
 479         bool fcn_id_array[I40IW_MAX_STATS_COUNT];
 480         struct i40iw_dma_mem vf_fpm_query_buf[I40IW_MAX_PE_ENABLED_VF_COUNT];
 481         u64 fpm_query_buf_pa;
 482         u64 fpm_commit_buf_pa;
 483         u64 *fpm_query_buf;
 484         u64 *fpm_commit_buf;
 485         void *back_dev;
 486         struct i40iw_hw *hw;
 487         u8 __iomem *db_addr;
 488         struct i40iw_hmc_info *hmc_info;
 489         struct i40iw_hmc_pble_info *pble_info;
 490         struct i40iw_vfdev *vf_dev[I40IW_MAX_PE_ENABLED_VF_COUNT];
 491         struct i40iw_sc_cqp *cqp;
 492         struct i40iw_sc_aeq *aeq;
 493         struct i40iw_sc_ceq *ceq[I40IW_CEQ_MAX_COUNT];
 494         struct i40iw_sc_cq *ccq;
 495         const struct i40iw_cqp_ops *cqp_ops;
 496         const struct i40iw_ccq_ops *ccq_ops;
 497         const struct i40iw_ceq_ops *ceq_ops;
 498         const struct i40iw_aeq_ops *aeq_ops;
 499         const struct i40iw_pd_ops *iw_pd_ops;
 500         const struct i40iw_priv_qp_ops *iw_priv_qp_ops;
 501         const struct i40iw_priv_cq_ops *iw_priv_cq_ops;
 502         const struct i40iw_mr_ops *mr_ops;
 503         const struct i40iw_cqp_misc_ops *cqp_misc_ops;
 504         const struct i40iw_hmc_ops *hmc_ops;
 505         struct i40iw_vchnl_if vchnl_if;
 506         const struct i40iw_vf_cqp_ops *iw_vf_cqp_ops;
 507
 508         struct i40iw_hmc_fpm_misc hmc_fpm_misc;
 509         u64 feature_info[I40IW_MAX_FEATURES];
 510         u32 debug_mask;
 511         u8 hmc_fn_id;
 512         bool is_pf;
 513         bool vchnl_up;
 514         bool ceq_valid;
 515         u8 vf_id;
 516         wait_queue_head_t vf_reqs;
 517         u64 cqp_cmd_stats[OP_SIZE_CQP_STAT_ARRAY];
 518         struct i40iw_vchnl_vf_msg_buffer vchnl_vf_msg_buf;
 519         u8 hw_rev;
 520 };
 521
 522 struct i40iw_modify_cq_info {
 523         u64 cq_pa;
 524         struct i40iw_cqe *cq_base;
 525         void *pbl_list;
 526         u32 ceq_id;
 527         u32 cq_size;
 528         u32 shadow_read_threshold;
 529         bool virtual_map;
 530         u8 pbl_chunk_size;
 531         bool check_overflow;
 532         bool cq_resize;
 533         bool ceq_change;
 534         bool check_overflow_change;
 535         u32 first_pm_pbl_idx;
 536         bool ceq_valid;
 537 };
 538
 539 struct i40iw_create_qp_info {
 540         u8 next_iwarp_state;
 541         bool ord_valid;
 542         bool tcp_ctx_valid;
 543         bool cq_num_valid;
 544         bool arp_cache_idx_valid;
 545 };
 546
 547 struct i40iw_modify_qp_info {
 548         u64 rx_win0;
 549         u64 rx_win1;
 550         u8 next_iwarp_state;
 551         u8 termlen;
 552         bool ord_valid;
 553         bool tcp_ctx_valid;
 554         bool cq_num_valid;
 555         bool arp_cache_idx_valid;
 556         bool reset_tcp_conn;
 557         bool remove_hash_idx;
 558         bool dont_send_term;
 559         bool dont_send_fin;
 560         bool cached_var_valid;
 561         bool force_loopback;
 562 };
 563
 564 struct i40iw_ccq_cqe_info {
 565         struct i40iw_sc_cqp *cqp;
 566         u64 scratch;
 567         u32 op_ret_val;
 568         u16 maj_err_code;
 569         u16 min_err_code;
 570         u8 op_code;
 571         bool error;
 572 };
 573
 574 struct i40iw_l2params {
 575         u16 qs_handle_list[I40IW_MAX_USER_PRIORITY];
 576         u16 mtu;
 577 };
 578
 579 struct i40iw_vsi_init_info {
 580         struct i40iw_sc_dev *dev;
 581         void  *back_vsi;
 582         struct i40iw_l2params *params;
 583         u16 exception_lan_queue;
 584 };
 585
 586 struct i40iw_vsi_stats_info {
 587         struct i40iw_vsi_pestat *pestat;
 588         u8 fcn_id;
 589         bool alloc_fcn_id;
 590         bool stats_initialize;
 591 };
 592
 593 struct i40iw_device_init_info {
 594         u64 fpm_query_buf_pa;
 595         u64 fpm_commit_buf_pa;
 596         u64 *fpm_query_buf;
 597         u64 *fpm_commit_buf;
 598         struct i40iw_hw *hw;
 599         void __iomem *bar0;
 600         enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16);
 601         u8 hmc_fn_id;
 602         bool is_pf;
 603         u32 debug_mask;
 604 };
 605
 606 enum i40iw_cqp_hmc_profile {
 607         I40IW_HMC_PROFILE_DEFAULT = 1,
 608         I40IW_HMC_PROFILE_FAVOR_VF = 2,
 609         I40IW_HMC_PROFILE_EQUAL = 3,
 610 };
 611
 612 struct i40iw_cqp_init_info {
 613         u64 cqp_compl_ctx;
 614         u64 host_ctx_pa;
 615         u64 sq_pa;
 616         struct i40iw_sc_dev *dev;
 617         struct i40iw_cqp_quanta *sq;
 618         u64 *host_ctx;
 619         u64 *scratch_array;
 620         u32 sq_size;
 621         u8 struct_ver;
 622         bool en_datacenter_tcp;
 623         u8 hmc_profile;
 624         u8 enabled_vf_count;
 625 };
 626
 627 struct i40iw_ceq_init_info {
 628         u64 ceqe_pa;
 629         struct i40iw_sc_dev *dev;
 630         u64 *ceqe_base;
 631         void *pbl_list;
 632         u32 elem_cnt;
 633         u32 ceq_id;
 634         bool virtual_map;
 635         u8 pbl_chunk_size;
 636         bool tph_en;
 637         u8 tph_val;
 638         u32 first_pm_pbl_idx;
 639 };
 640
 641 struct i40iw_aeq_init_info {
 642         u64 aeq_elem_pa;
 643         struct i40iw_sc_dev *dev;
 644         u32 *aeqe_base;
 645         void *pbl_list;
 646         u32 elem_cnt;
 647         bool virtual_map;
 648         u8 pbl_chunk_size;
 649         u32 first_pm_pbl_idx;
 650 };
 651
 652 struct i40iw_ccq_init_info {
 653         u64 cq_pa;
 654         u64 shadow_area_pa;
 655         struct i40iw_sc_dev *dev;
 656         struct i40iw_cqe *cq_base;
 657         u64 *shadow_area;
 658         void *pbl_list;
 659         u32 num_elem;
 660         u32 ceq_id;
 661         u32 shadow_read_threshold;
 662         bool ceqe_mask;
 663         bool ceq_id_valid;
 664         bool tph_en;
 665         u8 tph_val;
 666         bool avoid_mem_cflct;
 667         bool virtual_map;
 668         u8 pbl_chunk_size;
 669         u32 first_pm_pbl_idx;
 670 };
 671
 672 struct i40iwarp_offload_info {
 673         u16 rcv_mark_offset;
 674         u16 snd_mark_offset;
 675         u16 pd_id;
 676         u8 ddp_ver;
 677         u8 rdmap_ver;
 678         u8 ord_size;
 679         u8 ird_size;
 680         bool wr_rdresp_en;
 681         bool rd_enable;
 682         bool snd_mark_en;
 683         bool rcv_mark_en;
 684         bool bind_en;
 685         bool fast_reg_en;
 686         bool priv_mode_en;
 687         bool lsmm_present;
 688         u8 iwarp_mode;
 689         bool align_hdrs;
 690         bool rcv_no_mpa_crc;
 691
 692         u8 last_byte_sent;
 693 };
 694
 695 struct i40iw_tcp_offload_info {
 696         bool ipv4;
 697         bool no_nagle;
 698         bool insert_vlan_tag;
 699         bool time_stamp;
 700         u8 cwnd_inc_limit;
 701         bool drop_ooo_seg;
 702         u8 dup_ack_thresh;
 703         u8 ttl;
 704         u8 src_mac_addr_idx;
 705         bool avoid_stretch_ack;
 706         u8 tos;
 707         u16 src_port;
 708         u16 dst_port;
 709         u32 dest_ip_addr0;
 710         u32 dest_ip_addr1;
 711         u32 dest_ip_addr2;
 712         u32 dest_ip_addr3;
 713         u32 snd_mss;
 714         u16 vlan_tag;
 715         u16 arp_idx;
 716         u32 flow_label;
 717         bool wscale;
 718         u8 tcp_state;
 719         u8 snd_wscale;
 720         u8 rcv_wscale;
 721         u32 time_stamp_recent;
 722         u32 time_stamp_age;
 723         u32 snd_nxt;
 724         u32 snd_wnd;
 725         u32 rcv_nxt;
 726         u32 rcv_wnd;
 727         u32 snd_max;
 728         u32 snd_una;
 729         u32 srtt;
 730         u32 rtt_var;
 731         u32 ss_thresh;
 732         u32 cwnd;
 733         u32 snd_wl1;
 734         u32 snd_wl2;
 735         u32 max_snd_window;
 736         u8 rexmit_thresh;
 737         u32 local_ipaddr0;
 738         u32 local_ipaddr1;
 739         u32 local_ipaddr2;
 740         u32 local_ipaddr3;
 741         bool ignore_tcp_opt;
 742         bool ignore_tcp_uns_opt;
 743 };
 744
 745 struct i40iw_qp_host_ctx_info {
 746         u64 qp_compl_ctx;
 747         struct i40iw_tcp_offload_info *tcp_info;
 748         struct i40iwarp_offload_info *iwarp_info;
 749         u32 send_cq_num;
 750         u32 rcv_cq_num;
 751         bool tcp_info_valid;
 752         bool iwarp_info_valid;
 753         bool err_rq_idx_valid;
 754         u16 err_rq_idx;
 755         bool add_to_qoslist;
 756         u8 user_pri;
 757 };
 758
 759 struct i40iw_aeqe_info {
 760         u64 compl_ctx;
 761         u32 qp_cq_id;
 762         u16 ae_id;
 763         u16 wqe_idx;
 764         u8 tcp_state;
 765         u8 iwarp_state;
 766         bool qp;
 767         bool cq;
 768         bool sq;
 769         bool in_rdrsp_wr;
 770         bool out_rdrsp;
 771         u8 q2_data_written;
 772         bool aeqe_overflow;
 773 };
 774
 775 struct i40iw_allocate_stag_info {
 776         u64 total_len;
 777         u32 chunk_size;
 778         u32 stag_idx;
 779         u32 page_size;
 780         u16 pd_id;
 781         u16 access_rights;
 782         bool remote_access;
 783         bool use_hmc_fcn_index;
 784         u8 hmc_fcn_index;
 785         bool use_pf_rid;
 786 };
 787
 788 struct i40iw_reg_ns_stag_info {
 789         u64 reg_addr_pa;
 790         u64 fbo;
 791         void *va;
 792         u64 total_len;
 793         u32 page_size;
 794         u32 chunk_size;
 795         u32 first_pm_pbl_index;
 796         enum i40iw_addressing_type addr_type;
 797         i40iw_stag_index stag_idx;
 798         u16 access_rights;
 799         u16 pd_id;
 800         i40iw_stag_key stag_key;
 801         bool use_hmc_fcn_index;
 802         u8 hmc_fcn_index;
 803         bool use_pf_rid;
 804 };
 805
 806 struct i40iw_fast_reg_stag_info {
 807         u64 wr_id;
 808         u64 reg_addr_pa;
 809         u64 fbo;
 810         void *va;
 811         u64 total_len;
 812         u32 page_size;
 813         u32 chunk_size;
 814         u32 first_pm_pbl_index;
 815         enum i40iw_addressing_type addr_type;
 816         i40iw_stag_index stag_idx;
 817         u16 access_rights;
 818         u16 pd_id;
 819         i40iw_stag_key stag_key;
 820         bool local_fence;
 821         bool read_fence;
 822         bool signaled;
 823         bool use_hmc_fcn_index;
 824         u8 hmc_fcn_index;
 825         bool use_pf_rid;
 826         bool defer_flag;
 827 };
 828
 829 struct i40iw_dealloc_stag_info {
 830         u32 stag_idx;
 831         u16 pd_id;
 832         bool mr;
 833         bool dealloc_pbl;
 834 };
 835
 836 struct i40iw_register_shared_stag {
 837         void *va;
 838         enum i40iw_addressing_type addr_type;
 839         i40iw_stag_index new_stag_idx;
 840         i40iw_stag_index parent_stag_idx;
 841         u32 access_rights;
 842         u16 pd_id;
 843         i40iw_stag_key new_stag_key;
 844 };
 845
 846 struct i40iw_qp_init_info {
 847         struct i40iw_qp_uk_init_info qp_uk_init_info;
 848         struct i40iw_sc_pd *pd;
 849         struct i40iw_sc_vsi *vsi;
 850         u64 *host_ctx;
 851         u8 *q2;
 852         u64 sq_pa;
 853         u64 rq_pa;
 854         u64 host_ctx_pa;
 855         u64 q2_pa;
 856         u64 shadow_area_pa;
 857         int abi_ver;
 858         u8 sq_tph_val;
 859         u8 rq_tph_val;
 860         u8 type;
 861         bool sq_tph_en;
 862         bool rq_tph_en;
 863         bool rcv_tph_en;
 864         bool xmit_tph_en;
 865         bool virtual_map;
 866 };
 867
 868 struct i40iw_cq_init_info {
 869         struct i40iw_sc_dev *dev;
 870         u64 cq_base_pa;
 871         u64 shadow_area_pa;
 872         u32 ceq_id;
 873         u32 shadow_read_threshold;
 874         bool virtual_map;
 875         bool ceqe_mask;
 876         u8 pbl_chunk_size;
 877         u32 first_pm_pbl_idx;
 878         bool ceq_id_valid;
 879         bool tph_en;
 880         u8 tph_val;
 881         u8 type;
 882         struct i40iw_cq_uk_init_info cq_uk_init_info;
 883 };
 884
 885 struct i40iw_upload_context_info {
 886         u64 buf_pa;
 887         bool freeze_qp;
 888         bool raw_format;
 889         u32 qp_id;
 890         u8 qp_type;
 891 };
 892
 893 struct i40iw_add_arp_cache_entry_info {
 894         u8 mac_addr[6];
 895         u32 reach_max;
 896         u16 arp_index;
 897         bool permanent;
 898 };
 899
 900 struct i40iw_apbvt_info {
 901         u16 port;
 902         bool add;
 903 };
 904
 905 enum i40iw_quad_entry_type {
 906         I40IW_QHASH_TYPE_TCP_ESTABLISHED = 1,
 907         I40IW_QHASH_TYPE_TCP_SYN,
 908 };
 909
 910 enum i40iw_quad_hash_manage_type {
 911         I40IW_QHASH_MANAGE_TYPE_DELETE = 0,
 912         I40IW_QHASH_MANAGE_TYPE_ADD,
 913         I40IW_QHASH_MANAGE_TYPE_MODIFY
 914 };
 915
 916 struct i40iw_qhash_table_info {
 917         struct i40iw_sc_vsi *vsi;
 918         enum i40iw_quad_hash_manage_type manage;
 919         enum i40iw_quad_entry_type entry_type;
 920         bool vlan_valid;
 921         bool ipv4_valid;
 922         u8 mac_addr[6];
 923         u16 vlan_id;
 924         u8 user_pri;
 925         u32 qp_num;
 926         u32 dest_ip[4];
 927         u32 src_ip[4];
 928         u16 dest_port;
 929         u16 src_port;
 930 };
 931
 932 struct i40iw_local_mac_ipaddr_entry_info {
 933         u8 mac_addr[6];
 934         u8 entry_idx;
 935 };
 936
 937 struct i40iw_qp_flush_info {
 938         u16 sq_minor_code;
 939         u16 sq_major_code;
 940         u16 rq_minor_code;
 941         u16 rq_major_code;
 942         u16 ae_code;
 943         u8 ae_source;
 944         bool sq;
 945         bool rq;
 946         bool userflushcode;
 947         bool generate_ae;
 948 };
 949
 950 struct i40iw_cqp_commit_fpm_values {
 951         u64 qp_base;
 952         u64 cq_base;
 953         u32 hte_base;
 954         u32 arp_base;
 955         u32 apbvt_inuse_base;
 956         u32 mr_base;
 957         u32 xf_base;
 958         u32 xffl_base;
 959         u32 q1_base;
 960         u32 q1fl_base;
 961         u32 fsimc_base;
 962         u32 fsiav_base;
 963         u32 pbl_base;
 964
 965         u32 qp_cnt;
 966         u32 cq_cnt;
 967         u32 hte_cnt;
 968         u32 arp_cnt;
 969         u32 mr_cnt;
 970         u32 xf_cnt;
 971         u32 xffl_cnt;
 972         u32 q1_cnt;
 973         u32 q1fl_cnt;
 974         u32 fsimc_cnt;
 975         u32 fsiav_cnt;
 976         u32 pbl_cnt;
 977 };
 978
 979 struct i40iw_cqp_query_fpm_values {
 980         u16 first_pe_sd_index;
 981         u32 qp_objsize;
 982         u32 cq_objsize;
 983         u32 hte_objsize;
 984         u32 arp_objsize;
 985         u32 mr_objsize;
 986         u32 xf_objsize;
 987         u32 q1_objsize;
 988         u32 fsimc_objsize;
 989         u32 fsiav_objsize;
 990
 991         u32 qp_max;
 992         u32 cq_max;
 993         u32 hte_max;
 994         u32 arp_max;
 995         u32 mr_max;
 996         u32 xf_max;
 997         u32 xffl_max;
 998         u32 q1_max;
 999         u32 q1fl_max;
1000         u32 fsimc_max;
1001         u32 fsiav_max;
1002         u32 pbl_max;
1003 };
1004
1005 struct i40iw_gen_ae_info {
1006         u16 ae_code;
1007         u8 ae_source;
1008 };
1009
1010 struct i40iw_cqp_ops {
1011         enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *,
1012                                            struct i40iw_cqp_init_info *);
1013         enum i40iw_status_code (*cqp_create)(struct i40iw_sc_cqp *, u16 *, u16 *);
1014         void (*cqp_post_sq)(struct i40iw_sc_cqp *);
1015         u64 *(*cqp_get_next_send_wqe)(struct i40iw_sc_cqp *, u64 scratch);
1016         enum i40iw_status_code (*cqp_destroy)(struct i40iw_sc_cqp *);
1017         enum i40iw_status_code (*poll_for_cqp_op_done)(struct i40iw_sc_cqp *, u8,
1018                                                        struct i40iw_ccq_cqe_info *);
1019 };
1020
1021 struct i40iw_ccq_ops {
1022         enum i40iw_status_code (*ccq_init)(struct i40iw_sc_cq *,
1023                                            struct i40iw_ccq_init_info *);
1024         enum i40iw_status_code (*ccq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1025         enum i40iw_status_code (*ccq_destroy)(struct i40iw_sc_cq *, u64, bool);
1026         enum i40iw_status_code (*ccq_create_done)(struct i40iw_sc_cq *);
1027         enum i40iw_status_code (*ccq_get_cqe_info)(struct i40iw_sc_cq *,
1028                                                    struct i40iw_ccq_cqe_info *);
1029         void (*ccq_arm)(struct i40iw_sc_cq *);
1030 };
1031
1032 struct i40iw_ceq_ops {
1033         enum i40iw_status_code (*ceq_init)(struct i40iw_sc_ceq *,
1034                                            struct i40iw_ceq_init_info *);
1035         enum i40iw_status_code (*ceq_create)(struct i40iw_sc_ceq *, u64, bool);
1036         enum i40iw_status_code (*cceq_create_done)(struct i40iw_sc_ceq *);
1037         enum i40iw_status_code (*cceq_destroy_done)(struct i40iw_sc_ceq *);
1038         enum i40iw_status_code (*cceq_create)(struct i40iw_sc_ceq *, u64);
1039         enum i40iw_status_code (*ceq_destroy)(struct i40iw_sc_ceq *, u64, bool);
1040         void *(*process_ceq)(struct i40iw_sc_dev *, struct i40iw_sc_ceq *);
1041 };
1042
1043 struct i40iw_aeq_ops {
1044         enum i40iw_status_code (*aeq_init)(struct i40iw_sc_aeq *,
1045                                            struct i40iw_aeq_init_info *);
1046         enum i40iw_status_code (*aeq_create)(struct i40iw_sc_aeq *, u64, bool);
1047         enum i40iw_status_code (*aeq_destroy)(struct i40iw_sc_aeq *, u64, bool);
1048         enum i40iw_status_code (*get_next_aeqe)(struct i40iw_sc_aeq *,
1049                                                 struct i40iw_aeqe_info *);
1050         enum i40iw_status_code (*repost_aeq_entries)(struct i40iw_sc_dev *, u32);
1051         enum i40iw_status_code (*aeq_create_done)(struct i40iw_sc_aeq *);
1052         enum i40iw_status_code (*aeq_destroy_done)(struct i40iw_sc_aeq *);
1053 };
1054
1055 struct i40iw_pd_ops {
1056         void (*pd_init)(struct i40iw_sc_dev *, struct i40iw_sc_pd *, u16, int);
1057 };
1058
1059 struct i40iw_priv_qp_ops {
1060         enum i40iw_status_code (*qp_init)(struct i40iw_sc_qp *, struct i40iw_qp_init_info *);
1061         enum i40iw_status_code (*qp_create)(struct i40iw_sc_qp *,
1062                                             struct i40iw_create_qp_info *, u64, bool);
1063         enum i40iw_status_code (*qp_modify)(struct i40iw_sc_qp *,
1064                                             struct i40iw_modify_qp_info *, u64, bool);
1065         enum i40iw_status_code (*qp_destroy)(struct i40iw_sc_qp *, u64, bool, bool, bool);
1066         enum i40iw_status_code (*qp_flush_wqes)(struct i40iw_sc_qp *,
1067                                                 struct i40iw_qp_flush_info *, u64, bool);
1068         enum i40iw_status_code (*qp_upload_context)(struct i40iw_sc_dev *,
1069                                                     struct i40iw_upload_context_info *,
1070                                                     u64, bool);
1071         enum i40iw_status_code (*qp_setctx)(struct i40iw_sc_qp *, u64 *,
1072                                             struct i40iw_qp_host_ctx_info *);
1073
1074         void (*qp_send_lsmm)(struct i40iw_sc_qp *, void *, u32, i40iw_stag);
1075         void (*qp_send_lsmm_nostag)(struct i40iw_sc_qp *, void *, u32);
1076         void (*qp_send_rtt)(struct i40iw_sc_qp *, bool);
1077         enum i40iw_status_code (*qp_post_wqe0)(struct i40iw_sc_qp *, u8);
1078         enum i40iw_status_code (*iw_mr_fast_register)(struct i40iw_sc_qp *,
1079                                                       struct i40iw_fast_reg_stag_info *,
1080                                                       bool);
1081 };
1082
1083 struct i40iw_priv_cq_ops {
1084         enum i40iw_status_code (*cq_init)(struct i40iw_sc_cq *, struct i40iw_cq_init_info *);
1085         enum i40iw_status_code (*cq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1086         enum i40iw_status_code (*cq_destroy)(struct i40iw_sc_cq *, u64, bool);
1087         enum i40iw_status_code (*cq_modify)(struct i40iw_sc_cq *,
1088                                             struct i40iw_modify_cq_info *, u64, bool);
1089 };
1090
1091 struct i40iw_mr_ops {
1092         enum i40iw_status_code (*alloc_stag)(struct i40iw_sc_dev *,
1093                                              struct i40iw_allocate_stag_info *, u64, bool);
1094         enum i40iw_status_code (*mr_reg_non_shared)(struct i40iw_sc_dev *,
1095                                                     struct i40iw_reg_ns_stag_info *,
1096                                                     u64, bool);
1097         enum i40iw_status_code (*mr_reg_shared)(struct i40iw_sc_dev *,
1098                                                 struct i40iw_register_shared_stag *,
1099                                                 u64, bool);
1100         enum i40iw_status_code (*dealloc_stag)(struct i40iw_sc_dev *,
1101                                                struct i40iw_dealloc_stag_info *,
1102                                                u64, bool);
1103         enum i40iw_status_code (*query_stag)(struct i40iw_sc_dev *, u64, u32, bool);
1104         enum i40iw_status_code (*mw_alloc)(struct i40iw_sc_dev *, u64, u32, u16, bool);
1105 };
1106
1107 struct i40iw_cqp_misc_ops {
1108         enum i40iw_status_code (*manage_hmc_pm_func_table)(struct i40iw_sc_cqp *,
1109                                                            u64, u8, bool, bool);
1110         enum i40iw_status_code (*set_hmc_resource_profile)(struct i40iw_sc_cqp *,
1111                                                            u64, u8, u8, bool, bool);
1112         enum i40iw_status_code (*commit_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1113                                                     struct i40iw_dma_mem *, bool, u8);
1114         enum i40iw_status_code (*query_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1115                                                    struct i40iw_dma_mem *, bool, u8);
1116         enum i40iw_status_code (*static_hmc_pages_allocated)(struct i40iw_sc_cqp *,
1117                                                              u64, u8, bool, bool);
1118         enum i40iw_status_code (*add_arp_cache_entry)(struct i40iw_sc_cqp *,
1119                                                       struct i40iw_add_arp_cache_entry_info *,
1120                                                       u64, bool);
1121         enum i40iw_status_code (*del_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1122         enum i40iw_status_code (*query_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1123         enum i40iw_status_code (*manage_apbvt_entry)(struct i40iw_sc_cqp *,
1124                                                      struct i40iw_apbvt_info *, u64, bool);
1125         enum i40iw_status_code (*manage_qhash_table_entry)(struct i40iw_sc_cqp *,
1126                                                            struct i40iw_qhash_table_info *, u64, bool);
1127         enum i40iw_status_code (*alloc_local_mac_ipaddr_table_entry)(struct i40iw_sc_cqp *, u64, bool);
1128         enum i40iw_status_code (*add_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *,
1129                                                              struct i40iw_local_mac_ipaddr_entry_info *,
1130                                                              u64, bool);
1131         enum i40iw_status_code (*del_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *, u64, u8, u8, bool);
1132         enum i40iw_status_code (*cqp_nop)(struct i40iw_sc_cqp *, u64, bool);
1133         enum i40iw_status_code (*commit_fpm_values_done)(struct i40iw_sc_cqp
1134                                                           *);
1135         enum i40iw_status_code (*query_fpm_values_done)(struct i40iw_sc_cqp *);
1136         enum i40iw_status_code (*manage_hmc_pm_func_table_done)(struct i40iw_sc_cqp *);
1137         enum i40iw_status_code (*update_suspend_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1138         enum i40iw_status_code (*update_resume_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1139 };
1140
1141 struct i40iw_hmc_ops {
1142         enum i40iw_status_code (*init_iw_hmc)(struct i40iw_sc_dev *, u8);
1143         enum i40iw_status_code (*parse_fpm_query_buf)(u64 *, struct i40iw_hmc_info *,
1144                                                       struct i40iw_hmc_fpm_misc *);
1145         enum i40iw_status_code (*configure_iw_fpm)(struct i40iw_sc_dev *, u8);
1146         enum i40iw_status_code (*parse_fpm_commit_buf)(u64 *, struct i40iw_hmc_obj_info *, u32 *sd);
1147         enum i40iw_status_code (*create_hmc_object)(struct i40iw_sc_dev *dev,
1148                                                     struct i40iw_hmc_create_obj_info *);
1149         enum i40iw_status_code (*del_hmc_object)(struct i40iw_sc_dev *dev,
1150                                                  struct i40iw_hmc_del_obj_info *,
1151                                                  bool reset);
1152         enum i40iw_status_code (*pf_init_vfhmc)(struct i40iw_sc_dev *, u8, u32 *);
1153         enum i40iw_status_code (*vf_configure_vffpm)(struct i40iw_sc_dev *, u32 *);
1154 };
1155
1156 struct cqp_info {
1157         union {
1158                 struct {
1159                         struct i40iw_sc_qp *qp;
1160                         struct i40iw_create_qp_info info;
1161                         u64 scratch;
1162                 } qp_create;
1163
1164                 struct {
1165                         struct i40iw_sc_qp *qp;
1166                         struct i40iw_modify_qp_info info;
1167                         u64 scratch;
1168                 } qp_modify;
1169
1170                 struct {
1171                         struct i40iw_sc_qp *qp;
1172                         u64 scratch;
1173                         bool remove_hash_idx;
1174                         bool ignore_mw_bnd;
1175                 } qp_destroy;
1176
1177                 struct {
1178                         struct i40iw_sc_cq *cq;
1179                         u64 scratch;
1180                         bool check_overflow;
1181                 } cq_create;
1182
1183                 struct {
1184                         struct i40iw_sc_cq *cq;
1185                         u64 scratch;
1186                 } cq_destroy;
1187
1188                 struct {
1189                         struct i40iw_sc_dev *dev;
1190                         struct i40iw_allocate_stag_info info;
1191                         u64 scratch;
1192                 } alloc_stag;
1193
1194                 struct {
1195                         struct i40iw_sc_dev *dev;
1196                         u64 scratch;
1197                         u32 mw_stag_index;
1198                         u16 pd_id;
1199                 } mw_alloc;
1200
1201                 struct {
1202                         struct i40iw_sc_dev *dev;
1203                         struct i40iw_reg_ns_stag_info info;
1204                         u64 scratch;
1205                 } mr_reg_non_shared;
1206
1207                 struct {
1208                         struct i40iw_sc_dev *dev;
1209                         struct i40iw_dealloc_stag_info info;
1210                         u64 scratch;
1211                 } dealloc_stag;
1212
1213                 struct {
1214                         struct i40iw_sc_cqp *cqp;
1215                         struct i40iw_local_mac_ipaddr_entry_info info;
1216                         u64 scratch;
1217                 } add_local_mac_ipaddr_entry;
1218
1219                 struct {
1220                         struct i40iw_sc_cqp *cqp;
1221                         struct i40iw_add_arp_cache_entry_info info;
1222                         u64 scratch;
1223                 } add_arp_cache_entry;
1224
1225                 struct {
1226                         struct i40iw_sc_cqp *cqp;
1227                         u64 scratch;
1228                         u8 entry_idx;
1229                         u8 ignore_ref_count;
1230                 } del_local_mac_ipaddr_entry;
1231
1232                 struct {
1233                         struct i40iw_sc_cqp *cqp;
1234                         u64 scratch;
1235                         u16 arp_index;
1236                 } del_arp_cache_entry;
1237
1238                 struct {
1239                         struct i40iw_sc_cqp *cqp;
1240                         struct i40iw_manage_vf_pble_info info;
1241                         u64 scratch;
1242                 } manage_vf_pble_bp;
1243
1244                 struct {
1245                         struct i40iw_sc_dev *dev;
1246                         struct i40iw_upload_context_info info;
1247                         u64 scratch;
1248                 } qp_upload_context;
1249
1250                 struct {
1251                         struct i40iw_sc_cqp *cqp;
1252                         u64 scratch;
1253                 } alloc_local_mac_ipaddr_entry;
1254
1255                 struct {
1256                         struct i40iw_sc_dev *dev;
1257                         struct i40iw_hmc_fcn_info info;
1258                         u64 scratch;
1259                 } manage_hmc_pm;
1260
1261                 struct {
1262                         struct i40iw_sc_ceq *ceq;
1263                         u64 scratch;
1264                 } ceq_create;
1265
1266                 struct {
1267                         struct i40iw_sc_ceq *ceq;
1268                         u64 scratch;
1269                 } ceq_destroy;
1270
1271                 struct {
1272                         struct i40iw_sc_aeq *aeq;
1273                         u64 scratch;
1274                 } aeq_create;
1275
1276                 struct {
1277                         struct i40iw_sc_aeq *aeq;
1278                         u64 scratch;
1279                 } aeq_destroy;
1280
1281                 struct {
1282                         struct i40iw_sc_qp *qp;
1283                         struct i40iw_qp_flush_info info;
1284                         u64 scratch;
1285                 } qp_flush_wqes;
1286
1287                 struct {
1288                         struct i40iw_sc_qp *qp;
1289                         struct i40iw_gen_ae_info info;
1290                         u64 scratch;
1291                 } gen_ae;
1292
1293                 struct {
1294                         struct i40iw_sc_cqp *cqp;
1295                         void *fpm_values_va;
1296                         u64 fpm_values_pa;
1297                         u8 hmc_fn_id;
1298                         u64 scratch;
1299                 } query_fpm_values;
1300
1301                 struct {
1302                         struct i40iw_sc_cqp *cqp;
1303                         void *fpm_values_va;
1304                         u64 fpm_values_pa;
1305                         u8 hmc_fn_id;
1306                         u64 scratch;
1307                 } commit_fpm_values;
1308
1309                 struct {
1310                         struct i40iw_sc_cqp *cqp;
1311                         struct i40iw_apbvt_info info;
1312                         u64 scratch;
1313                 } manage_apbvt_entry;
1314
1315                 struct {
1316                         struct i40iw_sc_cqp *cqp;
1317                         struct i40iw_qhash_table_info info;
1318                         u64 scratch;
1319                 } manage_qhash_table_entry;
1320
1321                 struct {
1322                         struct i40iw_sc_dev *dev;
1323                         struct i40iw_update_sds_info info;
1324                         u64 scratch;
1325                 } update_pe_sds;
1326
1327                 struct {
1328                         struct i40iw_sc_cqp *cqp;
1329                         struct i40iw_sc_qp *qp;
1330                         u64 scratch;
1331                 } suspend_resume;
1332                 struct {
1333                         struct i40iw_sc_cqp *cqp;
1334                         void *cap_va;
1335                         u64 cap_pa;
1336                         u64 scratch;
1337                 } query_rdma_features;
1338         } u;
1339 };
1340
1341 struct cqp_commands_info {
1342         struct list_head cqp_cmd_entry;
1343         u8 cqp_cmd;
1344         u8 post_sq;
1345         struct cqp_info in;
1346 };
1347
1348 struct i40iw_virtchnl_work_info {
1349         void (*callback_fcn)(void *vf_dev);
1350         void *worker_vf_dev;
1351 };
1352
1353 struct i40iw_cqp_timeout {
1354         u64 compl_cqp_cmds;
1355         u8 count;
1356 };
1357
1358 #endif