drivers/infiniband/hw/hns/hns_roce_qp.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/platform_device.h>
  36 #include <rdma/ib_addr.h>
  37 #include <rdma/ib_umem.h>
  38 #include <rdma/uverbs_ioctl.h>
  39 #include "hns_roce_common.h"
  40 #include "hns_roce_device.h"
  41 #include "hns_roce_hem.h"
  42
  43 static void flush_work_handle(struct work_struct *work)
  44 {
  45         struct hns_roce_work *flush_work = container_of(work,
  46                                         struct hns_roce_work, work);
  47         struct hns_roce_qp *hr_qp = container_of(flush_work,
  48                                         struct hns_roce_qp, flush_work);
  49         struct device *dev = flush_work->hr_dev->dev;
  50         struct ib_qp_attr attr;
  51         int attr_mask;
  52         int ret;
  53
  54         attr_mask = IB_QP_STATE;
  55         attr.qp_state = IB_QPS_ERR;
  56
  57         if (test_and_clear_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag)) {
  58                 ret = hns_roce_modify_qp(&hr_qp->ibqp, &attr, attr_mask, NULL);
  59                 if (ret)
  60                         dev_err(dev, "Modify QP to error state failed(%d) during CQE flush\n",
  61                                 ret);
  62         }
  63
  64         /*
  65          * make sure we signal QP destroy leg that flush QP was completed
  66          * so that it can safely proceed ahead now and destroy QP
  67          */
  68         if (refcount_dec_and_test(&hr_qp->refcount))
  69                 complete(&hr_qp->free);
  70 }
  71
  72 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
  73 {
  74         struct hns_roce_work *flush_work = &hr_qp->flush_work;
  75
  76         flush_work->hr_dev = hr_dev;
  77         INIT_WORK(&flush_work->work, flush_work_handle);
  78         refcount_inc(&hr_qp->refcount);
  79         queue_work(hr_dev->irq_workq, &flush_work->work);
  80 }
  81
  82 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
  83 {
  84         struct device *dev = hr_dev->dev;
  85         struct hns_roce_qp *qp;
  86
  87         xa_lock(&hr_dev->qp_table_xa);
  88         qp = __hns_roce_qp_lookup(hr_dev, qpn);
  89         if (qp)
  90                 refcount_inc(&qp->refcount);
  91         xa_unlock(&hr_dev->qp_table_xa);
  92
  93         if (!qp) {
  94                 dev_warn(dev, "Async event for bogus QP %08x\n", qpn);
  95                 return;
  96         }
  97
  98         if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 &&
  99             (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR ||
 100              event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR ||
 101              event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR ||
 102              event_type == HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION ||
 103              event_type == HNS_ROCE_EVENT_TYPE_INVALID_XRCETH)) {
 104                 qp->state = IB_QPS_ERR;
 105                 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
 106                         init_flush_work(hr_dev, qp);
 107         }
 108
 109         qp->event(qp, (enum hns_roce_event)event_type);
 110
 111         if (refcount_dec_and_test(&qp->refcount))
 112                 complete(&qp->free);
 113 }
 114
 115 static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
 116                                  enum hns_roce_event type)
 117 {
 118         struct ib_qp *ibqp = &hr_qp->ibqp;
 119         struct ib_event event;
 120
 121         if (ibqp->event_handler) {
 122                 event.device = ibqp->device;
 123                 event.element.qp = ibqp;
 124                 switch (type) {
 125                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
 126                         event.event = IB_EVENT_PATH_MIG;
 127                         break;
 128                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
 129                         event.event = IB_EVENT_COMM_EST;
 130                         break;
 131                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
 132                         event.event = IB_EVENT_SQ_DRAINED;
 133                         break;
 134                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
 135                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 136                         break;
 137                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
 138                         event.event = IB_EVENT_QP_FATAL;
 139                         break;
 140                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
 141                         event.event = IB_EVENT_PATH_MIG_ERR;
 142                         break;
 143                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
 144                         event.event = IB_EVENT_QP_REQ_ERR;
 145                         break;
 146                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
 147                 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
 148                 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
 149                         event.event = IB_EVENT_QP_ACCESS_ERR;
 150                         break;
 151                 default:
 152                         dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n",
 153                                 type, hr_qp->qpn);
 154                         return;
 155                 }
 156                 ibqp->event_handler(&event, ibqp->qp_context);
 157         }
 158 }
 159
 160 static u8 get_least_load_bankid_for_qp(struct hns_roce_bank *bank)
 161 {
 162         u32 least_load = bank[0].inuse;
 163         u8 bankid = 0;
 164         u32 bankcnt;
 165         u8 i;
 166
 167         for (i = 1; i < HNS_ROCE_QP_BANK_NUM; i++) {
 168                 bankcnt = bank[i].inuse;
 169                 if (bankcnt < least_load) {
 170                         least_load = bankcnt;
 171                         bankid = i;
 172                 }
 173         }
 174
 175         return bankid;
 176 }
 177
 178 static int alloc_qpn_with_bankid(struct hns_roce_bank *bank, u8 bankid,
 179                                  unsigned long *qpn)
 180 {
 181         int id;
 182
 183         id = ida_alloc_range(&bank->ida, bank->next, bank->max, GFP_KERNEL);
 184         if (id < 0) {
 185                 id = ida_alloc_range(&bank->ida, bank->min, bank->max,
 186                                      GFP_KERNEL);
 187                 if (id < 0)
 188                         return id;
 189         }
 190
 191         /* the QPN should keep increasing until the max value is reached. */
 192         bank->next = (id + 1) > bank->max ? bank->min : id + 1;
 193
 194         /* the lower 3 bits is bankid */
 195         *qpn = (id << 3) | bankid;
 196
 197         return 0;
 198 }
 199 static int alloc_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 200 {
 201         struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
 202         unsigned long num = 0;
 203         u8 bankid;
 204         int ret;
 205
 206         if (hr_qp->ibqp.qp_type == IB_QPT_GSI) {
 207                 /* when hw version is v1, the sqpn is allocated */
 208                 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1)
 209                         num = HNS_ROCE_MAX_PORTS +
 210                               hr_dev->iboe.phy_port[hr_qp->port];
 211                 else
 212                         num = 1;
 213
 214                 hr_qp->doorbell_qpn = 1;
 215         } else {
 216                 mutex_lock(&qp_table->bank_mutex);
 217                 bankid = get_least_load_bankid_for_qp(qp_table->bank);
 218
 219                 ret = alloc_qpn_with_bankid(&qp_table->bank[bankid], bankid,
 220                                             &num);
 221                 if (ret) {
 222                         ibdev_err(&hr_dev->ib_dev,
 223                                   "failed to alloc QPN, ret = %d\n", ret);
 224                         mutex_unlock(&qp_table->bank_mutex);
 225                         return ret;
 226                 }
 227
 228                 qp_table->bank[bankid].inuse++;
 229                 mutex_unlock(&qp_table->bank_mutex);
 230
 231                 hr_qp->doorbell_qpn = (u32)num;
 232         }
 233
 234         hr_qp->qpn = num;
 235
 236         return 0;
 237 }
 238
 239 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state)
 240 {
 241         switch (state) {
 242         case IB_QPS_RESET:
 243                 return HNS_ROCE_QP_STATE_RST;
 244         case IB_QPS_INIT:
 245                 return HNS_ROCE_QP_STATE_INIT;
 246         case IB_QPS_RTR:
 247                 return HNS_ROCE_QP_STATE_RTR;
 248         case IB_QPS_RTS:
 249                 return HNS_ROCE_QP_STATE_RTS;
 250         case IB_QPS_SQD:
 251                 return HNS_ROCE_QP_STATE_SQD;
 252         case IB_QPS_ERR:
 253                 return HNS_ROCE_QP_STATE_ERR;
 254         default:
 255                 return HNS_ROCE_QP_NUM_STATE;
 256         }
 257 }
 258
 259 static void add_qp_to_list(struct hns_roce_dev *hr_dev,
 260                            struct hns_roce_qp *hr_qp,
 261                            struct ib_cq *send_cq, struct ib_cq *recv_cq)
 262 {
 263         struct hns_roce_cq *hr_send_cq, *hr_recv_cq;
 264         unsigned long flags;
 265
 266         hr_send_cq = send_cq ? to_hr_cq(send_cq) : NULL;
 267         hr_recv_cq = recv_cq ? to_hr_cq(recv_cq) : NULL;
 268
 269         spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
 270         hns_roce_lock_cqs(hr_send_cq, hr_recv_cq);
 271
 272         list_add_tail(&hr_qp->node, &hr_dev->qp_list);
 273         if (hr_send_cq)
 274                 list_add_tail(&hr_qp->sq_node, &hr_send_cq->sq_list);
 275         if (hr_recv_cq)
 276                 list_add_tail(&hr_qp->rq_node, &hr_recv_cq->rq_list);
 277
 278         hns_roce_unlock_cqs(hr_send_cq, hr_recv_cq);
 279         spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
 280 }
 281
 282 static int hns_roce_qp_store(struct hns_roce_dev *hr_dev,
 283                              struct hns_roce_qp *hr_qp,
 284                              struct ib_qp_init_attr *init_attr)
 285 {
 286         struct xarray *xa = &hr_dev->qp_table_xa;
 287         int ret;
 288
 289         if (!hr_qp->qpn)
 290                 return -EINVAL;
 291
 292         ret = xa_err(xa_store_irq(xa, hr_qp->qpn, hr_qp, GFP_KERNEL));
 293         if (ret)
 294                 dev_err(hr_dev->dev, "Failed to xa store for QPC\n");
 295         else
 296                 /* add QP to device's QP list for softwc */
 297                 add_qp_to_list(hr_dev, hr_qp, init_attr->send_cq,
 298                                init_attr->recv_cq);
 299
 300         return ret;
 301 }
 302
 303 static int alloc_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 304 {
 305         struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
 306         struct device *dev = hr_dev->dev;
 307         int ret;
 308
 309         if (!hr_qp->qpn)
 310                 return -EINVAL;
 311
 312         /* In v1 engine, GSI QP context is saved in the RoCE hw's register */
 313         if (hr_qp->ibqp.qp_type == IB_QPT_GSI &&
 314             hr_dev->hw_rev == HNS_ROCE_HW_VER1)
 315                 return 0;
 316
 317         /* Alloc memory for QPC */
 318         ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn);
 319         if (ret) {
 320                 dev_err(dev, "Failed to get QPC table\n");
 321                 goto err_out;
 322         }
 323
 324         /* Alloc memory for IRRL */
 325         ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
 326         if (ret) {
 327                 dev_err(dev, "Failed to get IRRL table\n");
 328                 goto err_put_qp;
 329         }
 330
 331         if (hr_dev->caps.trrl_entry_sz) {
 332                 /* Alloc memory for TRRL */
 333                 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
 334                                          hr_qp->qpn);
 335                 if (ret) {
 336                         dev_err(dev, "Failed to get TRRL table\n");
 337                         goto err_put_irrl;
 338                 }
 339         }
 340
 341         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
 342                 /* Alloc memory for SCC CTX */
 343                 ret = hns_roce_table_get(hr_dev, &qp_table->sccc_table,
 344                                          hr_qp->qpn);
 345                 if (ret) {
 346                         dev_err(dev, "Failed to get SCC CTX table\n");
 347                         goto err_put_trrl;
 348                 }
 349         }
 350
 351         return 0;
 352
 353 err_put_trrl:
 354         if (hr_dev->caps.trrl_entry_sz)
 355                 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
 356
 357 err_put_irrl:
 358         hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
 359
 360 err_put_qp:
 361         hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
 362
 363 err_out:
 364         return ret;
 365 }
 366
 367 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 368 {
 369         struct xarray *xa = &hr_dev->qp_table_xa;
 370         unsigned long flags;
 371
 372         list_del(&hr_qp->node);
 373
 374         if (hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT)
 375                 list_del(&hr_qp->sq_node);
 376
 377         if (hr_qp->ibqp.qp_type != IB_QPT_XRC_INI &&
 378             hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT)
 379                 list_del(&hr_qp->rq_node);
 380
 381         xa_lock_irqsave(xa, flags);
 382         __xa_erase(xa, hr_qp->qpn);
 383         xa_unlock_irqrestore(xa, flags);
 384 }
 385
 386 static void free_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 387 {
 388         struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
 389
 390         /* In v1 engine, GSI QP context is saved in the RoCE hw's register */
 391         if (hr_qp->ibqp.qp_type == IB_QPT_GSI &&
 392             hr_dev->hw_rev == HNS_ROCE_HW_VER1)
 393                 return;
 394
 395         if (hr_dev->caps.trrl_entry_sz)
 396                 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
 397         hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
 398 }
 399
 400 static inline u8 get_qp_bankid(unsigned long qpn)
 401 {
 402         /* The lower 3 bits of QPN are used to hash to different banks */
 403         return (u8)(qpn & GENMASK(2, 0));
 404 }
 405
 406 static void free_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 407 {
 408         u8 bankid;
 409
 410         if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
 411                 return;
 412
 413         if (hr_qp->qpn < hr_dev->caps.reserved_qps)
 414                 return;
 415
 416         bankid = get_qp_bankid(hr_qp->qpn);
 417
 418         ida_free(&hr_dev->qp_table.bank[bankid].ida, hr_qp->qpn >> 3);
 419
 420         mutex_lock(&hr_dev->qp_table.bank_mutex);
 421         hr_dev->qp_table.bank[bankid].inuse--;
 422         mutex_unlock(&hr_dev->qp_table.bank_mutex);
 423 }
 424
 425 static u32 proc_rq_sge(struct hns_roce_dev *dev, struct hns_roce_qp *hr_qp,
 426                        bool user)
 427 {
 428         u32 max_sge = dev->caps.max_rq_sg;
 429
 430         if (dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 431                 return max_sge;
 432
 433         /* Reserve SGEs only for HIP08 in kernel; The userspace driver will
 434          * calculate number of max_sge with reserved SGEs when allocating wqe
 435          * buf, so there is no need to do this again in kernel. But the number
 436          * may exceed the capacity of SGEs recorded in the firmware, so the
 437          * kernel driver should just adapt the value accordingly.
 438          */
 439         if (user)
 440                 max_sge = roundup_pow_of_two(max_sge + 1);
 441         else
 442                 hr_qp->rq.rsv_sge = 1;
 443
 444         return max_sge;
 445 }
 446
 447 static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap,
 448                        struct hns_roce_qp *hr_qp, int has_rq, bool user)
 449 {
 450         u32 max_sge = proc_rq_sge(hr_dev, hr_qp, user);
 451         u32 cnt;
 452
 453         /* If srq exist, set zero for relative number of rq */
 454         if (!has_rq) {
 455                 hr_qp->rq.wqe_cnt = 0;
 456                 hr_qp->rq.max_gs = 0;
 457                 hr_qp->rq_inl_buf.wqe_cnt = 0;
 458                 cap->max_recv_wr = 0;
 459                 cap->max_recv_sge = 0;
 460
 461                 return 0;
 462         }
 463
 464         /* Check the validity of QP support capacity */
 465         if (!cap->max_recv_wr || cap->max_recv_wr > hr_dev->caps.max_wqes ||
 466             cap->max_recv_sge > max_sge) {
 467                 ibdev_err(&hr_dev->ib_dev,
 468                           "RQ config error, depth = %u, sge = %u\n",
 469                           cap->max_recv_wr, cap->max_recv_sge);
 470                 return -EINVAL;
 471         }
 472
 473         cnt = roundup_pow_of_two(max(cap->max_recv_wr, hr_dev->caps.min_wqes));
 474         if (cnt > hr_dev->caps.max_wqes) {
 475                 ibdev_err(&hr_dev->ib_dev, "rq depth %u too large\n",
 476                           cap->max_recv_wr);
 477                 return -EINVAL;
 478         }
 479
 480         hr_qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge) +
 481                                               hr_qp->rq.rsv_sge);
 482
 483         if (hr_dev->caps.max_rq_sg <= HNS_ROCE_SGE_IN_WQE)
 484                 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz);
 485         else
 486                 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz *
 487                                             hr_qp->rq.max_gs);
 488
 489         hr_qp->rq.wqe_cnt = cnt;
 490         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE &&
 491             hr_qp->ibqp.qp_type != IB_QPT_UD &&
 492             hr_qp->ibqp.qp_type != IB_QPT_GSI)
 493                 hr_qp->rq_inl_buf.wqe_cnt = cnt;
 494         else
 495                 hr_qp->rq_inl_buf.wqe_cnt = 0;
 496
 497         cap->max_recv_wr = cnt;
 498         cap->max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
 499
 500         return 0;
 501 }
 502
 503 static u32 get_wqe_ext_sge_cnt(struct hns_roce_qp *qp)
 504 {
 505         /* GSI/UD QP only has extended sge */
 506         if (qp->ibqp.qp_type == IB_QPT_GSI || qp->ibqp.qp_type == IB_QPT_UD)
 507                 return qp->sq.max_gs;
 508
 509         if (qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE)
 510                 return qp->sq.max_gs - HNS_ROCE_SGE_IN_WQE;
 511
 512         return 0;
 513 }
 514
 515 static void set_ext_sge_param(struct hns_roce_dev *hr_dev, u32 sq_wqe_cnt,
 516                               struct hns_roce_qp *hr_qp, struct ib_qp_cap *cap)
 517 {
 518         u32 total_sge_cnt;
 519         u32 wqe_sge_cnt;
 520
 521         hr_qp->sge.sge_shift = HNS_ROCE_SGE_SHIFT;
 522
 523         if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
 524                 hr_qp->sq.max_gs = HNS_ROCE_SGE_IN_WQE;
 525                 return;
 526         }
 527
 528         hr_qp->sq.max_gs = max(1U, cap->max_send_sge);
 529
 530         wqe_sge_cnt = get_wqe_ext_sge_cnt(hr_qp);
 531
 532         /* If the number of extended sge is not zero, they MUST use the
 533          * space of HNS_HW_PAGE_SIZE at least.
 534          */
 535         if (wqe_sge_cnt) {
 536                 total_sge_cnt = roundup_pow_of_two(sq_wqe_cnt * wqe_sge_cnt);
 537                 hr_qp->sge.sge_cnt = max(total_sge_cnt,
 538                                 (u32)HNS_HW_PAGE_SIZE / HNS_ROCE_SGE_SIZE);
 539         }
 540 }
 541
 542 static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev,
 543                                         struct ib_qp_cap *cap,
 544                                         struct hns_roce_ib_create_qp *ucmd)
 545 {
 546         u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz);
 547         u8 max_sq_stride = ilog2(roundup_sq_stride);
 548
 549         /* Sanity check SQ size before proceeding */
 550         if (ucmd->log_sq_stride > max_sq_stride ||
 551             ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
 552                 ibdev_err(&hr_dev->ib_dev, "failed to check SQ stride size.\n");
 553                 return -EINVAL;
 554         }
 555
 556         if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
 557                 ibdev_err(&hr_dev->ib_dev, "failed to check SQ SGE size %u.\n",
 558                           cap->max_send_sge);
 559                 return -EINVAL;
 560         }
 561
 562         return 0;
 563 }
 564
 565 static int set_user_sq_size(struct hns_roce_dev *hr_dev,
 566                             struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp,
 567                             struct hns_roce_ib_create_qp *ucmd)
 568 {
 569         struct ib_device *ibdev = &hr_dev->ib_dev;
 570         u32 cnt = 0;
 571         int ret;
 572
 573         if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) ||
 574             cnt > hr_dev->caps.max_wqes)
 575                 return -EINVAL;
 576
 577         ret = check_sq_size_with_integrity(hr_dev, cap, ucmd);
 578         if (ret) {
 579                 ibdev_err(ibdev, "failed to check user SQ size, ret = %d.\n",
 580                           ret);
 581                 return ret;
 582         }
 583
 584         set_ext_sge_param(hr_dev, cnt, hr_qp, cap);
 585
 586         hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
 587         hr_qp->sq.wqe_cnt = cnt;
 588
 589         return 0;
 590 }
 591
 592 static int set_wqe_buf_attr(struct hns_roce_dev *hr_dev,
 593                             struct hns_roce_qp *hr_qp,
 594                             struct hns_roce_buf_attr *buf_attr)
 595 {
 596         int buf_size;
 597         int idx = 0;
 598
 599         hr_qp->buff_size = 0;
 600
 601         /* SQ WQE */
 602         hr_qp->sq.offset = 0;
 603         buf_size = to_hr_hem_entries_size(hr_qp->sq.wqe_cnt,
 604                                           hr_qp->sq.wqe_shift);
 605         if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) {
 606                 buf_attr->region[idx].size = buf_size;
 607                 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sq_hop_num;
 608                 idx++;
 609                 hr_qp->buff_size += buf_size;
 610         }
 611
 612         /* extend SGE WQE in SQ */
 613         hr_qp->sge.offset = hr_qp->buff_size;
 614         buf_size = to_hr_hem_entries_size(hr_qp->sge.sge_cnt,
 615                                           hr_qp->sge.sge_shift);
 616         if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) {
 617                 buf_attr->region[idx].size = buf_size;
 618                 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sge_hop_num;
 619                 idx++;
 620                 hr_qp->buff_size += buf_size;
 621         }
 622
 623         /* RQ WQE */
 624         hr_qp->rq.offset = hr_qp->buff_size;
 625         buf_size = to_hr_hem_entries_size(hr_qp->rq.wqe_cnt,
 626                                           hr_qp->rq.wqe_shift);
 627         if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) {
 628                 buf_attr->region[idx].size = buf_size;
 629                 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_rq_hop_num;
 630                 idx++;
 631                 hr_qp->buff_size += buf_size;
 632         }
 633
 634         if (hr_qp->buff_size < 1)
 635                 return -EINVAL;
 636
 637         buf_attr->page_shift = HNS_HW_PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
 638         buf_attr->region_count = idx;
 639
 640         return 0;
 641 }
 642
 643 static int set_kernel_sq_size(struct hns_roce_dev *hr_dev,
 644                               struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp)
 645 {
 646         struct ib_device *ibdev = &hr_dev->ib_dev;
 647         u32 cnt;
 648
 649         if (!cap->max_send_wr || cap->max_send_wr > hr_dev->caps.max_wqes ||
 650             cap->max_send_sge > hr_dev->caps.max_sq_sg) {
 651                 ibdev_err(ibdev, "failed to check SQ WR or SGE num.\n");
 652                 return -EINVAL;
 653         }
 654
 655         cnt = roundup_pow_of_two(max(cap->max_send_wr, hr_dev->caps.min_wqes));
 656         if (cnt > hr_dev->caps.max_wqes) {
 657                 ibdev_err(ibdev, "failed to check WQE num, WQE num = %u.\n",
 658                           cnt);
 659                 return -EINVAL;
 660         }
 661
 662         hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz);
 663         hr_qp->sq.wqe_cnt = cnt;
 664
 665         set_ext_sge_param(hr_dev, cnt, hr_qp, cap);
 666
 667         /* sync the parameters of kernel QP to user's configuration */
 668         cap->max_send_wr = cnt;
 669         cap->max_send_sge = hr_qp->sq.max_gs;
 670
 671         return 0;
 672 }
 673
 674 static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr)
 675 {
 676         if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr)
 677                 return 0;
 678
 679         return 1;
 680 }
 681
 682 static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr)
 683 {
 684         if (attr->qp_type == IB_QPT_XRC_INI ||
 685             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 686             !attr->cap.max_recv_wr)
 687                 return 0;
 688
 689         return 1;
 690 }
 691
 692 static int alloc_rq_inline_buf(struct hns_roce_qp *hr_qp,
 693                                struct ib_qp_init_attr *init_attr)
 694 {
 695         u32 max_recv_sge = init_attr->cap.max_recv_sge;
 696         u32 wqe_cnt = hr_qp->rq_inl_buf.wqe_cnt;
 697         struct hns_roce_rinl_wqe *wqe_list;
 698         int i;
 699
 700         /* allocate recv inline buf */
 701         wqe_list = kcalloc(wqe_cnt, sizeof(struct hns_roce_rinl_wqe),
 702                            GFP_KERNEL);
 703
 704         if (!wqe_list)
 705                 goto err;
 706
 707         /* Allocate a continuous buffer for all inline sge we need */
 708         wqe_list[0].sg_list = kcalloc(wqe_cnt, (max_recv_sge *
 709                                       sizeof(struct hns_roce_rinl_sge)),
 710                                       GFP_KERNEL);
 711         if (!wqe_list[0].sg_list)
 712                 goto err_wqe_list;
 713
 714         /* Assign buffers of sg_list to each inline wqe */
 715         for (i = 1; i < wqe_cnt; i++)
 716                 wqe_list[i].sg_list = &wqe_list[0].sg_list[i * max_recv_sge];
 717
 718         hr_qp->rq_inl_buf.wqe_list = wqe_list;
 719
 720         return 0;
 721
 722 err_wqe_list:
 723         kfree(wqe_list);
 724
 725 err:
 726         return -ENOMEM;
 727 }
 728
 729 static void free_rq_inline_buf(struct hns_roce_qp *hr_qp)
 730 {
 731         if (hr_qp->rq_inl_buf.wqe_list)
 732                 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
 733         kfree(hr_qp->rq_inl_buf.wqe_list);
 734 }
 735
 736 static int alloc_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
 737                         struct ib_qp_init_attr *init_attr,
 738                         struct ib_udata *udata, unsigned long addr)
 739 {
 740         struct ib_device *ibdev = &hr_dev->ib_dev;
 741         struct hns_roce_buf_attr buf_attr = {};
 742         int ret;
 743
 744         if (!udata && hr_qp->rq_inl_buf.wqe_cnt) {
 745                 ret = alloc_rq_inline_buf(hr_qp, init_attr);
 746                 if (ret) {
 747                         ibdev_err(ibdev,
 748                                   "failed to alloc inline buf, ret = %d.\n",
 749                                   ret);
 750                         return ret;
 751                 }
 752         } else {
 753                 hr_qp->rq_inl_buf.wqe_list = NULL;
 754         }
 755
 756         ret = set_wqe_buf_attr(hr_dev, hr_qp, &buf_attr);
 757         if (ret) {
 758                 ibdev_err(ibdev, "failed to split WQE buf, ret = %d.\n", ret);
 759                 goto err_inline;
 760         }
 761         ret = hns_roce_mtr_create(hr_dev, &hr_qp->mtr, &buf_attr,
 762                                   PAGE_SHIFT + hr_dev->caps.mtt_ba_pg_sz,
 763                                   udata, addr);
 764         if (ret) {
 765                 ibdev_err(ibdev, "failed to create WQE mtr, ret = %d.\n", ret);
 766                 goto err_inline;
 767         }
 768
 769         return 0;
 770 err_inline:
 771         free_rq_inline_buf(hr_qp);
 772
 773         return ret;
 774 }
 775
 776 static void free_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 777 {
 778         hns_roce_mtr_destroy(hr_dev, &hr_qp->mtr);
 779         free_rq_inline_buf(hr_qp);
 780 }
 781
 782 static inline bool user_qp_has_sdb(struct hns_roce_dev *hr_dev,
 783                                    struct ib_qp_init_attr *init_attr,
 784                                    struct ib_udata *udata,
 785                                    struct hns_roce_ib_create_qp_resp *resp,
 786                                    struct hns_roce_ib_create_qp *ucmd)
 787 {
 788         return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) &&
 789                 udata->outlen >= offsetofend(typeof(*resp), cap_flags) &&
 790                 hns_roce_qp_has_sq(init_attr) &&
 791                 udata->inlen >= offsetofend(typeof(*ucmd), sdb_addr));
 792 }
 793
 794 static inline bool user_qp_has_rdb(struct hns_roce_dev *hr_dev,
 795                                    struct ib_qp_init_attr *init_attr,
 796                                    struct ib_udata *udata,
 797                                    struct hns_roce_ib_create_qp_resp *resp)
 798 {
 799         return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) &&
 800                 udata->outlen >= offsetofend(typeof(*resp), cap_flags) &&
 801                 hns_roce_qp_has_rq(init_attr));
 802 }
 803
 804 static inline bool kernel_qp_has_rdb(struct hns_roce_dev *hr_dev,
 805                                      struct ib_qp_init_attr *init_attr)
 806 {
 807         return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) &&
 808                 hns_roce_qp_has_rq(init_attr));
 809 }
 810
 811 static int alloc_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
 812                        struct ib_qp_init_attr *init_attr,
 813                        struct ib_udata *udata,
 814                        struct hns_roce_ib_create_qp *ucmd,
 815                        struct hns_roce_ib_create_qp_resp *resp)
 816 {
 817         struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(
 818                 udata, struct hns_roce_ucontext, ibucontext);
 819         struct ib_device *ibdev = &hr_dev->ib_dev;
 820         int ret;
 821
 822         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SDI_MODE)
 823                 hr_qp->en_flags |= HNS_ROCE_QP_CAP_OWNER_DB;
 824
 825         if (udata) {
 826                 if (user_qp_has_sdb(hr_dev, init_attr, udata, resp, ucmd)) {
 827                         ret = hns_roce_db_map_user(uctx, ucmd->sdb_addr,
 828                                                    &hr_qp->sdb);
 829                         if (ret) {
 830                                 ibdev_err(ibdev,
 831                                           "failed to map user SQ doorbell, ret = %d.\n",
 832                                           ret);
 833                                 goto err_out;
 834                         }
 835                         hr_qp->en_flags |= HNS_ROCE_QP_CAP_SQ_RECORD_DB;
 836                         resp->cap_flags |= HNS_ROCE_QP_CAP_SQ_RECORD_DB;
 837                 }
 838
 839                 if (user_qp_has_rdb(hr_dev, init_attr, udata, resp)) {
 840                         ret = hns_roce_db_map_user(uctx, ucmd->db_addr,
 841                                                    &hr_qp->rdb);
 842                         if (ret) {
 843                                 ibdev_err(ibdev,
 844                                           "failed to map user RQ doorbell, ret = %d.\n",
 845                                           ret);
 846                                 goto err_sdb;
 847                         }
 848                         hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB;
 849                         resp->cap_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB;
 850                 }
 851         } else {
 852                 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 853                         hr_qp->sq.db_reg = hr_dev->mem_base +
 854                                            HNS_ROCE_DWQE_SIZE * hr_qp->qpn;
 855                 else
 856                         hr_qp->sq.db_reg =
 857                                 hr_dev->reg_base + hr_dev->sdb_offset +
 858                                 DB_REG_OFFSET * hr_dev->priv_uar.index;
 859
 860                 hr_qp->rq.db_reg = hr_dev->reg_base + hr_dev->odb_offset +
 861                                    DB_REG_OFFSET * hr_dev->priv_uar.index;
 862
 863                 if (kernel_qp_has_rdb(hr_dev, init_attr)) {
 864                         ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0);
 865                         if (ret) {
 866                                 ibdev_err(ibdev,
 867                                           "failed to alloc kernel RQ doorbell, ret = %d.\n",
 868                                           ret);
 869                                 goto err_out;
 870                         }
 871                         *hr_qp->rdb.db_record = 0;
 872                         hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB;
 873                 }
 874         }
 875
 876         return 0;
 877 err_sdb:
 878         if (udata && hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB)
 879                 hns_roce_db_unmap_user(uctx, &hr_qp->sdb);
 880 err_out:
 881         return ret;
 882 }
 883
 884 static void free_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
 885                        struct ib_udata *udata)
 886 {
 887         struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(
 888                 udata, struct hns_roce_ucontext, ibucontext);
 889
 890         if (udata) {
 891                 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
 892                         hns_roce_db_unmap_user(uctx, &hr_qp->rdb);
 893                 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB)
 894                         hns_roce_db_unmap_user(uctx, &hr_qp->sdb);
 895         } else {
 896                 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
 897                         hns_roce_free_db(hr_dev, &hr_qp->rdb);
 898         }
 899 }
 900
 901 static int alloc_kernel_wrid(struct hns_roce_dev *hr_dev,
 902                              struct hns_roce_qp *hr_qp)
 903 {
 904         struct ib_device *ibdev = &hr_dev->ib_dev;
 905         u64 *sq_wrid = NULL;
 906         u64 *rq_wrid = NULL;
 907         int ret;
 908
 909         sq_wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64), GFP_KERNEL);
 910         if (ZERO_OR_NULL_PTR(sq_wrid)) {
 911                 ibdev_err(ibdev, "failed to alloc SQ wrid.\n");
 912                 return -ENOMEM;
 913         }
 914
 915         if (hr_qp->rq.wqe_cnt) {
 916                 rq_wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64), GFP_KERNEL);
 917                 if (ZERO_OR_NULL_PTR(rq_wrid)) {
 918                         ibdev_err(ibdev, "failed to alloc RQ wrid.\n");
 919                         ret = -ENOMEM;
 920                         goto err_sq;
 921                 }
 922         }
 923
 924         hr_qp->sq.wrid = sq_wrid;
 925         hr_qp->rq.wrid = rq_wrid;
 926         return 0;
 927 err_sq:
 928         kfree(sq_wrid);
 929
 930         return ret;
 931 }
 932
 933 static void free_kernel_wrid(struct hns_roce_qp *hr_qp)
 934 {
 935         kfree(hr_qp->rq.wrid);
 936         kfree(hr_qp->sq.wrid);
 937 }
 938
 939 static int set_qp_param(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
 940                         struct ib_qp_init_attr *init_attr,
 941                         struct ib_udata *udata,
 942                         struct hns_roce_ib_create_qp *ucmd)
 943 {
 944         struct ib_device *ibdev = &hr_dev->ib_dev;
 945         int ret;
 946
 947         hr_qp->ibqp.qp_type = init_attr->qp_type;
 948
 949         if (init_attr->cap.max_inline_data > hr_dev->caps.max_sq_inline)
 950                 init_attr->cap.max_inline_data = hr_dev->caps.max_sq_inline;
 951
 952         hr_qp->max_inline_data = init_attr->cap.max_inline_data;
 953
 954         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 955                 hr_qp->sq_signal_bits = IB_SIGNAL_ALL_WR;
 956         else
 957                 hr_qp->sq_signal_bits = IB_SIGNAL_REQ_WR;
 958
 959         ret = set_rq_size(hr_dev, &init_attr->cap, hr_qp,
 960                           hns_roce_qp_has_rq(init_attr), !!udata);
 961         if (ret) {
 962                 ibdev_err(ibdev, "failed to set user RQ size, ret = %d.\n",
 963                           ret);
 964                 return ret;
 965         }
 966
 967         if (udata) {
 968                 ret = ib_copy_from_udata(ucmd, udata,
 969                                          min(udata->inlen, sizeof(*ucmd)));
 970                 if (ret) {
 971                         ibdev_err(ibdev,
 972                                   "failed to copy QP ucmd, ret = %d\n", ret);
 973                         return ret;
 974                 }
 975
 976                 ret = set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, ucmd);
 977                 if (ret)
 978                         ibdev_err(ibdev,
 979                                   "failed to set user SQ size, ret = %d.\n",
 980                                   ret);
 981         } else {
 982                 ret = set_kernel_sq_size(hr_dev, &init_attr->cap, hr_qp);
 983                 if (ret)
 984                         ibdev_err(ibdev,
 985                                   "failed to set kernel SQ size, ret = %d.\n",
 986                                   ret);
 987         }
 988
 989         return ret;
 990 }
 991
 992 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
 993                                      struct ib_pd *ib_pd,
 994                                      struct ib_qp_init_attr *init_attr,
 995                                      struct ib_udata *udata,
 996                                      struct hns_roce_qp *hr_qp)
 997 {
 998         struct hns_roce_ib_create_qp_resp resp = {};
 999         struct ib_device *ibdev = &hr_dev->ib_dev;
1000         struct hns_roce_ib_create_qp ucmd;
1001         int ret;
1002
1003         mutex_init(&hr_qp->mutex);
1004         spin_lock_init(&hr_qp->sq.lock);
1005         spin_lock_init(&hr_qp->rq.lock);
1006
1007         hr_qp->state = IB_QPS_RESET;
1008         hr_qp->flush_flag = 0;
1009
1010         if (init_attr->create_flags)
1011                 return -EOPNOTSUPP;
1012
1013         ret = set_qp_param(hr_dev, hr_qp, init_attr, udata, &ucmd);
1014         if (ret) {
1015                 ibdev_err(ibdev, "failed to set QP param, ret = %d.\n", ret);
1016                 return ret;
1017         }
1018
1019         if (!udata) {
1020                 ret = alloc_kernel_wrid(hr_dev, hr_qp);
1021                 if (ret) {
1022                         ibdev_err(ibdev, "failed to alloc wrid, ret = %d.\n",
1023                                   ret);
1024                         return ret;
1025                 }
1026         }
1027
1028         ret = alloc_qp_buf(hr_dev, hr_qp, init_attr, udata, ucmd.buf_addr);
1029         if (ret) {
1030                 ibdev_err(ibdev, "failed to alloc QP buffer, ret = %d.\n", ret);
1031                 goto err_buf;
1032         }
1033
1034         ret = alloc_qpn(hr_dev, hr_qp);
1035         if (ret) {
1036                 ibdev_err(ibdev, "failed to alloc QPN, ret = %d.\n", ret);
1037                 goto err_qpn;
1038         }
1039
1040         ret = alloc_qp_db(hr_dev, hr_qp, init_attr, udata, &ucmd, &resp);
1041         if (ret) {
1042                 ibdev_err(ibdev, "failed to alloc QP doorbell, ret = %d.\n",
1043                           ret);
1044                 goto err_db;
1045         }
1046
1047         ret = alloc_qpc(hr_dev, hr_qp);
1048         if (ret) {
1049                 ibdev_err(ibdev, "failed to alloc QP context, ret = %d.\n",
1050                           ret);
1051                 goto err_qpc;
1052         }
1053
1054         ret = hns_roce_qp_store(hr_dev, hr_qp, init_attr);
1055         if (ret) {
1056                 ibdev_err(ibdev, "failed to store QP, ret = %d.\n", ret);
1057                 goto err_store;
1058         }
1059
1060         if (udata) {
1061                 ret = ib_copy_to_udata(udata, &resp,
1062                                        min(udata->outlen, sizeof(resp)));
1063                 if (ret) {
1064                         ibdev_err(ibdev, "copy qp resp failed!\n");
1065                         goto err_store;
1066                 }
1067         }
1068
1069         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
1070                 ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp);
1071                 if (ret)
1072                         goto err_flow_ctrl;
1073         }
1074
1075         hr_qp->ibqp.qp_num = hr_qp->qpn;
1076         hr_qp->event = hns_roce_ib_qp_event;
1077         refcount_set(&hr_qp->refcount, 1);
1078         init_completion(&hr_qp->free);
1079
1080         return 0;
1081
1082 err_flow_ctrl:
1083         hns_roce_qp_remove(hr_dev, hr_qp);
1084 err_store:
1085         free_qpc(hr_dev, hr_qp);
1086 err_qpc:
1087         free_qp_db(hr_dev, hr_qp, udata);
1088 err_db:
1089         free_qpn(hr_dev, hr_qp);
1090 err_qpn:
1091         free_qp_buf(hr_dev, hr_qp);
1092 err_buf:
1093         free_kernel_wrid(hr_qp);
1094         return ret;
1095 }
1096
1097 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1098                          struct ib_udata *udata)
1099 {
1100         if (refcount_dec_and_test(&hr_qp->refcount))
1101                 complete(&hr_qp->free);
1102         wait_for_completion(&hr_qp->free);
1103
1104         free_qpc(hr_dev, hr_qp);
1105         free_qpn(hr_dev, hr_qp);
1106         free_qp_buf(hr_dev, hr_qp);
1107         free_kernel_wrid(hr_qp);
1108         free_qp_db(hr_dev, hr_qp, udata);
1109
1110         kfree(hr_qp);
1111 }
1112
1113 static int check_qp_type(struct hns_roce_dev *hr_dev, enum ib_qp_type type,
1114                          bool is_user)
1115 {
1116         switch (type) {
1117         case IB_QPT_XRC_INI:
1118         case IB_QPT_XRC_TGT:
1119                 if (!(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC))
1120                         goto out;
1121                 break;
1122         case IB_QPT_UD:
1123                 if (hr_dev->pci_dev->revision <= PCI_REVISION_ID_HIP08 &&
1124                     is_user)
1125                         goto out;
1126                 break;
1127         case IB_QPT_RC:
1128         case IB_QPT_GSI:
1129                 break;
1130         default:
1131                 goto out;
1132         }
1133
1134         return 0;
1135
1136 out:
1137         ibdev_err(&hr_dev->ib_dev, "not support QP type %d\n", type);
1138
1139         return -EOPNOTSUPP;
1140 }
1141
1142 struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
1143                                  struct ib_qp_init_attr *init_attr,
1144                                  struct ib_udata *udata)
1145 {
1146         struct ib_device *ibdev = pd ? pd->device : init_attr->xrcd->device;
1147         struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
1148         struct hns_roce_qp *hr_qp;
1149         int ret;
1150
1151         ret = check_qp_type(hr_dev, init_attr->qp_type, !!udata);
1152         if (ret)
1153                 return ERR_PTR(ret);
1154
1155         hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
1156         if (!hr_qp)
1157                 return ERR_PTR(-ENOMEM);
1158
1159         if (init_attr->qp_type == IB_QPT_XRC_INI)
1160                 init_attr->recv_cq = NULL;
1161
1162         if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1163                 hr_qp->xrcdn = to_hr_xrcd(init_attr->xrcd)->xrcdn;
1164                 init_attr->recv_cq = NULL;
1165                 init_attr->send_cq = NULL;
1166         }
1167
1168         if (init_attr->qp_type == IB_QPT_GSI) {
1169                 hr_qp->port = init_attr->port_num - 1;
1170                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
1171         }
1172
1173         ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, hr_qp);
1174         if (ret) {
1175                 ibdev_err(ibdev, "Create QP type 0x%x failed(%d)\n",
1176                           init_attr->qp_type, ret);
1177
1178                 kfree(hr_qp);
1179                 return ERR_PTR(ret);
1180         }
1181
1182         return &hr_qp->ibqp;
1183 }
1184
1185 int to_hr_qp_type(int qp_type)
1186 {
1187         switch (qp_type) {
1188         case IB_QPT_RC:
1189                 return SERV_TYPE_RC;
1190         case IB_QPT_UD:
1191         case IB_QPT_GSI:
1192                 return SERV_TYPE_UD;
1193         case IB_QPT_XRC_INI:
1194         case IB_QPT_XRC_TGT:
1195                 return SERV_TYPE_XRC;
1196         default:
1197                 return -1;
1198         }
1199 }
1200
1201 static int check_mtu_validate(struct hns_roce_dev *hr_dev,
1202                               struct hns_roce_qp *hr_qp,
1203                               struct ib_qp_attr *attr, int attr_mask)
1204 {
1205         enum ib_mtu active_mtu;
1206         int p;
1207
1208         p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
1209         active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu);
1210
1211         if ((hr_dev->caps.max_mtu >= IB_MTU_2048 &&
1212             attr->path_mtu > hr_dev->caps.max_mtu) ||
1213             attr->path_mtu < IB_MTU_256 || attr->path_mtu > active_mtu) {
1214                 ibdev_err(&hr_dev->ib_dev,
1215                         "attr path_mtu(%d)invalid while modify qp",
1216                         attr->path_mtu);
1217                 return -EINVAL;
1218         }
1219
1220         return 0;
1221 }
1222
1223 static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1224                                   int attr_mask)
1225 {
1226         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
1227         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1228         int p;
1229
1230         if ((attr_mask & IB_QP_PORT) &&
1231             (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) {
1232                 ibdev_err(&hr_dev->ib_dev, "invalid attr, port_num = %u.\n",
1233                           attr->port_num);
1234                 return -EINVAL;
1235         }
1236
1237         if (attr_mask & IB_QP_PKEY_INDEX) {
1238                 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
1239                 if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) {
1240                         ibdev_err(&hr_dev->ib_dev,
1241                                   "invalid attr, pkey_index = %u.\n",
1242                                   attr->pkey_index);
1243                         return -EINVAL;
1244                 }
1245         }
1246
1247         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1248             attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) {
1249                 ibdev_err(&hr_dev->ib_dev,
1250                           "invalid attr, max_rd_atomic = %u.\n",
1251                           attr->max_rd_atomic);
1252                 return -EINVAL;
1253         }
1254
1255         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1256             attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) {
1257                 ibdev_err(&hr_dev->ib_dev,
1258                           "invalid attr, max_dest_rd_atomic = %u.\n",
1259                           attr->max_dest_rd_atomic);
1260                 return -EINVAL;
1261         }
1262
1263         if (attr_mask & IB_QP_PATH_MTU)
1264                 return check_mtu_validate(hr_dev, hr_qp, attr, attr_mask);
1265
1266         return 0;
1267 }
1268
1269 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1270                        int attr_mask, struct ib_udata *udata)
1271 {
1272         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
1273         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1274         enum ib_qp_state cur_state, new_state;
1275         int ret = -EINVAL;
1276
1277         mutex_lock(&hr_qp->mutex);
1278
1279         if (attr_mask & IB_QP_CUR_STATE && attr->cur_qp_state != hr_qp->state)
1280                 goto out;
1281
1282         cur_state = hr_qp->state;
1283         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1284
1285         if (ibqp->uobject &&
1286             (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) {
1287                 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) {
1288                         hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
1289
1290                         if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
1291                                 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
1292                 } else {
1293                         ibdev_warn(&hr_dev->ib_dev,
1294                                   "flush cqe is not supported in userspace!\n");
1295                         goto out;
1296                 }
1297         }
1298
1299         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1300                                 attr_mask)) {
1301                 ibdev_err(&hr_dev->ib_dev, "ib_modify_qp_is_ok failed\n");
1302                 goto out;
1303         }
1304
1305         ret = hns_roce_check_qp_attr(ibqp, attr, attr_mask);
1306         if (ret)
1307                 goto out;
1308
1309         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1310                 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
1311                         ret = -EPERM;
1312                         ibdev_err(&hr_dev->ib_dev,
1313                                   "RST2RST state is not supported\n");
1314                 } else {
1315                         ret = 0;
1316                 }
1317
1318                 goto out;
1319         }
1320
1321         ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state,
1322                                     new_state);
1323
1324 out:
1325         mutex_unlock(&hr_qp->mutex);
1326
1327         return ret;
1328 }
1329
1330 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq)
1331                        __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1332 {
1333         if (unlikely(send_cq == NULL && recv_cq == NULL)) {
1334                 __acquire(&send_cq->lock);
1335                 __acquire(&recv_cq->lock);
1336         } else if (unlikely(send_cq != NULL && recv_cq == NULL)) {
1337                 spin_lock_irq(&send_cq->lock);
1338                 __acquire(&recv_cq->lock);
1339         } else if (unlikely(send_cq == NULL && recv_cq != NULL)) {
1340                 spin_lock_irq(&recv_cq->lock);
1341                 __acquire(&send_cq->lock);
1342         } else if (send_cq == recv_cq) {
1343                 spin_lock_irq(&send_cq->lock);
1344                 __acquire(&recv_cq->lock);
1345         } else if (send_cq->cqn < recv_cq->cqn) {
1346                 spin_lock_irq(&send_cq->lock);
1347                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1348         } else {
1349                 spin_lock_irq(&recv_cq->lock);
1350                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1351         }
1352 }
1353
1354 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1355                          struct hns_roce_cq *recv_cq) __releases(&send_cq->lock)
1356                          __releases(&recv_cq->lock)
1357 {
1358         if (unlikely(send_cq == NULL && recv_cq == NULL)) {
1359                 __release(&recv_cq->lock);
1360                 __release(&send_cq->lock);
1361         } else if (unlikely(send_cq != NULL && recv_cq == NULL)) {
1362                 __release(&recv_cq->lock);
1363                 spin_unlock(&send_cq->lock);
1364         } else if (unlikely(send_cq == NULL && recv_cq != NULL)) {
1365                 __release(&send_cq->lock);
1366                 spin_unlock(&recv_cq->lock);
1367         } else if (send_cq == recv_cq) {
1368                 __release(&recv_cq->lock);
1369                 spin_unlock_irq(&send_cq->lock);
1370         } else if (send_cq->cqn < recv_cq->cqn) {
1371                 spin_unlock(&recv_cq->lock);
1372                 spin_unlock_irq(&send_cq->lock);
1373         } else {
1374                 spin_unlock(&send_cq->lock);
1375                 spin_unlock_irq(&recv_cq->lock);
1376         }
1377 }
1378
1379 static inline void *get_wqe(struct hns_roce_qp *hr_qp, int offset)
1380 {
1381         return hns_roce_buf_offset(hr_qp->mtr.kmem, offset);
1382 }
1383
1384 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n)
1385 {
1386         return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
1387 }
1388
1389 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n)
1390 {
1391         return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
1392 }
1393
1394 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n)
1395 {
1396         return get_wqe(hr_qp, hr_qp->sge.offset + (n << hr_qp->sge.sge_shift));
1397 }
1398
1399 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1400                           struct ib_cq *ib_cq)
1401 {
1402         struct hns_roce_cq *hr_cq;
1403         u32 cur;
1404
1405         cur = hr_wq->head - hr_wq->tail;
1406         if (likely(cur + nreq < hr_wq->wqe_cnt))
1407                 return false;
1408
1409         hr_cq = to_hr_cq(ib_cq);
1410         spin_lock(&hr_cq->lock);
1411         cur = hr_wq->head - hr_wq->tail;
1412         spin_unlock(&hr_cq->lock);
1413
1414         return cur + nreq >= hr_wq->wqe_cnt;
1415 }
1416
1417 void hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
1418 {
1419         struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
1420         unsigned int reserved_from_bot;
1421         unsigned int i;
1422
1423         mutex_init(&qp_table->scc_mutex);
1424         mutex_init(&qp_table->bank_mutex);
1425         xa_init(&hr_dev->qp_table_xa);
1426
1427         reserved_from_bot = hr_dev->caps.reserved_qps;
1428
1429         for (i = 0; i < reserved_from_bot; i++) {
1430                 hr_dev->qp_table.bank[get_qp_bankid(i)].inuse++;
1431                 hr_dev->qp_table.bank[get_qp_bankid(i)].min++;
1432         }
1433
1434         for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++) {
1435                 ida_init(&hr_dev->qp_table.bank[i].ida);
1436                 hr_dev->qp_table.bank[i].max = hr_dev->caps.num_qps /
1437                                                HNS_ROCE_QP_BANK_NUM - 1;
1438                 hr_dev->qp_table.bank[i].next = hr_dev->qp_table.bank[i].min;
1439         }
1440 }
1441
1442 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev)
1443 {
1444         int i;
1445
1446         for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++)
1447                 ida_destroy(&hr_dev->qp_table.bank[i].ida);
1448 }