drivers/infiniband/hw/hns/hns_roce_main.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 #include <linux/acpi.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <rdma/ib_addr.h>
  37 #include <rdma/ib_smi.h>
  38 #include <rdma/ib_user_verbs.h>
  39 #include <rdma/ib_cache.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include "hns_roce_hem.h"
  43
  44 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
  45                             const u8 *addr)
  46 {
  47         u8 phy_port;
  48         u32 i;
  49
  50         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
  51                 return 0;
  52
  53         if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
  54                 return 0;
  55
  56         for (i = 0; i < ETH_ALEN; i++)
  57                 hr_dev->dev_addr[port][i] = addr[i];
  58
  59         phy_port = hr_dev->iboe.phy_port[port];
  60         return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  61 }
  62
  63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
  64 {
  65         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  66         u32 port = attr->port_num - 1;
  67         int ret;
  68
  69         if (port >= hr_dev->caps.num_ports)
  70                 return -EINVAL;
  71
  72         ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
  73
  74         return ret;
  75 }
  76
  77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
  78 {
  79         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  80         u32 port = attr->port_num - 1;
  81         int ret;
  82
  83         if (port >= hr_dev->caps.num_ports)
  84                 return -EINVAL;
  85
  86         ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
  87
  88         return ret;
  89 }
  90
  91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
  92                            unsigned long event)
  93 {
  94         struct device *dev = hr_dev->dev;
  95         struct net_device *netdev;
  96         int ret = 0;
  97
  98         netdev = hr_dev->iboe.netdevs[port];
  99         if (!netdev) {
 100                 dev_err(dev, "can't find netdev on port(%u)!\n", port);
 101                 return -ENODEV;
 102         }
 103
 104         switch (event) {
 105         case NETDEV_UP:
 106         case NETDEV_CHANGE:
 107         case NETDEV_REGISTER:
 108         case NETDEV_CHANGEADDR:
 109                 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
 110                 break;
 111         case NETDEV_DOWN:
 112                 /*
 113                  * In v1 engine, only support all ports closed together.
 114                  */
 115                 break;
 116         default:
 117                 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
 118                 break;
 119         }
 120
 121         return ret;
 122 }
 123
 124 static int hns_roce_netdev_event(struct notifier_block *self,
 125                                  unsigned long event, void *ptr)
 126 {
 127         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
 128         struct hns_roce_ib_iboe *iboe = NULL;
 129         struct hns_roce_dev *hr_dev = NULL;
 130         int ret;
 131         u32 port;
 132
 133         hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
 134         iboe = &hr_dev->iboe;
 135
 136         for (port = 0; port < hr_dev->caps.num_ports; port++) {
 137                 if (dev == iboe->netdevs[port]) {
 138                         ret = handle_en_event(hr_dev, port, event);
 139                         if (ret)
 140                                 return NOTIFY_DONE;
 141                         break;
 142                 }
 143         }
 144
 145         return NOTIFY_DONE;
 146 }
 147
 148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
 149 {
 150         int ret;
 151         u8 i;
 152
 153         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 154                 ret = hns_roce_set_mac(hr_dev, i,
 155                                        hr_dev->iboe.netdevs[i]->dev_addr);
 156                 if (ret)
 157                         return ret;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int hns_roce_query_device(struct ib_device *ib_dev,
 164                                  struct ib_device_attr *props,
 165                                  struct ib_udata *uhw)
 166 {
 167         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 168
 169         memset(props, 0, sizeof(*props));
 170
 171         props->fw_ver = hr_dev->caps.fw_ver;
 172         props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
 173         props->max_mr_size = (u64)(~(0ULL));
 174         props->page_size_cap = hr_dev->caps.page_size_cap;
 175         props->vendor_id = hr_dev->vendor_id;
 176         props->vendor_part_id = hr_dev->vendor_part_id;
 177         props->hw_ver = hr_dev->hw_rev;
 178         props->max_qp = hr_dev->caps.num_qps;
 179         props->max_qp_wr = hr_dev->caps.max_wqes;
 180         props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
 181                                   IB_DEVICE_RC_RNR_NAK_GEN;
 182         props->max_send_sge = hr_dev->caps.max_sq_sg;
 183         props->max_recv_sge = hr_dev->caps.max_rq_sg;
 184         props->max_sge_rd = 1;
 185         props->max_cq = hr_dev->caps.num_cqs;
 186         props->max_cqe = hr_dev->caps.max_cqes;
 187         props->max_mr = hr_dev->caps.num_mtpts;
 188         props->max_pd = hr_dev->caps.num_pds;
 189         props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
 190         props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
 191         props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
 192                             IB_ATOMIC_HCA : IB_ATOMIC_NONE;
 193         props->max_pkeys = 1;
 194         props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
 195         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 196                 props->max_srq = hr_dev->caps.num_srqs;
 197                 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
 198                 props->max_srq_sge = hr_dev->caps.max_srq_sges;
 199         }
 200
 201         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
 202             hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
 203                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 204                 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
 205         }
 206
 207         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 208                 props->device_cap_flags |= IB_DEVICE_XRC;
 209
 210         return 0;
 211 }
 212
 213 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
 214                                struct ib_port_attr *props)
 215 {
 216         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 217         struct device *dev = hr_dev->dev;
 218         struct net_device *net_dev;
 219         unsigned long flags;
 220         enum ib_mtu mtu;
 221         u32 port;
 222         int ret;
 223
 224         port = port_num - 1;
 225
 226         /* props being zeroed by the caller, avoid zeroing it here */
 227
 228         props->max_mtu = hr_dev->caps.max_mtu;
 229         props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
 230         props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
 231                                 IB_PORT_VENDOR_CLASS_SUP |
 232                                 IB_PORT_BOOT_MGMT_SUP;
 233         props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
 234         props->pkey_tbl_len = 1;
 235         ret = ib_get_eth_speed(ib_dev, port_num, &props->active_speed,
 236                                &props->active_width);
 237         if (ret)
 238                 ibdev_warn(ib_dev, "failed to get speed, ret = %d.\n", ret);
 239
 240         spin_lock_irqsave(&hr_dev->iboe.lock, flags);
 241
 242         net_dev = hr_dev->iboe.netdevs[port];
 243         if (!net_dev) {
 244                 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 245                 dev_err(dev, "find netdev %u failed!\n", port);
 246                 return -EINVAL;
 247         }
 248
 249         mtu = iboe_get_mtu(net_dev->mtu);
 250         props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
 251         props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
 252                                IB_PORT_ACTIVE :
 253                                IB_PORT_DOWN;
 254         props->phys_state = props->state == IB_PORT_ACTIVE ?
 255                                     IB_PORT_PHYS_STATE_LINK_UP :
 256                                     IB_PORT_PHYS_STATE_DISABLED;
 257
 258         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 259
 260         return 0;
 261 }
 262
 263 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
 264                                                     u32 port_num)
 265 {
 266         return IB_LINK_LAYER_ETHERNET;
 267 }
 268
 269 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
 270                                u16 *pkey)
 271 {
 272         if (index > 0)
 273                 return -EINVAL;
 274
 275         *pkey = PKEY_ID;
 276
 277         return 0;
 278 }
 279
 280 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
 281                                   struct ib_device_modify *props)
 282 {
 283         unsigned long flags;
 284
 285         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 286                 return -EOPNOTSUPP;
 287
 288         if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
 289                 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
 290                 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
 291                 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
 292         }
 293
 294         return 0;
 295 }
 296
 297 struct hns_user_mmap_entry *
 298 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
 299                                 size_t length,
 300                                 enum hns_roce_mmap_type mmap_type)
 301 {
 302         struct hns_user_mmap_entry *entry;
 303         int ret;
 304
 305         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
 306         if (!entry)
 307                 return NULL;
 308
 309         entry->address = address;
 310         entry->mmap_type = mmap_type;
 311
 312         switch (mmap_type) {
 313         /* pgoff 0 must be used by DB for compatibility */
 314         case HNS_ROCE_MMAP_TYPE_DB:
 315                 ret = rdma_user_mmap_entry_insert_exact(
 316                                 ucontext, &entry->rdma_entry, length, 0);
 317                 break;
 318         case HNS_ROCE_MMAP_TYPE_DWQE:
 319                 ret = rdma_user_mmap_entry_insert_range(
 320                                 ucontext, &entry->rdma_entry, length, 1,
 321                                 U32_MAX);
 322                 break;
 323         default:
 324                 ret = -EINVAL;
 325                 break;
 326         }
 327
 328         if (ret) {
 329                 kfree(entry);
 330                 return NULL;
 331         }
 332
 333         return entry;
 334 }
 335
 336 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
 337 {
 338         if (context->db_mmap_entry)
 339                 rdma_user_mmap_entry_remove(
 340                         &context->db_mmap_entry->rdma_entry);
 341 }
 342
 343 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
 344 {
 345         struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
 346         u64 address;
 347
 348         address = context->uar.pfn << PAGE_SHIFT;
 349         context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
 350                 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
 351         if (!context->db_mmap_entry)
 352                 return -ENOMEM;
 353
 354         return 0;
 355 }
 356
 357 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
 358                                    struct ib_udata *udata)
 359 {
 360         struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
 361         struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
 362         struct hns_roce_ib_alloc_ucontext_resp resp = {};
 363         struct hns_roce_ib_alloc_ucontext ucmd = {};
 364         int ret = -EAGAIN;
 365
 366         if (!hr_dev->active)
 367                 goto error_out;
 368
 369         resp.qp_tab_size = hr_dev->caps.num_qps;
 370         resp.srq_tab_size = hr_dev->caps.num_srqs;
 371
 372         ret = ib_copy_from_udata(&ucmd, udata,
 373                                  min(udata->inlen, sizeof(ucmd)));
 374         if (ret)
 375                 goto error_out;
 376
 377         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 378                 context->config = ucmd.config & HNS_ROCE_EXSGE_FLAGS;
 379
 380         if (context->config & HNS_ROCE_EXSGE_FLAGS) {
 381                 resp.config |= HNS_ROCE_RSP_EXSGE_FLAGS;
 382                 resp.max_inline_data = hr_dev->caps.max_sq_inline;
 383         }
 384
 385         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
 386                 context->config |= ucmd.config & HNS_ROCE_RQ_INLINE_FLAGS;
 387                 if (context->config & HNS_ROCE_RQ_INLINE_FLAGS)
 388                         resp.config |= HNS_ROCE_RSP_RQ_INLINE_FLAGS;
 389         }
 390
 391         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQE_INLINE) {
 392                 context->config |= ucmd.config & HNS_ROCE_CQE_INLINE_FLAGS;
 393                 if (context->config & HNS_ROCE_CQE_INLINE_FLAGS)
 394                         resp.config |= HNS_ROCE_RSP_CQE_INLINE_FLAGS;
 395         }
 396
 397         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 398                 resp.congest_type = hr_dev->caps.cong_cap;
 399
 400         ret = hns_roce_uar_alloc(hr_dev, &context->uar);
 401         if (ret)
 402                 goto error_out;
 403
 404         ret = hns_roce_alloc_uar_entry(uctx);
 405         if (ret)
 406                 goto error_fail_uar_entry;
 407
 408         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
 409             hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
 410                 INIT_LIST_HEAD(&context->page_list);
 411                 mutex_init(&context->page_mutex);
 412         }
 413
 414         resp.cqe_size = hr_dev->caps.cqe_sz;
 415
 416         ret = ib_copy_to_udata(udata, &resp,
 417                                min(udata->outlen, sizeof(resp)));
 418         if (ret)
 419                 goto error_fail_copy_to_udata;
 420
 421         return 0;
 422
 423 error_fail_copy_to_udata:
 424         hns_roce_dealloc_uar_entry(context);
 425
 426 error_fail_uar_entry:
 427         ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
 428
 429 error_out:
 430         atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT]);
 431
 432         return ret;
 433 }
 434
 435 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
 436 {
 437         struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
 438         struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
 439
 440         hns_roce_dealloc_uar_entry(context);
 441
 442         ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
 443 }
 444
 445 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
 446 {
 447         struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
 448         struct rdma_user_mmap_entry *rdma_entry;
 449         struct hns_user_mmap_entry *entry;
 450         phys_addr_t pfn;
 451         pgprot_t prot;
 452         int ret;
 453
 454         rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
 455         if (!rdma_entry) {
 456                 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);
 457                 return -EINVAL;
 458         }
 459
 460         entry = to_hns_mmap(rdma_entry);
 461         pfn = entry->address >> PAGE_SHIFT;
 462
 463         switch (entry->mmap_type) {
 464         case HNS_ROCE_MMAP_TYPE_DB:
 465         case HNS_ROCE_MMAP_TYPE_DWQE:
 466                 prot = pgprot_device(vma->vm_page_prot);
 467                 break;
 468         default:
 469                 ret = -EINVAL;
 470                 goto out;
 471         }
 472
 473         ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
 474                                 prot, rdma_entry);
 475
 476 out:
 477         rdma_user_mmap_entry_put(rdma_entry);
 478         if (ret)
 479                 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);
 480
 481         return ret;
 482 }
 483
 484 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
 485 {
 486         struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
 487
 488         kfree(entry);
 489 }
 490
 491 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
 492                                    struct ib_port_immutable *immutable)
 493 {
 494         struct ib_port_attr attr;
 495         int ret;
 496
 497         ret = ib_query_port(ib_dev, port_num, &attr);
 498         if (ret)
 499                 return ret;
 500
 501         immutable->pkey_tbl_len = attr.pkey_tbl_len;
 502         immutable->gid_tbl_len = attr.gid_tbl_len;
 503
 504         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 505         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
 506         if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
 507                 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
 508
 509         return 0;
 510 }
 511
 512 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
 513 {
 514 }
 515
 516 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
 517 {
 518         u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
 519         unsigned int major, minor, sub_minor;
 520
 521         major = upper_32_bits(fw_ver);
 522         minor = high_16_bits(lower_32_bits(fw_ver));
 523         sub_minor = low_16_bits(fw_ver);
 524
 525         snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
 526                  sub_minor);
 527 }
 528
 529 #define HNS_ROCE_HW_CNT(ename, cname) \
 530         [HNS_ROCE_HW_##ename##_CNT].name = cname
 531
 532 static const struct rdma_stat_desc hns_roce_port_stats_descs[] = {
 533         HNS_ROCE_HW_CNT(RX_RC_PKT, "rx_rc_pkt"),
 534         HNS_ROCE_HW_CNT(RX_UC_PKT, "rx_uc_pkt"),
 535         HNS_ROCE_HW_CNT(RX_UD_PKT, "rx_ud_pkt"),
 536         HNS_ROCE_HW_CNT(RX_XRC_PKT, "rx_xrc_pkt"),
 537         HNS_ROCE_HW_CNT(RX_PKT, "rx_pkt"),
 538         HNS_ROCE_HW_CNT(RX_ERR_PKT, "rx_err_pkt"),
 539         HNS_ROCE_HW_CNT(RX_CNP_PKT, "rx_cnp_pkt"),
 540         HNS_ROCE_HW_CNT(TX_RC_PKT, "tx_rc_pkt"),
 541         HNS_ROCE_HW_CNT(TX_UC_PKT, "tx_uc_pkt"),
 542         HNS_ROCE_HW_CNT(TX_UD_PKT, "tx_ud_pkt"),
 543         HNS_ROCE_HW_CNT(TX_XRC_PKT, "tx_xrc_pkt"),
 544         HNS_ROCE_HW_CNT(TX_PKT, "tx_pkt"),
 545         HNS_ROCE_HW_CNT(TX_ERR_PKT, "tx_err_pkt"),
 546         HNS_ROCE_HW_CNT(TX_CNP_PKT, "tx_cnp_pkt"),
 547         HNS_ROCE_HW_CNT(TRP_GET_MPT_ERR_PKT, "trp_get_mpt_err_pkt"),
 548         HNS_ROCE_HW_CNT(TRP_GET_IRRL_ERR_PKT, "trp_get_irrl_err_pkt"),
 549         HNS_ROCE_HW_CNT(ECN_DB, "ecn_doorbell"),
 550         HNS_ROCE_HW_CNT(RX_BUF, "rx_buffer"),
 551         HNS_ROCE_HW_CNT(TRP_RX_SOF, "trp_rx_sof"),
 552         HNS_ROCE_HW_CNT(CQ_CQE, "cq_cqe"),
 553         HNS_ROCE_HW_CNT(CQ_POE, "cq_poe"),
 554         HNS_ROCE_HW_CNT(CQ_NOTIFY, "cq_notify"),
 555 };
 556
 557 static struct rdma_hw_stats *hns_roce_alloc_hw_port_stats(
 558                                 struct ib_device *device, u32 port_num)
 559 {
 560         struct hns_roce_dev *hr_dev = to_hr_dev(device);
 561
 562         if (port_num > hr_dev->caps.num_ports) {
 563                 ibdev_err(device, "invalid port num.\n");
 564                 return NULL;
 565         }
 566
 567         return rdma_alloc_hw_stats_struct(hns_roce_port_stats_descs,
 568                                           ARRAY_SIZE(hns_roce_port_stats_descs),
 569                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
 570 }
 571
 572 static int hns_roce_get_hw_stats(struct ib_device *device,
 573                                  struct rdma_hw_stats *stats,
 574                                  u32 port, int index)
 575 {
 576         struct hns_roce_dev *hr_dev = to_hr_dev(device);
 577         int num_counters = HNS_ROCE_HW_CNT_TOTAL;
 578         int ret;
 579
 580         if (port == 0)
 581                 return 0;
 582
 583         if (port > hr_dev->caps.num_ports)
 584                 return -EINVAL;
 585
 586         ret = hr_dev->hw->query_hw_counter(hr_dev, stats->value, port,
 587                                            &num_counters);
 588         if (ret) {
 589                 ibdev_err(device, "failed to query hw counter, ret = %d\n",
 590                           ret);
 591                 return ret;
 592         }
 593
 594         return num_counters;
 595 }
 596
 597 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
 598 {
 599         struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
 600
 601         hr_dev->active = false;
 602         unregister_netdevice_notifier(&iboe->nb);
 603         ib_unregister_device(&hr_dev->ib_dev);
 604 }
 605
 606 static const struct ib_device_ops hns_roce_dev_ops = {
 607         .owner = THIS_MODULE,
 608         .driver_id = RDMA_DRIVER_HNS,
 609         .uverbs_abi_ver = 1,
 610         .uverbs_no_driver_id_binding = 1,
 611
 612         .get_dev_fw_str = hns_roce_get_fw_ver,
 613         .add_gid = hns_roce_add_gid,
 614         .alloc_pd = hns_roce_alloc_pd,
 615         .alloc_ucontext = hns_roce_alloc_ucontext,
 616         .create_ah = hns_roce_create_ah,
 617         .create_user_ah = hns_roce_create_ah,
 618         .create_cq = hns_roce_create_cq,
 619         .create_qp = hns_roce_create_qp,
 620         .dealloc_pd = hns_roce_dealloc_pd,
 621         .dealloc_ucontext = hns_roce_dealloc_ucontext,
 622         .del_gid = hns_roce_del_gid,
 623         .dereg_mr = hns_roce_dereg_mr,
 624         .destroy_ah = hns_roce_destroy_ah,
 625         .destroy_cq = hns_roce_destroy_cq,
 626         .disassociate_ucontext = hns_roce_disassociate_ucontext,
 627         .get_dma_mr = hns_roce_get_dma_mr,
 628         .get_link_layer = hns_roce_get_link_layer,
 629         .get_port_immutable = hns_roce_port_immutable,
 630         .mmap = hns_roce_mmap,
 631         .mmap_free = hns_roce_free_mmap,
 632         .modify_device = hns_roce_modify_device,
 633         .modify_qp = hns_roce_modify_qp,
 634         .query_ah = hns_roce_query_ah,
 635         .query_device = hns_roce_query_device,
 636         .query_pkey = hns_roce_query_pkey,
 637         .query_port = hns_roce_query_port,
 638         .reg_user_mr = hns_roce_reg_user_mr,
 639
 640         INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
 641         INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
 642         INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
 643         INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
 644         INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
 645 };
 646
 647 static const struct ib_device_ops hns_roce_dev_hw_stats_ops = {
 648         .alloc_hw_port_stats = hns_roce_alloc_hw_port_stats,
 649         .get_hw_stats = hns_roce_get_hw_stats,
 650 };
 651
 652 static const struct ib_device_ops hns_roce_dev_mr_ops = {
 653         .rereg_user_mr = hns_roce_rereg_user_mr,
 654 };
 655
 656 static const struct ib_device_ops hns_roce_dev_mw_ops = {
 657         .alloc_mw = hns_roce_alloc_mw,
 658         .dealloc_mw = hns_roce_dealloc_mw,
 659
 660         INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
 661 };
 662
 663 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
 664         .alloc_mr = hns_roce_alloc_mr,
 665         .map_mr_sg = hns_roce_map_mr_sg,
 666 };
 667
 668 static const struct ib_device_ops hns_roce_dev_srq_ops = {
 669         .create_srq = hns_roce_create_srq,
 670         .destroy_srq = hns_roce_destroy_srq,
 671
 672         INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
 673 };
 674
 675 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
 676         .alloc_xrcd = hns_roce_alloc_xrcd,
 677         .dealloc_xrcd = hns_roce_dealloc_xrcd,
 678
 679         INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
 680 };
 681
 682 static const struct ib_device_ops hns_roce_dev_restrack_ops = {
 683         .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
 684         .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw,
 685         .fill_res_qp_entry = hns_roce_fill_res_qp_entry,
 686         .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw,
 687         .fill_res_mr_entry = hns_roce_fill_res_mr_entry,
 688         .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw,
 689         .fill_res_srq_entry = hns_roce_fill_res_srq_entry,
 690         .fill_res_srq_entry_raw = hns_roce_fill_res_srq_entry_raw,
 691 };
 692
 693 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
 694 {
 695         int ret;
 696         struct hns_roce_ib_iboe *iboe = NULL;
 697         struct ib_device *ib_dev = NULL;
 698         struct device *dev = hr_dev->dev;
 699         unsigned int i;
 700
 701         iboe = &hr_dev->iboe;
 702         spin_lock_init(&iboe->lock);
 703
 704         ib_dev = &hr_dev->ib_dev;
 705
 706         ib_dev->node_type = RDMA_NODE_IB_CA;
 707         ib_dev->dev.parent = dev;
 708
 709         ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
 710         ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
 711         ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
 712
 713         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
 714                 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
 715
 716         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
 717                 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
 718
 719         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
 720                 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
 721
 722         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 723                 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
 724                 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
 725         }
 726
 727         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 728                 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
 729
 730         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09 &&
 731             !hr_dev->is_vf)
 732                 ib_set_device_ops(ib_dev, &hns_roce_dev_hw_stats_ops);
 733
 734         ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
 735         ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
 736         ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops);
 737         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 738                 if (!hr_dev->iboe.netdevs[i])
 739                         continue;
 740
 741                 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
 742                                            i + 1);
 743                 if (ret)
 744                         return ret;
 745         }
 746         dma_set_max_seg_size(dev, UINT_MAX);
 747         ret = ib_register_device(ib_dev, "hns_%d", dev);
 748         if (ret) {
 749                 dev_err(dev, "ib_register_device failed!\n");
 750                 return ret;
 751         }
 752
 753         ret = hns_roce_setup_mtu_mac(hr_dev);
 754         if (ret) {
 755                 dev_err(dev, "setup_mtu_mac failed!\n");
 756                 goto error_failed_setup_mtu_mac;
 757         }
 758
 759         iboe->nb.notifier_call = hns_roce_netdev_event;
 760         ret = register_netdevice_notifier(&iboe->nb);
 761         if (ret) {
 762                 dev_err(dev, "register_netdevice_notifier failed!\n");
 763                 goto error_failed_setup_mtu_mac;
 764         }
 765
 766         hr_dev->active = true;
 767         return 0;
 768
 769 error_failed_setup_mtu_mac:
 770         ib_unregister_device(ib_dev);
 771
 772         return ret;
 773 }
 774
 775 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
 776 {
 777         struct device *dev = hr_dev->dev;
 778         int ret;
 779
 780         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
 781                                       HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
 782                                       hr_dev->caps.num_mtpts);
 783         if (ret) {
 784                 dev_err(dev, "failed to init MTPT context memory, aborting.\n");
 785                 return ret;
 786         }
 787
 788         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
 789                                       HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
 790                                       hr_dev->caps.num_qps);
 791         if (ret) {
 792                 dev_err(dev, "failed to init QP context memory, aborting.\n");
 793                 goto err_unmap_dmpt;
 794         }
 795
 796         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
 797                                       HEM_TYPE_IRRL,
 798                                       hr_dev->caps.irrl_entry_sz *
 799                                       hr_dev->caps.max_qp_init_rdma,
 800                                       hr_dev->caps.num_qps);
 801         if (ret) {
 802                 dev_err(dev, "failed to init irrl_table memory, aborting.\n");
 803                 goto err_unmap_qp;
 804         }
 805
 806         if (hr_dev->caps.trrl_entry_sz) {
 807                 ret = hns_roce_init_hem_table(hr_dev,
 808                                               &hr_dev->qp_table.trrl_table,
 809                                               HEM_TYPE_TRRL,
 810                                               hr_dev->caps.trrl_entry_sz *
 811                                               hr_dev->caps.max_qp_dest_rdma,
 812                                               hr_dev->caps.num_qps);
 813                 if (ret) {
 814                         dev_err(dev,
 815                                 "failed to init trrl_table memory, aborting.\n");
 816                         goto err_unmap_irrl;
 817                 }
 818         }
 819
 820         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
 821                                       HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
 822                                       hr_dev->caps.num_cqs);
 823         if (ret) {
 824                 dev_err(dev, "failed to init CQ context memory, aborting.\n");
 825                 goto err_unmap_trrl;
 826         }
 827
 828         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 829                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
 830                                               HEM_TYPE_SRQC,
 831                                               hr_dev->caps.srqc_entry_sz,
 832                                               hr_dev->caps.num_srqs);
 833                 if (ret) {
 834                         dev_err(dev,
 835                                 "failed to init SRQ context memory, aborting.\n");
 836                         goto err_unmap_cq;
 837                 }
 838         }
 839
 840         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
 841                 ret = hns_roce_init_hem_table(hr_dev,
 842                                               &hr_dev->qp_table.sccc_table,
 843                                               HEM_TYPE_SCCC,
 844                                               hr_dev->caps.sccc_sz,
 845                                               hr_dev->caps.num_qps);
 846                 if (ret) {
 847                         dev_err(dev,
 848                                 "failed to init SCC context memory, aborting.\n");
 849                         goto err_unmap_srq;
 850                 }
 851         }
 852
 853         if (hr_dev->caps.qpc_timer_entry_sz) {
 854                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
 855                                               HEM_TYPE_QPC_TIMER,
 856                                               hr_dev->caps.qpc_timer_entry_sz,
 857                                               hr_dev->caps.qpc_timer_bt_num);
 858                 if (ret) {
 859                         dev_err(dev,
 860                                 "failed to init QPC timer memory, aborting.\n");
 861                         goto err_unmap_ctx;
 862                 }
 863         }
 864
 865         if (hr_dev->caps.cqc_timer_entry_sz) {
 866                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
 867                                               HEM_TYPE_CQC_TIMER,
 868                                               hr_dev->caps.cqc_timer_entry_sz,
 869                                               hr_dev->caps.cqc_timer_bt_num);
 870                 if (ret) {
 871                         dev_err(dev,
 872                                 "failed to init CQC timer memory, aborting.\n");
 873                         goto err_unmap_qpc_timer;
 874                 }
 875         }
 876
 877         if (hr_dev->caps.gmv_entry_sz) {
 878                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
 879                                               HEM_TYPE_GMV,
 880                                               hr_dev->caps.gmv_entry_sz,
 881                                               hr_dev->caps.gmv_entry_num);
 882                 if (ret) {
 883                         dev_err(dev,
 884                                 "failed to init gmv table memory, ret = %d\n",
 885                                 ret);
 886                         goto err_unmap_cqc_timer;
 887                 }
 888         }
 889
 890         return 0;
 891
 892 err_unmap_cqc_timer:
 893         if (hr_dev->caps.cqc_timer_entry_sz)
 894                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
 895
 896 err_unmap_qpc_timer:
 897         if (hr_dev->caps.qpc_timer_entry_sz)
 898                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
 899
 900 err_unmap_ctx:
 901         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
 902                 hns_roce_cleanup_hem_table(hr_dev,
 903                                            &hr_dev->qp_table.sccc_table);
 904 err_unmap_srq:
 905         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
 906                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
 907
 908 err_unmap_cq:
 909         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
 910
 911 err_unmap_trrl:
 912         if (hr_dev->caps.trrl_entry_sz)
 913                 hns_roce_cleanup_hem_table(hr_dev,
 914                                            &hr_dev->qp_table.trrl_table);
 915
 916 err_unmap_irrl:
 917         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
 918
 919 err_unmap_qp:
 920         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
 921
 922 err_unmap_dmpt:
 923         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
 924
 925         return ret;
 926 }
 927
 928 /**
 929  * hns_roce_setup_hca - setup host channel adapter
 930  * @hr_dev: pointer to hns roce device
 931  * Return : int
 932  */
 933 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
 934 {
 935         struct device *dev = hr_dev->dev;
 936         int ret;
 937
 938         spin_lock_init(&hr_dev->sm_lock);
 939
 940         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
 941             hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
 942                 INIT_LIST_HEAD(&hr_dev->pgdir_list);
 943                 mutex_init(&hr_dev->pgdir_mutex);
 944         }
 945
 946         hns_roce_init_uar_table(hr_dev);
 947
 948         ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
 949         if (ret) {
 950                 dev_err(dev, "failed to allocate priv_uar.\n");
 951                 goto err_uar_table_free;
 952         }
 953
 954         ret = hns_roce_init_qp_table(hr_dev);
 955         if (ret) {
 956                 dev_err(dev, "failed to init qp_table.\n");
 957                 goto err_uar_table_free;
 958         }
 959
 960         hns_roce_init_pd_table(hr_dev);
 961
 962         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 963                 hns_roce_init_xrcd_table(hr_dev);
 964
 965         hns_roce_init_mr_table(hr_dev);
 966
 967         hns_roce_init_cq_table(hr_dev);
 968
 969         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
 970                 hns_roce_init_srq_table(hr_dev);
 971
 972         return 0;
 973
 974 err_uar_table_free:
 975         ida_destroy(&hr_dev->uar_ida.ida);
 976         return ret;
 977 }
 978
 979 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
 980 {
 981         struct hns_roce_cq *hr_cq = to_hr_cq(cq);
 982         unsigned long flags;
 983
 984         spin_lock_irqsave(&hr_cq->lock, flags);
 985         if (cq->comp_handler) {
 986                 if (!hr_cq->is_armed) {
 987                         hr_cq->is_armed = 1;
 988                         list_add_tail(&hr_cq->node, cq_list);
 989                 }
 990         }
 991         spin_unlock_irqrestore(&hr_cq->lock, flags);
 992 }
 993
 994 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
 995 {
 996         struct hns_roce_qp *hr_qp;
 997         struct hns_roce_cq *hr_cq;
 998         struct list_head cq_list;
 999         unsigned long flags_qp;
1000         unsigned long flags;
1001
1002         INIT_LIST_HEAD(&cq_list);
1003
1004         spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
1005         list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
1006                 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
1007                 if (hr_qp->sq.tail != hr_qp->sq.head)
1008                         check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
1009                 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
1010
1011                 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
1012                 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
1013                         check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
1014                 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
1015         }
1016
1017         list_for_each_entry(hr_cq, &cq_list, node)
1018                 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
1019
1020         spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
1021 }
1022
1023 static int hns_roce_alloc_dfx_cnt(struct hns_roce_dev *hr_dev)
1024 {
1025         hr_dev->dfx_cnt = kvcalloc(HNS_ROCE_DFX_CNT_TOTAL, sizeof(atomic64_t),
1026                                    GFP_KERNEL);
1027         if (!hr_dev->dfx_cnt)
1028                 return -ENOMEM;
1029
1030         return 0;
1031 }
1032
1033 static void hns_roce_dealloc_dfx_cnt(struct hns_roce_dev *hr_dev)
1034 {
1035         kvfree(hr_dev->dfx_cnt);
1036 }
1037
1038 int hns_roce_init(struct hns_roce_dev *hr_dev)
1039 {
1040         struct device *dev = hr_dev->dev;
1041         int ret;
1042
1043         hr_dev->is_reset = false;
1044
1045         ret = hns_roce_alloc_dfx_cnt(hr_dev);
1046         if (ret)
1047                 return ret;
1048
1049         if (hr_dev->hw->cmq_init) {
1050                 ret = hr_dev->hw->cmq_init(hr_dev);
1051                 if (ret) {
1052                         dev_err(dev, "init RoCE Command Queue failed!\n");
1053                         goto error_failed_alloc_dfx_cnt;
1054                 }
1055         }
1056
1057         ret = hr_dev->hw->hw_profile(hr_dev);
1058         if (ret) {
1059                 dev_err(dev, "get RoCE engine profile failed!\n");
1060                 goto error_failed_cmd_init;
1061         }
1062
1063         ret = hns_roce_cmd_init(hr_dev);
1064         if (ret) {
1065                 dev_err(dev, "cmd init failed!\n");
1066                 goto error_failed_cmd_init;
1067         }
1068
1069         /* EQ depends on poll mode, event mode depends on EQ */
1070         ret = hr_dev->hw->init_eq(hr_dev);
1071         if (ret) {
1072                 dev_err(dev, "eq init failed!\n");
1073                 goto error_failed_eq_table;
1074         }
1075
1076         if (hr_dev->cmd_mod) {
1077                 ret = hns_roce_cmd_use_events(hr_dev);
1078                 if (ret)
1079                         dev_warn(dev,
1080                                  "Cmd event  mode failed, set back to poll!\n");
1081         }
1082
1083         ret = hns_roce_init_hem(hr_dev);
1084         if (ret) {
1085                 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
1086                 goto error_failed_init_hem;
1087         }
1088
1089         ret = hns_roce_setup_hca(hr_dev);
1090         if (ret) {
1091                 dev_err(dev, "setup hca failed!\n");
1092                 goto error_failed_setup_hca;
1093         }
1094
1095         if (hr_dev->hw->hw_init) {
1096                 ret = hr_dev->hw->hw_init(hr_dev);
1097                 if (ret) {
1098                         dev_err(dev, "hw_init failed!\n");
1099                         goto error_failed_engine_init;
1100                 }
1101         }
1102
1103         INIT_LIST_HEAD(&hr_dev->qp_list);
1104         spin_lock_init(&hr_dev->qp_list_lock);
1105         INIT_LIST_HEAD(&hr_dev->dip_list);
1106         spin_lock_init(&hr_dev->dip_list_lock);
1107
1108         ret = hns_roce_register_device(hr_dev);
1109         if (ret)
1110                 goto error_failed_register_device;
1111
1112         hns_roce_register_debugfs(hr_dev);
1113
1114         return 0;
1115
1116 error_failed_register_device:
1117         if (hr_dev->hw->hw_exit)
1118                 hr_dev->hw->hw_exit(hr_dev);
1119
1120 error_failed_engine_init:
1121         hns_roce_cleanup_bitmap(hr_dev);
1122
1123 error_failed_setup_hca:
1124         hns_roce_cleanup_hem(hr_dev);
1125
1126 error_failed_init_hem:
1127         if (hr_dev->cmd_mod)
1128                 hns_roce_cmd_use_polling(hr_dev);
1129         hr_dev->hw->cleanup_eq(hr_dev);
1130
1131 error_failed_eq_table:
1132         hns_roce_cmd_cleanup(hr_dev);
1133
1134 error_failed_cmd_init:
1135         if (hr_dev->hw->cmq_exit)
1136                 hr_dev->hw->cmq_exit(hr_dev);
1137
1138 error_failed_alloc_dfx_cnt:
1139         hns_roce_dealloc_dfx_cnt(hr_dev);
1140
1141         return ret;
1142 }
1143
1144 void hns_roce_exit(struct hns_roce_dev *hr_dev)
1145 {
1146         hns_roce_unregister_debugfs(hr_dev);
1147         hns_roce_unregister_device(hr_dev);
1148
1149         if (hr_dev->hw->hw_exit)
1150                 hr_dev->hw->hw_exit(hr_dev);
1151         hns_roce_cleanup_bitmap(hr_dev);
1152         hns_roce_cleanup_hem(hr_dev);
1153
1154         if (hr_dev->cmd_mod)
1155                 hns_roce_cmd_use_polling(hr_dev);
1156
1157         hr_dev->hw->cleanup_eq(hr_dev);
1158         hns_roce_cmd_cleanup(hr_dev);
1159         if (hr_dev->hw->cmq_exit)
1160                 hr_dev->hw->cmq_exit(hr_dev);
1161         hns_roce_dealloc_dfx_cnt(hr_dev);
1162 }
1163
1164 MODULE_LICENSE("Dual BSD/GPL");
1165 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1166 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1167 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1168 MODULE_DESCRIPTION("HNS RoCE Driver");