2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_HW_V2_H
34 #define _HNS_ROCE_HW_V2_H
36 #include <linux/bitops.h>
38 #define HNS_ROCE_VF_QPC_BT_NUM 256
39 #define HNS_ROCE_VF_SCCC_BT_NUM 64
40 #define HNS_ROCE_VF_SRQC_BT_NUM 64
41 #define HNS_ROCE_VF_CQC_BT_NUM 64
42 #define HNS_ROCE_VF_MPT_BT_NUM 64
43 #define HNS_ROCE_VF_SMAC_NUM 32
44 #define HNS_ROCE_VF_SL_NUM 8
45 #define HNS_ROCE_VF_GMV_BT_NUM 256
47 #define HNS_ROCE_V2_MAX_QP_NUM 0x1000
48 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
49 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
50 #define HNS_ROCE_V2_MAX_SRQ 0x100000
51 #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
52 #define HNS_ROCE_V2_MAX_SRQ_SGE 64
53 #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
54 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100
55 #define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
56 #define HNS_ROCE_V2_MAX_CQE_NUM 0x400000
57 #define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000
58 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 64
59 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64
60 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
61 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
62 #define HNS_ROCE_V2_MAX_SQ_INL_EXT 0x400
63 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32
64 #define HNS_ROCE_V2_UAR_NUM 256
65 #define HNS_ROCE_V2_PHY_UAR_NUM 1
66 #define HNS_ROCE_V2_MAX_IRQ_NUM 65
67 #define HNS_ROCE_V2_COMP_VEC_NUM 63
68 #define HNS_ROCE_V2_AEQE_VEC_NUM 1
69 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
70 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000
71 #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
72 #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
73 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
74 #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
75 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
76 #define HNS_ROCE_V2_MAX_XRCD_NUM 0x1000000
77 #define HNS_ROCE_V2_RSV_XRCD_NUM 0
78 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
79 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
80 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
81 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
82 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
83 #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
84 #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
85 #define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ 100
86 #define HNS_ROCE_V2_CQC_ENTRY_SZ 64
87 #define HNS_ROCE_V2_SRQC_ENTRY_SZ 64
88 #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
89 #define HNS_ROCE_V2_MTT_ENTRY_SZ 64
90 #define HNS_ROCE_V2_IDX_ENTRY_SZ 4
92 #define HNS_ROCE_V2_SCCC_SZ 32
93 #define HNS_ROCE_V3_SCCC_SZ 64
94 #define HNS_ROCE_V3_GMV_ENTRY_SZ 32
96 #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE
97 #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE
98 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
99 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
100 #define HNS_ROCE_INVALID_LKEY 0x0
101 #define HNS_ROCE_INVALID_SGE_LENGTH 0x80000000
102 #define HNS_ROCE_CMQ_TX_TIMEOUT 30000
103 #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
104 #define HNS_ROCE_V2_RSV_QPS 8
106 #define HNS_ROCE_V2_HW_RST_TIMEOUT 1000
107 #define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100
109 #define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20
111 #define HNS_ROCE_CONTEXT_HOP_NUM 1
112 #define HNS_ROCE_SCCC_HOP_NUM 1
113 #define HNS_ROCE_MTT_HOP_NUM 1
114 #define HNS_ROCE_CQE_HOP_NUM 1
115 #define HNS_ROCE_SRQWQE_HOP_NUM 1
116 #define HNS_ROCE_PBL_HOP_NUM 2
117 #define HNS_ROCE_EQE_HOP_NUM 2
118 #define HNS_ROCE_IDX_HOP_NUM 1
119 #define HNS_ROCE_SQWQE_HOP_NUM 2
120 #define HNS_ROCE_EXT_SGE_HOP_NUM 1
121 #define HNS_ROCE_RQWQE_HOP_NUM 2
123 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K 6
124 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K 2
125 #define HNS_ROCE_V2_GID_INDEX_NUM 16
127 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
129 #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
130 #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1
131 #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2
132 #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3
133 #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
134 #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5
136 #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
137 #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
138 #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
139 #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
140 #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
141 #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
143 #define HNS_ROCE_CMQ_DESC_NUM_S 3
145 #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5
147 #define HNS_ROCE_CONG_SIZE 64
149 #define check_whether_last_step(hop_num, step_idx) \
150 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
151 (step_idx == 1 && hop_num == 1) || \
152 (step_idx == 2 && hop_num == 2))
153 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
154 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
156 #define CMD_CSQ_DESC_NUM 1024
157 #define CMD_CRQ_DESC_NUM 1024
162 REG_NXT_SE_CEQE = 0x3
165 #define V2_CQ_DB_REQ_NOT_SOL 0
166 #define V2_CQ_DB_REQ_NOT 1
168 #define V2_CQ_STATE_VALID 1
169 #define V2_QKEY_VAL 0x80010000
171 #define GID_LEN_V2 16
173 #define HNS_ROCE_V2_CQE_QPN_MASK 0xfffff
176 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
177 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
178 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
179 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
180 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
181 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
182 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
183 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
184 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
185 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
186 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
187 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
188 HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc,
189 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
194 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
195 HNS_ROCE_V2_OPCODE_SEND = 0x1,
196 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
197 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
205 HNS_ROCE_V2_CQ_DB_NOTIFY
209 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
210 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
211 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
212 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
213 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
214 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
215 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
216 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
217 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
218 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
219 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
220 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
221 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
222 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
223 HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23,
225 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
229 enum hns_roce_opcode_type {
230 HNS_QUERY_FW_VER = 0x0001,
231 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
232 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
233 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
234 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
235 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
236 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
237 HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404,
238 HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406,
239 HNS_ROCE_OPC_QUERY_FUNC_INFO = 0x8407,
240 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408,
241 HNS_ROCE_OPC_CFG_ENTRY_SIZE = 0x8409,
242 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
243 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
244 HNS_ROCE_OPC_POST_MB = 0x8504,
245 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
246 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
247 HNS_ROCE_OPC_FUNC_CLEAR = 0x8508,
248 HNS_ROCE_OPC_CLR_SCCC = 0x8509,
249 HNS_ROCE_OPC_QUERY_SCCC = 0x850a,
250 HNS_ROCE_OPC_RESET_SCCC = 0x850b,
251 HNS_ROCE_OPC_QUERY_VF_RES = 0x850e,
252 HNS_ROCE_OPC_CFG_GMV_TBL = 0x850f,
253 HNS_ROCE_OPC_CFG_GMV_BT = 0x8510,
254 HNS_SWITCH_PARAMETER_CFG = 0x1033,
262 enum hns_roce_cmd_return_status {
279 enum hns_roce_sgid_type {
280 GID_TYPE_FLAG_ROCE_V1 = 0,
281 GID_TYPE_FLAG_ROCE_V2_IPV4,
282 GID_TYPE_FLAG_ROCE_V2_IPV6,
285 struct hns_roce_v2_cq_context {
286 __le32 byte_4_pg_ceqn;
288 __le32 cqe_cur_blk_addr;
289 __le32 byte_16_hop_addr;
290 __le32 cqe_nxt_blk_addr;
291 __le32 byte_24_pgsz_addr;
292 __le32 byte_28_cq_pi;
293 __le32 byte_32_cq_ci;
295 __le32 byte_40_cqe_ba;
296 __le32 byte_44_db_record;
297 __le32 db_record_addr;
298 __le32 byte_52_cqe_cnt;
299 __le32 byte_56_cqe_period_maxcnt;
300 __le32 cqe_report_timer;
301 __le32 byte_64_se_cqe_idx;
304 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
305 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
307 #define V2_CQC_BYTE_4_CQ_ST_S 0
308 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
310 #define V2_CQC_BYTE_4_POLL_S 2
312 #define V2_CQC_BYTE_4_SE_S 3
314 #define V2_CQC_BYTE_4_OVER_IGNORE_S 4
316 #define V2_CQC_BYTE_4_COALESCE_S 5
318 #define V2_CQC_BYTE_4_ARM_ST_S 6
319 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
321 #define V2_CQC_BYTE_4_SHIFT_S 8
322 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
324 #define V2_CQC_BYTE_4_CMD_SN_S 13
325 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
327 #define V2_CQC_BYTE_4_CEQN_S 15
328 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
330 #define V2_CQC_BYTE_4_PAGE_OFFSET_S 24
331 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
333 #define V2_CQC_BYTE_8_CQN_S 0
334 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
336 #define V2_CQC_BYTE_8_CQE_SIZE_S 27
337 #define V2_CQC_BYTE_8_CQE_SIZE_M GENMASK(28, 27)
339 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
340 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
342 #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
343 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
345 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
346 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
348 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24
349 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
351 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28
352 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
354 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
355 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
357 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
358 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
360 #define V2_CQC_BYTE_40_CQE_BA_S 0
361 #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
363 #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0
365 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1
366 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
368 #define V2_CQC_BYTE_52_CQE_CNT_S 0
369 #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
371 #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
372 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
374 #define V2_CQC_BYTE_56_CQ_PERIOD_S 16
375 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
377 #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
378 #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
380 #define CQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cq_context, h, l)
382 #define CQC_STASH CQC_FIELD_LOC(63, 63)
384 struct hns_roce_srq_context {
385 __le32 byte_4_srqn_srqst;
386 __le32 byte_8_limit_wl;
388 __le32 byte_16_pi_ci;
390 __le32 byte_24_wqe_bt_ba;
391 __le32 byte_28_rqws_pd;
393 __le32 rsv_idx_bt_ba;
394 __le32 idx_cur_blk_addr;
395 __le32 byte_44_idxbufpgsz_addr;
396 __le32 idx_nxt_blk_addr;
397 __le32 rsv_idxnxtblkaddr;
398 __le32 byte_56_xrc_cqn;
399 __le32 db_record_addr_record_en;
400 __le32 db_record_addr;
403 #define SRQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_srq_context, h, l)
405 #define SRQC_SRQ_ST SRQC_FIELD_LOC(1, 0)
406 #define SRQC_WQE_HOP_NUM SRQC_FIELD_LOC(3, 2)
407 #define SRQC_SHIFT SRQC_FIELD_LOC(7, 4)
408 #define SRQC_SRQN SRQC_FIELD_LOC(31, 8)
409 #define SRQC_LIMIT_WL SRQC_FIELD_LOC(47, 32)
410 #define SRQC_RSV0 SRQC_FIELD_LOC(63, 48)
411 #define SRQC_XRCD SRQC_FIELD_LOC(87, 64)
412 #define SRQC_RSV1 SRQC_FIELD_LOC(95, 88)
413 #define SRQC_PRODUCER_IDX SRQC_FIELD_LOC(111, 96)
414 #define SRQC_CONSUMER_IDX SRQC_FIELD_LOC(127, 112)
415 #define SRQC_WQE_BT_BA_L SRQC_FIELD_LOC(159, 128)
416 #define SRQC_WQE_BT_BA_H SRQC_FIELD_LOC(188, 160)
417 #define SRQC_RSV2 SRQC_FIELD_LOC(190, 189)
418 #define SRQC_SRQ_TYPE SRQC_FIELD_LOC(191, 191)
419 #define SRQC_PD SRQC_FIELD_LOC(215, 192)
420 #define SRQC_RQWS SRQC_FIELD_LOC(219, 216)
421 #define SRQC_RSV3 SRQC_FIELD_LOC(223, 220)
422 #define SRQC_IDX_BT_BA_L SRQC_FIELD_LOC(255, 224)
423 #define SRQC_IDX_BT_BA_H SRQC_FIELD_LOC(284, 256)
424 #define SRQC_RSV4 SRQC_FIELD_LOC(287, 285)
425 #define SRQC_IDX_CUR_BLK_ADDR_L SRQC_FIELD_LOC(319, 288)
426 #define SRQC_IDX_CUR_BLK_ADDR_H SRQC_FIELD_LOC(339, 320)
427 #define SRQC_RSV5 SRQC_FIELD_LOC(341, 340)
428 #define SRQC_IDX_HOP_NUM SRQC_FIELD_LOC(343, 342)
429 #define SRQC_IDX_BA_PG_SZ SRQC_FIELD_LOC(347, 344)
430 #define SRQC_IDX_BUF_PG_SZ SRQC_FIELD_LOC(351, 348)
431 #define SRQC_IDX_NXT_BLK_ADDR_L SRQC_FIELD_LOC(383, 352)
432 #define SRQC_IDX_NXT_BLK_ADDR_H SRQC_FIELD_LOC(403, 384)
433 #define SRQC_RSV6 SRQC_FIELD_LOC(415, 404)
434 #define SRQC_XRC_CQN SRQC_FIELD_LOC(439, 416)
435 #define SRQC_WQE_BA_PG_SZ SRQC_FIELD_LOC(443, 440)
436 #define SRQC_WQE_BUF_PG_SZ SRQC_FIELD_LOC(447, 444)
437 #define SRQC_DB_RECORD_EN SRQC_FIELD_LOC(448, 448)
438 #define SRQC_DB_RECORD_ADDR_L SRQC_FIELD_LOC(479, 449)
439 #define SRQC_DB_RECORD_ADDR_H SRQC_FIELD_LOC(511, 480)
441 #define SRQC_BYTE_4_SRQ_ST_S 0
442 #define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0)
444 #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2
445 #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2)
447 #define SRQC_BYTE_4_SRQ_SHIFT_S 4
448 #define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4)
450 #define SRQC_BYTE_4_SRQN_S 8
451 #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
453 #define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0
454 #define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0)
456 #define SRQC_BYTE_12_SRQ_XRCD_S 0
457 #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
459 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0
460 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0)
462 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0
463 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
465 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0
466 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0)
468 #define SRQC_BYTE_28_PD_S 0
469 #define SRQC_BYTE_28_PD_M GENMASK(23, 0)
471 #define SRQC_BYTE_28_RQWS_S 24
472 #define SRQC_BYTE_28_RQWS_M GENMASK(27, 24)
474 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0
475 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0)
477 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0
478 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0)
480 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22
481 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22)
483 #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24
484 #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24)
486 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28
487 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
489 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0
490 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0)
492 #define SRQC_BYTE_56_SRQ_XRC_CQN_S 0
493 #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
495 #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24
496 #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24)
498 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28
499 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
501 #define SRQC_BYTE_60_SRQ_RECORD_EN_S 0
503 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1
504 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
507 V2_MPT_ST_VALID = 0x1,
508 V2_MPT_ST_FREE = 0x2,
511 enum hns_roce_v2_qp_state {
519 HNS_ROCE_QP_ST_SQ_DRAINING,
523 struct hns_roce_v2_qp_context_ex {
526 struct hns_roce_v2_qp_context {
527 __le32 byte_4_sqpn_tst;
529 __le32 byte_12_sq_hop;
530 __le32 byte_16_buf_ba_pg_sz;
531 __le32 byte_20_smac_sgid_idx;
532 __le32 byte_24_mtu_tc;
533 __le32 byte_28_at_fl;
536 __le32 byte_52_udpspn_dmac;
537 __le32 byte_56_dqpn_err;
538 __le32 byte_60_qpst_tempid;
540 __le32 byte_68_rq_db;
541 __le32 rq_db_record_addr;
542 __le32 byte_76_srqn_op_en;
543 __le32 byte_80_rnr_rx_cqn;
544 __le32 byte_84_rq_ci_pi;
545 __le32 rq_cur_blk_addr;
546 __le32 byte_92_srq_info;
547 __le32 byte_96_rx_reqmsn;
548 __le32 rq_nxt_blk_addr;
549 __le32 byte_104_rq_sge;
550 __le32 byte_108_rx_reqepsn;
553 __le32 rx_rkey_pkt_info;
555 __le32 byte_132_trrl;
562 __le32 byte_160_sq_ci_pi;
563 __le32 sq_cur_blk_addr;
564 __le32 byte_168_irrl_idx;
565 __le32 byte_172_sq_psn;
566 __le32 byte_176_msg_pktn;
567 __le32 sq_cur_sge_blk_addr;
568 __le32 byte_184_irrl_idx;
569 __le32 cur_sge_offset;
570 __le32 byte_192_ext_sge;
571 __le32 byte_196_sq_psn;
572 __le32 byte_200_sq_max;
574 __le32 byte_208_irrl;
577 __le32 byte_220_retry_psn_msn;
578 __le32 byte_224_retry_msg;
579 __le32 rx_sq_cur_blk_addr;
580 __le32 byte_232_irrl_sge;
581 __le32 irrl_cur_sge_offset;
582 __le32 byte_240_irrl_tail;
583 __le32 byte_244_rnr_rxack;
584 __le32 byte_248_ack_psn;
585 __le32 byte_252_err_txcqn;
586 __le32 byte_256_sqflush_rqcqe;
588 struct hns_roce_v2_qp_context_ex ext;
591 #define QPC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context, h, l)
593 #define QPC_CONG_ALGO_TMPL_ID QPC_FIELD_LOC(455, 448)
595 #define V2_QPC_BYTE_4_TST_S 0
596 #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
598 #define V2_QPC_BYTE_4_SGE_SHIFT_S 3
599 #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
601 #define V2_QPC_BYTE_4_SQPN_S 8
602 #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
604 #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
605 #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
607 #define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
608 #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
610 #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
612 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
613 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
615 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
616 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
618 #define V2_QPC_BYTE_16_PD_S 8
619 #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
621 #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
622 #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
624 #define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
625 #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
627 #define V2_QPC_BYTE_20_RQWS_S 4
628 #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
630 #define V2_QPC_BYTE_20_SQ_SHIFT_S 8
631 #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
633 #define V2_QPC_BYTE_20_RQ_SHIFT_S 12
634 #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
636 #define V2_QPC_BYTE_20_SGID_IDX_S 16
637 #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
639 #define V2_QPC_BYTE_20_SMAC_IDX_S 24
640 #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
642 #define V2_QPC_BYTE_24_HOP_LIMIT_S 0
643 #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
645 #define V2_QPC_BYTE_24_TC_S 8
646 #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
648 #define V2_QPC_BYTE_24_VLAN_ID_S 16
649 #define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
651 #define V2_QPC_BYTE_24_MTU_S 28
652 #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
654 #define V2_QPC_BYTE_28_FL_S 0
655 #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
657 #define V2_QPC_BYTE_28_SL_S 20
658 #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
660 #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
662 #define V2_QPC_BYTE_28_CE_FLAG_S 25
664 #define V2_QPC_BYTE_28_LBI_S 26
666 #define V2_QPC_BYTE_28_AT_S 27
667 #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
669 #define V2_QPC_BYTE_52_DMAC_S 0
670 #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
672 #define V2_QPC_BYTE_52_UDPSPN_S 16
673 #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
675 #define V2_QPC_BYTE_56_DQPN_S 0
676 #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
678 #define V2_QPC_BYTE_56_SQ_TX_ERR_S 24
679 #define V2_QPC_BYTE_56_SQ_RX_ERR_S 25
680 #define V2_QPC_BYTE_56_RQ_TX_ERR_S 26
681 #define V2_QPC_BYTE_56_RQ_RX_ERR_S 27
683 #define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
684 #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
686 #define V2_QPC_BYTE_60_SCC_TOKEN_S 8
687 #define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
689 #define V2_QPC_BYTE_60_SQ_DB_DOING_S 27
691 #define V2_QPC_BYTE_60_RQ_DB_DOING_S 28
693 #define V2_QPC_BYTE_60_QP_ST_S 29
694 #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
696 #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
698 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
699 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
701 #define V2_QPC_BYTE_76_SRQN_S 0
702 #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
704 #define V2_QPC_BYTE_76_SRQ_EN_S 24
706 #define V2_QPC_BYTE_76_RRE_S 25
708 #define V2_QPC_BYTE_76_RWE_S 26
710 #define V2_QPC_BYTE_76_ATE_S 27
712 #define V2_QPC_BYTE_76_RQIE_S 28
713 #define V2_QPC_BYTE_76_EXT_ATE_S 29
714 #define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
715 #define V2_QPC_BYTE_80_RX_CQN_S 0
716 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
718 #define V2_QPC_BYTE_80_XRC_QP_TYPE_S 24
720 #define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
721 #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
723 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
724 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
726 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
727 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
729 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
730 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
732 #define V2_QPC_BYTE_92_SRQ_INFO_S 20
733 #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
735 #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
736 #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
738 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
739 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
741 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
742 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
744 #define V2_QPC_BYTE_108_INV_CREDIT_S 0
746 #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
748 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
749 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
751 #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
753 #define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
754 #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
756 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
757 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
759 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
760 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
762 #define V2_QPC_BYTE_132_TRRL_BA_S 16
763 #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
765 #define V2_QPC_BYTE_140_TRRL_BA_S 0
766 #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
768 #define V2_QPC_BYTE_140_RR_MAX_S 12
769 #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
771 #define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
773 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
774 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
776 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
777 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
779 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
780 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
782 #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
783 #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
785 #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
787 #define V2_QPC_BYTE_148_RQ_MSN_S 0
788 #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
790 #define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
791 #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
793 #define V2_QPC_BYTE_152_RAQ_PSN_S 0
794 #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
796 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
797 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
799 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
800 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
802 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
803 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
805 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
806 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
808 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
809 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
811 #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
813 #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
815 #define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
816 #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
818 #define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
819 #define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
820 #define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
821 #define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
822 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
823 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
825 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
826 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
828 #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
830 #define V2_QPC_BYTE_172_FRE_S 7
832 #define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
833 #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
835 #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
836 #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
838 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
839 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
841 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
842 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
844 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
845 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
847 #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
848 #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
850 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
851 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
853 #define V2_QPC_BYTE_196_IRRL_HEAD_S 0
854 #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
856 #define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
857 #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
859 #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
860 #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
862 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
863 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
865 #define V2_QPC_BYTE_208_IRRL_BA_S 0
866 #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
868 #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
870 #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
872 #define V2_QPC_BYTE_208_RMT_E2E_S 28
874 #define V2_QPC_BYTE_208_SR_MAX_S 29
875 #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
877 #define V2_QPC_BYTE_212_LSN_S 0
878 #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
880 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
881 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
883 #define V2_QPC_BYTE_212_CHECK_FLG_S 27
884 #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
886 #define V2_QPC_BYTE_212_RETRY_CNT_S 29
887 #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
889 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
890 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
892 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
893 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
895 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
896 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
898 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
899 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
901 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
902 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
904 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
905 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
907 #define V2_QPC_BYTE_232_SO_LP_VLD_S 29
908 #define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
909 #define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
911 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
912 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
914 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
915 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
917 #define V2_QPC_BYTE_240_RX_ACK_MSN_S 16
918 #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
920 #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
921 #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
923 #define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
924 #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
926 #define V2_QPC_BYTE_244_RNR_CNT_S 27
927 #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
929 #define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
930 #define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
932 #define V2_QPC_BYTE_248_IRRL_PSN_S 0
933 #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
935 #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
937 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
938 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
940 #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
942 #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
944 #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
946 #define V2_QPC_BYTE_252_TX_CQN_S 0
947 #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
949 #define V2_QPC_BYTE_252_SIG_TYPE_S 24
951 #define V2_QPC_BYTE_252_ERR_TYPE_S 25
952 #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
954 #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
955 #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
957 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
958 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
960 #define QPCEX_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context_ex, h, l)
962 #define QPCEX_CONG_ALG_SEL QPCEX_FIELD_LOC(0, 0)
963 #define QPCEX_CONG_ALG_SUB_SEL QPCEX_FIELD_LOC(1, 1)
964 #define QPCEX_DIP_CTX_IDX_VLD QPCEX_FIELD_LOC(2, 2)
965 #define QPCEX_DIP_CTX_IDX QPCEX_FIELD_LOC(22, 3)
966 #define QPCEX_STASH QPCEX_FIELD_LOC(82, 82)
968 #define V2_QP_RWE_S 1 /* rdma write enable */
969 #define V2_QP_RRE_S 2 /* rdma read enable */
970 #define V2_QP_ATE_S 3 /* rdma atomic enable */
972 struct hns_roce_v2_cqe {
987 #define V2_CQE_BYTE_4_OPCODE_S 0
988 #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
990 #define V2_CQE_BYTE_4_RQ_INLINE_S 5
992 #define V2_CQE_BYTE_4_S_R_S 6
994 #define V2_CQE_BYTE_4_OWNER_S 7
996 #define V2_CQE_BYTE_4_STATUS_S 8
997 #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
999 #define V2_CQE_BYTE_4_WQE_INDX_S 16
1000 #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
1002 #define V2_CQE_BYTE_12_XRC_SRQN_S 0
1003 #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
1005 #define V2_CQE_BYTE_16_LCL_QPN_S 0
1006 #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
1008 #define V2_CQE_BYTE_16_SUB_STATUS_S 24
1009 #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
1011 #define V2_CQE_BYTE_28_SMAC_4_S 0
1012 #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0)
1014 #define V2_CQE_BYTE_28_SMAC_5_S 8
1015 #define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8)
1017 #define V2_CQE_BYTE_28_PORT_TYPE_S 16
1018 #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
1020 #define V2_CQE_BYTE_28_VID_S 18
1021 #define V2_CQE_BYTE_28_VID_M GENMASK(29, 18)
1023 #define V2_CQE_BYTE_28_VID_VLD_S 30
1025 #define V2_CQE_BYTE_32_RMT_QPN_S 0
1026 #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
1028 #define V2_CQE_BYTE_32_SL_S 24
1029 #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
1031 #define V2_CQE_BYTE_32_PORTN_S 27
1032 #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
1034 #define V2_CQE_BYTE_32_GRH_S 30
1036 #define V2_CQE_BYTE_32_LPK_S 31
1038 struct hns_roce_v2_mpt_entry {
1039 __le32 byte_4_pd_hop_st;
1040 __le32 byte_8_mw_cnt_en;
1041 __le32 byte_12_mw_pa;
1050 __le32 byte_48_mode_ba;
1052 __le32 byte_56_pa0_h;
1054 __le32 byte_64_buf_pa1;
1057 #define MPT_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_mpt_entry, h, l)
1059 #define MPT_ST MPT_FIELD_LOC(1, 0)
1060 #define MPT_PBL_HOP_NUM MPT_FIELD_LOC(3, 2)
1061 #define MPT_PBL_BA_PG_SZ MPT_FIELD_LOC(7, 4)
1062 #define MPT_PD MPT_FIELD_LOC(31, 8)
1063 #define MPT_RA_EN MPT_FIELD_LOC(32, 32)
1064 #define MPT_R_INV_EN MPT_FIELD_LOC(33, 33)
1065 #define MPT_L_INV_EN MPT_FIELD_LOC(34, 34)
1066 #define MPT_BIND_EN MPT_FIELD_LOC(35, 35)
1067 #define MPT_ATOMIC_EN MPT_FIELD_LOC(36, 36)
1068 #define MPT_RR_EN MPT_FIELD_LOC(37, 37)
1069 #define MPT_RW_EN MPT_FIELD_LOC(38, 38)
1070 #define MPT_LW_EN MPT_FIELD_LOC(39, 39)
1071 #define MPT_MW_CNT MPT_FIELD_LOC(63, 40)
1072 #define MPT_FRE MPT_FIELD_LOC(64, 64)
1073 #define MPT_PA MPT_FIELD_LOC(65, 65)
1074 #define MPT_ZBVA MPT_FIELD_LOC(66, 66)
1075 #define MPT_SHARE MPT_FIELD_LOC(67, 67)
1076 #define MPT_MR_MW MPT_FIELD_LOC(68, 68)
1077 #define MPT_BPD MPT_FIELD_LOC(69, 69)
1078 #define MPT_BQP MPT_FIELD_LOC(70, 70)
1079 #define MPT_INNER_PA_VLD MPT_FIELD_LOC(71, 71)
1080 #define MPT_MW_BIND_QPN MPT_FIELD_LOC(95, 72)
1081 #define MPT_BOUND_LKEY MPT_FIELD_LOC(127, 96)
1082 #define MPT_LEN MPT_FIELD_LOC(191, 128)
1083 #define MPT_LKEY MPT_FIELD_LOC(223, 192)
1084 #define MPT_VA MPT_FIELD_LOC(287, 224)
1085 #define MPT_PBL_SIZE MPT_FIELD_LOC(319, 288)
1086 #define MPT_PBL_BA MPT_FIELD_LOC(380, 320)
1087 #define MPT_BLK_MODE MPT_FIELD_LOC(381, 381)
1088 #define MPT_RSV0 MPT_FIELD_LOC(383, 382)
1089 #define MPT_PA0 MPT_FIELD_LOC(441, 384)
1090 #define MPT_BOUND_VA MPT_FIELD_LOC(447, 442)
1091 #define MPT_PA1 MPT_FIELD_LOC(505, 448)
1092 #define MPT_PERSIST_EN MPT_FIELD_LOC(506, 506)
1093 #define MPT_RSV2 MPT_FIELD_LOC(507, 507)
1094 #define MPT_PBL_BUF_PG_SZ MPT_FIELD_LOC(511, 508)
1096 #define V2_MPT_BYTE_4_MPT_ST_S 0
1097 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
1099 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
1100 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
1102 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
1103 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
1105 #define V2_MPT_BYTE_4_PD_S 8
1106 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
1108 #define V2_MPT_BYTE_8_RA_EN_S 0
1110 #define V2_MPT_BYTE_8_R_INV_EN_S 1
1112 #define V2_MPT_BYTE_8_L_INV_EN_S 2
1114 #define V2_MPT_BYTE_8_BIND_EN_S 3
1116 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4
1118 #define V2_MPT_BYTE_8_RR_EN_S 5
1120 #define V2_MPT_BYTE_8_RW_EN_S 6
1122 #define V2_MPT_BYTE_8_LW_EN_S 7
1124 #define V2_MPT_BYTE_8_MW_CNT_S 8
1125 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
1127 #define V2_MPT_BYTE_12_FRE_S 0
1129 #define V2_MPT_BYTE_12_PA_S 1
1131 #define V2_MPT_BYTE_12_MR_MW_S 4
1133 #define V2_MPT_BYTE_12_BPD_S 5
1135 #define V2_MPT_BYTE_12_BQP_S 6
1137 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
1139 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
1140 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
1142 #define V2_MPT_BYTE_48_PBL_BA_H_S 0
1143 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
1145 #define V2_MPT_BYTE_48_BLK_MODE_S 29
1147 #define V2_MPT_BYTE_56_PA0_H_S 0
1148 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
1150 #define V2_MPT_BYTE_64_PA1_H_S 0
1151 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
1153 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
1154 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
1156 #define V2_DB_TAG_S 0
1157 #define V2_DB_TAG_M GENMASK(23, 0)
1159 #define V2_DB_CMD_S 24
1160 #define V2_DB_CMD_M GENMASK(27, 24)
1162 #define V2_DB_FLAG_S 31
1164 #define V2_DB_PRODUCER_IDX_S 0
1165 #define V2_DB_PRODUCER_IDX_M GENMASK(15, 0)
1167 #define V2_DB_SL_S 16
1168 #define V2_DB_SL_M GENMASK(18, 16)
1170 #define V2_CQ_DB_CONS_IDX_S 0
1171 #define V2_CQ_DB_CONS_IDX_M GENMASK(23, 0)
1173 #define V2_CQ_DB_NOTIFY_TYPE_S 24
1175 #define V2_CQ_DB_CMD_SN_S 25
1176 #define V2_CQ_DB_CMD_SN_M GENMASK(26, 25)
1178 struct hns_roce_v2_ud_send_wqe {
1192 u8 dgid[GID_LEN_V2];
1195 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
1196 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1198 #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
1200 #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8
1202 #define V2_UD_SEND_WQE_BYTE_4_SE_S 11
1204 #define V2_UD_SEND_WQE_BYTE_16_PD_S 0
1205 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
1207 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
1208 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1210 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1211 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1213 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
1214 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
1216 #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
1217 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
1219 #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
1220 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
1222 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
1223 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
1225 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
1226 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
1228 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
1229 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
1231 #define V2_UD_SEND_WQE_BYTE_40_SL_S 20
1232 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
1234 #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
1236 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
1238 struct hns_roce_v2_rc_send_wqe {
1251 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
1252 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1254 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S 5
1255 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M GENMASK(6, 5)
1257 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S 13
1258 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M GENMASK(14, 13)
1260 #define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S 15
1261 #define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M GENMASK(30, 15)
1263 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
1265 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
1267 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
1269 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10
1271 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11
1273 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
1275 #define V2_RC_FRMR_WQE_BYTE_40_BIND_EN_S 10
1277 #define V2_RC_FRMR_WQE_BYTE_40_ATOMIC_S 11
1279 #define V2_RC_FRMR_WQE_BYTE_40_RR_S 12
1281 #define V2_RC_FRMR_WQE_BYTE_40_RW_S 13
1283 #define V2_RC_FRMR_WQE_BYTE_40_LW_S 14
1285 #define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31
1287 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1288 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1290 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
1291 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1293 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1294 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1296 #define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31
1298 struct hns_roce_wqe_frmr_seg {
1303 #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4
1304 #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4)
1306 #define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8
1308 struct hns_roce_v2_wqe_data_seg {
1314 struct hns_roce_v2_db {
1319 struct hns_roce_query_version {
1320 __le16 rocee_vendor_id;
1321 __le16 rocee_hw_version;
1325 struct hns_roce_query_fw_info {
1330 struct hns_roce_func_clear {
1331 __le32 rst_funcid_en;
1336 #define FUNC_CLEAR_RST_FUN_DONE_S 0
1337 /* Each physical function manages up to 248 virtual functions, it takes up to
1338 * 100ms for each function to execute clear. If an abnormal reset occurs, it is
1339 * executed twice at most, so it takes up to 249 * 2 * 100ms.
1341 #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100)
1342 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40
1343 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20
1345 struct hns_roce_cfg_llm_a {
1348 __le32 depth_pgsz_init_en;
1350 __le32 head_ba_h_nxtptr;
1354 #define CFG_LLM_QUE_DEPTH_S 0
1355 #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
1357 #define CFG_LLM_QUE_PGSZ_S 16
1358 #define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16)
1360 #define CFG_LLM_INIT_EN_S 20
1361 #define CFG_LLM_INIT_EN_M GENMASK(20, 20)
1363 #define CFG_LLM_HEAD_PTR_S 0
1364 #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
1366 struct hns_roce_cfg_llm_b {
1373 #define CFG_LLM_TAIL_BA_H_S 0
1374 #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
1376 #define CFG_LLM_TAIL_PTR_S 0
1377 #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
1379 /* Fields of HNS_ROCE_OPC_CFG_GLOBAL_PARAM */
1380 #define CFG_GLOBAL_PARAM_1US_CYCLES CMQ_REQ_FIELD_LOC(9, 0)
1381 #define CFG_GLOBAL_PARAM_UDP_PORT CMQ_REQ_FIELD_LOC(31, 16)
1384 * Fields of HNS_ROCE_OPC_QUERY_PF_RES, HNS_ROCE_OPC_QUERY_VF_RES
1385 * and HNS_ROCE_OPC_ALLOC_VF_RES
1387 #define FUNC_RES_A_VF_ID CMQ_REQ_FIELD_LOC(7, 0)
1388 #define FUNC_RES_A_QPC_BT_IDX CMQ_REQ_FIELD_LOC(42, 32)
1389 #define FUNC_RES_A_QPC_BT_NUM CMQ_REQ_FIELD_LOC(59, 48)
1390 #define FUNC_RES_A_SRQC_BT_IDX CMQ_REQ_FIELD_LOC(72, 64)
1391 #define FUNC_RES_A_SRQC_BT_NUM CMQ_REQ_FIELD_LOC(89, 80)
1392 #define FUNC_RES_A_CQC_BT_IDX CMQ_REQ_FIELD_LOC(104, 96)
1393 #define FUNC_RES_A_CQC_BT_NUM CMQ_REQ_FIELD_LOC(121, 112)
1394 #define FUNC_RES_A_MPT_BT_IDX CMQ_REQ_FIELD_LOC(136, 128)
1395 #define FUNC_RES_A_MPT_BT_NUM CMQ_REQ_FIELD_LOC(153, 144)
1396 #define FUNC_RES_A_EQC_BT_IDX CMQ_REQ_FIELD_LOC(168, 160)
1397 #define FUNC_RES_A_EQC_BT_NUM CMQ_REQ_FIELD_LOC(185, 176)
1398 #define FUNC_RES_B_SMAC_IDX CMQ_REQ_FIELD_LOC(39, 32)
1399 #define FUNC_RES_B_SMAC_NUM CMQ_REQ_FIELD_LOC(48, 40)
1400 #define FUNC_RES_B_SGID_IDX CMQ_REQ_FIELD_LOC(71, 64)
1401 #define FUNC_RES_B_SGID_NUM CMQ_REQ_FIELD_LOC(80, 72)
1402 #define FUNC_RES_B_QID_IDX CMQ_REQ_FIELD_LOC(105, 96)
1403 #define FUNC_RES_B_QID_NUM CMQ_REQ_FIELD_LOC(122, 112)
1404 #define FUNC_RES_V_QID_NUM CMQ_REQ_FIELD_LOC(115, 112)
1406 #define FUNC_RES_B_SCCC_BT_IDX CMQ_REQ_FIELD_LOC(136, 128)
1407 #define FUNC_RES_B_SCCC_BT_NUM CMQ_REQ_FIELD_LOC(145, 137)
1408 #define FUNC_RES_B_GMV_BT_IDX CMQ_REQ_FIELD_LOC(167, 160)
1409 #define FUNC_RES_B_GMV_BT_NUM CMQ_REQ_FIELD_LOC(176, 168)
1410 #define FUNC_RES_V_GMV_BT_NUM CMQ_REQ_FIELD_LOC(184, 176)
1412 /* Fields of HNS_ROCE_OPC_QUERY_PF_TIMER_RES */
1413 #define PF_TIMER_RES_QPC_ITEM_IDX CMQ_REQ_FIELD_LOC(43, 32)
1414 #define PF_TIMER_RES_QPC_ITEM_NUM CMQ_REQ_FIELD_LOC(60, 48)
1415 #define PF_TIMER_RES_CQC_ITEM_IDX CMQ_REQ_FIELD_LOC(74, 64)
1416 #define PF_TIMER_RES_CQC_ITEM_NUM CMQ_REQ_FIELD_LOC(91, 80)
1418 struct hns_roce_vf_switch {
1427 #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
1428 #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
1430 #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
1431 #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
1432 #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
1434 struct hns_roce_post_mbox {
1440 __le32 token_event_en;
1443 struct hns_roce_mbox_status {
1444 __le32 mb_status_hw_run;
1448 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1450 #define MB_ST_HW_RUN_M BIT(31)
1451 #define MB_ST_COMPLETE_M GENMASK(7, 0)
1453 #define MB_ST_COMPLETE_SUCC 1
1455 /* Fields of HNS_ROCE_OPC_CFG_BT_ATTR */
1456 #define CFG_BT_ATTR_QPC_BA_PGSZ CMQ_REQ_FIELD_LOC(3, 0)
1457 #define CFG_BT_ATTR_QPC_BUF_PGSZ CMQ_REQ_FIELD_LOC(7, 4)
1458 #define CFG_BT_ATTR_QPC_HOPNUM CMQ_REQ_FIELD_LOC(9, 8)
1459 #define CFG_BT_ATTR_SRQC_BA_PGSZ CMQ_REQ_FIELD_LOC(35, 32)
1460 #define CFG_BT_ATTR_SRQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(39, 36)
1461 #define CFG_BT_ATTR_SRQC_HOPNUM CMQ_REQ_FIELD_LOC(41, 40)
1462 #define CFG_BT_ATTR_CQC_BA_PGSZ CMQ_REQ_FIELD_LOC(67, 64)
1463 #define CFG_BT_ATTR_CQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(71, 68)
1464 #define CFG_BT_ATTR_CQC_HOPNUM CMQ_REQ_FIELD_LOC(73, 72)
1465 #define CFG_BT_ATTR_MPT_BA_PGSZ CMQ_REQ_FIELD_LOC(99, 96)
1466 #define CFG_BT_ATTR_MPT_BUF_PGSZ CMQ_REQ_FIELD_LOC(103, 100)
1467 #define CFG_BT_ATTR_MPT_HOPNUM CMQ_REQ_FIELD_LOC(105, 104)
1468 #define CFG_BT_ATTR_SCCC_BA_PGSZ CMQ_REQ_FIELD_LOC(131, 128)
1469 #define CFG_BT_ATTR_SCCC_BUF_PGSZ CMQ_REQ_FIELD_LOC(135, 132)
1470 #define CFG_BT_ATTR_SCCC_HOPNUM CMQ_REQ_FIELD_LOC(137, 136)
1472 /* Fields of HNS_ROCE_OPC_CFG_ENTRY_SIZE */
1473 #define CFG_HEM_ENTRY_SIZE_TYPE CMQ_REQ_FIELD_LOC(31, 0)
1475 HNS_ROCE_CFG_QPC_SIZE = BIT(0),
1476 HNS_ROCE_CFG_SCCC_SIZE = BIT(1),
1479 #define CFG_HEM_ENTRY_SIZE_VALUE CMQ_REQ_FIELD_LOC(191, 160)
1481 /* Fields of HNS_ROCE_OPC_CFG_GMV_BT */
1482 #define CFG_GMV_BT_BA_L CMQ_REQ_FIELD_LOC(31, 0)
1483 #define CFG_GMV_BT_BA_H CMQ_REQ_FIELD_LOC(51, 32)
1484 #define CFG_GMV_BT_IDX CMQ_REQ_FIELD_LOC(95, 64)
1486 struct hns_roce_cfg_sgid_tb {
1487 __le32 table_idx_rsv;
1492 __le32 vf_sgid_type_rsv;
1495 #define CFG_SGID_TB_TABLE_IDX_S 0
1496 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1498 #define CFG_SGID_TB_VF_SGID_TYPE_S 0
1499 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1501 struct hns_roce_cfg_smac_tb {
1504 __le32 vf_smac_h_rsv;
1507 #define CFG_SMAC_TB_IDX_S 0
1508 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1510 #define CFG_SMAC_TB_VF_SMAC_H_S 0
1511 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1513 struct hns_roce_cfg_gmv_tb_a {
1518 __le32 vf_sgid_type_vlan;
1522 #define CFG_GMV_TB_SGID_IDX_S 0
1523 #define CFG_GMV_TB_SGID_IDX_M GENMASK(7, 0)
1525 #define CFG_GMV_TB_VF_SGID_TYPE_S 0
1526 #define CFG_GMV_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1528 #define CFG_GMV_TB_VF_VLAN_EN_S 2
1530 #define CFG_GMV_TB_VF_VLAN_ID_S 16
1531 #define CFG_GMV_TB_VF_VLAN_ID_M GENMASK(27, 16)
1533 struct hns_roce_cfg_gmv_tb_b {
1536 __le32 table_idx_rsv;
1540 #define CFG_GMV_TB_SMAC_H_S 0
1541 #define CFG_GMV_TB_SMAC_H_M GENMASK(15, 0)
1543 #define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5
1544 struct hns_roce_query_pf_caps_a {
1546 u8 local_ca_ack_delay;
1548 __le16 max_sq_inline;
1550 __le32 max_extend_sg;
1551 __le16 num_qpc_timer;
1552 __le16 num_cqc_timer;
1553 __le16 max_srq_sges;
1555 u8 num_other_vectors;
1562 struct hns_roce_query_pf_caps_b {
1572 __le16 qpc_timer_entry_sz;
1573 __le16 cqc_timer_entry_sz;
1576 __le32 page_size_cap;
1583 struct hns_roce_query_pf_caps_c {
1584 __le32 cap_flags_num_pds;
1585 __le32 max_gid_num_cqs;
1593 #define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0
1594 #define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0)
1596 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20
1597 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20)
1599 #define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0
1600 #define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0)
1602 #define V2_QUERY_PF_CAPS_C_MAX_GID_S 20
1603 #define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20)
1605 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0
1606 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0)
1608 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0
1609 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0)
1611 #define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0
1612 #define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0)
1614 #define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20
1615 #define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20)
1617 struct hns_roce_query_pf_caps_d {
1618 __le32 wq_hop_num_max_srqs;
1620 __le16 cap_flags_ex;
1621 __le32 num_ceqs_ceq_depth;
1622 __le32 arm_st_aeq_depth;
1623 __le32 num_uars_rsv_pds;
1624 __le32 rsv_uars_rsv_qps;
1626 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0
1627 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0)
1629 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20
1630 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20)
1632 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22
1633 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22)
1635 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24
1636 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24)
1638 #define V2_QUERY_PF_CAPS_D_CONG_TYPE_S 26
1639 #define V2_QUERY_PF_CAPS_D_CONG_TYPE_M GENMASK(29, 26)
1641 struct hns_roce_congestion_algorithm {
1647 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0
1648 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0)
1650 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22
1651 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22)
1653 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0
1654 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0)
1656 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22
1657 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22)
1659 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24
1660 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24)
1662 #define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0
1663 #define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0)
1665 #define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20
1666 #define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20)
1668 #define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0
1669 #define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0)
1671 #define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20
1672 #define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20)
1674 struct hns_roce_query_pf_caps_e {
1675 __le32 chunk_size_shift_rsv_mrws;
1685 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0
1686 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0)
1688 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20
1689 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20)
1691 #define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0
1692 #define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0)
1694 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0
1695 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0)
1697 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0
1698 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0)
1700 struct hns_roce_cmq_req {
1704 #define CMQ_REQ_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cmq_req, h, l)
1706 struct hns_roce_cmq_desc {
1714 __le32 own_func_num;
1722 struct hns_roce_v2_cmq_ring {
1723 dma_addr_t desc_dma_addr;
1724 struct hns_roce_cmq_desc *desc;
1729 spinlock_t lock; /* command queue lock */
1732 struct hns_roce_v2_cmq {
1733 struct hns_roce_v2_cmq_ring csq;
1734 struct hns_roce_v2_cmq_ring crq;
1738 enum hns_roce_link_table_type {
1743 struct hns_roce_link_table {
1744 struct hns_roce_buf_list table;
1745 struct hns_roce_buf_list *pg_list;
1750 struct hns_roce_link_table_entry {
1752 u32 blk_ba1_nxt_ptr;
1754 #define HNS_ROCE_LINK_TABLE_BA1_S 0
1755 #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
1757 #define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20
1758 #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1760 struct hns_roce_v2_priv {
1761 struct hnae3_handle *handle;
1762 struct hns_roce_v2_cmq cmq;
1763 struct hns_roce_link_table tsq;
1764 struct hns_roce_link_table tpq;
1767 struct hns_roce_eq_context {
1771 __le32 eqe_report_timer;
1782 struct hns_roce_dip {
1783 u8 dgid[GID_LEN_V2];
1785 struct list_head node; /* all dips are on a list */
1788 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1789 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1790 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1791 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1793 #define HNS_ROCE_V2_EQ_STATE_INVALID 0
1794 #define HNS_ROCE_V2_EQ_STATE_VALID 1
1795 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2
1796 #define HNS_ROCE_V2_EQ_STATE_FAILURE 3
1798 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1799 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1
1801 #define HNS_ROCE_V2_EQ_COALESCE_0 0
1802 #define HNS_ROCE_V2_EQ_COALESCE_1 1
1804 #define HNS_ROCE_V2_EQ_FIRED 0
1805 #define HNS_ROCE_V2_EQ_ARMED 1
1806 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3
1808 #define HNS_ROCE_EQ_INIT_EQE_CNT 0
1809 #define HNS_ROCE_EQ_INIT_PROD_IDX 0
1810 #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1811 #define HNS_ROCE_EQ_INIT_MSI_IDX 0
1812 #define HNS_ROCE_EQ_INIT_CONS_IDX 0
1813 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1815 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1816 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1818 #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1819 #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1821 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1822 #define HNS_ROCE_V2_VF_INT_ST_RAS_INT_S 1
1824 #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1825 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1826 #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1827 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1830 #define EQ_DISABLE 0
1832 #define EQ_REG_OFFSET 0x4
1834 #define HNS_ROCE_INT_NAME_LEN 32
1835 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1837 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1838 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1839 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1840 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1841 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1843 #define EQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_eq_context, h, l)
1845 #define EQC_EQ_ST EQC_FIELD_LOC(1, 0)
1846 #define EQC_EQE_HOP_NUM EQC_FIELD_LOC(3, 2)
1847 #define EQC_OVER_IGNORE EQC_FIELD_LOC(4, 4)
1848 #define EQC_COALESCE EQC_FIELD_LOC(5, 5)
1849 #define EQC_ARM_ST EQC_FIELD_LOC(7, 6)
1850 #define EQC_EQN EQC_FIELD_LOC(15, 8)
1851 #define EQC_EQE_CNT EQC_FIELD_LOC(31, 16)
1852 #define EQC_EQE_BA_PG_SZ EQC_FIELD_LOC(35, 32)
1853 #define EQC_EQE_BUF_PG_SZ EQC_FIELD_LOC(39, 36)
1854 #define EQC_EQ_PROD_INDX EQC_FIELD_LOC(63, 40)
1855 #define EQC_EQ_MAX_CNT EQC_FIELD_LOC(79, 64)
1856 #define EQC_EQ_PERIOD EQC_FIELD_LOC(95, 80)
1857 #define EQC_EQE_REPORT_TIMER EQC_FIELD_LOC(127, 96)
1858 #define EQC_EQE_BA_L EQC_FIELD_LOC(159, 128)
1859 #define EQC_EQE_BA_H EQC_FIELD_LOC(188, 160)
1860 #define EQC_SHIFT EQC_FIELD_LOC(199, 192)
1861 #define EQC_MSI_INDX EQC_FIELD_LOC(207, 200)
1862 #define EQC_CUR_EQE_BA_L EQC_FIELD_LOC(223, 208)
1863 #define EQC_CUR_EQE_BA_M EQC_FIELD_LOC(255, 224)
1864 #define EQC_CUR_EQE_BA_H EQC_FIELD_LOC(259, 256)
1865 #define EQC_EQ_CONS_INDX EQC_FIELD_LOC(287, 264)
1866 #define EQC_NEX_EQE_BA_L EQC_FIELD_LOC(319, 288)
1867 #define EQC_NEX_EQE_BA_H EQC_FIELD_LOC(339, 320)
1868 #define EQC_EQE_SIZE EQC_FIELD_LOC(341, 340)
1870 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1871 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1873 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1874 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1876 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1877 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1879 #define V2_EQ_DB_TAG_S 0
1880 #define V2_EQ_DB_TAG_M GENMASK(7, 0)
1882 #define V2_EQ_DB_CMD_S 16
1883 #define V2_EQ_DB_CMD_M GENMASK(17, 16)
1885 #define V2_EQ_DB_CONS_IDX_S 0
1886 #define V2_EQ_DB_CONS_IDX_M GENMASK(23, 0)
1888 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1889 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1891 #define MAX_SERVICE_LEVEL 0x7
1893 struct hns_roce_wqe_atomic_seg {
1894 __le64 fetchadd_swap_data;
1898 struct hns_roce_sccc_clr {
1903 struct hns_roce_sccc_clr_done {
1908 int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn,
1911 static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
1914 struct hns_roce_v2_priv *priv = hr_dev->priv;
1915 struct hnae3_handle *handle = priv->handle;
1916 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1918 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
1919 hns_roce_write64_k(val, dest);