2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_HW_V2_H
34 #define _HNS_ROCE_HW_V2_H
36 #include <linux/bitops.h>
38 #define HNS_ROCE_VF_QPC_BT_NUM 256
39 #define HNS_ROCE_VF_SCCC_BT_NUM 64
40 #define HNS_ROCE_VF_SRQC_BT_NUM 64
41 #define HNS_ROCE_VF_CQC_BT_NUM 64
42 #define HNS_ROCE_VF_MPT_BT_NUM 64
43 #define HNS_ROCE_VF_EQC_NUM 64
44 #define HNS_ROCE_VF_SMAC_NUM 32
45 #define HNS_ROCE_VF_SGID_NUM 32
46 #define HNS_ROCE_VF_SL_NUM 8
48 #define HNS_ROCE_V2_MAX_QP_NUM 0x100000
49 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
50 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
51 #define HNS_ROCE_V2_MAX_SRQ 0x100000
52 #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
53 #define HNS_ROCE_V2_MAX_SRQ_SGE 0x100
54 #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
55 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100
56 #define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
57 #define HNS_ROCE_V2_MAX_CQE_NUM 0x10000
58 #define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000
59 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100
60 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff
61 #define HNS_ROCE_V2_MAX_SRQ_SGE_NUM 0x100
62 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
63 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
64 #define HNS_ROCE_V2_UAR_NUM 256
65 #define HNS_ROCE_V2_PHY_UAR_NUM 1
66 #define HNS_ROCE_V2_MAX_IRQ_NUM 65
67 #define HNS_ROCE_V2_COMP_VEC_NUM 63
68 #define HNS_ROCE_V2_AEQE_VEC_NUM 1
69 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
70 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000
71 #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
72 #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
73 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
74 #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
75 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
76 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
77 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
78 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
79 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
80 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
81 #define HNS_ROCE_V2_QPC_ENTRY_SZ 256
82 #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
83 #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
84 #define HNS_ROCE_V2_CQC_ENTRY_SZ 64
85 #define HNS_ROCE_V2_SRQC_ENTRY_SZ 64
86 #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
87 #define HNS_ROCE_V2_MTT_ENTRY_SZ 64
88 #define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
89 #define HNS_ROCE_V2_SCCC_ENTRY_SZ 32
90 #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ 4096
91 #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ 4096
92 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
93 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
94 #define HNS_ROCE_INVALID_LKEY 0x100
95 #define HNS_ROCE_CMQ_TX_TIMEOUT 30000
96 #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
97 #define HNS_ROCE_V2_RSV_QPS 8
99 #define HNS_ROCE_V2_HW_RST_TIMEOUT 1000
101 #define HNS_ROCE_CONTEXT_HOP_NUM 1
102 #define HNS_ROCE_SCCC_HOP_NUM 1
103 #define HNS_ROCE_MTT_HOP_NUM 1
104 #define HNS_ROCE_CQE_HOP_NUM 1
105 #define HNS_ROCE_SRQWQE_HOP_NUM 1
106 #define HNS_ROCE_PBL_HOP_NUM 2
107 #define HNS_ROCE_EQE_HOP_NUM 2
108 #define HNS_ROCE_IDX_HOP_NUM 1
110 #define HNS_ROCE_V2_GID_INDEX_NUM 256
112 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
114 #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
115 #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1
116 #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2
117 #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3
118 #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
119 #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5
121 #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
122 #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
123 #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
124 #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
125 #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
126 #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
128 #define HNS_ROCE_CMQ_DESC_NUM_S 3
129 #define HNS_ROCE_CMQ_EN_B 16
130 #define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B)
132 #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5
134 #define check_whether_last_step(hop_num, step_idx) \
135 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
136 (step_idx == 1 && hop_num == 1) || \
137 (step_idx == 2 && hop_num == 2))
138 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
139 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
141 #define CMD_CSQ_DESC_NUM 1024
142 #define CMD_CRQ_DESC_NUM 1024
147 REG_NXT_SE_CEQE = 0x3
150 #define V2_CQ_DB_REQ_NOT_SOL 0
151 #define V2_CQ_DB_REQ_NOT 1
153 #define V2_CQ_STATE_VALID 1
154 #define V2_QKEY_VAL 0x80010000
156 #define GID_LEN_V2 16
158 #define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff
161 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
162 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
163 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
164 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
165 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
166 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
167 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
168 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
169 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
170 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
171 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
172 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
173 HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc,
174 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
178 HNS_ROCE_SQ_OPCODE_SEND = 0x0,
179 HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1,
180 HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2,
181 HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3,
182 HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4,
183 HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5,
184 HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6,
185 HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7,
186 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8,
187 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9,
188 HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa,
189 HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb,
190 HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc,
195 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
196 HNS_ROCE_V2_OPCODE_SEND = 0x1,
197 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
198 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
202 HNS_ROCE_V2_SQ_DB = 0x0,
203 HNS_ROCE_V2_RQ_DB = 0x1,
204 HNS_ROCE_V2_SRQ_DB = 0x2,
205 HNS_ROCE_V2_CQ_DB_PTR = 0x3,
206 HNS_ROCE_V2_CQ_DB_NTR = 0x4,
210 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
211 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
212 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
213 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
214 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
215 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
216 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
217 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
218 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
219 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
220 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
221 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
222 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
223 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
225 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
229 enum hns_roce_opcode_type {
230 HNS_QUERY_FW_VER = 0x0001,
231 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
232 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
233 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
234 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
235 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
236 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
237 HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404,
238 HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406,
239 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
240 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
241 HNS_ROCE_OPC_POST_MB = 0x8504,
242 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
243 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
244 HNS_ROCE_OPC_CLR_SCCC = 0x8509,
245 HNS_ROCE_OPC_QUERY_SCCC = 0x850a,
246 HNS_ROCE_OPC_RESET_SCCC = 0x850b,
247 HNS_SWITCH_PARAMETER_CFG = 0x1033,
255 enum hns_roce_cmd_return_status {
256 CMD_EXEC_SUCCESS = 0,
262 enum hns_roce_sgid_type {
263 GID_TYPE_FLAG_ROCE_V1 = 0,
264 GID_TYPE_FLAG_ROCE_V2_IPV4,
265 GID_TYPE_FLAG_ROCE_V2_IPV6,
268 struct hns_roce_v2_cq_context {
269 __le32 byte_4_pg_ceqn;
271 __le32 cqe_cur_blk_addr;
272 __le32 byte_16_hop_addr;
273 __le32 cqe_nxt_blk_addr;
274 __le32 byte_24_pgsz_addr;
275 __le32 byte_28_cq_pi;
276 __le32 byte_32_cq_ci;
278 __le32 byte_40_cqe_ba;
279 __le32 byte_44_db_record;
280 __le32 db_record_addr;
281 __le32 byte_52_cqe_cnt;
282 __le32 byte_56_cqe_period_maxcnt;
283 __le32 cqe_report_timer;
284 __le32 byte_64_se_cqe_idx;
286 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
287 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
289 #define V2_CQC_BYTE_4_CQ_ST_S 0
290 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
292 #define V2_CQC_BYTE_4_POLL_S 2
294 #define V2_CQC_BYTE_4_SE_S 3
296 #define V2_CQC_BYTE_4_OVER_IGNORE_S 4
298 #define V2_CQC_BYTE_4_COALESCE_S 5
300 #define V2_CQC_BYTE_4_ARM_ST_S 6
301 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
303 #define V2_CQC_BYTE_4_SHIFT_S 8
304 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
306 #define V2_CQC_BYTE_4_CMD_SN_S 13
307 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
309 #define V2_CQC_BYTE_4_CEQN_S 15
310 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
312 #define V2_CQC_BYTE_4_PAGE_OFFSET_S 24
313 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
315 #define V2_CQC_BYTE_8_CQN_S 0
316 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
318 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
319 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
321 #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
322 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
324 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
325 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
327 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24
328 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
330 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28
331 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
333 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
334 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
336 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
337 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
339 #define V2_CQC_BYTE_40_CQE_BA_S 0
340 #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
342 #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0
344 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1
345 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
347 #define V2_CQC_BYTE_52_CQE_CNT_S 0
348 #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
350 #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
351 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
353 #define V2_CQC_BYTE_56_CQ_PERIOD_S 16
354 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
356 #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
357 #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
359 struct hns_roce_srq_context {
360 __le32 byte_4_srqn_srqst;
361 __le32 byte_8_limit_wl;
363 __le32 byte_16_pi_ci;
365 __le32 byte_24_wqe_bt_ba;
366 __le32 byte_28_rqws_pd;
368 __le32 rsv_idx_bt_ba;
369 __le32 idx_cur_blk_addr;
370 __le32 byte_44_idxbufpgsz_addr;
371 __le32 idx_nxt_blk_addr;
372 __le32 rsv_idxnxtblkaddr;
373 __le32 byte_56_xrc_cqn;
374 __le32 db_record_addr_record_en;
375 __le32 db_record_addr;
378 #define SRQC_BYTE_4_SRQ_ST_S 0
379 #define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0)
381 #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2
382 #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2)
384 #define SRQC_BYTE_4_SRQ_SHIFT_S 4
385 #define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4)
387 #define SRQC_BYTE_4_SRQN_S 8
388 #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
390 #define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0
391 #define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0)
393 #define SRQC_BYTE_12_SRQ_XRCD_S 0
394 #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
396 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0
397 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0)
399 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0
400 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
402 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0
403 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0)
405 #define SRQC_BYTE_28_PD_S 0
406 #define SRQC_BYTE_28_PD_M GENMASK(23, 0)
408 #define SRQC_BYTE_28_RQWS_S 24
409 #define SRQC_BYTE_28_RQWS_M GENMASK(27, 24)
411 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0
412 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0)
414 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0
415 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0)
417 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22
418 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22)
420 #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24
421 #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24)
423 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28
424 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
426 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0
427 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0)
429 #define SRQC_BYTE_56_SRQ_XRC_CQN_S 0
430 #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
432 #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24
433 #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24)
435 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28
436 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
438 #define SRQC_BYTE_60_SRQ_RECORD_EN_S 0
440 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1
441 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
444 V2_MPT_ST_VALID = 0x1,
445 V2_MPT_ST_FREE = 0x2,
448 enum hns_roce_v2_qp_state {
456 HNS_ROCE_QP_ST_SQ_DRAINING,
460 struct hns_roce_v2_qp_context {
461 __le32 byte_4_sqpn_tst;
463 __le32 byte_12_sq_hop;
464 __le32 byte_16_buf_ba_pg_sz;
465 __le32 byte_20_smac_sgid_idx;
466 __le32 byte_24_mtu_tc;
467 __le32 byte_28_at_fl;
470 __le32 byte_52_udpspn_dmac;
471 __le32 byte_56_dqpn_err;
472 __le32 byte_60_qpst_tempid;
474 __le32 byte_68_rq_db;
475 __le32 rq_db_record_addr;
476 __le32 byte_76_srqn_op_en;
477 __le32 byte_80_rnr_rx_cqn;
478 __le32 byte_84_rq_ci_pi;
479 __le32 rq_cur_blk_addr;
480 __le32 byte_92_srq_info;
481 __le32 byte_96_rx_reqmsn;
482 __le32 rq_nxt_blk_addr;
483 __le32 byte_104_rq_sge;
484 __le32 byte_108_rx_reqepsn;
487 __le32 rx_rkey_pkt_info;
489 __le32 byte_132_trrl;
496 __le32 byte_160_sq_ci_pi;
497 __le32 sq_cur_blk_addr;
498 __le32 byte_168_irrl_idx;
499 __le32 byte_172_sq_psn;
500 __le32 byte_176_msg_pktn;
501 __le32 sq_cur_sge_blk_addr;
502 __le32 byte_184_irrl_idx;
503 __le32 cur_sge_offset;
504 __le32 byte_192_ext_sge;
505 __le32 byte_196_sq_psn;
506 __le32 byte_200_sq_max;
508 __le32 byte_208_irrl;
511 __le32 byte_220_retry_psn_msn;
512 __le32 byte_224_retry_msg;
513 __le32 rx_sq_cur_blk_addr;
514 __le32 byte_232_irrl_sge;
515 __le32 irrl_cur_sge_offset;
516 __le32 byte_240_irrl_tail;
517 __le32 byte_244_rnr_rxack;
518 __le32 byte_248_ack_psn;
519 __le32 byte_252_err_txcqn;
520 __le32 byte_256_sqflush_rqcqe;
523 #define V2_QPC_BYTE_4_TST_S 0
524 #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
526 #define V2_QPC_BYTE_4_SGE_SHIFT_S 3
527 #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
529 #define V2_QPC_BYTE_4_SQPN_S 8
530 #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
532 #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
533 #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
535 #define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
536 #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
538 #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
540 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
541 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
543 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
544 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
546 #define V2_QPC_BYTE_16_PD_S 8
547 #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
549 #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
550 #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
552 #define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
553 #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
555 #define V2_QPC_BYTE_20_RQWS_S 4
556 #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
558 #define V2_QPC_BYTE_20_SQ_SHIFT_S 8
559 #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
561 #define V2_QPC_BYTE_20_RQ_SHIFT_S 12
562 #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
564 #define V2_QPC_BYTE_20_SGID_IDX_S 16
565 #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
567 #define V2_QPC_BYTE_20_SMAC_IDX_S 24
568 #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
570 #define V2_QPC_BYTE_24_HOP_LIMIT_S 0
571 #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
573 #define V2_QPC_BYTE_24_TC_S 8
574 #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
576 #define V2_QPC_BYTE_24_VLAN_ID_S 16
577 #define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
579 #define V2_QPC_BYTE_24_MTU_S 28
580 #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
582 #define V2_QPC_BYTE_28_FL_S 0
583 #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
585 #define V2_QPC_BYTE_28_SL_S 20
586 #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
588 #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
590 #define V2_QPC_BYTE_28_CE_FLAG_S 25
592 #define V2_QPC_BYTE_28_LBI_S 26
594 #define V2_QPC_BYTE_28_AT_S 27
595 #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
597 #define V2_QPC_BYTE_52_DMAC_S 0
598 #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
600 #define V2_QPC_BYTE_52_UDPSPN_S 16
601 #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
603 #define V2_QPC_BYTE_56_DQPN_S 0
604 #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
606 #define V2_QPC_BYTE_56_SQ_TX_ERR_S 24
607 #define V2_QPC_BYTE_56_SQ_RX_ERR_S 25
608 #define V2_QPC_BYTE_56_RQ_TX_ERR_S 26
609 #define V2_QPC_BYTE_56_RQ_RX_ERR_S 27
611 #define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
612 #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
614 #define V2_QPC_BYTE_60_TEMPID_S 0
615 #define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
617 #define V2_QPC_BYTE_60_SCC_TOKEN_S 8
618 #define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
620 #define V2_QPC_BYTE_60_SQ_DB_DOING_S 27
622 #define V2_QPC_BYTE_60_RQ_DB_DOING_S 28
624 #define V2_QPC_BYTE_60_QP_ST_S 29
625 #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
627 #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
629 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
630 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
632 #define V2_QPC_BYTE_76_SRQN_S 0
633 #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
635 #define V2_QPC_BYTE_76_SRQ_EN_S 24
637 #define V2_QPC_BYTE_76_RRE_S 25
639 #define V2_QPC_BYTE_76_RWE_S 26
641 #define V2_QPC_BYTE_76_ATE_S 27
643 #define V2_QPC_BYTE_76_RQIE_S 28
645 #define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
646 #define V2_QPC_BYTE_80_RX_CQN_S 0
647 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
649 #define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
650 #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
652 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
653 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
655 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
656 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
658 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
659 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
661 #define V2_QPC_BYTE_92_SRQ_INFO_S 20
662 #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
664 #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
665 #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
667 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
668 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
670 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
671 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
673 #define V2_QPC_BYTE_108_INV_CREDIT_S 0
675 #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
677 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
678 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
680 #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
682 #define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
683 #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
685 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
686 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
688 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
689 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
691 #define V2_QPC_BYTE_132_TRRL_BA_S 16
692 #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
694 #define V2_QPC_BYTE_140_TRRL_BA_S 0
695 #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
697 #define V2_QPC_BYTE_140_RR_MAX_S 12
698 #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
700 #define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
702 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
703 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
705 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
706 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
708 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
709 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
711 #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
712 #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
714 #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
716 #define V2_QPC_BYTE_148_RQ_MSN_S 0
717 #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
719 #define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
720 #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
722 #define V2_QPC_BYTE_152_RAQ_PSN_S 0
723 #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
725 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
726 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
728 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
729 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
731 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
732 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
734 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
735 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
737 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
738 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
740 #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
742 #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
744 #define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
745 #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
747 #define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
748 #define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
749 #define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
750 #define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
751 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
752 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
754 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
755 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
757 #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
759 #define V2_QPC_BYTE_172_FRE_S 7
761 #define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
762 #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
764 #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
765 #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
767 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
768 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
770 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
771 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
773 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
774 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
776 #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
777 #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
779 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
780 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
782 #define V2_QPC_BYTE_196_IRRL_HEAD_S 0
783 #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
785 #define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
786 #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
788 #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
789 #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
791 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
792 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
794 #define V2_QPC_BYTE_208_IRRL_BA_S 0
795 #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
797 #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
799 #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
801 #define V2_QPC_BYTE_208_RMT_E2E_S 28
803 #define V2_QPC_BYTE_208_SR_MAX_S 29
804 #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
806 #define V2_QPC_BYTE_212_LSN_S 0
807 #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
809 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
810 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
812 #define V2_QPC_BYTE_212_CHECK_FLG_S 27
813 #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
815 #define V2_QPC_BYTE_212_RETRY_CNT_S 29
816 #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
818 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
819 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
821 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
822 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
824 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
825 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
827 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
828 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
830 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
831 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
833 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
834 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
836 #define V2_QPC_BYTE_232_SO_LP_VLD_S 29
837 #define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
838 #define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
840 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
841 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
843 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
844 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
846 #define V2_QPC_BYTE_240_RX_ACK_MSN_S 16
847 #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
849 #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
850 #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
852 #define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
853 #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
855 #define V2_QPC_BYTE_244_RNR_CNT_S 27
856 #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
858 #define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
859 #define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
861 #define V2_QPC_BYTE_248_IRRL_PSN_S 0
862 #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
864 #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
866 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
867 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
869 #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
871 #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
873 #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
875 #define V2_QPC_BYTE_252_TX_CQN_S 0
876 #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
878 #define V2_QPC_BYTE_252_SIG_TYPE_S 24
880 #define V2_QPC_BYTE_252_ERR_TYPE_S 25
881 #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
883 #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
884 #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
886 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
887 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
889 struct hns_roce_v2_cqe {
903 #define V2_CQE_BYTE_4_OPCODE_S 0
904 #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
906 #define V2_CQE_BYTE_4_RQ_INLINE_S 5
908 #define V2_CQE_BYTE_4_S_R_S 6
910 #define V2_CQE_BYTE_4_OWNER_S 7
912 #define V2_CQE_BYTE_4_STATUS_S 8
913 #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
915 #define V2_CQE_BYTE_4_WQE_INDX_S 16
916 #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
918 #define V2_CQE_BYTE_12_XRC_SRQN_S 0
919 #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
921 #define V2_CQE_BYTE_16_LCL_QPN_S 0
922 #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
924 #define V2_CQE_BYTE_16_SUB_STATUS_S 24
925 #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
927 #define V2_CQE_BYTE_28_SMAC_4_S 0
928 #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0)
930 #define V2_CQE_BYTE_28_SMAC_5_S 8
931 #define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8)
933 #define V2_CQE_BYTE_28_PORT_TYPE_S 16
934 #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
936 #define V2_CQE_BYTE_28_VID_S 18
937 #define V2_CQE_BYTE_28_VID_M GENMASK(29, 18)
939 #define V2_CQE_BYTE_28_VID_VLD_S 30
941 #define V2_CQE_BYTE_32_RMT_QPN_S 0
942 #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
944 #define V2_CQE_BYTE_32_SL_S 24
945 #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
947 #define V2_CQE_BYTE_32_PORTN_S 27
948 #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
950 #define V2_CQE_BYTE_32_GRH_S 30
952 #define V2_CQE_BYTE_32_LPK_S 31
954 struct hns_roce_v2_mpt_entry {
955 __le32 byte_4_pd_hop_st;
956 __le32 byte_8_mw_cnt_en;
957 __le32 byte_12_mw_pa;
966 __le32 byte_48_mode_ba;
968 __le32 byte_56_pa0_h;
970 __le32 byte_64_buf_pa1;
973 #define V2_MPT_BYTE_4_MPT_ST_S 0
974 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
976 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
977 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
979 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
980 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
982 #define V2_MPT_BYTE_4_PD_S 8
983 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
985 #define V2_MPT_BYTE_8_RA_EN_S 0
987 #define V2_MPT_BYTE_8_R_INV_EN_S 1
989 #define V2_MPT_BYTE_8_L_INV_EN_S 2
991 #define V2_MPT_BYTE_8_BIND_EN_S 3
993 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4
995 #define V2_MPT_BYTE_8_RR_EN_S 5
997 #define V2_MPT_BYTE_8_RW_EN_S 6
999 #define V2_MPT_BYTE_8_LW_EN_S 7
1001 #define V2_MPT_BYTE_8_MW_CNT_S 8
1002 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
1004 #define V2_MPT_BYTE_12_FRE_S 0
1006 #define V2_MPT_BYTE_12_PA_S 1
1008 #define V2_MPT_BYTE_12_MR_MW_S 4
1010 #define V2_MPT_BYTE_12_BPD_S 5
1012 #define V2_MPT_BYTE_12_BQP_S 6
1014 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
1016 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
1017 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
1019 #define V2_MPT_BYTE_48_PBL_BA_H_S 0
1020 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
1022 #define V2_MPT_BYTE_48_BLK_MODE_S 29
1024 #define V2_MPT_BYTE_56_PA0_H_S 0
1025 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
1027 #define V2_MPT_BYTE_64_PA1_H_S 0
1028 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
1030 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
1031 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
1033 #define V2_DB_BYTE_4_TAG_S 0
1034 #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
1036 #define V2_DB_BYTE_4_CMD_S 24
1037 #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24)
1039 #define V2_DB_PARAMETER_IDX_S 0
1040 #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0)
1042 #define V2_DB_PARAMETER_SL_S 16
1043 #define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
1045 struct hns_roce_v2_cq_db {
1050 #define V2_CQ_DB_BYTE_4_TAG_S 0
1051 #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
1053 #define V2_CQ_DB_BYTE_4_CMD_S 24
1054 #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24)
1056 #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0
1057 #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
1059 #define V2_CQ_DB_PARAMETER_CMD_SN_S 25
1060 #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25)
1062 #define V2_CQ_DB_PARAMETER_NOTIFY_S 24
1064 struct hns_roce_v2_ud_send_wqe {
1077 u8 dgid[GID_LEN_V2];
1080 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
1081 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1083 #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
1085 #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8
1087 #define V2_UD_SEND_WQE_BYTE_4_SE_S 11
1089 #define V2_UD_SEND_WQE_BYTE_16_PD_S 0
1090 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
1092 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
1093 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1095 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1096 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1098 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
1099 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
1101 #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
1102 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
1104 #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
1105 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
1107 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
1108 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
1110 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
1111 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
1113 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
1114 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
1116 #define V2_UD_SEND_WQE_BYTE_40_SL_S 20
1117 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
1119 #define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24
1120 #define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24)
1122 #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
1124 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
1126 #define V2_UD_SEND_WQE_DMAC_0_S 0
1127 #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0)
1129 #define V2_UD_SEND_WQE_DMAC_1_S 8
1130 #define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8)
1132 #define V2_UD_SEND_WQE_DMAC_2_S 16
1133 #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16)
1135 #define V2_UD_SEND_WQE_DMAC_3_S 24
1136 #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
1138 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0
1139 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0)
1141 #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8
1142 #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8)
1144 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16
1145 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16)
1147 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24
1148 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
1150 struct hns_roce_v2_rc_send_wqe {
1163 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
1164 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1166 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
1168 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
1170 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
1172 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10
1174 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11
1176 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
1178 #define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19
1180 #define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20
1182 #define V2_RC_FRMR_WQE_BYTE_4_RR_S 21
1184 #define V2_RC_FRMR_WQE_BYTE_4_RW_S 22
1186 #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23
1188 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1189 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1191 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
1192 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1194 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1195 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1197 struct hns_roce_wqe_frmr_seg {
1199 __le32 mode_buf_pg_sz;
1202 #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4
1203 #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4)
1205 #define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8
1207 struct hns_roce_v2_wqe_data_seg {
1213 struct hns_roce_v2_db {
1218 struct hns_roce_query_version {
1219 __le16 rocee_vendor_id;
1220 __le16 rocee_hw_version;
1224 struct hns_roce_query_fw_info {
1229 struct hns_roce_cfg_llm_a {
1232 __le32 depth_pgsz_init_en;
1234 __le32 head_ba_h_nxtptr;
1238 #define CFG_LLM_QUE_DEPTH_S 0
1239 #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
1241 #define CFG_LLM_QUE_PGSZ_S 16
1242 #define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16)
1244 #define CFG_LLM_INIT_EN_S 20
1245 #define CFG_LLM_INIT_EN_M GENMASK(20, 20)
1247 #define CFG_LLM_HEAD_PTR_S 0
1248 #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
1250 struct hns_roce_cfg_llm_b {
1257 #define CFG_LLM_TAIL_BA_H_S 0
1258 #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
1260 #define CFG_LLM_TAIL_PTR_S 0
1261 #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
1263 struct hns_roce_cfg_global_param {
1264 __le32 time_cfg_udp_port;
1268 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
1269 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
1271 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16
1272 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
1274 struct hns_roce_pf_res_a {
1276 __le32 qpc_bt_idx_num;
1277 __le32 srqc_bt_idx_num;
1278 __le32 cqc_bt_idx_num;
1279 __le32 mpt_bt_idx_num;
1280 __le32 eqc_bt_idx_num;
1283 #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
1284 #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
1286 #define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16
1287 #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
1289 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
1290 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
1292 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16
1293 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
1295 #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
1296 #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
1298 #define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16
1299 #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
1301 #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
1302 #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
1304 #define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16
1305 #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
1307 #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
1308 #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
1310 #define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16
1311 #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
1313 struct hns_roce_pf_res_b {
1315 __le32 smac_idx_num;
1316 __le32 sgid_idx_num;
1317 __le32 qid_idx_sl_num;
1318 __le32 sccc_bt_idx_num;
1322 #define PF_RES_DATA_1_PF_SMAC_IDX_S 0
1323 #define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0)
1325 #define PF_RES_DATA_1_PF_SMAC_NUM_S 8
1326 #define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8)
1328 #define PF_RES_DATA_2_PF_SGID_IDX_S 0
1329 #define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0)
1331 #define PF_RES_DATA_2_PF_SGID_NUM_S 8
1332 #define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8)
1334 #define PF_RES_DATA_3_PF_QID_IDX_S 0
1335 #define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0)
1337 #define PF_RES_DATA_3_PF_SL_NUM_S 16
1338 #define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16)
1340 #define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0
1341 #define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0)
1343 #define PF_RES_DATA_4_PF_SCCC_BT_NUM_S 9
1344 #define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9)
1346 struct hns_roce_pf_timer_res_a {
1348 __le32 qpc_timer_bt_idx_num;
1349 __le32 cqc_timer_bt_idx_num;
1353 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0
1354 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0)
1356 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S 16
1357 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16)
1359 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0
1360 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0)
1362 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S 16
1363 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16)
1365 struct hns_roce_vf_res_a {
1367 __le32 vf_qpc_bt_idx_num;
1368 __le32 vf_srqc_bt_idx_num;
1369 __le32 vf_cqc_bt_idx_num;
1370 __le32 vf_mpt_bt_idx_num;
1371 __le32 vf_eqc_bt_idx_num;
1374 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
1375 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
1377 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16
1378 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
1380 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
1381 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
1383 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16
1384 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
1386 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
1387 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
1389 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16
1390 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
1392 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
1393 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
1395 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16
1396 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
1398 #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
1399 #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
1401 #define VF_RES_A_DATA_5_VF_EQC_NUM_S 16
1402 #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
1404 struct hns_roce_vf_res_b {
1406 __le32 vf_smac_idx_num;
1407 __le32 vf_sgid_idx_num;
1408 __le32 vf_qid_idx_sl_num;
1409 __le32 vf_sccc_idx_num;
1413 #define VF_RES_B_DATA_0_VF_ID_S 0
1414 #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
1416 #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
1417 #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
1419 #define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8
1420 #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
1422 #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
1423 #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
1425 #define VF_RES_B_DATA_2_VF_SGID_NUM_S 8
1426 #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
1428 #define VF_RES_B_DATA_3_VF_QID_IDX_S 0
1429 #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
1431 #define VF_RES_B_DATA_3_VF_SL_NUM_S 16
1432 #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
1434 #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0
1435 #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0)
1437 #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S 9
1438 #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9)
1440 struct hns_roce_vf_switch {
1449 #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
1450 #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
1452 #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
1453 #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
1454 #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
1456 struct hns_roce_post_mbox {
1462 __le32 token_event_en;
1465 struct hns_roce_mbox_status {
1466 __le32 mb_status_hw_run;
1470 struct hns_roce_cfg_bt_attr {
1479 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
1480 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
1482 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4
1483 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4)
1485 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8
1486 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8)
1488 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0
1489 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
1491 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4
1492 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4)
1494 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8
1495 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8)
1497 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0
1498 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
1500 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4
1501 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4)
1503 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8
1504 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8)
1506 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0
1507 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
1509 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4
1510 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4)
1512 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8
1513 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
1515 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0
1516 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0)
1518 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S 4
1519 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4)
1521 #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S 8
1522 #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8)
1524 struct hns_roce_cfg_sgid_tb {
1525 __le32 table_idx_rsv;
1530 __le32 vf_sgid_type_rsv;
1532 #define CFG_SGID_TB_TABLE_IDX_S 0
1533 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1535 #define CFG_SGID_TB_VF_SGID_TYPE_S 0
1536 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1538 struct hns_roce_cfg_smac_tb {
1541 __le32 vf_smac_h_rsv;
1544 #define CFG_SMAC_TB_IDX_S 0
1545 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1547 #define CFG_SMAC_TB_VF_SMAC_H_S 0
1548 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1550 struct hns_roce_cmq_desc {
1558 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1560 #define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1561 #define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
1563 struct hns_roce_v2_cmq_ring {
1564 dma_addr_t desc_dma_addr;
1565 struct hns_roce_cmq_desc *desc;
1574 spinlock_t lock; /* command queue lock */
1577 struct hns_roce_v2_cmq {
1578 struct hns_roce_v2_cmq_ring csq;
1579 struct hns_roce_v2_cmq_ring crq;
1584 enum hns_roce_link_table_type {
1589 struct hns_roce_link_table {
1590 struct hns_roce_buf_list table;
1591 struct hns_roce_buf_list *pg_list;
1596 struct hns_roce_link_table_entry {
1598 u32 blk_ba1_nxt_ptr;
1600 #define HNS_ROCE_LINK_TABLE_BA1_S 0
1601 #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
1603 #define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20
1604 #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1606 struct hns_roce_v2_priv {
1607 struct hnae3_handle *handle;
1608 struct hns_roce_v2_cmq cmq;
1609 struct hns_roce_link_table tsq;
1610 struct hns_roce_link_table tpq;
1613 struct hns_roce_eq_context {
1617 __le32 eqe_report_timer;
1628 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1629 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1630 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1631 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1633 #define HNS_ROCE_V2_EQ_STATE_INVALID 0
1634 #define HNS_ROCE_V2_EQ_STATE_VALID 1
1635 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2
1636 #define HNS_ROCE_V2_EQ_STATE_FAILURE 3
1638 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1639 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1
1641 #define HNS_ROCE_V2_EQ_COALESCE_0 0
1642 #define HNS_ROCE_V2_EQ_COALESCE_1 1
1644 #define HNS_ROCE_V2_EQ_FIRED 0
1645 #define HNS_ROCE_V2_EQ_ARMED 1
1646 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3
1648 #define HNS_ROCE_EQ_INIT_EQE_CNT 0
1649 #define HNS_ROCE_EQ_INIT_PROD_IDX 0
1650 #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1651 #define HNS_ROCE_EQ_INIT_MSI_IDX 0
1652 #define HNS_ROCE_EQ_INIT_CONS_IDX 0
1653 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1655 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1656 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1658 #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1659 #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1661 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1662 #define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1
1663 #define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2
1665 #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1666 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1667 #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1668 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1671 #define EQ_DISABLE 0
1673 #define EQ_REG_OFFSET 0x4
1675 #define HNS_ROCE_INT_NAME_LEN 32
1676 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1678 #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
1680 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1681 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1682 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1683 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1684 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1687 #define HNS_ROCE_EQC_EQ_ST_S 0
1688 #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
1690 #define HNS_ROCE_EQC_HOP_NUM_S 2
1691 #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)
1693 #define HNS_ROCE_EQC_OVER_IGNORE_S 4
1694 #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)
1696 #define HNS_ROCE_EQC_COALESCE_S 5
1697 #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)
1699 #define HNS_ROCE_EQC_ARM_ST_S 6
1700 #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)
1702 #define HNS_ROCE_EQC_EQN_S 8
1703 #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)
1705 #define HNS_ROCE_EQC_EQE_CNT_S 16
1706 #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
1709 #define HNS_ROCE_EQC_BA_PG_SZ_S 0
1710 #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
1712 #define HNS_ROCE_EQC_BUF_PG_SZ_S 4
1713 #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
1715 #define HNS_ROCE_EQC_PROD_INDX_S 8
1716 #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
1719 #define HNS_ROCE_EQC_MAX_CNT_S 0
1720 #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
1722 #define HNS_ROCE_EQC_PERIOD_S 16
1723 #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
1726 #define HNS_ROCE_EQC_REPORT_TIMER_S 0
1727 #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
1730 #define HNS_ROCE_EQC_EQE_BA_L_S 0
1731 #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
1734 #define HNS_ROCE_EQC_EQE_BA_H_S 0
1735 #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
1738 #define HNS_ROCE_EQC_SHIFT_S 0
1739 #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
1741 #define HNS_ROCE_EQC_MSI_INDX_S 8
1742 #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
1744 #define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16
1745 #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
1748 #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
1749 #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
1752 #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
1753 #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
1755 #define HNS_ROCE_EQC_CONS_INDX_S 8
1756 #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
1759 #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
1760 #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
1763 #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
1764 #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
1766 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1767 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1769 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1770 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1772 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1773 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1775 #define HNS_ROCE_V2_EQ_DB_CMD_S 16
1776 #define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16)
1778 #define HNS_ROCE_V2_EQ_DB_TAG_S 0
1779 #define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0)
1781 #define HNS_ROCE_V2_EQ_DB_PARA_S 0
1782 #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
1784 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1785 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1787 struct hns_roce_wqe_atomic_seg {
1788 __le64 fetchadd_swap_data;
1792 struct hns_roce_sccc_clr {
1797 struct hns_roce_sccc_clr_done {
1802 int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn,
1805 static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
1808 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1809 struct hnae3_handle *handle = priv->handle;
1810 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1812 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
1813 hns_roce_write64_k(val, dest);