2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_HW_V1_H
34 #define _HNS_ROCE_HW_V1_H
36 #define CQ_STATE_VALID 2
38 #define HNS_ROCE_V1_MAX_PD_NUM 0x8000
39 #define HNS_ROCE_V1_MAX_CQ_NUM 0x10000
40 #define HNS_ROCE_V1_MAX_CQE_NUM 0x8000
42 #define HNS_ROCE_V1_MAX_QP_NUM 0x40000
43 #define HNS_ROCE_V1_MAX_WQE_NUM 0x4000
45 #define HNS_ROCE_V1_MAX_MTPT_NUM 0x80000
47 #define HNS_ROCE_V1_MAX_MTT_SEGS 0x100000
49 #define HNS_ROCE_V1_MAX_QP_INIT_RDMA 128
50 #define HNS_ROCE_V1_MAX_QP_DEST_RDMA 128
52 #define HNS_ROCE_V1_MAX_SQ_DESC_SZ 64
53 #define HNS_ROCE_V1_MAX_RQ_DESC_SZ 64
54 #define HNS_ROCE_V1_SG_NUM 2
55 #define HNS_ROCE_V1_INLINE_SIZE 32
57 #define HNS_ROCE_V1_UAR_NUM 256
58 #define HNS_ROCE_V1_PHY_UAR_NUM 8
60 #define HNS_ROCE_V1_GID_NUM 16
61 #define HNS_ROCE_V1_RESV_QP 8
63 #define HNS_ROCE_V1_MAX_IRQ_NUM 34
64 #define HNS_ROCE_V1_COMP_VEC_NUM 32
65 #define HNS_ROCE_V1_AEQE_VEC_NUM 1
66 #define HNS_ROCE_V1_ABNORMAL_VEC_NUM 1
68 #define HNS_ROCE_V1_COMP_EQE_NUM 0x8000
69 #define HNS_ROCE_V1_ASYNC_EQE_NUM 0x400
71 #define HNS_ROCE_V1_QPC_SIZE 256
72 #define HNS_ROCE_V1_IRRL_ENTRY_SIZE 8
73 #define HNS_ROCE_V1_CQC_ENTRY_SIZE 64
74 #define HNS_ROCE_V1_MTPT_ENTRY_SIZE 64
75 #define HNS_ROCE_V1_MTT_ENTRY_SIZE 64
77 #define HNS_ROCE_V1_CQE_SIZE 32
78 #define HNS_ROCE_V1_PAGE_SIZE_SUPPORT 0xFFFFF000
80 #define HNS_ROCE_V1_TABLE_CHUNK_SIZE (1 << 17)
82 #define HNS_ROCE_V1_EXT_RAQ_WF 8
83 #define HNS_ROCE_V1_RAQ_ENTRY 64
84 #define HNS_ROCE_V1_RAQ_DEPTH 32768
85 #define HNS_ROCE_V1_RAQ_SIZE (HNS_ROCE_V1_RAQ_ENTRY * HNS_ROCE_V1_RAQ_DEPTH)
87 #define HNS_ROCE_V1_SDB_DEPTH 0x400
88 #define HNS_ROCE_V1_ODB_DEPTH 0x400
90 #define HNS_ROCE_V1_DB_RSVD 0x80
92 #define HNS_ROCE_V1_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
93 #define HNS_ROCE_V1_SDB_ALFUL (HNS_ROCE_V1_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
94 #define HNS_ROCE_V1_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
95 #define HNS_ROCE_V1_ODB_ALFUL (HNS_ROCE_V1_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
97 #define HNS_ROCE_V1_EXT_SDB_DEPTH 0x4000
98 #define HNS_ROCE_V1_EXT_ODB_DEPTH 0x4000
99 #define HNS_ROCE_V1_EXT_SDB_ENTRY 16
100 #define HNS_ROCE_V1_EXT_ODB_ENTRY 16
101 #define HNS_ROCE_V1_EXT_SDB_SIZE \
102 (HNS_ROCE_V1_EXT_SDB_DEPTH * HNS_ROCE_V1_EXT_SDB_ENTRY)
103 #define HNS_ROCE_V1_EXT_ODB_SIZE \
104 (HNS_ROCE_V1_EXT_ODB_DEPTH * HNS_ROCE_V1_EXT_ODB_ENTRY)
106 #define HNS_ROCE_V1_EXT_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
107 #define HNS_ROCE_V1_EXT_SDB_ALFUL \
108 (HNS_ROCE_V1_EXT_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
109 #define HNS_ROCE_V1_EXT_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
110 #define HNS_ROCE_V1_EXT_ODB_ALFUL \
111 (HNS_ROCE_V1_EXT_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
113 #define HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS 50000
114 #define HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS 10000
115 #define HNS_ROCE_V1_FREE_MR_WAIT_VALUE 5
116 #define HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE 20
118 #define HNS_ROCE_BT_RSV_BUF_SIZE (1 << 17)
120 #define HNS_ROCE_V1_TPTR_ENTRY_SIZE 2
121 #define HNS_ROCE_V1_TPTR_BUF_SIZE \
122 (HNS_ROCE_V1_TPTR_ENTRY_SIZE * HNS_ROCE_V1_MAX_CQ_NUM)
124 #define HNS_ROCE_ODB_POLL_MODE 0
126 #define HNS_ROCE_SDB_NORMAL_MODE 0
127 #define HNS_ROCE_SDB_EXTEND_MODE 1
129 #define HNS_ROCE_ODB_EXTEND_MODE 1
131 #define KEY_VALID 0x02
133 #define HNS_ROCE_CQE_QPN_MASK 0x3ffff
134 #define HNS_ROCE_CQE_STATUS_MASK 0x1f
135 #define HNS_ROCE_CQE_OPCODE_MASK 0xf
137 #define HNS_ROCE_CQE_SUCCESS 0x00
138 #define HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR 0x01
139 #define HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR 0x02
140 #define HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR 0x03
141 #define HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR 0x04
142 #define HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR 0x05
143 #define HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR 0x06
144 #define HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR 0x07
145 #define HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR 0x08
146 #define HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR 0x09
147 #define HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR 0x0a
148 #define HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR 0x0b
149 #define HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR 0x0c
151 #define QP1C_CFGN_OFFSET 0x28
152 #define PHY_PORT_OFFSET 0x8
153 #define MTPT_IDX_SHIFT 16
154 #define ALL_PORT_VAL_OPEN 0x3f
155 #define POL_TIME_INTERVAL_VAL 0x80
156 #define SLEEP_TIME_INTERVAL 20
157 #define SQ_PSN_SHIFT 8
158 #define QKEY_VAL 0x80010000
159 #define SDB_INV_CNT_OFFSET 8
161 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x10
162 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x10
164 #define HNS_ROCE_INT_MASK_DISABLE 0
165 #define HNS_ROCE_INT_MASK_ENABLE 1
167 #define CEQ_REG_OFFSET 0x18
169 #define HNS_ROCE_CEQE_CEQE_COMP_OWNER_S 0
171 #define HNS_ROCE_V1_CONS_IDX_M GENMASK(15, 0)
173 #define HNS_ROCE_CEQE_CEQE_COMP_CQN_S 16
174 #define HNS_ROCE_CEQE_CEQE_COMP_CQN_M GENMASK(31, 16)
176 #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S 16
177 #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M GENMASK(23, 16)
179 #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S 24
180 #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M GENMASK(30, 24)
182 #define HNS_ROCE_AEQE_U32_4_OWNER_S 31
184 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S 0
185 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M GENMASK(23, 0)
187 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S 25
188 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M GENMASK(27, 25)
190 #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S 0
191 #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M GENMASK(15, 0)
193 #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0
194 #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M GENMASK(4, 0)
196 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
198 HNS_ROCE_LWQCE_QPC_ERROR = 1,
199 HNS_ROCE_LWQCE_MTU_ERROR,
200 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR,
201 HNS_ROCE_LWQCE_WQE_ADDR_ERROR,
202 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR,
203 HNS_ROCE_LWQCE_SL_ERROR,
204 HNS_ROCE_LWQCE_PORT_ERROR,
207 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
209 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1,
210 HNS_ROCE_LAVWQE_LENGTH_ERROR,
211 HNS_ROCE_LAVWQE_VA_ERROR,
212 HNS_ROCE_LAVWQE_PD_ERROR,
213 HNS_ROCE_LAVWQE_RW_ACC_ERROR,
214 HNS_ROCE_LAVWQE_KEY_STATE_ERROR,
215 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR,
218 /* DOORBELL overflow subtype */
220 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1,
221 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF,
222 HNS_ROCE_DB_SUBTYPE_ODB_OVF,
223 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF,
224 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP,
225 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP,
229 /* RQ&SRQ related operations */
230 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06,
231 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE,
235 HNS_ROCE_PORT_DOWN = 0,
239 struct hns_roce_cq_context {
243 __le32 cur_cqe_ba0_l;
245 __le32 cqe_tptr_addr_l;
246 __le32 cur_cqe_ba1_l;
250 #define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S 0
251 #define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M \
252 (((1UL << 2) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S)
254 #define CQ_CONTEXT_CQC_BYTE_4_CQN_S 16
255 #define CQ_CONTEXT_CQC_BYTE_4_CQN_M \
256 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQN_S)
258 #define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S 0
259 #define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M \
260 (((1UL << 17) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S)
262 #define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S 20
263 #define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M \
264 (((1UL << 4) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S)
266 #define CQ_CONTEXT_CQC_BYTE_12_CEQN_S 24
267 #define CQ_CONTEXT_CQC_BYTE_12_CEQN_M \
268 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_12_CEQN_S)
270 #define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S 0
271 #define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M \
272 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S)
274 #define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S 16
275 #define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M \
276 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S)
278 #define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S 8
279 #define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M \
280 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S)
282 #define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S 0
283 #define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M \
284 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S)
286 #define CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S 9
288 #define CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S 8
289 #define CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S 14
290 #define CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S 15
292 #define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S 16
293 #define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M \
294 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S)
296 struct hns_roce_cqe {
300 __le32 immediate_data;
310 #define CQE_BYTE_4_OWNER_S 7
311 #define CQE_BYTE_4_SQ_RQ_FLAG_S 14
313 #define CQE_BYTE_4_STATUS_OF_THE_OPERATION_S 8
314 #define CQE_BYTE_4_STATUS_OF_THE_OPERATION_M \
315 (((1UL << 5) - 1) << CQE_BYTE_4_STATUS_OF_THE_OPERATION_S)
317 #define CQE_BYTE_4_WQE_INDEX_S 16
318 #define CQE_BYTE_4_WQE_INDEX_M (((1UL << 14) - 1) << CQE_BYTE_4_WQE_INDEX_S)
320 #define CQE_BYTE_4_OPERATION_TYPE_S 0
321 #define CQE_BYTE_4_OPERATION_TYPE_M \
322 (((1UL << 4) - 1) << CQE_BYTE_4_OPERATION_TYPE_S)
324 #define CQE_BYTE_4_IMM_INDICATOR_S 15
326 #define CQE_BYTE_16_LOCAL_QPN_S 0
327 #define CQE_BYTE_16_LOCAL_QPN_M (((1UL << 24) - 1) << CQE_BYTE_16_LOCAL_QPN_S)
329 #define CQE_BYTE_20_PORT_NUM_S 26
330 #define CQE_BYTE_20_PORT_NUM_M (((1UL << 3) - 1) << CQE_BYTE_20_PORT_NUM_S)
332 #define CQE_BYTE_20_SL_S 24
333 #define CQE_BYTE_20_SL_M (((1UL << 2) - 1) << CQE_BYTE_20_SL_S)
335 #define CQE_BYTE_20_REMOTE_QPN_S 0
336 #define CQE_BYTE_20_REMOTE_QPN_M \
337 (((1UL << 24) - 1) << CQE_BYTE_20_REMOTE_QPN_S)
339 #define CQE_BYTE_20_GRH_PRESENT_S 29
341 #define CQE_BYTE_28_P_KEY_IDX_S 16
342 #define CQE_BYTE_28_P_KEY_IDX_M (((1UL << 16) - 1) << CQE_BYTE_28_P_KEY_IDX_S)
344 #define CQ_DB_REQ_NOT_SOL 0
345 #define CQ_DB_REQ_NOT (1 << 16)
347 struct hns_roce_v1_mpt_entry {
366 #define MPT_BYTE_4_KEY_STATE_S 0
367 #define MPT_BYTE_4_KEY_STATE_M (((1UL << 2) - 1) << MPT_BYTE_4_KEY_STATE_S)
369 #define MPT_BYTE_4_KEY_S 8
370 #define MPT_BYTE_4_KEY_M (((1UL << 8) - 1) << MPT_BYTE_4_KEY_S)
372 #define MPT_BYTE_4_PAGE_SIZE_S 16
373 #define MPT_BYTE_4_PAGE_SIZE_M (((1UL << 2) - 1) << MPT_BYTE_4_PAGE_SIZE_S)
375 #define MPT_BYTE_4_MW_TYPE_S 20
377 #define MPT_BYTE_4_MW_BIND_ENABLE_S 21
379 #define MPT_BYTE_4_OWN_S 22
381 #define MPT_BYTE_4_MEMORY_LOCATION_TYPE_S 24
382 #define MPT_BYTE_4_MEMORY_LOCATION_TYPE_M \
383 (((1UL << 2) - 1) << MPT_BYTE_4_MEMORY_LOCATION_TYPE_S)
385 #define MPT_BYTE_4_REMOTE_ATOMIC_S 26
386 #define MPT_BYTE_4_LOCAL_WRITE_S 27
387 #define MPT_BYTE_4_REMOTE_WRITE_S 28
388 #define MPT_BYTE_4_REMOTE_READ_S 29
389 #define MPT_BYTE_4_REMOTE_INVAL_ENABLE_S 30
390 #define MPT_BYTE_4_ADDRESS_TYPE_S 31
392 #define MPT_BYTE_12_PBL_ADDR_H_S 0
393 #define MPT_BYTE_12_PBL_ADDR_H_M \
394 (((1UL << 17) - 1) << MPT_BYTE_12_PBL_ADDR_H_S)
396 #define MPT_BYTE_12_MW_BIND_COUNTER_S 17
397 #define MPT_BYTE_12_MW_BIND_COUNTER_M \
398 (((1UL << 15) - 1) << MPT_BYTE_12_MW_BIND_COUNTER_S)
400 #define MPT_BYTE_28_PD_S 0
401 #define MPT_BYTE_28_PD_M (((1UL << 16) - 1) << MPT_BYTE_28_PD_S)
403 #define MPT_BYTE_28_L_KEY_IDX_L_S 16
404 #define MPT_BYTE_28_L_KEY_IDX_L_M \
405 (((1UL << 16) - 1) << MPT_BYTE_28_L_KEY_IDX_L_S)
407 #define MPT_BYTE_36_PA0_H_S 0
408 #define MPT_BYTE_36_PA0_H_M (((1UL << 5) - 1) << MPT_BYTE_36_PA0_H_S)
410 #define MPT_BYTE_36_PA1_L_S 8
411 #define MPT_BYTE_36_PA1_L_M (((1UL << 24) - 1) << MPT_BYTE_36_PA1_L_S)
413 #define MPT_BYTE_40_PA1_H_S 0
414 #define MPT_BYTE_40_PA1_H_M (((1UL << 13) - 1) << MPT_BYTE_40_PA1_H_S)
416 #define MPT_BYTE_40_PA2_L_S 16
417 #define MPT_BYTE_40_PA2_L_M (((1UL << 16) - 1) << MPT_BYTE_40_PA2_L_S)
419 #define MPT_BYTE_44_PA2_H_S 0
420 #define MPT_BYTE_44_PA2_H_M (((1UL << 21) - 1) << MPT_BYTE_44_PA2_H_S)
422 #define MPT_BYTE_44_PA3_L_S 24
423 #define MPT_BYTE_44_PA3_L_M (((1UL << 8) - 1) << MPT_BYTE_44_PA3_L_S)
425 #define MPT_BYTE_48_PA3_H_S 0
426 #define MPT_BYTE_48_PA3_H_M (((1UL << 29) - 1) << MPT_BYTE_48_PA3_H_S)
428 #define MPT_BYTE_56_PA4_H_S 0
429 #define MPT_BYTE_56_PA4_H_M (((1UL << 5) - 1) << MPT_BYTE_56_PA4_H_S)
431 #define MPT_BYTE_56_PA5_L_S 8
432 #define MPT_BYTE_56_PA5_L_M (((1UL << 24) - 1) << MPT_BYTE_56_PA5_L_S)
434 #define MPT_BYTE_60_PA5_H_S 0
435 #define MPT_BYTE_60_PA5_H_M (((1UL << 13) - 1) << MPT_BYTE_60_PA5_H_S)
437 #define MPT_BYTE_60_PA6_L_S 16
438 #define MPT_BYTE_60_PA6_L_M (((1UL << 16) - 1) << MPT_BYTE_60_PA6_L_S)
440 #define MPT_BYTE_64_PA6_H_S 0
441 #define MPT_BYTE_64_PA6_H_M (((1UL << 21) - 1) << MPT_BYTE_64_PA6_H_S)
443 #define MPT_BYTE_64_L_KEY_IDX_H_S 24
444 #define MPT_BYTE_64_L_KEY_IDX_H_M \
445 (((1UL << 8) - 1) << MPT_BYTE_64_L_KEY_IDX_H_S)
447 struct hns_roce_wqe_ctrl_seg {
457 struct hns_roce_wqe_data_seg {
463 struct hns_roce_wqe_raddr_seg {
465 __le32 len; /* reserved */
469 struct hns_roce_rq_wqe_ctrl {
471 __le32 rocee_sgl_ba_l;
476 #define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S 16
477 #define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M \
478 (((1UL << 6) - 1) << RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S)
480 #define HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS 10000
484 struct hns_roce_ud_send_wqe {
487 __le32 immediate_data;
491 unsigned char dgid[GID_LEN];
512 #define UD_SEND_WQE_U32_4_DMAC_0_S 0
513 #define UD_SEND_WQE_U32_4_DMAC_0_M \
514 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_0_S)
516 #define UD_SEND_WQE_U32_4_DMAC_1_S 8
517 #define UD_SEND_WQE_U32_4_DMAC_1_M \
518 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_1_S)
520 #define UD_SEND_WQE_U32_4_DMAC_2_S 16
521 #define UD_SEND_WQE_U32_4_DMAC_2_M \
522 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_2_S)
524 #define UD_SEND_WQE_U32_4_DMAC_3_S 24
525 #define UD_SEND_WQE_U32_4_DMAC_3_M \
526 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_3_S)
528 #define UD_SEND_WQE_U32_8_DMAC_4_S 0
529 #define UD_SEND_WQE_U32_8_DMAC_4_M \
530 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_4_S)
532 #define UD_SEND_WQE_U32_8_DMAC_5_S 8
533 #define UD_SEND_WQE_U32_8_DMAC_5_M \
534 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_5_S)
536 #define UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S 22
538 #define UD_SEND_WQE_U32_8_OPERATION_TYPE_S 16
539 #define UD_SEND_WQE_U32_8_OPERATION_TYPE_M \
540 (((1UL << 4) - 1) << UD_SEND_WQE_U32_8_OPERATION_TYPE_S)
542 #define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S 24
543 #define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M \
544 (((1UL << 6) - 1) << UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S)
546 #define UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S 31
548 #define UD_SEND_WQE_U32_16_DEST_QP_S 0
549 #define UD_SEND_WQE_U32_16_DEST_QP_M \
550 (((1UL << 24) - 1) << UD_SEND_WQE_U32_16_DEST_QP_S)
552 #define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S 24
553 #define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M \
554 (((1UL << 8) - 1) << UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S)
556 #define UD_SEND_WQE_U32_36_FLOW_LABEL_S 0
557 #define UD_SEND_WQE_U32_36_FLOW_LABEL_M \
558 (((1UL << 20) - 1) << UD_SEND_WQE_U32_36_FLOW_LABEL_S)
560 #define UD_SEND_WQE_U32_36_PRIORITY_S 20
561 #define UD_SEND_WQE_U32_36_PRIORITY_M \
562 (((1UL << 4) - 1) << UD_SEND_WQE_U32_36_PRIORITY_S)
564 #define UD_SEND_WQE_U32_36_SGID_INDEX_S 24
565 #define UD_SEND_WQE_U32_36_SGID_INDEX_M \
566 (((1UL << 8) - 1) << UD_SEND_WQE_U32_36_SGID_INDEX_S)
568 #define UD_SEND_WQE_U32_40_HOP_LIMIT_S 0
569 #define UD_SEND_WQE_U32_40_HOP_LIMIT_M \
570 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_HOP_LIMIT_S)
572 #define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S 8
573 #define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M \
574 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S)
576 struct hns_roce_sqp_context {
579 __le32 qp1c_bytes_12;
580 __le32 qp1c_bytes_16;
581 __le32 qp1c_bytes_20;
582 __le32 cur_rq_wqe_ba_l;
583 __le32 qp1c_bytes_28;
584 __le32 qp1c_bytes_32;
585 __le32 cur_sq_wqe_ba_l;
586 __le32 qp1c_bytes_40;
589 #define QP1C_BYTES_4_QP_STATE_S 0
590 #define QP1C_BYTES_4_QP_STATE_M \
591 (((1UL << 3) - 1) << QP1C_BYTES_4_QP_STATE_S)
593 #define QP1C_BYTES_4_SQ_WQE_SHIFT_S 8
594 #define QP1C_BYTES_4_SQ_WQE_SHIFT_M \
595 (((1UL << 4) - 1) << QP1C_BYTES_4_SQ_WQE_SHIFT_S)
597 #define QP1C_BYTES_4_RQ_WQE_SHIFT_S 12
598 #define QP1C_BYTES_4_RQ_WQE_SHIFT_M \
599 (((1UL << 4) - 1) << QP1C_BYTES_4_RQ_WQE_SHIFT_S)
601 #define QP1C_BYTES_4_PD_S 16
602 #define QP1C_BYTES_4_PD_M (((1UL << 16) - 1) << QP1C_BYTES_4_PD_S)
604 #define QP1C_BYTES_12_SQ_RQ_BT_H_S 0
605 #define QP1C_BYTES_12_SQ_RQ_BT_H_M \
606 (((1UL << 17) - 1) << QP1C_BYTES_12_SQ_RQ_BT_H_S)
608 #define QP1C_BYTES_16_RQ_HEAD_S 0
609 #define QP1C_BYTES_16_RQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_16_RQ_HEAD_S)
611 #define QP1C_BYTES_16_PORT_NUM_S 16
612 #define QP1C_BYTES_16_PORT_NUM_M \
613 (((1UL << 3) - 1) << QP1C_BYTES_16_PORT_NUM_S)
615 #define QP1C_BYTES_16_SIGNALING_TYPE_S 27
616 #define QP1C_BYTES_16_LOCAL_ENABLE_E2E_CREDIT_S 28
617 #define QP1C_BYTES_16_RQ_BA_FLG_S 29
618 #define QP1C_BYTES_16_SQ_BA_FLG_S 30
619 #define QP1C_BYTES_16_QP1_ERR_S 31
621 #define QP1C_BYTES_20_SQ_HEAD_S 0
622 #define QP1C_BYTES_20_SQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_20_SQ_HEAD_S)
624 #define QP1C_BYTES_20_PKEY_IDX_S 16
625 #define QP1C_BYTES_20_PKEY_IDX_M \
626 (((1UL << 16) - 1) << QP1C_BYTES_20_PKEY_IDX_S)
628 #define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S 0
629 #define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M \
630 (((1UL << 5) - 1) << QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S)
632 #define QP1C_BYTES_28_RQ_CUR_IDX_S 16
633 #define QP1C_BYTES_28_RQ_CUR_IDX_M \
634 (((1UL << 15) - 1) << QP1C_BYTES_28_RQ_CUR_IDX_S)
636 #define QP1C_BYTES_32_TX_CQ_NUM_S 0
637 #define QP1C_BYTES_32_TX_CQ_NUM_M \
638 (((1UL << 16) - 1) << QP1C_BYTES_32_TX_CQ_NUM_S)
640 #define QP1C_BYTES_32_RX_CQ_NUM_S 16
641 #define QP1C_BYTES_32_RX_CQ_NUM_M \
642 (((1UL << 16) - 1) << QP1C_BYTES_32_RX_CQ_NUM_S)
644 #define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S 0
645 #define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M \
646 (((1UL << 5) - 1) << QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S)
648 #define QP1C_BYTES_40_SQ_CUR_IDX_S 16
649 #define QP1C_BYTES_40_SQ_CUR_IDX_M \
650 (((1UL << 15) - 1) << QP1C_BYTES_40_SQ_CUR_IDX_S)
652 #define HNS_ROCE_WQE_INLINE (1UL<<31)
653 #define HNS_ROCE_WQE_SE (1UL<<30)
655 #define HNS_ROCE_WQE_SGE_NUM_BIT 24
656 #define HNS_ROCE_WQE_IMM (1UL<<23)
657 #define HNS_ROCE_WQE_FENCE (1UL<<21)
658 #define HNS_ROCE_WQE_CQ_NOTIFY (1UL<<20)
660 #define HNS_ROCE_WQE_OPCODE_SEND (0<<16)
661 #define HNS_ROCE_WQE_OPCODE_RDMA_READ (1<<16)
662 #define HNS_ROCE_WQE_OPCODE_RDMA_WRITE (2<<16)
663 #define HNS_ROCE_WQE_OPCODE_LOCAL_INV (4<<16)
664 #define HNS_ROCE_WQE_OPCODE_UD_SEND (7<<16)
665 #define HNS_ROCE_WQE_OPCODE_MASK (15<<16)
667 struct hns_roce_qp_context {
682 __le32 cur_rq_wqe_ba_l;
698 __le32 qpc_bytes_108;
699 __le32 qpc_bytes_112;
700 __le32 rx_cur_sq_wqe_ba_l;
701 __le32 qpc_bytes_120;
702 __le32 qpc_bytes_124;
703 __le32 qpc_bytes_128;
704 __le32 qpc_bytes_132;
705 __le32 qpc_bytes_136;
706 __le32 qpc_bytes_140;
707 __le32 qpc_bytes_144;
708 __le32 qpc_bytes_148;
713 __le32 qpc_bytes_156;
715 __le32 qpc_bytes_164;
716 __le32 qpc_bytes_168;
721 __le32 qpc_bytes_176;
722 __le32 qpc_bytes_180;
723 __le32 tx_cur_sq_wqe_ba_l;
724 __le32 qpc_bytes_188;
728 #define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S 0
729 #define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M \
730 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S)
732 #define QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S 3
733 #define QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S 4
734 #define QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S 5
735 #define QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S 6
736 #define QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S 7
738 #define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S 8
739 #define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M \
740 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S)
742 #define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S 12
743 #define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M \
744 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S)
746 #define QP_CONTEXT_QPC_BYTES_4_PD_S 16
747 #define QP_CONTEXT_QPC_BYTES_4_PD_M \
748 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_4_PD_S)
750 #define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S 0
751 #define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M \
752 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S)
754 #define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S 16
755 #define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M \
756 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S)
758 #define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S 0
759 #define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M \
760 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S)
762 #define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S 16
763 #define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M \
764 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S)
766 #define QP_CONTEXT_QPC_BYTES_16_QP_NUM_S 0
767 #define QP_CONTEXT_QPC_BYTES_16_QP_NUM_M \
768 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_16_QP_NUM_S)
770 #define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S 0
771 #define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M \
772 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S)
774 #define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S 18
775 #define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M \
776 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S)
778 #define QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S 23
780 #define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S 0
781 #define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M \
782 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S)
784 #define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S 18
785 #define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M \
786 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S)
788 #define QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S 20
789 #define QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S 21
790 #define QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S 22
791 #define QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S 23
793 #define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S 24
794 #define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M \
795 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S)
797 #define QP_CONTEXT_QPC_BYTES_36_DEST_QP_S 0
798 #define QP_CONTEXT_QPC_BYTES_36_DEST_QP_M \
799 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_36_DEST_QP_S)
801 #define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S 24
802 #define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M \
803 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S)
805 #define QP_CONTEXT_QPC_BYTES_44_DMAC_H_S 0
806 #define QP_CONTEXT_QPC_BYTES_44_DMAC_H_M \
807 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_44_DMAC_H_S)
809 #define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S 16
810 #define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M \
811 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S)
813 #define QP_CONTEXT_QPC_BYTES_44_HOPLMT_S 24
814 #define QP_CONTEXT_QPC_BYTES_44_HOPLMT_M \
815 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_HOPLMT_S)
817 #define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S 0
818 #define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M \
819 (((1UL << 20) - 1) << QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S)
821 #define QP_CONTEXT_QPC_BYTES_48_TCLASS_S 20
822 #define QP_CONTEXT_QPC_BYTES_48_TCLASS_M \
823 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_48_TCLASS_S)
825 #define QP_CONTEXT_QPC_BYTES_48_MTU_S 28
826 #define QP_CONTEXT_QPC_BYTES_48_MTU_M \
827 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_48_MTU_S)
829 #define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S 0
830 #define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M \
831 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S)
833 #define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S 16
834 #define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M \
835 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S)
837 #define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S 0
838 #define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M \
839 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S)
841 #define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S 8
842 #define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M \
843 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S)
845 #define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S 0
846 #define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M \
847 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S)
849 #define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S 24
850 #define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M \
851 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S)
853 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S 0
854 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M \
855 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S)
857 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S 24
858 #define QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S 25
860 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S 26
861 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M \
862 (((1UL << 2) - 1) << \
863 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S)
865 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S 29
866 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M \
867 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S)
869 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S 0
870 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M \
871 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S)
873 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S 24
874 #define QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S 25
876 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S 0
877 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M \
878 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S)
880 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S 24
881 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M \
882 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S)
884 #define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S 0
885 #define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M \
886 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S)
888 #define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S 0
889 #define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M \
890 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S)
892 #define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S 16
893 #define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M \
894 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S)
896 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S 0
897 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M \
898 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S)
900 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S 24
902 #define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S 25
903 #define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M \
904 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S)
906 #define QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S 27
908 #define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S 0
909 #define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M \
910 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S)
912 #define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S 24
913 #define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M \
914 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S)
916 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S 0
917 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M \
918 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S)
920 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S 24
921 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M \
922 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S)
924 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S 0
925 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M \
926 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S)
928 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S 16
929 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M \
930 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S)
932 #define QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S 31
934 #define QP_CONTEXT_QPC_BYTES_144_QP_STATE_S 0
935 #define QP_CONTEXT_QPC_BYTES_144_QP_STATE_M \
936 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_144_QP_STATE_S)
938 #define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S 0
939 #define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M \
940 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S)
942 #define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S 2
943 #define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M \
944 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S)
946 #define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S 5
947 #define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M \
948 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S)
950 #define QP_CONTEXT_QPC_BYTES_148_LSN_S 8
951 #define QP_CONTEXT_QPC_BYTES_148_LSN_M \
952 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_148_LSN_S)
954 #define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S 0
955 #define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M \
956 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S)
958 #define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S 3
959 #define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M \
960 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S)
962 #define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S 8
963 #define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M \
964 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S)
966 #define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S 11
967 #define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M \
968 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S)
970 #define QP_CONTEXT_QPC_BYTES_156_SL_S 14
971 #define QP_CONTEXT_QPC_BYTES_156_SL_M \
972 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_SL_S)
974 #define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S 16
975 #define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M \
976 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S)
978 #define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S 24
979 #define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M \
980 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S)
982 #define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S 0
983 #define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M \
984 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S)
986 #define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S 24
987 #define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M \
988 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S)
990 #define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S 0
991 #define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M \
992 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S)
994 #define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S 24
995 #define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M \
996 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S)
998 #define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S 26
999 #define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M \
1000 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S)
1002 #define QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S 28
1003 #define QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S 29
1004 #define QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S 30
1006 #define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S 0
1007 #define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M \
1008 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S)
1010 #define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S 16
1011 #define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M \
1012 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S)
1014 #define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S 0
1015 #define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M \
1016 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S)
1018 #define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S 16
1019 #define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M \
1020 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S)
1022 #define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S 0
1023 #define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M \
1024 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S)
1026 #define QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S 8
1028 #define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S 16
1029 #define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M \
1030 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S)
1032 #define STATUS_MASK 0xff
1033 #define GO_BIT_TIMEOUT_MSECS 10000
1034 #define HCR_STATUS_OFFSET 0x18
1035 #define HCR_GO_BIT 15
1037 struct hns_roce_rq_db {
1042 #define RQ_DOORBELL_U32_4_RQ_HEAD_S 0
1043 #define RQ_DOORBELL_U32_4_RQ_HEAD_M \
1044 (((1UL << 15) - 1) << RQ_DOORBELL_U32_4_RQ_HEAD_S)
1046 #define RQ_DOORBELL_U32_8_QPN_S 0
1047 #define RQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << RQ_DOORBELL_U32_8_QPN_S)
1049 #define RQ_DOORBELL_U32_8_CMD_S 28
1050 #define RQ_DOORBELL_U32_8_CMD_M (((1UL << 3) - 1) << RQ_DOORBELL_U32_8_CMD_S)
1052 #define RQ_DOORBELL_U32_8_HW_SYNC_S 31
1054 struct hns_roce_sq_db {
1059 #define SQ_DOORBELL_U32_4_SQ_HEAD_S 0
1060 #define SQ_DOORBELL_U32_4_SQ_HEAD_M \
1061 (((1UL << 15) - 1) << SQ_DOORBELL_U32_4_SQ_HEAD_S)
1063 #define SQ_DOORBELL_U32_4_SL_S 16
1064 #define SQ_DOORBELL_U32_4_SL_M \
1065 (((1UL << 2) - 1) << SQ_DOORBELL_U32_4_SL_S)
1067 #define SQ_DOORBELL_U32_4_PORT_S 18
1068 #define SQ_DOORBELL_U32_4_PORT_M (((1UL << 3) - 1) << SQ_DOORBELL_U32_4_PORT_S)
1070 #define SQ_DOORBELL_U32_8_QPN_S 0
1071 #define SQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << SQ_DOORBELL_U32_8_QPN_S)
1073 #define SQ_DOORBELL_HW_SYNC_S 31
1075 struct hns_roce_ext_db {
1078 struct hns_roce_buf_list *sdb_buf_list;
1079 struct hns_roce_buf_list *odb_buf_list;
1082 struct hns_roce_db_table {
1085 struct hns_roce_ext_db *ext_db;
1088 #define HW_SYNC_SLEEP_TIME_INTERVAL 20
1089 #define HW_SYNC_TIMEOUT_MSECS (25 * HW_SYNC_SLEEP_TIME_INTERVAL)
1090 #define BT_CMD_SYNC_SHIFT 31
1091 #define HNS_ROCE_BA_SIZE (32 * 4096)
1093 struct hns_roce_bt_table {
1094 struct hns_roce_buf_list qpc_buf;
1095 struct hns_roce_buf_list mtpt_buf;
1096 struct hns_roce_buf_list cqc_buf;
1099 struct hns_roce_tptr_table {
1100 struct hns_roce_buf_list tptr_buf;
1103 struct hns_roce_qp_work {
1104 struct work_struct work;
1105 struct ib_device *ib_dev;
1106 struct hns_roce_qp *qp;
1113 struct hns_roce_mr_free_work {
1114 struct work_struct work;
1115 struct ib_device *ib_dev;
1116 struct completion *comp;
1121 struct hns_roce_recreate_lp_qp_work {
1122 struct work_struct work;
1123 struct ib_device *ib_dev;
1124 struct completion *comp;
1128 struct hns_roce_free_mr {
1129 struct workqueue_struct *free_mr_wq;
1130 struct hns_roce_qp *mr_free_qp[HNS_ROCE_V1_RESV_QP];
1131 struct hns_roce_cq *mr_free_cq;
1132 struct hns_roce_pd *mr_free_pd;
1135 struct hns_roce_v1_priv {
1136 struct hns_roce_db_table db_table;
1137 struct hns_roce_raq_table raq_table;
1138 struct hns_roce_bt_table bt_table;
1139 struct hns_roce_tptr_table tptr_table;
1140 struct hns_roce_free_mr free_mr;
1143 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);
1144 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1145 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata);