2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/platform_device.h>
34 #include <linux/acpi.h>
35 #include <linux/etherdevice.h>
36 #include <linux/interrupt.h>
38 #include <linux/of_platform.h>
39 #include <rdma/ib_umem.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_cmd.h"
43 #include "hns_roce_hem.h"
44 #include "hns_roce_hw_v1.h"
46 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
48 dseg->lkey = cpu_to_le32(sg->lkey);
49 dseg->addr = cpu_to_le64(sg->addr);
50 dseg->len = cpu_to_le32(sg->length);
53 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
56 rseg->raddr = cpu_to_le64(remote_addr);
57 rseg->rkey = cpu_to_le32(rkey);
61 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
62 const struct ib_send_wr *wr,
63 const struct ib_send_wr **bad_wr)
65 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
66 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
67 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
68 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
69 struct hns_roce_wqe_data_seg *dseg = NULL;
70 struct hns_roce_qp *qp = to_hr_qp(ibqp);
71 struct device *dev = &hr_dev->pdev->dev;
72 struct hns_roce_sq_db sq_db;
73 int ps_opcode = 0, i = 0;
74 unsigned long flags = 0;
83 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
84 ibqp->qp_type != IB_QPT_RC)) {
85 dev_err(dev, "un-supported QP type\n");
90 spin_lock_irqsave(&qp->sq.lock, flags);
91 ind = qp->sq_next_wqe;
92 for (nreq = 0; wr; ++nreq, wr = wr->next) {
93 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
99 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
100 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
101 wr->num_sge, qp->sq.max_gs);
107 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
108 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
111 /* Corresponding to the RC and RD type wqe process separately */
112 if (ibqp->qp_type == IB_QPT_GSI) {
114 roce_set_field(ud_sq_wqe->dmac_h,
115 UD_SEND_WQE_U32_4_DMAC_0_M,
116 UD_SEND_WQE_U32_4_DMAC_0_S,
118 roce_set_field(ud_sq_wqe->dmac_h,
119 UD_SEND_WQE_U32_4_DMAC_1_M,
120 UD_SEND_WQE_U32_4_DMAC_1_S,
122 roce_set_field(ud_sq_wqe->dmac_h,
123 UD_SEND_WQE_U32_4_DMAC_2_M,
124 UD_SEND_WQE_U32_4_DMAC_2_S,
126 roce_set_field(ud_sq_wqe->dmac_h,
127 UD_SEND_WQE_U32_4_DMAC_3_M,
128 UD_SEND_WQE_U32_4_DMAC_3_S,
131 roce_set_field(ud_sq_wqe->u32_8,
132 UD_SEND_WQE_U32_8_DMAC_4_M,
133 UD_SEND_WQE_U32_8_DMAC_4_S,
135 roce_set_field(ud_sq_wqe->u32_8,
136 UD_SEND_WQE_U32_8_DMAC_5_M,
137 UD_SEND_WQE_U32_8_DMAC_5_S,
140 smac = (u8 *)hr_dev->dev_addr[qp->port];
141 loopback = ether_addr_equal_unaligned(ah->av.mac,
143 roce_set_bit(ud_sq_wqe->u32_8,
144 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
147 roce_set_field(ud_sq_wqe->u32_8,
148 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
149 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
150 HNS_ROCE_WQE_OPCODE_SEND);
151 roce_set_field(ud_sq_wqe->u32_8,
152 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
153 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
155 roce_set_bit(ud_sq_wqe->u32_8,
156 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
159 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
160 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
161 (wr->send_flags & IB_SEND_SOLICITED ?
162 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
163 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
164 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
166 roce_set_field(ud_sq_wqe->u32_16,
167 UD_SEND_WQE_U32_16_DEST_QP_M,
168 UD_SEND_WQE_U32_16_DEST_QP_S,
169 ud_wr(wr)->remote_qpn);
170 roce_set_field(ud_sq_wqe->u32_16,
171 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
172 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
175 roce_set_field(ud_sq_wqe->u32_36,
176 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
177 UD_SEND_WQE_U32_36_FLOW_LABEL_S,
178 ah->av.sl_tclass_flowlabel &
179 HNS_ROCE_FLOW_LABEL_MASK);
180 roce_set_field(ud_sq_wqe->u32_36,
181 UD_SEND_WQE_U32_36_PRIORITY_M,
182 UD_SEND_WQE_U32_36_PRIORITY_S,
183 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
185 roce_set_field(ud_sq_wqe->u32_36,
186 UD_SEND_WQE_U32_36_SGID_INDEX_M,
187 UD_SEND_WQE_U32_36_SGID_INDEX_S,
188 hns_get_gid_index(hr_dev, qp->phy_port,
191 roce_set_field(ud_sq_wqe->u32_40,
192 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
193 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
195 roce_set_field(ud_sq_wqe->u32_40,
196 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
197 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
198 ah->av.sl_tclass_flowlabel >>
199 HNS_ROCE_TCLASS_SHIFT);
201 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
204 cpu_to_le32((u32)wr->sg_list[0].addr);
206 cpu_to_le32((wr->sg_list[0].addr) >> 32);
208 cpu_to_le32(wr->sg_list[0].lkey);
211 cpu_to_le32((u32)wr->sg_list[1].addr);
213 cpu_to_le32((wr->sg_list[1].addr) >> 32);
215 cpu_to_le32(wr->sg_list[1].lkey);
217 } else if (ibqp->qp_type == IB_QPT_RC) {
221 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
222 for (i = 0; i < wr->num_sge; i++)
223 tmp_len += wr->sg_list[i].length;
226 cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
231 switch (wr->opcode) {
232 case IB_WR_SEND_WITH_IMM:
233 case IB_WR_RDMA_WRITE_WITH_IMM:
234 ctrl->imm_data = wr->ex.imm_data;
236 case IB_WR_SEND_WITH_INV:
238 cpu_to_le32(wr->ex.invalidate_rkey);
245 /*Ctrl field, ctrl set type: sig, solic, imm, fence */
246 /* SO wait for conforming application scenarios */
247 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
248 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
249 (wr->send_flags & IB_SEND_SOLICITED ?
250 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
251 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
252 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
253 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
254 (wr->send_flags & IB_SEND_FENCE ?
255 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
257 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
259 switch (wr->opcode) {
260 case IB_WR_RDMA_READ:
261 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
262 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
265 case IB_WR_RDMA_WRITE:
266 case IB_WR_RDMA_WRITE_WITH_IMM:
267 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
268 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
272 case IB_WR_SEND_WITH_INV:
273 case IB_WR_SEND_WITH_IMM:
274 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
276 case IB_WR_LOCAL_INV:
278 case IB_WR_ATOMIC_CMP_AND_SWP:
279 case IB_WR_ATOMIC_FETCH_AND_ADD:
282 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
285 ctrl->flag |= cpu_to_le32(ps_opcode);
286 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
289 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
290 if (le32_to_cpu(ctrl->msg_length) >
291 hr_dev->caps.max_sq_inline) {
294 dev_err(dev, "inline len(1-%d)=%d, illegal",
296 hr_dev->caps.max_sq_inline);
299 for (i = 0; i < wr->num_sge; i++) {
300 memcpy(wqe, ((void *) (uintptr_t)
301 wr->sg_list[i].addr),
302 wr->sg_list[i].length);
303 wqe += wr->sg_list[i].length;
305 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
308 for (i = 0; i < wr->num_sge; i++)
309 set_data_seg(dseg + i, wr->sg_list + i);
311 ctrl->flag |= cpu_to_le32(wr->num_sge <<
312 HNS_ROCE_WQE_SGE_NUM_BIT);
327 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
328 SQ_DOORBELL_U32_4_SQ_HEAD_S,
329 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
330 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
331 SQ_DOORBELL_U32_4_SL_S, qp->sl);
332 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
333 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
334 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
335 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
336 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
338 doorbell[0] = le32_to_cpu(sq_db.u32_4);
339 doorbell[1] = le32_to_cpu(sq_db.u32_8);
341 hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l);
342 qp->sq_next_wqe = ind;
345 spin_unlock_irqrestore(&qp->sq.lock, flags);
350 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
351 const struct ib_recv_wr *wr,
352 const struct ib_recv_wr **bad_wr)
359 unsigned long flags = 0;
360 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
361 struct hns_roce_wqe_data_seg *scat = NULL;
362 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
363 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
364 struct device *dev = &hr_dev->pdev->dev;
365 struct hns_roce_rq_db rq_db;
366 uint32_t doorbell[2] = {0};
368 spin_lock_irqsave(&hr_qp->rq.lock, flags);
369 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
371 for (nreq = 0; wr; ++nreq, wr = wr->next) {
372 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
373 hr_qp->ibqp.recv_cq)) {
379 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
380 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
381 wr->num_sge, hr_qp->rq.max_gs);
387 ctrl = get_recv_wqe(hr_qp, ind);
389 roce_set_field(ctrl->rwqe_byte_12,
390 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
391 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
394 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
396 for (i = 0; i < wr->num_sge; i++)
397 set_data_seg(scat + i, wr->sg_list + i);
399 hr_qp->rq.wrid[ind] = wr->wr_id;
401 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
406 hr_qp->rq.head += nreq;
410 if (ibqp->qp_type == IB_QPT_GSI) {
413 /* SW update GSI rq header */
414 reg_val = roce_read(to_hr_dev(ibqp->device),
415 ROCEE_QP1C_CFG3_0_REG +
416 QP1C_CFGN_OFFSET * hr_qp->phy_port);
417 tmp = cpu_to_le32(reg_val);
419 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
420 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
422 reg_val = le32_to_cpu(tmp);
423 roce_write(to_hr_dev(ibqp->device),
424 ROCEE_QP1C_CFG3_0_REG +
425 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
430 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
431 RQ_DOORBELL_U32_4_RQ_HEAD_S,
433 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
434 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
435 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
436 RQ_DOORBELL_U32_8_CMD_S, 1);
437 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
440 doorbell[0] = le32_to_cpu(rq_db.u32_4);
441 doorbell[1] = le32_to_cpu(rq_db.u32_8);
443 hns_roce_write64_k((__le32 *)doorbell,
447 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
452 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
453 int sdb_mode, int odb_mode)
458 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
459 tmp = cpu_to_le32(val);
460 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
461 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
462 val = le32_to_cpu(tmp);
463 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
466 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
472 /* Configure SDB/ODB extend mode */
473 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
474 tmp = cpu_to_le32(val);
475 roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
476 roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
477 val = le32_to_cpu(tmp);
478 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
481 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
488 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
489 tmp = cpu_to_le32(val);
490 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
491 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
492 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
493 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
494 val = le32_to_cpu(tmp);
495 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
498 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
505 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
506 tmp = cpu_to_le32(val);
507 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
508 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
509 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
510 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
511 val = le32_to_cpu(tmp);
512 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
515 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
518 struct device *dev = &hr_dev->pdev->dev;
519 struct hns_roce_v1_priv *priv;
520 struct hns_roce_db_table *db;
521 dma_addr_t sdb_dma_addr;
525 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
526 db = &priv->db_table;
528 /* Configure extend SDB threshold */
529 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
530 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
532 /* Configure extend SDB base addr */
533 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
534 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
536 /* Configure extend SDB depth */
537 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
538 tmp = cpu_to_le32(val);
539 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
540 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
541 db->ext_db->esdb_dep);
543 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
544 * using 4K page, and shift more 32 because of
545 * caculating the high 32 bit value evaluated to hardware.
547 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
548 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
549 val = le32_to_cpu(tmp);
550 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
552 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
553 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
554 ext_sdb_alept, ext_sdb_alful);
557 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
560 struct device *dev = &hr_dev->pdev->dev;
561 struct hns_roce_v1_priv *priv;
562 struct hns_roce_db_table *db;
563 dma_addr_t odb_dma_addr;
567 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
568 db = &priv->db_table;
570 /* Configure extend ODB threshold */
571 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
572 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
574 /* Configure extend ODB base addr */
575 odb_dma_addr = db->ext_db->odb_buf_list->map;
576 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
578 /* Configure extend ODB depth */
579 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
580 tmp = cpu_to_le32(val);
581 roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
582 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
583 db->ext_db->eodb_dep);
584 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
585 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
586 db->ext_db->eodb_dep);
587 val = le32_to_cpu(tmp);
588 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
590 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
591 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
592 ext_odb_alept, ext_odb_alful);
595 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
598 struct device *dev = &hr_dev->pdev->dev;
599 struct hns_roce_v1_priv *priv;
600 struct hns_roce_db_table *db;
601 dma_addr_t sdb_dma_addr;
602 dma_addr_t odb_dma_addr;
605 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
606 db = &priv->db_table;
608 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
613 db->ext_db->sdb_buf_list = kmalloc(
614 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
615 if (!db->ext_db->sdb_buf_list) {
617 goto ext_sdb_buf_fail_out;
620 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
621 HNS_ROCE_V1_EXT_SDB_SIZE,
622 &sdb_dma_addr, GFP_KERNEL);
623 if (!db->ext_db->sdb_buf_list->buf) {
625 goto alloc_sq_db_buf_fail;
627 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
629 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
630 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
631 HNS_ROCE_V1_EXT_SDB_ALFUL);
633 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
634 HNS_ROCE_V1_SDB_ALFUL);
637 db->ext_db->odb_buf_list = kmalloc(
638 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
639 if (!db->ext_db->odb_buf_list) {
641 goto ext_odb_buf_fail_out;
644 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
645 HNS_ROCE_V1_EXT_ODB_SIZE,
646 &odb_dma_addr, GFP_KERNEL);
647 if (!db->ext_db->odb_buf_list->buf) {
649 goto alloc_otr_db_buf_fail;
651 db->ext_db->odb_buf_list->map = odb_dma_addr;
653 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
654 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
655 HNS_ROCE_V1_EXT_ODB_ALFUL);
657 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
658 HNS_ROCE_V1_ODB_ALFUL);
660 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
664 alloc_otr_db_buf_fail:
665 kfree(db->ext_db->odb_buf_list);
667 ext_odb_buf_fail_out:
669 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
670 db->ext_db->sdb_buf_list->buf,
671 db->ext_db->sdb_buf_list->map);
674 alloc_sq_db_buf_fail:
676 kfree(db->ext_db->sdb_buf_list);
678 ext_sdb_buf_fail_out:
683 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
686 struct device *dev = &hr_dev->pdev->dev;
687 struct ib_qp_init_attr init_attr;
690 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
691 init_attr.qp_type = IB_QPT_RC;
692 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
693 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
694 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
696 qp = hns_roce_create_qp(pd, &init_attr, NULL);
698 dev_err(dev, "Create loop qp for mr free failed!");
705 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
707 struct hns_roce_caps *caps = &hr_dev->caps;
708 struct device *dev = &hr_dev->pdev->dev;
709 struct ib_cq_init_attr cq_init_attr;
710 struct hns_roce_free_mr *free_mr;
711 struct ib_qp_attr attr = { 0 };
712 struct hns_roce_v1_priv *priv;
713 struct hns_roce_qp *hr_qp;
714 struct ib_device *ibdev;
722 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
727 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
728 free_mr = &priv->free_mr;
730 /* Reserved cq for loop qp */
731 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
732 cq_init_attr.comp_vector = 0;
733 cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL);
735 dev_err(dev, "Create cq for reserved loop qp failed!");
738 free_mr->mr_free_cq = to_hr_cq(cq);
739 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
740 free_mr->mr_free_cq->ib_cq.uobject = NULL;
741 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
742 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
743 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
744 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
746 ibdev = &hr_dev->ib_dev;
747 pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
749 goto alloc_mem_failed;
752 ret = hns_roce_alloc_pd(pd, NULL);
754 goto alloc_pd_failed;
756 free_mr->mr_free_pd = to_hr_pd(pd);
757 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
758 free_mr->mr_free_pd->ibpd.uobject = NULL;
759 free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
760 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
762 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
764 attr.min_rnr_timer = 0;
765 /* Disable read ability */
766 attr.max_dest_rd_atomic = 0;
767 attr.max_rd_atomic = 0;
768 /* Use arbitrary values as rq_psn and sq_psn */
769 attr.rq_psn = 0x0808;
770 attr.sq_psn = 0x0808;
774 attr.path_mtu = IB_MTU_256;
775 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
776 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
777 rdma_ah_set_static_rate(&attr.ah_attr, 3);
779 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
780 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
781 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
782 (i % HNS_ROCE_MAX_PORTS);
783 sl = i / HNS_ROCE_MAX_PORTS;
785 for (j = 0; j < caps->num_ports; j++) {
786 if (hr_dev->iboe.phy_port[j] == phy_port) {
796 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
797 if (!free_mr->mr_free_qp[i]) {
798 dev_err(dev, "Create loop qp failed!\n");
800 goto create_lp_qp_failed;
802 hr_qp = free_mr->mr_free_qp[i];
805 hr_qp->phy_port = phy_port;
806 hr_qp->ibqp.qp_type = IB_QPT_RC;
807 hr_qp->ibqp.device = &hr_dev->ib_dev;
808 hr_qp->ibqp.uobject = NULL;
809 atomic_set(&hr_qp->ibqp.usecnt, 0);
811 hr_qp->ibqp.recv_cq = cq;
812 hr_qp->ibqp.send_cq = cq;
814 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
815 rdma_ah_set_sl(&attr.ah_attr, sl);
816 attr.port_num = port + 1;
818 attr.dest_qp_num = hr_qp->qpn;
819 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
820 hr_dev->dev_addr[port],
823 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
824 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
825 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
829 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
831 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
832 IB_QPS_RESET, IB_QPS_INIT);
834 dev_err(dev, "modify qp failed(%d)!\n", ret);
835 goto create_lp_qp_failed;
838 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
839 IB_QPS_INIT, IB_QPS_RTR);
841 dev_err(dev, "modify qp failed(%d)!\n", ret);
842 goto create_lp_qp_failed;
845 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
846 IB_QPS_RTR, IB_QPS_RTS);
848 dev_err(dev, "modify qp failed(%d)!\n", ret);
849 goto create_lp_qp_failed;
856 for (i -= 1; i >= 0; i--) {
857 hr_qp = free_mr->mr_free_qp[i];
858 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
859 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
862 hns_roce_dealloc_pd(pd, NULL);
868 if (hns_roce_ib_destroy_cq(cq, NULL))
869 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
874 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
876 struct device *dev = &hr_dev->pdev->dev;
877 struct hns_roce_free_mr *free_mr;
878 struct hns_roce_v1_priv *priv;
879 struct hns_roce_qp *hr_qp;
883 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
884 free_mr = &priv->free_mr;
886 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
887 hr_qp = free_mr->mr_free_qp[i];
891 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
893 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
897 ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
899 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
901 hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
902 kfree(&free_mr->mr_free_pd->ibpd);
905 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
907 struct device *dev = &hr_dev->pdev->dev;
908 struct hns_roce_v1_priv *priv;
909 struct hns_roce_db_table *db;
916 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
917 db = &priv->db_table;
919 memset(db, 0, sizeof(*db));
921 /* Default DB mode */
922 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
923 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
924 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
925 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
927 db->sdb_ext_mod = sdb_ext_mod;
928 db->odb_ext_mod = odb_ext_mod;
931 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
933 dev_err(dev, "Failed in extend DB configuration.\n");
937 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
942 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
944 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
945 struct hns_roce_dev *hr_dev;
947 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
949 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
951 hns_roce_v1_release_lp_qp(hr_dev);
953 if (hns_roce_v1_rsv_lp_qp(hr_dev))
954 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
956 if (lp_qp_work->comp_flag)
957 complete(lp_qp_work->comp);
962 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
964 struct device *dev = &hr_dev->pdev->dev;
965 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
966 struct hns_roce_free_mr *free_mr;
967 struct hns_roce_v1_priv *priv;
968 struct completion comp;
970 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
972 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
973 free_mr = &priv->free_mr;
975 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
980 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
982 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
983 lp_qp_work->comp = ∁
984 lp_qp_work->comp_flag = 1;
986 init_completion(lp_qp_work->comp);
988 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
990 while (time_before_eq(jiffies, end)) {
991 if (try_wait_for_completion(&comp))
993 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
996 lp_qp_work->comp_flag = 0;
997 if (try_wait_for_completion(&comp))
1000 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
1004 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
1006 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1007 struct device *dev = &hr_dev->pdev->dev;
1008 struct ib_send_wr send_wr;
1009 const struct ib_send_wr *bad_wr;
1012 memset(&send_wr, 0, sizeof(send_wr));
1013 send_wr.next = NULL;
1014 send_wr.num_sge = 0;
1015 send_wr.send_flags = 0;
1016 send_wr.sg_list = NULL;
1017 send_wr.wr_id = (unsigned long long)&send_wr;
1018 send_wr.opcode = IB_WR_RDMA_WRITE;
1020 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1022 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1029 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1031 struct hns_roce_mr_free_work *mr_work;
1032 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1033 struct hns_roce_free_mr *free_mr;
1034 struct hns_roce_cq *mr_free_cq;
1035 struct hns_roce_v1_priv *priv;
1036 struct hns_roce_dev *hr_dev;
1037 struct hns_roce_mr *hr_mr;
1038 struct hns_roce_qp *hr_qp;
1041 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1046 mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1047 hr_mr = (struct hns_roce_mr *)mr_work->mr;
1048 hr_dev = to_hr_dev(mr_work->ib_dev);
1049 dev = &hr_dev->pdev->dev;
1051 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1052 free_mr = &priv->free_mr;
1053 mr_free_cq = free_mr->mr_free_cq;
1055 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1056 hr_qp = free_mr->mr_free_qp[i];
1061 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1064 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1071 dev_err(dev, "Reserved loop qp is absent!\n");
1076 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1077 if (ret < 0 && hr_qp) {
1079 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1080 hr_qp->qpn, ret, hr_mr->key, ne);
1084 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1085 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1086 } while (ne && time_before_eq(jiffies, end));
1090 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1094 if (mr_work->comp_flag)
1095 complete(mr_work->comp);
1099 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1100 struct hns_roce_mr *mr, struct ib_udata *udata)
1102 struct device *dev = &hr_dev->pdev->dev;
1103 struct hns_roce_mr_free_work *mr_work;
1104 struct hns_roce_free_mr *free_mr;
1105 struct hns_roce_v1_priv *priv;
1106 struct completion comp;
1108 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1109 unsigned long start = jiffies;
1113 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1114 free_mr = &priv->free_mr;
1117 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1118 & (hr_dev->caps.num_mtpts - 1)))
1119 dev_warn(dev, "HW2SW_MPT failed!\n");
1122 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1128 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1130 mr_work->ib_dev = &(hr_dev->ib_dev);
1131 mr_work->comp = ∁
1132 mr_work->comp_flag = 1;
1133 mr_work->mr = (void *)mr;
1134 init_completion(mr_work->comp);
1136 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1138 while (time_before_eq(jiffies, end)) {
1139 if (try_wait_for_completion(&comp))
1141 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1144 mr_work->comp_flag = 0;
1145 if (try_wait_for_completion(&comp))
1148 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1152 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1153 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1155 if (mr->size != ~0ULL) {
1156 npages = ib_umem_page_count(mr->umem);
1157 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1161 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1162 key_to_hw_index(mr->key), 0);
1165 ib_umem_release(mr->umem);
1172 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1174 struct device *dev = &hr_dev->pdev->dev;
1175 struct hns_roce_v1_priv *priv;
1176 struct hns_roce_db_table *db;
1178 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1179 db = &priv->db_table;
1181 if (db->sdb_ext_mod) {
1182 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1183 db->ext_db->sdb_buf_list->buf,
1184 db->ext_db->sdb_buf_list->map);
1185 kfree(db->ext_db->sdb_buf_list);
1188 if (db->odb_ext_mod) {
1189 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1190 db->ext_db->odb_buf_list->buf,
1191 db->ext_db->odb_buf_list->map);
1192 kfree(db->ext_db->odb_buf_list);
1198 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1205 struct hns_roce_v1_priv *priv;
1206 struct hns_roce_raq_table *raq;
1207 struct device *dev = &hr_dev->pdev->dev;
1209 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1210 raq = &priv->raq_table;
1212 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1213 if (!raq->e_raq_buf)
1216 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1218 if (!raq->e_raq_buf->buf) {
1220 goto err_dma_alloc_raq;
1222 raq->e_raq_buf->map = addr;
1224 /* Configure raq extended address. 48bit 4K align*/
1225 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1227 /* Configure raq_shift */
1228 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1229 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1230 tmp = cpu_to_le32(val);
1231 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1232 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1234 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1235 * using 4K page, and shift more 32 because of
1236 * caculating the high 32 bit value evaluated to hardware.
1238 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1239 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1240 raq->e_raq_buf->map >> 44);
1241 val = le32_to_cpu(tmp);
1242 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1243 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1245 /* Configure raq threshold */
1246 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1247 tmp = cpu_to_le32(val);
1248 roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1249 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1250 HNS_ROCE_V1_EXT_RAQ_WF);
1251 val = le32_to_cpu(tmp);
1252 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1253 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1255 /* Enable extend raq */
1256 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1257 tmp = cpu_to_le32(val);
1259 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1260 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1261 POL_TIME_INTERVAL_VAL);
1262 roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1264 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1265 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1268 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1269 val = le32_to_cpu(tmp);
1270 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1271 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1273 /* Enable raq drop */
1274 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1275 tmp = cpu_to_le32(val);
1276 roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1277 val = le32_to_cpu(tmp);
1278 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1279 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1284 kfree(raq->e_raq_buf);
1288 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1290 struct device *dev = &hr_dev->pdev->dev;
1291 struct hns_roce_v1_priv *priv;
1292 struct hns_roce_raq_table *raq;
1294 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1295 raq = &priv->raq_table;
1297 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1298 raq->e_raq_buf->map);
1299 kfree(raq->e_raq_buf);
1302 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1308 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1309 /* Open all ports */
1310 tmp = cpu_to_le32(val);
1311 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1312 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1314 val = le32_to_cpu(tmp);
1315 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1317 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1318 /* Close all ports */
1319 tmp = cpu_to_le32(val);
1320 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1321 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1322 val = le32_to_cpu(tmp);
1323 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1327 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1329 struct device *dev = &hr_dev->pdev->dev;
1330 struct hns_roce_v1_priv *priv;
1333 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1335 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1336 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1338 if (!priv->bt_table.qpc_buf.buf)
1341 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1342 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1344 if (!priv->bt_table.mtpt_buf.buf) {
1346 goto err_failed_alloc_mtpt_buf;
1349 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1350 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1352 if (!priv->bt_table.cqc_buf.buf) {
1354 goto err_failed_alloc_cqc_buf;
1359 err_failed_alloc_cqc_buf:
1360 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1361 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1363 err_failed_alloc_mtpt_buf:
1364 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1365 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1370 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1372 struct device *dev = &hr_dev->pdev->dev;
1373 struct hns_roce_v1_priv *priv;
1375 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1377 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1378 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1380 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1381 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1383 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1384 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1387 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1389 struct device *dev = &hr_dev->pdev->dev;
1390 struct hns_roce_buf_list *tptr_buf;
1391 struct hns_roce_v1_priv *priv;
1393 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1394 tptr_buf = &priv->tptr_table.tptr_buf;
1397 * This buffer will be used for CQ's tptr(tail pointer), also
1398 * named ci(customer index). Every CQ will use 2 bytes to save
1399 * cqe ci in hip06. Hardware will read this area to get new ci
1400 * when the queue is almost full.
1402 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1403 &tptr_buf->map, GFP_KERNEL);
1407 hr_dev->tptr_dma_addr = tptr_buf->map;
1408 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1413 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1415 struct device *dev = &hr_dev->pdev->dev;
1416 struct hns_roce_buf_list *tptr_buf;
1417 struct hns_roce_v1_priv *priv;
1419 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1420 tptr_buf = &priv->tptr_table.tptr_buf;
1422 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1423 tptr_buf->buf, tptr_buf->map);
1426 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1428 struct device *dev = &hr_dev->pdev->dev;
1429 struct hns_roce_free_mr *free_mr;
1430 struct hns_roce_v1_priv *priv;
1433 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1434 free_mr = &priv->free_mr;
1436 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1437 if (!free_mr->free_mr_wq) {
1438 dev_err(dev, "Create free mr workqueue failed!\n");
1442 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1444 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1445 flush_workqueue(free_mr->free_mr_wq);
1446 destroy_workqueue(free_mr->free_mr_wq);
1452 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1454 struct hns_roce_free_mr *free_mr;
1455 struct hns_roce_v1_priv *priv;
1457 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1458 free_mr = &priv->free_mr;
1460 flush_workqueue(free_mr->free_mr_wq);
1461 destroy_workqueue(free_mr->free_mr_wq);
1463 hns_roce_v1_release_lp_qp(hr_dev);
1467 * hns_roce_v1_reset - reset RoCE
1468 * @hr_dev: RoCE device struct pointer
1469 * @enable: true -- drop reset, false -- reset
1470 * return 0 - success , negative --fail
1472 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1474 struct device_node *dsaf_node;
1475 struct device *dev = &hr_dev->pdev->dev;
1476 struct device_node *np = dev->of_node;
1477 struct fwnode_handle *fwnode;
1480 /* check if this is DT/ACPI case */
1481 if (dev_of_node(dev)) {
1482 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1484 dev_err(dev, "could not find dsaf-handle\n");
1487 fwnode = &dsaf_node->fwnode;
1488 } else if (is_acpi_device_node(dev->fwnode)) {
1489 struct fwnode_reference_args args;
1491 ret = acpi_node_get_property_reference(dev->fwnode,
1492 "dsaf-handle", 0, &args);
1494 dev_err(dev, "could not find dsaf-handle\n");
1497 fwnode = args.fwnode;
1499 dev_err(dev, "cannot read data from DT or ACPI\n");
1503 ret = hns_dsaf_roce_reset(fwnode, false);
1508 msleep(SLEEP_TIME_INTERVAL);
1509 ret = hns_dsaf_roce_reset(fwnode, true);
1515 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1518 struct hns_roce_caps *caps = &hr_dev->caps;
1520 hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1521 hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1522 hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1523 ((u64)roce_read(hr_dev,
1524 ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1525 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
1527 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1528 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1529 caps->min_wqes = HNS_ROCE_MIN_WQE_NUM;
1530 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1531 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1532 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1533 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1534 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1535 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1536 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1537 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1538 caps->num_aeq_vectors = HNS_ROCE_V1_AEQE_VEC_NUM;
1539 caps->num_comp_vectors = HNS_ROCE_V1_COMP_VEC_NUM;
1540 caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1541 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1542 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1543 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1544 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1545 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1546 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1547 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1548 caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1549 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1550 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1551 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1552 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1553 caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1554 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1555 caps->reserved_lkey = 0;
1556 caps->reserved_pds = 0;
1557 caps->reserved_mrws = 1;
1558 caps->reserved_uars = 0;
1559 caps->reserved_cqs = 0;
1560 caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1562 for (i = 0; i < caps->num_ports; i++)
1563 caps->pkey_table_len[i] = 1;
1565 for (i = 0; i < caps->num_ports; i++) {
1566 /* Six ports shared 16 GID in v1 engine */
1567 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1568 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1571 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1572 caps->num_ports + 1;
1575 caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1576 caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1577 caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1578 caps->max_mtu = IB_MTU_2048;
1583 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1588 struct device *dev = &hr_dev->pdev->dev;
1590 /* DMAE user config */
1591 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1592 tmp = cpu_to_le32(val);
1593 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1594 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1595 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1596 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1597 1 << PAGES_SHIFT_16);
1598 val = le32_to_cpu(tmp);
1599 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1601 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1602 tmp = cpu_to_le32(val);
1603 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1604 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1605 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1606 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1607 1 << PAGES_SHIFT_16);
1609 ret = hns_roce_db_init(hr_dev);
1611 dev_err(dev, "doorbell init failed!\n");
1615 ret = hns_roce_raq_init(hr_dev);
1617 dev_err(dev, "raq init failed!\n");
1618 goto error_failed_raq_init;
1621 ret = hns_roce_bt_init(hr_dev);
1623 dev_err(dev, "bt init failed!\n");
1624 goto error_failed_bt_init;
1627 ret = hns_roce_tptr_init(hr_dev);
1629 dev_err(dev, "tptr init failed!\n");
1630 goto error_failed_tptr_init;
1633 ret = hns_roce_free_mr_init(hr_dev);
1635 dev_err(dev, "free mr init failed!\n");
1636 goto error_failed_free_mr_init;
1639 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1643 error_failed_free_mr_init:
1644 hns_roce_tptr_free(hr_dev);
1646 error_failed_tptr_init:
1647 hns_roce_bt_free(hr_dev);
1649 error_failed_bt_init:
1650 hns_roce_raq_free(hr_dev);
1652 error_failed_raq_init:
1653 hns_roce_db_free(hr_dev);
1657 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1659 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1660 hns_roce_free_mr_free(hr_dev);
1661 hns_roce_tptr_free(hr_dev);
1662 hns_roce_bt_free(hr_dev);
1663 hns_roce_raq_free(hr_dev);
1664 hns_roce_db_free(hr_dev);
1667 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1669 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1671 return (!!(status & (1 << HCR_GO_BIT)));
1674 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1675 u64 out_param, u32 in_modifier, u8 op_modifier,
1676 u16 op, u16 token, int event)
1678 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1683 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1684 while (hns_roce_v1_cmd_pending(hr_dev)) {
1685 if (time_after(jiffies, end)) {
1686 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1687 (int)jiffies, (int)end);
1693 tmp = cpu_to_le32(val);
1694 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1696 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1697 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1698 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1699 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1700 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1701 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1703 val = le32_to_cpu(tmp);
1704 writeq(in_param, hcr + 0);
1705 writeq(out_param, hcr + 2);
1706 writel(in_modifier, hcr + 4);
1707 /* Memory barrier */
1710 writel(val, hcr + 5);
1715 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1716 unsigned long timeout)
1718 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1719 unsigned long end = 0;
1722 end = msecs_to_jiffies(timeout) + jiffies;
1723 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1726 if (hns_roce_v1_cmd_pending(hr_dev)) {
1727 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1731 status = le32_to_cpu((__force __le32)
1732 __raw_readl(hcr + HCR_STATUS_OFFSET));
1733 if ((status & STATUS_MASK) != 0x1) {
1734 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1741 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1742 int gid_index, const union ib_gid *gid,
1743 const struct ib_gid_attr *attr)
1748 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1750 p = (u32 *)&gid->raw[0];
1751 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1752 (HNS_ROCE_V1_GID_NUM * gid_idx));
1754 p = (u32 *)&gid->raw[4];
1755 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1756 (HNS_ROCE_V1_GID_NUM * gid_idx));
1758 p = (u32 *)&gid->raw[8];
1759 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1760 (HNS_ROCE_V1_GID_NUM * gid_idx));
1762 p = (u32 *)&gid->raw[0xc];
1763 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1764 (HNS_ROCE_V1_GID_NUM * gid_idx));
1769 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1780 * When mac changed, loopback may fail
1781 * because of smac not equal to dmac.
1782 * We Need to release and create reserved qp again.
1784 if (hr_dev->hw->dereg_mr) {
1787 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1788 if (ret && ret != -ETIMEDOUT)
1792 p = (u32 *)(&addr[0]);
1794 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1795 PHY_PORT_OFFSET * phy_port);
1797 val = roce_read(hr_dev,
1798 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1799 tmp = cpu_to_le32(val);
1800 p_h = (u16 *)(&addr[4]);
1802 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1803 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1804 val = le32_to_cpu(tmp);
1805 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1811 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1817 val = roce_read(hr_dev,
1818 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1819 tmp = cpu_to_le32(val);
1820 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1821 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1822 val = le32_to_cpu(tmp);
1823 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1827 static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1828 unsigned long mtpt_idx)
1830 struct hns_roce_v1_mpt_entry *mpt_entry;
1831 struct sg_dma_page_iter sg_iter;
1835 /* MPT filled into mailbox buf */
1836 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1837 memset(mpt_entry, 0, sizeof(*mpt_entry));
1839 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1840 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1841 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1842 MPT_BYTE_4_KEY_S, mr->key);
1843 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1844 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1845 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1846 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1847 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1848 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1849 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1850 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1851 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1852 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1853 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1854 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1855 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1856 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1857 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1858 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1860 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1862 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1863 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1864 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1865 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1867 mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1868 mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1869 mpt_entry->length = cpu_to_le32((u32)mr->size);
1871 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1872 MPT_BYTE_28_PD_S, mr->pd);
1873 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1874 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1875 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1876 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1878 /* DMA memory register */
1879 if (mr->type == MR_TYPE_DMA)
1882 pages = (u64 *) __get_free_page(GFP_KERNEL);
1887 for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
1888 pages[i] = ((u64)sg_page_iter_dma_address(&sg_iter)) >> 12;
1890 /* Directly record to MTPT table firstly 7 entry */
1891 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1896 /* Register user mr */
1897 for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1900 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1901 roce_set_field(mpt_entry->mpt_byte_36,
1902 MPT_BYTE_36_PA0_H_M,
1903 MPT_BYTE_36_PA0_H_S,
1904 (u32)(pages[i] >> PAGES_SHIFT_32));
1907 roce_set_field(mpt_entry->mpt_byte_36,
1908 MPT_BYTE_36_PA1_L_M,
1909 MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1910 roce_set_field(mpt_entry->mpt_byte_40,
1911 MPT_BYTE_40_PA1_H_M,
1912 MPT_BYTE_40_PA1_H_S,
1913 (u32)(pages[i] >> PAGES_SHIFT_24));
1916 roce_set_field(mpt_entry->mpt_byte_40,
1917 MPT_BYTE_40_PA2_L_M,
1918 MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1919 roce_set_field(mpt_entry->mpt_byte_44,
1920 MPT_BYTE_44_PA2_H_M,
1921 MPT_BYTE_44_PA2_H_S,
1922 (u32)(pages[i] >> PAGES_SHIFT_16));
1925 roce_set_field(mpt_entry->mpt_byte_44,
1926 MPT_BYTE_44_PA3_L_M,
1927 MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1928 roce_set_field(mpt_entry->mpt_byte_48,
1929 MPT_BYTE_48_PA3_H_M,
1930 MPT_BYTE_48_PA3_H_S,
1931 (u32)(pages[i] >> PAGES_SHIFT_8));
1934 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1935 roce_set_field(mpt_entry->mpt_byte_56,
1936 MPT_BYTE_56_PA4_H_M,
1937 MPT_BYTE_56_PA4_H_S,
1938 (u32)(pages[i] >> PAGES_SHIFT_32));
1941 roce_set_field(mpt_entry->mpt_byte_56,
1942 MPT_BYTE_56_PA5_L_M,
1943 MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1944 roce_set_field(mpt_entry->mpt_byte_60,
1945 MPT_BYTE_60_PA5_H_M,
1946 MPT_BYTE_60_PA5_H_S,
1947 (u32)(pages[i] >> PAGES_SHIFT_24));
1950 roce_set_field(mpt_entry->mpt_byte_60,
1951 MPT_BYTE_60_PA6_L_M,
1952 MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1953 roce_set_field(mpt_entry->mpt_byte_64,
1954 MPT_BYTE_64_PA6_H_M,
1955 MPT_BYTE_64_PA6_H_S,
1956 (u32)(pages[i] >> PAGES_SHIFT_16));
1963 free_page((unsigned long) pages);
1965 mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
1967 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1968 MPT_BYTE_12_PBL_ADDR_H_S,
1969 ((u32)(mr->pbl_dma_addr >> 32)));
1974 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1976 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1977 n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1980 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1982 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1984 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1985 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1986 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
1989 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1991 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1994 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1998 doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
2000 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2001 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2002 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2003 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2004 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2005 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2006 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2008 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2011 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2012 struct hns_roce_srq *srq)
2014 struct hns_roce_cqe *cqe, *dest;
2019 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2021 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2026 * Now backwards through the CQ, removing CQ entries
2027 * that match our QP by overwriting them with next entries.
2029 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2030 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2031 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2032 CQE_BYTE_16_LOCAL_QPN_S) &
2033 HNS_ROCE_CQE_QPN_MASK) == qpn) {
2034 /* In v1 engine, not support SRQ */
2036 } else if (nfreed) {
2037 dest = get_cqe(hr_cq, (prod_index + nfreed) &
2039 owner_bit = roce_get_bit(dest->cqe_byte_4,
2040 CQE_BYTE_4_OWNER_S);
2041 memcpy(dest, cqe, sizeof(*cqe));
2042 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2048 hr_cq->cons_index += nfreed;
2050 * Make sure update of buffer contents is done before
2051 * updating consumer index.
2055 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2059 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2060 struct hns_roce_srq *srq)
2062 spin_lock_irq(&hr_cq->lock);
2063 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2064 spin_unlock_irq(&hr_cq->lock);
2067 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2068 struct hns_roce_cq *hr_cq, void *mb_buf,
2069 u64 *mtts, dma_addr_t dma_handle, int nent,
2072 struct hns_roce_cq_context *cq_context = NULL;
2073 struct hns_roce_buf_list *tptr_buf;
2074 struct hns_roce_v1_priv *priv;
2075 dma_addr_t tptr_dma_addr;
2078 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2079 tptr_buf = &priv->tptr_table.tptr_buf;
2081 cq_context = mb_buf;
2082 memset(cq_context, 0, sizeof(*cq_context));
2084 /* Get the tptr for this CQ. */
2085 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2086 tptr_dma_addr = tptr_buf->map + offset;
2087 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2089 /* Register cq_context members */
2090 roce_set_field(cq_context->cqc_byte_4,
2091 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2092 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2093 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2094 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2096 cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2098 roce_set_field(cq_context->cqc_byte_12,
2099 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2100 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2101 ((u64)dma_handle >> 32));
2102 roce_set_field(cq_context->cqc_byte_12,
2103 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2104 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2105 ilog2((unsigned int)nent));
2106 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2107 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
2109 cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2111 roce_set_field(cq_context->cqc_byte_20,
2112 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2113 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2114 /* Dedicated hardware, directly set 0 */
2115 roce_set_field(cq_context->cqc_byte_20,
2116 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2117 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2119 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2120 * using 4K page, and shift more 32 because of
2121 * caculating the high 32 bit value evaluated to hardware.
2123 roce_set_field(cq_context->cqc_byte_20,
2124 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2125 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2126 tptr_dma_addr >> 44);
2128 cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2130 roce_set_field(cq_context->cqc_byte_32,
2131 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2132 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2133 roce_set_bit(cq_context->cqc_byte_32,
2134 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2135 roce_set_bit(cq_context->cqc_byte_32,
2136 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2137 roce_set_bit(cq_context->cqc_byte_32,
2138 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2139 roce_set_bit(cq_context->cqc_byte_32,
2140 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2142 /* The initial value of cq's ci is 0 */
2143 roce_set_field(cq_context->cqc_byte_32,
2144 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2145 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2148 static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2153 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2154 enum ib_cq_notify_flags flags)
2156 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2157 u32 notification_flag;
2160 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2161 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2163 * flags = 0; Notification Flag = 1, next
2164 * flags = 1; Notification Flag = 0, solocited
2167 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2168 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2169 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2170 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2171 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2172 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2173 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2174 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2175 hr_cq->cqn | notification_flag);
2177 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2182 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2183 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2190 struct hns_roce_cqe *cqe;
2191 struct hns_roce_qp *hr_qp;
2192 struct hns_roce_wq *wq;
2193 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2194 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2195 struct device *dev = &hr_dev->pdev->dev;
2197 /* Find cqe according consumer index */
2198 cqe = next_cqe_sw(hr_cq);
2202 ++hr_cq->cons_index;
2203 /* Memory barrier */
2206 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2208 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2209 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2210 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2211 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2212 CQE_BYTE_20_PORT_NUM_S) +
2213 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2214 CQE_BYTE_16_LOCAL_QPN_S) *
2217 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2218 CQE_BYTE_16_LOCAL_QPN_S);
2221 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2222 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2223 if (unlikely(!hr_qp)) {
2224 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2225 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2232 wc->qp = &(*cur_qp)->ibqp;
2235 status = roce_get_field(cqe->cqe_byte_4,
2236 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2237 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2238 HNS_ROCE_CQE_STATUS_MASK;
2240 case HNS_ROCE_CQE_SUCCESS:
2241 wc->status = IB_WC_SUCCESS;
2243 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2244 wc->status = IB_WC_LOC_LEN_ERR;
2246 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2247 wc->status = IB_WC_LOC_QP_OP_ERR;
2249 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2250 wc->status = IB_WC_LOC_PROT_ERR;
2252 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2253 wc->status = IB_WC_WR_FLUSH_ERR;
2255 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2256 wc->status = IB_WC_MW_BIND_ERR;
2258 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2259 wc->status = IB_WC_BAD_RESP_ERR;
2261 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2262 wc->status = IB_WC_LOC_ACCESS_ERR;
2264 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2265 wc->status = IB_WC_REM_INV_REQ_ERR;
2267 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2268 wc->status = IB_WC_REM_ACCESS_ERR;
2270 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2271 wc->status = IB_WC_REM_OP_ERR;
2273 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2274 wc->status = IB_WC_RETRY_EXC_ERR;
2276 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2277 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2280 wc->status = IB_WC_GENERAL_ERR;
2284 /* CQE status error, directly return */
2285 if (wc->status != IB_WC_SUCCESS)
2289 /* SQ conrespond to CQE */
2290 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2291 CQE_BYTE_4_WQE_INDEX_M,
2292 CQE_BYTE_4_WQE_INDEX_S)&
2293 ((*cur_qp)->sq.wqe_cnt-1));
2294 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2295 case HNS_ROCE_WQE_OPCODE_SEND:
2296 wc->opcode = IB_WC_SEND;
2298 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2299 wc->opcode = IB_WC_RDMA_READ;
2300 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2302 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2303 wc->opcode = IB_WC_RDMA_WRITE;
2305 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2306 wc->opcode = IB_WC_LOCAL_INV;
2308 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2309 wc->opcode = IB_WC_SEND;
2312 wc->status = IB_WC_GENERAL_ERR;
2315 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2316 IB_WC_WITH_IMM : 0);
2318 wq = &(*cur_qp)->sq;
2319 if ((*cur_qp)->sq_signal_bits) {
2321 * If sg_signal_bit is 1,
2322 * firstly tail pointer updated to wqe
2323 * which current cqe correspond to
2325 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2326 CQE_BYTE_4_WQE_INDEX_M,
2327 CQE_BYTE_4_WQE_INDEX_S);
2328 wq->tail += (wqe_ctr - (u16)wq->tail) &
2331 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2334 /* RQ conrespond to CQE */
2335 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2336 opcode = roce_get_field(cqe->cqe_byte_4,
2337 CQE_BYTE_4_OPERATION_TYPE_M,
2338 CQE_BYTE_4_OPERATION_TYPE_S) &
2339 HNS_ROCE_CQE_OPCODE_MASK;
2341 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2342 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2343 wc->wc_flags = IB_WC_WITH_IMM;
2345 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2347 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2348 if (roce_get_bit(cqe->cqe_byte_4,
2349 CQE_BYTE_4_IMM_INDICATOR_S)) {
2350 wc->opcode = IB_WC_RECV;
2351 wc->wc_flags = IB_WC_WITH_IMM;
2352 wc->ex.imm_data = cpu_to_be32(
2353 le32_to_cpu(cqe->immediate_data));
2355 wc->opcode = IB_WC_RECV;
2360 wc->status = IB_WC_GENERAL_ERR;
2364 /* Update tail pointer, record wr_id */
2365 wq = &(*cur_qp)->rq;
2366 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2368 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2370 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2371 CQE_BYTE_20_REMOTE_QPN_M,
2372 CQE_BYTE_20_REMOTE_QPN_S);
2373 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2374 CQE_BYTE_20_GRH_PRESENT_S) ?
2376 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2377 CQE_BYTE_28_P_KEY_IDX_M,
2378 CQE_BYTE_28_P_KEY_IDX_S);
2384 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2386 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2387 struct hns_roce_qp *cur_qp = NULL;
2388 unsigned long flags;
2392 spin_lock_irqsave(&hr_cq->lock, flags);
2394 for (npolled = 0; npolled < num_entries; ++npolled) {
2395 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2401 *hr_cq->tptr_addr = hr_cq->cons_index &
2402 ((hr_cq->cq_depth << 1) - 1);
2404 /* Memroy barrier */
2406 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2409 spin_unlock_irqrestore(&hr_cq->lock, flags);
2411 if (ret == 0 || ret == -EAGAIN)
2417 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2418 struct hns_roce_hem_table *table, int obj,
2421 struct device *dev = &hr_dev->pdev->dev;
2422 struct hns_roce_v1_priv *priv;
2423 unsigned long end = 0, flags = 0;
2424 __le32 bt_cmd_val[2] = {0};
2425 void __iomem *bt_cmd;
2428 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2430 switch (table->type) {
2432 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2433 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2434 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2437 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2438 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2439 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2442 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2443 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2444 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2447 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2452 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2453 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2454 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2455 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2457 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2459 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2461 end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2463 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2464 if (!(time_before(jiffies, end))) {
2465 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2466 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2473 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2476 bt_cmd_val[0] = (__le32)bt_ba;
2477 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2478 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2479 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2481 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2486 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2487 struct hns_roce_mtt *mtt,
2488 enum hns_roce_qp_state cur_state,
2489 enum hns_roce_qp_state new_state,
2490 struct hns_roce_qp_context *context,
2491 struct hns_roce_qp *hr_qp)
2494 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2495 [HNS_ROCE_QP_STATE_RST] = {
2496 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2497 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2498 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2500 [HNS_ROCE_QP_STATE_INIT] = {
2501 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2502 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2503 /* Note: In v1 engine, HW doesn't support RST2INIT.
2504 * We use RST2INIT cmd instead of INIT2INIT.
2506 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2507 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2509 [HNS_ROCE_QP_STATE_RTR] = {
2510 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2511 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2512 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2514 [HNS_ROCE_QP_STATE_RTS] = {
2515 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2516 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2517 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2518 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2520 [HNS_ROCE_QP_STATE_SQD] = {
2521 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2522 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2523 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2524 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2526 [HNS_ROCE_QP_STATE_ERR] = {
2527 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2528 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2532 struct hns_roce_cmd_mailbox *mailbox;
2533 struct device *dev = &hr_dev->pdev->dev;
2536 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2537 new_state >= HNS_ROCE_QP_NUM_STATE ||
2538 !op[cur_state][new_state]) {
2539 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2540 cur_state, new_state);
2544 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2545 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2546 HNS_ROCE_CMD_2RST_QP,
2547 HNS_ROCE_CMD_TIMEOUT_MSECS);
2549 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2550 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2551 HNS_ROCE_CMD_2ERR_QP,
2552 HNS_ROCE_CMD_TIMEOUT_MSECS);
2554 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2555 if (IS_ERR(mailbox))
2556 return PTR_ERR(mailbox);
2558 memcpy(mailbox->buf, context, sizeof(*context));
2560 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2561 op[cur_state][new_state],
2562 HNS_ROCE_CMD_TIMEOUT_MSECS);
2564 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2568 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2569 int attr_mask, enum ib_qp_state cur_state,
2570 enum ib_qp_state new_state)
2572 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2573 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2574 struct hns_roce_sqp_context *context;
2575 struct device *dev = &hr_dev->pdev->dev;
2576 dma_addr_t dma_handle = 0;
2583 context = kzalloc(sizeof(*context), GFP_KERNEL);
2587 /* Search QP buf's MTTs */
2588 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2589 hr_qp->mtt.first_seg, &dma_handle);
2591 dev_err(dev, "qp buf pa find failed\n");
2595 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2596 roce_set_field(context->qp1c_bytes_4,
2597 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2598 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2599 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2600 roce_set_field(context->qp1c_bytes_4,
2601 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2602 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2603 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2604 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2605 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2607 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2608 roce_set_field(context->qp1c_bytes_12,
2609 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2610 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2611 ((u32)(dma_handle >> 32)));
2613 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2614 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2615 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2616 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2617 roce_set_bit(context->qp1c_bytes_16,
2618 QP1C_BYTES_16_SIGNALING_TYPE_S,
2619 le32_to_cpu(hr_qp->sq_signal_bits));
2620 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2622 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2624 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2627 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2628 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2629 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2630 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2632 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2633 context->cur_rq_wqe_ba_l =
2634 cpu_to_le32((u32)(mtts[rq_pa_start]));
2636 roce_set_field(context->qp1c_bytes_28,
2637 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2638 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2639 (mtts[rq_pa_start]) >> 32);
2640 roce_set_field(context->qp1c_bytes_28,
2641 QP1C_BYTES_28_RQ_CUR_IDX_M,
2642 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2644 roce_set_field(context->qp1c_bytes_32,
2645 QP1C_BYTES_32_RX_CQ_NUM_M,
2646 QP1C_BYTES_32_RX_CQ_NUM_S,
2647 to_hr_cq(ibqp->recv_cq)->cqn);
2648 roce_set_field(context->qp1c_bytes_32,
2649 QP1C_BYTES_32_TX_CQ_NUM_M,
2650 QP1C_BYTES_32_TX_CQ_NUM_S,
2651 to_hr_cq(ibqp->send_cq)->cqn);
2653 context->cur_sq_wqe_ba_l = cpu_to_le32((u32)mtts[0]);
2655 roce_set_field(context->qp1c_bytes_40,
2656 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2657 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2659 roce_set_field(context->qp1c_bytes_40,
2660 QP1C_BYTES_40_SQ_CUR_IDX_M,
2661 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2663 /* Copy context to QP1C register */
2664 addr = (u32 __iomem *)(hr_dev->reg_base +
2665 ROCEE_QP1C_CFG0_0_REG +
2666 hr_qp->phy_port * sizeof(*context));
2668 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2669 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2670 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2671 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2672 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2673 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2674 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2675 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2676 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2677 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2680 /* Modify QP1C status */
2681 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2682 hr_qp->phy_port * sizeof(*context));
2683 tmp = cpu_to_le32(reg_val);
2684 roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2685 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2686 reg_val = le32_to_cpu(tmp);
2687 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2688 hr_qp->phy_port * sizeof(*context), reg_val);
2690 hr_qp->state = new_state;
2691 if (new_state == IB_QPS_RESET) {
2692 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2693 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2694 if (ibqp->send_cq != ibqp->recv_cq)
2695 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2702 hr_qp->sq_next_wqe = 0;
2713 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2714 int attr_mask, enum ib_qp_state cur_state,
2715 enum ib_qp_state new_state)
2717 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2718 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2719 struct device *dev = &hr_dev->pdev->dev;
2720 struct hns_roce_qp_context *context;
2721 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2722 dma_addr_t dma_handle_2 = 0;
2723 dma_addr_t dma_handle = 0;
2724 __le32 doorbell[2] = {0};
2725 int rq_pa_start = 0;
2734 context = kzalloc(sizeof(*context), GFP_KERNEL);
2738 /* Search qp buf's mtts */
2739 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2740 hr_qp->mtt.first_seg, &dma_handle);
2742 dev_err(dev, "qp buf pa find failed\n");
2746 /* Search IRRL's mtts */
2747 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2748 hr_qp->qpn, &dma_handle_2);
2749 if (mtts_2 == NULL) {
2750 dev_err(dev, "qp irrl_table find failed\n");
2757 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2758 * Optional param: NA
2760 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2761 roce_set_field(context->qpc_bytes_4,
2762 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2763 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2764 to_hr_qp_type(hr_qp->ibqp.qp_type));
2766 roce_set_bit(context->qpc_bytes_4,
2767 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2768 roce_set_bit(context->qpc_bytes_4,
2769 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2770 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2771 roce_set_bit(context->qpc_bytes_4,
2772 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2773 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2775 roce_set_bit(context->qpc_bytes_4,
2776 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2777 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2779 roce_set_bit(context->qpc_bytes_4,
2780 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2781 roce_set_field(context->qpc_bytes_4,
2782 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2783 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2784 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2785 roce_set_field(context->qpc_bytes_4,
2786 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2787 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2788 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2789 roce_set_field(context->qpc_bytes_4,
2790 QP_CONTEXT_QPC_BYTES_4_PD_M,
2791 QP_CONTEXT_QPC_BYTES_4_PD_S,
2792 to_hr_pd(ibqp->pd)->pdn);
2793 hr_qp->access_flags = attr->qp_access_flags;
2794 roce_set_field(context->qpc_bytes_8,
2795 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2796 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2797 to_hr_cq(ibqp->send_cq)->cqn);
2798 roce_set_field(context->qpc_bytes_8,
2799 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2800 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2801 to_hr_cq(ibqp->recv_cq)->cqn);
2804 roce_set_field(context->qpc_bytes_12,
2805 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2806 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2807 to_hr_srq(ibqp->srq)->srqn);
2809 roce_set_field(context->qpc_bytes_12,
2810 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2811 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2813 hr_qp->pkey_index = attr->pkey_index;
2814 roce_set_field(context->qpc_bytes_16,
2815 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2816 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2818 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2819 roce_set_field(context->qpc_bytes_4,
2820 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2821 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2822 to_hr_qp_type(hr_qp->ibqp.qp_type));
2823 roce_set_bit(context->qpc_bytes_4,
2824 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2825 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2826 roce_set_bit(context->qpc_bytes_4,
2827 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2828 !!(attr->qp_access_flags &
2829 IB_ACCESS_REMOTE_READ));
2830 roce_set_bit(context->qpc_bytes_4,
2831 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2832 !!(attr->qp_access_flags &
2833 IB_ACCESS_REMOTE_WRITE));
2835 roce_set_bit(context->qpc_bytes_4,
2836 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2837 !!(hr_qp->access_flags &
2838 IB_ACCESS_REMOTE_READ));
2839 roce_set_bit(context->qpc_bytes_4,
2840 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2841 !!(hr_qp->access_flags &
2842 IB_ACCESS_REMOTE_WRITE));
2845 roce_set_bit(context->qpc_bytes_4,
2846 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2847 roce_set_field(context->qpc_bytes_4,
2848 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2849 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2850 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2851 roce_set_field(context->qpc_bytes_4,
2852 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2853 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2854 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2855 roce_set_field(context->qpc_bytes_4,
2856 QP_CONTEXT_QPC_BYTES_4_PD_M,
2857 QP_CONTEXT_QPC_BYTES_4_PD_S,
2858 to_hr_pd(ibqp->pd)->pdn);
2860 roce_set_field(context->qpc_bytes_8,
2861 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2862 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2863 to_hr_cq(ibqp->send_cq)->cqn);
2864 roce_set_field(context->qpc_bytes_8,
2865 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2866 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2867 to_hr_cq(ibqp->recv_cq)->cqn);
2870 roce_set_field(context->qpc_bytes_12,
2871 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2872 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2873 to_hr_srq(ibqp->srq)->srqn);
2874 if (attr_mask & IB_QP_PKEY_INDEX)
2875 roce_set_field(context->qpc_bytes_12,
2876 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2877 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2880 roce_set_field(context->qpc_bytes_12,
2881 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2882 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2885 roce_set_field(context->qpc_bytes_16,
2886 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2887 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2888 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2889 if ((attr_mask & IB_QP_ALT_PATH) ||
2890 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2891 (attr_mask & IB_QP_PKEY_INDEX) ||
2892 (attr_mask & IB_QP_QKEY)) {
2893 dev_err(dev, "INIT2RTR attr_mask error\n");
2897 dmac = (u8 *)attr->ah_attr.roce.dmac;
2899 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2900 roce_set_field(context->qpc_bytes_24,
2901 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2902 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2903 ((u32)(dma_handle >> 32)));
2904 roce_set_bit(context->qpc_bytes_24,
2905 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2907 roce_set_field(context->qpc_bytes_24,
2908 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2909 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2910 attr->min_rnr_timer);
2911 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2912 roce_set_field(context->qpc_bytes_32,
2913 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2914 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2915 ((u32)(dma_handle_2 >> 32)) &
2916 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2917 roce_set_field(context->qpc_bytes_32,
2918 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2919 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2920 roce_set_bit(context->qpc_bytes_32,
2921 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2923 roce_set_bit(context->qpc_bytes_32,
2924 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2925 le32_to_cpu(hr_qp->sq_signal_bits));
2927 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2929 smac = (u8 *)hr_dev->dev_addr[port];
2930 /* when dmac equals smac or loop_idc is 1, it should loopback */
2931 if (ether_addr_equal_unaligned(dmac, smac) ||
2932 hr_dev->loop_idc == 0x1)
2933 roce_set_bit(context->qpc_bytes_32,
2934 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2936 roce_set_bit(context->qpc_bytes_32,
2937 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2938 rdma_ah_get_ah_flags(&attr->ah_attr));
2939 roce_set_field(context->qpc_bytes_32,
2940 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2941 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2942 ilog2((unsigned int)attr->max_dest_rd_atomic));
2944 if (attr_mask & IB_QP_DEST_QPN)
2945 roce_set_field(context->qpc_bytes_36,
2946 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2947 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2950 /* Configure GID index */
2951 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2952 roce_set_field(context->qpc_bytes_36,
2953 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2954 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2955 hns_get_gid_index(hr_dev,
2959 memcpy(&(context->dmac_l), dmac, 4);
2961 roce_set_field(context->qpc_bytes_44,
2962 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2963 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2964 *((u16 *)(&dmac[4])));
2965 roce_set_field(context->qpc_bytes_44,
2966 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2967 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2968 rdma_ah_get_static_rate(&attr->ah_attr));
2969 roce_set_field(context->qpc_bytes_44,
2970 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2971 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2974 roce_set_field(context->qpc_bytes_48,
2975 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2976 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2978 roce_set_field(context->qpc_bytes_48,
2979 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2980 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2981 grh->traffic_class);
2982 roce_set_field(context->qpc_bytes_48,
2983 QP_CONTEXT_QPC_BYTES_48_MTU_M,
2984 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2986 memcpy(context->dgid, grh->dgid.raw,
2987 sizeof(grh->dgid.raw));
2989 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2990 roce_get_field(context->qpc_bytes_44,
2991 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2992 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2994 roce_set_field(context->qpc_bytes_68,
2995 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2996 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2998 roce_set_field(context->qpc_bytes_68,
2999 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3000 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3002 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
3003 context->cur_rq_wqe_ba_l =
3004 cpu_to_le32((u32)(mtts[rq_pa_start]));
3006 roce_set_field(context->qpc_bytes_76,
3007 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3008 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3009 mtts[rq_pa_start] >> 32);
3010 roce_set_field(context->qpc_bytes_76,
3011 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3012 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3014 context->rx_rnr_time = 0;
3016 roce_set_field(context->qpc_bytes_84,
3017 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3018 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3020 roce_set_field(context->qpc_bytes_84,
3021 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3022 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3024 roce_set_field(context->qpc_bytes_88,
3025 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3026 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3028 roce_set_bit(context->qpc_bytes_88,
3029 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3030 roce_set_bit(context->qpc_bytes_88,
3031 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3032 roce_set_field(context->qpc_bytes_88,
3033 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3034 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3036 roce_set_field(context->qpc_bytes_88,
3037 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3038 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3041 context->dma_length = 0;
3046 roce_set_field(context->qpc_bytes_108,
3047 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3048 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3049 roce_set_bit(context->qpc_bytes_108,
3050 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3051 roce_set_bit(context->qpc_bytes_108,
3052 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3054 roce_set_field(context->qpc_bytes_112,
3055 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3056 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3057 roce_set_field(context->qpc_bytes_112,
3058 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3059 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3061 /* For chip resp ack */
3062 roce_set_field(context->qpc_bytes_156,
3063 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3064 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3066 roce_set_field(context->qpc_bytes_156,
3067 QP_CONTEXT_QPC_BYTES_156_SL_M,
3068 QP_CONTEXT_QPC_BYTES_156_SL_S,
3069 rdma_ah_get_sl(&attr->ah_attr));
3070 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3071 } else if (cur_state == IB_QPS_RTR &&
3072 new_state == IB_QPS_RTS) {
3073 /* If exist optional param, return error */
3074 if ((attr_mask & IB_QP_ALT_PATH) ||
3075 (attr_mask & IB_QP_ACCESS_FLAGS) ||
3076 (attr_mask & IB_QP_QKEY) ||
3077 (attr_mask & IB_QP_PATH_MIG_STATE) ||
3078 (attr_mask & IB_QP_CUR_STATE) ||
3079 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3080 dev_err(dev, "RTR2RTS attr_mask error\n");
3084 context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3086 roce_set_field(context->qpc_bytes_120,
3087 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3088 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3091 roce_set_field(context->qpc_bytes_124,
3092 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3093 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3094 roce_set_field(context->qpc_bytes_124,
3095 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3096 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3098 roce_set_field(context->qpc_bytes_128,
3099 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3100 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3102 roce_set_bit(context->qpc_bytes_128,
3103 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3104 roce_set_field(context->qpc_bytes_128,
3105 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3106 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3108 roce_set_bit(context->qpc_bytes_128,
3109 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3111 roce_set_field(context->qpc_bytes_132,
3112 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3113 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3114 roce_set_field(context->qpc_bytes_132,
3115 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3116 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3118 roce_set_field(context->qpc_bytes_136,
3119 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3120 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3122 roce_set_field(context->qpc_bytes_136,
3123 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3124 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3127 roce_set_field(context->qpc_bytes_140,
3128 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3129 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3130 (attr->sq_psn >> SQ_PSN_SHIFT));
3131 roce_set_field(context->qpc_bytes_140,
3132 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3133 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3134 roce_set_bit(context->qpc_bytes_140,
3135 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3137 roce_set_field(context->qpc_bytes_148,
3138 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3139 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3140 roce_set_field(context->qpc_bytes_148,
3141 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3142 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3144 roce_set_field(context->qpc_bytes_148,
3145 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3146 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3148 roce_set_field(context->qpc_bytes_148,
3149 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3150 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3152 context->rnr_retry = 0;
3154 roce_set_field(context->qpc_bytes_156,
3155 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3156 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3158 if (attr->timeout < 0x12) {
3159 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3161 roce_set_field(context->qpc_bytes_156,
3162 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3163 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3166 roce_set_field(context->qpc_bytes_156,
3167 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3168 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3171 roce_set_field(context->qpc_bytes_156,
3172 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3173 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3175 roce_set_field(context->qpc_bytes_156,
3176 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3177 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3179 roce_set_field(context->qpc_bytes_156,
3180 QP_CONTEXT_QPC_BYTES_156_SL_M,
3181 QP_CONTEXT_QPC_BYTES_156_SL_S,
3182 rdma_ah_get_sl(&attr->ah_attr));
3183 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3184 roce_set_field(context->qpc_bytes_156,
3185 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3186 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3187 ilog2((unsigned int)attr->max_rd_atomic));
3188 roce_set_field(context->qpc_bytes_156,
3189 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3190 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3191 context->pkt_use_len = 0;
3193 roce_set_field(context->qpc_bytes_164,
3194 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3195 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3196 roce_set_field(context->qpc_bytes_164,
3197 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3198 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3200 roce_set_field(context->qpc_bytes_168,
3201 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3202 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3204 roce_set_field(context->qpc_bytes_168,
3205 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3206 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3207 roce_set_field(context->qpc_bytes_168,
3208 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3209 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3210 roce_set_bit(context->qpc_bytes_168,
3211 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3212 roce_set_bit(context->qpc_bytes_168,
3213 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3214 roce_set_bit(context->qpc_bytes_168,
3215 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3216 context->sge_use_len = 0;
3218 roce_set_field(context->qpc_bytes_176,
3219 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3220 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3221 roce_set_field(context->qpc_bytes_176,
3222 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3223 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3225 roce_set_field(context->qpc_bytes_180,
3226 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3227 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3228 roce_set_field(context->qpc_bytes_180,
3229 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3230 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3232 context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3234 roce_set_field(context->qpc_bytes_188,
3235 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3236 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3238 roce_set_bit(context->qpc_bytes_188,
3239 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3240 roce_set_field(context->qpc_bytes_188,
3241 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3242 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3244 } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3245 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3246 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3247 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3248 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3249 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3250 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3251 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3252 dev_err(dev, "not support this status migration\n");
3256 /* Every status migrate must change state */
3257 roce_set_field(context->qpc_bytes_144,
3258 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3259 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3261 /* SW pass context to HW */
3262 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3263 to_hns_roce_state(cur_state),
3264 to_hns_roce_state(new_state), context,
3267 dev_err(dev, "hns_roce_qp_modify failed\n");
3272 * Use rst2init to instead of init2init with drv,
3273 * need to hw to flash RQ HEAD by DB again
3275 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3276 /* Memory barrier */
3279 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3280 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3281 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3282 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3283 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3284 RQ_DOORBELL_U32_8_CMD_S, 1);
3285 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3287 if (ibqp->uobject) {
3288 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3289 hr_dev->odb_offset +
3290 DB_REG_OFFSET * hr_dev->priv_uar.index;
3293 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3296 hr_qp->state = new_state;
3298 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3299 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3300 if (attr_mask & IB_QP_PORT) {
3301 hr_qp->port = attr->port_num - 1;
3302 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3305 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3306 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3307 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3308 if (ibqp->send_cq != ibqp->recv_cq)
3309 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3316 hr_qp->sq_next_wqe = 0;
3323 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3324 const struct ib_qp_attr *attr, int attr_mask,
3325 enum ib_qp_state cur_state,
3326 enum ib_qp_state new_state)
3329 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3330 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3333 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3337 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3340 case HNS_ROCE_QP_STATE_RST:
3341 return IB_QPS_RESET;
3342 case HNS_ROCE_QP_STATE_INIT:
3344 case HNS_ROCE_QP_STATE_RTR:
3346 case HNS_ROCE_QP_STATE_RTS:
3348 case HNS_ROCE_QP_STATE_SQD:
3350 case HNS_ROCE_QP_STATE_ERR:
3357 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3358 struct hns_roce_qp *hr_qp,
3359 struct hns_roce_qp_context *hr_context)
3361 struct hns_roce_cmd_mailbox *mailbox;
3364 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3365 if (IS_ERR(mailbox))
3366 return PTR_ERR(mailbox);
3368 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3369 HNS_ROCE_CMD_QUERY_QP,
3370 HNS_ROCE_CMD_TIMEOUT_MSECS);
3372 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3374 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3376 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3381 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3383 struct ib_qp_init_attr *qp_init_attr)
3385 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3386 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3387 struct hns_roce_sqp_context context;
3390 mutex_lock(&hr_qp->mutex);
3392 if (hr_qp->state == IB_QPS_RESET) {
3393 qp_attr->qp_state = IB_QPS_RESET;
3397 addr = ROCEE_QP1C_CFG0_0_REG +
3398 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3399 context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3400 context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3401 context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3402 context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3403 context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3404 context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3405 context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3406 context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3407 context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3408 context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3410 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3411 QP1C_BYTES_4_QP_STATE_M,
3412 QP1C_BYTES_4_QP_STATE_S);
3413 qp_attr->qp_state = hr_qp->state;
3414 qp_attr->path_mtu = IB_MTU_256;
3415 qp_attr->path_mig_state = IB_MIG_ARMED;
3416 qp_attr->qkey = QKEY_VAL;
3417 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3418 qp_attr->rq_psn = 0;
3419 qp_attr->sq_psn = 0;
3420 qp_attr->dest_qp_num = 1;
3421 qp_attr->qp_access_flags = 6;
3423 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3424 QP1C_BYTES_20_PKEY_IDX_M,
3425 QP1C_BYTES_20_PKEY_IDX_S);
3426 qp_attr->port_num = hr_qp->port + 1;
3427 qp_attr->sq_draining = 0;
3428 qp_attr->max_rd_atomic = 0;
3429 qp_attr->max_dest_rd_atomic = 0;
3430 qp_attr->min_rnr_timer = 0;
3431 qp_attr->timeout = 0;
3432 qp_attr->retry_cnt = 0;
3433 qp_attr->rnr_retry = 0;
3434 qp_attr->alt_timeout = 0;
3437 qp_attr->cur_qp_state = qp_attr->qp_state;
3438 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3439 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3440 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3441 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3442 qp_attr->cap.max_inline_data = 0;
3443 qp_init_attr->cap = qp_attr->cap;
3444 qp_init_attr->create_flags = 0;
3446 mutex_unlock(&hr_qp->mutex);
3451 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3453 struct ib_qp_init_attr *qp_init_attr)
3455 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3456 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3457 struct device *dev = &hr_dev->pdev->dev;
3458 struct hns_roce_qp_context *context;
3459 int tmp_qp_state = 0;
3463 context = kzalloc(sizeof(*context), GFP_KERNEL);
3467 memset(qp_attr, 0, sizeof(*qp_attr));
3468 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3470 mutex_lock(&hr_qp->mutex);
3472 if (hr_qp->state == IB_QPS_RESET) {
3473 qp_attr->qp_state = IB_QPS_RESET;
3477 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3479 dev_err(dev, "query qpc error\n");
3484 state = roce_get_field(context->qpc_bytes_144,
3485 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3486 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3487 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3488 if (tmp_qp_state == -1) {
3489 dev_err(dev, "to_ib_qp_state error\n");
3493 hr_qp->state = (u8)tmp_qp_state;
3494 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3495 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3496 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3497 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3498 qp_attr->path_mig_state = IB_MIG_ARMED;
3499 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3500 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3501 qp_attr->qkey = QKEY_VAL;
3503 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3504 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3505 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3506 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3507 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3508 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3509 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3510 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3511 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3512 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3513 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3514 ((roce_get_bit(context->qpc_bytes_4,
3515 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3516 ((roce_get_bit(context->qpc_bytes_4,
3517 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3519 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3520 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3521 struct ib_global_route *grh =
3522 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3524 rdma_ah_set_sl(&qp_attr->ah_attr,
3525 roce_get_field(context->qpc_bytes_156,
3526 QP_CONTEXT_QPC_BYTES_156_SL_M,
3527 QP_CONTEXT_QPC_BYTES_156_SL_S));
3528 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3530 roce_get_field(context->qpc_bytes_48,
3531 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3532 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3534 roce_get_field(context->qpc_bytes_36,
3535 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3536 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3538 roce_get_field(context->qpc_bytes_44,
3539 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3540 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3541 grh->traffic_class =
3542 roce_get_field(context->qpc_bytes_48,
3543 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3544 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3546 memcpy(grh->dgid.raw, context->dgid,
3547 sizeof(grh->dgid.raw));
3550 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3551 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3552 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3553 qp_attr->port_num = hr_qp->port + 1;
3554 qp_attr->sq_draining = 0;
3555 qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3556 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3557 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3558 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3559 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3560 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3561 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3562 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3563 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3564 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3565 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3566 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3567 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3568 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3569 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3570 qp_attr->rnr_retry = (u8)context->rnr_retry;
3573 qp_attr->cur_qp_state = qp_attr->qp_state;
3574 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3575 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3577 if (!ibqp->uobject) {
3578 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3579 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3581 qp_attr->cap.max_send_wr = 0;
3582 qp_attr->cap.max_send_sge = 0;
3585 qp_init_attr->cap = qp_attr->cap;
3588 mutex_unlock(&hr_qp->mutex);
3593 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3595 struct ib_qp_init_attr *qp_init_attr)
3597 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3599 return hr_qp->doorbell_qpn <= 1 ?
3600 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3601 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3604 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3606 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3607 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3608 struct hns_roce_cq *send_cq, *recv_cq;
3611 ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3615 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3616 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3618 hns_roce_lock_cqs(send_cq, recv_cq);
3620 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3621 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3622 if (send_cq != recv_cq)
3623 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3625 hns_roce_unlock_cqs(send_cq, recv_cq);
3627 hns_roce_qp_remove(hr_dev, hr_qp);
3628 hns_roce_qp_free(hr_dev, hr_qp);
3630 /* RC QP, release QPN */
3631 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3632 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3634 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3637 ib_umem_release(hr_qp->umem);
3639 kfree(hr_qp->sq.wrid);
3640 kfree(hr_qp->rq.wrid);
3642 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3645 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3648 kfree(hr_to_hr_sqp(hr_qp));
3652 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3654 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3655 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3656 struct device *dev = &hr_dev->pdev->dev;
3663 hns_roce_free_cq(hr_dev, hr_cq);
3666 * Before freeing cq buffer, we need to ensure that the outstanding CQE
3667 * have been written by checking the CQE counter.
3669 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3671 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3672 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3675 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3676 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3679 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3680 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3681 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3689 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
3692 ib_umem_release(hr_cq->umem);
3694 /* Free the buff of stored cq */
3695 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
3696 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
3704 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
3706 roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3707 (req_not << eq->log_entries), eq->doorbell);
3710 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3711 struct hns_roce_aeqe *aeqe, int qpn)
3713 struct device *dev = &hr_dev->pdev->dev;
3715 dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3716 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3717 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3718 case HNS_ROCE_LWQCE_QPC_ERROR:
3719 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3721 case HNS_ROCE_LWQCE_MTU_ERROR:
3722 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3724 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3725 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3727 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3728 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3730 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3731 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3733 case HNS_ROCE_LWQCE_SL_ERROR:
3734 dev_warn(dev, "QP %d, SL error.\n", qpn);
3736 case HNS_ROCE_LWQCE_PORT_ERROR:
3737 dev_warn(dev, "QP %d, port error.\n", qpn);
3744 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3745 struct hns_roce_aeqe *aeqe,
3748 struct device *dev = &hr_dev->pdev->dev;
3750 dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3751 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3752 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3753 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3754 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3756 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3757 dev_warn(dev, "QP %d, length error.\n", qpn);
3759 case HNS_ROCE_LAVWQE_VA_ERROR:
3760 dev_warn(dev, "QP %d, VA error.\n", qpn);
3762 case HNS_ROCE_LAVWQE_PD_ERROR:
3763 dev_err(dev, "QP %d, PD error.\n", qpn);
3765 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3766 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3768 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3769 dev_warn(dev, "QP %d, key state error.\n", qpn);
3771 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3772 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3779 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3780 struct hns_roce_aeqe *aeqe,
3783 struct device *dev = &hr_dev->pdev->dev;
3787 qpn = roce_get_field(aeqe->event.qp_event.qp,
3788 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3789 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3790 phy_port = roce_get_field(aeqe->event.qp_event.qp,
3791 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3792 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3794 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3796 switch (event_type) {
3797 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3798 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3799 "QP %d, phy_port %d.\n", qpn, phy_port);
3801 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3802 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3804 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3805 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3811 hns_roce_qp_event(hr_dev, qpn, event_type);
3814 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3815 struct hns_roce_aeqe *aeqe,
3818 struct device *dev = &hr_dev->pdev->dev;
3821 cqn = roce_get_field(aeqe->event.cq_event.cq,
3822 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3823 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3825 switch (event_type) {
3826 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3827 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3829 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3830 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3832 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3833 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3839 hns_roce_cq_event(hr_dev, cqn, event_type);
3842 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3843 struct hns_roce_aeqe *aeqe)
3845 struct device *dev = &hr_dev->pdev->dev;
3847 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3848 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3849 case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3850 dev_warn(dev, "SDB overflow.\n");
3852 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3853 dev_warn(dev, "SDB almost overflow.\n");
3855 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3856 dev_warn(dev, "SDB almost empty.\n");
3858 case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3859 dev_warn(dev, "ODB overflow.\n");
3861 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3862 dev_warn(dev, "ODB almost overflow.\n");
3864 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3865 dev_warn(dev, "SDB almost empty.\n");
3872 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3874 unsigned long off = (entry & (eq->entries - 1)) *
3875 HNS_ROCE_AEQ_ENTRY_SIZE;
3877 return (struct hns_roce_aeqe *)((u8 *)
3878 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3879 off % HNS_ROCE_BA_SIZE);
3882 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3884 struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3886 return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3887 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3890 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3891 struct hns_roce_eq *eq)
3893 struct device *dev = &hr_dev->pdev->dev;
3894 struct hns_roce_aeqe *aeqe;
3895 int aeqes_found = 0;
3898 while ((aeqe = next_aeqe_sw_v1(eq))) {
3900 /* Make sure we read the AEQ entry after we have checked the
3905 dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
3906 roce_get_field(aeqe->asyn,
3907 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3908 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3909 event_type = roce_get_field(aeqe->asyn,
3910 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3911 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3912 switch (event_type) {
3913 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3914 dev_warn(dev, "PATH MIG not supported\n");
3916 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3917 dev_warn(dev, "COMMUNICATION established\n");
3919 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3920 dev_warn(dev, "SQ DRAINED not supported\n");
3922 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3923 dev_warn(dev, "PATH MIG failed\n");
3925 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3926 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3927 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3928 hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3930 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3931 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3932 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3933 dev_warn(dev, "SRQ not support!\n");
3935 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3936 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3937 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3938 hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3940 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3941 dev_warn(dev, "port change.\n");
3943 case HNS_ROCE_EVENT_TYPE_MB:
3944 hns_roce_cmd_event(hr_dev,
3945 le16_to_cpu(aeqe->event.cmd.token),
3946 aeqe->event.cmd.status,
3947 le64_to_cpu(aeqe->event.cmd.out_param
3950 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3951 hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3953 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
3954 dev_warn(dev, "CEQ 0x%lx overflow.\n",
3955 roce_get_field(aeqe->event.ce_event.ceqe,
3956 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M,
3957 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S));
3960 dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3961 event_type, eq->eqn, eq->cons_index);
3968 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
3969 dev_warn(dev, "cons_index overflow, set back to 0.\n");
3974 set_eq_cons_index_v1(eq, 0);
3979 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3981 unsigned long off = (entry & (eq->entries - 1)) *
3982 HNS_ROCE_CEQ_ENTRY_SIZE;
3984 return (struct hns_roce_ceqe *)((u8 *)
3985 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3986 off % HNS_ROCE_BA_SIZE);
3989 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3991 struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3993 return (!!(roce_get_bit(ceqe->comp,
3994 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3995 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3998 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3999 struct hns_roce_eq *eq)
4001 struct hns_roce_ceqe *ceqe;
4002 int ceqes_found = 0;
4005 while ((ceqe = next_ceqe_sw_v1(eq))) {
4007 /* Make sure we read CEQ entry after we have checked the
4012 cqn = roce_get_field(ceqe->comp,
4013 HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
4014 HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
4015 hns_roce_cq_completion(hr_dev, cqn);
4020 if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
4021 dev_warn(&eq->hr_dev->pdev->dev,
4022 "cons_index overflow, set back to 0.\n");
4027 set_eq_cons_index_v1(eq, 0);
4032 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
4034 struct hns_roce_eq *eq = eq_ptr;
4035 struct hns_roce_dev *hr_dev = eq->hr_dev;
4038 if (eq->type_flag == HNS_ROCE_CEQ)
4039 /* CEQ irq routine, CEQ is pulse irq, not clear */
4040 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4042 /* AEQ irq routine, AEQ is pulse irq, not clear */
4043 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4045 return IRQ_RETVAL(int_work);
4048 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4050 struct hns_roce_dev *hr_dev = dev_id;
4051 struct device *dev = &hr_dev->pdev->dev;
4063 * Abnormal interrupt:
4064 * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4065 * interrupt, mask irq, clear irq, cancel mask operation
4067 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4068 tmp = cpu_to_le32(aeshift_val);
4071 if (roce_get_bit(tmp,
4072 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4073 dev_warn(dev, "AEQ overflow!\n");
4076 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4077 tmp = cpu_to_le32(caepaemask_val);
4078 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4079 HNS_ROCE_INT_MASK_ENABLE);
4080 caepaemask_val = le32_to_cpu(tmp);
4081 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4083 /* Clear int state(INT_WC : write 1 clear) */
4084 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4085 tmp = cpu_to_le32(caepaest_val);
4086 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4087 caepaest_val = le32_to_cpu(tmp);
4088 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4091 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4092 tmp = cpu_to_le32(caepaemask_val);
4093 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4094 HNS_ROCE_INT_MASK_DISABLE);
4095 caepaemask_val = le32_to_cpu(tmp);
4096 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4099 /* CEQ almost overflow */
4100 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4101 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4102 i * CEQ_REG_OFFSET);
4103 tmp = cpu_to_le32(ceshift_val);
4105 if (roce_get_bit(tmp,
4106 ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4107 dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4111 cemask_val = roce_read(hr_dev,
4112 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4113 i * CEQ_REG_OFFSET);
4114 tmp = cpu_to_le32(cemask_val);
4116 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4117 HNS_ROCE_INT_MASK_ENABLE);
4118 cemask_val = le32_to_cpu(tmp);
4119 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4120 i * CEQ_REG_OFFSET, cemask_val);
4122 /* Clear int state(INT_WC : write 1 clear) */
4123 cealmovf_val = roce_read(hr_dev,
4124 ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4125 i * CEQ_REG_OFFSET);
4126 tmp = cpu_to_le32(cealmovf_val);
4128 ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4130 cealmovf_val = le32_to_cpu(tmp);
4131 roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4132 i * CEQ_REG_OFFSET, cealmovf_val);
4135 cemask_val = roce_read(hr_dev,
4136 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4137 i * CEQ_REG_OFFSET);
4138 tmp = cpu_to_le32(cemask_val);
4140 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4141 HNS_ROCE_INT_MASK_DISABLE);
4142 cemask_val = le32_to_cpu(tmp);
4143 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4144 i * CEQ_REG_OFFSET, cemask_val);
4148 /* ECC multi-bit error alarm */
4149 dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4150 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4151 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4152 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4154 dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4155 roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4156 roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4157 roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4159 return IRQ_RETVAL(int_work);
4162 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4170 aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4171 tmp = cpu_to_le32(aemask_val);
4172 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4174 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4175 aemask_val = le32_to_cpu(tmp);
4176 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4179 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4181 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4182 i * CEQ_REG_OFFSET, masken);
4186 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4187 struct hns_roce_eq *eq)
4189 int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4190 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4196 for (i = 0; i < npages; ++i)
4197 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4198 eq->buf_list[i].buf, eq->buf_list[i].map);
4200 kfree(eq->buf_list);
4203 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4206 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4211 tmp = cpu_to_le32(val);
4215 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4216 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4217 HNS_ROCE_EQ_STAT_VALID);
4220 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4221 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4222 HNS_ROCE_EQ_STAT_INVALID);
4224 val = le32_to_cpu(tmp);
4228 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4229 struct hns_roce_eq *eq)
4231 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4232 struct device *dev = &hr_dev->pdev->dev;
4233 dma_addr_t tmp_dma_addr;
4234 u32 eqconsindx_val = 0;
4235 u32 eqcuridx_val = 0;
4236 u32 eqshift_val = 0;
4244 num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4245 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4247 if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4248 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4249 (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4254 eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4258 for (i = 0; i < num_bas; ++i) {
4259 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4262 if (!eq->buf_list[i].buf) {
4264 goto err_out_free_pages;
4267 eq->buf_list[i].map = tmp_dma_addr;
4268 memset(eq->buf_list[i].buf, 0, HNS_ROCE_BA_SIZE);
4271 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4272 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4273 HNS_ROCE_EQ_STAT_INVALID);
4274 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4275 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4277 eqshift_val = le32_to_cpu(tmp);
4278 writel(eqshift_val, eqc);
4280 /* Configure eq extended address 12~44bit */
4281 writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4284 * Configure eq extended address 45~49 bit.
4285 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4286 * using 4K page, and shift more 32 because of
4287 * caculating the high 32 bit value evaluated to hardware.
4289 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4290 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4291 eq->buf_list[0].map >> 44);
4292 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4293 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4294 eqcuridx_val = le32_to_cpu(tmp1);
4295 writel(eqcuridx_val, eqc + 8);
4297 /* Configure eq consumer index */
4298 roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4299 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4300 eqconsindx_val = le32_to_cpu(tmp2);
4301 writel(eqconsindx_val, eqc + 0xc);
4306 for (i -= 1; i >= 0; i--)
4307 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4308 eq->buf_list[i].map);
4310 kfree(eq->buf_list);
4314 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4316 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4317 struct device *dev = &hr_dev->pdev->dev;
4318 struct hns_roce_eq *eq;
4324 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4325 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4327 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4331 eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4333 if (!eq_table->eqc_base) {
4335 goto err_eqc_base_alloc_fail;
4338 for (i = 0; i < eq_num; i++) {
4339 eq = &eq_table->eq[i];
4340 eq->hr_dev = hr_dev;
4342 eq->irq = hr_dev->irq[i];
4343 eq->log_page_size = PAGE_SHIFT;
4345 if (i < hr_dev->caps.num_comp_vectors) {
4347 eq_table->eqc_base[i] = hr_dev->reg_base +
4348 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4350 eq->type_flag = HNS_ROCE_CEQ;
4351 eq->doorbell = hr_dev->reg_base +
4352 ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4354 eq->entries = hr_dev->caps.ceqe_depth;
4355 eq->log_entries = ilog2(eq->entries);
4356 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
4359 eq_table->eqc_base[i] = hr_dev->reg_base +
4360 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4361 eq->type_flag = HNS_ROCE_AEQ;
4362 eq->doorbell = hr_dev->reg_base +
4363 ROCEE_CAEP_AEQE_CONS_IDX_REG;
4364 eq->entries = hr_dev->caps.aeqe_depth;
4365 eq->log_entries = ilog2(eq->entries);
4366 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
4371 hns_roce_v1_int_mask_enable(hr_dev);
4373 /* Configure ce int interval */
4374 roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4375 HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4377 /* Configure ce int burst num */
4378 roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4379 HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4381 for (i = 0; i < eq_num; i++) {
4382 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4384 dev_err(dev, "eq create failed\n");
4385 goto err_create_eq_fail;
4389 for (j = 0; j < irq_num; j++) {
4391 ret = request_irq(hr_dev->irq[j],
4392 hns_roce_v1_msix_interrupt_eq, 0,
4393 hr_dev->irq_names[j],
4396 ret = request_irq(hr_dev->irq[j],
4397 hns_roce_v1_msix_interrupt_abn, 0,
4398 hr_dev->irq_names[j], hr_dev);
4401 dev_err(dev, "request irq error!\n");
4402 goto err_request_irq_fail;
4406 for (i = 0; i < eq_num; i++)
4407 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4411 err_request_irq_fail:
4412 for (j -= 1; j >= 0; j--)
4413 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4416 for (i -= 1; i >= 0; i--)
4417 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4419 kfree(eq_table->eqc_base);
4421 err_eqc_base_alloc_fail:
4422 kfree(eq_table->eq);
4427 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4429 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4434 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4435 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4436 for (i = 0; i < eq_num; i++) {
4438 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4440 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4442 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4444 for (i = eq_num; i < irq_num; i++)
4445 free_irq(hr_dev->irq[i], hr_dev);
4447 kfree(eq_table->eqc_base);
4448 kfree(eq_table->eq);
4451 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4452 .destroy_qp = hns_roce_v1_destroy_qp,
4453 .modify_cq = hns_roce_v1_modify_cq,
4454 .poll_cq = hns_roce_v1_poll_cq,
4455 .post_recv = hns_roce_v1_post_recv,
4456 .post_send = hns_roce_v1_post_send,
4457 .query_qp = hns_roce_v1_query_qp,
4458 .req_notify_cq = hns_roce_v1_req_notify_cq,
4461 static const struct hns_roce_hw hns_roce_hw_v1 = {
4462 .reset = hns_roce_v1_reset,
4463 .hw_profile = hns_roce_v1_profile,
4464 .hw_init = hns_roce_v1_init,
4465 .hw_exit = hns_roce_v1_exit,
4466 .post_mbox = hns_roce_v1_post_mbox,
4467 .chk_mbox = hns_roce_v1_chk_mbox,
4468 .set_gid = hns_roce_v1_set_gid,
4469 .set_mac = hns_roce_v1_set_mac,
4470 .set_mtu = hns_roce_v1_set_mtu,
4471 .write_mtpt = hns_roce_v1_write_mtpt,
4472 .write_cqc = hns_roce_v1_write_cqc,
4473 .modify_cq = hns_roce_v1_modify_cq,
4474 .clear_hem = hns_roce_v1_clear_hem,
4475 .modify_qp = hns_roce_v1_modify_qp,
4476 .query_qp = hns_roce_v1_query_qp,
4477 .destroy_qp = hns_roce_v1_destroy_qp,
4478 .post_send = hns_roce_v1_post_send,
4479 .post_recv = hns_roce_v1_post_recv,
4480 .req_notify_cq = hns_roce_v1_req_notify_cq,
4481 .poll_cq = hns_roce_v1_poll_cq,
4482 .dereg_mr = hns_roce_v1_dereg_mr,
4483 .destroy_cq = hns_roce_v1_destroy_cq,
4484 .init_eq = hns_roce_v1_init_eq_table,
4485 .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4486 .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4489 static const struct of_device_id hns_roce_of_match[] = {
4490 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4493 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4495 static const struct acpi_device_id hns_roce_acpi_match[] = {
4496 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4499 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4501 static int hns_roce_node_match(struct device *dev, const void *fwnode)
4503 return dev->fwnode == fwnode;
4507 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4511 /* get the 'device' corresponding to the matching 'fwnode' */
4512 dev = bus_find_device(&platform_bus_type, NULL,
4513 fwnode, hns_roce_node_match);
4514 /* get the platform device */
4515 return dev ? to_platform_device(dev) : NULL;
4518 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4520 struct device *dev = &hr_dev->pdev->dev;
4521 struct platform_device *pdev = NULL;
4522 struct net_device *netdev = NULL;
4523 struct device_node *net_node;
4524 struct resource *res;
4530 /* check if we are compatible with the underlying SoC */
4531 if (dev_of_node(dev)) {
4532 const struct of_device_id *of_id;
4534 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4536 dev_err(dev, "device is not compatible!\n");
4539 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4541 dev_err(dev, "couldn't get H/W specific DT data!\n");
4544 } else if (is_acpi_device_node(dev->fwnode)) {
4545 const struct acpi_device_id *acpi_id;
4547 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4549 dev_err(dev, "device is not compatible!\n");
4552 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4554 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4558 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4562 /* get the mapped register base address */
4563 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4564 hr_dev->reg_base = devm_ioremap_resource(dev, res);
4565 if (IS_ERR(hr_dev->reg_base))
4566 return PTR_ERR(hr_dev->reg_base);
4568 /* read the node_guid of IB device from the DT or ACPI */
4569 ret = device_property_read_u8_array(dev, "node-guid",
4570 (u8 *)&hr_dev->ib_dev.node_guid,
4573 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4577 /* get the RoCE associated ethernet ports or netdevices */
4578 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4579 if (dev_of_node(dev)) {
4580 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4584 pdev = of_find_device_by_node(net_node);
4585 } else if (is_acpi_device_node(dev->fwnode)) {
4586 struct fwnode_reference_args args;
4588 ret = acpi_node_get_property_reference(dev->fwnode,
4593 pdev = hns_roce_find_pdev(args.fwnode);
4595 dev_err(dev, "cannot read data from DT or ACPI\n");
4600 netdev = platform_get_drvdata(pdev);
4603 hr_dev->iboe.netdevs[port_cnt] = netdev;
4604 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4606 dev_err(dev, "no netdev found with pdev %s\n",
4614 if (port_cnt == 0) {
4615 dev_err(dev, "unable to get eth-handle for available ports!\n");
4619 hr_dev->caps.num_ports = port_cnt;
4621 /* cmd issue mode: 0 is poll, 1 is event */
4622 hr_dev->cmd_mod = 1;
4623 hr_dev->loop_idc = 0;
4624 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4625 hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4627 /* read the interrupt names from the DT or ACPI */
4628 ret = device_property_read_string_array(dev, "interrupt-names",
4630 HNS_ROCE_V1_MAX_IRQ_NUM);
4632 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4636 /* fetch the interrupt numbers */
4637 for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4638 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4639 if (hr_dev->irq[i] <= 0) {
4640 dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4649 * hns_roce_probe - RoCE driver entrance
4650 * @pdev: pointer to platform device
4654 static int hns_roce_probe(struct platform_device *pdev)
4657 struct hns_roce_dev *hr_dev;
4658 struct device *dev = &pdev->dev;
4660 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4664 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4665 if (!hr_dev->priv) {
4667 goto error_failed_kzalloc;
4670 hr_dev->pdev = pdev;
4672 platform_set_drvdata(pdev, hr_dev);
4674 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4675 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4676 dev_err(dev, "Not usable DMA addressing mode\n");
4678 goto error_failed_get_cfg;
4681 ret = hns_roce_get_cfg(hr_dev);
4683 dev_err(dev, "Get Configuration failed!\n");
4684 goto error_failed_get_cfg;
4687 ret = hns_roce_init(hr_dev);
4689 dev_err(dev, "RoCE engine init failed!\n");
4690 goto error_failed_get_cfg;
4695 error_failed_get_cfg:
4696 kfree(hr_dev->priv);
4698 error_failed_kzalloc:
4699 ib_dealloc_device(&hr_dev->ib_dev);
4705 * hns_roce_remove - remove RoCE device
4706 * @pdev: pointer to platform device
4708 static int hns_roce_remove(struct platform_device *pdev)
4710 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4712 hns_roce_exit(hr_dev);
4713 kfree(hr_dev->priv);
4714 ib_dealloc_device(&hr_dev->ib_dev);
4719 static struct platform_driver hns_roce_driver = {
4720 .probe = hns_roce_probe,
4721 .remove = hns_roce_remove,
4724 .of_match_table = hns_roce_of_match,
4725 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4729 module_platform_driver(hns_roce_driver);
4731 MODULE_LICENSE("Dual BSD/GPL");
4732 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4733 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4734 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4735 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");