drivers/infiniband/hw/hns/hns_roce_hw_v1.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/platform_device.h>
  34 #include <linux/acpi.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <rdma/ib_umem.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include "hns_roce_cmd.h"
  43 #include "hns_roce_hem.h"
  44 #include "hns_roce_hw_v1.h"
  45
  46 /**
  47  * hns_get_gid_index - Get gid index.
  48  * @hr_dev: pointer to structure hns_roce_dev.
  49  * @port:  port, value range: 0 ~ MAX
  50  * @gid_index:  gid_index, value range: 0 ~ MAX
  51  * Description:
  52  *    N ports shared gids, allocation method as follow:
  53  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  54  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  55  *              And so on
  56  */
  57 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index)
  58 {
  59         return gid_index * hr_dev->caps.num_ports + port;
  60 }
  61
  62 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
  63 {
  64         dseg->lkey = cpu_to_le32(sg->lkey);
  65         dseg->addr = cpu_to_le64(sg->addr);
  66         dseg->len  = cpu_to_le32(sg->length);
  67 }
  68
  69 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
  70                           u32 rkey)
  71 {
  72         rseg->raddr = cpu_to_le64(remote_addr);
  73         rseg->rkey  = cpu_to_le32(rkey);
  74         rseg->len   = 0;
  75 }
  76
  77 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
  78                                  const struct ib_send_wr *wr,
  79                                  const struct ib_send_wr **bad_wr)
  80 {
  81         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  82         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
  83         struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
  84         struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
  85         struct hns_roce_wqe_data_seg *dseg = NULL;
  86         struct hns_roce_qp *qp = to_hr_qp(ibqp);
  87         struct device *dev = &hr_dev->pdev->dev;
  88         struct hns_roce_sq_db sq_db = {};
  89         int ps_opcode, i;
  90         unsigned long flags = 0;
  91         void *wqe = NULL;
  92         __le32 doorbell[2];
  93         int ret = 0;
  94         int loopback;
  95         u32 wqe_idx;
  96         int nreq;
  97         u8 *smac;
  98
  99         if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
 100                 ibqp->qp_type != IB_QPT_RC)) {
 101                 dev_err(dev, "un-supported QP type\n");
 102                 *bad_wr = NULL;
 103                 return -EOPNOTSUPP;
 104         }
 105
 106         spin_lock_irqsave(&qp->sq.lock, flags);
 107
 108         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 109                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
 110                         ret = -ENOMEM;
 111                         *bad_wr = wr;
 112                         goto out;
 113                 }
 114
 115                 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
 116
 117                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 118                         dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
 119                                 wr->num_sge, qp->sq.max_gs);
 120                         ret = -EINVAL;
 121                         *bad_wr = wr;
 122                         goto out;
 123                 }
 124
 125                 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
 126                 qp->sq.wrid[wqe_idx] = wr->wr_id;
 127
 128                 /* Corresponding to the RC and RD type wqe process separately */
 129                 if (ibqp->qp_type == IB_QPT_GSI) {
 130                         ud_sq_wqe = wqe;
 131                         roce_set_field(ud_sq_wqe->dmac_h,
 132                                        UD_SEND_WQE_U32_4_DMAC_0_M,
 133                                        UD_SEND_WQE_U32_4_DMAC_0_S,
 134                                        ah->av.mac[0]);
 135                         roce_set_field(ud_sq_wqe->dmac_h,
 136                                        UD_SEND_WQE_U32_4_DMAC_1_M,
 137                                        UD_SEND_WQE_U32_4_DMAC_1_S,
 138                                        ah->av.mac[1]);
 139                         roce_set_field(ud_sq_wqe->dmac_h,
 140                                        UD_SEND_WQE_U32_4_DMAC_2_M,
 141                                        UD_SEND_WQE_U32_4_DMAC_2_S,
 142                                        ah->av.mac[2]);
 143                         roce_set_field(ud_sq_wqe->dmac_h,
 144                                        UD_SEND_WQE_U32_4_DMAC_3_M,
 145                                        UD_SEND_WQE_U32_4_DMAC_3_S,
 146                                        ah->av.mac[3]);
 147
 148                         roce_set_field(ud_sq_wqe->u32_8,
 149                                        UD_SEND_WQE_U32_8_DMAC_4_M,
 150                                        UD_SEND_WQE_U32_8_DMAC_4_S,
 151                                        ah->av.mac[4]);
 152                         roce_set_field(ud_sq_wqe->u32_8,
 153                                        UD_SEND_WQE_U32_8_DMAC_5_M,
 154                                        UD_SEND_WQE_U32_8_DMAC_5_S,
 155                                        ah->av.mac[5]);
 156
 157                         smac = (u8 *)hr_dev->dev_addr[qp->port];
 158                         loopback = ether_addr_equal_unaligned(ah->av.mac,
 159                                                               smac) ? 1 : 0;
 160                         roce_set_bit(ud_sq_wqe->u32_8,
 161                                      UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
 162                                      loopback);
 163
 164                         roce_set_field(ud_sq_wqe->u32_8,
 165                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
 166                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
 167                                        HNS_ROCE_WQE_OPCODE_SEND);
 168                         roce_set_field(ud_sq_wqe->u32_8,
 169                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
 170                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
 171                                        2);
 172                         roce_set_bit(ud_sq_wqe->u32_8,
 173                                 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
 174                                 1);
 175
 176                         ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
 177                                 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 178                                 (wr->send_flags & IB_SEND_SOLICITED ?
 179                                 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 180                                 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
 181                                 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
 182
 183                         roce_set_field(ud_sq_wqe->u32_16,
 184                                        UD_SEND_WQE_U32_16_DEST_QP_M,
 185                                        UD_SEND_WQE_U32_16_DEST_QP_S,
 186                                        ud_wr(wr)->remote_qpn);
 187                         roce_set_field(ud_sq_wqe->u32_16,
 188                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
 189                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
 190                                        ah->av.stat_rate);
 191
 192                         roce_set_field(ud_sq_wqe->u32_36,
 193                                        UD_SEND_WQE_U32_36_FLOW_LABEL_M,
 194                                        UD_SEND_WQE_U32_36_FLOW_LABEL_S,
 195                                        ah->av.flowlabel);
 196                         roce_set_field(ud_sq_wqe->u32_36,
 197                                       UD_SEND_WQE_U32_36_PRIORITY_M,
 198                                       UD_SEND_WQE_U32_36_PRIORITY_S,
 199                                       ah->av.sl);
 200                         roce_set_field(ud_sq_wqe->u32_36,
 201                                        UD_SEND_WQE_U32_36_SGID_INDEX_M,
 202                                        UD_SEND_WQE_U32_36_SGID_INDEX_S,
 203                                        hns_get_gid_index(hr_dev, qp->phy_port,
 204                                                          ah->av.gid_index));
 205
 206                         roce_set_field(ud_sq_wqe->u32_40,
 207                                        UD_SEND_WQE_U32_40_HOP_LIMIT_M,
 208                                        UD_SEND_WQE_U32_40_HOP_LIMIT_S,
 209                                        ah->av.hop_limit);
 210                         roce_set_field(ud_sq_wqe->u32_40,
 211                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
 212                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
 213                                        ah->av.tclass);
 214
 215                         memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
 216
 217                         ud_sq_wqe->va0_l =
 218                                        cpu_to_le32((u32)wr->sg_list[0].addr);
 219                         ud_sq_wqe->va0_h =
 220                                        cpu_to_le32((wr->sg_list[0].addr) >> 32);
 221                         ud_sq_wqe->l_key0 =
 222                                        cpu_to_le32(wr->sg_list[0].lkey);
 223
 224                         ud_sq_wqe->va1_l =
 225                                        cpu_to_le32((u32)wr->sg_list[1].addr);
 226                         ud_sq_wqe->va1_h =
 227                                        cpu_to_le32((wr->sg_list[1].addr) >> 32);
 228                         ud_sq_wqe->l_key1 =
 229                                        cpu_to_le32(wr->sg_list[1].lkey);
 230                 } else if (ibqp->qp_type == IB_QPT_RC) {
 231                         u32 tmp_len = 0;
 232
 233                         ctrl = wqe;
 234                         memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
 235                         for (i = 0; i < wr->num_sge; i++)
 236                                 tmp_len += wr->sg_list[i].length;
 237
 238                         ctrl->msg_length =
 239                           cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
 240
 241                         ctrl->sgl_pa_h = 0;
 242                         ctrl->flag = 0;
 243
 244                         switch (wr->opcode) {
 245                         case IB_WR_SEND_WITH_IMM:
 246                         case IB_WR_RDMA_WRITE_WITH_IMM:
 247                                 ctrl->imm_data = wr->ex.imm_data;
 248                                 break;
 249                         case IB_WR_SEND_WITH_INV:
 250                                 ctrl->inv_key =
 251                                         cpu_to_le32(wr->ex.invalidate_rkey);
 252                                 break;
 253                         default:
 254                                 ctrl->imm_data = 0;
 255                                 break;
 256                         }
 257
 258                         /* Ctrl field, ctrl set type: sig, solic, imm, fence */
 259                         /* SO wait for conforming application scenarios */
 260                         ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
 261                                       cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 262                                       (wr->send_flags & IB_SEND_SOLICITED ?
 263                                       cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 264                                       ((wr->opcode == IB_WR_SEND_WITH_IMM ||
 265                                       wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
 266                                       cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
 267                                       (wr->send_flags & IB_SEND_FENCE ?
 268                                       (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
 269
 270                         wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
 271
 272                         switch (wr->opcode) {
 273                         case IB_WR_RDMA_READ:
 274                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
 275                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 276                                                rdma_wr(wr)->rkey);
 277                                 break;
 278                         case IB_WR_RDMA_WRITE:
 279                         case IB_WR_RDMA_WRITE_WITH_IMM:
 280                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
 281                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 282                                               rdma_wr(wr)->rkey);
 283                                 break;
 284                         case IB_WR_SEND:
 285                         case IB_WR_SEND_WITH_INV:
 286                         case IB_WR_SEND_WITH_IMM:
 287                                 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
 288                                 break;
 289                         case IB_WR_LOCAL_INV:
 290                         case IB_WR_ATOMIC_CMP_AND_SWP:
 291                         case IB_WR_ATOMIC_FETCH_AND_ADD:
 292                         case IB_WR_LSO:
 293                         default:
 294                                 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
 295                                 break;
 296                         }
 297                         ctrl->flag |= cpu_to_le32(ps_opcode);
 298                         wqe += sizeof(struct hns_roce_wqe_raddr_seg);
 299
 300                         dseg = wqe;
 301                         if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
 302                                 if (le32_to_cpu(ctrl->msg_length) >
 303                                     hr_dev->caps.max_sq_inline) {
 304                                         ret = -EINVAL;
 305                                         *bad_wr = wr;
 306                                         dev_err(dev, "inline len(1-%d)=%d, illegal",
 307                                                 le32_to_cpu(ctrl->msg_length),
 308                                                 hr_dev->caps.max_sq_inline);
 309                                         goto out;
 310                                 }
 311                                 for (i = 0; i < wr->num_sge; i++) {
 312                                         memcpy(wqe, ((void *) (uintptr_t)
 313                                                wr->sg_list[i].addr),
 314                                                wr->sg_list[i].length);
 315                                         wqe += wr->sg_list[i].length;
 316                                 }
 317                                 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
 318                         } else {
 319                                 /* sqe num is two */
 320                                 for (i = 0; i < wr->num_sge; i++)
 321                                         set_data_seg(dseg + i, wr->sg_list + i);
 322
 323                                 ctrl->flag |= cpu_to_le32(wr->num_sge <<
 324                                               HNS_ROCE_WQE_SGE_NUM_BIT);
 325                         }
 326                 }
 327         }
 328
 329 out:
 330         /* Set DB return */
 331         if (likely(nreq)) {
 332                 qp->sq.head += nreq;
 333
 334                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
 335                                SQ_DOORBELL_U32_4_SQ_HEAD_S,
 336                               (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
 337                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
 338                                SQ_DOORBELL_U32_4_SL_S, qp->sl);
 339                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
 340                                SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
 341                 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
 342                                SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
 343                 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
 344
 345                 doorbell[0] = sq_db.u32_4;
 346                 doorbell[1] = sq_db.u32_8;
 347
 348                 hns_roce_write64_k(doorbell, qp->sq.db_reg);
 349         }
 350
 351         spin_unlock_irqrestore(&qp->sq.lock, flags);
 352
 353         return ret;
 354 }
 355
 356 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
 357                                  const struct ib_recv_wr *wr,
 358                                  const struct ib_recv_wr **bad_wr)
 359 {
 360         struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
 361         struct hns_roce_wqe_data_seg *scat = NULL;
 362         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 363         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 364         struct device *dev = &hr_dev->pdev->dev;
 365         struct hns_roce_rq_db rq_db = {};
 366         __le32 doorbell[2] = {0};
 367         unsigned long flags = 0;
 368         unsigned int wqe_idx;
 369         int ret = 0;
 370         int nreq;
 371         int i;
 372         u32 reg_val;
 373
 374         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 375
 376         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 377                 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
 378                         hr_qp->ibqp.recv_cq)) {
 379                         ret = -ENOMEM;
 380                         *bad_wr = wr;
 381                         goto out;
 382                 }
 383
 384                 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
 385
 386                 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
 387                         dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
 388                                 wr->num_sge, hr_qp->rq.max_gs);
 389                         ret = -EINVAL;
 390                         *bad_wr = wr;
 391                         goto out;
 392                 }
 393
 394                 ctrl = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
 395
 396                 roce_set_field(ctrl->rwqe_byte_12,
 397                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
 398                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
 399                                wr->num_sge);
 400
 401                 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
 402
 403                 for (i = 0; i < wr->num_sge; i++)
 404                         set_data_seg(scat + i, wr->sg_list + i);
 405
 406                 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
 407         }
 408
 409 out:
 410         if (likely(nreq)) {
 411                 hr_qp->rq.head += nreq;
 412
 413                 if (ibqp->qp_type == IB_QPT_GSI) {
 414                         __le32 tmp;
 415
 416                         /* SW update GSI rq header */
 417                         reg_val = roce_read(to_hr_dev(ibqp->device),
 418                                             ROCEE_QP1C_CFG3_0_REG +
 419                                             QP1C_CFGN_OFFSET * hr_qp->phy_port);
 420                         tmp = cpu_to_le32(reg_val);
 421                         roce_set_field(tmp,
 422                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
 423                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
 424                                        hr_qp->rq.head);
 425                         reg_val = le32_to_cpu(tmp);
 426                         roce_write(to_hr_dev(ibqp->device),
 427                                    ROCEE_QP1C_CFG3_0_REG +
 428                                    QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
 429                 } else {
 430                         roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
 431                                        RQ_DOORBELL_U32_4_RQ_HEAD_S,
 432                                        hr_qp->rq.head);
 433                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
 434                                        RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
 435                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
 436                                        RQ_DOORBELL_U32_8_CMD_S, 1);
 437                         roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
 438                                      1);
 439
 440                         doorbell[0] = rq_db.u32_4;
 441                         doorbell[1] = rq_db.u32_8;
 442
 443                         hns_roce_write64_k(doorbell, hr_qp->rq.db_reg);
 444                 }
 445         }
 446         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 447
 448         return ret;
 449 }
 450
 451 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
 452                                        int sdb_mode, int odb_mode)
 453 {
 454         __le32 tmp;
 455         u32 val;
 456
 457         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 458         tmp = cpu_to_le32(val);
 459         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
 460         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
 461         val = le32_to_cpu(tmp);
 462         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 463 }
 464
 465 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
 466                                      u32 odb_mode)
 467 {
 468         __le32 tmp;
 469         u32 val;
 470
 471         /* Configure SDB/ODB extend mode */
 472         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 473         tmp = cpu_to_le32(val);
 474         roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
 475         roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
 476         val = le32_to_cpu(tmp);
 477         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 478 }
 479
 480 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
 481                              u32 sdb_alful)
 482 {
 483         __le32 tmp;
 484         u32 val;
 485
 486         /* Configure SDB */
 487         val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
 488         tmp = cpu_to_le32(val);
 489         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
 490                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
 491         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
 492                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
 493         val = le32_to_cpu(tmp);
 494         roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
 495 }
 496
 497 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
 498                              u32 odb_alful)
 499 {
 500         __le32 tmp;
 501         u32 val;
 502
 503         /* Configure ODB */
 504         val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
 505         tmp = cpu_to_le32(val);
 506         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
 507                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
 508         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
 509                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
 510         val = le32_to_cpu(tmp);
 511         roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
 512 }
 513
 514 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
 515                                  u32 ext_sdb_alful)
 516 {
 517         struct hns_roce_v1_priv *priv = hr_dev->priv;
 518         struct hns_roce_db_table *db = &priv->db_table;
 519         struct device *dev = &hr_dev->pdev->dev;
 520         dma_addr_t sdb_dma_addr;
 521         __le32 tmp;
 522         u32 val;
 523
 524         /* Configure extend SDB threshold */
 525         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
 526         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
 527
 528         /* Configure extend SDB base addr */
 529         sdb_dma_addr = db->ext_db->sdb_buf_list->map;
 530         roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
 531
 532         /* Configure extend SDB depth */
 533         val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
 534         tmp = cpu_to_le32(val);
 535         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
 536                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
 537                        db->ext_db->esdb_dep);
 538         /*
 539          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
 540          * using 4K page, and shift more 32 because of
 541          * calculating the high 32 bit value evaluated to hardware.
 542          */
 543         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
 544                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
 545         val = le32_to_cpu(tmp);
 546         roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
 547
 548         dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
 549         dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
 550                 ext_sdb_alept, ext_sdb_alful);
 551 }
 552
 553 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
 554                                  u32 ext_odb_alful)
 555 {
 556         struct hns_roce_v1_priv *priv = hr_dev->priv;
 557         struct hns_roce_db_table *db = &priv->db_table;
 558         struct device *dev = &hr_dev->pdev->dev;
 559         dma_addr_t odb_dma_addr;
 560         __le32 tmp;
 561         u32 val;
 562
 563         /* Configure extend ODB threshold */
 564         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
 565         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
 566
 567         /* Configure extend ODB base addr */
 568         odb_dma_addr = db->ext_db->odb_buf_list->map;
 569         roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
 570
 571         /* Configure extend ODB depth */
 572         val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
 573         tmp = cpu_to_le32(val);
 574         roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
 575                        ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
 576                        db->ext_db->eodb_dep);
 577         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
 578                        ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
 579                        db->ext_db->eodb_dep);
 580         val = le32_to_cpu(tmp);
 581         roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
 582
 583         dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
 584         dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
 585                 ext_odb_alept, ext_odb_alful);
 586 }
 587
 588 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
 589                                 u32 odb_ext_mod)
 590 {
 591         struct hns_roce_v1_priv *priv = hr_dev->priv;
 592         struct hns_roce_db_table *db = &priv->db_table;
 593         struct device *dev = &hr_dev->pdev->dev;
 594         dma_addr_t sdb_dma_addr;
 595         dma_addr_t odb_dma_addr;
 596         int ret = 0;
 597
 598         db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
 599         if (!db->ext_db)
 600                 return -ENOMEM;
 601
 602         if (sdb_ext_mod) {
 603                 db->ext_db->sdb_buf_list = kmalloc(
 604                                 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
 605                 if (!db->ext_db->sdb_buf_list) {
 606                         ret = -ENOMEM;
 607                         goto ext_sdb_buf_fail_out;
 608                 }
 609
 610                 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
 611                                                      HNS_ROCE_V1_EXT_SDB_SIZE,
 612                                                      &sdb_dma_addr, GFP_KERNEL);
 613                 if (!db->ext_db->sdb_buf_list->buf) {
 614                         ret = -ENOMEM;
 615                         goto alloc_sq_db_buf_fail;
 616                 }
 617                 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
 618
 619                 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
 620                 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
 621                                      HNS_ROCE_V1_EXT_SDB_ALFUL);
 622         } else
 623                 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
 624                                  HNS_ROCE_V1_SDB_ALFUL);
 625
 626         if (odb_ext_mod) {
 627                 db->ext_db->odb_buf_list = kmalloc(
 628                                 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
 629                 if (!db->ext_db->odb_buf_list) {
 630                         ret = -ENOMEM;
 631                         goto ext_odb_buf_fail_out;
 632                 }
 633
 634                 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
 635                                                      HNS_ROCE_V1_EXT_ODB_SIZE,
 636                                                      &odb_dma_addr, GFP_KERNEL);
 637                 if (!db->ext_db->odb_buf_list->buf) {
 638                         ret = -ENOMEM;
 639                         goto alloc_otr_db_buf_fail;
 640                 }
 641                 db->ext_db->odb_buf_list->map = odb_dma_addr;
 642
 643                 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
 644                 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
 645                                      HNS_ROCE_V1_EXT_ODB_ALFUL);
 646         } else
 647                 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
 648                                  HNS_ROCE_V1_ODB_ALFUL);
 649
 650         hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
 651
 652         return 0;
 653
 654 alloc_otr_db_buf_fail:
 655         kfree(db->ext_db->odb_buf_list);
 656
 657 ext_odb_buf_fail_out:
 658         if (sdb_ext_mod) {
 659                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
 660                                   db->ext_db->sdb_buf_list->buf,
 661                                   db->ext_db->sdb_buf_list->map);
 662         }
 663
 664 alloc_sq_db_buf_fail:
 665         if (sdb_ext_mod)
 666                 kfree(db->ext_db->sdb_buf_list);
 667
 668 ext_sdb_buf_fail_out:
 669         kfree(db->ext_db);
 670         return ret;
 671 }
 672
 673 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
 674                                                     struct ib_pd *pd)
 675 {
 676         struct device *dev = &hr_dev->pdev->dev;
 677         struct ib_qp_init_attr init_attr;
 678         struct ib_qp *qp;
 679
 680         memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
 681         init_attr.qp_type               = IB_QPT_RC;
 682         init_attr.sq_sig_type           = IB_SIGNAL_ALL_WR;
 683         init_attr.cap.max_recv_wr       = HNS_ROCE_MIN_WQE_NUM;
 684         init_attr.cap.max_send_wr       = HNS_ROCE_MIN_WQE_NUM;
 685
 686         qp = hns_roce_create_qp(pd, &init_attr, NULL);
 687         if (IS_ERR(qp)) {
 688                 dev_err(dev, "Create loop qp for mr free failed!");
 689                 return NULL;
 690         }
 691
 692         return to_hr_qp(qp);
 693 }
 694
 695 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 696 {
 697         struct hns_roce_v1_priv *priv = hr_dev->priv;
 698         struct hns_roce_free_mr *free_mr = &priv->free_mr;
 699         struct hns_roce_caps *caps = &hr_dev->caps;
 700         struct ib_device *ibdev = &hr_dev->ib_dev;
 701         struct device *dev = &hr_dev->pdev->dev;
 702         struct ib_cq_init_attr cq_init_attr;
 703         struct ib_qp_attr attr = { 0 };
 704         struct hns_roce_qp *hr_qp;
 705         struct ib_cq *cq;
 706         struct ib_pd *pd;
 707         union ib_gid dgid;
 708         __be64 subnet_prefix;
 709         int attr_mask = 0;
 710         int ret;
 711         int i, j;
 712         u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
 713         u8 phy_port;
 714         u32 port = 0;
 715         u8 sl;
 716
 717         /* Reserved cq for loop qp */
 718         cq_init_attr.cqe                = HNS_ROCE_MIN_WQE_NUM * 2;
 719         cq_init_attr.comp_vector        = 0;
 720
 721         cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
 722         if (!cq)
 723                 return -ENOMEM;
 724
 725         ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
 726         if (ret) {
 727                 dev_err(dev, "Create cq for reserved loop qp failed!");
 728                 goto alloc_cq_failed;
 729         }
 730         free_mr->mr_free_cq = to_hr_cq(cq);
 731         free_mr->mr_free_cq->ib_cq.device               = &hr_dev->ib_dev;
 732         free_mr->mr_free_cq->ib_cq.uobject              = NULL;
 733         free_mr->mr_free_cq->ib_cq.comp_handler         = NULL;
 734         free_mr->mr_free_cq->ib_cq.event_handler        = NULL;
 735         free_mr->mr_free_cq->ib_cq.cq_context           = NULL;
 736         atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
 737
 738         pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
 739         if (!pd) {
 740                 ret = -ENOMEM;
 741                 goto alloc_mem_failed;
 742         }
 743
 744         pd->device  = ibdev;
 745         ret = hns_roce_alloc_pd(pd, NULL);
 746         if (ret)
 747                 goto alloc_pd_failed;
 748
 749         free_mr->mr_free_pd = to_hr_pd(pd);
 750         free_mr->mr_free_pd->ibpd.device  = &hr_dev->ib_dev;
 751         free_mr->mr_free_pd->ibpd.uobject = NULL;
 752         free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
 753         atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
 754
 755         attr.qp_access_flags    = IB_ACCESS_REMOTE_WRITE;
 756         attr.pkey_index         = 0;
 757         attr.min_rnr_timer      = 0;
 758         /* Disable read ability */
 759         attr.max_dest_rd_atomic = 0;
 760         attr.max_rd_atomic      = 0;
 761         /* Use arbitrary values as rq_psn and sq_psn */
 762         attr.rq_psn             = 0x0808;
 763         attr.sq_psn             = 0x0808;
 764         attr.retry_cnt          = 7;
 765         attr.rnr_retry          = 7;
 766         attr.timeout            = 0x12;
 767         attr.path_mtu           = IB_MTU_256;
 768         attr.ah_attr.type       = RDMA_AH_ATTR_TYPE_ROCE;
 769         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
 770         rdma_ah_set_static_rate(&attr.ah_attr, 3);
 771
 772         subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 773         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 774                 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
 775                                 (i % HNS_ROCE_MAX_PORTS);
 776                 sl = i / HNS_ROCE_MAX_PORTS;
 777
 778                 for (j = 0; j < caps->num_ports; j++) {
 779                         if (hr_dev->iboe.phy_port[j] == phy_port) {
 780                                 queue_en[i] = 1;
 781                                 port = j;
 782                                 break;
 783                         }
 784                 }
 785
 786                 if (!queue_en[i])
 787                         continue;
 788
 789                 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
 790                 if (!free_mr->mr_free_qp[i]) {
 791                         dev_err(dev, "Create loop qp failed!\n");
 792                         ret = -ENOMEM;
 793                         goto create_lp_qp_failed;
 794                 }
 795                 hr_qp = free_mr->mr_free_qp[i];
 796
 797                 hr_qp->port             = port;
 798                 hr_qp->phy_port         = phy_port;
 799                 hr_qp->ibqp.qp_type     = IB_QPT_RC;
 800                 hr_qp->ibqp.device      = &hr_dev->ib_dev;
 801                 hr_qp->ibqp.uobject     = NULL;
 802                 atomic_set(&hr_qp->ibqp.usecnt, 0);
 803                 hr_qp->ibqp.pd          = pd;
 804                 hr_qp->ibqp.recv_cq     = cq;
 805                 hr_qp->ibqp.send_cq     = cq;
 806
 807                 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
 808                 rdma_ah_set_sl(&attr.ah_attr, sl);
 809                 attr.port_num           = port + 1;
 810
 811                 attr.dest_qp_num        = hr_qp->qpn;
 812                 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
 813                        hr_dev->dev_addr[port],
 814                        ETH_ALEN);
 815
 816                 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
 817                 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
 818                 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
 819                 dgid.raw[11] = 0xff;
 820                 dgid.raw[12] = 0xfe;
 821                 dgid.raw[8] ^= 2;
 822                 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
 823
 824                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 825                                             IB_QPS_RESET, IB_QPS_INIT);
 826                 if (ret) {
 827                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 828                         goto create_lp_qp_failed;
 829                 }
 830
 831                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
 832                                             IB_QPS_INIT, IB_QPS_RTR);
 833                 if (ret) {
 834                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 835                         goto create_lp_qp_failed;
 836                 }
 837
 838                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 839                                             IB_QPS_RTR, IB_QPS_RTS);
 840                 if (ret) {
 841                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 842                         goto create_lp_qp_failed;
 843                 }
 844         }
 845
 846         return 0;
 847
 848 create_lp_qp_failed:
 849         for (i -= 1; i >= 0; i--) {
 850                 hr_qp = free_mr->mr_free_qp[i];
 851                 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
 852                         dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
 853         }
 854
 855         hns_roce_dealloc_pd(pd, NULL);
 856
 857 alloc_pd_failed:
 858         kfree(pd);
 859
 860 alloc_mem_failed:
 861         hns_roce_destroy_cq(cq, NULL);
 862 alloc_cq_failed:
 863         kfree(cq);
 864         return ret;
 865 }
 866
 867 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
 868 {
 869         struct hns_roce_v1_priv *priv = hr_dev->priv;
 870         struct hns_roce_free_mr *free_mr = &priv->free_mr;
 871         struct device *dev = &hr_dev->pdev->dev;
 872         struct hns_roce_qp *hr_qp;
 873         int ret;
 874         int i;
 875
 876         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 877                 hr_qp = free_mr->mr_free_qp[i];
 878                 if (!hr_qp)
 879                         continue;
 880
 881                 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
 882                 if (ret)
 883                         dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
 884                                 i, ret);
 885         }
 886
 887         hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
 888         kfree(&free_mr->mr_free_cq->ib_cq);
 889         hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
 890         kfree(&free_mr->mr_free_pd->ibpd);
 891 }
 892
 893 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
 894 {
 895         struct hns_roce_v1_priv *priv = hr_dev->priv;
 896         struct hns_roce_db_table *db = &priv->db_table;
 897         struct device *dev = &hr_dev->pdev->dev;
 898         u32 sdb_ext_mod;
 899         u32 odb_ext_mod;
 900         u32 sdb_evt_mod;
 901         u32 odb_evt_mod;
 902         int ret;
 903
 904         memset(db, 0, sizeof(*db));
 905
 906         /* Default DB mode */
 907         sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
 908         odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
 909         sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
 910         odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
 911
 912         db->sdb_ext_mod = sdb_ext_mod;
 913         db->odb_ext_mod = odb_ext_mod;
 914
 915         /* Init extend DB */
 916         ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
 917         if (ret) {
 918                 dev_err(dev, "Failed in extend DB configuration.\n");
 919                 return ret;
 920         }
 921
 922         hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
 923
 924         return 0;
 925 }
 926
 927 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
 928 {
 929         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 930         struct hns_roce_dev *hr_dev;
 931
 932         lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
 933                                   work);
 934         hr_dev = to_hr_dev(lp_qp_work->ib_dev);
 935
 936         hns_roce_v1_release_lp_qp(hr_dev);
 937
 938         if (hns_roce_v1_rsv_lp_qp(hr_dev))
 939                 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
 940
 941         if (lp_qp_work->comp_flag)
 942                 complete(lp_qp_work->comp);
 943
 944         kfree(lp_qp_work);
 945 }
 946
 947 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
 948 {
 949         long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
 950         struct hns_roce_v1_priv *priv = hr_dev->priv;
 951         struct hns_roce_free_mr *free_mr = &priv->free_mr;
 952         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 953         struct device *dev = &hr_dev->pdev->dev;
 954         struct completion comp;
 955
 956         lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
 957                              GFP_KERNEL);
 958         if (!lp_qp_work)
 959                 return -ENOMEM;
 960
 961         INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
 962
 963         lp_qp_work->ib_dev = &(hr_dev->ib_dev);
 964         lp_qp_work->comp = &comp;
 965         lp_qp_work->comp_flag = 1;
 966
 967         init_completion(lp_qp_work->comp);
 968
 969         queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
 970
 971         while (end > 0) {
 972                 if (try_wait_for_completion(&comp))
 973                         return 0;
 974                 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
 975                 end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
 976         }
 977
 978         lp_qp_work->comp_flag = 0;
 979         if (try_wait_for_completion(&comp))
 980                 return 0;
 981
 982         dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
 983         return -ETIMEDOUT;
 984 }
 985
 986 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
 987 {
 988         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
 989         struct device *dev = &hr_dev->pdev->dev;
 990         struct ib_send_wr send_wr;
 991         const struct ib_send_wr *bad_wr;
 992         int ret;
 993
 994         memset(&send_wr, 0, sizeof(send_wr));
 995         send_wr.next    = NULL;
 996         send_wr.num_sge = 0;
 997         send_wr.send_flags = 0;
 998         send_wr.sg_list = NULL;
 999         send_wr.wr_id   = (unsigned long long)&send_wr;
1000         send_wr.opcode  = IB_WR_RDMA_WRITE;
1001
1002         ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1003         if (ret) {
1004                 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1005                 return ret;
1006         }
1007
1008         return 0;
1009 }
1010
1011 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1012 {
1013         unsigned long end =
1014                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1015         struct hns_roce_mr_free_work *mr_work =
1016                 container_of(work, struct hns_roce_mr_free_work, work);
1017         struct hns_roce_dev *hr_dev = to_hr_dev(mr_work->ib_dev);
1018         struct hns_roce_v1_priv *priv = hr_dev->priv;
1019         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1020         struct hns_roce_cq *mr_free_cq = free_mr->mr_free_cq;
1021         struct hns_roce_mr *hr_mr = mr_work->mr;
1022         struct device *dev = &hr_dev->pdev->dev;
1023         struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1024         struct hns_roce_qp *hr_qp;
1025         int ne = 0;
1026         int ret;
1027         int i;
1028
1029         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1030                 hr_qp = free_mr->mr_free_qp[i];
1031                 if (!hr_qp)
1032                         continue;
1033                 ne++;
1034
1035                 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1036                 if (ret) {
1037                         dev_err(dev,
1038                              "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1039                              hr_qp->qpn, ret);
1040                         goto free_work;
1041                 }
1042         }
1043
1044         if (!ne) {
1045                 dev_err(dev, "Reserved loop qp is absent!\n");
1046                 goto free_work;
1047         }
1048
1049         do {
1050                 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1051                 if (ret < 0 && hr_qp) {
1052                         dev_err(dev,
1053                            "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1054                            hr_qp->qpn, ret, hr_mr->key, ne);
1055                         goto free_work;
1056                 }
1057                 ne -= ret;
1058                 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1059                              (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1060         } while (ne && time_before_eq(jiffies, end));
1061
1062         if (ne != 0)
1063                 dev_err(dev,
1064                         "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1065                         hr_mr->key, ne);
1066
1067 free_work:
1068         if (mr_work->comp_flag)
1069                 complete(mr_work->comp);
1070         kfree(mr_work);
1071 }
1072
1073 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1074                                 struct hns_roce_mr *mr, struct ib_udata *udata)
1075 {
1076         struct hns_roce_v1_priv *priv = hr_dev->priv;
1077         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1078         long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1079         struct device *dev = &hr_dev->pdev->dev;
1080         struct hns_roce_mr_free_work *mr_work;
1081         unsigned long start = jiffies;
1082         struct completion comp;
1083         int ret = 0;
1084
1085         if (mr->enabled) {
1086                 if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
1087                                             key_to_hw_index(mr->key) &
1088                                             (hr_dev->caps.num_mtpts - 1)))
1089                         dev_warn(dev, "DESTROY_MPT failed!\n");
1090         }
1091
1092         mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1093         if (!mr_work) {
1094                 ret = -ENOMEM;
1095                 goto free_mr;
1096         }
1097
1098         INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1099
1100         mr_work->ib_dev = &(hr_dev->ib_dev);
1101         mr_work->comp = &comp;
1102         mr_work->comp_flag = 1;
1103         mr_work->mr = (void *)mr;
1104         init_completion(mr_work->comp);
1105
1106         queue_work(free_mr->free_mr_wq, &(mr_work->work));
1107
1108         while (end > 0) {
1109                 if (try_wait_for_completion(&comp))
1110                         goto free_mr;
1111                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1112                 end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1113         }
1114
1115         mr_work->comp_flag = 0;
1116         if (try_wait_for_completion(&comp))
1117                 goto free_mr;
1118
1119         dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1120         ret = -ETIMEDOUT;
1121
1122 free_mr:
1123         dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1124                 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1125
1126         hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1127                              key_to_hw_index(mr->key), 0);
1128         hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
1129         kfree(mr);
1130
1131         return ret;
1132 }
1133
1134 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1135 {
1136         struct hns_roce_v1_priv *priv = hr_dev->priv;
1137         struct hns_roce_db_table *db = &priv->db_table;
1138         struct device *dev = &hr_dev->pdev->dev;
1139
1140         if (db->sdb_ext_mod) {
1141                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1142                                   db->ext_db->sdb_buf_list->buf,
1143                                   db->ext_db->sdb_buf_list->map);
1144                 kfree(db->ext_db->sdb_buf_list);
1145         }
1146
1147         if (db->odb_ext_mod) {
1148                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1149                                   db->ext_db->odb_buf_list->buf,
1150                                   db->ext_db->odb_buf_list->map);
1151                 kfree(db->ext_db->odb_buf_list);
1152         }
1153
1154         kfree(db->ext_db);
1155 }
1156
1157 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1158 {
1159         struct hns_roce_v1_priv *priv = hr_dev->priv;
1160         struct hns_roce_raq_table *raq = &priv->raq_table;
1161         struct device *dev = &hr_dev->pdev->dev;
1162         dma_addr_t addr;
1163         int raq_shift;
1164         __le32 tmp;
1165         u32 val;
1166         int ret;
1167
1168         raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1169         if (!raq->e_raq_buf)
1170                 return -ENOMEM;
1171
1172         raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1173                                                  &addr, GFP_KERNEL);
1174         if (!raq->e_raq_buf->buf) {
1175                 ret = -ENOMEM;
1176                 goto err_dma_alloc_raq;
1177         }
1178         raq->e_raq_buf->map = addr;
1179
1180         /* Configure raq extended address. 48bit 4K align */
1181         roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1182
1183         /* Configure raq_shift */
1184         raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1185         val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1186         tmp = cpu_to_le32(val);
1187         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1188                        ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1189         /*
1190          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1191          * using 4K page, and shift more 32 because of
1192          * calculating the high 32 bit value evaluated to hardware.
1193          */
1194         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1195                        ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1196                        raq->e_raq_buf->map >> 44);
1197         val = le32_to_cpu(tmp);
1198         roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1199         dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1200
1201         /* Configure raq threshold */
1202         val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1203         tmp = cpu_to_le32(val);
1204         roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1205                        ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1206                        HNS_ROCE_V1_EXT_RAQ_WF);
1207         val = le32_to_cpu(tmp);
1208         roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1209         dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1210
1211         /* Enable extend raq */
1212         val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1213         tmp = cpu_to_le32(val);
1214         roce_set_field(tmp,
1215                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1216                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1217                        POL_TIME_INTERVAL_VAL);
1218         roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1219         roce_set_field(tmp,
1220                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1221                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1222                        2);
1223         roce_set_bit(tmp,
1224                      ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1225         val = le32_to_cpu(tmp);
1226         roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1227         dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1228
1229         /* Enable raq drop */
1230         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1231         tmp = cpu_to_le32(val);
1232         roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1233         val = le32_to_cpu(tmp);
1234         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1235         dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1236
1237         return 0;
1238
1239 err_dma_alloc_raq:
1240         kfree(raq->e_raq_buf);
1241         return ret;
1242 }
1243
1244 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1245 {
1246         struct hns_roce_v1_priv *priv = hr_dev->priv;
1247         struct hns_roce_raq_table *raq = &priv->raq_table;
1248         struct device *dev = &hr_dev->pdev->dev;
1249
1250         dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1251                           raq->e_raq_buf->map);
1252         kfree(raq->e_raq_buf);
1253 }
1254
1255 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1256 {
1257         __le32 tmp;
1258         u32 val;
1259
1260         if (enable_flag) {
1261                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1262                  /* Open all ports */
1263                 tmp = cpu_to_le32(val);
1264                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1265                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1266                                ALL_PORT_VAL_OPEN);
1267                 val = le32_to_cpu(tmp);
1268                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1269         } else {
1270                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1271                 /* Close all ports */
1272                 tmp = cpu_to_le32(val);
1273                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1274                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1275                 val = le32_to_cpu(tmp);
1276                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1277         }
1278 }
1279
1280 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1281 {
1282         struct hns_roce_v1_priv *priv = hr_dev->priv;
1283         struct device *dev = &hr_dev->pdev->dev;
1284         int ret;
1285
1286         priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1287                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1288                 GFP_KERNEL);
1289         if (!priv->bt_table.qpc_buf.buf)
1290                 return -ENOMEM;
1291
1292         priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1293                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1294                 GFP_KERNEL);
1295         if (!priv->bt_table.mtpt_buf.buf) {
1296                 ret = -ENOMEM;
1297                 goto err_failed_alloc_mtpt_buf;
1298         }
1299
1300         priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1301                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1302                 GFP_KERNEL);
1303         if (!priv->bt_table.cqc_buf.buf) {
1304                 ret = -ENOMEM;
1305                 goto err_failed_alloc_cqc_buf;
1306         }
1307
1308         return 0;
1309
1310 err_failed_alloc_cqc_buf:
1311         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1312                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1313
1314 err_failed_alloc_mtpt_buf:
1315         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1316                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1317
1318         return ret;
1319 }
1320
1321 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1322 {
1323         struct hns_roce_v1_priv *priv = hr_dev->priv;
1324         struct device *dev = &hr_dev->pdev->dev;
1325
1326         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1327                 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1328
1329         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1330                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1331
1332         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1333                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1334 }
1335
1336 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1337 {
1338         struct hns_roce_v1_priv *priv = hr_dev->priv;
1339         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1340         struct device *dev = &hr_dev->pdev->dev;
1341
1342         /*
1343          * This buffer will be used for CQ's tptr(tail pointer), also
1344          * named ci(customer index). Every CQ will use 2 bytes to save
1345          * cqe ci in hip06. Hardware will read this area to get new ci
1346          * when the queue is almost full.
1347          */
1348         tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1349                                            &tptr_buf->map, GFP_KERNEL);
1350         if (!tptr_buf->buf)
1351                 return -ENOMEM;
1352
1353         hr_dev->tptr_dma_addr = tptr_buf->map;
1354         hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1355
1356         return 0;
1357 }
1358
1359 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1360 {
1361         struct hns_roce_v1_priv *priv = hr_dev->priv;
1362         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1363         struct device *dev = &hr_dev->pdev->dev;
1364
1365         dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1366                           tptr_buf->buf, tptr_buf->map);
1367 }
1368
1369 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1370 {
1371         struct hns_roce_v1_priv *priv = hr_dev->priv;
1372         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1373         struct device *dev = &hr_dev->pdev->dev;
1374         int ret;
1375
1376         free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1377         if (!free_mr->free_mr_wq) {
1378                 dev_err(dev, "Create free mr workqueue failed!\n");
1379                 return -ENOMEM;
1380         }
1381
1382         ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1383         if (ret) {
1384                 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1385                 destroy_workqueue(free_mr->free_mr_wq);
1386         }
1387
1388         return ret;
1389 }
1390
1391 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1392 {
1393         struct hns_roce_v1_priv *priv = hr_dev->priv;
1394         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1395
1396         destroy_workqueue(free_mr->free_mr_wq);
1397
1398         hns_roce_v1_release_lp_qp(hr_dev);
1399 }
1400
1401 /**
1402  * hns_roce_v1_reset - reset RoCE
1403  * @hr_dev: RoCE device struct pointer
1404  * @dereset: true -- drop reset, false -- reset
1405  * return 0 - success , negative --fail
1406  */
1407 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1408 {
1409         struct device_node *dsaf_node;
1410         struct device *dev = &hr_dev->pdev->dev;
1411         struct device_node *np = dev->of_node;
1412         struct fwnode_handle *fwnode;
1413         int ret;
1414
1415         /* check if this is DT/ACPI case */
1416         if (dev_of_node(dev)) {
1417                 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1418                 if (!dsaf_node) {
1419                         dev_err(dev, "could not find dsaf-handle\n");
1420                         return -EINVAL;
1421                 }
1422                 fwnode = &dsaf_node->fwnode;
1423         } else if (is_acpi_device_node(dev->fwnode)) {
1424                 struct fwnode_reference_args args;
1425
1426                 ret = acpi_node_get_property_reference(dev->fwnode,
1427                                                        "dsaf-handle", 0, &args);
1428                 if (ret) {
1429                         dev_err(dev, "could not find dsaf-handle\n");
1430                         return ret;
1431                 }
1432                 fwnode = args.fwnode;
1433         } else {
1434                 dev_err(dev, "cannot read data from DT or ACPI\n");
1435                 return -ENXIO;
1436         }
1437
1438         ret = hns_dsaf_roce_reset(fwnode, false);
1439         if (ret)
1440                 return ret;
1441
1442         if (dereset) {
1443                 msleep(SLEEP_TIME_INTERVAL);
1444                 ret = hns_dsaf_roce_reset(fwnode, true);
1445         }
1446
1447         return ret;
1448 }
1449
1450 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1451 {
1452         struct hns_roce_caps *caps = &hr_dev->caps;
1453         int i;
1454
1455         hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1456         hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1457         hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1458                                 ((u64)roce_read(hr_dev,
1459                                             ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1460         hr_dev->hw_rev          = HNS_ROCE_HW_VER1;
1461
1462         caps->num_qps           = HNS_ROCE_V1_MAX_QP_NUM;
1463         caps->max_wqes          = HNS_ROCE_V1_MAX_WQE_NUM;
1464         caps->min_wqes          = HNS_ROCE_MIN_WQE_NUM;
1465         caps->num_cqs           = HNS_ROCE_V1_MAX_CQ_NUM;
1466         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1467         caps->max_cqes          = HNS_ROCE_V1_MAX_CQE_NUM;
1468         caps->max_sq_sg         = HNS_ROCE_V1_SG_NUM;
1469         caps->max_rq_sg         = HNS_ROCE_V1_SG_NUM;
1470         caps->max_sq_inline     = HNS_ROCE_V1_INLINE_SIZE;
1471         caps->num_uars          = HNS_ROCE_V1_UAR_NUM;
1472         caps->phy_num_uars      = HNS_ROCE_V1_PHY_UAR_NUM;
1473         caps->num_aeq_vectors   = HNS_ROCE_V1_AEQE_VEC_NUM;
1474         caps->num_comp_vectors  = HNS_ROCE_V1_COMP_VEC_NUM;
1475         caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1476         caps->num_mtpts         = HNS_ROCE_V1_MAX_MTPT_NUM;
1477         caps->num_mtt_segs      = HNS_ROCE_V1_MAX_MTT_SEGS;
1478         caps->num_pds           = HNS_ROCE_V1_MAX_PD_NUM;
1479         caps->max_qp_init_rdma  = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1480         caps->max_qp_dest_rdma  = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1481         caps->max_sq_desc_sz    = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1482         caps->max_rq_desc_sz    = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1483         caps->qpc_sz            = HNS_ROCE_V1_QPC_SIZE;
1484         caps->irrl_entry_sz     = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1485         caps->cqc_entry_sz      = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1486         caps->mtpt_entry_sz     = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1487         caps->mtt_entry_sz      = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1488         caps->cqe_sz            = HNS_ROCE_V1_CQE_SIZE;
1489         caps->page_size_cap     = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1490         caps->reserved_lkey     = 0;
1491         caps->reserved_pds      = 0;
1492         caps->reserved_mrws     = 1;
1493         caps->reserved_uars     = 0;
1494         caps->reserved_cqs      = 0;
1495         caps->reserved_qps      = 12; /* 2 SQP per port, six ports total 12 */
1496         caps->chunk_sz          = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1497
1498         for (i = 0; i < caps->num_ports; i++)
1499                 caps->pkey_table_len[i] = 1;
1500
1501         for (i = 0; i < caps->num_ports; i++) {
1502                 /* Six ports shared 16 GID in v1 engine */
1503                 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1504                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1505                                                  caps->num_ports;
1506                 else
1507                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1508                                                  caps->num_ports + 1;
1509         }
1510
1511         caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1512         caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1513         caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1514         caps->max_mtu = IB_MTU_2048;
1515
1516         return 0;
1517 }
1518
1519 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1520 {
1521         int ret;
1522         u32 val;
1523         __le32 tmp;
1524         struct device *dev = &hr_dev->pdev->dev;
1525
1526         /* DMAE user config */
1527         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1528         tmp = cpu_to_le32(val);
1529         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1530                        ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1531         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1532                        ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1533                        1 << PAGES_SHIFT_16);
1534         val = le32_to_cpu(tmp);
1535         roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1536
1537         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1538         tmp = cpu_to_le32(val);
1539         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1540                        ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1541         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1542                        ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1543                        1 << PAGES_SHIFT_16);
1544
1545         ret = hns_roce_db_init(hr_dev);
1546         if (ret) {
1547                 dev_err(dev, "doorbell init failed!\n");
1548                 return ret;
1549         }
1550
1551         ret = hns_roce_raq_init(hr_dev);
1552         if (ret) {
1553                 dev_err(dev, "raq init failed!\n");
1554                 goto error_failed_raq_init;
1555         }
1556
1557         ret = hns_roce_bt_init(hr_dev);
1558         if (ret) {
1559                 dev_err(dev, "bt init failed!\n");
1560                 goto error_failed_bt_init;
1561         }
1562
1563         ret = hns_roce_tptr_init(hr_dev);
1564         if (ret) {
1565                 dev_err(dev, "tptr init failed!\n");
1566                 goto error_failed_tptr_init;
1567         }
1568
1569         ret = hns_roce_free_mr_init(hr_dev);
1570         if (ret) {
1571                 dev_err(dev, "free mr init failed!\n");
1572                 goto error_failed_free_mr_init;
1573         }
1574
1575         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1576
1577         return 0;
1578
1579 error_failed_free_mr_init:
1580         hns_roce_tptr_free(hr_dev);
1581
1582 error_failed_tptr_init:
1583         hns_roce_bt_free(hr_dev);
1584
1585 error_failed_bt_init:
1586         hns_roce_raq_free(hr_dev);
1587
1588 error_failed_raq_init:
1589         hns_roce_db_free(hr_dev);
1590         return ret;
1591 }
1592
1593 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1594 {
1595         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1596         hns_roce_free_mr_free(hr_dev);
1597         hns_roce_tptr_free(hr_dev);
1598         hns_roce_bt_free(hr_dev);
1599         hns_roce_raq_free(hr_dev);
1600         hns_roce_db_free(hr_dev);
1601 }
1602
1603 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1604 {
1605         u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1606
1607         return (!!(status & (1 << HCR_GO_BIT)));
1608 }
1609
1610 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1611                                  u64 out_param, u32 in_modifier, u8 op_modifier,
1612                                  u16 op, u16 token, int event)
1613 {
1614         u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1615         unsigned long end;
1616         u32 val = 0;
1617         __le32 tmp;
1618
1619         end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1620         while (hns_roce_v1_cmd_pending(hr_dev)) {
1621                 if (time_after(jiffies, end)) {
1622                         dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1623                                 (int)jiffies, (int)end);
1624                         return -EAGAIN;
1625                 }
1626                 cond_resched();
1627         }
1628
1629         tmp = cpu_to_le32(val);
1630         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1631                        op);
1632         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1633                        ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1634         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1635         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1636         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1637                        ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1638
1639         val = le32_to_cpu(tmp);
1640         writeq(in_param, hcr + 0);
1641         writeq(out_param, hcr + 2);
1642         writel(in_modifier, hcr + 4);
1643         /* Memory barrier */
1644         wmb();
1645
1646         writel(val, hcr + 5);
1647
1648         return 0;
1649 }
1650
1651 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1652                                 unsigned int timeout)
1653 {
1654         u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1655         unsigned long end;
1656         u32 status = 0;
1657
1658         end = msecs_to_jiffies(timeout) + jiffies;
1659         while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1660                 cond_resched();
1661
1662         if (hns_roce_v1_cmd_pending(hr_dev)) {
1663                 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1664                 return -ETIMEDOUT;
1665         }
1666
1667         status = le32_to_cpu((__force __le32)
1668                               __raw_readl(hcr + HCR_STATUS_OFFSET));
1669         if ((status & STATUS_MASK) != 0x1) {
1670                 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1671                 return -EBUSY;
1672         }
1673
1674         return 0;
1675 }
1676
1677 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u32 port,
1678                                int gid_index, const union ib_gid *gid,
1679                                const struct ib_gid_attr *attr)
1680 {
1681         unsigned long flags;
1682         u32 *p = NULL;
1683         u8 gid_idx;
1684
1685         gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1686
1687         spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1688
1689         p = (u32 *)&gid->raw[0];
1690         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1691                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1692
1693         p = (u32 *)&gid->raw[4];
1694         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1695                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1696
1697         p = (u32 *)&gid->raw[8];
1698         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1699                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1700
1701         p = (u32 *)&gid->raw[0xc];
1702         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1703                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1704
1705         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1706
1707         return 0;
1708 }
1709
1710 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1711                                u8 *addr)
1712 {
1713         u32 reg_smac_l;
1714         u16 reg_smac_h;
1715         __le32 tmp;
1716         u16 *p_h;
1717         u32 *p;
1718         u32 val;
1719
1720         /*
1721          * When mac changed, loopback may fail
1722          * because of smac not equal to dmac.
1723          * We Need to release and create reserved qp again.
1724          */
1725         if (hr_dev->hw->dereg_mr) {
1726                 int ret;
1727
1728                 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1729                 if (ret && ret != -ETIMEDOUT)
1730                         return ret;
1731         }
1732
1733         p = (u32 *)(&addr[0]);
1734         reg_smac_l = *p;
1735         roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1736                        PHY_PORT_OFFSET * phy_port);
1737
1738         val = roce_read(hr_dev,
1739                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1740         tmp = cpu_to_le32(val);
1741         p_h = (u16 *)(&addr[4]);
1742         reg_smac_h  = *p_h;
1743         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1744                        ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1745         val = le32_to_cpu(tmp);
1746         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1747                    val);
1748
1749         return 0;
1750 }
1751
1752 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1753                                 enum ib_mtu mtu)
1754 {
1755         __le32 tmp;
1756         u32 val;
1757
1758         val = roce_read(hr_dev,
1759                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1760         tmp = cpu_to_le32(val);
1761         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1762                        ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1763         val = le32_to_cpu(tmp);
1764         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1765                    val);
1766 }
1767
1768 static int hns_roce_v1_write_mtpt(struct hns_roce_dev *hr_dev, void *mb_buf,
1769                                   struct hns_roce_mr *mr,
1770                                   unsigned long mtpt_idx)
1771 {
1772         u64 pages[HNS_ROCE_MAX_INNER_MTPT_NUM] = { 0 };
1773         struct ib_device *ibdev = &hr_dev->ib_dev;
1774         struct hns_roce_v1_mpt_entry *mpt_entry;
1775         dma_addr_t pbl_ba;
1776         int count;
1777         int i;
1778
1779         /* MPT filled into mailbox buf */
1780         mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1781         memset(mpt_entry, 0, sizeof(*mpt_entry));
1782
1783         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1784                        MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1785         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1786                        MPT_BYTE_4_KEY_S, mr->key);
1787         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1788                        MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1789         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1790         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1791                      (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1792         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1793         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1794                        MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1795         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1796         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1797                      (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1798         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1799                      (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1800         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1801                      (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1802         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1803                      0);
1804         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1805
1806         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1807                        MPT_BYTE_12_PBL_ADDR_H_S, 0);
1808         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1809                        MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1810
1811         mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1812         mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1813         mpt_entry->length = cpu_to_le32((u32)mr->size);
1814
1815         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1816                        MPT_BYTE_28_PD_S, mr->pd);
1817         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1818                        MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1819         roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1820                        MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1821
1822         /* DMA memory register */
1823         if (mr->type == MR_TYPE_DMA)
1824                 return 0;
1825
1826         count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
1827                                   ARRAY_SIZE(pages), &pbl_ba);
1828         if (count < 1) {
1829                 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.", count);
1830                 return -ENOBUFS;
1831         }
1832
1833         /* Register user mr */
1834         for (i = 0; i < count; i++) {
1835                 switch (i) {
1836                 case 0:
1837                         mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1838                         roce_set_field(mpt_entry->mpt_byte_36,
1839                                 MPT_BYTE_36_PA0_H_M,
1840                                 MPT_BYTE_36_PA0_H_S,
1841                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1842                         break;
1843                 case 1:
1844                         roce_set_field(mpt_entry->mpt_byte_36,
1845                                        MPT_BYTE_36_PA1_L_M,
1846                                        MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1847                         roce_set_field(mpt_entry->mpt_byte_40,
1848                                 MPT_BYTE_40_PA1_H_M,
1849                                 MPT_BYTE_40_PA1_H_S,
1850                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1851                         break;
1852                 case 2:
1853                         roce_set_field(mpt_entry->mpt_byte_40,
1854                                        MPT_BYTE_40_PA2_L_M,
1855                                        MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1856                         roce_set_field(mpt_entry->mpt_byte_44,
1857                                 MPT_BYTE_44_PA2_H_M,
1858                                 MPT_BYTE_44_PA2_H_S,
1859                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1860                         break;
1861                 case 3:
1862                         roce_set_field(mpt_entry->mpt_byte_44,
1863                                        MPT_BYTE_44_PA3_L_M,
1864                                        MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1865                         roce_set_field(mpt_entry->mpt_byte_48,
1866                                 MPT_BYTE_48_PA3_H_M,
1867                                 MPT_BYTE_48_PA3_H_S,
1868                                 (u32)(pages[i] >> PAGES_SHIFT_8));
1869                         break;
1870                 case 4:
1871                         mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1872                         roce_set_field(mpt_entry->mpt_byte_56,
1873                                 MPT_BYTE_56_PA4_H_M,
1874                                 MPT_BYTE_56_PA4_H_S,
1875                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1876                         break;
1877                 case 5:
1878                         roce_set_field(mpt_entry->mpt_byte_56,
1879                                        MPT_BYTE_56_PA5_L_M,
1880                                        MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1881                         roce_set_field(mpt_entry->mpt_byte_60,
1882                                 MPT_BYTE_60_PA5_H_M,
1883                                 MPT_BYTE_60_PA5_H_S,
1884                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1885                         break;
1886                 case 6:
1887                         roce_set_field(mpt_entry->mpt_byte_60,
1888                                        MPT_BYTE_60_PA6_L_M,
1889                                        MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1890                         roce_set_field(mpt_entry->mpt_byte_64,
1891                                 MPT_BYTE_64_PA6_H_M,
1892                                 MPT_BYTE_64_PA6_H_S,
1893                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1894                         break;
1895                 default:
1896                         break;
1897                 }
1898         }
1899
1900         mpt_entry->pbl_addr_l = cpu_to_le32(pbl_ba);
1901         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1902                        MPT_BYTE_12_PBL_ADDR_H_S, upper_32_bits(pbl_ba));
1903
1904         return 0;
1905 }
1906
1907 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1908 {
1909         return hns_roce_buf_offset(hr_cq->mtr.kmem, n * HNS_ROCE_V1_CQE_SIZE);
1910 }
1911
1912 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1913 {
1914         struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1915
1916         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1917         return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1918                 !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
1919 }
1920
1921 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1922 {
1923         return get_sw_cqe(hr_cq, hr_cq->cons_index);
1924 }
1925
1926 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1927 {
1928         __le32 doorbell[2];
1929
1930         doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
1931         doorbell[1] = 0;
1932         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1933         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1934                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1935         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1936                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1937         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1938                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1939
1940         hns_roce_write64_k(doorbell, hr_cq->db_reg);
1941 }
1942
1943 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1944                                    struct hns_roce_srq *srq)
1945 {
1946         struct hns_roce_cqe *cqe, *dest;
1947         u32 prod_index;
1948         int nfreed = 0;
1949         u8 owner_bit;
1950
1951         for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1952              ++prod_index) {
1953                 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1954                         break;
1955         }
1956
1957         /*
1958          * Now backwards through the CQ, removing CQ entries
1959          * that match our QP by overwriting them with next entries.
1960          */
1961         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1962                 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1963                 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1964                                      CQE_BYTE_16_LOCAL_QPN_S) &
1965                                      HNS_ROCE_CQE_QPN_MASK) == qpn) {
1966                         /* In v1 engine, not support SRQ */
1967                         ++nfreed;
1968                 } else if (nfreed) {
1969                         dest = get_cqe(hr_cq, (prod_index + nfreed) &
1970                                        hr_cq->ib_cq.cqe);
1971                         owner_bit = roce_get_bit(dest->cqe_byte_4,
1972                                                  CQE_BYTE_4_OWNER_S);
1973                         memcpy(dest, cqe, sizeof(*cqe));
1974                         roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1975                                      owner_bit);
1976                 }
1977         }
1978
1979         if (nfreed) {
1980                 hr_cq->cons_index += nfreed;
1981                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
1982         }
1983 }
1984
1985 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1986                                  struct hns_roce_srq *srq)
1987 {
1988         spin_lock_irq(&hr_cq->lock);
1989         __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
1990         spin_unlock_irq(&hr_cq->lock);
1991 }
1992
1993 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1994                                   struct hns_roce_cq *hr_cq, void *mb_buf,
1995                                   u64 *mtts, dma_addr_t dma_handle)
1996 {
1997         struct hns_roce_v1_priv *priv = hr_dev->priv;
1998         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1999         struct hns_roce_cq_context *cq_context = mb_buf;
2000         dma_addr_t tptr_dma_addr;
2001         int offset;
2002
2003         memset(cq_context, 0, sizeof(*cq_context));
2004
2005         /* Get the tptr for this CQ. */
2006         offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2007         tptr_dma_addr = tptr_buf->map + offset;
2008         hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2009
2010         /* Register cq_context members */
2011         roce_set_field(cq_context->cqc_byte_4,
2012                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2013                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2014         roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2015                        CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2016
2017         cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2018
2019         roce_set_field(cq_context->cqc_byte_12,
2020                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2021                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2022                        ((u64)dma_handle >> 32));
2023         roce_set_field(cq_context->cqc_byte_12,
2024                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2025                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2026                        ilog2(hr_cq->cq_depth));
2027         roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2028                        CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2029
2030         cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2031
2032         roce_set_field(cq_context->cqc_byte_20,
2033                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2034                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2035         /* Dedicated hardware, directly set 0 */
2036         roce_set_field(cq_context->cqc_byte_20,
2037                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2038                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2039         /**
2040          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2041          * using 4K page, and shift more 32 because of
2042          * calculating the high 32 bit value evaluated to hardware.
2043          */
2044         roce_set_field(cq_context->cqc_byte_20,
2045                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2046                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2047                        tptr_dma_addr >> 44);
2048
2049         cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2050
2051         roce_set_field(cq_context->cqc_byte_32,
2052                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2053                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2054         roce_set_bit(cq_context->cqc_byte_32,
2055                      CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2056         roce_set_bit(cq_context->cqc_byte_32,
2057                      CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2058         roce_set_bit(cq_context->cqc_byte_32,
2059                      CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2060         roce_set_bit(cq_context->cqc_byte_32,
2061                      CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2062                      0);
2063         /* The initial value of cq's ci is 0 */
2064         roce_set_field(cq_context->cqc_byte_32,
2065                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2066                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2067 }
2068
2069 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2070                                      enum ib_cq_notify_flags flags)
2071 {
2072         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2073         u32 notification_flag;
2074         __le32 doorbell[2] = {};
2075
2076         notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2077                             IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2078         /*
2079          * flags = 0; Notification Flag = 1, next
2080          * flags = 1; Notification Flag = 0, solocited
2081          */
2082         doorbell[0] =
2083                 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2084         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2085         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2086                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2087         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2088                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2089         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2090                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2091                        hr_cq->cqn | notification_flag);
2092
2093         hns_roce_write64_k(doorbell, hr_cq->db_reg);
2094
2095         return 0;
2096 }
2097
2098 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2099                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2100 {
2101         int qpn;
2102         int is_send;
2103         u16 wqe_ctr;
2104         u32 status;
2105         u32 opcode;
2106         struct hns_roce_cqe *cqe;
2107         struct hns_roce_qp *hr_qp;
2108         struct hns_roce_wq *wq;
2109         struct hns_roce_wqe_ctrl_seg *sq_wqe;
2110         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2111         struct device *dev = &hr_dev->pdev->dev;
2112
2113         /* Find cqe according consumer index */
2114         cqe = next_cqe_sw(hr_cq);
2115         if (!cqe)
2116                 return -EAGAIN;
2117
2118         ++hr_cq->cons_index;
2119         /* Memory barrier */
2120         rmb();
2121         /* 0->SQ, 1->RQ */
2122         is_send  = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2123
2124         /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2125         if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2126                            CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2127                 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2128                                      CQE_BYTE_20_PORT_NUM_S) +
2129                       roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2130                                      CQE_BYTE_16_LOCAL_QPN_S) *
2131                                      HNS_ROCE_MAX_PORTS;
2132         } else {
2133                 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2134                                      CQE_BYTE_16_LOCAL_QPN_S);
2135         }
2136
2137         if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2138                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2139                 if (unlikely(!hr_qp)) {
2140                         dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2141                                 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2142                         return -EINVAL;
2143                 }
2144
2145                 *cur_qp = hr_qp;
2146         }
2147
2148         wc->qp = &(*cur_qp)->ibqp;
2149         wc->vendor_err = 0;
2150
2151         status = roce_get_field(cqe->cqe_byte_4,
2152                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2153                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2154                                 HNS_ROCE_CQE_STATUS_MASK;
2155         switch (status) {
2156         case HNS_ROCE_CQE_SUCCESS:
2157                 wc->status = IB_WC_SUCCESS;
2158                 break;
2159         case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2160                 wc->status = IB_WC_LOC_LEN_ERR;
2161                 break;
2162         case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2163                 wc->status = IB_WC_LOC_QP_OP_ERR;
2164                 break;
2165         case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2166                 wc->status = IB_WC_LOC_PROT_ERR;
2167                 break;
2168         case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2169                 wc->status = IB_WC_WR_FLUSH_ERR;
2170                 break;
2171         case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2172                 wc->status = IB_WC_MW_BIND_ERR;
2173                 break;
2174         case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2175                 wc->status = IB_WC_BAD_RESP_ERR;
2176                 break;
2177         case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2178                 wc->status = IB_WC_LOC_ACCESS_ERR;
2179                 break;
2180         case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2181                 wc->status = IB_WC_REM_INV_REQ_ERR;
2182                 break;
2183         case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2184                 wc->status = IB_WC_REM_ACCESS_ERR;
2185                 break;
2186         case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2187                 wc->status = IB_WC_REM_OP_ERR;
2188                 break;
2189         case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2190                 wc->status = IB_WC_RETRY_EXC_ERR;
2191                 break;
2192         case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2193                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2194                 break;
2195         default:
2196                 wc->status = IB_WC_GENERAL_ERR;
2197                 break;
2198         }
2199
2200         /* CQE status error, directly return */
2201         if (wc->status != IB_WC_SUCCESS)
2202                 return 0;
2203
2204         if (is_send) {
2205                 /* SQ conrespond to CQE */
2206                 sq_wqe = hns_roce_get_send_wqe(*cur_qp,
2207                                                 roce_get_field(cqe->cqe_byte_4,
2208                                                 CQE_BYTE_4_WQE_INDEX_M,
2209                                                 CQE_BYTE_4_WQE_INDEX_S) &
2210                                                 ((*cur_qp)->sq.wqe_cnt-1));
2211                 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2212                 case HNS_ROCE_WQE_OPCODE_SEND:
2213                         wc->opcode = IB_WC_SEND;
2214                         break;
2215                 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2216                         wc->opcode = IB_WC_RDMA_READ;
2217                         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2218                         break;
2219                 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2220                         wc->opcode = IB_WC_RDMA_WRITE;
2221                         break;
2222                 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2223                         wc->opcode = IB_WC_LOCAL_INV;
2224                         break;
2225                 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2226                         wc->opcode = IB_WC_SEND;
2227                         break;
2228                 default:
2229                         wc->status = IB_WC_GENERAL_ERR;
2230                         break;
2231                 }
2232                 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2233                                 IB_WC_WITH_IMM : 0);
2234
2235                 wq = &(*cur_qp)->sq;
2236                 if ((*cur_qp)->sq_signal_bits) {
2237                         /*
2238                          * If sg_signal_bit is 1,
2239                          * firstly tail pointer updated to wqe
2240                          * which current cqe correspond to
2241                          */
2242                         wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2243                                                       CQE_BYTE_4_WQE_INDEX_M,
2244                                                       CQE_BYTE_4_WQE_INDEX_S);
2245                         wq->tail += (wqe_ctr - (u16)wq->tail) &
2246                                     (wq->wqe_cnt - 1);
2247                 }
2248                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2249                 ++wq->tail;
2250         } else {
2251                 /* RQ conrespond to CQE */
2252                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2253                 opcode = roce_get_field(cqe->cqe_byte_4,
2254                                         CQE_BYTE_4_OPERATION_TYPE_M,
2255                                         CQE_BYTE_4_OPERATION_TYPE_S) &
2256                                         HNS_ROCE_CQE_OPCODE_MASK;
2257                 switch (opcode) {
2258                 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2259                         wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2260                         wc->wc_flags = IB_WC_WITH_IMM;
2261                         wc->ex.imm_data =
2262                                 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2263                         break;
2264                 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2265                         if (roce_get_bit(cqe->cqe_byte_4,
2266                                          CQE_BYTE_4_IMM_INDICATOR_S)) {
2267                                 wc->opcode = IB_WC_RECV;
2268                                 wc->wc_flags = IB_WC_WITH_IMM;
2269                                 wc->ex.imm_data = cpu_to_be32(
2270                                         le32_to_cpu(cqe->immediate_data));
2271                         } else {
2272                                 wc->opcode = IB_WC_RECV;
2273                                 wc->wc_flags = 0;
2274                         }
2275                         break;
2276                 default:
2277                         wc->status = IB_WC_GENERAL_ERR;
2278                         break;
2279                 }
2280
2281                 /* Update tail pointer, record wr_id */
2282                 wq = &(*cur_qp)->rq;
2283                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2284                 ++wq->tail;
2285                 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2286                                             CQE_BYTE_20_SL_S);
2287                 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2288                                                 CQE_BYTE_20_REMOTE_QPN_M,
2289                                                 CQE_BYTE_20_REMOTE_QPN_S);
2290                 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2291                                               CQE_BYTE_20_GRH_PRESENT_S) ?
2292                                               IB_WC_GRH : 0);
2293                 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2294                                                      CQE_BYTE_28_P_KEY_IDX_M,
2295                                                      CQE_BYTE_28_P_KEY_IDX_S);
2296         }
2297
2298         return 0;
2299 }
2300
2301 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2302 {
2303         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2304         struct hns_roce_qp *cur_qp = NULL;
2305         unsigned long flags;
2306         int npolled;
2307         int ret;
2308
2309         spin_lock_irqsave(&hr_cq->lock, flags);
2310
2311         for (npolled = 0; npolled < num_entries; ++npolled) {
2312                 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2313                 if (ret)
2314                         break;
2315         }
2316
2317         if (npolled) {
2318                 *hr_cq->tptr_addr = hr_cq->cons_index &
2319                         ((hr_cq->cq_depth << 1) - 1);
2320
2321                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2322         }
2323
2324         spin_unlock_irqrestore(&hr_cq->lock, flags);
2325
2326         if (ret == 0 || ret == -EAGAIN)
2327                 return npolled;
2328         else
2329                 return ret;
2330 }
2331
2332 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2333                                  struct hns_roce_hem_table *table, int obj,
2334                                  int step_idx)
2335 {
2336         struct hns_roce_v1_priv *priv = hr_dev->priv;
2337         struct device *dev = &hr_dev->pdev->dev;
2338         long end = HW_SYNC_TIMEOUT_MSECS;
2339         __le32 bt_cmd_val[2] = {0};
2340         unsigned long flags = 0;
2341         void __iomem *bt_cmd;
2342         u64 bt_ba = 0;
2343
2344         switch (table->type) {
2345         case HEM_TYPE_QPC:
2346                 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2347                 break;
2348         case HEM_TYPE_MTPT:
2349                 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2350                 break;
2351         case HEM_TYPE_CQC:
2352                 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2353                 break;
2354         case HEM_TYPE_SRQC:
2355                 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2356                 return -EINVAL;
2357         default:
2358                 return 0;
2359         }
2360         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2361                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2362         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2363                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2364         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2365         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2366
2367         spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2368
2369         bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2370
2371         while (1) {
2372                 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2373                         if (!end) {
2374                                 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2375                                 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2376                                         flags);
2377                                 return -EBUSY;
2378                         }
2379                 } else {
2380                         break;
2381                 }
2382                 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
2383                 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2384         }
2385
2386         bt_cmd_val[0] = cpu_to_le32(bt_ba);
2387         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2388                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2389         hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2390
2391         spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2392
2393         return 0;
2394 }
2395
2396 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2397                                  enum hns_roce_qp_state cur_state,
2398                                  enum hns_roce_qp_state new_state,
2399                                  struct hns_roce_qp_context *context,
2400                                  struct hns_roce_qp *hr_qp)
2401 {
2402         static const u16
2403         op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2404                 [HNS_ROCE_QP_STATE_RST] = {
2405                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2406                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2407                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2408                 },
2409                 [HNS_ROCE_QP_STATE_INIT] = {
2410                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2411                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2412                 /* Note: In v1 engine, HW doesn't support RST2INIT.
2413                  * We use RST2INIT cmd instead of INIT2INIT.
2414                  */
2415                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2416                 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2417                 },
2418                 [HNS_ROCE_QP_STATE_RTR] = {
2419                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2420                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2421                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2422                 },
2423                 [HNS_ROCE_QP_STATE_RTS] = {
2424                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2425                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2426                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2427                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2428                 },
2429                 [HNS_ROCE_QP_STATE_SQD] = {
2430                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2431                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2432                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2433                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2434                 },
2435                 [HNS_ROCE_QP_STATE_ERR] = {
2436                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2437                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2438                 }
2439         };
2440
2441         struct hns_roce_cmd_mailbox *mailbox;
2442         struct device *dev = &hr_dev->pdev->dev;
2443         int ret;
2444
2445         if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2446             new_state >= HNS_ROCE_QP_NUM_STATE ||
2447             !op[cur_state][new_state]) {
2448                 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2449                         cur_state, new_state);
2450                 return -EINVAL;
2451         }
2452
2453         if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2454                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2455                                          HNS_ROCE_CMD_2RST_QP,
2456                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2457
2458         if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2459                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2460                                          HNS_ROCE_CMD_2ERR_QP,
2461                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2462
2463         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2464         if (IS_ERR(mailbox))
2465                 return PTR_ERR(mailbox);
2466
2467         memcpy(mailbox->buf, context, sizeof(*context));
2468
2469         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2470                                 op[cur_state][new_state],
2471                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
2472
2473         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2474         return ret;
2475 }
2476
2477 static int find_wqe_mtt(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
2478                         u64 *sq_ba, u64 *rq_ba, dma_addr_t *bt_ba)
2479 {
2480         struct ib_device *ibdev = &hr_dev->ib_dev;
2481         int count;
2482
2483         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, sq_ba, 1, bt_ba);
2484         if (count < 1) {
2485                 ibdev_err(ibdev, "Failed to find SQ ba\n");
2486                 return -ENOBUFS;
2487         }
2488
2489         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, rq_ba,
2490                                   1, NULL);
2491         if (!count) {
2492                 ibdev_err(ibdev, "Failed to find RQ ba\n");
2493                 return -ENOBUFS;
2494         }
2495
2496         return 0;
2497 }
2498
2499 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2500                              int attr_mask, enum ib_qp_state cur_state,
2501                              enum ib_qp_state new_state)
2502 {
2503         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2504         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2505         struct hns_roce_sqp_context *context;
2506         dma_addr_t dma_handle = 0;
2507         u32 __iomem *addr;
2508         u64 sq_ba = 0;
2509         u64 rq_ba = 0;
2510         __le32 tmp;
2511         u32 reg_val;
2512
2513         context = kzalloc(sizeof(*context), GFP_KERNEL);
2514         if (!context)
2515                 return -ENOMEM;
2516
2517         /* Search QP buf's MTTs */
2518         if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2519                 goto out;
2520
2521         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2522                 roce_set_field(context->qp1c_bytes_4,
2523                                QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2524                                QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2525                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2526                 roce_set_field(context->qp1c_bytes_4,
2527                                QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2528                                QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2529                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2530                 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2531                                QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2532
2533                 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2534                 roce_set_field(context->qp1c_bytes_12,
2535                                QP1C_BYTES_12_SQ_RQ_BT_H_M,
2536                                QP1C_BYTES_12_SQ_RQ_BT_H_S,
2537                                upper_32_bits(dma_handle));
2538
2539                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2540                                QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2541                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2542                                QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2543                 roce_set_bit(context->qp1c_bytes_16,
2544                              QP1C_BYTES_16_SIGNALING_TYPE_S,
2545                              hr_qp->sq_signal_bits);
2546                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2547                              1);
2548                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2549                              1);
2550                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2551                              0);
2552
2553                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2554                                QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2555                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2556                                QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2557
2558                 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2559
2560                 roce_set_field(context->qp1c_bytes_28,
2561                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2562                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2563                                upper_32_bits(rq_ba));
2564                 roce_set_field(context->qp1c_bytes_28,
2565                                QP1C_BYTES_28_RQ_CUR_IDX_M,
2566                                QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2567
2568                 roce_set_field(context->qp1c_bytes_32,
2569                                QP1C_BYTES_32_RX_CQ_NUM_M,
2570                                QP1C_BYTES_32_RX_CQ_NUM_S,
2571                                to_hr_cq(ibqp->recv_cq)->cqn);
2572                 roce_set_field(context->qp1c_bytes_32,
2573                                QP1C_BYTES_32_TX_CQ_NUM_M,
2574                                QP1C_BYTES_32_TX_CQ_NUM_S,
2575                                to_hr_cq(ibqp->send_cq)->cqn);
2576
2577                 context->cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
2578
2579                 roce_set_field(context->qp1c_bytes_40,
2580                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2581                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2582                                upper_32_bits(sq_ba));
2583                 roce_set_field(context->qp1c_bytes_40,
2584                                QP1C_BYTES_40_SQ_CUR_IDX_M,
2585                                QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2586
2587                 /* Copy context to QP1C register */
2588                 addr = (u32 __iomem *)(hr_dev->reg_base +
2589                                        ROCEE_QP1C_CFG0_0_REG +
2590                                        hr_qp->phy_port * sizeof(*context));
2591
2592                 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2593                 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2594                 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2595                 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2596                 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2597                 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2598                 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2599                 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2600                 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2601                 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2602         }
2603
2604         /* Modify QP1C status */
2605         reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2606                             hr_qp->phy_port * sizeof(*context));
2607         tmp = cpu_to_le32(reg_val);
2608         roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2609                        ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2610         reg_val = le32_to_cpu(tmp);
2611         roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2612                     hr_qp->phy_port * sizeof(*context), reg_val);
2613
2614         hr_qp->state = new_state;
2615         if (new_state == IB_QPS_RESET) {
2616                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2617                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2618                 if (ibqp->send_cq != ibqp->recv_cq)
2619                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2620                                              hr_qp->qpn, NULL);
2621
2622                 hr_qp->rq.head = 0;
2623                 hr_qp->rq.tail = 0;
2624                 hr_qp->sq.head = 0;
2625                 hr_qp->sq.tail = 0;
2626         }
2627
2628         kfree(context);
2629         return 0;
2630
2631 out:
2632         kfree(context);
2633         return -EINVAL;
2634 }
2635
2636 static bool check_qp_state(enum ib_qp_state cur_state,
2637                            enum ib_qp_state new_state)
2638 {
2639         static const bool sm[][IB_QPS_ERR + 1] = {
2640                 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
2641                                    [IB_QPS_INIT] = true },
2642                 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
2643                                   [IB_QPS_INIT] = true,
2644                                   [IB_QPS_RTR] = true,
2645                                   [IB_QPS_ERR] = true },
2646                 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
2647                                  [IB_QPS_RTS] = true,
2648                                  [IB_QPS_ERR] = true },
2649                 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
2650                 [IB_QPS_SQD] = {},
2651                 [IB_QPS_SQE] = {},
2652                 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
2653         };
2654
2655         return sm[cur_state][new_state];
2656 }
2657
2658 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2659                             int attr_mask, enum ib_qp_state cur_state,
2660                             enum ib_qp_state new_state)
2661 {
2662         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2663         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2664         struct device *dev = &hr_dev->pdev->dev;
2665         struct hns_roce_qp_context *context;
2666         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2667         dma_addr_t dma_handle_2 = 0;
2668         dma_addr_t dma_handle = 0;
2669         __le32 doorbell[2] = {0};
2670         u64 *mtts_2 = NULL;
2671         int ret = -EINVAL;
2672         u64 sq_ba = 0;
2673         u64 rq_ba = 0;
2674         u32 port;
2675         u32 port_num;
2676         u8 *dmac;
2677         u8 *smac;
2678
2679         if (!check_qp_state(cur_state, new_state)) {
2680                 ibdev_err(ibqp->device,
2681                           "not support QP(%u) status from %d to %d\n",
2682                           ibqp->qp_num, cur_state, new_state);
2683                 return -EINVAL;
2684         }
2685
2686         context = kzalloc(sizeof(*context), GFP_KERNEL);
2687         if (!context)
2688                 return -ENOMEM;
2689
2690         /* Search qp buf's mtts */
2691         if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2692                 goto out;
2693
2694         /* Search IRRL's mtts */
2695         mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2696                                      hr_qp->qpn, &dma_handle_2);
2697         if (mtts_2 == NULL) {
2698                 dev_err(dev, "qp irrl_table find failed\n");
2699                 goto out;
2700         }
2701
2702         /*
2703          * Reset to init
2704          *      Mandatory param:
2705          *      IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2706          *      Optional param: NA
2707          */
2708         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2709                 roce_set_field(context->qpc_bytes_4,
2710                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2711                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2712                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2713
2714                 roce_set_bit(context->qpc_bytes_4,
2715                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2716                 roce_set_bit(context->qpc_bytes_4,
2717                              QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2718                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2719                 roce_set_bit(context->qpc_bytes_4,
2720                              QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2721                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2722                              );
2723                 roce_set_bit(context->qpc_bytes_4,
2724                              QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2725                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2726                              );
2727                 roce_set_bit(context->qpc_bytes_4,
2728                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2729                 roce_set_field(context->qpc_bytes_4,
2730                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2731                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2732                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2733                 roce_set_field(context->qpc_bytes_4,
2734                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2735                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2736                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2737                 roce_set_field(context->qpc_bytes_4,
2738                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2739                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2740                                to_hr_pd(ibqp->pd)->pdn);
2741                 hr_qp->access_flags = attr->qp_access_flags;
2742                 roce_set_field(context->qpc_bytes_8,
2743                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2744                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2745                                to_hr_cq(ibqp->send_cq)->cqn);
2746                 roce_set_field(context->qpc_bytes_8,
2747                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2748                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2749                                to_hr_cq(ibqp->recv_cq)->cqn);
2750
2751                 if (ibqp->srq)
2752                         roce_set_field(context->qpc_bytes_12,
2753                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2754                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2755                                        to_hr_srq(ibqp->srq)->srqn);
2756
2757                 roce_set_field(context->qpc_bytes_12,
2758                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2759                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2760                                attr->pkey_index);
2761                 hr_qp->pkey_index = attr->pkey_index;
2762                 roce_set_field(context->qpc_bytes_16,
2763                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2764                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2765         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2766                 roce_set_field(context->qpc_bytes_4,
2767                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2768                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2769                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2770                 roce_set_bit(context->qpc_bytes_4,
2771                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2772                 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2773                         roce_set_bit(context->qpc_bytes_4,
2774                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2775                                      !!(attr->qp_access_flags &
2776                                      IB_ACCESS_REMOTE_READ));
2777                         roce_set_bit(context->qpc_bytes_4,
2778                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2779                                      !!(attr->qp_access_flags &
2780                                      IB_ACCESS_REMOTE_WRITE));
2781                 } else {
2782                         roce_set_bit(context->qpc_bytes_4,
2783                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2784                                      !!(hr_qp->access_flags &
2785                                      IB_ACCESS_REMOTE_READ));
2786                         roce_set_bit(context->qpc_bytes_4,
2787                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2788                                      !!(hr_qp->access_flags &
2789                                      IB_ACCESS_REMOTE_WRITE));
2790                 }
2791
2792                 roce_set_bit(context->qpc_bytes_4,
2793                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2794                 roce_set_field(context->qpc_bytes_4,
2795                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2796                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2797                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2798                 roce_set_field(context->qpc_bytes_4,
2799                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2800                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2801                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2802                 roce_set_field(context->qpc_bytes_4,
2803                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2804                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2805                                to_hr_pd(ibqp->pd)->pdn);
2806
2807                 roce_set_field(context->qpc_bytes_8,
2808                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2809                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2810                                to_hr_cq(ibqp->send_cq)->cqn);
2811                 roce_set_field(context->qpc_bytes_8,
2812                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2813                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2814                                to_hr_cq(ibqp->recv_cq)->cqn);
2815
2816                 if (ibqp->srq)
2817                         roce_set_field(context->qpc_bytes_12,
2818                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2819                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2820                                        to_hr_srq(ibqp->srq)->srqn);
2821                 if (attr_mask & IB_QP_PKEY_INDEX)
2822                         roce_set_field(context->qpc_bytes_12,
2823                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2824                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2825                                        attr->pkey_index);
2826                 else
2827                         roce_set_field(context->qpc_bytes_12,
2828                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2829                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2830                                        hr_qp->pkey_index);
2831
2832                 roce_set_field(context->qpc_bytes_16,
2833                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2834                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2835         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2836                 if ((attr_mask & IB_QP_ALT_PATH) ||
2837                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2838                     (attr_mask & IB_QP_PKEY_INDEX) ||
2839                     (attr_mask & IB_QP_QKEY)) {
2840                         dev_err(dev, "INIT2RTR attr_mask error\n");
2841                         goto out;
2842                 }
2843
2844                 dmac = (u8 *)attr->ah_attr.roce.dmac;
2845
2846                 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2847                 roce_set_field(context->qpc_bytes_24,
2848                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2849                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2850                                upper_32_bits(dma_handle));
2851                 roce_set_bit(context->qpc_bytes_24,
2852                              QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2853                              1);
2854                 roce_set_field(context->qpc_bytes_24,
2855                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2856                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2857                                attr->min_rnr_timer);
2858                 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2859                 roce_set_field(context->qpc_bytes_32,
2860                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2861                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2862                                ((u32)(dma_handle_2 >> 32)) &
2863                                 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2864                 roce_set_field(context->qpc_bytes_32,
2865                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2866                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2867                 roce_set_bit(context->qpc_bytes_32,
2868                              QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2869                              1);
2870                 roce_set_bit(context->qpc_bytes_32,
2871                              QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2872                              hr_qp->sq_signal_bits);
2873
2874                 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2875                         hr_qp->port;
2876                 smac = (u8 *)hr_dev->dev_addr[port];
2877                 /* when dmac equals smac or loop_idc is 1, it should loopback */
2878                 if (ether_addr_equal_unaligned(dmac, smac) ||
2879                     hr_dev->loop_idc == 0x1)
2880                         roce_set_bit(context->qpc_bytes_32,
2881                               QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2882
2883                 roce_set_bit(context->qpc_bytes_32,
2884                              QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2885                              rdma_ah_get_ah_flags(&attr->ah_attr));
2886                 roce_set_field(context->qpc_bytes_32,
2887                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2888                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2889                                ilog2((unsigned int)attr->max_dest_rd_atomic));
2890
2891                 if (attr_mask & IB_QP_DEST_QPN)
2892                         roce_set_field(context->qpc_bytes_36,
2893                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2894                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2895                                        attr->dest_qp_num);
2896
2897                 /* Configure GID index */
2898                 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2899                 roce_set_field(context->qpc_bytes_36,
2900                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2901                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2902                                 hns_get_gid_index(hr_dev,
2903                                                   port_num - 1,
2904                                                   grh->sgid_index));
2905
2906                 memcpy(&(context->dmac_l), dmac, 4);
2907
2908                 roce_set_field(context->qpc_bytes_44,
2909                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2910                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2911                                *((u16 *)(&dmac[4])));
2912                 roce_set_field(context->qpc_bytes_44,
2913                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2914                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2915                                rdma_ah_get_static_rate(&attr->ah_attr));
2916                 roce_set_field(context->qpc_bytes_44,
2917                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2918                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2919                                grh->hop_limit);
2920
2921                 roce_set_field(context->qpc_bytes_48,
2922                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2923                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2924                                grh->flow_label);
2925                 roce_set_field(context->qpc_bytes_48,
2926                                QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2927                                QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2928                                grh->traffic_class);
2929                 roce_set_field(context->qpc_bytes_48,
2930                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
2931                                QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2932
2933                 memcpy(context->dgid, grh->dgid.raw,
2934                        sizeof(grh->dgid.raw));
2935
2936                 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2937                         roce_get_field(context->qpc_bytes_44,
2938                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2939                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2940
2941                 roce_set_field(context->qpc_bytes_68,
2942                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2943                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2944                                hr_qp->rq.head);
2945                 roce_set_field(context->qpc_bytes_68,
2946                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2947                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2948
2949                 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2950
2951                 roce_set_field(context->qpc_bytes_76,
2952                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2953                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2954                         upper_32_bits(rq_ba));
2955                 roce_set_field(context->qpc_bytes_76,
2956                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2957                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2958
2959                 context->rx_rnr_time = 0;
2960
2961                 roce_set_field(context->qpc_bytes_84,
2962                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2963                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2964                                attr->rq_psn - 1);
2965                 roce_set_field(context->qpc_bytes_84,
2966                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2967                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2968
2969                 roce_set_field(context->qpc_bytes_88,
2970                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2971                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2972                                attr->rq_psn);
2973                 roce_set_bit(context->qpc_bytes_88,
2974                              QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2975                 roce_set_bit(context->qpc_bytes_88,
2976                              QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2977                 roce_set_field(context->qpc_bytes_88,
2978                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2979                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2980                         0);
2981                 roce_set_field(context->qpc_bytes_88,
2982                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2983                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2984                                0);
2985
2986                 context->dma_length = 0;
2987                 context->r_key = 0;
2988                 context->va_l = 0;
2989                 context->va_h = 0;
2990
2991                 roce_set_field(context->qpc_bytes_108,
2992                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2993                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2994                 roce_set_bit(context->qpc_bytes_108,
2995                              QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2996                 roce_set_bit(context->qpc_bytes_108,
2997                              QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
2998
2999                 roce_set_field(context->qpc_bytes_112,
3000                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3001                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3002                 roce_set_field(context->qpc_bytes_112,
3003                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3004                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3005
3006                 /* For chip resp ack */
3007                 roce_set_field(context->qpc_bytes_156,
3008                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3009                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3010                                hr_qp->phy_port);
3011                 roce_set_field(context->qpc_bytes_156,
3012                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3013                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3014                                rdma_ah_get_sl(&attr->ah_attr));
3015                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3016         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3017                 /* If exist optional param, return error */
3018                 if ((attr_mask & IB_QP_ALT_PATH) ||
3019                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
3020                     (attr_mask & IB_QP_QKEY) ||
3021                     (attr_mask & IB_QP_PATH_MIG_STATE) ||
3022                     (attr_mask & IB_QP_CUR_STATE) ||
3023                     (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3024                         dev_err(dev, "RTR2RTS attr_mask error\n");
3025                         goto out;
3026                 }
3027
3028                 context->rx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3029
3030                 roce_set_field(context->qpc_bytes_120,
3031                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3032                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3033                                upper_32_bits(sq_ba));
3034
3035                 roce_set_field(context->qpc_bytes_124,
3036                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3037                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3038                 roce_set_field(context->qpc_bytes_124,
3039                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3040                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3041
3042                 roce_set_field(context->qpc_bytes_128,
3043                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3044                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3045                                attr->sq_psn);
3046                 roce_set_bit(context->qpc_bytes_128,
3047                              QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3048                 roce_set_field(context->qpc_bytes_128,
3049                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3050                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3051                              0);
3052                 roce_set_bit(context->qpc_bytes_128,
3053                              QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3054
3055                 roce_set_field(context->qpc_bytes_132,
3056                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3057                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3058                 roce_set_field(context->qpc_bytes_132,
3059                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3060                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3061
3062                 roce_set_field(context->qpc_bytes_136,
3063                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3064                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3065                                attr->sq_psn);
3066                 roce_set_field(context->qpc_bytes_136,
3067                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3068                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3069                                attr->sq_psn);
3070
3071                 roce_set_field(context->qpc_bytes_140,
3072                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3073                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3074                                (attr->sq_psn >> SQ_PSN_SHIFT));
3075                 roce_set_field(context->qpc_bytes_140,
3076                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3077                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3078                 roce_set_bit(context->qpc_bytes_140,
3079                              QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3080
3081                 roce_set_field(context->qpc_bytes_148,
3082                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3083                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3084                 roce_set_field(context->qpc_bytes_148,
3085                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3086                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3087                                attr->retry_cnt);
3088                 roce_set_field(context->qpc_bytes_148,
3089                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3090                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3091                                attr->rnr_retry);
3092                 roce_set_field(context->qpc_bytes_148,
3093                                QP_CONTEXT_QPC_BYTES_148_LSN_M,
3094                                QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3095
3096                 context->rnr_retry = 0;
3097
3098                 roce_set_field(context->qpc_bytes_156,
3099                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3100                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3101                                attr->retry_cnt);
3102                 if (attr->timeout < 0x12) {
3103                         dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3104                                  attr->timeout);
3105                         roce_set_field(context->qpc_bytes_156,
3106                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3107                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3108                                        0x12);
3109                 } else {
3110                         roce_set_field(context->qpc_bytes_156,
3111                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3112                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3113                                        attr->timeout);
3114                 }
3115                 roce_set_field(context->qpc_bytes_156,
3116                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3117                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3118                                attr->rnr_retry);
3119                 roce_set_field(context->qpc_bytes_156,
3120                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3121                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3122                                hr_qp->phy_port);
3123                 roce_set_field(context->qpc_bytes_156,
3124                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3125                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3126                                rdma_ah_get_sl(&attr->ah_attr));
3127                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3128                 roce_set_field(context->qpc_bytes_156,
3129                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3130                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3131                                ilog2((unsigned int)attr->max_rd_atomic));
3132                 roce_set_field(context->qpc_bytes_156,
3133                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3134                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3135                 context->pkt_use_len = 0;
3136
3137                 roce_set_field(context->qpc_bytes_164,
3138                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3139                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3140                 roce_set_field(context->qpc_bytes_164,
3141                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3142                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3143
3144                 roce_set_field(context->qpc_bytes_168,
3145                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3146                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3147                                attr->sq_psn);
3148                 roce_set_field(context->qpc_bytes_168,
3149                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3150                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3151                 roce_set_field(context->qpc_bytes_168,
3152                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3153                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3154                 roce_set_bit(context->qpc_bytes_168,
3155                              QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3156                 roce_set_bit(context->qpc_bytes_168,
3157                              QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3158                 roce_set_bit(context->qpc_bytes_168,
3159                              QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3160                 context->sge_use_len = 0;
3161
3162                 roce_set_field(context->qpc_bytes_176,
3163                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3164                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3165                 roce_set_field(context->qpc_bytes_176,
3166                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3167                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3168                                0);
3169                 roce_set_field(context->qpc_bytes_180,
3170                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3171                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3172                 roce_set_field(context->qpc_bytes_180,
3173                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3174                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3175
3176                 context->tx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3177
3178                 roce_set_field(context->qpc_bytes_188,
3179                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3180                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3181                                upper_32_bits(sq_ba));
3182                 roce_set_bit(context->qpc_bytes_188,
3183                              QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3184                 roce_set_field(context->qpc_bytes_188,
3185                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3186                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3187                                0);
3188         }
3189
3190         /* Every status migrate must change state */
3191         roce_set_field(context->qpc_bytes_144,
3192                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3193                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3194
3195         /* SW pass context to HW */
3196         ret = hns_roce_v1_qp_modify(hr_dev, to_hns_roce_state(cur_state),
3197                                     to_hns_roce_state(new_state), context,
3198                                     hr_qp);
3199         if (ret) {
3200                 dev_err(dev, "hns_roce_qp_modify failed\n");
3201                 goto out;
3202         }
3203
3204         /*
3205          * Use rst2init to instead of init2init with drv,
3206          * need to hw to flash RQ HEAD by DB again
3207          */
3208         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3209                 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3210                                RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3211                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3212                                RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3213                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3214                                RQ_DOORBELL_U32_8_CMD_S, 1);
3215                 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3216
3217                 if (ibqp->uobject) {
3218                         hr_qp->rq.db_reg = hr_dev->reg_base +
3219                                      hr_dev->odb_offset +
3220                                      DB_REG_OFFSET * hr_dev->priv_uar.index;
3221                 }
3222
3223                 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg);
3224         }
3225
3226         hr_qp->state = new_state;
3227
3228         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3229                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3230         if (attr_mask & IB_QP_PORT) {
3231                 hr_qp->port = attr->port_num - 1;
3232                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3233         }
3234
3235         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3236                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3237                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3238                 if (ibqp->send_cq != ibqp->recv_cq)
3239                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3240                                              hr_qp->qpn, NULL);
3241
3242                 hr_qp->rq.head = 0;
3243                 hr_qp->rq.tail = 0;
3244                 hr_qp->sq.head = 0;
3245                 hr_qp->sq.tail = 0;
3246         }
3247 out:
3248         kfree(context);
3249         return ret;
3250 }
3251
3252 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3253                                  const struct ib_qp_attr *attr, int attr_mask,
3254                                  enum ib_qp_state cur_state,
3255                                  enum ib_qp_state new_state)
3256 {
3257         if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
3258                 return -EOPNOTSUPP;
3259
3260         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3261                 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3262                                          new_state);
3263         else
3264                 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3265                                         new_state);
3266 }
3267
3268 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3269 {
3270         switch (state) {
3271         case HNS_ROCE_QP_STATE_RST:
3272                 return IB_QPS_RESET;
3273         case HNS_ROCE_QP_STATE_INIT:
3274                 return IB_QPS_INIT;
3275         case HNS_ROCE_QP_STATE_RTR:
3276                 return IB_QPS_RTR;
3277         case HNS_ROCE_QP_STATE_RTS:
3278                 return IB_QPS_RTS;
3279         case HNS_ROCE_QP_STATE_SQD:
3280                 return IB_QPS_SQD;
3281         case HNS_ROCE_QP_STATE_ERR:
3282                 return IB_QPS_ERR;
3283         default:
3284                 return IB_QPS_ERR;
3285         }
3286 }
3287
3288 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3289                                  struct hns_roce_qp *hr_qp,
3290                                  struct hns_roce_qp_context *hr_context)
3291 {
3292         struct hns_roce_cmd_mailbox *mailbox;
3293         int ret;
3294
3295         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3296         if (IS_ERR(mailbox))
3297                 return PTR_ERR(mailbox);
3298
3299         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3300                                 HNS_ROCE_CMD_QUERY_QP,
3301                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
3302         if (!ret)
3303                 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3304         else
3305                 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3306
3307         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3308
3309         return ret;
3310 }
3311
3312 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3313                              int qp_attr_mask,
3314                              struct ib_qp_init_attr *qp_init_attr)
3315 {
3316         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3317         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3318         struct hns_roce_sqp_context context;
3319         u32 addr;
3320
3321         mutex_lock(&hr_qp->mutex);
3322
3323         if (hr_qp->state == IB_QPS_RESET) {
3324                 qp_attr->qp_state = IB_QPS_RESET;
3325                 goto done;
3326         }
3327
3328         addr = ROCEE_QP1C_CFG0_0_REG +
3329                 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3330         context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3331         context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3332         context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3333         context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3334         context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3335         context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3336         context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3337         context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3338         context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3339         context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3340
3341         hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3342                                       QP1C_BYTES_4_QP_STATE_M,
3343                                       QP1C_BYTES_4_QP_STATE_S);
3344         qp_attr->qp_state       = hr_qp->state;
3345         qp_attr->path_mtu       = IB_MTU_256;
3346         qp_attr->path_mig_state = IB_MIG_ARMED;
3347         qp_attr->qkey           = QKEY_VAL;
3348         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3349         qp_attr->rq_psn         = 0;
3350         qp_attr->sq_psn         = 0;
3351         qp_attr->dest_qp_num    = 1;
3352         qp_attr->qp_access_flags = 6;
3353
3354         qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3355                                              QP1C_BYTES_20_PKEY_IDX_M,
3356                                              QP1C_BYTES_20_PKEY_IDX_S);
3357         qp_attr->port_num = hr_qp->port + 1;
3358         qp_attr->sq_draining = 0;
3359         qp_attr->max_rd_atomic = 0;
3360         qp_attr->max_dest_rd_atomic = 0;
3361         qp_attr->min_rnr_timer = 0;
3362         qp_attr->timeout = 0;
3363         qp_attr->retry_cnt = 0;
3364         qp_attr->rnr_retry = 0;
3365         qp_attr->alt_timeout = 0;
3366
3367 done:
3368         qp_attr->cur_qp_state = qp_attr->qp_state;
3369         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3370         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3371         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3372         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3373         qp_attr->cap.max_inline_data = 0;
3374         qp_init_attr->cap = qp_attr->cap;
3375         qp_init_attr->create_flags = 0;
3376
3377         mutex_unlock(&hr_qp->mutex);
3378
3379         return 0;
3380 }
3381
3382 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3383                             int qp_attr_mask,
3384                             struct ib_qp_init_attr *qp_init_attr)
3385 {
3386         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3387         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3388         struct device *dev = &hr_dev->pdev->dev;
3389         struct hns_roce_qp_context *context;
3390         int tmp_qp_state;
3391         int ret = 0;
3392         int state;
3393
3394         context = kzalloc(sizeof(*context), GFP_KERNEL);
3395         if (!context)
3396                 return -ENOMEM;
3397
3398         memset(qp_attr, 0, sizeof(*qp_attr));
3399         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3400
3401         mutex_lock(&hr_qp->mutex);
3402
3403         if (hr_qp->state == IB_QPS_RESET) {
3404                 qp_attr->qp_state = IB_QPS_RESET;
3405                 goto done;
3406         }
3407
3408         ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3409         if (ret) {
3410                 dev_err(dev, "query qpc error\n");
3411                 ret = -EINVAL;
3412                 goto out;
3413         }
3414
3415         state = roce_get_field(context->qpc_bytes_144,
3416                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3417                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3418         tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3419         if (tmp_qp_state == -1) {
3420                 dev_err(dev, "to_ib_qp_state error\n");
3421                 ret = -EINVAL;
3422                 goto out;
3423         }
3424         hr_qp->state = (u8)tmp_qp_state;
3425         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3426         qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3427                                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3428                                                QP_CONTEXT_QPC_BYTES_48_MTU_S);
3429         qp_attr->path_mig_state = IB_MIG_ARMED;
3430         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3431         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3432                 qp_attr->qkey = QKEY_VAL;
3433
3434         qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3435                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3436                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3437         qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3438                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3439                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3440         qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3441                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3442                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3443         qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3444                         QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3445                                    ((roce_get_bit(context->qpc_bytes_4,
3446                         QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3447                                    ((roce_get_bit(context->qpc_bytes_4,
3448                         QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3449
3450         if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3451                 struct ib_global_route *grh =
3452                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3453
3454                 rdma_ah_set_sl(&qp_attr->ah_attr,
3455                                roce_get_field(context->qpc_bytes_156,
3456                                               QP_CONTEXT_QPC_BYTES_156_SL_M,
3457                                               QP_CONTEXT_QPC_BYTES_156_SL_S));
3458                 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3459                 grh->flow_label =
3460                         roce_get_field(context->qpc_bytes_48,
3461                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3462                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3463                 grh->sgid_index =
3464                         roce_get_field(context->qpc_bytes_36,
3465                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3466                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3467                 grh->hop_limit =
3468                         roce_get_field(context->qpc_bytes_44,
3469                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3470                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3471                 grh->traffic_class =
3472                         roce_get_field(context->qpc_bytes_48,
3473                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3474                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3475
3476                 memcpy(grh->dgid.raw, context->dgid,
3477                        sizeof(grh->dgid.raw));
3478         }
3479
3480         qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3481                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3482                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3483         qp_attr->port_num = hr_qp->port + 1;
3484         qp_attr->sq_draining = 0;
3485         qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3486                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3487                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3488         qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3489                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3490                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3491         qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3492                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3493                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3494         qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3495                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3496                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3497         qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3498                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3499                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3500         qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3501
3502 done:
3503         qp_attr->cur_qp_state = qp_attr->qp_state;
3504         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3505         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3506
3507         if (!ibqp->uobject) {
3508                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3509                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3510         } else {
3511                 qp_attr->cap.max_send_wr = 0;
3512                 qp_attr->cap.max_send_sge = 0;
3513         }
3514
3515         qp_init_attr->cap = qp_attr->cap;
3516
3517 out:
3518         mutex_unlock(&hr_qp->mutex);
3519         kfree(context);
3520         return ret;
3521 }
3522
3523 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3524                                 int qp_attr_mask,
3525                                 struct ib_qp_init_attr *qp_init_attr)
3526 {
3527         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3528
3529         return hr_qp->doorbell_qpn <= 1 ?
3530                 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3531                 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3532 }
3533
3534 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3535 {
3536         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3537         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3538         struct hns_roce_cq *send_cq, *recv_cq;
3539         int ret;
3540
3541         ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3542         if (ret)
3543                 return ret;
3544
3545         send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
3546         recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3547
3548         hns_roce_lock_cqs(send_cq, recv_cq);
3549         if (!udata) {
3550                 if (recv_cq)
3551                         __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
3552                                                (hr_qp->ibqp.srq ?
3553                                                 to_hr_srq(hr_qp->ibqp.srq) :
3554                                                 NULL));
3555
3556                 if (send_cq && send_cq != recv_cq)
3557                         __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3558         }
3559         hns_roce_qp_remove(hr_dev, hr_qp);
3560         hns_roce_unlock_cqs(send_cq, recv_cq);
3561
3562         hns_roce_qp_destroy(hr_dev, hr_qp, udata);
3563
3564         return 0;
3565 }
3566
3567 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3568 {
3569         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3570         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3571         struct device *dev = &hr_dev->pdev->dev;
3572         u32 cqe_cnt_ori;
3573         u32 cqe_cnt_cur;
3574         int wait_time = 0;
3575
3576         /*
3577          * Before freeing cq buffer, we need to ensure that the outstanding CQE
3578          * have been written by checking the CQE counter.
3579          */
3580         cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3581         while (1) {
3582                 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3583                     HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3584                         break;
3585
3586                 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3587                 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3588                         break;
3589
3590                 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3591                 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3592                         dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3593                                 hr_cq->cqn);
3594                         break;
3595                 }
3596                 wait_time++;
3597         }
3598         return 0;
3599 }
3600
3601 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, u32 req_not)
3602 {
3603         roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3604                        (req_not << eq->log_entries), eq->db_reg);
3605 }
3606
3607 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3608                                             struct hns_roce_aeqe *aeqe, int qpn)
3609 {
3610         struct device *dev = &hr_dev->pdev->dev;
3611
3612         dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3613         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3614                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3615         case HNS_ROCE_LWQCE_QPC_ERROR:
3616                 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3617                 break;
3618         case HNS_ROCE_LWQCE_MTU_ERROR:
3619                 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3620                 break;
3621         case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3622                 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3623                 break;
3624         case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3625                 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3626                 break;
3627         case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3628                 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3629                 break;
3630         case HNS_ROCE_LWQCE_SL_ERROR:
3631                 dev_warn(dev, "QP %d, SL error.\n", qpn);
3632                 break;
3633         case HNS_ROCE_LWQCE_PORT_ERROR:
3634                 dev_warn(dev, "QP %d, port error.\n", qpn);
3635                 break;
3636         default:
3637                 break;
3638         }
3639 }
3640
3641 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3642                                                    struct hns_roce_aeqe *aeqe,
3643                                                    int qpn)
3644 {
3645         struct device *dev = &hr_dev->pdev->dev;
3646
3647         dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3648         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3649                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3650         case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3651                 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3652                 break;
3653         case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3654                 dev_warn(dev, "QP %d, length error.\n", qpn);
3655                 break;
3656         case HNS_ROCE_LAVWQE_VA_ERROR:
3657                 dev_warn(dev, "QP %d, VA error.\n", qpn);
3658                 break;
3659         case HNS_ROCE_LAVWQE_PD_ERROR:
3660                 dev_err(dev, "QP %d, PD error.\n", qpn);
3661                 break;
3662         case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3663                 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3664                 break;
3665         case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3666                 dev_warn(dev, "QP %d, key state error.\n", qpn);
3667                 break;
3668         case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3669                 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3670                 break;
3671         default:
3672                 break;
3673         }
3674 }
3675
3676 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3677                                       struct hns_roce_aeqe *aeqe,
3678                                       int event_type)
3679 {
3680         struct device *dev = &hr_dev->pdev->dev;
3681         int phy_port;
3682         int qpn;
3683
3684         qpn = roce_get_field(aeqe->event.queue_event.num,
3685                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3686                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3687         phy_port = roce_get_field(aeqe->event.queue_event.num,
3688                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3689                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3690         if (qpn <= 1)
3691                 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3692
3693         switch (event_type) {
3694         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3695                 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3696                          "QP %d, phy_port %d.\n", qpn, phy_port);
3697                 break;
3698         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3699                 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3700                 break;
3701         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3702                 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3703                 break;
3704         default:
3705                 break;
3706         }
3707
3708         hns_roce_qp_event(hr_dev, qpn, event_type);
3709 }
3710
3711 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3712                                       struct hns_roce_aeqe *aeqe,
3713                                       int event_type)
3714 {
3715         struct device *dev = &hr_dev->pdev->dev;
3716         u32 cqn;
3717
3718         cqn = roce_get_field(aeqe->event.queue_event.num,
3719                              HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3720                              HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3721
3722         switch (event_type) {
3723         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3724                 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3725                 break;
3726         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3727                 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3728                 break;
3729         case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3730                 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3731                 break;
3732         default:
3733                 break;
3734         }
3735
3736         hns_roce_cq_event(hr_dev, cqn, event_type);
3737 }
3738
3739 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3740                                            struct hns_roce_aeqe *aeqe)
3741 {
3742         struct device *dev = &hr_dev->pdev->dev;
3743
3744         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3745                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3746         case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3747                 dev_warn(dev, "SDB overflow.\n");
3748                 break;
3749         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3750                 dev_warn(dev, "SDB almost overflow.\n");
3751                 break;
3752         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3753                 dev_warn(dev, "SDB almost empty.\n");
3754                 break;
3755         case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3756                 dev_warn(dev, "ODB overflow.\n");
3757                 break;
3758         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3759                 dev_warn(dev, "ODB almost overflow.\n");
3760                 break;
3761         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3762                 dev_warn(dev, "SDB almost empty.\n");
3763                 break;
3764         default:
3765                 break;
3766         }
3767 }
3768
3769 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3770 {
3771         unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
3772
3773         return (struct hns_roce_aeqe *)((u8 *)
3774                 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3775                 off % HNS_ROCE_BA_SIZE);
3776 }
3777
3778 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3779 {
3780         struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3781
3782         return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3783                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3784 }
3785
3786 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3787                                struct hns_roce_eq *eq)
3788 {
3789         struct device *dev = &hr_dev->pdev->dev;
3790         struct hns_roce_aeqe *aeqe;
3791         int aeqes_found = 0;
3792         int event_type;
3793
3794         while ((aeqe = next_aeqe_sw_v1(eq))) {
3795                 /* Make sure we read the AEQ entry after we have checked the
3796                  * ownership bit
3797                  */
3798                 dma_rmb();
3799
3800                 dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
3801                         aeqe,
3802                         roce_get_field(aeqe->asyn,
3803                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3804                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3805                 event_type = roce_get_field(aeqe->asyn,
3806                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3807                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3808                 switch (event_type) {
3809                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3810                         dev_warn(dev, "PATH MIG not supported\n");
3811                         break;
3812                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3813                         dev_warn(dev, "COMMUNICATION established\n");
3814                         break;
3815                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3816                         dev_warn(dev, "SQ DRAINED not supported\n");
3817                         break;
3818                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3819                         dev_warn(dev, "PATH MIG failed\n");
3820                         break;
3821                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3822                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3823                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3824                         hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3825                         break;
3826                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3827                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3828                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3829                         dev_warn(dev, "SRQ not support!\n");
3830                         break;
3831                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3832                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3833                 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3834                         hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3835                         break;
3836                 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3837                         dev_warn(dev, "port change.\n");
3838                         break;
3839                 case HNS_ROCE_EVENT_TYPE_MB:
3840                         hns_roce_cmd_event(hr_dev,
3841                                            le16_to_cpu(aeqe->event.cmd.token),
3842                                            aeqe->event.cmd.status,
3843                                            le64_to_cpu(aeqe->event.cmd.out_param
3844                                            ));
3845                         break;
3846                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3847                         hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3848                         break;
3849                 default:
3850                         dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3851                                  event_type, eq->eqn, eq->cons_index);
3852                         break;
3853                 }
3854
3855                 eq->cons_index++;
3856                 aeqes_found = 1;
3857
3858                 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1)
3859                         eq->cons_index = 0;
3860         }
3861
3862         set_eq_cons_index_v1(eq, 0);
3863
3864         return aeqes_found;
3865 }
3866
3867 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3868 {
3869         unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
3870
3871         return (struct hns_roce_ceqe *)((u8 *)
3872                         (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3873                         off % HNS_ROCE_BA_SIZE);
3874 }
3875
3876 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3877 {
3878         struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3879
3880         return (!!(roce_get_bit(ceqe->comp,
3881                 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3882                 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3883 }
3884
3885 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3886                                struct hns_roce_eq *eq)
3887 {
3888         struct hns_roce_ceqe *ceqe;
3889         int ceqes_found = 0;
3890         u32 cqn;
3891
3892         while ((ceqe = next_ceqe_sw_v1(eq))) {
3893                 /* Make sure we read CEQ entry after we have checked the
3894                  * ownership bit
3895                  */
3896                 dma_rmb();
3897
3898                 cqn = roce_get_field(ceqe->comp,
3899                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
3900                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
3901                 hns_roce_cq_completion(hr_dev, cqn);
3902
3903                 ++eq->cons_index;
3904                 ceqes_found = 1;
3905
3906                 if (eq->cons_index >
3907                     EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1)
3908                         eq->cons_index = 0;
3909         }
3910
3911         set_eq_cons_index_v1(eq, 0);
3912
3913         return ceqes_found;
3914 }
3915
3916 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
3917 {
3918         struct hns_roce_eq  *eq  = eq_ptr;
3919         struct hns_roce_dev *hr_dev = eq->hr_dev;
3920         int int_work;
3921
3922         if (eq->type_flag == HNS_ROCE_CEQ)
3923                 /* CEQ irq routine, CEQ is pulse irq, not clear */
3924                 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
3925         else
3926                 /* AEQ irq routine, AEQ is pulse irq, not clear */
3927                 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
3928
3929         return IRQ_RETVAL(int_work);
3930 }
3931
3932 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
3933 {
3934         struct hns_roce_dev *hr_dev = dev_id;
3935         struct device *dev = &hr_dev->pdev->dev;
3936         int int_work = 0;
3937         u32 caepaemask_val;
3938         u32 cealmovf_val;
3939         u32 caepaest_val;
3940         u32 aeshift_val;
3941         u32 ceshift_val;
3942         u32 cemask_val;
3943         __le32 tmp;
3944         int i;
3945
3946         /*
3947          * Abnormal interrupt:
3948          * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
3949          * interrupt, mask irq, clear irq, cancel mask operation
3950          */
3951         aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
3952         tmp = cpu_to_le32(aeshift_val);
3953
3954         /* AEQE overflow */
3955         if (roce_get_bit(tmp,
3956                 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
3957                 dev_warn(dev, "AEQ overflow!\n");
3958
3959                 /* Set mask */
3960                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
3961                 tmp = cpu_to_le32(caepaemask_val);
3962                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
3963                              HNS_ROCE_INT_MASK_ENABLE);
3964                 caepaemask_val = le32_to_cpu(tmp);
3965                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
3966
3967                 /* Clear int state(INT_WC : write 1 clear) */
3968                 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
3969                 tmp = cpu_to_le32(caepaest_val);
3970                 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
3971                 caepaest_val = le32_to_cpu(tmp);
3972                 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
3973
3974                 /* Clear mask */
3975                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
3976                 tmp = cpu_to_le32(caepaemask_val);
3977                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
3978                              HNS_ROCE_INT_MASK_DISABLE);
3979                 caepaemask_val = le32_to_cpu(tmp);
3980                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
3981         }
3982
3983         /* CEQ almost overflow */
3984         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
3985                 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
3986                                         i * CEQ_REG_OFFSET);
3987                 tmp = cpu_to_le32(ceshift_val);
3988
3989                 if (roce_get_bit(tmp,
3990                         ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
3991                         dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
3992                         int_work++;
3993
3994                         /* Set mask */
3995                         cemask_val = roce_read(hr_dev,
3996                                                ROCEE_CAEP_CE_IRQ_MASK_0_REG +
3997                                                i * CEQ_REG_OFFSET);
3998                         tmp = cpu_to_le32(cemask_val);
3999                         roce_set_bit(tmp,
4000                                 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4001                                 HNS_ROCE_INT_MASK_ENABLE);
4002                         cemask_val = le32_to_cpu(tmp);
4003                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4004                                    i * CEQ_REG_OFFSET, cemask_val);
4005
4006                         /* Clear int state(INT_WC : write 1 clear) */
4007                         cealmovf_val = roce_read(hr_dev,
4008                                        ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4009                                        i * CEQ_REG_OFFSET);
4010                         tmp = cpu_to_le32(cealmovf_val);
4011                         roce_set_bit(tmp,
4012                                      ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4013                                      1);
4014                         cealmovf_val = le32_to_cpu(tmp);
4015                         roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4016                                    i * CEQ_REG_OFFSET, cealmovf_val);
4017
4018                         /* Clear mask */
4019                         cemask_val = roce_read(hr_dev,
4020                                      ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4021                                      i * CEQ_REG_OFFSET);
4022                         tmp = cpu_to_le32(cemask_val);
4023                         roce_set_bit(tmp,
4024                                ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4025                                HNS_ROCE_INT_MASK_DISABLE);
4026                         cemask_val = le32_to_cpu(tmp);
4027                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4028                                    i * CEQ_REG_OFFSET, cemask_val);
4029                 }
4030         }
4031
4032         /* ECC multi-bit error alarm */
4033         dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4034                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4035                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4036                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4037
4038         dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4039                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4040                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4041                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4042
4043         return IRQ_RETVAL(int_work);
4044 }
4045
4046 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4047 {
4048         u32 aemask_val;
4049         int masken = 0;
4050         __le32 tmp;
4051         int i;
4052
4053         /* AEQ INT */
4054         aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4055         tmp = cpu_to_le32(aemask_val);
4056         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4057                      masken);
4058         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4059         aemask_val = le32_to_cpu(tmp);
4060         roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4061
4062         /* CEQ INT */
4063         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4064                 /* IRQ mask */
4065                 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4066                            i * CEQ_REG_OFFSET, masken);
4067         }
4068 }
4069
4070 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4071                                 struct hns_roce_eq *eq)
4072 {
4073         int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4074                       HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4075         int i;
4076
4077         if (!eq->buf_list)
4078                 return;
4079
4080         for (i = 0; i < npages; ++i)
4081                 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4082                                   eq->buf_list[i].buf, eq->buf_list[i].map);
4083
4084         kfree(eq->buf_list);
4085 }
4086
4087 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4088                                   int enable_flag)
4089 {
4090         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4091         __le32 tmp;
4092         u32 val;
4093
4094         val = readl(eqc);
4095         tmp = cpu_to_le32(val);
4096
4097         if (enable_flag)
4098                 roce_set_field(tmp,
4099                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4100                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4101                                HNS_ROCE_EQ_STAT_VALID);
4102         else
4103                 roce_set_field(tmp,
4104                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4105                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4106                                HNS_ROCE_EQ_STAT_INVALID);
4107
4108         val = le32_to_cpu(tmp);
4109         writel(val, eqc);
4110 }
4111
4112 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4113                                  struct hns_roce_eq *eq)
4114 {
4115         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4116         struct device *dev = &hr_dev->pdev->dev;
4117         dma_addr_t tmp_dma_addr;
4118         u32 eqcuridx_val;
4119         u32 eqconsindx_val;
4120         u32 eqshift_val;
4121         __le32 tmp2 = 0;
4122         __le32 tmp1 = 0;
4123         __le32 tmp = 0;
4124         int num_bas;
4125         int ret;
4126         int i;
4127
4128         num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4129                    HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4130
4131         if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4132                 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4133                         (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4134                         num_bas);
4135                 return -EINVAL;
4136         }
4137
4138         eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4139         if (!eq->buf_list)
4140                 return -ENOMEM;
4141
4142         for (i = 0; i < num_bas; ++i) {
4143                 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4144                                                          &tmp_dma_addr,
4145                                                          GFP_KERNEL);
4146                 if (!eq->buf_list[i].buf) {
4147                         ret = -ENOMEM;
4148                         goto err_out_free_pages;
4149                 }
4150
4151                 eq->buf_list[i].map = tmp_dma_addr;
4152         }
4153         eq->cons_index = 0;
4154         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4155                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4156                        HNS_ROCE_EQ_STAT_INVALID);
4157         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4158                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4159                        eq->log_entries);
4160         eqshift_val = le32_to_cpu(tmp);
4161         writel(eqshift_val, eqc);
4162
4163         /* Configure eq extended address 12~44bit */
4164         writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4165
4166         /*
4167          * Configure eq extended address 45~49 bit.
4168          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4169          * using 4K page, and shift more 32 because of
4170          * calculating the high 32 bit value evaluated to hardware.
4171          */
4172         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4173                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4174                        eq->buf_list[0].map >> 44);
4175         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4176                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4177         eqcuridx_val = le32_to_cpu(tmp1);
4178         writel(eqcuridx_val, eqc + 8);
4179
4180         /* Configure eq consumer index */
4181         roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4182                        ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4183         eqconsindx_val = le32_to_cpu(tmp2);
4184         writel(eqconsindx_val, eqc + 0xc);
4185
4186         return 0;
4187
4188 err_out_free_pages:
4189         for (i -= 1; i >= 0; i--)
4190                 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4191                                   eq->buf_list[i].map);
4192
4193         kfree(eq->buf_list);
4194         return ret;
4195 }
4196
4197 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4198 {
4199         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4200         struct device *dev = &hr_dev->pdev->dev;
4201         struct hns_roce_eq *eq;
4202         int irq_num;
4203         int eq_num;
4204         int ret;
4205         int i, j;
4206
4207         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4208         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4209
4210         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4211         if (!eq_table->eq)
4212                 return -ENOMEM;
4213
4214         eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4215                                      GFP_KERNEL);
4216         if (!eq_table->eqc_base) {
4217                 ret = -ENOMEM;
4218                 goto err_eqc_base_alloc_fail;
4219         }
4220
4221         for (i = 0; i < eq_num; i++) {
4222                 eq = &eq_table->eq[i];
4223                 eq->hr_dev = hr_dev;
4224                 eq->eqn = i;
4225                 eq->irq = hr_dev->irq[i];
4226                 eq->log_page_size = PAGE_SHIFT;
4227
4228                 if (i < hr_dev->caps.num_comp_vectors) {
4229                         /* CEQ */
4230                         eq_table->eqc_base[i] = hr_dev->reg_base +
4231                                                 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4232                                                 CEQ_REG_OFFSET * i;
4233                         eq->type_flag = HNS_ROCE_CEQ;
4234                         eq->db_reg = hr_dev->reg_base +
4235                                      ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4236                                      CEQ_REG_OFFSET * i;
4237                         eq->entries = hr_dev->caps.ceqe_depth;
4238                         eq->log_entries = ilog2(eq->entries);
4239                         eq->eqe_size = HNS_ROCE_CEQE_SIZE;
4240                 } else {
4241                         /* AEQ */
4242                         eq_table->eqc_base[i] = hr_dev->reg_base +
4243                                                 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4244                         eq->type_flag = HNS_ROCE_AEQ;
4245                         eq->db_reg = hr_dev->reg_base +
4246                                      ROCEE_CAEP_AEQE_CONS_IDX_REG;
4247                         eq->entries = hr_dev->caps.aeqe_depth;
4248                         eq->log_entries = ilog2(eq->entries);
4249                         eq->eqe_size = HNS_ROCE_AEQE_SIZE;
4250                 }
4251         }
4252
4253         /* Disable irq */
4254         hns_roce_v1_int_mask_enable(hr_dev);
4255
4256         /* Configure ce int interval */
4257         roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4258                    HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4259
4260         /* Configure ce int burst num */
4261         roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4262                    HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4263
4264         for (i = 0; i < eq_num; i++) {
4265                 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4266                 if (ret) {
4267                         dev_err(dev, "eq create failed\n");
4268                         goto err_create_eq_fail;
4269                 }
4270         }
4271
4272         for (j = 0; j < irq_num; j++) {
4273                 if (j < eq_num)
4274                         ret = request_irq(hr_dev->irq[j],
4275                                           hns_roce_v1_msix_interrupt_eq, 0,
4276                                           hr_dev->irq_names[j],
4277                                           &eq_table->eq[j]);
4278                 else
4279                         ret = request_irq(hr_dev->irq[j],
4280                                           hns_roce_v1_msix_interrupt_abn, 0,
4281                                           hr_dev->irq_names[j], hr_dev);
4282
4283                 if (ret) {
4284                         dev_err(dev, "request irq error!\n");
4285                         goto err_request_irq_fail;
4286                 }
4287         }
4288
4289         for (i = 0; i < eq_num; i++)
4290                 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4291
4292         return 0;
4293
4294 err_request_irq_fail:
4295         for (j -= 1; j >= 0; j--)
4296                 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4297
4298 err_create_eq_fail:
4299         for (i -= 1; i >= 0; i--)
4300                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4301
4302         kfree(eq_table->eqc_base);
4303
4304 err_eqc_base_alloc_fail:
4305         kfree(eq_table->eq);
4306
4307         return ret;
4308 }
4309
4310 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4311 {
4312         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4313         int irq_num;
4314         int eq_num;
4315         int i;
4316
4317         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4318         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4319         for (i = 0; i < eq_num; i++) {
4320                 /* Disable EQ */
4321                 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4322
4323                 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4324
4325                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4326         }
4327         for (i = eq_num; i < irq_num; i++)
4328                 free_irq(hr_dev->irq[i], hr_dev);
4329
4330         kfree(eq_table->eqc_base);
4331         kfree(eq_table->eq);
4332 }
4333
4334 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4335         .destroy_qp = hns_roce_v1_destroy_qp,
4336         .poll_cq = hns_roce_v1_poll_cq,
4337         .post_recv = hns_roce_v1_post_recv,
4338         .post_send = hns_roce_v1_post_send,
4339         .query_qp = hns_roce_v1_query_qp,
4340         .req_notify_cq = hns_roce_v1_req_notify_cq,
4341 };
4342
4343 static const struct hns_roce_hw hns_roce_hw_v1 = {
4344         .reset = hns_roce_v1_reset,
4345         .hw_profile = hns_roce_v1_profile,
4346         .hw_init = hns_roce_v1_init,
4347         .hw_exit = hns_roce_v1_exit,
4348         .post_mbox = hns_roce_v1_post_mbox,
4349         .poll_mbox_done = hns_roce_v1_chk_mbox,
4350         .set_gid = hns_roce_v1_set_gid,
4351         .set_mac = hns_roce_v1_set_mac,
4352         .set_mtu = hns_roce_v1_set_mtu,
4353         .write_mtpt = hns_roce_v1_write_mtpt,
4354         .write_cqc = hns_roce_v1_write_cqc,
4355         .clear_hem = hns_roce_v1_clear_hem,
4356         .modify_qp = hns_roce_v1_modify_qp,
4357         .dereg_mr = hns_roce_v1_dereg_mr,
4358         .destroy_cq = hns_roce_v1_destroy_cq,
4359         .init_eq = hns_roce_v1_init_eq_table,
4360         .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4361         .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4362 };
4363
4364 static const struct of_device_id hns_roce_of_match[] = {
4365         { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4366         {},
4367 };
4368 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4369
4370 static const struct acpi_device_id hns_roce_acpi_match[] = {
4371         { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4372         {},
4373 };
4374 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4375
4376 static struct
4377 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4378 {
4379         struct device *dev;
4380
4381         /* get the 'device' corresponding to the matching 'fwnode' */
4382         dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4383         /* get the platform device */
4384         return dev ? to_platform_device(dev) : NULL;
4385 }
4386
4387 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4388 {
4389         struct device *dev = &hr_dev->pdev->dev;
4390         struct platform_device *pdev = NULL;
4391         struct net_device *netdev = NULL;
4392         struct device_node *net_node;
4393         int port_cnt = 0;
4394         u8 phy_port;
4395         int ret;
4396         int i;
4397
4398         /* check if we are compatible with the underlying SoC */
4399         if (dev_of_node(dev)) {
4400                 const struct of_device_id *of_id;
4401
4402                 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4403                 if (!of_id) {
4404                         dev_err(dev, "device is not compatible!\n");
4405                         return -ENXIO;
4406                 }
4407                 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4408                 if (!hr_dev->hw) {
4409                         dev_err(dev, "couldn't get H/W specific DT data!\n");
4410                         return -ENXIO;
4411                 }
4412         } else if (is_acpi_device_node(dev->fwnode)) {
4413                 const struct acpi_device_id *acpi_id;
4414
4415                 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4416                 if (!acpi_id) {
4417                         dev_err(dev, "device is not compatible!\n");
4418                         return -ENXIO;
4419                 }
4420                 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4421                 if (!hr_dev->hw) {
4422                         dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4423                         return -ENXIO;
4424                 }
4425         } else {
4426                 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4427                 return -ENXIO;
4428         }
4429
4430         /* get the mapped register base address */
4431         hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4432         if (IS_ERR(hr_dev->reg_base))
4433                 return PTR_ERR(hr_dev->reg_base);
4434
4435         /* read the node_guid of IB device from the DT or ACPI */
4436         ret = device_property_read_u8_array(dev, "node-guid",
4437                                             (u8 *)&hr_dev->ib_dev.node_guid,
4438                                             GUID_LEN);
4439         if (ret) {
4440                 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4441                 return ret;
4442         }
4443
4444         /* get the RoCE associated ethernet ports or netdevices */
4445         for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4446                 if (dev_of_node(dev)) {
4447                         net_node = of_parse_phandle(dev->of_node, "eth-handle",
4448                                                     i);
4449                         if (!net_node)
4450                                 continue;
4451                         pdev = of_find_device_by_node(net_node);
4452                 } else if (is_acpi_device_node(dev->fwnode)) {
4453                         struct fwnode_reference_args args;
4454
4455                         ret = acpi_node_get_property_reference(dev->fwnode,
4456                                                                "eth-handle",
4457                                                                i, &args);
4458                         if (ret)
4459                                 continue;
4460                         pdev = hns_roce_find_pdev(args.fwnode);
4461                 } else {
4462                         dev_err(dev, "cannot read data from DT or ACPI\n");
4463                         return -ENXIO;
4464                 }
4465
4466                 if (pdev) {
4467                         netdev = platform_get_drvdata(pdev);
4468                         phy_port = (u8)i;
4469                         if (netdev) {
4470                                 hr_dev->iboe.netdevs[port_cnt] = netdev;
4471                                 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4472                         } else {
4473                                 dev_err(dev, "no netdev found with pdev %s\n",
4474                                         pdev->name);
4475                                 return -ENODEV;
4476                         }
4477                         port_cnt++;
4478                 }
4479         }
4480
4481         if (port_cnt == 0) {
4482                 dev_err(dev, "unable to get eth-handle for available ports!\n");
4483                 return -EINVAL;
4484         }
4485
4486         hr_dev->caps.num_ports = port_cnt;
4487
4488         /* cmd issue mode: 0 is poll, 1 is event */
4489         hr_dev->cmd_mod = 1;
4490         hr_dev->loop_idc = 0;
4491         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4492         hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4493
4494         /* read the interrupt names from the DT or ACPI */
4495         ret = device_property_read_string_array(dev, "interrupt-names",
4496                                                 hr_dev->irq_names,
4497                                                 HNS_ROCE_V1_MAX_IRQ_NUM);
4498         if (ret < 0) {
4499                 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4500                 return ret;
4501         }
4502
4503         /* fetch the interrupt numbers */
4504         for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4505                 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4506                 if (hr_dev->irq[i] <= 0)
4507                         return -EINVAL;
4508         }
4509
4510         return 0;
4511 }
4512
4513 /**
4514  * hns_roce_probe - RoCE driver entrance
4515  * @pdev: pointer to platform device
4516  * Return : int
4517  *
4518  */
4519 static int hns_roce_probe(struct platform_device *pdev)
4520 {
4521         int ret;
4522         struct hns_roce_dev *hr_dev;
4523         struct device *dev = &pdev->dev;
4524
4525         hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4526         if (!hr_dev)
4527                 return -ENOMEM;
4528
4529         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4530         if (!hr_dev->priv) {
4531                 ret = -ENOMEM;
4532                 goto error_failed_kzalloc;
4533         }
4534
4535         hr_dev->pdev = pdev;
4536         hr_dev->dev = dev;
4537         platform_set_drvdata(pdev, hr_dev);
4538
4539         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4540             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4541                 dev_err(dev, "Not usable DMA addressing mode\n");
4542                 ret = -EIO;
4543                 goto error_failed_get_cfg;
4544         }
4545
4546         ret = hns_roce_get_cfg(hr_dev);
4547         if (ret) {
4548                 dev_err(dev, "Get Configuration failed!\n");
4549                 goto error_failed_get_cfg;
4550         }
4551
4552         ret = hns_roce_init(hr_dev);
4553         if (ret) {
4554                 dev_err(dev, "RoCE engine init failed!\n");
4555                 goto error_failed_get_cfg;
4556         }
4557
4558         return 0;
4559
4560 error_failed_get_cfg:
4561         kfree(hr_dev->priv);
4562
4563 error_failed_kzalloc:
4564         ib_dealloc_device(&hr_dev->ib_dev);
4565
4566         return ret;
4567 }
4568
4569 /**
4570  * hns_roce_remove - remove RoCE device
4571  * @pdev: pointer to platform device
4572  */
4573 static int hns_roce_remove(struct platform_device *pdev)
4574 {
4575         struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4576
4577         hns_roce_exit(hr_dev);
4578         kfree(hr_dev->priv);
4579         ib_dealloc_device(&hr_dev->ib_dev);
4580
4581         return 0;
4582 }
4583
4584 static struct platform_driver hns_roce_driver = {
4585         .probe = hns_roce_probe,
4586         .remove = hns_roce_remove,
4587         .driver = {
4588                 .name = DRV_NAME,
4589                 .of_match_table = hns_roce_of_match,
4590                 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4591         },
4592 };
4593
4594 module_platform_driver(hns_roce_driver);
4595
4596 MODULE_LICENSE("Dual BSD/GPL");
4597 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4598 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4599 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4600 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");