2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/platform_device.h>
34 #include <linux/acpi.h>
35 #include <linux/etherdevice.h>
36 #include <linux/interrupt.h>
38 #include <linux/of_platform.h>
39 #include <rdma/ib_umem.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_cmd.h"
43 #include "hns_roce_hem.h"
44 #include "hns_roce_hw_v1.h"
47 * hns_get_gid_index - Get gid index.
48 * @hr_dev: pointer to structure hns_roce_dev.
49 * @port: port, value range: 0 ~ MAX
50 * @gid_index: gid_index, value range: 0 ~ MAX
52 * N ports shared gids, allocation method as follow:
53 * GID[0][0], GID[1][0],.....GID[N - 1][0],
54 * GID[0][0], GID[1][0],.....GID[N - 1][0],
57 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index)
59 return gid_index * hr_dev->caps.num_ports + port;
62 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
64 dseg->lkey = cpu_to_le32(sg->lkey);
65 dseg->addr = cpu_to_le64(sg->addr);
66 dseg->len = cpu_to_le32(sg->length);
69 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
72 rseg->raddr = cpu_to_le64(remote_addr);
73 rseg->rkey = cpu_to_le32(rkey);
77 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
78 const struct ib_send_wr *wr,
79 const struct ib_send_wr **bad_wr)
81 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
82 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
83 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
84 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
85 struct hns_roce_wqe_data_seg *dseg = NULL;
86 struct hns_roce_qp *qp = to_hr_qp(ibqp);
87 struct device *dev = &hr_dev->pdev->dev;
88 struct hns_roce_sq_db sq_db = {};
90 unsigned long flags = 0;
99 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
100 ibqp->qp_type != IB_QPT_RC)) {
101 dev_err(dev, "un-supported QP type\n");
106 spin_lock_irqsave(&qp->sq.lock, flags);
108 for (nreq = 0; wr; ++nreq, wr = wr->next) {
109 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
115 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
117 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
118 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
119 wr->num_sge, qp->sq.max_gs);
125 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
126 qp->sq.wrid[wqe_idx] = wr->wr_id;
128 /* Corresponding to the RC and RD type wqe process separately */
129 if (ibqp->qp_type == IB_QPT_GSI) {
131 roce_set_field(ud_sq_wqe->dmac_h,
132 UD_SEND_WQE_U32_4_DMAC_0_M,
133 UD_SEND_WQE_U32_4_DMAC_0_S,
135 roce_set_field(ud_sq_wqe->dmac_h,
136 UD_SEND_WQE_U32_4_DMAC_1_M,
137 UD_SEND_WQE_U32_4_DMAC_1_S,
139 roce_set_field(ud_sq_wqe->dmac_h,
140 UD_SEND_WQE_U32_4_DMAC_2_M,
141 UD_SEND_WQE_U32_4_DMAC_2_S,
143 roce_set_field(ud_sq_wqe->dmac_h,
144 UD_SEND_WQE_U32_4_DMAC_3_M,
145 UD_SEND_WQE_U32_4_DMAC_3_S,
148 roce_set_field(ud_sq_wqe->u32_8,
149 UD_SEND_WQE_U32_8_DMAC_4_M,
150 UD_SEND_WQE_U32_8_DMAC_4_S,
152 roce_set_field(ud_sq_wqe->u32_8,
153 UD_SEND_WQE_U32_8_DMAC_5_M,
154 UD_SEND_WQE_U32_8_DMAC_5_S,
157 smac = (u8 *)hr_dev->dev_addr[qp->port];
158 loopback = ether_addr_equal_unaligned(ah->av.mac,
160 roce_set_bit(ud_sq_wqe->u32_8,
161 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
164 roce_set_field(ud_sq_wqe->u32_8,
165 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
166 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
167 HNS_ROCE_WQE_OPCODE_SEND);
168 roce_set_field(ud_sq_wqe->u32_8,
169 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
170 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
172 roce_set_bit(ud_sq_wqe->u32_8,
173 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
176 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
177 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
178 (wr->send_flags & IB_SEND_SOLICITED ?
179 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
180 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
181 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
183 roce_set_field(ud_sq_wqe->u32_16,
184 UD_SEND_WQE_U32_16_DEST_QP_M,
185 UD_SEND_WQE_U32_16_DEST_QP_S,
186 ud_wr(wr)->remote_qpn);
187 roce_set_field(ud_sq_wqe->u32_16,
188 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
189 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
192 roce_set_field(ud_sq_wqe->u32_36,
193 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
194 UD_SEND_WQE_U32_36_FLOW_LABEL_S,
196 roce_set_field(ud_sq_wqe->u32_36,
197 UD_SEND_WQE_U32_36_PRIORITY_M,
198 UD_SEND_WQE_U32_36_PRIORITY_S,
200 roce_set_field(ud_sq_wqe->u32_36,
201 UD_SEND_WQE_U32_36_SGID_INDEX_M,
202 UD_SEND_WQE_U32_36_SGID_INDEX_S,
203 hns_get_gid_index(hr_dev, qp->phy_port,
206 roce_set_field(ud_sq_wqe->u32_40,
207 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
208 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
210 roce_set_field(ud_sq_wqe->u32_40,
211 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
212 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
215 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
218 cpu_to_le32((u32)wr->sg_list[0].addr);
220 cpu_to_le32((wr->sg_list[0].addr) >> 32);
222 cpu_to_le32(wr->sg_list[0].lkey);
225 cpu_to_le32((u32)wr->sg_list[1].addr);
227 cpu_to_le32((wr->sg_list[1].addr) >> 32);
229 cpu_to_le32(wr->sg_list[1].lkey);
230 } else if (ibqp->qp_type == IB_QPT_RC) {
234 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
235 for (i = 0; i < wr->num_sge; i++)
236 tmp_len += wr->sg_list[i].length;
239 cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
244 switch (wr->opcode) {
245 case IB_WR_SEND_WITH_IMM:
246 case IB_WR_RDMA_WRITE_WITH_IMM:
247 ctrl->imm_data = wr->ex.imm_data;
249 case IB_WR_SEND_WITH_INV:
251 cpu_to_le32(wr->ex.invalidate_rkey);
258 /* Ctrl field, ctrl set type: sig, solic, imm, fence */
259 /* SO wait for conforming application scenarios */
260 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
261 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
262 (wr->send_flags & IB_SEND_SOLICITED ?
263 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
264 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
265 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
266 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
267 (wr->send_flags & IB_SEND_FENCE ?
268 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
270 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
272 switch (wr->opcode) {
273 case IB_WR_RDMA_READ:
274 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
275 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
278 case IB_WR_RDMA_WRITE:
279 case IB_WR_RDMA_WRITE_WITH_IMM:
280 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
281 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
285 case IB_WR_SEND_WITH_INV:
286 case IB_WR_SEND_WITH_IMM:
287 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
289 case IB_WR_LOCAL_INV:
290 case IB_WR_ATOMIC_CMP_AND_SWP:
291 case IB_WR_ATOMIC_FETCH_AND_ADD:
294 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
297 ctrl->flag |= cpu_to_le32(ps_opcode);
298 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
301 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
302 if (le32_to_cpu(ctrl->msg_length) >
303 hr_dev->caps.max_sq_inline) {
306 dev_err(dev, "inline len(1-%d)=%d, illegal",
307 le32_to_cpu(ctrl->msg_length),
308 hr_dev->caps.max_sq_inline);
311 for (i = 0; i < wr->num_sge; i++) {
312 memcpy(wqe, ((void *) (uintptr_t)
313 wr->sg_list[i].addr),
314 wr->sg_list[i].length);
315 wqe += wr->sg_list[i].length;
317 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
320 for (i = 0; i < wr->num_sge; i++)
321 set_data_seg(dseg + i, wr->sg_list + i);
323 ctrl->flag |= cpu_to_le32(wr->num_sge <<
324 HNS_ROCE_WQE_SGE_NUM_BIT);
334 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
335 SQ_DOORBELL_U32_4_SQ_HEAD_S,
336 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
337 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
338 SQ_DOORBELL_U32_4_SL_S, qp->sl);
339 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
340 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
341 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
342 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
343 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
345 doorbell[0] = sq_db.u32_4;
346 doorbell[1] = sq_db.u32_8;
348 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
351 spin_unlock_irqrestore(&qp->sq.lock, flags);
356 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
357 const struct ib_recv_wr *wr,
358 const struct ib_recv_wr **bad_wr)
360 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
361 struct hns_roce_wqe_data_seg *scat = NULL;
362 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
363 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
364 struct device *dev = &hr_dev->pdev->dev;
365 struct hns_roce_rq_db rq_db = {};
366 __le32 doorbell[2] = {0};
367 unsigned long flags = 0;
368 unsigned int wqe_idx;
374 spin_lock_irqsave(&hr_qp->rq.lock, flags);
376 for (nreq = 0; wr; ++nreq, wr = wr->next) {
377 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
378 hr_qp->ibqp.recv_cq)) {
384 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
386 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
387 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
388 wr->num_sge, hr_qp->rq.max_gs);
394 ctrl = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
396 roce_set_field(ctrl->rwqe_byte_12,
397 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
398 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
401 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
403 for (i = 0; i < wr->num_sge; i++)
404 set_data_seg(scat + i, wr->sg_list + i);
406 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
411 hr_qp->rq.head += nreq;
413 if (ibqp->qp_type == IB_QPT_GSI) {
416 /* SW update GSI rq header */
417 reg_val = roce_read(to_hr_dev(ibqp->device),
418 ROCEE_QP1C_CFG3_0_REG +
419 QP1C_CFGN_OFFSET * hr_qp->phy_port);
420 tmp = cpu_to_le32(reg_val);
422 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
423 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
425 reg_val = le32_to_cpu(tmp);
426 roce_write(to_hr_dev(ibqp->device),
427 ROCEE_QP1C_CFG3_0_REG +
428 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
430 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
431 RQ_DOORBELL_U32_4_RQ_HEAD_S,
433 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
434 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
435 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
436 RQ_DOORBELL_U32_8_CMD_S, 1);
437 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
440 doorbell[0] = rq_db.u32_4;
441 doorbell[1] = rq_db.u32_8;
443 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
446 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
451 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
452 int sdb_mode, int odb_mode)
457 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
458 tmp = cpu_to_le32(val);
459 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
460 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
461 val = le32_to_cpu(tmp);
462 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
465 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
471 /* Configure SDB/ODB extend mode */
472 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
473 tmp = cpu_to_le32(val);
474 roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
475 roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
476 val = le32_to_cpu(tmp);
477 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
480 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
487 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
488 tmp = cpu_to_le32(val);
489 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
490 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
491 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
492 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
493 val = le32_to_cpu(tmp);
494 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
497 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
504 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
505 tmp = cpu_to_le32(val);
506 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
507 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
508 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
509 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
510 val = le32_to_cpu(tmp);
511 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
514 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
517 struct hns_roce_v1_priv *priv = hr_dev->priv;
518 struct hns_roce_db_table *db = &priv->db_table;
519 struct device *dev = &hr_dev->pdev->dev;
520 dma_addr_t sdb_dma_addr;
524 /* Configure extend SDB threshold */
525 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
526 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
528 /* Configure extend SDB base addr */
529 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
530 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
532 /* Configure extend SDB depth */
533 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
534 tmp = cpu_to_le32(val);
535 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
536 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
537 db->ext_db->esdb_dep);
539 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
540 * using 4K page, and shift more 32 because of
541 * calculating the high 32 bit value evaluated to hardware.
543 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
544 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
545 val = le32_to_cpu(tmp);
546 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
548 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
549 dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
550 ext_sdb_alept, ext_sdb_alful);
553 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
556 struct hns_roce_v1_priv *priv = hr_dev->priv;
557 struct hns_roce_db_table *db = &priv->db_table;
558 struct device *dev = &hr_dev->pdev->dev;
559 dma_addr_t odb_dma_addr;
563 /* Configure extend ODB threshold */
564 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
565 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
567 /* Configure extend ODB base addr */
568 odb_dma_addr = db->ext_db->odb_buf_list->map;
569 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
571 /* Configure extend ODB depth */
572 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
573 tmp = cpu_to_le32(val);
574 roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
575 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
576 db->ext_db->eodb_dep);
577 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
578 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
579 db->ext_db->eodb_dep);
580 val = le32_to_cpu(tmp);
581 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
583 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
584 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
585 ext_odb_alept, ext_odb_alful);
588 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
591 struct hns_roce_v1_priv *priv = hr_dev->priv;
592 struct hns_roce_db_table *db = &priv->db_table;
593 struct device *dev = &hr_dev->pdev->dev;
594 dma_addr_t sdb_dma_addr;
595 dma_addr_t odb_dma_addr;
598 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
603 db->ext_db->sdb_buf_list = kmalloc(
604 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
605 if (!db->ext_db->sdb_buf_list) {
607 goto ext_sdb_buf_fail_out;
610 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
611 HNS_ROCE_V1_EXT_SDB_SIZE,
612 &sdb_dma_addr, GFP_KERNEL);
613 if (!db->ext_db->sdb_buf_list->buf) {
615 goto alloc_sq_db_buf_fail;
617 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
619 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
620 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
621 HNS_ROCE_V1_EXT_SDB_ALFUL);
623 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
624 HNS_ROCE_V1_SDB_ALFUL);
627 db->ext_db->odb_buf_list = kmalloc(
628 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
629 if (!db->ext_db->odb_buf_list) {
631 goto ext_odb_buf_fail_out;
634 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
635 HNS_ROCE_V1_EXT_ODB_SIZE,
636 &odb_dma_addr, GFP_KERNEL);
637 if (!db->ext_db->odb_buf_list->buf) {
639 goto alloc_otr_db_buf_fail;
641 db->ext_db->odb_buf_list->map = odb_dma_addr;
643 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
644 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
645 HNS_ROCE_V1_EXT_ODB_ALFUL);
647 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
648 HNS_ROCE_V1_ODB_ALFUL);
650 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
654 alloc_otr_db_buf_fail:
655 kfree(db->ext_db->odb_buf_list);
657 ext_odb_buf_fail_out:
659 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
660 db->ext_db->sdb_buf_list->buf,
661 db->ext_db->sdb_buf_list->map);
664 alloc_sq_db_buf_fail:
666 kfree(db->ext_db->sdb_buf_list);
668 ext_sdb_buf_fail_out:
673 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
676 struct device *dev = &hr_dev->pdev->dev;
677 struct ib_qp_init_attr init_attr;
680 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
681 init_attr.qp_type = IB_QPT_RC;
682 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
683 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
684 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
686 qp = hns_roce_create_qp(pd, &init_attr, NULL);
688 dev_err(dev, "Create loop qp for mr free failed!");
695 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
697 struct hns_roce_v1_priv *priv = hr_dev->priv;
698 struct hns_roce_free_mr *free_mr = &priv->free_mr;
699 struct hns_roce_caps *caps = &hr_dev->caps;
700 struct ib_device *ibdev = &hr_dev->ib_dev;
701 struct device *dev = &hr_dev->pdev->dev;
702 struct ib_cq_init_attr cq_init_attr;
703 struct ib_qp_attr attr = { 0 };
704 struct hns_roce_qp *hr_qp;
708 __be64 subnet_prefix;
712 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
717 /* Reserved cq for loop qp */
718 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
719 cq_init_attr.comp_vector = 0;
721 cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
725 ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
727 dev_err(dev, "Create cq for reserved loop qp failed!");
728 goto alloc_cq_failed;
730 free_mr->mr_free_cq = to_hr_cq(cq);
731 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
732 free_mr->mr_free_cq->ib_cq.uobject = NULL;
733 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
734 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
735 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
736 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
738 pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
741 goto alloc_mem_failed;
745 ret = hns_roce_alloc_pd(pd, NULL);
747 goto alloc_pd_failed;
749 free_mr->mr_free_pd = to_hr_pd(pd);
750 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
751 free_mr->mr_free_pd->ibpd.uobject = NULL;
752 free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
753 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
755 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
757 attr.min_rnr_timer = 0;
758 /* Disable read ability */
759 attr.max_dest_rd_atomic = 0;
760 attr.max_rd_atomic = 0;
761 /* Use arbitrary values as rq_psn and sq_psn */
762 attr.rq_psn = 0x0808;
763 attr.sq_psn = 0x0808;
767 attr.path_mtu = IB_MTU_256;
768 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
769 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
770 rdma_ah_set_static_rate(&attr.ah_attr, 3);
772 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
773 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
774 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
775 (i % HNS_ROCE_MAX_PORTS);
776 sl = i / HNS_ROCE_MAX_PORTS;
778 for (j = 0; j < caps->num_ports; j++) {
779 if (hr_dev->iboe.phy_port[j] == phy_port) {
789 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
790 if (!free_mr->mr_free_qp[i]) {
791 dev_err(dev, "Create loop qp failed!\n");
793 goto create_lp_qp_failed;
795 hr_qp = free_mr->mr_free_qp[i];
798 hr_qp->phy_port = phy_port;
799 hr_qp->ibqp.qp_type = IB_QPT_RC;
800 hr_qp->ibqp.device = &hr_dev->ib_dev;
801 hr_qp->ibqp.uobject = NULL;
802 atomic_set(&hr_qp->ibqp.usecnt, 0);
804 hr_qp->ibqp.recv_cq = cq;
805 hr_qp->ibqp.send_cq = cq;
807 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
808 rdma_ah_set_sl(&attr.ah_attr, sl);
809 attr.port_num = port + 1;
811 attr.dest_qp_num = hr_qp->qpn;
812 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
813 hr_dev->dev_addr[port],
816 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
817 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
818 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
822 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
824 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
825 IB_QPS_RESET, IB_QPS_INIT);
827 dev_err(dev, "modify qp failed(%d)!\n", ret);
828 goto create_lp_qp_failed;
831 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
832 IB_QPS_INIT, IB_QPS_RTR);
834 dev_err(dev, "modify qp failed(%d)!\n", ret);
835 goto create_lp_qp_failed;
838 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
839 IB_QPS_RTR, IB_QPS_RTS);
841 dev_err(dev, "modify qp failed(%d)!\n", ret);
842 goto create_lp_qp_failed;
849 for (i -= 1; i >= 0; i--) {
850 hr_qp = free_mr->mr_free_qp[i];
851 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
852 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
855 hns_roce_dealloc_pd(pd, NULL);
861 hns_roce_destroy_cq(cq, NULL);
867 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
869 struct hns_roce_v1_priv *priv = hr_dev->priv;
870 struct hns_roce_free_mr *free_mr = &priv->free_mr;
871 struct device *dev = &hr_dev->pdev->dev;
872 struct hns_roce_qp *hr_qp;
876 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
877 hr_qp = free_mr->mr_free_qp[i];
881 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
883 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
887 hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
888 kfree(&free_mr->mr_free_cq->ib_cq);
889 hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
890 kfree(&free_mr->mr_free_pd->ibpd);
893 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
895 struct hns_roce_v1_priv *priv = hr_dev->priv;
896 struct hns_roce_db_table *db = &priv->db_table;
897 struct device *dev = &hr_dev->pdev->dev;
904 memset(db, 0, sizeof(*db));
906 /* Default DB mode */
907 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
908 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
909 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
910 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
912 db->sdb_ext_mod = sdb_ext_mod;
913 db->odb_ext_mod = odb_ext_mod;
916 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
918 dev_err(dev, "Failed in extend DB configuration.\n");
922 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
927 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
929 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
930 struct hns_roce_dev *hr_dev;
932 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
934 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
936 hns_roce_v1_release_lp_qp(hr_dev);
938 if (hns_roce_v1_rsv_lp_qp(hr_dev))
939 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
941 if (lp_qp_work->comp_flag)
942 complete(lp_qp_work->comp);
947 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
949 long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
950 struct hns_roce_v1_priv *priv = hr_dev->priv;
951 struct hns_roce_free_mr *free_mr = &priv->free_mr;
952 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
953 struct device *dev = &hr_dev->pdev->dev;
954 struct completion comp;
956 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
961 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
963 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
964 lp_qp_work->comp = ∁
965 lp_qp_work->comp_flag = 1;
967 init_completion(lp_qp_work->comp);
969 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
972 if (try_wait_for_completion(&comp))
974 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
975 end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
978 lp_qp_work->comp_flag = 0;
979 if (try_wait_for_completion(&comp))
982 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
986 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
988 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
989 struct device *dev = &hr_dev->pdev->dev;
990 struct ib_send_wr send_wr;
991 const struct ib_send_wr *bad_wr;
994 memset(&send_wr, 0, sizeof(send_wr));
997 send_wr.send_flags = 0;
998 send_wr.sg_list = NULL;
999 send_wr.wr_id = (unsigned long long)&send_wr;
1000 send_wr.opcode = IB_WR_RDMA_WRITE;
1002 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1004 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1011 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1014 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1015 struct hns_roce_mr_free_work *mr_work =
1016 container_of(work, struct hns_roce_mr_free_work, work);
1017 struct hns_roce_dev *hr_dev = to_hr_dev(mr_work->ib_dev);
1018 struct hns_roce_v1_priv *priv = hr_dev->priv;
1019 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1020 struct hns_roce_cq *mr_free_cq = free_mr->mr_free_cq;
1021 struct hns_roce_mr *hr_mr = mr_work->mr;
1022 struct device *dev = &hr_dev->pdev->dev;
1023 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1024 struct hns_roce_qp *hr_qp;
1029 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1030 hr_qp = free_mr->mr_free_qp[i];
1035 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1038 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1045 dev_err(dev, "Reserved loop qp is absent!\n");
1050 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1051 if (ret < 0 && hr_qp) {
1053 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1054 hr_qp->qpn, ret, hr_mr->key, ne);
1058 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1059 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1060 } while (ne && time_before_eq(jiffies, end));
1064 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1068 if (mr_work->comp_flag)
1069 complete(mr_work->comp);
1073 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1074 struct hns_roce_mr *mr, struct ib_udata *udata)
1076 struct hns_roce_v1_priv *priv = hr_dev->priv;
1077 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1078 long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1079 struct device *dev = &hr_dev->pdev->dev;
1080 struct hns_roce_mr_free_work *mr_work;
1081 unsigned long start = jiffies;
1082 struct completion comp;
1086 if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
1087 key_to_hw_index(mr->key) &
1088 (hr_dev->caps.num_mtpts - 1)))
1089 dev_warn(dev, "DESTROY_MPT failed!\n");
1092 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1098 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1100 mr_work->ib_dev = &(hr_dev->ib_dev);
1101 mr_work->comp = ∁
1102 mr_work->comp_flag = 1;
1103 mr_work->mr = (void *)mr;
1104 init_completion(mr_work->comp);
1106 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1109 if (try_wait_for_completion(&comp))
1111 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1112 end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1115 mr_work->comp_flag = 0;
1116 if (try_wait_for_completion(&comp))
1119 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1123 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1124 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1126 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1127 key_to_hw_index(mr->key), 0);
1128 hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
1134 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1136 struct hns_roce_v1_priv *priv = hr_dev->priv;
1137 struct hns_roce_db_table *db = &priv->db_table;
1138 struct device *dev = &hr_dev->pdev->dev;
1140 if (db->sdb_ext_mod) {
1141 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1142 db->ext_db->sdb_buf_list->buf,
1143 db->ext_db->sdb_buf_list->map);
1144 kfree(db->ext_db->sdb_buf_list);
1147 if (db->odb_ext_mod) {
1148 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1149 db->ext_db->odb_buf_list->buf,
1150 db->ext_db->odb_buf_list->map);
1151 kfree(db->ext_db->odb_buf_list);
1157 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1159 struct hns_roce_v1_priv *priv = hr_dev->priv;
1160 struct hns_roce_raq_table *raq = &priv->raq_table;
1161 struct device *dev = &hr_dev->pdev->dev;
1168 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1169 if (!raq->e_raq_buf)
1172 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1174 if (!raq->e_raq_buf->buf) {
1176 goto err_dma_alloc_raq;
1178 raq->e_raq_buf->map = addr;
1180 /* Configure raq extended address. 48bit 4K align */
1181 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1183 /* Configure raq_shift */
1184 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1185 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1186 tmp = cpu_to_le32(val);
1187 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1188 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1190 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1191 * using 4K page, and shift more 32 because of
1192 * calculating the high 32 bit value evaluated to hardware.
1194 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1195 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1196 raq->e_raq_buf->map >> 44);
1197 val = le32_to_cpu(tmp);
1198 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1199 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1201 /* Configure raq threshold */
1202 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1203 tmp = cpu_to_le32(val);
1204 roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1205 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1206 HNS_ROCE_V1_EXT_RAQ_WF);
1207 val = le32_to_cpu(tmp);
1208 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1209 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1211 /* Enable extend raq */
1212 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1213 tmp = cpu_to_le32(val);
1215 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1216 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1217 POL_TIME_INTERVAL_VAL);
1218 roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1220 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1221 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1224 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1225 val = le32_to_cpu(tmp);
1226 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1227 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1229 /* Enable raq drop */
1230 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1231 tmp = cpu_to_le32(val);
1232 roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1233 val = le32_to_cpu(tmp);
1234 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1235 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1240 kfree(raq->e_raq_buf);
1244 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1246 struct hns_roce_v1_priv *priv = hr_dev->priv;
1247 struct hns_roce_raq_table *raq = &priv->raq_table;
1248 struct device *dev = &hr_dev->pdev->dev;
1250 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1251 raq->e_raq_buf->map);
1252 kfree(raq->e_raq_buf);
1255 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1261 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1262 /* Open all ports */
1263 tmp = cpu_to_le32(val);
1264 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1265 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1267 val = le32_to_cpu(tmp);
1268 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1270 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1271 /* Close all ports */
1272 tmp = cpu_to_le32(val);
1273 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1274 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1275 val = le32_to_cpu(tmp);
1276 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1280 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1282 struct hns_roce_v1_priv *priv = hr_dev->priv;
1283 struct device *dev = &hr_dev->pdev->dev;
1286 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1287 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1289 if (!priv->bt_table.qpc_buf.buf)
1292 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1293 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1295 if (!priv->bt_table.mtpt_buf.buf) {
1297 goto err_failed_alloc_mtpt_buf;
1300 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1301 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1303 if (!priv->bt_table.cqc_buf.buf) {
1305 goto err_failed_alloc_cqc_buf;
1310 err_failed_alloc_cqc_buf:
1311 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1312 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1314 err_failed_alloc_mtpt_buf:
1315 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1316 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1321 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1323 struct hns_roce_v1_priv *priv = hr_dev->priv;
1324 struct device *dev = &hr_dev->pdev->dev;
1326 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1327 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1329 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1330 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1332 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1333 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1336 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1338 struct hns_roce_v1_priv *priv = hr_dev->priv;
1339 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1340 struct device *dev = &hr_dev->pdev->dev;
1343 * This buffer will be used for CQ's tptr(tail pointer), also
1344 * named ci(customer index). Every CQ will use 2 bytes to save
1345 * cqe ci in hip06. Hardware will read this area to get new ci
1346 * when the queue is almost full.
1348 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1349 &tptr_buf->map, GFP_KERNEL);
1353 hr_dev->tptr_dma_addr = tptr_buf->map;
1354 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1359 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1361 struct hns_roce_v1_priv *priv = hr_dev->priv;
1362 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1363 struct device *dev = &hr_dev->pdev->dev;
1365 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1366 tptr_buf->buf, tptr_buf->map);
1369 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1371 struct hns_roce_v1_priv *priv = hr_dev->priv;
1372 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1373 struct device *dev = &hr_dev->pdev->dev;
1376 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1377 if (!free_mr->free_mr_wq) {
1378 dev_err(dev, "Create free mr workqueue failed!\n");
1382 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1384 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1385 flush_workqueue(free_mr->free_mr_wq);
1386 destroy_workqueue(free_mr->free_mr_wq);
1392 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1394 struct hns_roce_v1_priv *priv = hr_dev->priv;
1395 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1397 flush_workqueue(free_mr->free_mr_wq);
1398 destroy_workqueue(free_mr->free_mr_wq);
1400 hns_roce_v1_release_lp_qp(hr_dev);
1404 * hns_roce_v1_reset - reset RoCE
1405 * @hr_dev: RoCE device struct pointer
1406 * @dereset: true -- drop reset, false -- reset
1407 * return 0 - success , negative --fail
1409 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1411 struct device_node *dsaf_node;
1412 struct device *dev = &hr_dev->pdev->dev;
1413 struct device_node *np = dev->of_node;
1414 struct fwnode_handle *fwnode;
1417 /* check if this is DT/ACPI case */
1418 if (dev_of_node(dev)) {
1419 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1421 dev_err(dev, "could not find dsaf-handle\n");
1424 fwnode = &dsaf_node->fwnode;
1425 } else if (is_acpi_device_node(dev->fwnode)) {
1426 struct fwnode_reference_args args;
1428 ret = acpi_node_get_property_reference(dev->fwnode,
1429 "dsaf-handle", 0, &args);
1431 dev_err(dev, "could not find dsaf-handle\n");
1434 fwnode = args.fwnode;
1436 dev_err(dev, "cannot read data from DT or ACPI\n");
1440 ret = hns_dsaf_roce_reset(fwnode, false);
1445 msleep(SLEEP_TIME_INTERVAL);
1446 ret = hns_dsaf_roce_reset(fwnode, true);
1452 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1454 struct hns_roce_caps *caps = &hr_dev->caps;
1457 hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1458 hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1459 hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1460 ((u64)roce_read(hr_dev,
1461 ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1462 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
1464 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1465 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1466 caps->min_wqes = HNS_ROCE_MIN_WQE_NUM;
1467 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1468 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1469 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1470 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1471 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1472 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1473 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1474 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1475 caps->num_aeq_vectors = HNS_ROCE_V1_AEQE_VEC_NUM;
1476 caps->num_comp_vectors = HNS_ROCE_V1_COMP_VEC_NUM;
1477 caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1478 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1479 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1480 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1481 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1482 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1483 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1484 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1485 caps->qpc_sz = HNS_ROCE_V1_QPC_SIZE;
1486 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1487 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1488 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1489 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1490 caps->cqe_sz = HNS_ROCE_V1_CQE_SIZE;
1491 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1492 caps->reserved_lkey = 0;
1493 caps->reserved_pds = 0;
1494 caps->reserved_mrws = 1;
1495 caps->reserved_uars = 0;
1496 caps->reserved_cqs = 0;
1497 caps->reserved_qps = 12; /* 2 SQP per port, six ports total 12 */
1498 caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1500 for (i = 0; i < caps->num_ports; i++)
1501 caps->pkey_table_len[i] = 1;
1503 for (i = 0; i < caps->num_ports; i++) {
1504 /* Six ports shared 16 GID in v1 engine */
1505 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1506 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1509 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1510 caps->num_ports + 1;
1513 caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1514 caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1515 caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1516 caps->max_mtu = IB_MTU_2048;
1521 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1526 struct device *dev = &hr_dev->pdev->dev;
1528 /* DMAE user config */
1529 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1530 tmp = cpu_to_le32(val);
1531 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1532 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1533 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1534 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1535 1 << PAGES_SHIFT_16);
1536 val = le32_to_cpu(tmp);
1537 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1539 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1540 tmp = cpu_to_le32(val);
1541 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1542 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1543 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1544 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1545 1 << PAGES_SHIFT_16);
1547 ret = hns_roce_db_init(hr_dev);
1549 dev_err(dev, "doorbell init failed!\n");
1553 ret = hns_roce_raq_init(hr_dev);
1555 dev_err(dev, "raq init failed!\n");
1556 goto error_failed_raq_init;
1559 ret = hns_roce_bt_init(hr_dev);
1561 dev_err(dev, "bt init failed!\n");
1562 goto error_failed_bt_init;
1565 ret = hns_roce_tptr_init(hr_dev);
1567 dev_err(dev, "tptr init failed!\n");
1568 goto error_failed_tptr_init;
1571 ret = hns_roce_free_mr_init(hr_dev);
1573 dev_err(dev, "free mr init failed!\n");
1574 goto error_failed_free_mr_init;
1577 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1581 error_failed_free_mr_init:
1582 hns_roce_tptr_free(hr_dev);
1584 error_failed_tptr_init:
1585 hns_roce_bt_free(hr_dev);
1587 error_failed_bt_init:
1588 hns_roce_raq_free(hr_dev);
1590 error_failed_raq_init:
1591 hns_roce_db_free(hr_dev);
1595 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1597 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1598 hns_roce_free_mr_free(hr_dev);
1599 hns_roce_tptr_free(hr_dev);
1600 hns_roce_bt_free(hr_dev);
1601 hns_roce_raq_free(hr_dev);
1602 hns_roce_db_free(hr_dev);
1605 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1607 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1609 return (!!(status & (1 << HCR_GO_BIT)));
1612 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1613 u64 out_param, u32 in_modifier, u8 op_modifier,
1614 u16 op, u16 token, int event)
1616 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1621 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1622 while (hns_roce_v1_cmd_pending(hr_dev)) {
1623 if (time_after(jiffies, end)) {
1624 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1625 (int)jiffies, (int)end);
1631 tmp = cpu_to_le32(val);
1632 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1634 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1635 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1636 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1637 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1638 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1639 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1641 val = le32_to_cpu(tmp);
1642 writeq(in_param, hcr + 0);
1643 writeq(out_param, hcr + 2);
1644 writel(in_modifier, hcr + 4);
1645 /* Memory barrier */
1648 writel(val, hcr + 5);
1653 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1654 unsigned int timeout)
1656 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1660 end = msecs_to_jiffies(timeout) + jiffies;
1661 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1664 if (hns_roce_v1_cmd_pending(hr_dev)) {
1665 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1669 status = le32_to_cpu((__force __le32)
1670 __raw_readl(hcr + HCR_STATUS_OFFSET));
1671 if ((status & STATUS_MASK) != 0x1) {
1672 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1679 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u32 port,
1680 int gid_index, const union ib_gid *gid,
1681 const struct ib_gid_attr *attr)
1683 unsigned long flags;
1687 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1689 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1691 p = (u32 *)&gid->raw[0];
1692 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1693 (HNS_ROCE_V1_GID_NUM * gid_idx));
1695 p = (u32 *)&gid->raw[4];
1696 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1697 (HNS_ROCE_V1_GID_NUM * gid_idx));
1699 p = (u32 *)&gid->raw[8];
1700 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1701 (HNS_ROCE_V1_GID_NUM * gid_idx));
1703 p = (u32 *)&gid->raw[0xc];
1704 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1705 (HNS_ROCE_V1_GID_NUM * gid_idx));
1707 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1712 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1723 * When mac changed, loopback may fail
1724 * because of smac not equal to dmac.
1725 * We Need to release and create reserved qp again.
1727 if (hr_dev->hw->dereg_mr) {
1730 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1731 if (ret && ret != -ETIMEDOUT)
1735 p = (u32 *)(&addr[0]);
1737 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1738 PHY_PORT_OFFSET * phy_port);
1740 val = roce_read(hr_dev,
1741 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1742 tmp = cpu_to_le32(val);
1743 p_h = (u16 *)(&addr[4]);
1745 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1746 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1747 val = le32_to_cpu(tmp);
1748 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1754 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1760 val = roce_read(hr_dev,
1761 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1762 tmp = cpu_to_le32(val);
1763 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1764 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1765 val = le32_to_cpu(tmp);
1766 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1770 static int hns_roce_v1_write_mtpt(struct hns_roce_dev *hr_dev, void *mb_buf,
1771 struct hns_roce_mr *mr,
1772 unsigned long mtpt_idx)
1774 u64 pages[HNS_ROCE_MAX_INNER_MTPT_NUM] = { 0 };
1775 struct ib_device *ibdev = &hr_dev->ib_dev;
1776 struct hns_roce_v1_mpt_entry *mpt_entry;
1781 /* MPT filled into mailbox buf */
1782 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1783 memset(mpt_entry, 0, sizeof(*mpt_entry));
1785 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1786 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1787 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1788 MPT_BYTE_4_KEY_S, mr->key);
1789 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1790 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1791 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1792 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1793 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1794 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1795 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1796 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1797 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1798 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1799 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1800 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1801 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1802 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1803 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1804 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1806 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1808 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1809 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1810 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1811 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1813 mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1814 mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1815 mpt_entry->length = cpu_to_le32((u32)mr->size);
1817 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1818 MPT_BYTE_28_PD_S, mr->pd);
1819 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1820 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1821 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1822 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1824 /* DMA memory register */
1825 if (mr->type == MR_TYPE_DMA)
1828 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
1829 ARRAY_SIZE(pages), &pbl_ba);
1831 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.", count);
1835 /* Register user mr */
1836 for (i = 0; i < count; i++) {
1839 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1840 roce_set_field(mpt_entry->mpt_byte_36,
1841 MPT_BYTE_36_PA0_H_M,
1842 MPT_BYTE_36_PA0_H_S,
1843 (u32)(pages[i] >> PAGES_SHIFT_32));
1846 roce_set_field(mpt_entry->mpt_byte_36,
1847 MPT_BYTE_36_PA1_L_M,
1848 MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1849 roce_set_field(mpt_entry->mpt_byte_40,
1850 MPT_BYTE_40_PA1_H_M,
1851 MPT_BYTE_40_PA1_H_S,
1852 (u32)(pages[i] >> PAGES_SHIFT_24));
1855 roce_set_field(mpt_entry->mpt_byte_40,
1856 MPT_BYTE_40_PA2_L_M,
1857 MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1858 roce_set_field(mpt_entry->mpt_byte_44,
1859 MPT_BYTE_44_PA2_H_M,
1860 MPT_BYTE_44_PA2_H_S,
1861 (u32)(pages[i] >> PAGES_SHIFT_16));
1864 roce_set_field(mpt_entry->mpt_byte_44,
1865 MPT_BYTE_44_PA3_L_M,
1866 MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1867 roce_set_field(mpt_entry->mpt_byte_48,
1868 MPT_BYTE_48_PA3_H_M,
1869 MPT_BYTE_48_PA3_H_S,
1870 (u32)(pages[i] >> PAGES_SHIFT_8));
1873 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1874 roce_set_field(mpt_entry->mpt_byte_56,
1875 MPT_BYTE_56_PA4_H_M,
1876 MPT_BYTE_56_PA4_H_S,
1877 (u32)(pages[i] >> PAGES_SHIFT_32));
1880 roce_set_field(mpt_entry->mpt_byte_56,
1881 MPT_BYTE_56_PA5_L_M,
1882 MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1883 roce_set_field(mpt_entry->mpt_byte_60,
1884 MPT_BYTE_60_PA5_H_M,
1885 MPT_BYTE_60_PA5_H_S,
1886 (u32)(pages[i] >> PAGES_SHIFT_24));
1889 roce_set_field(mpt_entry->mpt_byte_60,
1890 MPT_BYTE_60_PA6_L_M,
1891 MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1892 roce_set_field(mpt_entry->mpt_byte_64,
1893 MPT_BYTE_64_PA6_H_M,
1894 MPT_BYTE_64_PA6_H_S,
1895 (u32)(pages[i] >> PAGES_SHIFT_16));
1902 mpt_entry->pbl_addr_l = cpu_to_le32(pbl_ba);
1903 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1904 MPT_BYTE_12_PBL_ADDR_H_S, upper_32_bits(pbl_ba));
1909 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1911 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * HNS_ROCE_V1_CQE_SIZE);
1914 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1916 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1918 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1919 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1920 !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
1923 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1925 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1928 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1932 doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
1934 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1935 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1936 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1937 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1938 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1939 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1940 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1942 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1945 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1946 struct hns_roce_srq *srq)
1948 struct hns_roce_cqe *cqe, *dest;
1953 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1955 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1960 * Now backwards through the CQ, removing CQ entries
1961 * that match our QP by overwriting them with next entries.
1963 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1964 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1965 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1966 CQE_BYTE_16_LOCAL_QPN_S) &
1967 HNS_ROCE_CQE_QPN_MASK) == qpn) {
1968 /* In v1 engine, not support SRQ */
1970 } else if (nfreed) {
1971 dest = get_cqe(hr_cq, (prod_index + nfreed) &
1973 owner_bit = roce_get_bit(dest->cqe_byte_4,
1974 CQE_BYTE_4_OWNER_S);
1975 memcpy(dest, cqe, sizeof(*cqe));
1976 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1982 hr_cq->cons_index += nfreed;
1983 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
1987 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1988 struct hns_roce_srq *srq)
1990 spin_lock_irq(&hr_cq->lock);
1991 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
1992 spin_unlock_irq(&hr_cq->lock);
1995 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1996 struct hns_roce_cq *hr_cq, void *mb_buf,
1997 u64 *mtts, dma_addr_t dma_handle)
1999 struct hns_roce_v1_priv *priv = hr_dev->priv;
2000 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
2001 struct hns_roce_cq_context *cq_context = mb_buf;
2002 dma_addr_t tptr_dma_addr;
2005 memset(cq_context, 0, sizeof(*cq_context));
2007 /* Get the tptr for this CQ. */
2008 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2009 tptr_dma_addr = tptr_buf->map + offset;
2010 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2012 /* Register cq_context members */
2013 roce_set_field(cq_context->cqc_byte_4,
2014 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2015 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2016 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2017 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2019 cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2021 roce_set_field(cq_context->cqc_byte_12,
2022 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2023 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2024 ((u64)dma_handle >> 32));
2025 roce_set_field(cq_context->cqc_byte_12,
2026 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2027 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2028 ilog2(hr_cq->cq_depth));
2029 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2030 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2032 cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2034 roce_set_field(cq_context->cqc_byte_20,
2035 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2036 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2037 /* Dedicated hardware, directly set 0 */
2038 roce_set_field(cq_context->cqc_byte_20,
2039 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2040 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2042 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2043 * using 4K page, and shift more 32 because of
2044 * calculating the high 32 bit value evaluated to hardware.
2046 roce_set_field(cq_context->cqc_byte_20,
2047 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2048 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2049 tptr_dma_addr >> 44);
2051 cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2053 roce_set_field(cq_context->cqc_byte_32,
2054 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2055 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2056 roce_set_bit(cq_context->cqc_byte_32,
2057 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2058 roce_set_bit(cq_context->cqc_byte_32,
2059 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2060 roce_set_bit(cq_context->cqc_byte_32,
2061 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2062 roce_set_bit(cq_context->cqc_byte_32,
2063 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2065 /* The initial value of cq's ci is 0 */
2066 roce_set_field(cq_context->cqc_byte_32,
2067 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2068 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2071 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2072 enum ib_cq_notify_flags flags)
2074 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2075 u32 notification_flag;
2076 __le32 doorbell[2] = {};
2078 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2079 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2081 * flags = 0; Notification Flag = 1, next
2082 * flags = 1; Notification Flag = 0, solocited
2085 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2086 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2087 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2088 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2089 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2090 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2091 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2092 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2093 hr_cq->cqn | notification_flag);
2095 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2100 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2101 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2108 struct hns_roce_cqe *cqe;
2109 struct hns_roce_qp *hr_qp;
2110 struct hns_roce_wq *wq;
2111 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2112 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2113 struct device *dev = &hr_dev->pdev->dev;
2115 /* Find cqe according consumer index */
2116 cqe = next_cqe_sw(hr_cq);
2120 ++hr_cq->cons_index;
2121 /* Memory barrier */
2124 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2126 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2127 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2128 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2129 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2130 CQE_BYTE_20_PORT_NUM_S) +
2131 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2132 CQE_BYTE_16_LOCAL_QPN_S) *
2135 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2136 CQE_BYTE_16_LOCAL_QPN_S);
2139 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2140 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2141 if (unlikely(!hr_qp)) {
2142 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2143 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2150 wc->qp = &(*cur_qp)->ibqp;
2153 status = roce_get_field(cqe->cqe_byte_4,
2154 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2155 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2156 HNS_ROCE_CQE_STATUS_MASK;
2158 case HNS_ROCE_CQE_SUCCESS:
2159 wc->status = IB_WC_SUCCESS;
2161 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2162 wc->status = IB_WC_LOC_LEN_ERR;
2164 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2165 wc->status = IB_WC_LOC_QP_OP_ERR;
2167 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2168 wc->status = IB_WC_LOC_PROT_ERR;
2170 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2171 wc->status = IB_WC_WR_FLUSH_ERR;
2173 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2174 wc->status = IB_WC_MW_BIND_ERR;
2176 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2177 wc->status = IB_WC_BAD_RESP_ERR;
2179 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2180 wc->status = IB_WC_LOC_ACCESS_ERR;
2182 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2183 wc->status = IB_WC_REM_INV_REQ_ERR;
2185 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2186 wc->status = IB_WC_REM_ACCESS_ERR;
2188 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2189 wc->status = IB_WC_REM_OP_ERR;
2191 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2192 wc->status = IB_WC_RETRY_EXC_ERR;
2194 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2195 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2198 wc->status = IB_WC_GENERAL_ERR;
2202 /* CQE status error, directly return */
2203 if (wc->status != IB_WC_SUCCESS)
2207 /* SQ conrespond to CQE */
2208 sq_wqe = hns_roce_get_send_wqe(*cur_qp,
2209 roce_get_field(cqe->cqe_byte_4,
2210 CQE_BYTE_4_WQE_INDEX_M,
2211 CQE_BYTE_4_WQE_INDEX_S) &
2212 ((*cur_qp)->sq.wqe_cnt-1));
2213 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2214 case HNS_ROCE_WQE_OPCODE_SEND:
2215 wc->opcode = IB_WC_SEND;
2217 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2218 wc->opcode = IB_WC_RDMA_READ;
2219 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2221 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2222 wc->opcode = IB_WC_RDMA_WRITE;
2224 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2225 wc->opcode = IB_WC_LOCAL_INV;
2227 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2228 wc->opcode = IB_WC_SEND;
2231 wc->status = IB_WC_GENERAL_ERR;
2234 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2235 IB_WC_WITH_IMM : 0);
2237 wq = &(*cur_qp)->sq;
2238 if ((*cur_qp)->sq_signal_bits) {
2240 * If sg_signal_bit is 1,
2241 * firstly tail pointer updated to wqe
2242 * which current cqe correspond to
2244 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2245 CQE_BYTE_4_WQE_INDEX_M,
2246 CQE_BYTE_4_WQE_INDEX_S);
2247 wq->tail += (wqe_ctr - (u16)wq->tail) &
2250 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2253 /* RQ conrespond to CQE */
2254 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2255 opcode = roce_get_field(cqe->cqe_byte_4,
2256 CQE_BYTE_4_OPERATION_TYPE_M,
2257 CQE_BYTE_4_OPERATION_TYPE_S) &
2258 HNS_ROCE_CQE_OPCODE_MASK;
2260 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2261 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2262 wc->wc_flags = IB_WC_WITH_IMM;
2264 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2266 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2267 if (roce_get_bit(cqe->cqe_byte_4,
2268 CQE_BYTE_4_IMM_INDICATOR_S)) {
2269 wc->opcode = IB_WC_RECV;
2270 wc->wc_flags = IB_WC_WITH_IMM;
2271 wc->ex.imm_data = cpu_to_be32(
2272 le32_to_cpu(cqe->immediate_data));
2274 wc->opcode = IB_WC_RECV;
2279 wc->status = IB_WC_GENERAL_ERR;
2283 /* Update tail pointer, record wr_id */
2284 wq = &(*cur_qp)->rq;
2285 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2287 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2289 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2290 CQE_BYTE_20_REMOTE_QPN_M,
2291 CQE_BYTE_20_REMOTE_QPN_S);
2292 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2293 CQE_BYTE_20_GRH_PRESENT_S) ?
2295 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2296 CQE_BYTE_28_P_KEY_IDX_M,
2297 CQE_BYTE_28_P_KEY_IDX_S);
2303 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2305 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2306 struct hns_roce_qp *cur_qp = NULL;
2307 unsigned long flags;
2311 spin_lock_irqsave(&hr_cq->lock, flags);
2313 for (npolled = 0; npolled < num_entries; ++npolled) {
2314 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2320 *hr_cq->tptr_addr = hr_cq->cons_index &
2321 ((hr_cq->cq_depth << 1) - 1);
2323 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2326 spin_unlock_irqrestore(&hr_cq->lock, flags);
2328 if (ret == 0 || ret == -EAGAIN)
2334 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2335 struct hns_roce_hem_table *table, int obj,
2338 struct hns_roce_v1_priv *priv = hr_dev->priv;
2339 struct device *dev = &hr_dev->pdev->dev;
2340 long end = HW_SYNC_TIMEOUT_MSECS;
2341 __le32 bt_cmd_val[2] = {0};
2342 unsigned long flags = 0;
2343 void __iomem *bt_cmd;
2346 switch (table->type) {
2348 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2351 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2354 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2357 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2362 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2363 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2364 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2365 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2366 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2367 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2369 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2371 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2374 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2376 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2377 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2384 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
2385 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2388 bt_cmd_val[0] = cpu_to_le32(bt_ba);
2389 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2390 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2391 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2393 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2398 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2399 enum hns_roce_qp_state cur_state,
2400 enum hns_roce_qp_state new_state,
2401 struct hns_roce_qp_context *context,
2402 struct hns_roce_qp *hr_qp)
2405 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2406 [HNS_ROCE_QP_STATE_RST] = {
2407 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2408 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2409 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2411 [HNS_ROCE_QP_STATE_INIT] = {
2412 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2413 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2414 /* Note: In v1 engine, HW doesn't support RST2INIT.
2415 * We use RST2INIT cmd instead of INIT2INIT.
2417 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2418 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2420 [HNS_ROCE_QP_STATE_RTR] = {
2421 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2422 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2423 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2425 [HNS_ROCE_QP_STATE_RTS] = {
2426 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2427 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2428 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2429 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2431 [HNS_ROCE_QP_STATE_SQD] = {
2432 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2433 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2434 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2435 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2437 [HNS_ROCE_QP_STATE_ERR] = {
2438 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2439 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2443 struct hns_roce_cmd_mailbox *mailbox;
2444 struct device *dev = &hr_dev->pdev->dev;
2447 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2448 new_state >= HNS_ROCE_QP_NUM_STATE ||
2449 !op[cur_state][new_state]) {
2450 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2451 cur_state, new_state);
2455 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2456 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2457 HNS_ROCE_CMD_2RST_QP,
2458 HNS_ROCE_CMD_TIMEOUT_MSECS);
2460 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2461 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2462 HNS_ROCE_CMD_2ERR_QP,
2463 HNS_ROCE_CMD_TIMEOUT_MSECS);
2465 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2466 if (IS_ERR(mailbox))
2467 return PTR_ERR(mailbox);
2469 memcpy(mailbox->buf, context, sizeof(*context));
2471 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2472 op[cur_state][new_state],
2473 HNS_ROCE_CMD_TIMEOUT_MSECS);
2475 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2479 static int find_wqe_mtt(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
2480 u64 *sq_ba, u64 *rq_ba, dma_addr_t *bt_ba)
2482 struct ib_device *ibdev = &hr_dev->ib_dev;
2485 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, sq_ba, 1, bt_ba);
2487 ibdev_err(ibdev, "Failed to find SQ ba\n");
2491 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, rq_ba,
2494 ibdev_err(ibdev, "Failed to find RQ ba\n");
2501 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2502 int attr_mask, enum ib_qp_state cur_state,
2503 enum ib_qp_state new_state)
2505 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2506 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2507 struct hns_roce_sqp_context *context;
2508 dma_addr_t dma_handle = 0;
2515 context = kzalloc(sizeof(*context), GFP_KERNEL);
2519 /* Search QP buf's MTTs */
2520 if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2523 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2524 roce_set_field(context->qp1c_bytes_4,
2525 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2526 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2527 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2528 roce_set_field(context->qp1c_bytes_4,
2529 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2530 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2531 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2532 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2533 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2535 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2536 roce_set_field(context->qp1c_bytes_12,
2537 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2538 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2539 upper_32_bits(dma_handle));
2541 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2542 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2543 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2544 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2545 roce_set_bit(context->qp1c_bytes_16,
2546 QP1C_BYTES_16_SIGNALING_TYPE_S,
2547 hr_qp->sq_signal_bits);
2548 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2550 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2552 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2555 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2556 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2557 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2558 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2560 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2562 roce_set_field(context->qp1c_bytes_28,
2563 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2564 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2565 upper_32_bits(rq_ba));
2566 roce_set_field(context->qp1c_bytes_28,
2567 QP1C_BYTES_28_RQ_CUR_IDX_M,
2568 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2570 roce_set_field(context->qp1c_bytes_32,
2571 QP1C_BYTES_32_RX_CQ_NUM_M,
2572 QP1C_BYTES_32_RX_CQ_NUM_S,
2573 to_hr_cq(ibqp->recv_cq)->cqn);
2574 roce_set_field(context->qp1c_bytes_32,
2575 QP1C_BYTES_32_TX_CQ_NUM_M,
2576 QP1C_BYTES_32_TX_CQ_NUM_S,
2577 to_hr_cq(ibqp->send_cq)->cqn);
2579 context->cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
2581 roce_set_field(context->qp1c_bytes_40,
2582 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2583 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2584 upper_32_bits(sq_ba));
2585 roce_set_field(context->qp1c_bytes_40,
2586 QP1C_BYTES_40_SQ_CUR_IDX_M,
2587 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2589 /* Copy context to QP1C register */
2590 addr = (u32 __iomem *)(hr_dev->reg_base +
2591 ROCEE_QP1C_CFG0_0_REG +
2592 hr_qp->phy_port * sizeof(*context));
2594 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2595 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2596 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2597 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2598 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2599 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2600 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2601 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2602 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2603 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2606 /* Modify QP1C status */
2607 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2608 hr_qp->phy_port * sizeof(*context));
2609 tmp = cpu_to_le32(reg_val);
2610 roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2611 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2612 reg_val = le32_to_cpu(tmp);
2613 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2614 hr_qp->phy_port * sizeof(*context), reg_val);
2616 hr_qp->state = new_state;
2617 if (new_state == IB_QPS_RESET) {
2618 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2619 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2620 if (ibqp->send_cq != ibqp->recv_cq)
2621 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2638 static bool check_qp_state(enum ib_qp_state cur_state,
2639 enum ib_qp_state new_state)
2641 static const bool sm[][IB_QPS_ERR + 1] = {
2642 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
2643 [IB_QPS_INIT] = true },
2644 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
2645 [IB_QPS_INIT] = true,
2646 [IB_QPS_RTR] = true,
2647 [IB_QPS_ERR] = true },
2648 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
2649 [IB_QPS_RTS] = true,
2650 [IB_QPS_ERR] = true },
2651 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
2654 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
2657 return sm[cur_state][new_state];
2660 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2661 int attr_mask, enum ib_qp_state cur_state,
2662 enum ib_qp_state new_state)
2664 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2665 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2666 struct device *dev = &hr_dev->pdev->dev;
2667 struct hns_roce_qp_context *context;
2668 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2669 dma_addr_t dma_handle_2 = 0;
2670 dma_addr_t dma_handle = 0;
2671 __le32 doorbell[2] = {0};
2681 if (!check_qp_state(cur_state, new_state)) {
2682 ibdev_err(ibqp->device,
2683 "not support QP(%u) status from %d to %d\n",
2684 ibqp->qp_num, cur_state, new_state);
2688 context = kzalloc(sizeof(*context), GFP_KERNEL);
2692 /* Search qp buf's mtts */
2693 if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2696 /* Search IRRL's mtts */
2697 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2698 hr_qp->qpn, &dma_handle_2);
2699 if (mtts_2 == NULL) {
2700 dev_err(dev, "qp irrl_table find failed\n");
2707 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2708 * Optional param: NA
2710 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2711 roce_set_field(context->qpc_bytes_4,
2712 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2713 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2714 to_hr_qp_type(hr_qp->ibqp.qp_type));
2716 roce_set_bit(context->qpc_bytes_4,
2717 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2718 roce_set_bit(context->qpc_bytes_4,
2719 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2720 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2721 roce_set_bit(context->qpc_bytes_4,
2722 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2723 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2725 roce_set_bit(context->qpc_bytes_4,
2726 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2727 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2729 roce_set_bit(context->qpc_bytes_4,
2730 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2731 roce_set_field(context->qpc_bytes_4,
2732 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2733 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2734 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2735 roce_set_field(context->qpc_bytes_4,
2736 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2737 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2738 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2739 roce_set_field(context->qpc_bytes_4,
2740 QP_CONTEXT_QPC_BYTES_4_PD_M,
2741 QP_CONTEXT_QPC_BYTES_4_PD_S,
2742 to_hr_pd(ibqp->pd)->pdn);
2743 hr_qp->access_flags = attr->qp_access_flags;
2744 roce_set_field(context->qpc_bytes_8,
2745 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2746 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2747 to_hr_cq(ibqp->send_cq)->cqn);
2748 roce_set_field(context->qpc_bytes_8,
2749 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2750 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2751 to_hr_cq(ibqp->recv_cq)->cqn);
2754 roce_set_field(context->qpc_bytes_12,
2755 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2756 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2757 to_hr_srq(ibqp->srq)->srqn);
2759 roce_set_field(context->qpc_bytes_12,
2760 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2761 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2763 hr_qp->pkey_index = attr->pkey_index;
2764 roce_set_field(context->qpc_bytes_16,
2765 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2766 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2767 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2768 roce_set_field(context->qpc_bytes_4,
2769 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2770 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2771 to_hr_qp_type(hr_qp->ibqp.qp_type));
2772 roce_set_bit(context->qpc_bytes_4,
2773 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2774 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2775 roce_set_bit(context->qpc_bytes_4,
2776 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2777 !!(attr->qp_access_flags &
2778 IB_ACCESS_REMOTE_READ));
2779 roce_set_bit(context->qpc_bytes_4,
2780 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2781 !!(attr->qp_access_flags &
2782 IB_ACCESS_REMOTE_WRITE));
2784 roce_set_bit(context->qpc_bytes_4,
2785 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2786 !!(hr_qp->access_flags &
2787 IB_ACCESS_REMOTE_READ));
2788 roce_set_bit(context->qpc_bytes_4,
2789 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2790 !!(hr_qp->access_flags &
2791 IB_ACCESS_REMOTE_WRITE));
2794 roce_set_bit(context->qpc_bytes_4,
2795 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2796 roce_set_field(context->qpc_bytes_4,
2797 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2798 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2799 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2800 roce_set_field(context->qpc_bytes_4,
2801 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2802 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2803 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2804 roce_set_field(context->qpc_bytes_4,
2805 QP_CONTEXT_QPC_BYTES_4_PD_M,
2806 QP_CONTEXT_QPC_BYTES_4_PD_S,
2807 to_hr_pd(ibqp->pd)->pdn);
2809 roce_set_field(context->qpc_bytes_8,
2810 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2811 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2812 to_hr_cq(ibqp->send_cq)->cqn);
2813 roce_set_field(context->qpc_bytes_8,
2814 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2815 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2816 to_hr_cq(ibqp->recv_cq)->cqn);
2819 roce_set_field(context->qpc_bytes_12,
2820 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2821 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2822 to_hr_srq(ibqp->srq)->srqn);
2823 if (attr_mask & IB_QP_PKEY_INDEX)
2824 roce_set_field(context->qpc_bytes_12,
2825 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2826 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2829 roce_set_field(context->qpc_bytes_12,
2830 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2831 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2834 roce_set_field(context->qpc_bytes_16,
2835 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2836 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2837 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2838 if ((attr_mask & IB_QP_ALT_PATH) ||
2839 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2840 (attr_mask & IB_QP_PKEY_INDEX) ||
2841 (attr_mask & IB_QP_QKEY)) {
2842 dev_err(dev, "INIT2RTR attr_mask error\n");
2846 dmac = (u8 *)attr->ah_attr.roce.dmac;
2848 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2849 roce_set_field(context->qpc_bytes_24,
2850 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2851 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2852 upper_32_bits(dma_handle));
2853 roce_set_bit(context->qpc_bytes_24,
2854 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2856 roce_set_field(context->qpc_bytes_24,
2857 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2858 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2859 attr->min_rnr_timer);
2860 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2861 roce_set_field(context->qpc_bytes_32,
2862 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2863 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2864 ((u32)(dma_handle_2 >> 32)) &
2865 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2866 roce_set_field(context->qpc_bytes_32,
2867 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2868 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2869 roce_set_bit(context->qpc_bytes_32,
2870 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2872 roce_set_bit(context->qpc_bytes_32,
2873 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2874 hr_qp->sq_signal_bits);
2876 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2878 smac = (u8 *)hr_dev->dev_addr[port];
2879 /* when dmac equals smac or loop_idc is 1, it should loopback */
2880 if (ether_addr_equal_unaligned(dmac, smac) ||
2881 hr_dev->loop_idc == 0x1)
2882 roce_set_bit(context->qpc_bytes_32,
2883 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2885 roce_set_bit(context->qpc_bytes_32,
2886 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2887 rdma_ah_get_ah_flags(&attr->ah_attr));
2888 roce_set_field(context->qpc_bytes_32,
2889 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2890 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2891 ilog2((unsigned int)attr->max_dest_rd_atomic));
2893 if (attr_mask & IB_QP_DEST_QPN)
2894 roce_set_field(context->qpc_bytes_36,
2895 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2896 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2899 /* Configure GID index */
2900 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2901 roce_set_field(context->qpc_bytes_36,
2902 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2903 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2904 hns_get_gid_index(hr_dev,
2908 memcpy(&(context->dmac_l), dmac, 4);
2910 roce_set_field(context->qpc_bytes_44,
2911 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2912 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2913 *((u16 *)(&dmac[4])));
2914 roce_set_field(context->qpc_bytes_44,
2915 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2916 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2917 rdma_ah_get_static_rate(&attr->ah_attr));
2918 roce_set_field(context->qpc_bytes_44,
2919 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2920 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2923 roce_set_field(context->qpc_bytes_48,
2924 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2925 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2927 roce_set_field(context->qpc_bytes_48,
2928 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2929 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2930 grh->traffic_class);
2931 roce_set_field(context->qpc_bytes_48,
2932 QP_CONTEXT_QPC_BYTES_48_MTU_M,
2933 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2935 memcpy(context->dgid, grh->dgid.raw,
2936 sizeof(grh->dgid.raw));
2938 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2939 roce_get_field(context->qpc_bytes_44,
2940 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2941 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2943 roce_set_field(context->qpc_bytes_68,
2944 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2945 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2947 roce_set_field(context->qpc_bytes_68,
2948 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2949 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2951 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2953 roce_set_field(context->qpc_bytes_76,
2954 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2955 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2956 upper_32_bits(rq_ba));
2957 roce_set_field(context->qpc_bytes_76,
2958 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2959 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2961 context->rx_rnr_time = 0;
2963 roce_set_field(context->qpc_bytes_84,
2964 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2965 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2967 roce_set_field(context->qpc_bytes_84,
2968 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2969 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2971 roce_set_field(context->qpc_bytes_88,
2972 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2973 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2975 roce_set_bit(context->qpc_bytes_88,
2976 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2977 roce_set_bit(context->qpc_bytes_88,
2978 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2979 roce_set_field(context->qpc_bytes_88,
2980 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2981 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2983 roce_set_field(context->qpc_bytes_88,
2984 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2985 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2988 context->dma_length = 0;
2993 roce_set_field(context->qpc_bytes_108,
2994 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2995 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2996 roce_set_bit(context->qpc_bytes_108,
2997 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2998 roce_set_bit(context->qpc_bytes_108,
2999 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3001 roce_set_field(context->qpc_bytes_112,
3002 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3003 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3004 roce_set_field(context->qpc_bytes_112,
3005 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3006 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3008 /* For chip resp ack */
3009 roce_set_field(context->qpc_bytes_156,
3010 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3011 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3013 roce_set_field(context->qpc_bytes_156,
3014 QP_CONTEXT_QPC_BYTES_156_SL_M,
3015 QP_CONTEXT_QPC_BYTES_156_SL_S,
3016 rdma_ah_get_sl(&attr->ah_attr));
3017 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3018 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3019 /* If exist optional param, return error */
3020 if ((attr_mask & IB_QP_ALT_PATH) ||
3021 (attr_mask & IB_QP_ACCESS_FLAGS) ||
3022 (attr_mask & IB_QP_QKEY) ||
3023 (attr_mask & IB_QP_PATH_MIG_STATE) ||
3024 (attr_mask & IB_QP_CUR_STATE) ||
3025 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3026 dev_err(dev, "RTR2RTS attr_mask error\n");
3030 context->rx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3032 roce_set_field(context->qpc_bytes_120,
3033 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3034 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3035 upper_32_bits(sq_ba));
3037 roce_set_field(context->qpc_bytes_124,
3038 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3039 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3040 roce_set_field(context->qpc_bytes_124,
3041 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3042 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3044 roce_set_field(context->qpc_bytes_128,
3045 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3046 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3048 roce_set_bit(context->qpc_bytes_128,
3049 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3050 roce_set_field(context->qpc_bytes_128,
3051 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3052 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3054 roce_set_bit(context->qpc_bytes_128,
3055 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3057 roce_set_field(context->qpc_bytes_132,
3058 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3059 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3060 roce_set_field(context->qpc_bytes_132,
3061 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3062 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3064 roce_set_field(context->qpc_bytes_136,
3065 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3066 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3068 roce_set_field(context->qpc_bytes_136,
3069 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3070 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3073 roce_set_field(context->qpc_bytes_140,
3074 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3075 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3076 (attr->sq_psn >> SQ_PSN_SHIFT));
3077 roce_set_field(context->qpc_bytes_140,
3078 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3079 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3080 roce_set_bit(context->qpc_bytes_140,
3081 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3083 roce_set_field(context->qpc_bytes_148,
3084 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3085 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3086 roce_set_field(context->qpc_bytes_148,
3087 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3088 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3090 roce_set_field(context->qpc_bytes_148,
3091 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3092 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3094 roce_set_field(context->qpc_bytes_148,
3095 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3096 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3098 context->rnr_retry = 0;
3100 roce_set_field(context->qpc_bytes_156,
3101 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3102 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3104 if (attr->timeout < 0x12) {
3105 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3107 roce_set_field(context->qpc_bytes_156,
3108 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3109 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3112 roce_set_field(context->qpc_bytes_156,
3113 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3114 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3117 roce_set_field(context->qpc_bytes_156,
3118 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3119 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3121 roce_set_field(context->qpc_bytes_156,
3122 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3123 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3125 roce_set_field(context->qpc_bytes_156,
3126 QP_CONTEXT_QPC_BYTES_156_SL_M,
3127 QP_CONTEXT_QPC_BYTES_156_SL_S,
3128 rdma_ah_get_sl(&attr->ah_attr));
3129 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3130 roce_set_field(context->qpc_bytes_156,
3131 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3132 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3133 ilog2((unsigned int)attr->max_rd_atomic));
3134 roce_set_field(context->qpc_bytes_156,
3135 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3136 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3137 context->pkt_use_len = 0;
3139 roce_set_field(context->qpc_bytes_164,
3140 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3141 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3142 roce_set_field(context->qpc_bytes_164,
3143 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3144 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3146 roce_set_field(context->qpc_bytes_168,
3147 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3148 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3150 roce_set_field(context->qpc_bytes_168,
3151 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3152 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3153 roce_set_field(context->qpc_bytes_168,
3154 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3155 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3156 roce_set_bit(context->qpc_bytes_168,
3157 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3158 roce_set_bit(context->qpc_bytes_168,
3159 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3160 roce_set_bit(context->qpc_bytes_168,
3161 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3162 context->sge_use_len = 0;
3164 roce_set_field(context->qpc_bytes_176,
3165 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3166 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3167 roce_set_field(context->qpc_bytes_176,
3168 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3169 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3171 roce_set_field(context->qpc_bytes_180,
3172 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3173 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3174 roce_set_field(context->qpc_bytes_180,
3175 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3176 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3178 context->tx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3180 roce_set_field(context->qpc_bytes_188,
3181 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3182 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3183 upper_32_bits(sq_ba));
3184 roce_set_bit(context->qpc_bytes_188,
3185 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3186 roce_set_field(context->qpc_bytes_188,
3187 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3188 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3192 /* Every status migrate must change state */
3193 roce_set_field(context->qpc_bytes_144,
3194 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3195 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3197 /* SW pass context to HW */
3198 ret = hns_roce_v1_qp_modify(hr_dev, to_hns_roce_state(cur_state),
3199 to_hns_roce_state(new_state), context,
3202 dev_err(dev, "hns_roce_qp_modify failed\n");
3207 * Use rst2init to instead of init2init with drv,
3208 * need to hw to flash RQ HEAD by DB again
3210 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3211 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3212 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3213 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3214 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3215 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3216 RQ_DOORBELL_U32_8_CMD_S, 1);
3217 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3219 if (ibqp->uobject) {
3220 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3221 hr_dev->odb_offset +
3222 DB_REG_OFFSET * hr_dev->priv_uar.index;
3225 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3228 hr_qp->state = new_state;
3230 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3231 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3232 if (attr_mask & IB_QP_PORT) {
3233 hr_qp->port = attr->port_num - 1;
3234 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3237 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3238 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3239 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3240 if (ibqp->send_cq != ibqp->recv_cq)
3241 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3254 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3255 const struct ib_qp_attr *attr, int attr_mask,
3256 enum ib_qp_state cur_state,
3257 enum ib_qp_state new_state)
3259 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
3262 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3263 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3266 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3270 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3273 case HNS_ROCE_QP_STATE_RST:
3274 return IB_QPS_RESET;
3275 case HNS_ROCE_QP_STATE_INIT:
3277 case HNS_ROCE_QP_STATE_RTR:
3279 case HNS_ROCE_QP_STATE_RTS:
3281 case HNS_ROCE_QP_STATE_SQD:
3283 case HNS_ROCE_QP_STATE_ERR:
3290 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3291 struct hns_roce_qp *hr_qp,
3292 struct hns_roce_qp_context *hr_context)
3294 struct hns_roce_cmd_mailbox *mailbox;
3297 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3298 if (IS_ERR(mailbox))
3299 return PTR_ERR(mailbox);
3301 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3302 HNS_ROCE_CMD_QUERY_QP,
3303 HNS_ROCE_CMD_TIMEOUT_MSECS);
3305 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3307 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3309 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3314 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3316 struct ib_qp_init_attr *qp_init_attr)
3318 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3319 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3320 struct hns_roce_sqp_context context;
3323 mutex_lock(&hr_qp->mutex);
3325 if (hr_qp->state == IB_QPS_RESET) {
3326 qp_attr->qp_state = IB_QPS_RESET;
3330 addr = ROCEE_QP1C_CFG0_0_REG +
3331 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3332 context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3333 context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3334 context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3335 context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3336 context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3337 context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3338 context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3339 context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3340 context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3341 context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3343 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3344 QP1C_BYTES_4_QP_STATE_M,
3345 QP1C_BYTES_4_QP_STATE_S);
3346 qp_attr->qp_state = hr_qp->state;
3347 qp_attr->path_mtu = IB_MTU_256;
3348 qp_attr->path_mig_state = IB_MIG_ARMED;
3349 qp_attr->qkey = QKEY_VAL;
3350 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3351 qp_attr->rq_psn = 0;
3352 qp_attr->sq_psn = 0;
3353 qp_attr->dest_qp_num = 1;
3354 qp_attr->qp_access_flags = 6;
3356 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3357 QP1C_BYTES_20_PKEY_IDX_M,
3358 QP1C_BYTES_20_PKEY_IDX_S);
3359 qp_attr->port_num = hr_qp->port + 1;
3360 qp_attr->sq_draining = 0;
3361 qp_attr->max_rd_atomic = 0;
3362 qp_attr->max_dest_rd_atomic = 0;
3363 qp_attr->min_rnr_timer = 0;
3364 qp_attr->timeout = 0;
3365 qp_attr->retry_cnt = 0;
3366 qp_attr->rnr_retry = 0;
3367 qp_attr->alt_timeout = 0;
3370 qp_attr->cur_qp_state = qp_attr->qp_state;
3371 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3372 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3373 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3374 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3375 qp_attr->cap.max_inline_data = 0;
3376 qp_init_attr->cap = qp_attr->cap;
3377 qp_init_attr->create_flags = 0;
3379 mutex_unlock(&hr_qp->mutex);
3384 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3386 struct ib_qp_init_attr *qp_init_attr)
3388 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3389 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3390 struct device *dev = &hr_dev->pdev->dev;
3391 struct hns_roce_qp_context *context;
3396 context = kzalloc(sizeof(*context), GFP_KERNEL);
3400 memset(qp_attr, 0, sizeof(*qp_attr));
3401 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3403 mutex_lock(&hr_qp->mutex);
3405 if (hr_qp->state == IB_QPS_RESET) {
3406 qp_attr->qp_state = IB_QPS_RESET;
3410 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3412 dev_err(dev, "query qpc error\n");
3417 state = roce_get_field(context->qpc_bytes_144,
3418 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3419 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3420 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3421 if (tmp_qp_state == -1) {
3422 dev_err(dev, "to_ib_qp_state error\n");
3426 hr_qp->state = (u8)tmp_qp_state;
3427 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3428 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3429 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3430 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3431 qp_attr->path_mig_state = IB_MIG_ARMED;
3432 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3433 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3434 qp_attr->qkey = QKEY_VAL;
3436 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3437 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3438 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3439 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3440 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3441 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3442 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3443 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3444 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3445 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3446 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3447 ((roce_get_bit(context->qpc_bytes_4,
3448 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3449 ((roce_get_bit(context->qpc_bytes_4,
3450 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3452 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3453 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3454 struct ib_global_route *grh =
3455 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3457 rdma_ah_set_sl(&qp_attr->ah_attr,
3458 roce_get_field(context->qpc_bytes_156,
3459 QP_CONTEXT_QPC_BYTES_156_SL_M,
3460 QP_CONTEXT_QPC_BYTES_156_SL_S));
3461 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3463 roce_get_field(context->qpc_bytes_48,
3464 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3465 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3467 roce_get_field(context->qpc_bytes_36,
3468 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3469 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3471 roce_get_field(context->qpc_bytes_44,
3472 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3473 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3474 grh->traffic_class =
3475 roce_get_field(context->qpc_bytes_48,
3476 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3477 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3479 memcpy(grh->dgid.raw, context->dgid,
3480 sizeof(grh->dgid.raw));
3483 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3484 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3485 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3486 qp_attr->port_num = hr_qp->port + 1;
3487 qp_attr->sq_draining = 0;
3488 qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3489 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3490 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3491 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3492 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3493 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3494 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3495 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3496 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3497 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3498 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3499 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3500 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3501 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3502 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3503 qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3506 qp_attr->cur_qp_state = qp_attr->qp_state;
3507 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3508 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3510 if (!ibqp->uobject) {
3511 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3512 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3514 qp_attr->cap.max_send_wr = 0;
3515 qp_attr->cap.max_send_sge = 0;
3518 qp_init_attr->cap = qp_attr->cap;
3521 mutex_unlock(&hr_qp->mutex);
3526 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3528 struct ib_qp_init_attr *qp_init_attr)
3530 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3532 return hr_qp->doorbell_qpn <= 1 ?
3533 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3534 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3537 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3539 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3540 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3541 struct hns_roce_cq *send_cq, *recv_cq;
3544 ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3548 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
3549 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3551 hns_roce_lock_cqs(send_cq, recv_cq);
3554 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
3556 to_hr_srq(hr_qp->ibqp.srq) :
3559 if (send_cq && send_cq != recv_cq)
3560 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3562 hns_roce_qp_remove(hr_dev, hr_qp);
3563 hns_roce_unlock_cqs(send_cq, recv_cq);
3565 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
3570 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3572 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3573 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3574 struct device *dev = &hr_dev->pdev->dev;
3580 * Before freeing cq buffer, we need to ensure that the outstanding CQE
3581 * have been written by checking the CQE counter.
3583 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3585 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3586 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3589 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3590 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3593 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3594 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3595 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3604 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, u32 req_not)
3606 roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3607 (req_not << eq->log_entries), eq->doorbell);
3610 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3611 struct hns_roce_aeqe *aeqe, int qpn)
3613 struct device *dev = &hr_dev->pdev->dev;
3615 dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3616 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3617 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3618 case HNS_ROCE_LWQCE_QPC_ERROR:
3619 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3621 case HNS_ROCE_LWQCE_MTU_ERROR:
3622 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3624 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3625 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3627 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3628 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3630 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3631 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3633 case HNS_ROCE_LWQCE_SL_ERROR:
3634 dev_warn(dev, "QP %d, SL error.\n", qpn);
3636 case HNS_ROCE_LWQCE_PORT_ERROR:
3637 dev_warn(dev, "QP %d, port error.\n", qpn);
3644 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3645 struct hns_roce_aeqe *aeqe,
3648 struct device *dev = &hr_dev->pdev->dev;
3650 dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3651 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3652 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3653 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3654 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3656 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3657 dev_warn(dev, "QP %d, length error.\n", qpn);
3659 case HNS_ROCE_LAVWQE_VA_ERROR:
3660 dev_warn(dev, "QP %d, VA error.\n", qpn);
3662 case HNS_ROCE_LAVWQE_PD_ERROR:
3663 dev_err(dev, "QP %d, PD error.\n", qpn);
3665 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3666 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3668 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3669 dev_warn(dev, "QP %d, key state error.\n", qpn);
3671 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3672 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3679 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3680 struct hns_roce_aeqe *aeqe,
3683 struct device *dev = &hr_dev->pdev->dev;
3687 qpn = roce_get_field(aeqe->event.queue_event.num,
3688 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3689 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3690 phy_port = roce_get_field(aeqe->event.queue_event.num,
3691 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3692 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3694 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3696 switch (event_type) {
3697 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3698 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3699 "QP %d, phy_port %d.\n", qpn, phy_port);
3701 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3702 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3704 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3705 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3711 hns_roce_qp_event(hr_dev, qpn, event_type);
3714 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3715 struct hns_roce_aeqe *aeqe,
3718 struct device *dev = &hr_dev->pdev->dev;
3721 cqn = roce_get_field(aeqe->event.queue_event.num,
3722 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3723 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3725 switch (event_type) {
3726 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3727 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3729 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3730 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3732 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3733 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3739 hns_roce_cq_event(hr_dev, cqn, event_type);
3742 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3743 struct hns_roce_aeqe *aeqe)
3745 struct device *dev = &hr_dev->pdev->dev;
3747 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3748 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3749 case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3750 dev_warn(dev, "SDB overflow.\n");
3752 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3753 dev_warn(dev, "SDB almost overflow.\n");
3755 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3756 dev_warn(dev, "SDB almost empty.\n");
3758 case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3759 dev_warn(dev, "ODB overflow.\n");
3761 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3762 dev_warn(dev, "ODB almost overflow.\n");
3764 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3765 dev_warn(dev, "SDB almost empty.\n");
3772 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3774 unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
3776 return (struct hns_roce_aeqe *)((u8 *)
3777 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3778 off % HNS_ROCE_BA_SIZE);
3781 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3783 struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3785 return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3786 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3789 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3790 struct hns_roce_eq *eq)
3792 struct device *dev = &hr_dev->pdev->dev;
3793 struct hns_roce_aeqe *aeqe;
3794 int aeqes_found = 0;
3797 while ((aeqe = next_aeqe_sw_v1(eq))) {
3798 /* Make sure we read the AEQ entry after we have checked the
3803 dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
3805 roce_get_field(aeqe->asyn,
3806 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3807 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3808 event_type = roce_get_field(aeqe->asyn,
3809 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3810 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3811 switch (event_type) {
3812 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3813 dev_warn(dev, "PATH MIG not supported\n");
3815 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3816 dev_warn(dev, "COMMUNICATION established\n");
3818 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3819 dev_warn(dev, "SQ DRAINED not supported\n");
3821 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3822 dev_warn(dev, "PATH MIG failed\n");
3824 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3825 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3826 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3827 hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3829 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3830 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3831 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3832 dev_warn(dev, "SRQ not support!\n");
3834 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3835 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3836 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3837 hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3839 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3840 dev_warn(dev, "port change.\n");
3842 case HNS_ROCE_EVENT_TYPE_MB:
3843 hns_roce_cmd_event(hr_dev,
3844 le16_to_cpu(aeqe->event.cmd.token),
3845 aeqe->event.cmd.status,
3846 le64_to_cpu(aeqe->event.cmd.out_param
3849 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3850 hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3853 dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3854 event_type, eq->eqn, eq->cons_index);
3861 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1)
3865 set_eq_cons_index_v1(eq, 0);
3870 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3872 unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
3874 return (struct hns_roce_ceqe *)((u8 *)
3875 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3876 off % HNS_ROCE_BA_SIZE);
3879 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3881 struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3883 return (!!(roce_get_bit(ceqe->comp,
3884 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3885 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3888 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3889 struct hns_roce_eq *eq)
3891 struct hns_roce_ceqe *ceqe;
3892 int ceqes_found = 0;
3895 while ((ceqe = next_ceqe_sw_v1(eq))) {
3896 /* Make sure we read CEQ entry after we have checked the
3901 cqn = roce_get_field(ceqe->comp,
3902 HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
3903 HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
3904 hns_roce_cq_completion(hr_dev, cqn);
3909 if (eq->cons_index >
3910 EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1)
3914 set_eq_cons_index_v1(eq, 0);
3919 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
3921 struct hns_roce_eq *eq = eq_ptr;
3922 struct hns_roce_dev *hr_dev = eq->hr_dev;
3925 if (eq->type_flag == HNS_ROCE_CEQ)
3926 /* CEQ irq routine, CEQ is pulse irq, not clear */
3927 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
3929 /* AEQ irq routine, AEQ is pulse irq, not clear */
3930 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
3932 return IRQ_RETVAL(int_work);
3935 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
3937 struct hns_roce_dev *hr_dev = dev_id;
3938 struct device *dev = &hr_dev->pdev->dev;
3950 * Abnormal interrupt:
3951 * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
3952 * interrupt, mask irq, clear irq, cancel mask operation
3954 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
3955 tmp = cpu_to_le32(aeshift_val);
3958 if (roce_get_bit(tmp,
3959 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
3960 dev_warn(dev, "AEQ overflow!\n");
3963 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
3964 tmp = cpu_to_le32(caepaemask_val);
3965 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
3966 HNS_ROCE_INT_MASK_ENABLE);
3967 caepaemask_val = le32_to_cpu(tmp);
3968 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
3970 /* Clear int state(INT_WC : write 1 clear) */
3971 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
3972 tmp = cpu_to_le32(caepaest_val);
3973 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
3974 caepaest_val = le32_to_cpu(tmp);
3975 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
3978 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
3979 tmp = cpu_to_le32(caepaemask_val);
3980 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
3981 HNS_ROCE_INT_MASK_DISABLE);
3982 caepaemask_val = le32_to_cpu(tmp);
3983 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
3986 /* CEQ almost overflow */
3987 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
3988 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
3989 i * CEQ_REG_OFFSET);
3990 tmp = cpu_to_le32(ceshift_val);
3992 if (roce_get_bit(tmp,
3993 ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
3994 dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
3998 cemask_val = roce_read(hr_dev,
3999 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4000 i * CEQ_REG_OFFSET);
4001 tmp = cpu_to_le32(cemask_val);
4003 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4004 HNS_ROCE_INT_MASK_ENABLE);
4005 cemask_val = le32_to_cpu(tmp);
4006 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4007 i * CEQ_REG_OFFSET, cemask_val);
4009 /* Clear int state(INT_WC : write 1 clear) */
4010 cealmovf_val = roce_read(hr_dev,
4011 ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4012 i * CEQ_REG_OFFSET);
4013 tmp = cpu_to_le32(cealmovf_val);
4015 ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4017 cealmovf_val = le32_to_cpu(tmp);
4018 roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4019 i * CEQ_REG_OFFSET, cealmovf_val);
4022 cemask_val = roce_read(hr_dev,
4023 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4024 i * CEQ_REG_OFFSET);
4025 tmp = cpu_to_le32(cemask_val);
4027 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4028 HNS_ROCE_INT_MASK_DISABLE);
4029 cemask_val = le32_to_cpu(tmp);
4030 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4031 i * CEQ_REG_OFFSET, cemask_val);
4035 /* ECC multi-bit error alarm */
4036 dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4037 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4038 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4039 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4041 dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4042 roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4043 roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4044 roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4046 return IRQ_RETVAL(int_work);
4049 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4057 aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4058 tmp = cpu_to_le32(aemask_val);
4059 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4061 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4062 aemask_val = le32_to_cpu(tmp);
4063 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4066 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4068 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4069 i * CEQ_REG_OFFSET, masken);
4073 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4074 struct hns_roce_eq *eq)
4076 int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4077 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4083 for (i = 0; i < npages; ++i)
4084 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4085 eq->buf_list[i].buf, eq->buf_list[i].map);
4087 kfree(eq->buf_list);
4090 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4093 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4098 tmp = cpu_to_le32(val);
4102 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4103 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4104 HNS_ROCE_EQ_STAT_VALID);
4107 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4108 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4109 HNS_ROCE_EQ_STAT_INVALID);
4111 val = le32_to_cpu(tmp);
4115 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4116 struct hns_roce_eq *eq)
4118 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4119 struct device *dev = &hr_dev->pdev->dev;
4120 dma_addr_t tmp_dma_addr;
4131 num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4132 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4134 if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4135 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4136 (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4141 eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4145 for (i = 0; i < num_bas; ++i) {
4146 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4149 if (!eq->buf_list[i].buf) {
4151 goto err_out_free_pages;
4154 eq->buf_list[i].map = tmp_dma_addr;
4157 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4158 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4159 HNS_ROCE_EQ_STAT_INVALID);
4160 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4161 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4163 eqshift_val = le32_to_cpu(tmp);
4164 writel(eqshift_val, eqc);
4166 /* Configure eq extended address 12~44bit */
4167 writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4170 * Configure eq extended address 45~49 bit.
4171 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4172 * using 4K page, and shift more 32 because of
4173 * calculating the high 32 bit value evaluated to hardware.
4175 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4176 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4177 eq->buf_list[0].map >> 44);
4178 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4179 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4180 eqcuridx_val = le32_to_cpu(tmp1);
4181 writel(eqcuridx_val, eqc + 8);
4183 /* Configure eq consumer index */
4184 roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4185 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4186 eqconsindx_val = le32_to_cpu(tmp2);
4187 writel(eqconsindx_val, eqc + 0xc);
4192 for (i -= 1; i >= 0; i--)
4193 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4194 eq->buf_list[i].map);
4196 kfree(eq->buf_list);
4200 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4202 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4203 struct device *dev = &hr_dev->pdev->dev;
4204 struct hns_roce_eq *eq;
4210 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4211 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4213 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4217 eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4219 if (!eq_table->eqc_base) {
4221 goto err_eqc_base_alloc_fail;
4224 for (i = 0; i < eq_num; i++) {
4225 eq = &eq_table->eq[i];
4226 eq->hr_dev = hr_dev;
4228 eq->irq = hr_dev->irq[i];
4229 eq->log_page_size = PAGE_SHIFT;
4231 if (i < hr_dev->caps.num_comp_vectors) {
4233 eq_table->eqc_base[i] = hr_dev->reg_base +
4234 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4236 eq->type_flag = HNS_ROCE_CEQ;
4237 eq->doorbell = hr_dev->reg_base +
4238 ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4240 eq->entries = hr_dev->caps.ceqe_depth;
4241 eq->log_entries = ilog2(eq->entries);
4242 eq->eqe_size = HNS_ROCE_CEQE_SIZE;
4245 eq_table->eqc_base[i] = hr_dev->reg_base +
4246 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4247 eq->type_flag = HNS_ROCE_AEQ;
4248 eq->doorbell = hr_dev->reg_base +
4249 ROCEE_CAEP_AEQE_CONS_IDX_REG;
4250 eq->entries = hr_dev->caps.aeqe_depth;
4251 eq->log_entries = ilog2(eq->entries);
4252 eq->eqe_size = HNS_ROCE_AEQE_SIZE;
4257 hns_roce_v1_int_mask_enable(hr_dev);
4259 /* Configure ce int interval */
4260 roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4261 HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4263 /* Configure ce int burst num */
4264 roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4265 HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4267 for (i = 0; i < eq_num; i++) {
4268 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4270 dev_err(dev, "eq create failed\n");
4271 goto err_create_eq_fail;
4275 for (j = 0; j < irq_num; j++) {
4277 ret = request_irq(hr_dev->irq[j],
4278 hns_roce_v1_msix_interrupt_eq, 0,
4279 hr_dev->irq_names[j],
4282 ret = request_irq(hr_dev->irq[j],
4283 hns_roce_v1_msix_interrupt_abn, 0,
4284 hr_dev->irq_names[j], hr_dev);
4287 dev_err(dev, "request irq error!\n");
4288 goto err_request_irq_fail;
4292 for (i = 0; i < eq_num; i++)
4293 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4297 err_request_irq_fail:
4298 for (j -= 1; j >= 0; j--)
4299 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4302 for (i -= 1; i >= 0; i--)
4303 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4305 kfree(eq_table->eqc_base);
4307 err_eqc_base_alloc_fail:
4308 kfree(eq_table->eq);
4313 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4315 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4320 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4321 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4322 for (i = 0; i < eq_num; i++) {
4324 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4326 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4328 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4330 for (i = eq_num; i < irq_num; i++)
4331 free_irq(hr_dev->irq[i], hr_dev);
4333 kfree(eq_table->eqc_base);
4334 kfree(eq_table->eq);
4337 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4338 .destroy_qp = hns_roce_v1_destroy_qp,
4339 .poll_cq = hns_roce_v1_poll_cq,
4340 .post_recv = hns_roce_v1_post_recv,
4341 .post_send = hns_roce_v1_post_send,
4342 .query_qp = hns_roce_v1_query_qp,
4343 .req_notify_cq = hns_roce_v1_req_notify_cq,
4346 static const struct hns_roce_hw hns_roce_hw_v1 = {
4347 .reset = hns_roce_v1_reset,
4348 .hw_profile = hns_roce_v1_profile,
4349 .hw_init = hns_roce_v1_init,
4350 .hw_exit = hns_roce_v1_exit,
4351 .post_mbox = hns_roce_v1_post_mbox,
4352 .poll_mbox_done = hns_roce_v1_chk_mbox,
4353 .set_gid = hns_roce_v1_set_gid,
4354 .set_mac = hns_roce_v1_set_mac,
4355 .set_mtu = hns_roce_v1_set_mtu,
4356 .write_mtpt = hns_roce_v1_write_mtpt,
4357 .write_cqc = hns_roce_v1_write_cqc,
4358 .clear_hem = hns_roce_v1_clear_hem,
4359 .modify_qp = hns_roce_v1_modify_qp,
4360 .query_qp = hns_roce_v1_query_qp,
4361 .destroy_qp = hns_roce_v1_destroy_qp,
4362 .post_send = hns_roce_v1_post_send,
4363 .post_recv = hns_roce_v1_post_recv,
4364 .req_notify_cq = hns_roce_v1_req_notify_cq,
4365 .poll_cq = hns_roce_v1_poll_cq,
4366 .dereg_mr = hns_roce_v1_dereg_mr,
4367 .destroy_cq = hns_roce_v1_destroy_cq,
4368 .init_eq = hns_roce_v1_init_eq_table,
4369 .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4370 .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4373 static const struct of_device_id hns_roce_of_match[] = {
4374 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4377 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4379 static const struct acpi_device_id hns_roce_acpi_match[] = {
4380 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4383 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4386 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4390 /* get the 'device' corresponding to the matching 'fwnode' */
4391 dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4392 /* get the platform device */
4393 return dev ? to_platform_device(dev) : NULL;
4396 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4398 struct device *dev = &hr_dev->pdev->dev;
4399 struct platform_device *pdev = NULL;
4400 struct net_device *netdev = NULL;
4401 struct device_node *net_node;
4407 /* check if we are compatible with the underlying SoC */
4408 if (dev_of_node(dev)) {
4409 const struct of_device_id *of_id;
4411 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4413 dev_err(dev, "device is not compatible!\n");
4416 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4418 dev_err(dev, "couldn't get H/W specific DT data!\n");
4421 } else if (is_acpi_device_node(dev->fwnode)) {
4422 const struct acpi_device_id *acpi_id;
4424 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4426 dev_err(dev, "device is not compatible!\n");
4429 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4431 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4435 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4439 /* get the mapped register base address */
4440 hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4441 if (IS_ERR(hr_dev->reg_base))
4442 return PTR_ERR(hr_dev->reg_base);
4444 /* read the node_guid of IB device from the DT or ACPI */
4445 ret = device_property_read_u8_array(dev, "node-guid",
4446 (u8 *)&hr_dev->ib_dev.node_guid,
4449 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4453 /* get the RoCE associated ethernet ports or netdevices */
4454 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4455 if (dev_of_node(dev)) {
4456 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4460 pdev = of_find_device_by_node(net_node);
4461 } else if (is_acpi_device_node(dev->fwnode)) {
4462 struct fwnode_reference_args args;
4464 ret = acpi_node_get_property_reference(dev->fwnode,
4469 pdev = hns_roce_find_pdev(args.fwnode);
4471 dev_err(dev, "cannot read data from DT or ACPI\n");
4476 netdev = platform_get_drvdata(pdev);
4479 hr_dev->iboe.netdevs[port_cnt] = netdev;
4480 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4482 dev_err(dev, "no netdev found with pdev %s\n",
4490 if (port_cnt == 0) {
4491 dev_err(dev, "unable to get eth-handle for available ports!\n");
4495 hr_dev->caps.num_ports = port_cnt;
4497 /* cmd issue mode: 0 is poll, 1 is event */
4498 hr_dev->cmd_mod = 1;
4499 hr_dev->loop_idc = 0;
4500 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4501 hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4503 /* read the interrupt names from the DT or ACPI */
4504 ret = device_property_read_string_array(dev, "interrupt-names",
4506 HNS_ROCE_V1_MAX_IRQ_NUM);
4508 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4512 /* fetch the interrupt numbers */
4513 for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4514 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4515 if (hr_dev->irq[i] <= 0)
4523 * hns_roce_probe - RoCE driver entrance
4524 * @pdev: pointer to platform device
4528 static int hns_roce_probe(struct platform_device *pdev)
4531 struct hns_roce_dev *hr_dev;
4532 struct device *dev = &pdev->dev;
4534 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4538 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4539 if (!hr_dev->priv) {
4541 goto error_failed_kzalloc;
4544 hr_dev->pdev = pdev;
4546 platform_set_drvdata(pdev, hr_dev);
4548 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4549 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4550 dev_err(dev, "Not usable DMA addressing mode\n");
4552 goto error_failed_get_cfg;
4555 ret = hns_roce_get_cfg(hr_dev);
4557 dev_err(dev, "Get Configuration failed!\n");
4558 goto error_failed_get_cfg;
4561 ret = hns_roce_init(hr_dev);
4563 dev_err(dev, "RoCE engine init failed!\n");
4564 goto error_failed_get_cfg;
4569 error_failed_get_cfg:
4570 kfree(hr_dev->priv);
4572 error_failed_kzalloc:
4573 ib_dealloc_device(&hr_dev->ib_dev);
4579 * hns_roce_remove - remove RoCE device
4580 * @pdev: pointer to platform device
4582 static int hns_roce_remove(struct platform_device *pdev)
4584 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4586 hns_roce_exit(hr_dev);
4587 kfree(hr_dev->priv);
4588 ib_dealloc_device(&hr_dev->ib_dev);
4593 static struct platform_driver hns_roce_driver = {
4594 .probe = hns_roce_probe,
4595 .remove = hns_roce_remove,
4598 .of_match_table = hns_roce_of_match,
4599 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4603 module_platform_driver(hns_roce_driver);
4605 MODULE_LICENSE("Dual BSD/GPL");
4606 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4607 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4608 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4609 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");