drivers/infiniband/hw/hns/hns_roce_hw_v1.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/platform_device.h>
  34 #include <linux/acpi.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <rdma/ib_umem.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include "hns_roce_cmd.h"
  43 #include "hns_roce_hem.h"
  44 #include "hns_roce_hw_v1.h"
  45
  46 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
  47 {
  48         dseg->lkey = cpu_to_le32(sg->lkey);
  49         dseg->addr = cpu_to_le64(sg->addr);
  50         dseg->len  = cpu_to_le32(sg->length);
  51 }
  52
  53 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
  54                           u32 rkey)
  55 {
  56         rseg->raddr = cpu_to_le64(remote_addr);
  57         rseg->rkey  = cpu_to_le32(rkey);
  58         rseg->len   = 0;
  59 }
  60
  61 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
  62                                  const struct ib_send_wr *wr,
  63                                  const struct ib_send_wr **bad_wr)
  64 {
  65         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  66         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
  67         struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
  68         struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
  69         struct hns_roce_wqe_data_seg *dseg = NULL;
  70         struct hns_roce_qp *qp = to_hr_qp(ibqp);
  71         struct device *dev = &hr_dev->pdev->dev;
  72         struct hns_roce_sq_db sq_db;
  73         int ps_opcode = 0, i = 0;
  74         unsigned long flags = 0;
  75         void *wqe = NULL;
  76         u32 doorbell[2];
  77         int nreq = 0;
  78         u32 ind = 0;
  79         int ret = 0;
  80         u8 *smac;
  81         int loopback;
  82
  83         if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
  84                 ibqp->qp_type != IB_QPT_RC)) {
  85                 dev_err(dev, "un-supported QP type\n");
  86                 *bad_wr = NULL;
  87                 return -EOPNOTSUPP;
  88         }
  89
  90         spin_lock_irqsave(&qp->sq.lock, flags);
  91         ind = qp->sq_next_wqe;
  92         for (nreq = 0; wr; ++nreq, wr = wr->next) {
  93                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
  94                         ret = -ENOMEM;
  95                         *bad_wr = wr;
  96                         goto out;
  97                 }
  98
  99                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 100                         dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
 101                                 wr->num_sge, qp->sq.max_gs);
 102                         ret = -EINVAL;
 103                         *bad_wr = wr;
 104                         goto out;
 105                 }
 106
 107                 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 108                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
 109                                                                       wr->wr_id;
 110
 111                 /* Corresponding to the RC and RD type wqe process separately */
 112                 if (ibqp->qp_type == IB_QPT_GSI) {
 113                         ud_sq_wqe = wqe;
 114                         roce_set_field(ud_sq_wqe->dmac_h,
 115                                        UD_SEND_WQE_U32_4_DMAC_0_M,
 116                                        UD_SEND_WQE_U32_4_DMAC_0_S,
 117                                        ah->av.mac[0]);
 118                         roce_set_field(ud_sq_wqe->dmac_h,
 119                                        UD_SEND_WQE_U32_4_DMAC_1_M,
 120                                        UD_SEND_WQE_U32_4_DMAC_1_S,
 121                                        ah->av.mac[1]);
 122                         roce_set_field(ud_sq_wqe->dmac_h,
 123                                        UD_SEND_WQE_U32_4_DMAC_2_M,
 124                                        UD_SEND_WQE_U32_4_DMAC_2_S,
 125                                        ah->av.mac[2]);
 126                         roce_set_field(ud_sq_wqe->dmac_h,
 127                                        UD_SEND_WQE_U32_4_DMAC_3_M,
 128                                        UD_SEND_WQE_U32_4_DMAC_3_S,
 129                                        ah->av.mac[3]);
 130
 131                         roce_set_field(ud_sq_wqe->u32_8,
 132                                        UD_SEND_WQE_U32_8_DMAC_4_M,
 133                                        UD_SEND_WQE_U32_8_DMAC_4_S,
 134                                        ah->av.mac[4]);
 135                         roce_set_field(ud_sq_wqe->u32_8,
 136                                        UD_SEND_WQE_U32_8_DMAC_5_M,
 137                                        UD_SEND_WQE_U32_8_DMAC_5_S,
 138                                        ah->av.mac[5]);
 139
 140                         smac = (u8 *)hr_dev->dev_addr[qp->port];
 141                         loopback = ether_addr_equal_unaligned(ah->av.mac,
 142                                                               smac) ? 1 : 0;
 143                         roce_set_bit(ud_sq_wqe->u32_8,
 144                                      UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
 145                                      loopback);
 146
 147                         roce_set_field(ud_sq_wqe->u32_8,
 148                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
 149                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
 150                                        HNS_ROCE_WQE_OPCODE_SEND);
 151                         roce_set_field(ud_sq_wqe->u32_8,
 152                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
 153                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
 154                                        2);
 155                         roce_set_bit(ud_sq_wqe->u32_8,
 156                                 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
 157                                 1);
 158
 159                         ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
 160                                 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 161                                 (wr->send_flags & IB_SEND_SOLICITED ?
 162                                 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 163                                 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
 164                                 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
 165
 166                         roce_set_field(ud_sq_wqe->u32_16,
 167                                        UD_SEND_WQE_U32_16_DEST_QP_M,
 168                                        UD_SEND_WQE_U32_16_DEST_QP_S,
 169                                        ud_wr(wr)->remote_qpn);
 170                         roce_set_field(ud_sq_wqe->u32_16,
 171                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
 172                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
 173                                        ah->av.stat_rate);
 174
 175                         roce_set_field(ud_sq_wqe->u32_36,
 176                                        UD_SEND_WQE_U32_36_FLOW_LABEL_M,
 177                                        UD_SEND_WQE_U32_36_FLOW_LABEL_S,
 178                                        ah->av.sl_tclass_flowlabel &
 179                                        HNS_ROCE_FLOW_LABEL_MASK);
 180                         roce_set_field(ud_sq_wqe->u32_36,
 181                                       UD_SEND_WQE_U32_36_PRIORITY_M,
 182                                       UD_SEND_WQE_U32_36_PRIORITY_S,
 183                                       le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
 184                                       HNS_ROCE_SL_SHIFT);
 185                         roce_set_field(ud_sq_wqe->u32_36,
 186                                        UD_SEND_WQE_U32_36_SGID_INDEX_M,
 187                                        UD_SEND_WQE_U32_36_SGID_INDEX_S,
 188                                        hns_get_gid_index(hr_dev, qp->phy_port,
 189                                                          ah->av.gid_index));
 190
 191                         roce_set_field(ud_sq_wqe->u32_40,
 192                                        UD_SEND_WQE_U32_40_HOP_LIMIT_M,
 193                                        UD_SEND_WQE_U32_40_HOP_LIMIT_S,
 194                                        ah->av.hop_limit);
 195                         roce_set_field(ud_sq_wqe->u32_40,
 196                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
 197                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
 198                                        ah->av.sl_tclass_flowlabel >>
 199                                        HNS_ROCE_TCLASS_SHIFT);
 200
 201                         memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
 202
 203                         ud_sq_wqe->va0_l =
 204                                        cpu_to_le32((u32)wr->sg_list[0].addr);
 205                         ud_sq_wqe->va0_h =
 206                                        cpu_to_le32((wr->sg_list[0].addr) >> 32);
 207                         ud_sq_wqe->l_key0 =
 208                                        cpu_to_le32(wr->sg_list[0].lkey);
 209
 210                         ud_sq_wqe->va1_l =
 211                                        cpu_to_le32((u32)wr->sg_list[1].addr);
 212                         ud_sq_wqe->va1_h =
 213                                        cpu_to_le32((wr->sg_list[1].addr) >> 32);
 214                         ud_sq_wqe->l_key1 =
 215                                        cpu_to_le32(wr->sg_list[1].lkey);
 216                         ind++;
 217                 } else if (ibqp->qp_type == IB_QPT_RC) {
 218                         u32 tmp_len = 0;
 219
 220                         ctrl = wqe;
 221                         memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
 222                         for (i = 0; i < wr->num_sge; i++)
 223                                 tmp_len += wr->sg_list[i].length;
 224
 225                         ctrl->msg_length =
 226                           cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
 227
 228                         ctrl->sgl_pa_h = 0;
 229                         ctrl->flag = 0;
 230
 231                         switch (wr->opcode) {
 232                         case IB_WR_SEND_WITH_IMM:
 233                         case IB_WR_RDMA_WRITE_WITH_IMM:
 234                                 ctrl->imm_data = wr->ex.imm_data;
 235                                 break;
 236                         case IB_WR_SEND_WITH_INV:
 237                                 ctrl->inv_key =
 238                                         cpu_to_le32(wr->ex.invalidate_rkey);
 239                                 break;
 240                         default:
 241                                 ctrl->imm_data = 0;
 242                                 break;
 243                         }
 244
 245                         /*Ctrl field, ctrl set type: sig, solic, imm, fence */
 246                         /* SO wait for conforming application scenarios */
 247                         ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
 248                                       cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 249                                       (wr->send_flags & IB_SEND_SOLICITED ?
 250                                       cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 251                                       ((wr->opcode == IB_WR_SEND_WITH_IMM ||
 252                                       wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
 253                                       cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
 254                                       (wr->send_flags & IB_SEND_FENCE ?
 255                                       (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
 256
 257                         wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
 258
 259                         switch (wr->opcode) {
 260                         case IB_WR_RDMA_READ:
 261                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
 262                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 263                                                rdma_wr(wr)->rkey);
 264                                 break;
 265                         case IB_WR_RDMA_WRITE:
 266                         case IB_WR_RDMA_WRITE_WITH_IMM:
 267                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
 268                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 269                                               rdma_wr(wr)->rkey);
 270                                 break;
 271                         case IB_WR_SEND:
 272                         case IB_WR_SEND_WITH_INV:
 273                         case IB_WR_SEND_WITH_IMM:
 274                                 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
 275                                 break;
 276                         case IB_WR_LOCAL_INV:
 277                                 break;
 278                         case IB_WR_ATOMIC_CMP_AND_SWP:
 279                         case IB_WR_ATOMIC_FETCH_AND_ADD:
 280                         case IB_WR_LSO:
 281                         default:
 282                                 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
 283                                 break;
 284                         }
 285                         ctrl->flag |= cpu_to_le32(ps_opcode);
 286                         wqe += sizeof(struct hns_roce_wqe_raddr_seg);
 287
 288                         dseg = wqe;
 289                         if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
 290                                 if (le32_to_cpu(ctrl->msg_length) >
 291                                     hr_dev->caps.max_sq_inline) {
 292                                         ret = -EINVAL;
 293                                         *bad_wr = wr;
 294                                         dev_err(dev, "inline len(1-%d)=%d, illegal",
 295                                                 ctrl->msg_length,
 296                                                 hr_dev->caps.max_sq_inline);
 297                                         goto out;
 298                                 }
 299                                 for (i = 0; i < wr->num_sge; i++) {
 300                                         memcpy(wqe, ((void *) (uintptr_t)
 301                                                wr->sg_list[i].addr),
 302                                                wr->sg_list[i].length);
 303                                         wqe += wr->sg_list[i].length;
 304                                 }
 305                                 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
 306                         } else {
 307                                 /*sqe num is two */
 308                                 for (i = 0; i < wr->num_sge; i++)
 309                                         set_data_seg(dseg + i, wr->sg_list + i);
 310
 311                                 ctrl->flag |= cpu_to_le32(wr->num_sge <<
 312                                               HNS_ROCE_WQE_SGE_NUM_BIT);
 313                         }
 314                         ind++;
 315                 }
 316         }
 317
 318 out:
 319         /* Set DB return */
 320         if (likely(nreq)) {
 321                 qp->sq.head += nreq;
 322                 /* Memory barrier */
 323                 wmb();
 324
 325                 sq_db.u32_4 = 0;
 326                 sq_db.u32_8 = 0;
 327                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
 328                                SQ_DOORBELL_U32_4_SQ_HEAD_S,
 329                               (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
 330                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
 331                                SQ_DOORBELL_U32_4_SL_S, qp->sl);
 332                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
 333                                SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
 334                 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
 335                                SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
 336                 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
 337
 338                 doorbell[0] = le32_to_cpu(sq_db.u32_4);
 339                 doorbell[1] = le32_to_cpu(sq_db.u32_8);
 340
 341                 hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l);
 342                 qp->sq_next_wqe = ind;
 343         }
 344
 345         spin_unlock_irqrestore(&qp->sq.lock, flags);
 346
 347         return ret;
 348 }
 349
 350 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
 351                                  const struct ib_recv_wr *wr,
 352                                  const struct ib_recv_wr **bad_wr)
 353 {
 354         int ret = 0;
 355         int nreq = 0;
 356         int ind = 0;
 357         int i = 0;
 358         u32 reg_val;
 359         unsigned long flags = 0;
 360         struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
 361         struct hns_roce_wqe_data_seg *scat = NULL;
 362         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 363         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 364         struct device *dev = &hr_dev->pdev->dev;
 365         struct hns_roce_rq_db rq_db;
 366         uint32_t doorbell[2] = {0};
 367
 368         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 369         ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
 370
 371         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 372                 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
 373                         hr_qp->ibqp.recv_cq)) {
 374                         ret = -ENOMEM;
 375                         *bad_wr = wr;
 376                         goto out;
 377                 }
 378
 379                 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
 380                         dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
 381                                 wr->num_sge, hr_qp->rq.max_gs);
 382                         ret = -EINVAL;
 383                         *bad_wr = wr;
 384                         goto out;
 385                 }
 386
 387                 ctrl = get_recv_wqe(hr_qp, ind);
 388
 389                 roce_set_field(ctrl->rwqe_byte_12,
 390                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
 391                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
 392                                wr->num_sge);
 393
 394                 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
 395
 396                 for (i = 0; i < wr->num_sge; i++)
 397                         set_data_seg(scat + i, wr->sg_list + i);
 398
 399                 hr_qp->rq.wrid[ind] = wr->wr_id;
 400
 401                 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
 402         }
 403
 404 out:
 405         if (likely(nreq)) {
 406                 hr_qp->rq.head += nreq;
 407                 /* Memory barrier */
 408                 wmb();
 409
 410                 if (ibqp->qp_type == IB_QPT_GSI) {
 411                         __le32 tmp;
 412
 413                         /* SW update GSI rq header */
 414                         reg_val = roce_read(to_hr_dev(ibqp->device),
 415                                             ROCEE_QP1C_CFG3_0_REG +
 416                                             QP1C_CFGN_OFFSET * hr_qp->phy_port);
 417                         tmp = cpu_to_le32(reg_val);
 418                         roce_set_field(tmp,
 419                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
 420                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
 421                                        hr_qp->rq.head);
 422                         reg_val = le32_to_cpu(tmp);
 423                         roce_write(to_hr_dev(ibqp->device),
 424                                    ROCEE_QP1C_CFG3_0_REG +
 425                                    QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
 426                 } else {
 427                         rq_db.u32_4 = 0;
 428                         rq_db.u32_8 = 0;
 429
 430                         roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
 431                                        RQ_DOORBELL_U32_4_RQ_HEAD_S,
 432                                        hr_qp->rq.head);
 433                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
 434                                        RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
 435                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
 436                                        RQ_DOORBELL_U32_8_CMD_S, 1);
 437                         roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
 438                                      1);
 439
 440                         doorbell[0] = le32_to_cpu(rq_db.u32_4);
 441                         doorbell[1] = le32_to_cpu(rq_db.u32_8);
 442
 443                         hns_roce_write64_k((__le32 *)doorbell,
 444                                            hr_qp->rq.db_reg_l);
 445                 }
 446         }
 447         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 448
 449         return ret;
 450 }
 451
 452 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
 453                                        int sdb_mode, int odb_mode)
 454 {
 455         __le32 tmp;
 456         u32 val;
 457
 458         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 459         tmp = cpu_to_le32(val);
 460         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
 461         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
 462         val = le32_to_cpu(tmp);
 463         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 464 }
 465
 466 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
 467                                      u32 odb_mode)
 468 {
 469         __le32 tmp;
 470         u32 val;
 471
 472         /* Configure SDB/ODB extend mode */
 473         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 474         tmp = cpu_to_le32(val);
 475         roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
 476         roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
 477         val = le32_to_cpu(tmp);
 478         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 479 }
 480
 481 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
 482                              u32 sdb_alful)
 483 {
 484         __le32 tmp;
 485         u32 val;
 486
 487         /* Configure SDB */
 488         val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
 489         tmp = cpu_to_le32(val);
 490         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
 491                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
 492         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
 493                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
 494         val = le32_to_cpu(tmp);
 495         roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
 496 }
 497
 498 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
 499                              u32 odb_alful)
 500 {
 501         __le32 tmp;
 502         u32 val;
 503
 504         /* Configure ODB */
 505         val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
 506         tmp = cpu_to_le32(val);
 507         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
 508                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
 509         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
 510                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
 511         val = le32_to_cpu(tmp);
 512         roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
 513 }
 514
 515 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
 516                                  u32 ext_sdb_alful)
 517 {
 518         struct device *dev = &hr_dev->pdev->dev;
 519         struct hns_roce_v1_priv *priv;
 520         struct hns_roce_db_table *db;
 521         dma_addr_t sdb_dma_addr;
 522         __le32 tmp;
 523         u32 val;
 524
 525         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 526         db = &priv->db_table;
 527
 528         /* Configure extend SDB threshold */
 529         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
 530         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
 531
 532         /* Configure extend SDB base addr */
 533         sdb_dma_addr = db->ext_db->sdb_buf_list->map;
 534         roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
 535
 536         /* Configure extend SDB depth */
 537         val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
 538         tmp = cpu_to_le32(val);
 539         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
 540                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
 541                        db->ext_db->esdb_dep);
 542         /*
 543          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
 544          * using 4K page, and shift more 32 because of
 545          * caculating the high 32 bit value evaluated to hardware.
 546          */
 547         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
 548                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
 549         val = le32_to_cpu(tmp);
 550         roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
 551
 552         dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
 553         dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
 554                 ext_sdb_alept, ext_sdb_alful);
 555 }
 556
 557 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
 558                                  u32 ext_odb_alful)
 559 {
 560         struct device *dev = &hr_dev->pdev->dev;
 561         struct hns_roce_v1_priv *priv;
 562         struct hns_roce_db_table *db;
 563         dma_addr_t odb_dma_addr;
 564         __le32 tmp;
 565         u32 val;
 566
 567         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 568         db = &priv->db_table;
 569
 570         /* Configure extend ODB threshold */
 571         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
 572         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
 573
 574         /* Configure extend ODB base addr */
 575         odb_dma_addr = db->ext_db->odb_buf_list->map;
 576         roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
 577
 578         /* Configure extend ODB depth */
 579         val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
 580         tmp = cpu_to_le32(val);
 581         roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
 582                        ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
 583                        db->ext_db->eodb_dep);
 584         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
 585                        ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
 586                        db->ext_db->eodb_dep);
 587         val = le32_to_cpu(tmp);
 588         roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
 589
 590         dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
 591         dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
 592                 ext_odb_alept, ext_odb_alful);
 593 }
 594
 595 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
 596                                 u32 odb_ext_mod)
 597 {
 598         struct device *dev = &hr_dev->pdev->dev;
 599         struct hns_roce_v1_priv *priv;
 600         struct hns_roce_db_table *db;
 601         dma_addr_t sdb_dma_addr;
 602         dma_addr_t odb_dma_addr;
 603         int ret = 0;
 604
 605         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 606         db = &priv->db_table;
 607
 608         db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
 609         if (!db->ext_db)
 610                 return -ENOMEM;
 611
 612         if (sdb_ext_mod) {
 613                 db->ext_db->sdb_buf_list = kmalloc(
 614                                 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
 615                 if (!db->ext_db->sdb_buf_list) {
 616                         ret = -ENOMEM;
 617                         goto ext_sdb_buf_fail_out;
 618                 }
 619
 620                 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
 621                                                      HNS_ROCE_V1_EXT_SDB_SIZE,
 622                                                      &sdb_dma_addr, GFP_KERNEL);
 623                 if (!db->ext_db->sdb_buf_list->buf) {
 624                         ret = -ENOMEM;
 625                         goto alloc_sq_db_buf_fail;
 626                 }
 627                 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
 628
 629                 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
 630                 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
 631                                      HNS_ROCE_V1_EXT_SDB_ALFUL);
 632         } else
 633                 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
 634                                  HNS_ROCE_V1_SDB_ALFUL);
 635
 636         if (odb_ext_mod) {
 637                 db->ext_db->odb_buf_list = kmalloc(
 638                                 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
 639                 if (!db->ext_db->odb_buf_list) {
 640                         ret = -ENOMEM;
 641                         goto ext_odb_buf_fail_out;
 642                 }
 643
 644                 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
 645                                                      HNS_ROCE_V1_EXT_ODB_SIZE,
 646                                                      &odb_dma_addr, GFP_KERNEL);
 647                 if (!db->ext_db->odb_buf_list->buf) {
 648                         ret = -ENOMEM;
 649                         goto alloc_otr_db_buf_fail;
 650                 }
 651                 db->ext_db->odb_buf_list->map = odb_dma_addr;
 652
 653                 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
 654                 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
 655                                      HNS_ROCE_V1_EXT_ODB_ALFUL);
 656         } else
 657                 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
 658                                  HNS_ROCE_V1_ODB_ALFUL);
 659
 660         hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
 661
 662         return 0;
 663
 664 alloc_otr_db_buf_fail:
 665         kfree(db->ext_db->odb_buf_list);
 666
 667 ext_odb_buf_fail_out:
 668         if (sdb_ext_mod) {
 669                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
 670                                   db->ext_db->sdb_buf_list->buf,
 671                                   db->ext_db->sdb_buf_list->map);
 672         }
 673
 674 alloc_sq_db_buf_fail:
 675         if (sdb_ext_mod)
 676                 kfree(db->ext_db->sdb_buf_list);
 677
 678 ext_sdb_buf_fail_out:
 679         kfree(db->ext_db);
 680         return ret;
 681 }
 682
 683 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
 684                                                     struct ib_pd *pd)
 685 {
 686         struct device *dev = &hr_dev->pdev->dev;
 687         struct ib_qp_init_attr init_attr;
 688         struct ib_qp *qp;
 689
 690         memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
 691         init_attr.qp_type               = IB_QPT_RC;
 692         init_attr.sq_sig_type           = IB_SIGNAL_ALL_WR;
 693         init_attr.cap.max_recv_wr       = HNS_ROCE_MIN_WQE_NUM;
 694         init_attr.cap.max_send_wr       = HNS_ROCE_MIN_WQE_NUM;
 695
 696         qp = hns_roce_create_qp(pd, &init_attr, NULL);
 697         if (IS_ERR(qp)) {
 698                 dev_err(dev, "Create loop qp for mr free failed!");
 699                 return NULL;
 700         }
 701
 702         return to_hr_qp(qp);
 703 }
 704
 705 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 706 {
 707         struct hns_roce_caps *caps = &hr_dev->caps;
 708         struct device *dev = &hr_dev->pdev->dev;
 709         struct ib_cq_init_attr cq_init_attr;
 710         struct hns_roce_free_mr *free_mr;
 711         struct ib_qp_attr attr = { 0 };
 712         struct hns_roce_v1_priv *priv;
 713         struct hns_roce_qp *hr_qp;
 714         struct ib_device *ibdev;
 715         struct ib_cq *cq;
 716         struct ib_pd *pd;
 717         union ib_gid dgid;
 718         u64 subnet_prefix;
 719         int attr_mask = 0;
 720         int ret = -ENOMEM;
 721         int i, j;
 722         u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
 723         u8 phy_port;
 724         u8 port = 0;
 725         u8 sl;
 726
 727         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 728         free_mr = &priv->free_mr;
 729
 730         /* Reserved cq for loop qp */
 731         cq_init_attr.cqe                = HNS_ROCE_MIN_WQE_NUM * 2;
 732         cq_init_attr.comp_vector        = 0;
 733         cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL);
 734         if (IS_ERR(cq)) {
 735                 dev_err(dev, "Create cq for reserved loop qp failed!");
 736                 return -ENOMEM;
 737         }
 738         free_mr->mr_free_cq = to_hr_cq(cq);
 739         free_mr->mr_free_cq->ib_cq.device               = &hr_dev->ib_dev;
 740         free_mr->mr_free_cq->ib_cq.uobject              = NULL;
 741         free_mr->mr_free_cq->ib_cq.comp_handler         = NULL;
 742         free_mr->mr_free_cq->ib_cq.event_handler        = NULL;
 743         free_mr->mr_free_cq->ib_cq.cq_context           = NULL;
 744         atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
 745
 746         ibdev = &hr_dev->ib_dev;
 747         pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
 748         if (!pd)
 749                 goto alloc_mem_failed;
 750
 751         pd->device  = ibdev;
 752         ret = hns_roce_alloc_pd(pd, NULL);
 753         if (ret)
 754                 goto alloc_pd_failed;
 755
 756         free_mr->mr_free_pd = to_hr_pd(pd);
 757         free_mr->mr_free_pd->ibpd.device  = &hr_dev->ib_dev;
 758         free_mr->mr_free_pd->ibpd.uobject = NULL;
 759         free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
 760         atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
 761
 762         attr.qp_access_flags    = IB_ACCESS_REMOTE_WRITE;
 763         attr.pkey_index         = 0;
 764         attr.min_rnr_timer      = 0;
 765         /* Disable read ability */
 766         attr.max_dest_rd_atomic = 0;
 767         attr.max_rd_atomic      = 0;
 768         /* Use arbitrary values as rq_psn and sq_psn */
 769         attr.rq_psn             = 0x0808;
 770         attr.sq_psn             = 0x0808;
 771         attr.retry_cnt          = 7;
 772         attr.rnr_retry          = 7;
 773         attr.timeout            = 0x12;
 774         attr.path_mtu           = IB_MTU_256;
 775         attr.ah_attr.type       = RDMA_AH_ATTR_TYPE_ROCE;
 776         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
 777         rdma_ah_set_static_rate(&attr.ah_attr, 3);
 778
 779         subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 780         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 781                 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
 782                                 (i % HNS_ROCE_MAX_PORTS);
 783                 sl = i / HNS_ROCE_MAX_PORTS;
 784
 785                 for (j = 0; j < caps->num_ports; j++) {
 786                         if (hr_dev->iboe.phy_port[j] == phy_port) {
 787                                 queue_en[i] = 1;
 788                                 port = j;
 789                                 break;
 790                         }
 791                 }
 792
 793                 if (!queue_en[i])
 794                         continue;
 795
 796                 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
 797                 if (!free_mr->mr_free_qp[i]) {
 798                         dev_err(dev, "Create loop qp failed!\n");
 799                         ret = -ENOMEM;
 800                         goto create_lp_qp_failed;
 801                 }
 802                 hr_qp = free_mr->mr_free_qp[i];
 803
 804                 hr_qp->port             = port;
 805                 hr_qp->phy_port         = phy_port;
 806                 hr_qp->ibqp.qp_type     = IB_QPT_RC;
 807                 hr_qp->ibqp.device      = &hr_dev->ib_dev;
 808                 hr_qp->ibqp.uobject     = NULL;
 809                 atomic_set(&hr_qp->ibqp.usecnt, 0);
 810                 hr_qp->ibqp.pd          = pd;
 811                 hr_qp->ibqp.recv_cq     = cq;
 812                 hr_qp->ibqp.send_cq     = cq;
 813
 814                 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
 815                 rdma_ah_set_sl(&attr.ah_attr, sl);
 816                 attr.port_num           = port + 1;
 817
 818                 attr.dest_qp_num        = hr_qp->qpn;
 819                 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
 820                        hr_dev->dev_addr[port],
 821                        MAC_ADDR_OCTET_NUM);
 822
 823                 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
 824                 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
 825                 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
 826                 dgid.raw[11] = 0xff;
 827                 dgid.raw[12] = 0xfe;
 828                 dgid.raw[8] ^= 2;
 829                 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
 830
 831                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 832                                             IB_QPS_RESET, IB_QPS_INIT);
 833                 if (ret) {
 834                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 835                         goto create_lp_qp_failed;
 836                 }
 837
 838                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
 839                                             IB_QPS_INIT, IB_QPS_RTR);
 840                 if (ret) {
 841                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 842                         goto create_lp_qp_failed;
 843                 }
 844
 845                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 846                                             IB_QPS_RTR, IB_QPS_RTS);
 847                 if (ret) {
 848                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 849                         goto create_lp_qp_failed;
 850                 }
 851         }
 852
 853         return 0;
 854
 855 create_lp_qp_failed:
 856         for (i -= 1; i >= 0; i--) {
 857                 hr_qp = free_mr->mr_free_qp[i];
 858                 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
 859                         dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
 860         }
 861
 862         hns_roce_dealloc_pd(pd, NULL);
 863
 864 alloc_pd_failed:
 865         kfree(pd);
 866
 867 alloc_mem_failed:
 868         if (hns_roce_ib_destroy_cq(cq, NULL))
 869                 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
 870
 871         return ret;
 872 }
 873
 874 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
 875 {
 876         struct device *dev = &hr_dev->pdev->dev;
 877         struct hns_roce_free_mr *free_mr;
 878         struct hns_roce_v1_priv *priv;
 879         struct hns_roce_qp *hr_qp;
 880         int ret;
 881         int i;
 882
 883         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 884         free_mr = &priv->free_mr;
 885
 886         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 887                 hr_qp = free_mr->mr_free_qp[i];
 888                 if (!hr_qp)
 889                         continue;
 890
 891                 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
 892                 if (ret)
 893                         dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
 894                                 i, ret);
 895         }
 896
 897         ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
 898         if (ret)
 899                 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
 900
 901         hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
 902 }
 903
 904 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
 905 {
 906         struct device *dev = &hr_dev->pdev->dev;
 907         struct hns_roce_v1_priv *priv;
 908         struct hns_roce_db_table *db;
 909         u32 sdb_ext_mod;
 910         u32 odb_ext_mod;
 911         u32 sdb_evt_mod;
 912         u32 odb_evt_mod;
 913         int ret = 0;
 914
 915         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 916         db = &priv->db_table;
 917
 918         memset(db, 0, sizeof(*db));
 919
 920         /* Default DB mode */
 921         sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
 922         odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
 923         sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
 924         odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
 925
 926         db->sdb_ext_mod = sdb_ext_mod;
 927         db->odb_ext_mod = odb_ext_mod;
 928
 929         /* Init extend DB */
 930         ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
 931         if (ret) {
 932                 dev_err(dev, "Failed in extend DB configuration.\n");
 933                 return ret;
 934         }
 935
 936         hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
 937
 938         return 0;
 939 }
 940
 941 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
 942 {
 943         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 944         struct hns_roce_dev *hr_dev;
 945
 946         lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
 947                                   work);
 948         hr_dev = to_hr_dev(lp_qp_work->ib_dev);
 949
 950         hns_roce_v1_release_lp_qp(hr_dev);
 951
 952         if (hns_roce_v1_rsv_lp_qp(hr_dev))
 953                 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
 954
 955         if (lp_qp_work->comp_flag)
 956                 complete(lp_qp_work->comp);
 957
 958         kfree(lp_qp_work);
 959 }
 960
 961 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
 962 {
 963         struct device *dev = &hr_dev->pdev->dev;
 964         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 965         struct hns_roce_free_mr *free_mr;
 966         struct hns_roce_v1_priv *priv;
 967         struct completion comp;
 968         unsigned long end =
 969           msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
 970
 971         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 972         free_mr = &priv->free_mr;
 973
 974         lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
 975                              GFP_KERNEL);
 976         if (!lp_qp_work)
 977                 return -ENOMEM;
 978
 979         INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
 980
 981         lp_qp_work->ib_dev = &(hr_dev->ib_dev);
 982         lp_qp_work->comp = &comp;
 983         lp_qp_work->comp_flag = 1;
 984
 985         init_completion(lp_qp_work->comp);
 986
 987         queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
 988
 989         while (time_before_eq(jiffies, end)) {
 990                 if (try_wait_for_completion(&comp))
 991                         return 0;
 992                 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
 993         }
 994
 995         lp_qp_work->comp_flag = 0;
 996         if (try_wait_for_completion(&comp))
 997                 return 0;
 998
 999         dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
1000         return -ETIMEDOUT;
1001 }
1002
1003 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
1004 {
1005         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1006         struct device *dev = &hr_dev->pdev->dev;
1007         struct ib_send_wr send_wr;
1008         const struct ib_send_wr *bad_wr;
1009         int ret;
1010
1011         memset(&send_wr, 0, sizeof(send_wr));
1012         send_wr.next    = NULL;
1013         send_wr.num_sge = 0;
1014         send_wr.send_flags = 0;
1015         send_wr.sg_list = NULL;
1016         send_wr.wr_id   = (unsigned long long)&send_wr;
1017         send_wr.opcode  = IB_WR_RDMA_WRITE;
1018
1019         ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1020         if (ret) {
1021                 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1022                 return ret;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1029 {
1030         struct hns_roce_mr_free_work *mr_work;
1031         struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1032         struct hns_roce_free_mr *free_mr;
1033         struct hns_roce_cq *mr_free_cq;
1034         struct hns_roce_v1_priv *priv;
1035         struct hns_roce_dev *hr_dev;
1036         struct hns_roce_mr *hr_mr;
1037         struct hns_roce_qp *hr_qp;
1038         struct device *dev;
1039         unsigned long end =
1040                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1041         int i;
1042         int ret;
1043         int ne = 0;
1044
1045         mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1046         hr_mr = (struct hns_roce_mr *)mr_work->mr;
1047         hr_dev = to_hr_dev(mr_work->ib_dev);
1048         dev = &hr_dev->pdev->dev;
1049
1050         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1051         free_mr = &priv->free_mr;
1052         mr_free_cq = free_mr->mr_free_cq;
1053
1054         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1055                 hr_qp = free_mr->mr_free_qp[i];
1056                 if (!hr_qp)
1057                         continue;
1058                 ne++;
1059
1060                 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1061                 if (ret) {
1062                         dev_err(dev,
1063                              "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1064                              hr_qp->qpn, ret);
1065                         goto free_work;
1066                 }
1067         }
1068
1069         if (!ne) {
1070                 dev_err(dev, "Reserved loop qp is absent!\n");
1071                 goto free_work;
1072         }
1073
1074         do {
1075                 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1076                 if (ret < 0 && hr_qp) {
1077                         dev_err(dev,
1078                            "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1079                            hr_qp->qpn, ret, hr_mr->key, ne);
1080                         goto free_work;
1081                 }
1082                 ne -= ret;
1083                 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1084                              (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1085         } while (ne && time_before_eq(jiffies, end));
1086
1087         if (ne != 0)
1088                 dev_err(dev,
1089                         "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1090                         hr_mr->key, ne);
1091
1092 free_work:
1093         if (mr_work->comp_flag)
1094                 complete(mr_work->comp);
1095         kfree(mr_work);
1096 }
1097
1098 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1099                                 struct hns_roce_mr *mr, struct ib_udata *udata)
1100 {
1101         struct device *dev = &hr_dev->pdev->dev;
1102         struct hns_roce_mr_free_work *mr_work;
1103         struct hns_roce_free_mr *free_mr;
1104         struct hns_roce_v1_priv *priv;
1105         struct completion comp;
1106         unsigned long end =
1107                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1108         unsigned long start = jiffies;
1109         int npages;
1110         int ret = 0;
1111
1112         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1113         free_mr = &priv->free_mr;
1114
1115         if (mr->enabled) {
1116                 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1117                                        & (hr_dev->caps.num_mtpts - 1)))
1118                         dev_warn(dev, "HW2SW_MPT failed!\n");
1119         }
1120
1121         mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1122         if (!mr_work) {
1123                 ret = -ENOMEM;
1124                 goto free_mr;
1125         }
1126
1127         INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1128
1129         mr_work->ib_dev = &(hr_dev->ib_dev);
1130         mr_work->comp = &comp;
1131         mr_work->comp_flag = 1;
1132         mr_work->mr = (void *)mr;
1133         init_completion(mr_work->comp);
1134
1135         queue_work(free_mr->free_mr_wq, &(mr_work->work));
1136
1137         while (time_before_eq(jiffies, end)) {
1138                 if (try_wait_for_completion(&comp))
1139                         goto free_mr;
1140                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1141         }
1142
1143         mr_work->comp_flag = 0;
1144         if (try_wait_for_completion(&comp))
1145                 goto free_mr;
1146
1147         dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1148         ret = -ETIMEDOUT;
1149
1150 free_mr:
1151         dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1152                 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1153
1154         if (mr->size != ~0ULL) {
1155                 npages = ib_umem_page_count(mr->umem);
1156                 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1157                                   mr->pbl_dma_addr);
1158         }
1159
1160         hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1161                              key_to_hw_index(mr->key), 0);
1162
1163         if (mr->umem)
1164                 ib_umem_release(mr->umem);
1165
1166         kfree(mr);
1167
1168         return ret;
1169 }
1170
1171 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1172 {
1173         struct device *dev = &hr_dev->pdev->dev;
1174         struct hns_roce_v1_priv *priv;
1175         struct hns_roce_db_table *db;
1176
1177         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1178         db = &priv->db_table;
1179
1180         if (db->sdb_ext_mod) {
1181                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1182                                   db->ext_db->sdb_buf_list->buf,
1183                                   db->ext_db->sdb_buf_list->map);
1184                 kfree(db->ext_db->sdb_buf_list);
1185         }
1186
1187         if (db->odb_ext_mod) {
1188                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1189                                   db->ext_db->odb_buf_list->buf,
1190                                   db->ext_db->odb_buf_list->map);
1191                 kfree(db->ext_db->odb_buf_list);
1192         }
1193
1194         kfree(db->ext_db);
1195 }
1196
1197 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1198 {
1199         int ret;
1200         u32 val;
1201         __le32 tmp;
1202         int raq_shift = 0;
1203         dma_addr_t addr;
1204         struct hns_roce_v1_priv *priv;
1205         struct hns_roce_raq_table *raq;
1206         struct device *dev = &hr_dev->pdev->dev;
1207
1208         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1209         raq = &priv->raq_table;
1210
1211         raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1212         if (!raq->e_raq_buf)
1213                 return -ENOMEM;
1214
1215         raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1216                                                  &addr, GFP_KERNEL);
1217         if (!raq->e_raq_buf->buf) {
1218                 ret = -ENOMEM;
1219                 goto err_dma_alloc_raq;
1220         }
1221         raq->e_raq_buf->map = addr;
1222
1223         /* Configure raq extended address. 48bit 4K align*/
1224         roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1225
1226         /* Configure raq_shift */
1227         raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1228         val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1229         tmp = cpu_to_le32(val);
1230         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1231                        ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1232         /*
1233          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1234          * using 4K page, and shift more 32 because of
1235          * caculating the high 32 bit value evaluated to hardware.
1236          */
1237         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1238                        ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1239                        raq->e_raq_buf->map >> 44);
1240         val = le32_to_cpu(tmp);
1241         roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1242         dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1243
1244         /* Configure raq threshold */
1245         val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1246         tmp = cpu_to_le32(val);
1247         roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1248                        ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1249                        HNS_ROCE_V1_EXT_RAQ_WF);
1250         val = le32_to_cpu(tmp);
1251         roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1252         dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1253
1254         /* Enable extend raq */
1255         val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1256         tmp = cpu_to_le32(val);
1257         roce_set_field(tmp,
1258                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1259                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1260                        POL_TIME_INTERVAL_VAL);
1261         roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1262         roce_set_field(tmp,
1263                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1264                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1265                        2);
1266         roce_set_bit(tmp,
1267                      ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1268         val = le32_to_cpu(tmp);
1269         roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1270         dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1271
1272         /* Enable raq drop */
1273         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1274         tmp = cpu_to_le32(val);
1275         roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1276         val = le32_to_cpu(tmp);
1277         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1278         dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1279
1280         return 0;
1281
1282 err_dma_alloc_raq:
1283         kfree(raq->e_raq_buf);
1284         return ret;
1285 }
1286
1287 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1288 {
1289         struct device *dev = &hr_dev->pdev->dev;
1290         struct hns_roce_v1_priv *priv;
1291         struct hns_roce_raq_table *raq;
1292
1293         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1294         raq = &priv->raq_table;
1295
1296         dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1297                           raq->e_raq_buf->map);
1298         kfree(raq->e_raq_buf);
1299 }
1300
1301 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1302 {
1303         __le32 tmp;
1304         u32 val;
1305
1306         if (enable_flag) {
1307                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1308                  /* Open all ports */
1309                 tmp = cpu_to_le32(val);
1310                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1311                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1312                                ALL_PORT_VAL_OPEN);
1313                 val = le32_to_cpu(tmp);
1314                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1315         } else {
1316                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1317                 /* Close all ports */
1318                 tmp = cpu_to_le32(val);
1319                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1320                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1321                 val = le32_to_cpu(tmp);
1322                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1323         }
1324 }
1325
1326 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1327 {
1328         struct device *dev = &hr_dev->pdev->dev;
1329         struct hns_roce_v1_priv *priv;
1330         int ret;
1331
1332         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1333
1334         priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1335                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1336                 GFP_KERNEL);
1337         if (!priv->bt_table.qpc_buf.buf)
1338                 return -ENOMEM;
1339
1340         priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1341                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1342                 GFP_KERNEL);
1343         if (!priv->bt_table.mtpt_buf.buf) {
1344                 ret = -ENOMEM;
1345                 goto err_failed_alloc_mtpt_buf;
1346         }
1347
1348         priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1349                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1350                 GFP_KERNEL);
1351         if (!priv->bt_table.cqc_buf.buf) {
1352                 ret = -ENOMEM;
1353                 goto err_failed_alloc_cqc_buf;
1354         }
1355
1356         return 0;
1357
1358 err_failed_alloc_cqc_buf:
1359         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1360                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1361
1362 err_failed_alloc_mtpt_buf:
1363         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1364                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1365
1366         return ret;
1367 }
1368
1369 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1370 {
1371         struct device *dev = &hr_dev->pdev->dev;
1372         struct hns_roce_v1_priv *priv;
1373
1374         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1375
1376         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1377                 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1378
1379         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1380                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1381
1382         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1383                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1384 }
1385
1386 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1387 {
1388         struct device *dev = &hr_dev->pdev->dev;
1389         struct hns_roce_buf_list *tptr_buf;
1390         struct hns_roce_v1_priv *priv;
1391
1392         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1393         tptr_buf = &priv->tptr_table.tptr_buf;
1394
1395         /*
1396          * This buffer will be used for CQ's tptr(tail pointer), also
1397          * named ci(customer index). Every CQ will use 2 bytes to save
1398          * cqe ci in hip06. Hardware will read this area to get new ci
1399          * when the queue is almost full.
1400          */
1401         tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1402                                            &tptr_buf->map, GFP_KERNEL);
1403         if (!tptr_buf->buf)
1404                 return -ENOMEM;
1405
1406         hr_dev->tptr_dma_addr = tptr_buf->map;
1407         hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1408
1409         return 0;
1410 }
1411
1412 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1413 {
1414         struct device *dev = &hr_dev->pdev->dev;
1415         struct hns_roce_buf_list *tptr_buf;
1416         struct hns_roce_v1_priv *priv;
1417
1418         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1419         tptr_buf = &priv->tptr_table.tptr_buf;
1420
1421         dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1422                           tptr_buf->buf, tptr_buf->map);
1423 }
1424
1425 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1426 {
1427         struct device *dev = &hr_dev->pdev->dev;
1428         struct hns_roce_free_mr *free_mr;
1429         struct hns_roce_v1_priv *priv;
1430         int ret = 0;
1431
1432         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1433         free_mr = &priv->free_mr;
1434
1435         free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1436         if (!free_mr->free_mr_wq) {
1437                 dev_err(dev, "Create free mr workqueue failed!\n");
1438                 return -ENOMEM;
1439         }
1440
1441         ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1442         if (ret) {
1443                 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1444                 flush_workqueue(free_mr->free_mr_wq);
1445                 destroy_workqueue(free_mr->free_mr_wq);
1446         }
1447
1448         return ret;
1449 }
1450
1451 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1452 {
1453         struct hns_roce_free_mr *free_mr;
1454         struct hns_roce_v1_priv *priv;
1455
1456         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1457         free_mr = &priv->free_mr;
1458
1459         flush_workqueue(free_mr->free_mr_wq);
1460         destroy_workqueue(free_mr->free_mr_wq);
1461
1462         hns_roce_v1_release_lp_qp(hr_dev);
1463 }
1464
1465 /**
1466  * hns_roce_v1_reset - reset RoCE
1467  * @hr_dev: RoCE device struct pointer
1468  * @enable: true -- drop reset, false -- reset
1469  * return 0 - success , negative --fail
1470  */
1471 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1472 {
1473         struct device_node *dsaf_node;
1474         struct device *dev = &hr_dev->pdev->dev;
1475         struct device_node *np = dev->of_node;
1476         struct fwnode_handle *fwnode;
1477         int ret;
1478
1479         /* check if this is DT/ACPI case */
1480         if (dev_of_node(dev)) {
1481                 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1482                 if (!dsaf_node) {
1483                         dev_err(dev, "could not find dsaf-handle\n");
1484                         return -EINVAL;
1485                 }
1486                 fwnode = &dsaf_node->fwnode;
1487         } else if (is_acpi_device_node(dev->fwnode)) {
1488                 struct fwnode_reference_args args;
1489
1490                 ret = acpi_node_get_property_reference(dev->fwnode,
1491                                                        "dsaf-handle", 0, &args);
1492                 if (ret) {
1493                         dev_err(dev, "could not find dsaf-handle\n");
1494                         return ret;
1495                 }
1496                 fwnode = args.fwnode;
1497         } else {
1498                 dev_err(dev, "cannot read data from DT or ACPI\n");
1499                 return -ENXIO;
1500         }
1501
1502         ret = hns_dsaf_roce_reset(fwnode, false);
1503         if (ret)
1504                 return ret;
1505
1506         if (dereset) {
1507                 msleep(SLEEP_TIME_INTERVAL);
1508                 ret = hns_dsaf_roce_reset(fwnode, true);
1509         }
1510
1511         return ret;
1512 }
1513
1514 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1515 {
1516         int i = 0;
1517         struct hns_roce_caps *caps = &hr_dev->caps;
1518
1519         hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1520         hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1521         hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1522                                 ((u64)roce_read(hr_dev,
1523                                             ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1524         hr_dev->hw_rev          = HNS_ROCE_HW_VER1;
1525
1526         caps->num_qps           = HNS_ROCE_V1_MAX_QP_NUM;
1527         caps->max_wqes          = HNS_ROCE_V1_MAX_WQE_NUM;
1528         caps->min_wqes          = HNS_ROCE_MIN_WQE_NUM;
1529         caps->num_cqs           = HNS_ROCE_V1_MAX_CQ_NUM;
1530         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1531         caps->max_cqes          = HNS_ROCE_V1_MAX_CQE_NUM;
1532         caps->max_sq_sg         = HNS_ROCE_V1_SG_NUM;
1533         caps->max_rq_sg         = HNS_ROCE_V1_SG_NUM;
1534         caps->max_sq_inline     = HNS_ROCE_V1_INLINE_SIZE;
1535         caps->num_uars          = HNS_ROCE_V1_UAR_NUM;
1536         caps->phy_num_uars      = HNS_ROCE_V1_PHY_UAR_NUM;
1537         caps->num_aeq_vectors   = HNS_ROCE_V1_AEQE_VEC_NUM;
1538         caps->num_comp_vectors  = HNS_ROCE_V1_COMP_VEC_NUM;
1539         caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1540         caps->num_mtpts         = HNS_ROCE_V1_MAX_MTPT_NUM;
1541         caps->num_mtt_segs      = HNS_ROCE_V1_MAX_MTT_SEGS;
1542         caps->num_pds           = HNS_ROCE_V1_MAX_PD_NUM;
1543         caps->max_qp_init_rdma  = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1544         caps->max_qp_dest_rdma  = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1545         caps->max_sq_desc_sz    = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1546         caps->max_rq_desc_sz    = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1547         caps->qpc_entry_sz      = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1548         caps->irrl_entry_sz     = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1549         caps->cqc_entry_sz      = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1550         caps->mtpt_entry_sz     = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1551         caps->mtt_entry_sz      = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1552         caps->cq_entry_sz       = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1553         caps->page_size_cap     = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1554         caps->reserved_lkey     = 0;
1555         caps->reserved_pds      = 0;
1556         caps->reserved_mrws     = 1;
1557         caps->reserved_uars     = 0;
1558         caps->reserved_cqs      = 0;
1559         caps->chunk_sz          = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1560
1561         for (i = 0; i < caps->num_ports; i++)
1562                 caps->pkey_table_len[i] = 1;
1563
1564         for (i = 0; i < caps->num_ports; i++) {
1565                 /* Six ports shared 16 GID in v1 engine */
1566                 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1567                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1568                                                  caps->num_ports;
1569                 else
1570                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1571                                                  caps->num_ports + 1;
1572         }
1573
1574         caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1575         caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1576         caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1577         caps->max_mtu = IB_MTU_2048;
1578
1579         return 0;
1580 }
1581
1582 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1583 {
1584         int ret;
1585         u32 val;
1586         __le32 tmp;
1587         struct device *dev = &hr_dev->pdev->dev;
1588
1589         /* DMAE user config */
1590         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1591         tmp = cpu_to_le32(val);
1592         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1593                        ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1594         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1595                        ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1596                        1 << PAGES_SHIFT_16);
1597         val = le32_to_cpu(tmp);
1598         roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1599
1600         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1601         tmp = cpu_to_le32(val);
1602         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1603                        ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1604         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1605                        ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1606                        1 << PAGES_SHIFT_16);
1607
1608         ret = hns_roce_db_init(hr_dev);
1609         if (ret) {
1610                 dev_err(dev, "doorbell init failed!\n");
1611                 return ret;
1612         }
1613
1614         ret = hns_roce_raq_init(hr_dev);
1615         if (ret) {
1616                 dev_err(dev, "raq init failed!\n");
1617                 goto error_failed_raq_init;
1618         }
1619
1620         ret = hns_roce_bt_init(hr_dev);
1621         if (ret) {
1622                 dev_err(dev, "bt init failed!\n");
1623                 goto error_failed_bt_init;
1624         }
1625
1626         ret = hns_roce_tptr_init(hr_dev);
1627         if (ret) {
1628                 dev_err(dev, "tptr init failed!\n");
1629                 goto error_failed_tptr_init;
1630         }
1631
1632         ret = hns_roce_free_mr_init(hr_dev);
1633         if (ret) {
1634                 dev_err(dev, "free mr init failed!\n");
1635                 goto error_failed_free_mr_init;
1636         }
1637
1638         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1639
1640         return 0;
1641
1642 error_failed_free_mr_init:
1643         hns_roce_tptr_free(hr_dev);
1644
1645 error_failed_tptr_init:
1646         hns_roce_bt_free(hr_dev);
1647
1648 error_failed_bt_init:
1649         hns_roce_raq_free(hr_dev);
1650
1651 error_failed_raq_init:
1652         hns_roce_db_free(hr_dev);
1653         return ret;
1654 }
1655
1656 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1657 {
1658         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1659         hns_roce_free_mr_free(hr_dev);
1660         hns_roce_tptr_free(hr_dev);
1661         hns_roce_bt_free(hr_dev);
1662         hns_roce_raq_free(hr_dev);
1663         hns_roce_db_free(hr_dev);
1664 }
1665
1666 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1667 {
1668         u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1669
1670         return (!!(status & (1 << HCR_GO_BIT)));
1671 }
1672
1673 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1674                                  u64 out_param, u32 in_modifier, u8 op_modifier,
1675                                  u16 op, u16 token, int event)
1676 {
1677         u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1678         unsigned long end;
1679         u32 val = 0;
1680         __le32 tmp;
1681
1682         end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1683         while (hns_roce_v1_cmd_pending(hr_dev)) {
1684                 if (time_after(jiffies, end)) {
1685                         dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1686                                 (int)jiffies, (int)end);
1687                         return -EAGAIN;
1688                 }
1689                 cond_resched();
1690         }
1691
1692         tmp = cpu_to_le32(val);
1693         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1694                        op);
1695         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1696                        ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1697         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1698         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1699         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1700                        ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1701
1702         val = le32_to_cpu(tmp);
1703         writeq(in_param, hcr + 0);
1704         writeq(out_param, hcr + 2);
1705         writel(in_modifier, hcr + 4);
1706         /* Memory barrier */
1707         wmb();
1708
1709         writel(val, hcr + 5);
1710
1711         return 0;
1712 }
1713
1714 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1715                                 unsigned long timeout)
1716 {
1717         u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1718         unsigned long end = 0;
1719         u32 status = 0;
1720
1721         end = msecs_to_jiffies(timeout) + jiffies;
1722         while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1723                 cond_resched();
1724
1725         if (hns_roce_v1_cmd_pending(hr_dev)) {
1726                 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1727                 return -ETIMEDOUT;
1728         }
1729
1730         status = le32_to_cpu((__force __le32)
1731                               __raw_readl(hcr + HCR_STATUS_OFFSET));
1732         if ((status & STATUS_MASK) != 0x1) {
1733                 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1734                 return -EBUSY;
1735         }
1736
1737         return 0;
1738 }
1739
1740 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1741                                int gid_index, const union ib_gid *gid,
1742                                const struct ib_gid_attr *attr)
1743 {
1744         u32 *p = NULL;
1745         u8 gid_idx = 0;
1746
1747         gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1748
1749         p = (u32 *)&gid->raw[0];
1750         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1751                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1752
1753         p = (u32 *)&gid->raw[4];
1754         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1755                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1756
1757         p = (u32 *)&gid->raw[8];
1758         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1759                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1760
1761         p = (u32 *)&gid->raw[0xc];
1762         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1763                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1764
1765         return 0;
1766 }
1767
1768 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1769                                u8 *addr)
1770 {
1771         u32 reg_smac_l;
1772         u16 reg_smac_h;
1773         __le32 tmp;
1774         u16 *p_h;
1775         u32 *p;
1776         u32 val;
1777
1778         /*
1779          * When mac changed, loopback may fail
1780          * because of smac not equal to dmac.
1781          * We Need to release and create reserved qp again.
1782          */
1783         if (hr_dev->hw->dereg_mr) {
1784                 int ret;
1785
1786                 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1787                 if (ret && ret != -ETIMEDOUT)
1788                         return ret;
1789         }
1790
1791         p = (u32 *)(&addr[0]);
1792         reg_smac_l = *p;
1793         roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1794                        PHY_PORT_OFFSET * phy_port);
1795
1796         val = roce_read(hr_dev,
1797                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1798         tmp = cpu_to_le32(val);
1799         p_h = (u16 *)(&addr[4]);
1800         reg_smac_h  = *p_h;
1801         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1802                        ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1803         val = le32_to_cpu(tmp);
1804         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1805                    val);
1806
1807         return 0;
1808 }
1809
1810 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1811                                 enum ib_mtu mtu)
1812 {
1813         __le32 tmp;
1814         u32 val;
1815
1816         val = roce_read(hr_dev,
1817                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1818         tmp = cpu_to_le32(val);
1819         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1820                        ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1821         val = le32_to_cpu(tmp);
1822         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1823                    val);
1824 }
1825
1826 static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1827                                   unsigned long mtpt_idx)
1828 {
1829         struct hns_roce_v1_mpt_entry *mpt_entry;
1830         struct sg_dma_page_iter sg_iter;
1831         u64 *pages;
1832         int i;
1833
1834         /* MPT filled into mailbox buf */
1835         mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1836         memset(mpt_entry, 0, sizeof(*mpt_entry));
1837
1838         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1839                        MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1840         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1841                        MPT_BYTE_4_KEY_S, mr->key);
1842         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1843                        MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1844         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1845         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1846                      (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1847         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1848         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1849                        MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1850         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1851         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1852                      (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1853         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1854                      (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1855         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1856                      (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1857         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1858                      0);
1859         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1860
1861         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1862                        MPT_BYTE_12_PBL_ADDR_H_S, 0);
1863         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1864                        MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1865
1866         mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1867         mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1868         mpt_entry->length = cpu_to_le32((u32)mr->size);
1869
1870         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1871                        MPT_BYTE_28_PD_S, mr->pd);
1872         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1873                        MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1874         roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1875                        MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1876
1877         /* DMA memory register */
1878         if (mr->type == MR_TYPE_DMA)
1879                 return 0;
1880
1881         pages = (u64 *) __get_free_page(GFP_KERNEL);
1882         if (!pages)
1883                 return -ENOMEM;
1884
1885         i = 0;
1886         for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
1887                 pages[i] = ((u64)sg_page_iter_dma_address(&sg_iter)) >> 12;
1888
1889                 /* Directly record to MTPT table firstly 7 entry */
1890                 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1891                         break;
1892                 i++;
1893         }
1894
1895         /* Register user mr */
1896         for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1897                 switch (i) {
1898                 case 0:
1899                         mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1900                         roce_set_field(mpt_entry->mpt_byte_36,
1901                                 MPT_BYTE_36_PA0_H_M,
1902                                 MPT_BYTE_36_PA0_H_S,
1903                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1904                         break;
1905                 case 1:
1906                         roce_set_field(mpt_entry->mpt_byte_36,
1907                                        MPT_BYTE_36_PA1_L_M,
1908                                        MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1909                         roce_set_field(mpt_entry->mpt_byte_40,
1910                                 MPT_BYTE_40_PA1_H_M,
1911                                 MPT_BYTE_40_PA1_H_S,
1912                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1913                         break;
1914                 case 2:
1915                         roce_set_field(mpt_entry->mpt_byte_40,
1916                                        MPT_BYTE_40_PA2_L_M,
1917                                        MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1918                         roce_set_field(mpt_entry->mpt_byte_44,
1919                                 MPT_BYTE_44_PA2_H_M,
1920                                 MPT_BYTE_44_PA2_H_S,
1921                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1922                         break;
1923                 case 3:
1924                         roce_set_field(mpt_entry->mpt_byte_44,
1925                                        MPT_BYTE_44_PA3_L_M,
1926                                        MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1927                         roce_set_field(mpt_entry->mpt_byte_48,
1928                                 MPT_BYTE_48_PA3_H_M,
1929                                 MPT_BYTE_48_PA3_H_S,
1930                                 (u32)(pages[i] >> PAGES_SHIFT_8));
1931                         break;
1932                 case 4:
1933                         mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1934                         roce_set_field(mpt_entry->mpt_byte_56,
1935                                 MPT_BYTE_56_PA4_H_M,
1936                                 MPT_BYTE_56_PA4_H_S,
1937                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1938                         break;
1939                 case 5:
1940                         roce_set_field(mpt_entry->mpt_byte_56,
1941                                        MPT_BYTE_56_PA5_L_M,
1942                                        MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1943                         roce_set_field(mpt_entry->mpt_byte_60,
1944                                 MPT_BYTE_60_PA5_H_M,
1945                                 MPT_BYTE_60_PA5_H_S,
1946                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1947                         break;
1948                 case 6:
1949                         roce_set_field(mpt_entry->mpt_byte_60,
1950                                        MPT_BYTE_60_PA6_L_M,
1951                                        MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1952                         roce_set_field(mpt_entry->mpt_byte_64,
1953                                 MPT_BYTE_64_PA6_H_M,
1954                                 MPT_BYTE_64_PA6_H_S,
1955                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1956                         break;
1957                 default:
1958                         break;
1959                 }
1960         }
1961
1962         free_page((unsigned long) pages);
1963
1964         mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
1965
1966         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1967                        MPT_BYTE_12_PBL_ADDR_H_S,
1968                        ((u32)(mr->pbl_dma_addr >> 32)));
1969
1970         return 0;
1971 }
1972
1973 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1974 {
1975         return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1976                                    n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1977 }
1978
1979 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1980 {
1981         struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1982
1983         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1984         return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1985                 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
1986 }
1987
1988 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1989 {
1990         return get_sw_cqe(hr_cq, hr_cq->cons_index);
1991 }
1992
1993 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1994 {
1995         __le32 doorbell[2];
1996
1997         doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
1998         doorbell[1] = 0;
1999         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2000         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2001                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2002         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2003                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2004         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2005                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2006
2007         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2008 }
2009
2010 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2011                                    struct hns_roce_srq *srq)
2012 {
2013         struct hns_roce_cqe *cqe, *dest;
2014         u32 prod_index;
2015         int nfreed = 0;
2016         u8 owner_bit;
2017
2018         for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2019              ++prod_index) {
2020                 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2021                         break;
2022         }
2023
2024         /*
2025          * Now backwards through the CQ, removing CQ entries
2026          * that match our QP by overwriting them with next entries.
2027          */
2028         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2029                 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2030                 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2031                                      CQE_BYTE_16_LOCAL_QPN_S) &
2032                                      HNS_ROCE_CQE_QPN_MASK) == qpn) {
2033                         /* In v1 engine, not support SRQ */
2034                         ++nfreed;
2035                 } else if (nfreed) {
2036                         dest = get_cqe(hr_cq, (prod_index + nfreed) &
2037                                        hr_cq->ib_cq.cqe);
2038                         owner_bit = roce_get_bit(dest->cqe_byte_4,
2039                                                  CQE_BYTE_4_OWNER_S);
2040                         memcpy(dest, cqe, sizeof(*cqe));
2041                         roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2042                                      owner_bit);
2043                 }
2044         }
2045
2046         if (nfreed) {
2047                 hr_cq->cons_index += nfreed;
2048                 /*
2049                  * Make sure update of buffer contents is done before
2050                  * updating consumer index.
2051                  */
2052                 wmb();
2053
2054                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2055         }
2056 }
2057
2058 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2059                                  struct hns_roce_srq *srq)
2060 {
2061         spin_lock_irq(&hr_cq->lock);
2062         __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2063         spin_unlock_irq(&hr_cq->lock);
2064 }
2065
2066 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2067                                   struct hns_roce_cq *hr_cq, void *mb_buf,
2068                                   u64 *mtts, dma_addr_t dma_handle, int nent,
2069                                   u32 vector)
2070 {
2071         struct hns_roce_cq_context *cq_context = NULL;
2072         struct hns_roce_buf_list *tptr_buf;
2073         struct hns_roce_v1_priv *priv;
2074         dma_addr_t tptr_dma_addr;
2075         int offset;
2076
2077         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2078         tptr_buf = &priv->tptr_table.tptr_buf;
2079
2080         cq_context = mb_buf;
2081         memset(cq_context, 0, sizeof(*cq_context));
2082
2083         /* Get the tptr for this CQ. */
2084         offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2085         tptr_dma_addr = tptr_buf->map + offset;
2086         hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2087
2088         /* Register cq_context members */
2089         roce_set_field(cq_context->cqc_byte_4,
2090                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2091                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2092         roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2093                        CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2094
2095         cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2096
2097         roce_set_field(cq_context->cqc_byte_12,
2098                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2099                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2100                        ((u64)dma_handle >> 32));
2101         roce_set_field(cq_context->cqc_byte_12,
2102                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2103                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2104                        ilog2((unsigned int)nent));
2105         roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2106                        CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
2107
2108         cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2109
2110         roce_set_field(cq_context->cqc_byte_20,
2111                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2112                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2113         /* Dedicated hardware, directly set 0 */
2114         roce_set_field(cq_context->cqc_byte_20,
2115                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2116                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2117         /**
2118          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2119          * using 4K page, and shift more 32 because of
2120          * caculating the high 32 bit value evaluated to hardware.
2121          */
2122         roce_set_field(cq_context->cqc_byte_20,
2123                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2124                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2125                        tptr_dma_addr >> 44);
2126
2127         cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2128
2129         roce_set_field(cq_context->cqc_byte_32,
2130                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2131                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2132         roce_set_bit(cq_context->cqc_byte_32,
2133                      CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2134         roce_set_bit(cq_context->cqc_byte_32,
2135                      CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2136         roce_set_bit(cq_context->cqc_byte_32,
2137                      CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2138         roce_set_bit(cq_context->cqc_byte_32,
2139                      CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2140                      0);
2141         /* The initial value of cq's ci is 0 */
2142         roce_set_field(cq_context->cqc_byte_32,
2143                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2144                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2145 }
2146
2147 static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2148 {
2149         return -EOPNOTSUPP;
2150 }
2151
2152 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2153                                      enum ib_cq_notify_flags flags)
2154 {
2155         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2156         u32 notification_flag;
2157         __le32 doorbell[2];
2158
2159         notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2160                             IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2161         /*
2162          * flags = 0; Notification Flag = 1, next
2163          * flags = 1; Notification Flag = 0, solocited
2164          */
2165         doorbell[0] =
2166                 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2167         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2168         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2169                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2170         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2171                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2172         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2173                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2174                        hr_cq->cqn | notification_flag);
2175
2176         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2177
2178         return 0;
2179 }
2180
2181 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2182                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2183 {
2184         int qpn;
2185         int is_send;
2186         u16 wqe_ctr;
2187         u32 status;
2188         u32 opcode;
2189         struct hns_roce_cqe *cqe;
2190         struct hns_roce_qp *hr_qp;
2191         struct hns_roce_wq *wq;
2192         struct hns_roce_wqe_ctrl_seg *sq_wqe;
2193         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2194         struct device *dev = &hr_dev->pdev->dev;
2195
2196         /* Find cqe according consumer index */
2197         cqe = next_cqe_sw(hr_cq);
2198         if (!cqe)
2199                 return -EAGAIN;
2200
2201         ++hr_cq->cons_index;
2202         /* Memory barrier */
2203         rmb();
2204         /* 0->SQ, 1->RQ */
2205         is_send  = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2206
2207         /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2208         if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2209                            CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2210                 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2211                                      CQE_BYTE_20_PORT_NUM_S) +
2212                       roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2213                                      CQE_BYTE_16_LOCAL_QPN_S) *
2214                                      HNS_ROCE_MAX_PORTS;
2215         } else {
2216                 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2217                                      CQE_BYTE_16_LOCAL_QPN_S);
2218         }
2219
2220         if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2221                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2222                 if (unlikely(!hr_qp)) {
2223                         dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2224                                 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2225                         return -EINVAL;
2226                 }
2227
2228                 *cur_qp = hr_qp;
2229         }
2230
2231         wc->qp = &(*cur_qp)->ibqp;
2232         wc->vendor_err = 0;
2233
2234         status = roce_get_field(cqe->cqe_byte_4,
2235                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2236                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2237                                 HNS_ROCE_CQE_STATUS_MASK;
2238         switch (status) {
2239         case HNS_ROCE_CQE_SUCCESS:
2240                 wc->status = IB_WC_SUCCESS;
2241                 break;
2242         case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2243                 wc->status = IB_WC_LOC_LEN_ERR;
2244                 break;
2245         case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2246                 wc->status = IB_WC_LOC_QP_OP_ERR;
2247                 break;
2248         case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2249                 wc->status = IB_WC_LOC_PROT_ERR;
2250                 break;
2251         case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2252                 wc->status = IB_WC_WR_FLUSH_ERR;
2253                 break;
2254         case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2255                 wc->status = IB_WC_MW_BIND_ERR;
2256                 break;
2257         case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2258                 wc->status = IB_WC_BAD_RESP_ERR;
2259                 break;
2260         case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2261                 wc->status = IB_WC_LOC_ACCESS_ERR;
2262                 break;
2263         case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2264                 wc->status = IB_WC_REM_INV_REQ_ERR;
2265                 break;
2266         case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2267                 wc->status = IB_WC_REM_ACCESS_ERR;
2268                 break;
2269         case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2270                 wc->status = IB_WC_REM_OP_ERR;
2271                 break;
2272         case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2273                 wc->status = IB_WC_RETRY_EXC_ERR;
2274                 break;
2275         case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2276                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2277                 break;
2278         default:
2279                 wc->status = IB_WC_GENERAL_ERR;
2280                 break;
2281         }
2282
2283         /* CQE status error, directly return */
2284         if (wc->status != IB_WC_SUCCESS)
2285                 return 0;
2286
2287         if (is_send) {
2288                 /* SQ conrespond to CQE */
2289                 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2290                                                 CQE_BYTE_4_WQE_INDEX_M,
2291                                                 CQE_BYTE_4_WQE_INDEX_S)&
2292                                                 ((*cur_qp)->sq.wqe_cnt-1));
2293                 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2294                 case HNS_ROCE_WQE_OPCODE_SEND:
2295                         wc->opcode = IB_WC_SEND;
2296                         break;
2297                 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2298                         wc->opcode = IB_WC_RDMA_READ;
2299                         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2300                         break;
2301                 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2302                         wc->opcode = IB_WC_RDMA_WRITE;
2303                         break;
2304                 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2305                         wc->opcode = IB_WC_LOCAL_INV;
2306                         break;
2307                 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2308                         wc->opcode = IB_WC_SEND;
2309                         break;
2310                 default:
2311                         wc->status = IB_WC_GENERAL_ERR;
2312                         break;
2313                 }
2314                 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2315                                 IB_WC_WITH_IMM : 0);
2316
2317                 wq = &(*cur_qp)->sq;
2318                 if ((*cur_qp)->sq_signal_bits) {
2319                         /*
2320                          * If sg_signal_bit is 1,
2321                          * firstly tail pointer updated to wqe
2322                          * which current cqe correspond to
2323                          */
2324                         wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2325                                                       CQE_BYTE_4_WQE_INDEX_M,
2326                                                       CQE_BYTE_4_WQE_INDEX_S);
2327                         wq->tail += (wqe_ctr - (u16)wq->tail) &
2328                                     (wq->wqe_cnt - 1);
2329                 }
2330                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2331                 ++wq->tail;
2332         } else {
2333                 /* RQ conrespond to CQE */
2334                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2335                 opcode = roce_get_field(cqe->cqe_byte_4,
2336                                         CQE_BYTE_4_OPERATION_TYPE_M,
2337                                         CQE_BYTE_4_OPERATION_TYPE_S) &
2338                                         HNS_ROCE_CQE_OPCODE_MASK;
2339                 switch (opcode) {
2340                 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2341                         wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2342                         wc->wc_flags = IB_WC_WITH_IMM;
2343                         wc->ex.imm_data =
2344                                 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2345                         break;
2346                 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2347                         if (roce_get_bit(cqe->cqe_byte_4,
2348                                          CQE_BYTE_4_IMM_INDICATOR_S)) {
2349                                 wc->opcode = IB_WC_RECV;
2350                                 wc->wc_flags = IB_WC_WITH_IMM;
2351                                 wc->ex.imm_data = cpu_to_be32(
2352                                         le32_to_cpu(cqe->immediate_data));
2353                         } else {
2354                                 wc->opcode = IB_WC_RECV;
2355                                 wc->wc_flags = 0;
2356                         }
2357                         break;
2358                 default:
2359                         wc->status = IB_WC_GENERAL_ERR;
2360                         break;
2361                 }
2362
2363                 /* Update tail pointer, record wr_id */
2364                 wq = &(*cur_qp)->rq;
2365                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2366                 ++wq->tail;
2367                 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2368                                             CQE_BYTE_20_SL_S);
2369                 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2370                                                 CQE_BYTE_20_REMOTE_QPN_M,
2371                                                 CQE_BYTE_20_REMOTE_QPN_S);
2372                 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2373                                               CQE_BYTE_20_GRH_PRESENT_S) ?
2374                                               IB_WC_GRH : 0);
2375                 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2376                                                      CQE_BYTE_28_P_KEY_IDX_M,
2377                                                      CQE_BYTE_28_P_KEY_IDX_S);
2378         }
2379
2380         return 0;
2381 }
2382
2383 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2384 {
2385         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2386         struct hns_roce_qp *cur_qp = NULL;
2387         unsigned long flags;
2388         int npolled;
2389         int ret = 0;
2390
2391         spin_lock_irqsave(&hr_cq->lock, flags);
2392
2393         for (npolled = 0; npolled < num_entries; ++npolled) {
2394                 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2395                 if (ret)
2396                         break;
2397         }
2398
2399         if (npolled) {
2400                 *hr_cq->tptr_addr = hr_cq->cons_index &
2401                         ((hr_cq->cq_depth << 1) - 1);
2402
2403                 /* Memroy barrier */
2404                 wmb();
2405                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2406         }
2407
2408         spin_unlock_irqrestore(&hr_cq->lock, flags);
2409
2410         if (ret == 0 || ret == -EAGAIN)
2411                 return npolled;
2412         else
2413                 return ret;
2414 }
2415
2416 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2417                                  struct hns_roce_hem_table *table, int obj,
2418                                  int step_idx)
2419 {
2420         struct device *dev = &hr_dev->pdev->dev;
2421         struct hns_roce_v1_priv *priv;
2422         unsigned long end = 0, flags = 0;
2423         __le32 bt_cmd_val[2] = {0};
2424         void __iomem *bt_cmd;
2425         u64 bt_ba = 0;
2426
2427         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2428
2429         switch (table->type) {
2430         case HEM_TYPE_QPC:
2431                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2432                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2433                 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2434                 break;
2435         case HEM_TYPE_MTPT:
2436                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2437                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2438                 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2439                 break;
2440         case HEM_TYPE_CQC:
2441                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2442                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2443                 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2444                 break;
2445         case HEM_TYPE_SRQC:
2446                 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2447                 return -EINVAL;
2448         default:
2449                 return 0;
2450         }
2451         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2452                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2453         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2454         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2455
2456         spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2457
2458         bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2459
2460         end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2461         while (1) {
2462                 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2463                         if (!(time_before(jiffies, end))) {
2464                                 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2465                                 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2466                                         flags);
2467                                 return -EBUSY;
2468                         }
2469                 } else {
2470                         break;
2471                 }
2472                 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2473         }
2474
2475         bt_cmd_val[0] = (__le32)bt_ba;
2476         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2477                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2478         hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2479
2480         spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2481
2482         return 0;
2483 }
2484
2485 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2486                                  struct hns_roce_mtt *mtt,
2487                                  enum hns_roce_qp_state cur_state,
2488                                  enum hns_roce_qp_state new_state,
2489                                  struct hns_roce_qp_context *context,
2490                                  struct hns_roce_qp *hr_qp)
2491 {
2492         static const u16
2493         op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2494                 [HNS_ROCE_QP_STATE_RST] = {
2495                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2496                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2497                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2498                 },
2499                 [HNS_ROCE_QP_STATE_INIT] = {
2500                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2501                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2502                 /* Note: In v1 engine, HW doesn't support RST2INIT.
2503                  * We use RST2INIT cmd instead of INIT2INIT.
2504                  */
2505                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2506                 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2507                 },
2508                 [HNS_ROCE_QP_STATE_RTR] = {
2509                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2510                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2511                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2512                 },
2513                 [HNS_ROCE_QP_STATE_RTS] = {
2514                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2515                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2516                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2517                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2518                 },
2519                 [HNS_ROCE_QP_STATE_SQD] = {
2520                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2521                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2522                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2523                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2524                 },
2525                 [HNS_ROCE_QP_STATE_ERR] = {
2526                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2527                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2528                 }
2529         };
2530
2531         struct hns_roce_cmd_mailbox *mailbox;
2532         struct device *dev = &hr_dev->pdev->dev;
2533         int ret = 0;
2534
2535         if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2536             new_state >= HNS_ROCE_QP_NUM_STATE ||
2537             !op[cur_state][new_state]) {
2538                 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2539                         cur_state, new_state);
2540                 return -EINVAL;
2541         }
2542
2543         if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2544                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2545                                          HNS_ROCE_CMD_2RST_QP,
2546                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2547
2548         if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2549                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2550                                          HNS_ROCE_CMD_2ERR_QP,
2551                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2552
2553         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2554         if (IS_ERR(mailbox))
2555                 return PTR_ERR(mailbox);
2556
2557         memcpy(mailbox->buf, context, sizeof(*context));
2558
2559         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2560                                 op[cur_state][new_state],
2561                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
2562
2563         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2564         return ret;
2565 }
2566
2567 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2568                              int attr_mask, enum ib_qp_state cur_state,
2569                              enum ib_qp_state new_state)
2570 {
2571         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2572         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2573         struct hns_roce_sqp_context *context;
2574         struct device *dev = &hr_dev->pdev->dev;
2575         dma_addr_t dma_handle = 0;
2576         u32 __iomem *addr;
2577         int rq_pa_start;
2578         __le32 tmp;
2579         u32 reg_val;
2580         u64 *mtts;
2581
2582         context = kzalloc(sizeof(*context), GFP_KERNEL);
2583         if (!context)
2584                 return -ENOMEM;
2585
2586         /* Search QP buf's MTTs */
2587         mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2588                                    hr_qp->mtt.first_seg, &dma_handle);
2589         if (!mtts) {
2590                 dev_err(dev, "qp buf pa find failed\n");
2591                 goto out;
2592         }
2593
2594         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2595                 roce_set_field(context->qp1c_bytes_4,
2596                                QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2597                                QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2598                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2599                 roce_set_field(context->qp1c_bytes_4,
2600                                QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2601                                QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2602                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2603                 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2604                                QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2605
2606                 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2607                 roce_set_field(context->qp1c_bytes_12,
2608                                QP1C_BYTES_12_SQ_RQ_BT_H_M,
2609                                QP1C_BYTES_12_SQ_RQ_BT_H_S,
2610                                ((u32)(dma_handle >> 32)));
2611
2612                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2613                                QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2614                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2615                                QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2616                 roce_set_bit(context->qp1c_bytes_16,
2617                              QP1C_BYTES_16_SIGNALING_TYPE_S,
2618                              le32_to_cpu(hr_qp->sq_signal_bits));
2619                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2620                              1);
2621                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2622                              1);
2623                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2624                              0);
2625
2626                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2627                                QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2628                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2629                                QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2630
2631                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2632                 context->cur_rq_wqe_ba_l =
2633                                 cpu_to_le32((u32)(mtts[rq_pa_start]));
2634
2635                 roce_set_field(context->qp1c_bytes_28,
2636                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2637                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2638                                (mtts[rq_pa_start]) >> 32);
2639                 roce_set_field(context->qp1c_bytes_28,
2640                                QP1C_BYTES_28_RQ_CUR_IDX_M,
2641                                QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2642
2643                 roce_set_field(context->qp1c_bytes_32,
2644                                QP1C_BYTES_32_RX_CQ_NUM_M,
2645                                QP1C_BYTES_32_RX_CQ_NUM_S,
2646                                to_hr_cq(ibqp->recv_cq)->cqn);
2647                 roce_set_field(context->qp1c_bytes_32,
2648                                QP1C_BYTES_32_TX_CQ_NUM_M,
2649                                QP1C_BYTES_32_TX_CQ_NUM_S,
2650                                to_hr_cq(ibqp->send_cq)->cqn);
2651
2652                 context->cur_sq_wqe_ba_l  = cpu_to_le32((u32)mtts[0]);
2653
2654                 roce_set_field(context->qp1c_bytes_40,
2655                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2656                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2657                                (mtts[0]) >> 32);
2658                 roce_set_field(context->qp1c_bytes_40,
2659                                QP1C_BYTES_40_SQ_CUR_IDX_M,
2660                                QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2661
2662                 /* Copy context to QP1C register */
2663                 addr = (u32 __iomem *)(hr_dev->reg_base +
2664                                        ROCEE_QP1C_CFG0_0_REG +
2665                                        hr_qp->phy_port * sizeof(*context));
2666
2667                 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2668                 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2669                 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2670                 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2671                 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2672                 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2673                 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2674                 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2675                 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2676                 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2677         }
2678
2679         /* Modify QP1C status */
2680         reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2681                             hr_qp->phy_port * sizeof(*context));
2682         tmp = cpu_to_le32(reg_val);
2683         roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2684                        ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2685         reg_val = le32_to_cpu(tmp);
2686         roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2687                     hr_qp->phy_port * sizeof(*context), reg_val);
2688
2689         hr_qp->state = new_state;
2690         if (new_state == IB_QPS_RESET) {
2691                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2692                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2693                 if (ibqp->send_cq != ibqp->recv_cq)
2694                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2695                                              hr_qp->qpn, NULL);
2696
2697                 hr_qp->rq.head = 0;
2698                 hr_qp->rq.tail = 0;
2699                 hr_qp->sq.head = 0;
2700                 hr_qp->sq.tail = 0;
2701                 hr_qp->sq_next_wqe = 0;
2702         }
2703
2704         kfree(context);
2705         return 0;
2706
2707 out:
2708         kfree(context);
2709         return -EINVAL;
2710 }
2711
2712 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2713                             int attr_mask, enum ib_qp_state cur_state,
2714                             enum ib_qp_state new_state)
2715 {
2716         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2717         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2718         struct device *dev = &hr_dev->pdev->dev;
2719         struct hns_roce_qp_context *context;
2720         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2721         dma_addr_t dma_handle_2 = 0;
2722         dma_addr_t dma_handle = 0;
2723         __le32 doorbell[2] = {0};
2724         int rq_pa_start = 0;
2725         u64 *mtts_2 = NULL;
2726         int ret = -EINVAL;
2727         u64 *mtts = NULL;
2728         int port;
2729         u8 port_num;
2730         u8 *dmac;
2731         u8 *smac;
2732
2733         context = kzalloc(sizeof(*context), GFP_KERNEL);
2734         if (!context)
2735                 return -ENOMEM;
2736
2737         /* Search qp buf's mtts */
2738         mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2739                                    hr_qp->mtt.first_seg, &dma_handle);
2740         if (mtts == NULL) {
2741                 dev_err(dev, "qp buf pa find failed\n");
2742                 goto out;
2743         }
2744
2745         /* Search IRRL's mtts */
2746         mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2747                                      hr_qp->qpn, &dma_handle_2);
2748         if (mtts_2 == NULL) {
2749                 dev_err(dev, "qp irrl_table find failed\n");
2750                 goto out;
2751         }
2752
2753         /*
2754          * Reset to init
2755          *      Mandatory param:
2756          *      IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2757          *      Optional param: NA
2758          */
2759         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2760                 roce_set_field(context->qpc_bytes_4,
2761                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2762                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2763                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2764
2765                 roce_set_bit(context->qpc_bytes_4,
2766                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2767                 roce_set_bit(context->qpc_bytes_4,
2768                              QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2769                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2770                 roce_set_bit(context->qpc_bytes_4,
2771                              QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2772                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2773                              );
2774                 roce_set_bit(context->qpc_bytes_4,
2775                              QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2776                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2777                              );
2778                 roce_set_bit(context->qpc_bytes_4,
2779                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2780                 roce_set_field(context->qpc_bytes_4,
2781                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2782                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2783                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2784                 roce_set_field(context->qpc_bytes_4,
2785                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2786                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2787                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2788                 roce_set_field(context->qpc_bytes_4,
2789                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2790                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2791                                to_hr_pd(ibqp->pd)->pdn);
2792                 hr_qp->access_flags = attr->qp_access_flags;
2793                 roce_set_field(context->qpc_bytes_8,
2794                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2795                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2796                                to_hr_cq(ibqp->send_cq)->cqn);
2797                 roce_set_field(context->qpc_bytes_8,
2798                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2799                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2800                                to_hr_cq(ibqp->recv_cq)->cqn);
2801
2802                 if (ibqp->srq)
2803                         roce_set_field(context->qpc_bytes_12,
2804                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2805                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2806                                        to_hr_srq(ibqp->srq)->srqn);
2807
2808                 roce_set_field(context->qpc_bytes_12,
2809                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2810                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2811                                attr->pkey_index);
2812                 hr_qp->pkey_index = attr->pkey_index;
2813                 roce_set_field(context->qpc_bytes_16,
2814                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2815                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2816
2817         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2818                 roce_set_field(context->qpc_bytes_4,
2819                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2820                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2821                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2822                 roce_set_bit(context->qpc_bytes_4,
2823                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2824                 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2825                         roce_set_bit(context->qpc_bytes_4,
2826                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2827                                      !!(attr->qp_access_flags &
2828                                      IB_ACCESS_REMOTE_READ));
2829                         roce_set_bit(context->qpc_bytes_4,
2830                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2831                                      !!(attr->qp_access_flags &
2832                                      IB_ACCESS_REMOTE_WRITE));
2833                 } else {
2834                         roce_set_bit(context->qpc_bytes_4,
2835                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2836                                      !!(hr_qp->access_flags &
2837                                      IB_ACCESS_REMOTE_READ));
2838                         roce_set_bit(context->qpc_bytes_4,
2839                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2840                                      !!(hr_qp->access_flags &
2841                                      IB_ACCESS_REMOTE_WRITE));
2842                 }
2843
2844                 roce_set_bit(context->qpc_bytes_4,
2845                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2846                 roce_set_field(context->qpc_bytes_4,
2847                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2848                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2849                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2850                 roce_set_field(context->qpc_bytes_4,
2851                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2852                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2853                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2854                 roce_set_field(context->qpc_bytes_4,
2855                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2856                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2857                                to_hr_pd(ibqp->pd)->pdn);
2858
2859                 roce_set_field(context->qpc_bytes_8,
2860                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2861                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2862                                to_hr_cq(ibqp->send_cq)->cqn);
2863                 roce_set_field(context->qpc_bytes_8,
2864                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2865                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2866                                to_hr_cq(ibqp->recv_cq)->cqn);
2867
2868                 if (ibqp->srq)
2869                         roce_set_field(context->qpc_bytes_12,
2870                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2871                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2872                                        to_hr_srq(ibqp->srq)->srqn);
2873                 if (attr_mask & IB_QP_PKEY_INDEX)
2874                         roce_set_field(context->qpc_bytes_12,
2875                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2876                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2877                                        attr->pkey_index);
2878                 else
2879                         roce_set_field(context->qpc_bytes_12,
2880                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2881                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2882                                        hr_qp->pkey_index);
2883
2884                 roce_set_field(context->qpc_bytes_16,
2885                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2886                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2887         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2888                 if ((attr_mask & IB_QP_ALT_PATH) ||
2889                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2890                     (attr_mask & IB_QP_PKEY_INDEX) ||
2891                     (attr_mask & IB_QP_QKEY)) {
2892                         dev_err(dev, "INIT2RTR attr_mask error\n");
2893                         goto out;
2894                 }
2895
2896                 dmac = (u8 *)attr->ah_attr.roce.dmac;
2897
2898                 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2899                 roce_set_field(context->qpc_bytes_24,
2900                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2901                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2902                                ((u32)(dma_handle >> 32)));
2903                 roce_set_bit(context->qpc_bytes_24,
2904                              QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2905                              1);
2906                 roce_set_field(context->qpc_bytes_24,
2907                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2908                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2909                                attr->min_rnr_timer);
2910                 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2911                 roce_set_field(context->qpc_bytes_32,
2912                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2913                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2914                                ((u32)(dma_handle_2 >> 32)) &
2915                                 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2916                 roce_set_field(context->qpc_bytes_32,
2917                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2918                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2919                 roce_set_bit(context->qpc_bytes_32,
2920                              QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2921                              1);
2922                 roce_set_bit(context->qpc_bytes_32,
2923                              QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2924                              le32_to_cpu(hr_qp->sq_signal_bits));
2925
2926                 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2927                         hr_qp->port;
2928                 smac = (u8 *)hr_dev->dev_addr[port];
2929                 /* when dmac equals smac or loop_idc is 1, it should loopback */
2930                 if (ether_addr_equal_unaligned(dmac, smac) ||
2931                     hr_dev->loop_idc == 0x1)
2932                         roce_set_bit(context->qpc_bytes_32,
2933                               QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2934
2935                 roce_set_bit(context->qpc_bytes_32,
2936                              QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2937                              rdma_ah_get_ah_flags(&attr->ah_attr));
2938                 roce_set_field(context->qpc_bytes_32,
2939                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2940                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2941                                ilog2((unsigned int)attr->max_dest_rd_atomic));
2942
2943                 if (attr_mask & IB_QP_DEST_QPN)
2944                         roce_set_field(context->qpc_bytes_36,
2945                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2946                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2947                                        attr->dest_qp_num);
2948
2949                 /* Configure GID index */
2950                 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2951                 roce_set_field(context->qpc_bytes_36,
2952                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2953                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2954                                 hns_get_gid_index(hr_dev,
2955                                                   port_num - 1,
2956                                                   grh->sgid_index));
2957
2958                 memcpy(&(context->dmac_l), dmac, 4);
2959
2960                 roce_set_field(context->qpc_bytes_44,
2961                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2962                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2963                                *((u16 *)(&dmac[4])));
2964                 roce_set_field(context->qpc_bytes_44,
2965                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2966                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2967                                rdma_ah_get_static_rate(&attr->ah_attr));
2968                 roce_set_field(context->qpc_bytes_44,
2969                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2970                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2971                                grh->hop_limit);
2972
2973                 roce_set_field(context->qpc_bytes_48,
2974                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2975                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2976                                grh->flow_label);
2977                 roce_set_field(context->qpc_bytes_48,
2978                                QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2979                                QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2980                                grh->traffic_class);
2981                 roce_set_field(context->qpc_bytes_48,
2982                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
2983                                QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2984
2985                 memcpy(context->dgid, grh->dgid.raw,
2986                        sizeof(grh->dgid.raw));
2987
2988                 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2989                         roce_get_field(context->qpc_bytes_44,
2990                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2991                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2992
2993                 roce_set_field(context->qpc_bytes_68,
2994                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2995                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2996                                hr_qp->rq.head);
2997                 roce_set_field(context->qpc_bytes_68,
2998                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2999                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3000
3001                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
3002                 context->cur_rq_wqe_ba_l =
3003                                 cpu_to_le32((u32)(mtts[rq_pa_start]));
3004
3005                 roce_set_field(context->qpc_bytes_76,
3006                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3007                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3008                         mtts[rq_pa_start] >> 32);
3009                 roce_set_field(context->qpc_bytes_76,
3010                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3011                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3012
3013                 context->rx_rnr_time = 0;
3014
3015                 roce_set_field(context->qpc_bytes_84,
3016                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3017                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3018                                attr->rq_psn - 1);
3019                 roce_set_field(context->qpc_bytes_84,
3020                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3021                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3022
3023                 roce_set_field(context->qpc_bytes_88,
3024                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3025                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3026                                attr->rq_psn);
3027                 roce_set_bit(context->qpc_bytes_88,
3028                              QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3029                 roce_set_bit(context->qpc_bytes_88,
3030                              QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3031                 roce_set_field(context->qpc_bytes_88,
3032                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3033                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3034                         0);
3035                 roce_set_field(context->qpc_bytes_88,
3036                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3037                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3038                                0);
3039
3040                 context->dma_length = 0;
3041                 context->r_key = 0;
3042                 context->va_l = 0;
3043                 context->va_h = 0;
3044
3045                 roce_set_field(context->qpc_bytes_108,
3046                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3047                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3048                 roce_set_bit(context->qpc_bytes_108,
3049                              QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3050                 roce_set_bit(context->qpc_bytes_108,
3051                              QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3052
3053                 roce_set_field(context->qpc_bytes_112,
3054                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3055                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3056                 roce_set_field(context->qpc_bytes_112,
3057                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3058                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3059
3060                 /* For chip resp ack */
3061                 roce_set_field(context->qpc_bytes_156,
3062                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3063                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3064                                hr_qp->phy_port);
3065                 roce_set_field(context->qpc_bytes_156,
3066                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3067                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3068                                rdma_ah_get_sl(&attr->ah_attr));
3069                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3070         } else if (cur_state == IB_QPS_RTR &&
3071                 new_state == IB_QPS_RTS) {
3072                 /* If exist optional param, return error */
3073                 if ((attr_mask & IB_QP_ALT_PATH) ||
3074                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
3075                     (attr_mask & IB_QP_QKEY) ||
3076                     (attr_mask & IB_QP_PATH_MIG_STATE) ||
3077                     (attr_mask & IB_QP_CUR_STATE) ||
3078                     (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3079                         dev_err(dev, "RTR2RTS attr_mask error\n");
3080                         goto out;
3081                 }
3082
3083                 context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3084
3085                 roce_set_field(context->qpc_bytes_120,
3086                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3087                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3088                                (mtts[0]) >> 32);
3089
3090                 roce_set_field(context->qpc_bytes_124,
3091                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3092                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3093                 roce_set_field(context->qpc_bytes_124,
3094                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3095                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3096
3097                 roce_set_field(context->qpc_bytes_128,
3098                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3099                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3100                                attr->sq_psn);
3101                 roce_set_bit(context->qpc_bytes_128,
3102                              QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3103                 roce_set_field(context->qpc_bytes_128,
3104                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3105                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3106                              0);
3107                 roce_set_bit(context->qpc_bytes_128,
3108                              QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3109
3110                 roce_set_field(context->qpc_bytes_132,
3111                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3112                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3113                 roce_set_field(context->qpc_bytes_132,
3114                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3115                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3116
3117                 roce_set_field(context->qpc_bytes_136,
3118                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3119                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3120                                attr->sq_psn);
3121                 roce_set_field(context->qpc_bytes_136,
3122                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3123                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3124                                attr->sq_psn);
3125
3126                 roce_set_field(context->qpc_bytes_140,
3127                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3128                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3129                                (attr->sq_psn >> SQ_PSN_SHIFT));
3130                 roce_set_field(context->qpc_bytes_140,
3131                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3132                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3133                 roce_set_bit(context->qpc_bytes_140,
3134                              QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3135
3136                 roce_set_field(context->qpc_bytes_148,
3137                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3138                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3139                 roce_set_field(context->qpc_bytes_148,
3140                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3141                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3142                                attr->retry_cnt);
3143                 roce_set_field(context->qpc_bytes_148,
3144                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3145                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3146                                attr->rnr_retry);
3147                 roce_set_field(context->qpc_bytes_148,
3148                                QP_CONTEXT_QPC_BYTES_148_LSN_M,
3149                                QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3150
3151                 context->rnr_retry = 0;
3152
3153                 roce_set_field(context->qpc_bytes_156,
3154                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3155                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3156                                attr->retry_cnt);
3157                 if (attr->timeout < 0x12) {
3158                         dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3159                                  attr->timeout);
3160                         roce_set_field(context->qpc_bytes_156,
3161                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3162                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3163                                        0x12);
3164                 } else {
3165                         roce_set_field(context->qpc_bytes_156,
3166                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3167                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3168                                        attr->timeout);
3169                 }
3170                 roce_set_field(context->qpc_bytes_156,
3171                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3172                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3173                                attr->rnr_retry);
3174                 roce_set_field(context->qpc_bytes_156,
3175                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3176                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3177                                hr_qp->phy_port);
3178                 roce_set_field(context->qpc_bytes_156,
3179                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3180                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3181                                rdma_ah_get_sl(&attr->ah_attr));
3182                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3183                 roce_set_field(context->qpc_bytes_156,
3184                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3185                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3186                                ilog2((unsigned int)attr->max_rd_atomic));
3187                 roce_set_field(context->qpc_bytes_156,
3188                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3189                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3190                 context->pkt_use_len = 0;
3191
3192                 roce_set_field(context->qpc_bytes_164,
3193                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3194                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3195                 roce_set_field(context->qpc_bytes_164,
3196                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3197                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3198
3199                 roce_set_field(context->qpc_bytes_168,
3200                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3201                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3202                                attr->sq_psn);
3203                 roce_set_field(context->qpc_bytes_168,
3204                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3205                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3206                 roce_set_field(context->qpc_bytes_168,
3207                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3208                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3209                 roce_set_bit(context->qpc_bytes_168,
3210                              QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3211                 roce_set_bit(context->qpc_bytes_168,
3212                              QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3213                 roce_set_bit(context->qpc_bytes_168,
3214                              QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3215                 context->sge_use_len = 0;
3216
3217                 roce_set_field(context->qpc_bytes_176,
3218                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3219                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3220                 roce_set_field(context->qpc_bytes_176,
3221                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3222                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3223                                0);
3224                 roce_set_field(context->qpc_bytes_180,
3225                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3226                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3227                 roce_set_field(context->qpc_bytes_180,
3228                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3229                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3230
3231                 context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3232
3233                 roce_set_field(context->qpc_bytes_188,
3234                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3235                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3236                                (mtts[0]) >> 32);
3237                 roce_set_bit(context->qpc_bytes_188,
3238                              QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3239                 roce_set_field(context->qpc_bytes_188,
3240                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3241                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3242                                0);
3243         } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3244                    (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3245                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3246                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3247                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3248                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3249                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3250                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3251                 dev_err(dev, "not support this status migration\n");
3252                 goto out;
3253         }
3254
3255         /* Every status migrate must change state */
3256         roce_set_field(context->qpc_bytes_144,
3257                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3258                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3259
3260         /* SW pass context to HW */
3261         ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3262                                     to_hns_roce_state(cur_state),
3263                                     to_hns_roce_state(new_state), context,
3264                                     hr_qp);
3265         if (ret) {
3266                 dev_err(dev, "hns_roce_qp_modify failed\n");
3267                 goto out;
3268         }
3269
3270         /*
3271          * Use rst2init to instead of init2init with drv,
3272          * need to hw to flash RQ HEAD by DB again
3273          */
3274         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3275                 /* Memory barrier */
3276                 wmb();
3277
3278                 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3279                                RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3280                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3281                                RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3282                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3283                                RQ_DOORBELL_U32_8_CMD_S, 1);
3284                 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3285
3286                 if (ibqp->uobject) {
3287                         hr_qp->rq.db_reg_l = hr_dev->reg_base +
3288                                      hr_dev->odb_offset +
3289                                      DB_REG_OFFSET * hr_dev->priv_uar.index;
3290                 }
3291
3292                 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3293         }
3294
3295         hr_qp->state = new_state;
3296
3297         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3298                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3299         if (attr_mask & IB_QP_PORT) {
3300                 hr_qp->port = attr->port_num - 1;
3301                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3302         }
3303
3304         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3305                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3306                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3307                 if (ibqp->send_cq != ibqp->recv_cq)
3308                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3309                                              hr_qp->qpn, NULL);
3310
3311                 hr_qp->rq.head = 0;
3312                 hr_qp->rq.tail = 0;
3313                 hr_qp->sq.head = 0;
3314                 hr_qp->sq.tail = 0;
3315                 hr_qp->sq_next_wqe = 0;
3316         }
3317 out:
3318         kfree(context);
3319         return ret;
3320 }
3321
3322 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3323                                  const struct ib_qp_attr *attr, int attr_mask,
3324                                  enum ib_qp_state cur_state,
3325                                  enum ib_qp_state new_state)
3326 {
3327
3328         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3329                 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3330                                          new_state);
3331         else
3332                 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3333                                         new_state);
3334 }
3335
3336 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3337 {
3338         switch (state) {
3339         case HNS_ROCE_QP_STATE_RST:
3340                 return IB_QPS_RESET;
3341         case HNS_ROCE_QP_STATE_INIT:
3342                 return IB_QPS_INIT;
3343         case HNS_ROCE_QP_STATE_RTR:
3344                 return IB_QPS_RTR;
3345         case HNS_ROCE_QP_STATE_RTS:
3346                 return IB_QPS_RTS;
3347         case HNS_ROCE_QP_STATE_SQD:
3348                 return IB_QPS_SQD;
3349         case HNS_ROCE_QP_STATE_ERR:
3350                 return IB_QPS_ERR;
3351         default:
3352                 return IB_QPS_ERR;
3353         }
3354 }
3355
3356 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3357                                  struct hns_roce_qp *hr_qp,
3358                                  struct hns_roce_qp_context *hr_context)
3359 {
3360         struct hns_roce_cmd_mailbox *mailbox;
3361         int ret;
3362
3363         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3364         if (IS_ERR(mailbox))
3365                 return PTR_ERR(mailbox);
3366
3367         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3368                                 HNS_ROCE_CMD_QUERY_QP,
3369                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
3370         if (!ret)
3371                 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3372         else
3373                 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3374
3375         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3376
3377         return ret;
3378 }
3379
3380 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3381                              int qp_attr_mask,
3382                              struct ib_qp_init_attr *qp_init_attr)
3383 {
3384         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3385         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3386         struct hns_roce_sqp_context context;
3387         u32 addr;
3388
3389         mutex_lock(&hr_qp->mutex);
3390
3391         if (hr_qp->state == IB_QPS_RESET) {
3392                 qp_attr->qp_state = IB_QPS_RESET;
3393                 goto done;
3394         }
3395
3396         addr = ROCEE_QP1C_CFG0_0_REG +
3397                 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3398         context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3399         context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3400         context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3401         context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3402         context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3403         context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3404         context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3405         context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3406         context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3407         context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3408
3409         hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3410                                       QP1C_BYTES_4_QP_STATE_M,
3411                                       QP1C_BYTES_4_QP_STATE_S);
3412         qp_attr->qp_state       = hr_qp->state;
3413         qp_attr->path_mtu       = IB_MTU_256;
3414         qp_attr->path_mig_state = IB_MIG_ARMED;
3415         qp_attr->qkey           = QKEY_VAL;
3416         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3417         qp_attr->rq_psn         = 0;
3418         qp_attr->sq_psn         = 0;
3419         qp_attr->dest_qp_num    = 1;
3420         qp_attr->qp_access_flags = 6;
3421
3422         qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3423                                              QP1C_BYTES_20_PKEY_IDX_M,
3424                                              QP1C_BYTES_20_PKEY_IDX_S);
3425         qp_attr->port_num = hr_qp->port + 1;
3426         qp_attr->sq_draining = 0;
3427         qp_attr->max_rd_atomic = 0;
3428         qp_attr->max_dest_rd_atomic = 0;
3429         qp_attr->min_rnr_timer = 0;
3430         qp_attr->timeout = 0;
3431         qp_attr->retry_cnt = 0;
3432         qp_attr->rnr_retry = 0;
3433         qp_attr->alt_timeout = 0;
3434
3435 done:
3436         qp_attr->cur_qp_state = qp_attr->qp_state;
3437         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3438         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3439         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3440         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3441         qp_attr->cap.max_inline_data = 0;
3442         qp_init_attr->cap = qp_attr->cap;
3443         qp_init_attr->create_flags = 0;
3444
3445         mutex_unlock(&hr_qp->mutex);
3446
3447         return 0;
3448 }
3449
3450 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3451                             int qp_attr_mask,
3452                             struct ib_qp_init_attr *qp_init_attr)
3453 {
3454         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3455         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3456         struct device *dev = &hr_dev->pdev->dev;
3457         struct hns_roce_qp_context *context;
3458         int tmp_qp_state = 0;
3459         int ret = 0;
3460         int state;
3461
3462         context = kzalloc(sizeof(*context), GFP_KERNEL);
3463         if (!context)
3464                 return -ENOMEM;
3465
3466         memset(qp_attr, 0, sizeof(*qp_attr));
3467         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3468
3469         mutex_lock(&hr_qp->mutex);
3470
3471         if (hr_qp->state == IB_QPS_RESET) {
3472                 qp_attr->qp_state = IB_QPS_RESET;
3473                 goto done;
3474         }
3475
3476         ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3477         if (ret) {
3478                 dev_err(dev, "query qpc error\n");
3479                 ret = -EINVAL;
3480                 goto out;
3481         }
3482
3483         state = roce_get_field(context->qpc_bytes_144,
3484                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3485                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3486         tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3487         if (tmp_qp_state == -1) {
3488                 dev_err(dev, "to_ib_qp_state error\n");
3489                 ret = -EINVAL;
3490                 goto out;
3491         }
3492         hr_qp->state = (u8)tmp_qp_state;
3493         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3494         qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3495                                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3496                                                QP_CONTEXT_QPC_BYTES_48_MTU_S);
3497         qp_attr->path_mig_state = IB_MIG_ARMED;
3498         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3499         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3500                 qp_attr->qkey = QKEY_VAL;
3501
3502         qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3503                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3504                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3505         qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3506                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3507                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3508         qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3509                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3510                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3511         qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3512                         QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3513                                    ((roce_get_bit(context->qpc_bytes_4,
3514                         QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3515                                    ((roce_get_bit(context->qpc_bytes_4,
3516                         QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3517
3518         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3519             hr_qp->ibqp.qp_type == IB_QPT_UC) {
3520                 struct ib_global_route *grh =
3521                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3522
3523                 rdma_ah_set_sl(&qp_attr->ah_attr,
3524                                roce_get_field(context->qpc_bytes_156,
3525                                               QP_CONTEXT_QPC_BYTES_156_SL_M,
3526                                               QP_CONTEXT_QPC_BYTES_156_SL_S));
3527                 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3528                 grh->flow_label =
3529                         roce_get_field(context->qpc_bytes_48,
3530                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3531                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3532                 grh->sgid_index =
3533                         roce_get_field(context->qpc_bytes_36,
3534                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3535                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3536                 grh->hop_limit =
3537                         roce_get_field(context->qpc_bytes_44,
3538                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3539                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3540                 grh->traffic_class =
3541                         roce_get_field(context->qpc_bytes_48,
3542                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3543                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3544
3545                 memcpy(grh->dgid.raw, context->dgid,
3546                        sizeof(grh->dgid.raw));
3547         }
3548
3549         qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3550                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3551                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3552         qp_attr->port_num = hr_qp->port + 1;
3553         qp_attr->sq_draining = 0;
3554         qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3555                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3556                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3557         qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3558                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3559                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3560         qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3561                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3562                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3563         qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3564                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3565                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3566         qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3567                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3568                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3569         qp_attr->rnr_retry = (u8)context->rnr_retry;
3570
3571 done:
3572         qp_attr->cur_qp_state = qp_attr->qp_state;
3573         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3574         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3575
3576         if (!ibqp->uobject) {
3577                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3578                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3579         } else {
3580                 qp_attr->cap.max_send_wr = 0;
3581                 qp_attr->cap.max_send_sge = 0;
3582         }
3583
3584         qp_init_attr->cap = qp_attr->cap;
3585
3586 out:
3587         mutex_unlock(&hr_qp->mutex);
3588         kfree(context);
3589         return ret;
3590 }
3591
3592 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3593                                 int qp_attr_mask,
3594                                 struct ib_qp_init_attr *qp_init_attr)
3595 {
3596         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3597
3598         return hr_qp->doorbell_qpn <= 1 ?
3599                 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3600                 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3601 }
3602
3603 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3604 {
3605         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3606         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3607         struct hns_roce_cq *send_cq, *recv_cq;
3608         int ret;
3609
3610         ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3611         if (ret)
3612                 return ret;
3613
3614         send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3615         recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3616
3617         hns_roce_lock_cqs(send_cq, recv_cq);
3618         if (!udata) {
3619                 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3620                                        to_hr_srq(hr_qp->ibqp.srq) : NULL);
3621                 if (send_cq != recv_cq)
3622                         __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3623         }
3624         hns_roce_unlock_cqs(send_cq, recv_cq);
3625
3626         hns_roce_qp_remove(hr_dev, hr_qp);
3627         hns_roce_qp_free(hr_dev, hr_qp);
3628
3629         /* RC QP, release QPN */
3630         if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3631                 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3632
3633         hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3634
3635         if (udata)
3636                 ib_umem_release(hr_qp->umem);
3637         else {
3638                 kfree(hr_qp->sq.wrid);
3639                 kfree(hr_qp->rq.wrid);
3640
3641                 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3642         }
3643
3644         if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3645                 kfree(hr_qp);
3646         else
3647                 kfree(hr_to_hr_sqp(hr_qp));
3648         return 0;
3649 }
3650
3651 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3652 {
3653         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3654         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3655         struct device *dev = &hr_dev->pdev->dev;
3656         u32 cqe_cnt_ori;
3657         u32 cqe_cnt_cur;
3658         u32 cq_buf_size;
3659         int wait_time = 0;
3660         int ret = 0;
3661
3662         hns_roce_free_cq(hr_dev, hr_cq);
3663
3664         /*
3665          * Before freeing cq buffer, we need to ensure that the outstanding CQE
3666          * have been written by checking the CQE counter.
3667          */
3668         cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3669         while (1) {
3670                 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3671                     HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3672                         break;
3673
3674                 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3675                 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3676                         break;
3677
3678                 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3679                 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3680                         dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3681                                 hr_cq->cqn);
3682                         ret = -ETIMEDOUT;
3683                         break;
3684                 }
3685                 wait_time++;
3686         }
3687
3688         hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
3689
3690         if (ibcq->uobject)
3691                 ib_umem_release(hr_cq->umem);
3692         else {
3693                 /* Free the buff of stored cq */
3694                 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
3695                 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
3696         }
3697
3698         kfree(hr_cq);
3699
3700         return ret;
3701 }
3702
3703 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
3704 {
3705         roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3706                       (req_not << eq->log_entries), eq->doorbell);
3707 }
3708
3709 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3710                                             struct hns_roce_aeqe *aeqe, int qpn)
3711 {
3712         struct device *dev = &hr_dev->pdev->dev;
3713
3714         dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3715         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3716                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3717         case HNS_ROCE_LWQCE_QPC_ERROR:
3718                 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3719                 break;
3720         case HNS_ROCE_LWQCE_MTU_ERROR:
3721                 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3722                 break;
3723         case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3724                 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3725                 break;
3726         case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3727                 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3728                 break;
3729         case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3730                 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3731                 break;
3732         case HNS_ROCE_LWQCE_SL_ERROR:
3733                 dev_warn(dev, "QP %d, SL error.\n", qpn);
3734                 break;
3735         case HNS_ROCE_LWQCE_PORT_ERROR:
3736                 dev_warn(dev, "QP %d, port error.\n", qpn);
3737                 break;
3738         default:
3739                 break;
3740         }
3741 }
3742
3743 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3744                                                    struct hns_roce_aeqe *aeqe,
3745                                                    int qpn)
3746 {
3747         struct device *dev = &hr_dev->pdev->dev;
3748
3749         dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3750         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3751                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3752         case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3753                 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3754                 break;
3755         case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3756                 dev_warn(dev, "QP %d, length error.\n", qpn);
3757                 break;
3758         case HNS_ROCE_LAVWQE_VA_ERROR:
3759                 dev_warn(dev, "QP %d, VA error.\n", qpn);
3760                 break;
3761         case HNS_ROCE_LAVWQE_PD_ERROR:
3762                 dev_err(dev, "QP %d, PD error.\n", qpn);
3763                 break;
3764         case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3765                 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3766                 break;
3767         case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3768                 dev_warn(dev, "QP %d, key state error.\n", qpn);
3769                 break;
3770         case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3771                 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3772                 break;
3773         default:
3774                 break;
3775         }
3776 }
3777
3778 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3779                                       struct hns_roce_aeqe *aeqe,
3780                                       int event_type)
3781 {
3782         struct device *dev = &hr_dev->pdev->dev;
3783         int phy_port;
3784         int qpn;
3785
3786         qpn = roce_get_field(aeqe->event.qp_event.qp,
3787                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3788                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3789         phy_port = roce_get_field(aeqe->event.qp_event.qp,
3790                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3791                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3792         if (qpn <= 1)
3793                 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3794
3795         switch (event_type) {
3796         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3797                 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3798                          "QP %d, phy_port %d.\n", qpn, phy_port);
3799                 break;
3800         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3801                 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3802                 break;
3803         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3804                 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3805                 break;
3806         default:
3807                 break;
3808         }
3809
3810         hns_roce_qp_event(hr_dev, qpn, event_type);
3811 }
3812
3813 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3814                                       struct hns_roce_aeqe *aeqe,
3815                                       int event_type)
3816 {
3817         struct device *dev = &hr_dev->pdev->dev;
3818         u32 cqn;
3819
3820         cqn = roce_get_field(aeqe->event.cq_event.cq,
3821                           HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3822                           HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3823
3824         switch (event_type) {
3825         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3826                 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3827                 break;
3828         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3829                 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3830                 break;
3831         case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3832                 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3833                 break;
3834         default:
3835                 break;
3836         }
3837
3838         hns_roce_cq_event(hr_dev, cqn, event_type);
3839 }
3840
3841 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3842                                            struct hns_roce_aeqe *aeqe)
3843 {
3844         struct device *dev = &hr_dev->pdev->dev;
3845
3846         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3847                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3848         case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3849                 dev_warn(dev, "SDB overflow.\n");
3850                 break;
3851         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3852                 dev_warn(dev, "SDB almost overflow.\n");
3853                 break;
3854         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3855                 dev_warn(dev, "SDB almost empty.\n");
3856                 break;
3857         case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3858                 dev_warn(dev, "ODB overflow.\n");
3859                 break;
3860         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3861                 dev_warn(dev, "ODB almost overflow.\n");
3862                 break;
3863         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3864                 dev_warn(dev, "SDB almost empty.\n");
3865                 break;
3866         default:
3867                 break;
3868         }
3869 }
3870
3871 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3872 {
3873         unsigned long off = (entry & (eq->entries - 1)) *
3874                              HNS_ROCE_AEQ_ENTRY_SIZE;
3875
3876         return (struct hns_roce_aeqe *)((u8 *)
3877                 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3878                 off % HNS_ROCE_BA_SIZE);
3879 }
3880
3881 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3882 {
3883         struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3884
3885         return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3886                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3887 }
3888
3889 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3890                                struct hns_roce_eq *eq)
3891 {
3892         struct device *dev = &hr_dev->pdev->dev;
3893         struct hns_roce_aeqe *aeqe;
3894         int aeqes_found = 0;
3895         int event_type;
3896
3897         while ((aeqe = next_aeqe_sw_v1(eq))) {
3898
3899                 /* Make sure we read the AEQ entry after we have checked the
3900                  * ownership bit
3901                  */
3902                 dma_rmb();
3903
3904                 dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
3905                         roce_get_field(aeqe->asyn,
3906                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3907                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3908                 event_type = roce_get_field(aeqe->asyn,
3909                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3910                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3911                 switch (event_type) {
3912                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3913                         dev_warn(dev, "PATH MIG not supported\n");
3914                         break;
3915                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3916                         dev_warn(dev, "COMMUNICATION established\n");
3917                         break;
3918                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3919                         dev_warn(dev, "SQ DRAINED not supported\n");
3920                         break;
3921                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3922                         dev_warn(dev, "PATH MIG failed\n");
3923                         break;
3924                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3925                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3926                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3927                         hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3928                         break;
3929                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3930                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3931                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3932                         dev_warn(dev, "SRQ not support!\n");
3933                         break;
3934                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3935                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3936                 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3937                         hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3938                         break;
3939                 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3940                         dev_warn(dev, "port change.\n");
3941                         break;
3942                 case HNS_ROCE_EVENT_TYPE_MB:
3943                         hns_roce_cmd_event(hr_dev,
3944                                            le16_to_cpu(aeqe->event.cmd.token),
3945                                            aeqe->event.cmd.status,
3946                                            le64_to_cpu(aeqe->event.cmd.out_param
3947                                            ));
3948                         break;
3949                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3950                         hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3951                         break;
3952                 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
3953                         dev_warn(dev, "CEQ 0x%lx overflow.\n",
3954                         roce_get_field(aeqe->event.ce_event.ceqe,
3955                                      HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M,
3956                                      HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S));
3957                         break;
3958                 default:
3959                         dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3960                                  event_type, eq->eqn, eq->cons_index);
3961                         break;
3962                 }
3963
3964                 eq->cons_index++;
3965                 aeqes_found = 1;
3966
3967                 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
3968                         dev_warn(dev, "cons_index overflow, set back to 0.\n");
3969                         eq->cons_index = 0;
3970                 }
3971         }
3972
3973         set_eq_cons_index_v1(eq, 0);
3974
3975         return aeqes_found;
3976 }
3977
3978 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3979 {
3980         unsigned long off = (entry & (eq->entries - 1)) *
3981                              HNS_ROCE_CEQ_ENTRY_SIZE;
3982
3983         return (struct hns_roce_ceqe *)((u8 *)
3984                         (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3985                         off % HNS_ROCE_BA_SIZE);
3986 }
3987
3988 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3989 {
3990         struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3991
3992         return (!!(roce_get_bit(ceqe->comp,
3993                 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3994                 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3995 }
3996
3997 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3998                                struct hns_roce_eq *eq)
3999 {
4000         struct hns_roce_ceqe *ceqe;
4001         int ceqes_found = 0;
4002         u32 cqn;
4003
4004         while ((ceqe = next_ceqe_sw_v1(eq))) {
4005
4006                 /* Make sure we read CEQ entry after we have checked the
4007                  * ownership bit
4008                  */
4009                 dma_rmb();
4010
4011                 cqn = roce_get_field(ceqe->comp,
4012                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
4013                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
4014                 hns_roce_cq_completion(hr_dev, cqn);
4015
4016                 ++eq->cons_index;
4017                 ceqes_found = 1;
4018
4019                 if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
4020                         dev_warn(&eq->hr_dev->pdev->dev,
4021                                 "cons_index overflow, set back to 0.\n");
4022                         eq->cons_index = 0;
4023                 }
4024         }
4025
4026         set_eq_cons_index_v1(eq, 0);
4027
4028         return ceqes_found;
4029 }
4030
4031 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
4032 {
4033         struct hns_roce_eq  *eq  = eq_ptr;
4034         struct hns_roce_dev *hr_dev = eq->hr_dev;
4035         int int_work = 0;
4036
4037         if (eq->type_flag == HNS_ROCE_CEQ)
4038                 /* CEQ irq routine, CEQ is pulse irq, not clear */
4039                 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4040         else
4041                 /* AEQ irq routine, AEQ is pulse irq, not clear */
4042                 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4043
4044         return IRQ_RETVAL(int_work);
4045 }
4046
4047 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4048 {
4049         struct hns_roce_dev *hr_dev = dev_id;
4050         struct device *dev = &hr_dev->pdev->dev;
4051         int int_work = 0;
4052         u32 caepaemask_val;
4053         u32 cealmovf_val;
4054         u32 caepaest_val;
4055         u32 aeshift_val;
4056         u32 ceshift_val;
4057         u32 cemask_val;
4058         __le32 tmp;
4059         int i;
4060
4061         /*
4062          * Abnormal interrupt:
4063          * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4064          * interrupt, mask irq, clear irq, cancel mask operation
4065          */
4066         aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4067         tmp = cpu_to_le32(aeshift_val);
4068
4069         /* AEQE overflow */
4070         if (roce_get_bit(tmp,
4071                 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4072                 dev_warn(dev, "AEQ overflow!\n");
4073
4074                 /* Set mask */
4075                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4076                 tmp = cpu_to_le32(caepaemask_val);
4077                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4078                              HNS_ROCE_INT_MASK_ENABLE);
4079                 caepaemask_val = le32_to_cpu(tmp);
4080                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4081
4082                 /* Clear int state(INT_WC : write 1 clear) */
4083                 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4084                 tmp = cpu_to_le32(caepaest_val);
4085                 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4086                 caepaest_val = le32_to_cpu(tmp);
4087                 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4088
4089                 /* Clear mask */
4090                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4091                 tmp = cpu_to_le32(caepaemask_val);
4092                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4093                              HNS_ROCE_INT_MASK_DISABLE);
4094                 caepaemask_val = le32_to_cpu(tmp);
4095                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4096         }
4097
4098         /* CEQ almost overflow */
4099         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4100                 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4101                                         i * CEQ_REG_OFFSET);
4102                 tmp = cpu_to_le32(ceshift_val);
4103
4104                 if (roce_get_bit(tmp,
4105                         ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4106                         dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4107                         int_work++;
4108
4109                         /* Set mask */
4110                         cemask_val = roce_read(hr_dev,
4111                                                ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4112                                                i * CEQ_REG_OFFSET);
4113                         tmp = cpu_to_le32(cemask_val);
4114                         roce_set_bit(tmp,
4115                                 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4116                                 HNS_ROCE_INT_MASK_ENABLE);
4117                         cemask_val = le32_to_cpu(tmp);
4118                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4119                                    i * CEQ_REG_OFFSET, cemask_val);
4120
4121                         /* Clear int state(INT_WC : write 1 clear) */
4122                         cealmovf_val = roce_read(hr_dev,
4123                                        ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4124                                        i * CEQ_REG_OFFSET);
4125                         tmp = cpu_to_le32(cealmovf_val);
4126                         roce_set_bit(tmp,
4127                                      ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4128                                      1);
4129                         cealmovf_val = le32_to_cpu(tmp);
4130                         roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4131                                    i * CEQ_REG_OFFSET, cealmovf_val);
4132
4133                         /* Clear mask */
4134                         cemask_val = roce_read(hr_dev,
4135                                      ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4136                                      i * CEQ_REG_OFFSET);
4137                         tmp = cpu_to_le32(cemask_val);
4138                         roce_set_bit(tmp,
4139                                ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4140                                HNS_ROCE_INT_MASK_DISABLE);
4141                         cemask_val = le32_to_cpu(tmp);
4142                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4143                                    i * CEQ_REG_OFFSET, cemask_val);
4144                 }
4145         }
4146
4147         /* ECC multi-bit error alarm */
4148         dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4149                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4150                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4151                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4152
4153         dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4154                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4155                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4156                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4157
4158         return IRQ_RETVAL(int_work);
4159 }
4160
4161 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4162 {
4163         u32 aemask_val;
4164         int masken = 0;
4165         __le32 tmp;
4166         int i;
4167
4168         /* AEQ INT */
4169         aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4170         tmp = cpu_to_le32(aemask_val);
4171         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4172                      masken);
4173         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4174         aemask_val = le32_to_cpu(tmp);
4175         roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4176
4177         /* CEQ INT */
4178         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4179                 /* IRQ mask */
4180                 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4181                            i * CEQ_REG_OFFSET, masken);
4182         }
4183 }
4184
4185 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4186                                 struct hns_roce_eq *eq)
4187 {
4188         int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4189                       HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4190         int i;
4191
4192         if (!eq->buf_list)
4193                 return;
4194
4195         for (i = 0; i < npages; ++i)
4196                 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4197                                   eq->buf_list[i].buf, eq->buf_list[i].map);
4198
4199         kfree(eq->buf_list);
4200 }
4201
4202 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4203                                   int enable_flag)
4204 {
4205         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4206         __le32 tmp;
4207         u32 val;
4208
4209         val = readl(eqc);
4210         tmp = cpu_to_le32(val);
4211
4212         if (enable_flag)
4213                 roce_set_field(tmp,
4214                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4215                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4216                                HNS_ROCE_EQ_STAT_VALID);
4217         else
4218                 roce_set_field(tmp,
4219                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4220                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4221                                HNS_ROCE_EQ_STAT_INVALID);
4222
4223         val = le32_to_cpu(tmp);
4224         writel(val, eqc);
4225 }
4226
4227 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4228                                  struct hns_roce_eq *eq)
4229 {
4230         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4231         struct device *dev = &hr_dev->pdev->dev;
4232         dma_addr_t tmp_dma_addr;
4233         u32 eqconsindx_val = 0;
4234         u32 eqcuridx_val = 0;
4235         u32 eqshift_val = 0;
4236         __le32 tmp2 = 0;
4237         __le32 tmp1 = 0;
4238         __le32 tmp = 0;
4239         int num_bas;
4240         int ret;
4241         int i;
4242
4243         num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4244                    HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4245
4246         if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4247                 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4248                         (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4249                         num_bas);
4250                 return -EINVAL;
4251         }
4252
4253         eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4254         if (!eq->buf_list)
4255                 return -ENOMEM;
4256
4257         for (i = 0; i < num_bas; ++i) {
4258                 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4259                                                          &tmp_dma_addr,
4260                                                          GFP_KERNEL);
4261                 if (!eq->buf_list[i].buf) {
4262                         ret = -ENOMEM;
4263                         goto err_out_free_pages;
4264                 }
4265
4266                 eq->buf_list[i].map = tmp_dma_addr;
4267                 memset(eq->buf_list[i].buf, 0, HNS_ROCE_BA_SIZE);
4268         }
4269         eq->cons_index = 0;
4270         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4271                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4272                        HNS_ROCE_EQ_STAT_INVALID);
4273         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4274                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4275                        eq->log_entries);
4276         eqshift_val = le32_to_cpu(tmp);
4277         writel(eqshift_val, eqc);
4278
4279         /* Configure eq extended address 12~44bit */
4280         writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4281
4282         /*
4283          * Configure eq extended address 45~49 bit.
4284          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4285          * using 4K page, and shift more 32 because of
4286          * caculating the high 32 bit value evaluated to hardware.
4287          */
4288         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4289                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4290                        eq->buf_list[0].map >> 44);
4291         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4292                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4293         eqcuridx_val = le32_to_cpu(tmp1);
4294         writel(eqcuridx_val, eqc + 8);
4295
4296         /* Configure eq consumer index */
4297         roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4298                        ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4299         eqconsindx_val = le32_to_cpu(tmp2);
4300         writel(eqconsindx_val, eqc + 0xc);
4301
4302         return 0;
4303
4304 err_out_free_pages:
4305         for (i -= 1; i >= 0; i--)
4306                 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4307                                   eq->buf_list[i].map);
4308
4309         kfree(eq->buf_list);
4310         return ret;
4311 }
4312
4313 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4314 {
4315         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4316         struct device *dev = &hr_dev->pdev->dev;
4317         struct hns_roce_eq *eq;
4318         int irq_num;
4319         int eq_num;
4320         int ret;
4321         int i, j;
4322
4323         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4324         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4325
4326         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4327         if (!eq_table->eq)
4328                 return -ENOMEM;
4329
4330         eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4331                                      GFP_KERNEL);
4332         if (!eq_table->eqc_base) {
4333                 ret = -ENOMEM;
4334                 goto err_eqc_base_alloc_fail;
4335         }
4336
4337         for (i = 0; i < eq_num; i++) {
4338                 eq = &eq_table->eq[i];
4339                 eq->hr_dev = hr_dev;
4340                 eq->eqn = i;
4341                 eq->irq = hr_dev->irq[i];
4342                 eq->log_page_size = PAGE_SHIFT;
4343
4344                 if (i < hr_dev->caps.num_comp_vectors) {
4345                         /* CEQ */
4346                         eq_table->eqc_base[i] = hr_dev->reg_base +
4347                                                 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4348                                                 CEQ_REG_OFFSET * i;
4349                         eq->type_flag = HNS_ROCE_CEQ;
4350                         eq->doorbell = hr_dev->reg_base +
4351                                        ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4352                                        CEQ_REG_OFFSET * i;
4353                         eq->entries = hr_dev->caps.ceqe_depth;
4354                         eq->log_entries = ilog2(eq->entries);
4355                         eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
4356                 } else {
4357                         /* AEQ */
4358                         eq_table->eqc_base[i] = hr_dev->reg_base +
4359                                                 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4360                         eq->type_flag = HNS_ROCE_AEQ;
4361                         eq->doorbell = hr_dev->reg_base +
4362                                        ROCEE_CAEP_AEQE_CONS_IDX_REG;
4363                         eq->entries = hr_dev->caps.aeqe_depth;
4364                         eq->log_entries = ilog2(eq->entries);
4365                         eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
4366                 }
4367         }
4368
4369         /* Disable irq */
4370         hns_roce_v1_int_mask_enable(hr_dev);
4371
4372         /* Configure ce int interval */
4373         roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4374                    HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4375
4376         /* Configure ce int burst num */
4377         roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4378                    HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4379
4380         for (i = 0; i < eq_num; i++) {
4381                 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4382                 if (ret) {
4383                         dev_err(dev, "eq create failed\n");
4384                         goto err_create_eq_fail;
4385                 }
4386         }
4387
4388         for (j = 0; j < irq_num; j++) {
4389                 if (j < eq_num)
4390                         ret = request_irq(hr_dev->irq[j],
4391                                           hns_roce_v1_msix_interrupt_eq, 0,
4392                                           hr_dev->irq_names[j],
4393                                           &eq_table->eq[j]);
4394                 else
4395                         ret = request_irq(hr_dev->irq[j],
4396                                           hns_roce_v1_msix_interrupt_abn, 0,
4397                                           hr_dev->irq_names[j], hr_dev);
4398
4399                 if (ret) {
4400                         dev_err(dev, "request irq error!\n");
4401                         goto err_request_irq_fail;
4402                 }
4403         }
4404
4405         for (i = 0; i < eq_num; i++)
4406                 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4407
4408         return 0;
4409
4410 err_request_irq_fail:
4411         for (j -= 1; j >= 0; j--)
4412                 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4413
4414 err_create_eq_fail:
4415         for (i -= 1; i >= 0; i--)
4416                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4417
4418         kfree(eq_table->eqc_base);
4419
4420 err_eqc_base_alloc_fail:
4421         kfree(eq_table->eq);
4422
4423         return ret;
4424 }
4425
4426 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4427 {
4428         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4429         int irq_num;
4430         int eq_num;
4431         int i;
4432
4433         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4434         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4435         for (i = 0; i < eq_num; i++) {
4436                 /* Disable EQ */
4437                 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4438
4439                 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4440
4441                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4442         }
4443         for (i = eq_num; i < irq_num; i++)
4444                 free_irq(hr_dev->irq[i], hr_dev);
4445
4446         kfree(eq_table->eqc_base);
4447         kfree(eq_table->eq);
4448 }
4449
4450 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4451         .destroy_qp = hns_roce_v1_destroy_qp,
4452         .modify_cq = hns_roce_v1_modify_cq,
4453         .poll_cq = hns_roce_v1_poll_cq,
4454         .post_recv = hns_roce_v1_post_recv,
4455         .post_send = hns_roce_v1_post_send,
4456         .query_qp = hns_roce_v1_query_qp,
4457         .req_notify_cq = hns_roce_v1_req_notify_cq,
4458 };
4459
4460 static const struct hns_roce_hw hns_roce_hw_v1 = {
4461         .reset = hns_roce_v1_reset,
4462         .hw_profile = hns_roce_v1_profile,
4463         .hw_init = hns_roce_v1_init,
4464         .hw_exit = hns_roce_v1_exit,
4465         .post_mbox = hns_roce_v1_post_mbox,
4466         .chk_mbox = hns_roce_v1_chk_mbox,
4467         .set_gid = hns_roce_v1_set_gid,
4468         .set_mac = hns_roce_v1_set_mac,
4469         .set_mtu = hns_roce_v1_set_mtu,
4470         .write_mtpt = hns_roce_v1_write_mtpt,
4471         .write_cqc = hns_roce_v1_write_cqc,
4472         .modify_cq = hns_roce_v1_modify_cq,
4473         .clear_hem = hns_roce_v1_clear_hem,
4474         .modify_qp = hns_roce_v1_modify_qp,
4475         .query_qp = hns_roce_v1_query_qp,
4476         .destroy_qp = hns_roce_v1_destroy_qp,
4477         .post_send = hns_roce_v1_post_send,
4478         .post_recv = hns_roce_v1_post_recv,
4479         .req_notify_cq = hns_roce_v1_req_notify_cq,
4480         .poll_cq = hns_roce_v1_poll_cq,
4481         .dereg_mr = hns_roce_v1_dereg_mr,
4482         .destroy_cq = hns_roce_v1_destroy_cq,
4483         .init_eq = hns_roce_v1_init_eq_table,
4484         .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4485         .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4486 };
4487
4488 static const struct of_device_id hns_roce_of_match[] = {
4489         { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4490         {},
4491 };
4492 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4493
4494 static const struct acpi_device_id hns_roce_acpi_match[] = {
4495         { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4496         {},
4497 };
4498 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4499
4500 static int hns_roce_node_match(struct device *dev, void *fwnode)
4501 {
4502         return dev->fwnode == fwnode;
4503 }
4504
4505 static struct
4506 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4507 {
4508         struct device *dev;
4509
4510         /* get the 'device' corresponding to the matching 'fwnode' */
4511         dev = bus_find_device(&platform_bus_type, NULL,
4512                               fwnode, hns_roce_node_match);
4513         /* get the platform device */
4514         return dev ? to_platform_device(dev) : NULL;
4515 }
4516
4517 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4518 {
4519         struct device *dev = &hr_dev->pdev->dev;
4520         struct platform_device *pdev = NULL;
4521         struct net_device *netdev = NULL;
4522         struct device_node *net_node;
4523         struct resource *res;
4524         int port_cnt = 0;
4525         u8 phy_port;
4526         int ret;
4527         int i;
4528
4529         /* check if we are compatible with the underlying SoC */
4530         if (dev_of_node(dev)) {
4531                 const struct of_device_id *of_id;
4532
4533                 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4534                 if (!of_id) {
4535                         dev_err(dev, "device is not compatible!\n");
4536                         return -ENXIO;
4537                 }
4538                 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4539                 if (!hr_dev->hw) {
4540                         dev_err(dev, "couldn't get H/W specific DT data!\n");
4541                         return -ENXIO;
4542                 }
4543         } else if (is_acpi_device_node(dev->fwnode)) {
4544                 const struct acpi_device_id *acpi_id;
4545
4546                 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4547                 if (!acpi_id) {
4548                         dev_err(dev, "device is not compatible!\n");
4549                         return -ENXIO;
4550                 }
4551                 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4552                 if (!hr_dev->hw) {
4553                         dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4554                         return -ENXIO;
4555                 }
4556         } else {
4557                 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4558                 return -ENXIO;
4559         }
4560
4561         /* get the mapped register base address */
4562         res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4563         hr_dev->reg_base = devm_ioremap_resource(dev, res);
4564         if (IS_ERR(hr_dev->reg_base))
4565                 return PTR_ERR(hr_dev->reg_base);
4566
4567         /* read the node_guid of IB device from the DT or ACPI */
4568         ret = device_property_read_u8_array(dev, "node-guid",
4569                                             (u8 *)&hr_dev->ib_dev.node_guid,
4570                                             GUID_LEN);
4571         if (ret) {
4572                 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4573                 return ret;
4574         }
4575
4576         /* get the RoCE associated ethernet ports or netdevices */
4577         for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4578                 if (dev_of_node(dev)) {
4579                         net_node = of_parse_phandle(dev->of_node, "eth-handle",
4580                                                     i);
4581                         if (!net_node)
4582                                 continue;
4583                         pdev = of_find_device_by_node(net_node);
4584                 } else if (is_acpi_device_node(dev->fwnode)) {
4585                         struct fwnode_reference_args args;
4586
4587                         ret = acpi_node_get_property_reference(dev->fwnode,
4588                                                                "eth-handle",
4589                                                                i, &args);
4590                         if (ret)
4591                                 continue;
4592                         pdev = hns_roce_find_pdev(args.fwnode);
4593                 } else {
4594                         dev_err(dev, "cannot read data from DT or ACPI\n");
4595                         return -ENXIO;
4596                 }
4597
4598                 if (pdev) {
4599                         netdev = platform_get_drvdata(pdev);
4600                         phy_port = (u8)i;
4601                         if (netdev) {
4602                                 hr_dev->iboe.netdevs[port_cnt] = netdev;
4603                                 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4604                         } else {
4605                                 dev_err(dev, "no netdev found with pdev %s\n",
4606                                         pdev->name);
4607                                 return -ENODEV;
4608                         }
4609                         port_cnt++;
4610                 }
4611         }
4612
4613         if (port_cnt == 0) {
4614                 dev_err(dev, "unable to get eth-handle for available ports!\n");
4615                 return -EINVAL;
4616         }
4617
4618         hr_dev->caps.num_ports = port_cnt;
4619
4620         /* cmd issue mode: 0 is poll, 1 is event */
4621         hr_dev->cmd_mod = 1;
4622         hr_dev->loop_idc = 0;
4623         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4624         hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4625
4626         /* read the interrupt names from the DT or ACPI */
4627         ret = device_property_read_string_array(dev, "interrupt-names",
4628                                                 hr_dev->irq_names,
4629                                                 HNS_ROCE_V1_MAX_IRQ_NUM);
4630         if (ret < 0) {
4631                 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4632                 return ret;
4633         }
4634
4635         /* fetch the interrupt numbers */
4636         for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4637                 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4638                 if (hr_dev->irq[i] <= 0) {
4639                         dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4640                         return -EINVAL;
4641                 }
4642         }
4643
4644         return 0;
4645 }
4646
4647 /**
4648  * hns_roce_probe - RoCE driver entrance
4649  * @pdev: pointer to platform device
4650  * Return : int
4651  *
4652  */
4653 static int hns_roce_probe(struct platform_device *pdev)
4654 {
4655         int ret;
4656         struct hns_roce_dev *hr_dev;
4657         struct device *dev = &pdev->dev;
4658
4659         hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4660         if (!hr_dev)
4661                 return -ENOMEM;
4662
4663         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4664         if (!hr_dev->priv) {
4665                 ret = -ENOMEM;
4666                 goto error_failed_kzalloc;
4667         }
4668
4669         hr_dev->pdev = pdev;
4670         hr_dev->dev = dev;
4671         platform_set_drvdata(pdev, hr_dev);
4672
4673         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4674             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4675                 dev_err(dev, "Not usable DMA addressing mode\n");
4676                 ret = -EIO;
4677                 goto error_failed_get_cfg;
4678         }
4679
4680         ret = hns_roce_get_cfg(hr_dev);
4681         if (ret) {
4682                 dev_err(dev, "Get Configuration failed!\n");
4683                 goto error_failed_get_cfg;
4684         }
4685
4686         ret = hns_roce_init(hr_dev);
4687         if (ret) {
4688                 dev_err(dev, "RoCE engine init failed!\n");
4689                 goto error_failed_get_cfg;
4690         }
4691
4692         return 0;
4693
4694 error_failed_get_cfg:
4695         kfree(hr_dev->priv);
4696
4697 error_failed_kzalloc:
4698         ib_dealloc_device(&hr_dev->ib_dev);
4699
4700         return ret;
4701 }
4702
4703 /**
4704  * hns_roce_remove - remove RoCE device
4705  * @pdev: pointer to platform device
4706  */
4707 static int hns_roce_remove(struct platform_device *pdev)
4708 {
4709         struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4710
4711         hns_roce_exit(hr_dev);
4712         kfree(hr_dev->priv);
4713         ib_dealloc_device(&hr_dev->ib_dev);
4714
4715         return 0;
4716 }
4717
4718 static struct platform_driver hns_roce_driver = {
4719         .probe = hns_roce_probe,
4720         .remove = hns_roce_remove,
4721         .driver = {
4722                 .name = DRV_NAME,
4723                 .of_match_table = hns_roce_of_match,
4724                 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4725         },
4726 };
4727
4728 module_platform_driver(hns_roce_driver);
4729
4730 MODULE_LICENSE("Dual BSD/GPL");
4731 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4732 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4733 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4734 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");