2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/platform_device.h>
35 #include "hns_roce_device.h"
36 #include "hns_roce_hem.h"
37 #include "hns_roce_common.h"
39 #define HEM_INDEX_BUF BIT(0)
40 #define HEM_INDEX_L0 BIT(1)
41 #define HEM_INDEX_L1 BIT(2)
42 struct hns_roce_hem_index {
46 u32 inited; /* indicate which index is available */
49 bool hns_roce_check_whether_mhop(struct hns_roce_dev *hr_dev, u32 type)
55 hop_num = hr_dev->caps.qpc_hop_num;
58 hop_num = hr_dev->caps.mpt_hop_num;
61 hop_num = hr_dev->caps.cqc_hop_num;
64 hop_num = hr_dev->caps.srqc_hop_num;
67 hop_num = hr_dev->caps.sccc_hop_num;
69 case HEM_TYPE_QPC_TIMER:
70 hop_num = hr_dev->caps.qpc_timer_hop_num;
72 case HEM_TYPE_CQC_TIMER:
73 hop_num = hr_dev->caps.cqc_timer_hop_num;
76 hop_num = hr_dev->caps.gmv_hop_num;
82 return hop_num ? true : false;
85 static bool hns_roce_check_hem_null(struct hns_roce_hem **hem, u64 hem_idx,
86 u32 bt_chunk_num, u64 hem_max_num)
88 u64 start_idx = round_down(hem_idx, bt_chunk_num);
89 u64 check_max_num = start_idx + bt_chunk_num;
92 for (i = start_idx; (i < check_max_num) && (i < hem_max_num); i++)
93 if (i != hem_idx && hem[i])
99 static bool hns_roce_check_bt_null(u64 **bt, u64 ba_idx, u32 bt_chunk_num)
101 u64 start_idx = round_down(ba_idx, bt_chunk_num);
104 for (i = 0; i < bt_chunk_num; i++)
105 if (i != ba_idx && bt[start_idx + i])
111 static int hns_roce_get_bt_num(u32 table_type, u32 hop_num)
113 if (check_whether_bt_num_3(table_type, hop_num))
115 else if (check_whether_bt_num_2(table_type, hop_num))
117 else if (check_whether_bt_num_1(table_type, hop_num))
123 static int get_hem_table_config(struct hns_roce_dev *hr_dev,
124 struct hns_roce_hem_mhop *mhop,
127 struct device *dev = hr_dev->dev;
131 mhop->buf_chunk_size = 1 << (hr_dev->caps.qpc_buf_pg_sz
133 mhop->bt_chunk_size = 1 << (hr_dev->caps.qpc_ba_pg_sz
135 mhop->ba_l0_num = hr_dev->caps.qpc_bt_num;
136 mhop->hop_num = hr_dev->caps.qpc_hop_num;
139 mhop->buf_chunk_size = 1 << (hr_dev->caps.mpt_buf_pg_sz
141 mhop->bt_chunk_size = 1 << (hr_dev->caps.mpt_ba_pg_sz
143 mhop->ba_l0_num = hr_dev->caps.mpt_bt_num;
144 mhop->hop_num = hr_dev->caps.mpt_hop_num;
147 mhop->buf_chunk_size = 1 << (hr_dev->caps.cqc_buf_pg_sz
149 mhop->bt_chunk_size = 1 << (hr_dev->caps.cqc_ba_pg_sz
151 mhop->ba_l0_num = hr_dev->caps.cqc_bt_num;
152 mhop->hop_num = hr_dev->caps.cqc_hop_num;
155 mhop->buf_chunk_size = 1 << (hr_dev->caps.sccc_buf_pg_sz
157 mhop->bt_chunk_size = 1 << (hr_dev->caps.sccc_ba_pg_sz
159 mhop->ba_l0_num = hr_dev->caps.sccc_bt_num;
160 mhop->hop_num = hr_dev->caps.sccc_hop_num;
162 case HEM_TYPE_QPC_TIMER:
163 mhop->buf_chunk_size = 1 << (hr_dev->caps.qpc_timer_buf_pg_sz
165 mhop->bt_chunk_size = 1 << (hr_dev->caps.qpc_timer_ba_pg_sz
167 mhop->ba_l0_num = hr_dev->caps.qpc_timer_bt_num;
168 mhop->hop_num = hr_dev->caps.qpc_timer_hop_num;
170 case HEM_TYPE_CQC_TIMER:
171 mhop->buf_chunk_size = 1 << (hr_dev->caps.cqc_timer_buf_pg_sz
173 mhop->bt_chunk_size = 1 << (hr_dev->caps.cqc_timer_ba_pg_sz
175 mhop->ba_l0_num = hr_dev->caps.cqc_timer_bt_num;
176 mhop->hop_num = hr_dev->caps.cqc_timer_hop_num;
179 mhop->buf_chunk_size = 1 << (hr_dev->caps.srqc_buf_pg_sz
181 mhop->bt_chunk_size = 1 << (hr_dev->caps.srqc_ba_pg_sz
183 mhop->ba_l0_num = hr_dev->caps.srqc_bt_num;
184 mhop->hop_num = hr_dev->caps.srqc_hop_num;
187 mhop->buf_chunk_size = 1 << (hr_dev->caps.gmv_buf_pg_sz +
189 mhop->bt_chunk_size = 1 << (hr_dev->caps.gmv_ba_pg_sz +
191 mhop->ba_l0_num = hr_dev->caps.gmv_bt_num;
192 mhop->hop_num = hr_dev->caps.gmv_hop_num;
195 dev_err(dev, "table %u not support multi-hop addressing!\n",
203 int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev,
204 struct hns_roce_hem_table *table, unsigned long *obj,
205 struct hns_roce_hem_mhop *mhop)
207 struct device *dev = hr_dev->dev;
213 if (get_hem_table_config(hr_dev, mhop, table->type))
220 * QPC/MTPT/CQC/SRQC/SCCC alloc hem for buffer pages.
221 * MTT/CQE alloc hem for bt pages.
223 bt_num = hns_roce_get_bt_num(table->type, mhop->hop_num);
224 chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;
225 chunk_size = table->type < HEM_TYPE_MTT ? mhop->buf_chunk_size :
227 table_idx = *obj / (chunk_size / table->obj_size);
230 mhop->l2_idx = table_idx & (chunk_ba_num - 1);
231 mhop->l1_idx = table_idx / chunk_ba_num & (chunk_ba_num - 1);
232 mhop->l0_idx = (table_idx / chunk_ba_num) / chunk_ba_num;
235 mhop->l1_idx = table_idx & (chunk_ba_num - 1);
236 mhop->l0_idx = table_idx / chunk_ba_num;
239 mhop->l0_idx = table_idx;
242 dev_err(dev, "table %u not support hop_num = %u!\n",
243 table->type, mhop->hop_num);
246 if (mhop->l0_idx >= mhop->ba_l0_num)
247 mhop->l0_idx %= mhop->ba_l0_num;
252 static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
254 unsigned long hem_alloc_size,
257 struct hns_roce_hem_chunk *chunk = NULL;
258 struct hns_roce_hem *hem;
259 struct scatterlist *mem;
263 WARN_ON(gfp_mask & __GFP_HIGHMEM);
265 hem = kmalloc(sizeof(*hem),
266 gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
270 INIT_LIST_HEAD(&hem->chunk_list);
272 order = get_order(hem_alloc_size);
276 chunk = kmalloc(sizeof(*chunk),
277 gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
281 sg_init_table(chunk->mem, HNS_ROCE_HEM_CHUNK_LEN);
284 memset(chunk->buf, 0, sizeof(chunk->buf));
285 list_add_tail(&chunk->list, &hem->chunk_list);
288 while (1 << order > npages)
292 * Alloc memory one time. If failed, don't alloc small block
293 * memory, directly return fail.
295 mem = &chunk->mem[chunk->npages];
296 buf = dma_alloc_coherent(hr_dev->dev, PAGE_SIZE << order,
297 &sg_dma_address(mem), gfp_mask);
301 chunk->buf[chunk->npages] = buf;
302 sg_dma_len(mem) = PAGE_SIZE << order;
306 npages -= 1 << order;
312 hns_roce_free_hem(hr_dev, hem);
316 void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem)
318 struct hns_roce_hem_chunk *chunk, *tmp;
324 list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) {
325 for (i = 0; i < chunk->npages; ++i)
326 dma_free_coherent(hr_dev->dev,
327 sg_dma_len(&chunk->mem[i]),
329 sg_dma_address(&chunk->mem[i]));
336 static int calc_hem_config(struct hns_roce_dev *hr_dev,
337 struct hns_roce_hem_table *table, unsigned long obj,
338 struct hns_roce_hem_mhop *mhop,
339 struct hns_roce_hem_index *index)
341 struct ib_device *ibdev = &hr_dev->ib_dev;
342 unsigned long mhop_obj = obj;
343 u32 l0_idx, l1_idx, l2_idx;
348 ret = hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, mhop);
352 l0_idx = mhop->l0_idx;
353 l1_idx = mhop->l1_idx;
354 l2_idx = mhop->l2_idx;
355 chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;
356 bt_num = hns_roce_get_bt_num(table->type, mhop->hop_num);
359 index->l1 = l0_idx * chunk_ba_num + l1_idx;
361 index->buf = l0_idx * chunk_ba_num * chunk_ba_num +
362 l1_idx * chunk_ba_num + l2_idx;
366 index->buf = l0_idx * chunk_ba_num + l1_idx;
372 ibdev_err(ibdev, "table %u not support mhop.hop_num = %u!\n",
373 table->type, mhop->hop_num);
377 if (unlikely(index->buf >= table->num_hem)) {
378 ibdev_err(ibdev, "table %u exceed hem limt idx %llu, max %lu!\n",
379 table->type, index->buf, table->num_hem);
386 static void free_mhop_hem(struct hns_roce_dev *hr_dev,
387 struct hns_roce_hem_table *table,
388 struct hns_roce_hem_mhop *mhop,
389 struct hns_roce_hem_index *index)
391 u32 bt_size = mhop->bt_chunk_size;
392 struct device *dev = hr_dev->dev;
394 if (index->inited & HEM_INDEX_BUF) {
395 hns_roce_free_hem(hr_dev, table->hem[index->buf]);
396 table->hem[index->buf] = NULL;
399 if (index->inited & HEM_INDEX_L1) {
400 dma_free_coherent(dev, bt_size, table->bt_l1[index->l1],
401 table->bt_l1_dma_addr[index->l1]);
402 table->bt_l1[index->l1] = NULL;
405 if (index->inited & HEM_INDEX_L0) {
406 dma_free_coherent(dev, bt_size, table->bt_l0[index->l0],
407 table->bt_l0_dma_addr[index->l0]);
408 table->bt_l0[index->l0] = NULL;
412 static int alloc_mhop_hem(struct hns_roce_dev *hr_dev,
413 struct hns_roce_hem_table *table,
414 struct hns_roce_hem_mhop *mhop,
415 struct hns_roce_hem_index *index)
417 u32 bt_size = mhop->bt_chunk_size;
418 struct device *dev = hr_dev->dev;
419 struct hns_roce_hem_iter iter;
425 /* alloc L1 BA's chunk */
426 if ((check_whether_bt_num_3(table->type, mhop->hop_num) ||
427 check_whether_bt_num_2(table->type, mhop->hop_num)) &&
428 !table->bt_l0[index->l0]) {
429 table->bt_l0[index->l0] = dma_alloc_coherent(dev, bt_size,
430 &table->bt_l0_dma_addr[index->l0],
432 if (!table->bt_l0[index->l0]) {
436 index->inited |= HEM_INDEX_L0;
439 /* alloc L2 BA's chunk */
440 if (check_whether_bt_num_3(table->type, mhop->hop_num) &&
441 !table->bt_l1[index->l1]) {
442 table->bt_l1[index->l1] = dma_alloc_coherent(dev, bt_size,
443 &table->bt_l1_dma_addr[index->l1],
445 if (!table->bt_l1[index->l1]) {
449 index->inited |= HEM_INDEX_L1;
450 *(table->bt_l0[index->l0] + mhop->l1_idx) =
451 table->bt_l1_dma_addr[index->l1];
455 * alloc buffer space chunk for QPC/MTPT/CQC/SRQC/SCCC.
456 * alloc bt space chunk for MTT/CQE.
458 size = table->type < HEM_TYPE_MTT ? mhop->buf_chunk_size : bt_size;
459 flag = (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) | __GFP_NOWARN;
460 table->hem[index->buf] = hns_roce_alloc_hem(hr_dev, size >> PAGE_SHIFT,
462 if (!table->hem[index->buf]) {
467 index->inited |= HEM_INDEX_BUF;
468 hns_roce_hem_first(table->hem[index->buf], &iter);
469 bt_ba = hns_roce_hem_addr(&iter);
470 if (table->type < HEM_TYPE_MTT) {
471 if (mhop->hop_num == 2)
472 *(table->bt_l1[index->l1] + mhop->l2_idx) = bt_ba;
473 else if (mhop->hop_num == 1)
474 *(table->bt_l0[index->l0] + mhop->l1_idx) = bt_ba;
475 } else if (mhop->hop_num == 2) {
476 *(table->bt_l0[index->l0] + mhop->l1_idx) = bt_ba;
481 free_mhop_hem(hr_dev, table, mhop, index);
486 static int set_mhop_hem(struct hns_roce_dev *hr_dev,
487 struct hns_roce_hem_table *table, unsigned long obj,
488 struct hns_roce_hem_mhop *mhop,
489 struct hns_roce_hem_index *index)
491 struct ib_device *ibdev = &hr_dev->ib_dev;
495 if (index->inited & HEM_INDEX_L0) {
496 ret = hr_dev->hw->set_hem(hr_dev, table, obj, 0);
498 ibdev_err(ibdev, "set HEM step 0 failed!\n");
503 if (index->inited & HEM_INDEX_L1) {
504 ret = hr_dev->hw->set_hem(hr_dev, table, obj, 1);
506 ibdev_err(ibdev, "set HEM step 1 failed!\n");
511 if (index->inited & HEM_INDEX_BUF) {
512 if (mhop->hop_num == HNS_ROCE_HOP_NUM_0)
515 step_idx = mhop->hop_num;
516 ret = hr_dev->hw->set_hem(hr_dev, table, obj, step_idx);
518 ibdev_err(ibdev, "set HEM step last failed!\n");
524 static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev,
525 struct hns_roce_hem_table *table,
528 struct ib_device *ibdev = &hr_dev->ib_dev;
529 struct hns_roce_hem_index index = {};
530 struct hns_roce_hem_mhop mhop = {};
533 ret = calc_hem_config(hr_dev, table, obj, &mhop, &index);
535 ibdev_err(ibdev, "calc hem config failed!\n");
539 mutex_lock(&table->mutex);
540 if (table->hem[index.buf]) {
541 refcount_inc(&table->hem[index.buf]->refcount);
545 ret = alloc_mhop_hem(hr_dev, table, &mhop, &index);
547 ibdev_err(ibdev, "alloc mhop hem failed!\n");
551 /* set HEM base address to hardware */
552 if (table->type < HEM_TYPE_MTT) {
553 ret = set_mhop_hem(hr_dev, table, obj, &mhop, &index);
555 ibdev_err(ibdev, "set HEM address to HW failed!\n");
560 refcount_set(&table->hem[index.buf]->refcount, 1);
564 free_mhop_hem(hr_dev, table, &mhop, &index);
566 mutex_unlock(&table->mutex);
570 int hns_roce_table_get(struct hns_roce_dev *hr_dev,
571 struct hns_roce_hem_table *table, unsigned long obj)
573 struct device *dev = hr_dev->dev;
577 if (hns_roce_check_whether_mhop(hr_dev, table->type))
578 return hns_roce_table_mhop_get(hr_dev, table, obj);
580 i = obj / (table->table_chunk_size / table->obj_size);
582 mutex_lock(&table->mutex);
585 refcount_inc(&table->hem[i]->refcount);
589 table->hem[i] = hns_roce_alloc_hem(hr_dev,
590 table->table_chunk_size >> PAGE_SHIFT,
591 table->table_chunk_size,
592 (table->lowmem ? GFP_KERNEL :
593 GFP_HIGHUSER) | __GFP_NOWARN);
594 if (!table->hem[i]) {
599 /* Set HEM base address(128K/page, pa) to Hardware */
600 if (hr_dev->hw->set_hem(hr_dev, table, obj, HEM_HOP_STEP_DIRECT)) {
601 hns_roce_free_hem(hr_dev, table->hem[i]);
602 table->hem[i] = NULL;
604 dev_err(dev, "set HEM base address to HW failed.\n");
608 refcount_set(&table->hem[i]->refcount, 1);
610 mutex_unlock(&table->mutex);
614 static void clear_mhop_hem(struct hns_roce_dev *hr_dev,
615 struct hns_roce_hem_table *table, unsigned long obj,
616 struct hns_roce_hem_mhop *mhop,
617 struct hns_roce_hem_index *index)
619 struct ib_device *ibdev = &hr_dev->ib_dev;
620 u32 hop_num = mhop->hop_num;
624 index->inited = HEM_INDEX_BUF;
625 chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;
626 if (check_whether_bt_num_2(table->type, hop_num)) {
627 if (hns_roce_check_hem_null(table->hem, index->buf,
628 chunk_ba_num, table->num_hem))
629 index->inited |= HEM_INDEX_L0;
630 } else if (check_whether_bt_num_3(table->type, hop_num)) {
631 if (hns_roce_check_hem_null(table->hem, index->buf,
632 chunk_ba_num, table->num_hem)) {
633 index->inited |= HEM_INDEX_L1;
634 if (hns_roce_check_bt_null(table->bt_l1, index->l1,
636 index->inited |= HEM_INDEX_L0;
640 if (table->type < HEM_TYPE_MTT) {
641 if (hop_num == HNS_ROCE_HOP_NUM_0)
646 if (hr_dev->hw->clear_hem(hr_dev, table, obj, step_idx))
647 ibdev_warn(ibdev, "failed to clear hop%u HEM.\n", hop_num);
649 if (index->inited & HEM_INDEX_L1)
650 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 1))
651 ibdev_warn(ibdev, "failed to clear HEM step 1.\n");
653 if (index->inited & HEM_INDEX_L0)
654 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
655 ibdev_warn(ibdev, "failed to clear HEM step 0.\n");
659 static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
660 struct hns_roce_hem_table *table,
664 struct ib_device *ibdev = &hr_dev->ib_dev;
665 struct hns_roce_hem_index index = {};
666 struct hns_roce_hem_mhop mhop = {};
669 ret = calc_hem_config(hr_dev, table, obj, &mhop, &index);
671 ibdev_err(ibdev, "calc hem config failed!\n");
676 mutex_lock(&table->mutex);
677 else if (!refcount_dec_and_mutex_lock(&table->hem[index.buf]->refcount,
681 clear_mhop_hem(hr_dev, table, obj, &mhop, &index);
682 free_mhop_hem(hr_dev, table, &mhop, &index);
684 mutex_unlock(&table->mutex);
687 void hns_roce_table_put(struct hns_roce_dev *hr_dev,
688 struct hns_roce_hem_table *table, unsigned long obj)
690 struct device *dev = hr_dev->dev;
693 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
694 hns_roce_table_mhop_put(hr_dev, table, obj, 1);
698 i = obj / (table->table_chunk_size / table->obj_size);
700 if (!refcount_dec_and_mutex_lock(&table->hem[i]->refcount,
704 if (hr_dev->hw->clear_hem(hr_dev, table, obj, HEM_HOP_STEP_DIRECT))
705 dev_warn(dev, "failed to clear HEM base address.\n");
707 hns_roce_free_hem(hr_dev, table->hem[i]);
708 table->hem[i] = NULL;
710 mutex_unlock(&table->mutex);
713 void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
714 struct hns_roce_hem_table *table,
715 unsigned long obj, dma_addr_t *dma_handle)
717 struct hns_roce_hem_chunk *chunk;
718 struct hns_roce_hem_mhop mhop;
719 struct hns_roce_hem *hem;
720 unsigned long mhop_obj = obj;
721 unsigned long obj_per_chunk;
722 unsigned long idx_offset;
723 int offset, dma_offset;
732 mutex_lock(&table->mutex);
734 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) {
735 obj_per_chunk = table->table_chunk_size / table->obj_size;
736 hem = table->hem[obj / obj_per_chunk];
737 idx_offset = obj % obj_per_chunk;
738 dma_offset = offset = idx_offset * table->obj_size;
740 u32 seg_size = 64; /* 8 bytes per BA and 8 BA per segment */
742 if (hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop))
747 if (mhop.hop_num == 2)
748 hem_idx = i * (mhop.bt_chunk_size / BA_BYTE_LEN) + j;
749 else if (mhop.hop_num == 1 ||
750 mhop.hop_num == HNS_ROCE_HOP_NUM_0)
753 hem = table->hem[hem_idx];
754 dma_offset = offset = obj * seg_size % mhop.bt_chunk_size;
755 if (mhop.hop_num == 2)
756 dma_offset = offset = 0;
762 list_for_each_entry(chunk, &hem->chunk_list, list) {
763 for (i = 0; i < chunk->npages; ++i) {
764 length = sg_dma_len(&chunk->mem[i]);
765 if (dma_handle && dma_offset >= 0) {
766 if (length > (u32)dma_offset)
767 *dma_handle = sg_dma_address(
768 &chunk->mem[i]) + dma_offset;
769 dma_offset -= length;
772 if (length > (u32)offset) {
773 addr = chunk->buf[i] + offset;
781 mutex_unlock(&table->mutex);
785 int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
786 struct hns_roce_hem_table *table, u32 type,
787 unsigned long obj_size, unsigned long nobj,
790 unsigned long obj_per_chunk;
791 unsigned long num_hem;
793 if (!hns_roce_check_whether_mhop(hr_dev, type)) {
794 table->table_chunk_size = hr_dev->caps.chunk_sz;
795 obj_per_chunk = table->table_chunk_size / obj_size;
796 num_hem = DIV_ROUND_UP(nobj, obj_per_chunk);
798 table->hem = kcalloc(num_hem, sizeof(*table->hem), GFP_KERNEL);
802 struct hns_roce_hem_mhop mhop = {};
803 unsigned long buf_chunk_size;
804 unsigned long bt_chunk_size;
805 unsigned long bt_chunk_num;
806 unsigned long num_bt_l0;
809 if (get_hem_table_config(hr_dev, &mhop, type))
812 buf_chunk_size = mhop.buf_chunk_size;
813 bt_chunk_size = mhop.bt_chunk_size;
814 num_bt_l0 = mhop.ba_l0_num;
815 hop_num = mhop.hop_num;
817 obj_per_chunk = buf_chunk_size / obj_size;
818 num_hem = DIV_ROUND_UP(nobj, obj_per_chunk);
819 bt_chunk_num = bt_chunk_size / BA_BYTE_LEN;
821 if (type >= HEM_TYPE_MTT)
822 num_bt_l0 = bt_chunk_num;
824 table->hem = kcalloc(num_hem, sizeof(*table->hem),
827 goto err_kcalloc_hem_buf;
829 if (check_whether_bt_num_3(type, hop_num)) {
830 unsigned long num_bt_l1;
832 num_bt_l1 = DIV_ROUND_UP(num_hem, bt_chunk_num);
833 table->bt_l1 = kcalloc(num_bt_l1,
834 sizeof(*table->bt_l1),
837 goto err_kcalloc_bt_l1;
839 table->bt_l1_dma_addr = kcalloc(num_bt_l1,
840 sizeof(*table->bt_l1_dma_addr),
843 if (!table->bt_l1_dma_addr)
844 goto err_kcalloc_l1_dma;
847 if (check_whether_bt_num_2(type, hop_num) ||
848 check_whether_bt_num_3(type, hop_num)) {
849 table->bt_l0 = kcalloc(num_bt_l0, sizeof(*table->bt_l0),
852 goto err_kcalloc_bt_l0;
854 table->bt_l0_dma_addr = kcalloc(num_bt_l0,
855 sizeof(*table->bt_l0_dma_addr),
857 if (!table->bt_l0_dma_addr)
858 goto err_kcalloc_l0_dma;
863 table->num_hem = num_hem;
864 table->obj_size = obj_size;
865 table->lowmem = use_lowmem;
866 mutex_init(&table->mutex);
875 kfree(table->bt_l1_dma_addr);
876 table->bt_l1_dma_addr = NULL;
890 static void hns_roce_cleanup_mhop_hem_table(struct hns_roce_dev *hr_dev,
891 struct hns_roce_hem_table *table)
893 struct hns_roce_hem_mhop mhop;
898 if (hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop))
900 buf_chunk_size = table->type < HEM_TYPE_MTT ? mhop.buf_chunk_size :
903 for (i = 0; i < table->num_hem; ++i) {
904 obj = i * buf_chunk_size / table->obj_size;
906 hns_roce_table_mhop_put(hr_dev, table, obj, 0);
913 kfree(table->bt_l1_dma_addr);
914 table->bt_l1_dma_addr = NULL;
917 kfree(table->bt_l0_dma_addr);
918 table->bt_l0_dma_addr = NULL;
921 void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
922 struct hns_roce_hem_table *table)
924 struct device *dev = hr_dev->dev;
927 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
928 hns_roce_cleanup_mhop_hem_table(hr_dev, table);
932 for (i = 0; i < table->num_hem; ++i)
934 if (hr_dev->hw->clear_hem(hr_dev, table,
935 i * table->table_chunk_size / table->obj_size, 0))
936 dev_err(dev, "Clear HEM base address failed.\n");
938 hns_roce_free_hem(hr_dev, table->hem[i]);
944 void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev)
946 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
947 hns_roce_cleanup_hem_table(hr_dev,
948 &hr_dev->srq_table.table);
949 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
950 if (hr_dev->caps.qpc_timer_entry_sz)
951 hns_roce_cleanup_hem_table(hr_dev,
952 &hr_dev->qpc_timer_table);
953 if (hr_dev->caps.cqc_timer_entry_sz)
954 hns_roce_cleanup_hem_table(hr_dev,
955 &hr_dev->cqc_timer_table);
956 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
957 hns_roce_cleanup_hem_table(hr_dev,
958 &hr_dev->qp_table.sccc_table);
959 if (hr_dev->caps.trrl_entry_sz)
960 hns_roce_cleanup_hem_table(hr_dev,
961 &hr_dev->qp_table.trrl_table);
963 if (hr_dev->caps.gmv_entry_sz)
964 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->gmv_table);
966 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
967 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
968 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
971 struct hns_roce_hem_item {
972 struct list_head list; /* link all hems in the same bt level */
973 struct list_head sibling; /* link all hems in last hop for mtt */
976 size_t count; /* max ba numbers */
977 int start; /* start buf offset in this hem */
978 int end; /* end buf offset in this hem */
981 /* All HEM items are linked in a tree structure */
982 struct hns_roce_hem_head {
983 struct list_head branch[HNS_ROCE_MAX_BT_REGION];
984 struct list_head root;
985 struct list_head leaf;
988 static struct hns_roce_hem_item *
989 hem_list_alloc_item(struct hns_roce_dev *hr_dev, int start, int end, int count,
990 bool exist_bt, int bt_level)
992 struct hns_roce_hem_item *hem;
994 hem = kzalloc(sizeof(*hem), GFP_KERNEL);
999 hem->addr = dma_alloc_coherent(hr_dev->dev, count * BA_BYTE_LEN,
1000 &hem->dma_addr, GFP_KERNEL);
1010 INIT_LIST_HEAD(&hem->list);
1011 INIT_LIST_HEAD(&hem->sibling);
1016 static void hem_list_free_item(struct hns_roce_dev *hr_dev,
1017 struct hns_roce_hem_item *hem, bool exist_bt)
1020 dma_free_coherent(hr_dev->dev, hem->count * BA_BYTE_LEN,
1021 hem->addr, hem->dma_addr);
1025 static void hem_list_free_all(struct hns_roce_dev *hr_dev,
1026 struct list_head *head, bool exist_bt)
1028 struct hns_roce_hem_item *hem, *temp_hem;
1030 list_for_each_entry_safe(hem, temp_hem, head, list) {
1031 list_del(&hem->list);
1032 hem_list_free_item(hr_dev, hem, exist_bt);
1036 static void hem_list_link_bt(struct hns_roce_dev *hr_dev, void *base_addr,
1039 *(u64 *)(base_addr) = table_addr;
1042 /* assign L0 table address to hem from root bt */
1043 static void hem_list_assign_bt(struct hns_roce_dev *hr_dev,
1044 struct hns_roce_hem_item *hem, void *cpu_addr,
1047 hem->addr = cpu_addr;
1048 hem->dma_addr = (dma_addr_t)phy_addr;
1051 static inline bool hem_list_page_is_in_range(struct hns_roce_hem_item *hem,
1054 return (hem->start <= offset && offset <= hem->end);
1057 static struct hns_roce_hem_item *hem_list_search_item(struct list_head *ba_list,
1060 struct hns_roce_hem_item *hem, *temp_hem;
1061 struct hns_roce_hem_item *found = NULL;
1063 list_for_each_entry_safe(hem, temp_hem, ba_list, list) {
1064 if (hem_list_page_is_in_range(hem, page_offset)) {
1073 static bool hem_list_is_bottom_bt(int hopnum, int bt_level)
1076 * hopnum base address table levels
1080 * 3 L0 -> L1 -> L2 -> buf
1082 return bt_level >= (hopnum ? hopnum - 1 : hopnum);
1086 * calc base address entries num
1087 * @hopnum: num of mutihop addressing
1088 * @bt_level: base address table level
1089 * @unit: ba entries per bt page
1091 static u32 hem_list_calc_ba_range(int hopnum, int bt_level, int unit)
1097 if (hopnum <= bt_level)
1100 * hopnum bt_level range
1106 * 3 0 unit * unit * unit
1111 max = hopnum - bt_level;
1112 for (i = 0; i < max; i++)
1119 * calc the root ba entries which could cover all regions
1120 * @regions: buf region array
1121 * @region_cnt: array size of @regions
1122 * @unit: ba entries per bt page
1124 int hns_roce_hem_list_calc_root_ba(const struct hns_roce_buf_region *regions,
1125 int region_cnt, int unit)
1127 struct hns_roce_buf_region *r;
1132 for (i = 0; i < region_cnt; i++) {
1133 r = (struct hns_roce_buf_region *)®ions[i];
1134 if (r->hopnum > 1) {
1135 step = hem_list_calc_ba_range(r->hopnum, 1, unit);
1137 total += (r->count + step - 1) / step;
1146 static int hem_list_alloc_mid_bt(struct hns_roce_dev *hr_dev,
1147 const struct hns_roce_buf_region *r, int unit,
1148 int offset, struct list_head *mid_bt,
1149 struct list_head *btm_bt)
1151 struct hns_roce_hem_item *hem_ptrs[HNS_ROCE_MAX_BT_LEVEL] = { NULL };
1152 struct list_head temp_list[HNS_ROCE_MAX_BT_LEVEL];
1153 struct hns_roce_hem_item *cur, *pre;
1154 const int hopnum = r->hopnum;
1166 if (hopnum > HNS_ROCE_MAX_BT_LEVEL) {
1167 dev_err(hr_dev->dev, "invalid hopnum %d!\n", hopnum);
1171 if (offset < r->offset) {
1172 dev_err(hr_dev->dev, "invalid offset %d, min %u!\n",
1177 distance = offset - r->offset;
1178 max_ofs = r->offset + r->count - 1;
1179 for (level = 0; level < hopnum; level++)
1180 INIT_LIST_HEAD(&temp_list[level]);
1182 /* config L1 bt to last bt and link them to corresponding parent */
1183 for (level = 1; level < hopnum; level++) {
1184 cur = hem_list_search_item(&mid_bt[level], offset);
1186 hem_ptrs[level] = cur;
1190 step = hem_list_calc_ba_range(hopnum, level, unit);
1196 start_aligned = (distance / step) * step + r->offset;
1197 end = min_t(int, start_aligned + step - 1, max_ofs);
1198 cur = hem_list_alloc_item(hr_dev, start_aligned, end, unit,
1204 hem_ptrs[level] = cur;
1205 list_add(&cur->list, &temp_list[level]);
1206 if (hem_list_is_bottom_bt(hopnum, level))
1207 list_add(&cur->sibling, &temp_list[0]);
1209 /* link bt to parent bt */
1211 pre = hem_ptrs[level - 1];
1212 step = (cur->start - pre->start) / step * BA_BYTE_LEN;
1213 hem_list_link_bt(hr_dev, pre->addr + step,
1218 list_splice(&temp_list[0], btm_bt);
1219 for (level = 1; level < hopnum; level++)
1220 list_splice(&temp_list[level], &mid_bt[level]);
1225 for (level = 1; level < hopnum; level++)
1226 hem_list_free_all(hr_dev, &temp_list[level], true);
1231 static struct hns_roce_hem_item *
1232 alloc_root_hem(struct hns_roce_dev *hr_dev, int unit, int *max_ba_num,
1233 const struct hns_roce_buf_region *regions, int region_cnt)
1235 const struct hns_roce_buf_region *r;
1236 struct hns_roce_hem_item *hem;
1240 ba_num = hns_roce_hem_list_calc_root_ba(regions, region_cnt, unit);
1242 return ERR_PTR(-ENOMEM);
1245 return ERR_PTR(-ENOBUFS);
1247 offset = regions[0].offset;
1248 /* indicate to last region */
1249 r = ®ions[region_cnt - 1];
1250 hem = hem_list_alloc_item(hr_dev, offset, r->offset + r->count - 1,
1253 return ERR_PTR(-ENOMEM);
1255 *max_ba_num = ba_num;
1260 static int alloc_fake_root_bt(struct hns_roce_dev *hr_dev, void *cpu_base,
1261 u64 phy_base, const struct hns_roce_buf_region *r,
1262 struct list_head *branch_head,
1263 struct list_head *leaf_head)
1265 struct hns_roce_hem_item *hem;
1267 hem = hem_list_alloc_item(hr_dev, r->offset, r->offset + r->count - 1,
1268 r->count, false, 0);
1272 hem_list_assign_bt(hr_dev, hem, cpu_base, phy_base);
1273 list_add(&hem->list, branch_head);
1274 list_add(&hem->sibling, leaf_head);
1279 static int setup_middle_bt(struct hns_roce_dev *hr_dev, void *cpu_base,
1280 int unit, const struct hns_roce_buf_region *r,
1281 const struct list_head *branch_head)
1283 struct hns_roce_hem_item *hem, *temp_hem;
1288 step = hem_list_calc_ba_range(r->hopnum, 1, unit);
1292 /* if exist mid bt, link L1 to L0 */
1293 list_for_each_entry_safe(hem, temp_hem, branch_head, list) {
1294 offset = (hem->start - r->offset) / step * BA_BYTE_LEN;
1295 hem_list_link_bt(hr_dev, cpu_base + offset, hem->dma_addr);
1303 setup_root_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem_list *hem_list,
1304 int unit, int max_ba_num, struct hns_roce_hem_head *head,
1305 const struct hns_roce_buf_region *regions, int region_cnt)
1307 const struct hns_roce_buf_region *r;
1308 struct hns_roce_hem_item *root_hem;
1314 root_hem = list_first_entry(&head->root,
1315 struct hns_roce_hem_item, list);
1320 for (i = 0; i < region_cnt && total < max_ba_num; i++) {
1325 /* all regions's mid[x][0] shared the root_bt's trunk */
1326 cpu_base = root_hem->addr + total * BA_BYTE_LEN;
1327 phy_base = root_hem->dma_addr + total * BA_BYTE_LEN;
1329 /* if hopnum is 0 or 1, cut a new fake hem from the root bt
1330 * which's address share to all regions.
1332 if (hem_list_is_bottom_bt(r->hopnum, 0))
1333 ret = alloc_fake_root_bt(hr_dev, cpu_base, phy_base, r,
1334 &head->branch[i], &head->leaf);
1336 ret = setup_middle_bt(hr_dev, cpu_base, unit, r,
1337 &hem_list->mid_bt[i][1]);
1345 list_splice(&head->leaf, &hem_list->btm_bt);
1346 list_splice(&head->root, &hem_list->root_bt);
1347 for (i = 0; i < region_cnt; i++)
1348 list_splice(&head->branch[i], &hem_list->mid_bt[i][0]);
1353 static int hem_list_alloc_root_bt(struct hns_roce_dev *hr_dev,
1354 struct hns_roce_hem_list *hem_list, int unit,
1355 const struct hns_roce_buf_region *regions,
1358 struct hns_roce_hem_item *root_hem;
1359 struct hns_roce_hem_head head;
1364 root_hem = hem_list_search_item(&hem_list->root_bt, regions[0].offset);
1369 root_hem = alloc_root_hem(hr_dev, unit, &max_ba_num, regions,
1371 if (IS_ERR(root_hem))
1372 return PTR_ERR(root_hem);
1374 /* List head for storing all allocated HEM items */
1375 INIT_LIST_HEAD(&head.root);
1376 INIT_LIST_HEAD(&head.leaf);
1377 for (i = 0; i < region_cnt; i++)
1378 INIT_LIST_HEAD(&head.branch[i]);
1380 hem_list->root_ba = root_hem->dma_addr;
1381 list_add(&root_hem->list, &head.root);
1382 ret = setup_root_hem(hr_dev, hem_list, unit, max_ba_num, &head, regions,
1385 for (i = 0; i < region_cnt; i++)
1386 hem_list_free_all(hr_dev, &head.branch[i], false);
1388 hem_list_free_all(hr_dev, &head.root, true);
1394 /* construct the base address table and link them by address hop config */
1395 int hns_roce_hem_list_request(struct hns_roce_dev *hr_dev,
1396 struct hns_roce_hem_list *hem_list,
1397 const struct hns_roce_buf_region *regions,
1398 int region_cnt, unsigned int bt_pg_shift)
1400 const struct hns_roce_buf_region *r;
1406 if (region_cnt > HNS_ROCE_MAX_BT_REGION) {
1407 dev_err(hr_dev->dev, "invalid region region_cnt %d!\n",
1412 unit = (1 << bt_pg_shift) / BA_BYTE_LEN;
1413 for (i = 0; i < region_cnt; i++) {
1418 end = r->offset + r->count;
1419 for (ofs = r->offset; ofs < end; ofs += unit) {
1420 ret = hem_list_alloc_mid_bt(hr_dev, r, unit, ofs,
1421 hem_list->mid_bt[i],
1424 dev_err(hr_dev->dev,
1425 "alloc hem trunk fail ret=%d!\n", ret);
1431 ret = hem_list_alloc_root_bt(hr_dev, hem_list, unit, regions,
1434 dev_err(hr_dev->dev, "alloc hem root fail ret=%d!\n", ret);
1439 hns_roce_hem_list_release(hr_dev, hem_list);
1444 void hns_roce_hem_list_release(struct hns_roce_dev *hr_dev,
1445 struct hns_roce_hem_list *hem_list)
1449 for (i = 0; i < HNS_ROCE_MAX_BT_REGION; i++)
1450 for (j = 0; j < HNS_ROCE_MAX_BT_LEVEL; j++)
1451 hem_list_free_all(hr_dev, &hem_list->mid_bt[i][j],
1454 hem_list_free_all(hr_dev, &hem_list->root_bt, true);
1455 INIT_LIST_HEAD(&hem_list->btm_bt);
1456 hem_list->root_ba = 0;
1459 void hns_roce_hem_list_init(struct hns_roce_hem_list *hem_list)
1463 INIT_LIST_HEAD(&hem_list->root_bt);
1464 INIT_LIST_HEAD(&hem_list->btm_bt);
1465 for (i = 0; i < HNS_ROCE_MAX_BT_REGION; i++)
1466 for (j = 0; j < HNS_ROCE_MAX_BT_LEVEL; j++)
1467 INIT_LIST_HEAD(&hem_list->mid_bt[i][j]);
1470 void *hns_roce_hem_list_find_mtt(struct hns_roce_dev *hr_dev,
1471 struct hns_roce_hem_list *hem_list,
1472 int offset, int *mtt_cnt, u64 *phy_addr)
1474 struct list_head *head = &hem_list->btm_bt;
1475 struct hns_roce_hem_item *hem, *temp_hem;
1476 void *cpu_base = NULL;
1480 list_for_each_entry_safe(hem, temp_hem, head, sibling) {
1481 if (hem_list_page_is_in_range(hem, offset)) {
1482 nr = offset - hem->start;
1483 cpu_base = hem->addr + nr * BA_BYTE_LEN;
1484 phy_base = hem->dma_addr + nr * BA_BYTE_LEN;
1485 nr = hem->end + 1 - offset;
1494 *phy_addr = phy_base;