drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37 #include <rdma/hns-abi.h>
  38
  39 #define DRV_NAME "hns_roce"
  40
  41 #define PCI_REVISION_ID_HIP08                   0x21
  42 #define PCI_REVISION_ID_HIP09                   0x30
  43
  44 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  45
  46 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  47
  48 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  49
  50 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  51
  52 #define BA_BYTE_LEN                             8
  53
  54 /* Hardware specification only for v1 engine */
  55 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  56 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  57 #define HNS_ROCE_MIN_SRQ_WQE_NUM                1
  58
  59 /* Hardware specification only for v1 engine */
  60 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  61 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  62
  63 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  64 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  65         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  66 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  67 #define HNS_ROCE_MIN_CQE_CNT                    16
  68
  69 #define HNS_ROCE_RESERVED_SGE                   1
  70
  71 #define HNS_ROCE_MAX_IRQ_NUM                    128
  72
  73 #define HNS_ROCE_SGE_IN_WQE                     2
  74 #define HNS_ROCE_SGE_SHIFT                      4
  75
  76 #define EQ_ENABLE                               1
  77 #define EQ_DISABLE                              0
  78
  79 #define HNS_ROCE_CEQ                            0
  80 #define HNS_ROCE_AEQ                            1
  81
  82 #define HNS_ROCE_CEQE_SIZE 0x4
  83 #define HNS_ROCE_AEQE_SIZE 0x10
  84
  85 #define HNS_ROCE_V3_EQE_SIZE 0x40
  86
  87 #define HNS_ROCE_V2_CQE_SIZE 32
  88 #define HNS_ROCE_V3_CQE_SIZE 64
  89
  90 #define HNS_ROCE_V2_QPC_SZ 256
  91 #define HNS_ROCE_V3_QPC_SZ 512
  92
  93 #define HNS_ROCE_MAX_PORTS                      6
  94 #define HNS_ROCE_GID_SIZE                       16
  95 #define HNS_ROCE_SGE_SIZE                       16
  96 #define HNS_ROCE_DWQE_SIZE                      65536
  97
  98 #define HNS_ROCE_HOP_NUM_0                      0xff
  99
 100 #define BITMAP_NO_RR                            0
 101 #define BITMAP_RR                               1
 102
 103 #define MR_TYPE_MR                              0x00
 104 #define MR_TYPE_FRMR                            0x01
 105 #define MR_TYPE_DMA                             0x03
 106
 107 #define HNS_ROCE_FRMR_MAX_PA                    512
 108
 109 #define PKEY_ID                                 0xffff
 110 #define GUID_LEN                                8
 111 #define NODE_DESC_SIZE                          64
 112 #define DB_REG_OFFSET                           0x1000
 113
 114 /* Configure to HW for PAGE_SIZE larger than 4KB */
 115 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 116
 117 #define PAGES_SHIFT_8                           8
 118 #define PAGES_SHIFT_16                          16
 119 #define PAGES_SHIFT_24                          24
 120 #define PAGES_SHIFT_32                          32
 121
 122 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 123 #define SRQ_DB_REG                              0x230
 124
 125 #define HNS_ROCE_QP_BANK_NUM 8
 126 #define HNS_ROCE_CQ_BANK_NUM 4
 127
 128 #define CQ_BANKID_SHIFT 2
 129
 130 /* The chip implementation of the consumer index is calculated
 131  * according to twice the actual EQ depth
 132  */
 133 #define EQ_DEPTH_COEFF                          2
 134
 135 enum {
 136         SERV_TYPE_RC,
 137         SERV_TYPE_UC,
 138         SERV_TYPE_RD,
 139         SERV_TYPE_UD,
 140 };
 141
 142 enum hns_roce_qp_state {
 143         HNS_ROCE_QP_STATE_RST,
 144         HNS_ROCE_QP_STATE_INIT,
 145         HNS_ROCE_QP_STATE_RTR,
 146         HNS_ROCE_QP_STATE_RTS,
 147         HNS_ROCE_QP_STATE_SQD,
 148         HNS_ROCE_QP_STATE_ERR,
 149         HNS_ROCE_QP_NUM_STATE,
 150 };
 151
 152 enum hns_roce_event {
 153         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 154         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 155         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 156         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 157         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 158         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 159         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 160         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 161         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 162         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 163         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 164         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 165         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 166         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 167         /* 0x10 and 0x11 is unused in currently application case */
 168         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 169         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 170         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 171 };
 172
 173 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 174 enum {
 175         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 176         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 177         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 178         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 179         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 180         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 181         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 182 };
 183
 184 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 185 enum {
 186         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 187         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 188         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 189         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 190         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 191         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 192         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 193 };
 194
 195 /* DOORBELL overflow subtype */
 196 enum {
 197         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 198         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 199         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 200         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 201         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 202         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 203 };
 204
 205 enum {
 206         /* RQ&SRQ related operations */
 207         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 208         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 209 };
 210
 211 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
 212
 213 enum {
 214         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 215         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 216         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 217         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
 218         HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
 219         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 220         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 221         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 222         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 223         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 224         HNS_ROCE_CAP_FLAG_SDI_MODE              = BIT(14),
 225         HNS_ROCE_CAP_FLAG_STASH                 = BIT(17),
 226 };
 227
 228 #define HNS_ROCE_DB_TYPE_COUNT                  2
 229 #define HNS_ROCE_DB_UNIT_SIZE                   4
 230
 231 enum {
 232         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 233 };
 234
 235 enum hns_roce_reset_stage {
 236         HNS_ROCE_STATE_NON_RST,
 237         HNS_ROCE_STATE_RST_BEF_DOWN,
 238         HNS_ROCE_STATE_RST_DOWN,
 239         HNS_ROCE_STATE_RST_UNINIT,
 240         HNS_ROCE_STATE_RST_INIT,
 241         HNS_ROCE_STATE_RST_INITED,
 242 };
 243
 244 enum hns_roce_instance_state {
 245         HNS_ROCE_STATE_NON_INIT,
 246         HNS_ROCE_STATE_INIT,
 247         HNS_ROCE_STATE_INITED,
 248         HNS_ROCE_STATE_UNINIT,
 249 };
 250
 251 enum {
 252         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 253 };
 254
 255 enum {
 256         CMD_RST_PRC_OTHERS,
 257         CMD_RST_PRC_SUCCESS,
 258         CMD_RST_PRC_EBUSY,
 259 };
 260
 261 #define HNS_ROCE_CMD_SUCCESS                    1
 262
 263 #define HNS_ROCE_PORT_DOWN                      0
 264 #define HNS_ROCE_PORT_UP                        1
 265
 266 /* The minimum page size is 4K for hardware */
 267 #define HNS_HW_PAGE_SHIFT                       12
 268 #define HNS_HW_PAGE_SIZE                        (1 << HNS_HW_PAGE_SHIFT)
 269
 270 struct hns_roce_uar {
 271         u64             pfn;
 272         unsigned long   index;
 273         unsigned long   logic_idx;
 274 };
 275
 276 struct hns_roce_ucontext {
 277         struct ib_ucontext      ibucontext;
 278         struct hns_roce_uar     uar;
 279         struct list_head        page_list;
 280         struct mutex            page_mutex;
 281 };
 282
 283 struct hns_roce_pd {
 284         struct ib_pd            ibpd;
 285         unsigned long           pdn;
 286 };
 287
 288 struct hns_roce_bitmap {
 289         /* Bitmap Traversal last a bit which is 1 */
 290         unsigned long           last;
 291         unsigned long           top;
 292         unsigned long           max;
 293         unsigned long           reserved_top;
 294         unsigned long           mask;
 295         spinlock_t              lock;
 296         unsigned long           *table;
 297 };
 298
 299 /* For Hardware Entry Memory */
 300 struct hns_roce_hem_table {
 301         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 302         u32             type;
 303         /* HEM array elment num */
 304         unsigned long   num_hem;
 305         /* HEM entry record obj total num */
 306         unsigned long   num_obj;
 307         /* Single obj size */
 308         unsigned long   obj_size;
 309         unsigned long   table_chunk_size;
 310         int             lowmem;
 311         struct mutex    mutex;
 312         struct hns_roce_hem **hem;
 313         u64             **bt_l1;
 314         dma_addr_t      *bt_l1_dma_addr;
 315         u64             **bt_l0;
 316         dma_addr_t      *bt_l0_dma_addr;
 317 };
 318
 319 struct hns_roce_buf_region {
 320         u32 offset; /* page offset */
 321         u32 count; /* page count */
 322         int hopnum; /* addressing hop num */
 323 };
 324
 325 #define HNS_ROCE_MAX_BT_REGION  3
 326 #define HNS_ROCE_MAX_BT_LEVEL   3
 327 struct hns_roce_hem_list {
 328         struct list_head root_bt;
 329         /* link all bt dma mem by hop config */
 330         struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
 331         struct list_head btm_bt; /* link all bottom bt in @mid_bt */
 332         dma_addr_t root_ba; /* pointer to the root ba table */
 333 };
 334
 335 struct hns_roce_buf_attr {
 336         struct {
 337                 size_t  size;  /* region size */
 338                 int     hopnum; /* multi-hop addressing hop num */
 339         } region[HNS_ROCE_MAX_BT_REGION];
 340         unsigned int region_count; /* valid region count */
 341         unsigned int page_shift;  /* buffer page shift */
 342         unsigned int user_access; /* umem access flag */
 343         bool mtt_only; /* only alloc buffer-required MTT memory */
 344 };
 345
 346 struct hns_roce_hem_cfg {
 347         dma_addr_t      root_ba; /* root BA table's address */
 348         bool            is_direct; /* addressing without BA table */
 349         unsigned int    ba_pg_shift; /* BA table page shift */
 350         unsigned int    buf_pg_shift; /* buffer page shift */
 351         unsigned int    buf_pg_count;  /* buffer page count */
 352         struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
 353         unsigned int    region_count;
 354 };
 355
 356 /* memory translate region */
 357 struct hns_roce_mtr {
 358         struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
 359         struct ib_umem          *umem; /* user space buffer */
 360         struct hns_roce_buf     *kmem; /* kernel space buffer */
 361         struct hns_roce_hem_cfg  hem_cfg; /* config for hardware addressing */
 362 };
 363
 364 struct hns_roce_mw {
 365         struct ib_mw            ibmw;
 366         u32                     pdn;
 367         u32                     rkey;
 368         int                     enabled; /* MW's active status */
 369         u32                     pbl_hop_num;
 370         u32                     pbl_ba_pg_sz;
 371         u32                     pbl_buf_pg_sz;
 372 };
 373
 374 /* Only support 4K page size for mr register */
 375 #define MR_SIZE_4K 0
 376
 377 struct hns_roce_mr {
 378         struct ib_mr            ibmr;
 379         u64                     iova; /* MR's virtual orignal addr */
 380         u64                     size; /* Address range of MR */
 381         u32                     key; /* Key of MR */
 382         u32                     pd;   /* PD num of MR */
 383         u32                     access; /* Access permission of MR */
 384         int                     enabled; /* MR's active status */
 385         int                     type;   /* MR's register type */
 386         u32                     pbl_hop_num;    /* multi-hop number */
 387         struct hns_roce_mtr     pbl_mtr;
 388         u32                     npages;
 389         dma_addr_t              *page_list;
 390 };
 391
 392 struct hns_roce_mr_table {
 393         struct hns_roce_bitmap          mtpt_bitmap;
 394         struct hns_roce_hem_table       mtpt_table;
 395 };
 396
 397 struct hns_roce_wq {
 398         u64             *wrid;     /* Work request ID */
 399         spinlock_t      lock;
 400         u32             wqe_cnt;  /* WQE num */
 401         u32             max_gs;
 402         u32             rsv_sge;
 403         int             offset;
 404         int             wqe_shift;      /* WQE size */
 405         u32             head;
 406         u32             tail;
 407         void __iomem    *db_reg_l;
 408 };
 409
 410 struct hns_roce_sge {
 411         unsigned int    sge_cnt;        /* SGE num */
 412         int             offset;
 413         int             sge_shift;      /* SGE size */
 414 };
 415
 416 struct hns_roce_buf_list {
 417         void            *buf;
 418         dma_addr_t      map;
 419 };
 420
 421 /*
 422  * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
 423  * dma address range.
 424  *
 425  * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
 426  *
 427  * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
 428  * the allocated size is smaller than the required size.
 429  */
 430 enum {
 431         HNS_ROCE_BUF_DIRECT = BIT(0),
 432         HNS_ROCE_BUF_NOSLEEP = BIT(1),
 433         HNS_ROCE_BUF_NOFAIL = BIT(2),
 434 };
 435
 436 struct hns_roce_buf {
 437         struct hns_roce_buf_list        *trunk_list;
 438         u32                             ntrunks;
 439         u32                             npages;
 440         unsigned int                    trunk_shift;
 441         unsigned int                    page_shift;
 442 };
 443
 444 struct hns_roce_db_pgdir {
 445         struct list_head        list;
 446         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 447         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 448         unsigned long           *bits[HNS_ROCE_DB_TYPE_COUNT];
 449         u32                     *page;
 450         dma_addr_t              db_dma;
 451 };
 452
 453 struct hns_roce_user_db_page {
 454         struct list_head        list;
 455         struct ib_umem          *umem;
 456         unsigned long           user_virt;
 457         refcount_t              refcount;
 458 };
 459
 460 struct hns_roce_db {
 461         u32             *db_record;
 462         union {
 463                 struct hns_roce_db_pgdir *pgdir;
 464                 struct hns_roce_user_db_page *user_page;
 465         } u;
 466         dma_addr_t      dma;
 467         void            *virt_addr;
 468         unsigned long   index;
 469         unsigned long   order;
 470 };
 471
 472 struct hns_roce_cq {
 473         struct ib_cq                    ib_cq;
 474         struct hns_roce_mtr             mtr;
 475         struct hns_roce_db              db;
 476         u32                             flags;
 477         spinlock_t                      lock;
 478         u32                             cq_depth;
 479         u32                             cons_index;
 480         u32                             *set_ci_db;
 481         void __iomem                    *cq_db_l;
 482         u16                             *tptr_addr;
 483         int                             arm_sn;
 484         int                             cqe_size;
 485         unsigned long                   cqn;
 486         u32                             vector;
 487         atomic_t                        refcount;
 488         struct completion               free;
 489         struct list_head                sq_list; /* all qps on this send cq */
 490         struct list_head                rq_list; /* all qps on this recv cq */
 491         int                             is_armed; /* cq is armed */
 492         struct list_head                node; /* all armed cqs are on a list */
 493 };
 494
 495 struct hns_roce_idx_que {
 496         struct hns_roce_mtr             mtr;
 497         int                             entry_shift;
 498         unsigned long                   *bitmap;
 499         u32                             head;
 500         u32                             tail;
 501 };
 502
 503 struct hns_roce_srq {
 504         struct ib_srq           ibsrq;
 505         unsigned long           srqn;
 506         u32                     wqe_cnt;
 507         int                     max_gs;
 508         u32                     rsv_sge;
 509         int                     wqe_shift;
 510         u32                     cqn;
 511         void __iomem            *db_reg_l;
 512
 513         atomic_t                refcount;
 514         struct completion       free;
 515
 516         struct hns_roce_mtr     buf_mtr;
 517
 518         u64                    *wrid;
 519         struct hns_roce_idx_que idx_que;
 520         spinlock_t              lock;
 521         struct mutex            mutex;
 522         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 523 };
 524
 525 struct hns_roce_uar_table {
 526         struct hns_roce_bitmap bitmap;
 527 };
 528
 529 struct hns_roce_bank {
 530         struct ida ida;
 531         u32 inuse; /* Number of IDs allocated */
 532         u32 min; /* Lowest ID to allocate.  */
 533         u32 max; /* Highest ID to allocate. */
 534         u32 next; /* Next ID to allocate. */
 535 };
 536
 537 struct hns_roce_qp_table {
 538         struct hns_roce_hem_table       qp_table;
 539         struct hns_roce_hem_table       irrl_table;
 540         struct hns_roce_hem_table       trrl_table;
 541         struct hns_roce_hem_table       sccc_table;
 542         struct mutex                    scc_mutex;
 543         struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
 544         spinlock_t bank_lock;
 545 };
 546
 547 struct hns_roce_cq_table {
 548         struct xarray                   array;
 549         struct hns_roce_hem_table       table;
 550         struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
 551         struct mutex                    bank_mutex;
 552 };
 553
 554 struct hns_roce_srq_table {
 555         struct hns_roce_bitmap          bitmap;
 556         struct xarray                   xa;
 557         struct hns_roce_hem_table       table;
 558 };
 559
 560 struct hns_roce_raq_table {
 561         struct hns_roce_buf_list        *e_raq_buf;
 562 };
 563
 564 struct hns_roce_av {
 565         u8 port;
 566         u8 gid_index;
 567         u8 stat_rate;
 568         u8 hop_limit;
 569         u32 flowlabel;
 570         u16 udp_sport;
 571         u8 sl;
 572         u8 tclass;
 573         u8 dgid[HNS_ROCE_GID_SIZE];
 574         u8 mac[ETH_ALEN];
 575         u16 vlan_id;
 576         u8 vlan_en;
 577 };
 578
 579 struct hns_roce_ah {
 580         struct ib_ah            ibah;
 581         struct hns_roce_av      av;
 582 };
 583
 584 struct hns_roce_cmd_context {
 585         struct completion       done;
 586         int                     result;
 587         int                     next;
 588         u64                     out_param;
 589         u16                     token;
 590 };
 591
 592 struct hns_roce_cmdq {
 593         struct dma_pool         *pool;
 594         struct mutex            hcr_mutex;
 595         struct semaphore        poll_sem;
 596         /*
 597          * Event mode: cmd register mutex protection,
 598          * ensure to not exceed max_cmds and user use limit region
 599          */
 600         struct semaphore        event_sem;
 601         int                     max_cmds;
 602         spinlock_t              context_lock;
 603         int                     free_head;
 604         struct hns_roce_cmd_context *context;
 605         /*
 606          * Result of get integer part
 607          * which max_comds compute according a power of 2
 608          */
 609         u16                     token_mask;
 610         /*
 611          * Process whether use event mode, init default non-zero
 612          * After the event queue of cmd event ready,
 613          * can switch into event mode
 614          * close device, switch into poll mode(non event mode)
 615          */
 616         u8                      use_events;
 617 };
 618
 619 struct hns_roce_cmd_mailbox {
 620         void                   *buf;
 621         dma_addr_t              dma;
 622 };
 623
 624 struct hns_roce_dev;
 625
 626 struct hns_roce_rinl_sge {
 627         void                    *addr;
 628         u32                     len;
 629 };
 630
 631 struct hns_roce_rinl_wqe {
 632         struct hns_roce_rinl_sge *sg_list;
 633         u32                      sge_cnt;
 634 };
 635
 636 struct hns_roce_rinl_buf {
 637         struct hns_roce_rinl_wqe *wqe_list;
 638         u32                      wqe_cnt;
 639 };
 640
 641 enum {
 642         HNS_ROCE_FLUSH_FLAG = 0,
 643 };
 644
 645 struct hns_roce_work {
 646         struct hns_roce_dev *hr_dev;
 647         struct work_struct work;
 648         int event_type;
 649         int sub_type;
 650         u32 queue_num;
 651 };
 652
 653 enum {
 654         HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5),
 655 };
 656
 657 struct hns_roce_qp {
 658         struct ib_qp            ibqp;
 659         struct hns_roce_wq      rq;
 660         struct hns_roce_db      rdb;
 661         struct hns_roce_db      sdb;
 662         unsigned long           en_flags;
 663         u32                     doorbell_qpn;
 664         enum ib_sig_type        sq_signal_bits;
 665         struct hns_roce_wq      sq;
 666
 667         struct hns_roce_mtr     mtr;
 668
 669         u32                     buff_size;
 670         struct mutex            mutex;
 671         u8                      port;
 672         u8                      phy_port;
 673         u8                      sl;
 674         u8                      resp_depth;
 675         u8                      state;
 676         u32                     access_flags;
 677         u32                     atomic_rd_en;
 678         u32                     pkey_index;
 679         u32                     qkey;
 680         void                    (*event)(struct hns_roce_qp *qp,
 681                                          enum hns_roce_event event_type);
 682         unsigned long           qpn;
 683
 684         atomic_t                refcount;
 685         struct completion       free;
 686
 687         struct hns_roce_sge     sge;
 688         u32                     next_sge;
 689         enum ib_mtu             path_mtu;
 690         u32                     max_inline_data;
 691
 692         /* 0: flush needed, 1: unneeded */
 693         unsigned long           flush_flag;
 694         struct hns_roce_work    flush_work;
 695         struct hns_roce_rinl_buf rq_inl_buf;
 696         struct list_head        node;           /* all qps are on a list */
 697         struct list_head        rq_node;        /* all recv qps are on a list */
 698         struct list_head        sq_node;        /* all send qps are on a list */
 699 };
 700
 701 struct hns_roce_ib_iboe {
 702         spinlock_t              lock;
 703         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 704         struct notifier_block   nb;
 705         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 706 };
 707
 708 enum {
 709         HNS_ROCE_EQ_STAT_INVALID  = 0,
 710         HNS_ROCE_EQ_STAT_VALID    = 2,
 711 };
 712
 713 struct hns_roce_ceqe {
 714         __le32  comp;
 715         __le32  rsv[15];
 716 };
 717
 718 struct hns_roce_aeqe {
 719         __le32 asyn;
 720         union {
 721                 struct {
 722                         __le32 num;
 723                         u32 rsv0;
 724                         u32 rsv1;
 725                 } queue_event;
 726
 727                 struct {
 728                         __le64  out_param;
 729                         __le16  token;
 730                         u8      status;
 731                         u8      rsv0;
 732                 } __packed cmd;
 733          } event;
 734         __le32 rsv[12];
 735 };
 736
 737 struct hns_roce_eq {
 738         struct hns_roce_dev             *hr_dev;
 739         void __iomem                    *doorbell;
 740
 741         int                             type_flag; /* Aeq:1 ceq:0 */
 742         int                             eqn;
 743         u32                             entries;
 744         u32                             log_entries;
 745         int                             eqe_size;
 746         int                             irq;
 747         int                             log_page_size;
 748         u32                             cons_index;
 749         struct hns_roce_buf_list        *buf_list;
 750         int                             over_ignore;
 751         int                             coalesce;
 752         int                             arm_st;
 753         int                             hop_num;
 754         struct hns_roce_mtr             mtr;
 755         u16                             eq_max_cnt;
 756         u32                             eq_period;
 757         int                             shift;
 758         int                             event_type;
 759         int                             sub_type;
 760 };
 761
 762 struct hns_roce_eq_table {
 763         struct hns_roce_eq      *eq;
 764         void __iomem            **eqc_base; /* only for hw v1 */
 765 };
 766
 767 struct hns_roce_caps {
 768         u64             fw_ver;
 769         u8              num_ports;
 770         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 771         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 772         int             local_ca_ack_delay;
 773         int             num_uars;
 774         u32             phy_num_uars;
 775         u32             max_sq_sg;
 776         u32             max_sq_inline;
 777         u32             max_rq_sg;
 778         u32             max_extend_sg;
 779         u32             num_qps;
 780         u32             reserved_qps;
 781         int             num_qpc_timer;
 782         int             num_cqc_timer;
 783         int             num_srqs;
 784         u32             max_wqes;
 785         u32             max_srq_wrs;
 786         u32             max_srq_sges;
 787         u32             max_sq_desc_sz;
 788         u32             max_rq_desc_sz;
 789         u32             max_srq_desc_sz;
 790         int             max_qp_init_rdma;
 791         int             max_qp_dest_rdma;
 792         u32             num_cqs;
 793         u32             max_cqes;
 794         u32             min_cqes;
 795         u32             min_wqes;
 796         u32             reserved_cqs;
 797         int             reserved_srqs;
 798         int             num_aeq_vectors;
 799         int             num_comp_vectors;
 800         int             num_other_vectors;
 801         u32             num_mtpts;
 802         u32             num_mtt_segs;
 803         u32             num_cqe_segs;
 804         u32             num_srqwqe_segs;
 805         u32             num_idx_segs;
 806         int             reserved_mrws;
 807         int             reserved_uars;
 808         int             num_pds;
 809         int             reserved_pds;
 810         u32             mtt_entry_sz;
 811         u32             cqe_sz;
 812         u32             page_size_cap;
 813         u32             reserved_lkey;
 814         int             mtpt_entry_sz;
 815         int             qpc_sz;
 816         int             irrl_entry_sz;
 817         int             trrl_entry_sz;
 818         int             cqc_entry_sz;
 819         int             sccc_sz;
 820         int             qpc_timer_entry_sz;
 821         int             cqc_timer_entry_sz;
 822         int             srqc_entry_sz;
 823         int             idx_entry_sz;
 824         u32             pbl_ba_pg_sz;
 825         u32             pbl_buf_pg_sz;
 826         u32             pbl_hop_num;
 827         int             aeqe_depth;
 828         int             ceqe_depth;
 829         u32             aeqe_size;
 830         u32             ceqe_size;
 831         enum ib_mtu     max_mtu;
 832         u32             qpc_bt_num;
 833         u32             qpc_timer_bt_num;
 834         u32             srqc_bt_num;
 835         u32             cqc_bt_num;
 836         u32             cqc_timer_bt_num;
 837         u32             mpt_bt_num;
 838         u32             sccc_bt_num;
 839         u32             gmv_bt_num;
 840         u32             qpc_ba_pg_sz;
 841         u32             qpc_buf_pg_sz;
 842         u32             qpc_hop_num;
 843         u32             srqc_ba_pg_sz;
 844         u32             srqc_buf_pg_sz;
 845         u32             srqc_hop_num;
 846         u32             cqc_ba_pg_sz;
 847         u32             cqc_buf_pg_sz;
 848         u32             cqc_hop_num;
 849         u32             mpt_ba_pg_sz;
 850         u32             mpt_buf_pg_sz;
 851         u32             mpt_hop_num;
 852         u32             mtt_ba_pg_sz;
 853         u32             mtt_buf_pg_sz;
 854         u32             mtt_hop_num;
 855         u32             wqe_sq_hop_num;
 856         u32             wqe_sge_hop_num;
 857         u32             wqe_rq_hop_num;
 858         u32             sccc_ba_pg_sz;
 859         u32             sccc_buf_pg_sz;
 860         u32             sccc_hop_num;
 861         u32             qpc_timer_ba_pg_sz;
 862         u32             qpc_timer_buf_pg_sz;
 863         u32             qpc_timer_hop_num;
 864         u32             cqc_timer_ba_pg_sz;
 865         u32             cqc_timer_buf_pg_sz;
 866         u32             cqc_timer_hop_num;
 867         u32             cqe_ba_pg_sz;   /* page_size = 4K*(2^cqe_ba_pg_sz) */
 868         u32             cqe_buf_pg_sz;
 869         u32             cqe_hop_num;
 870         u32             srqwqe_ba_pg_sz;
 871         u32             srqwqe_buf_pg_sz;
 872         u32             srqwqe_hop_num;
 873         u32             idx_ba_pg_sz;
 874         u32             idx_buf_pg_sz;
 875         u32             idx_hop_num;
 876         u32             eqe_ba_pg_sz;
 877         u32             eqe_buf_pg_sz;
 878         u32             eqe_hop_num;
 879         u32             gmv_entry_num;
 880         u32             gmv_entry_sz;
 881         u32             gmv_ba_pg_sz;
 882         u32             gmv_buf_pg_sz;
 883         u32             gmv_hop_num;
 884         u32             sl_num;
 885         u32             tsq_buf_pg_sz;
 886         u32             tpq_buf_pg_sz;
 887         u32             chunk_sz;       /* chunk size in non multihop mode */
 888         u64             flags;
 889         u16             default_ceq_max_cnt;
 890         u16             default_ceq_period;
 891         u16             default_aeq_max_cnt;
 892         u16             default_aeq_period;
 893         u16             default_aeq_arm_st;
 894         u16             default_ceq_arm_st;
 895 };
 896
 897 struct hns_roce_dfx_hw {
 898         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 899                               int *buffer);
 900 };
 901
 902 enum hns_roce_device_state {
 903         HNS_ROCE_DEVICE_STATE_INITED,
 904         HNS_ROCE_DEVICE_STATE_RST_DOWN,
 905         HNS_ROCE_DEVICE_STATE_UNINIT,
 906 };
 907
 908 struct hns_roce_hw {
 909         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 910         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 911         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 912         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 913         int (*hw_init)(struct hns_roce_dev *hr_dev);
 914         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 915         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 916                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 917                          u16 token, int event);
 918         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned int timeout);
 919         int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
 920         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 921                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 922         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 923         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 924                         enum ib_mtu mtu);
 925         int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 926                           struct hns_roce_mr *mr, unsigned long mtpt_idx);
 927         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 928                                 struct hns_roce_mr *mr, int flags,
 929                                 void *mb_buf);
 930         int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 931                                struct hns_roce_mr *mr);
 932         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 933         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 934                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 935                           dma_addr_t dma_handle);
 936         int (*set_hem)(struct hns_roce_dev *hr_dev,
 937                        struct hns_roce_hem_table *table, int obj, int step_idx);
 938         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 939                          struct hns_roce_hem_table *table, int obj,
 940                          int step_idx);
 941         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 942                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 943         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 944                          int attr_mask, enum ib_qp_state cur_state,
 945                          enum ib_qp_state new_state);
 946         int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
 947         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 948                          struct hns_roce_qp *hr_qp);
 949         int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 950                          const struct ib_send_wr **bad_wr);
 951         int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
 952                          const struct ib_recv_wr **bad_recv_wr);
 953         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 954         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 955         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 956                         struct ib_udata *udata);
 957         int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 958         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 959         int (*init_eq)(struct hns_roce_dev *hr_dev);
 960         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 961         int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
 962         int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
 963                        enum ib_srq_attr_mask srq_attr_mask,
 964                        struct ib_udata *udata);
 965         int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
 966         int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
 967                              const struct ib_recv_wr **bad_wr);
 968         const struct ib_device_ops *hns_roce_dev_ops;
 969         const struct ib_device_ops *hns_roce_dev_srq_ops;
 970 };
 971
 972 struct hns_roce_dev {
 973         struct ib_device        ib_dev;
 974         struct platform_device  *pdev;
 975         struct pci_dev          *pci_dev;
 976         struct device           *dev;
 977         struct hns_roce_uar     priv_uar;
 978         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 979         spinlock_t              sm_lock;
 980         spinlock_t              bt_cmd_lock;
 981         bool                    active;
 982         bool                    is_reset;
 983         bool                    dis_db;
 984         unsigned long           reset_cnt;
 985         struct hns_roce_ib_iboe iboe;
 986         enum hns_roce_device_state state;
 987         struct list_head        qp_list; /* list of all qps on this dev */
 988         spinlock_t              qp_list_lock; /* protect qp_list */
 989
 990         struct list_head        pgdir_list;
 991         struct mutex            pgdir_mutex;
 992         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
 993         u8 __iomem              *reg_base;
 994         void __iomem            *mem_base;
 995         struct hns_roce_caps    caps;
 996         struct xarray           qp_table_xa;
 997
 998         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
 999         u64                     sys_image_guid;
1000         u32                     vendor_id;
1001         u32                     vendor_part_id;
1002         u32                     hw_rev;
1003         void __iomem            *priv_addr;
1004
1005         struct hns_roce_cmdq    cmd;
1006         struct hns_roce_bitmap    pd_bitmap;
1007         struct hns_roce_uar_table uar_table;
1008         struct hns_roce_mr_table  mr_table;
1009         struct hns_roce_cq_table  cq_table;
1010         struct hns_roce_srq_table srq_table;
1011         struct hns_roce_qp_table  qp_table;
1012         struct hns_roce_eq_table  eq_table;
1013         struct hns_roce_hem_table  qpc_timer_table;
1014         struct hns_roce_hem_table  cqc_timer_table;
1015         /* GMV is the memory area that the driver allocates for the hardware
1016          * to store SGID, SMAC and VLAN information.
1017          */
1018         struct hns_roce_hem_table  gmv_table;
1019
1020         int                     cmd_mod;
1021         int                     loop_idc;
1022         u32                     sdb_offset;
1023         u32                     odb_offset;
1024         dma_addr_t              tptr_dma_addr;  /* only for hw v1 */
1025         u32                     tptr_size;      /* only for hw v1 */
1026         const struct hns_roce_hw *hw;
1027         void                    *priv;
1028         struct workqueue_struct *irq_workq;
1029         const struct hns_roce_dfx_hw *dfx;
1030 };
1031
1032 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1033 {
1034         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1035 }
1036
1037 static inline struct hns_roce_ucontext
1038                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
1039 {
1040         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1041 }
1042
1043 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1044 {
1045         return container_of(ibpd, struct hns_roce_pd, ibpd);
1046 }
1047
1048 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1049 {
1050         return container_of(ibah, struct hns_roce_ah, ibah);
1051 }
1052
1053 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1054 {
1055         return container_of(ibmr, struct hns_roce_mr, ibmr);
1056 }
1057
1058 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1059 {
1060         return container_of(ibmw, struct hns_roce_mw, ibmw);
1061 }
1062
1063 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1064 {
1065         return container_of(ibqp, struct hns_roce_qp, ibqp);
1066 }
1067
1068 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1069 {
1070         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1071 }
1072
1073 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1074 {
1075         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1076 }
1077
1078 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1079 {
1080         __raw_writeq(*(u64 *) val, dest);
1081 }
1082
1083 static inline struct hns_roce_qp
1084         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1085 {
1086         return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1087 }
1088
1089 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1090                                         unsigned int offset)
1091 {
1092         return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1093                         (offset & ((1 << buf->trunk_shift) - 1));
1094 }
1095
1096 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1097 {
1098         unsigned int offset = idx << buf->page_shift;
1099
1100         return buf->trunk_list[offset >> buf->trunk_shift].map +
1101                         (offset & ((1 << buf->trunk_shift) - 1));
1102 }
1103
1104 #define hr_hw_page_align(x)             ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1105
1106 static inline u64 to_hr_hw_page_addr(u64 addr)
1107 {
1108         return addr >> HNS_HW_PAGE_SHIFT;
1109 }
1110
1111 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1112 {
1113         return page_shift - HNS_HW_PAGE_SHIFT;
1114 }
1115
1116 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1117 {
1118         if (count > 0)
1119                 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1120
1121         return 0;
1122 }
1123
1124 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1125 {
1126         return hr_hw_page_align(count << buf_shift);
1127 }
1128
1129 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1130 {
1131         return hr_hw_page_align(count << buf_shift) >> buf_shift;
1132 }
1133
1134 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1135 {
1136         if (!count)
1137                 return 0;
1138
1139         return ilog2(to_hr_hem_entries_count(count, buf_shift));
1140 }
1141
1142 #define DSCP_SHIFT 2
1143
1144 static inline u8 get_tclass(const struct ib_global_route *grh)
1145 {
1146         return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1147                grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1148 }
1149
1150 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1151 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1152 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1153 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1154
1155 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1156 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1157 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1158                         u64 out_param);
1159 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1160 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1161
1162 /* hns roce hw need current block and next block addr from mtt */
1163 #define MTT_MIN_COUNT    2
1164 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1165                       int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1166 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1167                         struct hns_roce_buf_attr *buf_attr,
1168                         unsigned int page_shift, struct ib_udata *udata,
1169                         unsigned long user_addr);
1170 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1171                           struct hns_roce_mtr *mtr);
1172 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1173                      dma_addr_t *pages, unsigned int page_cnt);
1174
1175 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1176 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1177 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1178 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1179 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1180
1181 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1182 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1183 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1184 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1185 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1186 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1187
1188 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1189 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1190                          int rr);
1191 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1192                          u32 reserved_bot, u32 resetrved_top);
1193 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1194 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1195 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1196                                 int align, unsigned long *obj);
1197 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1198                                 unsigned long obj, int cnt,
1199                                 int rr);
1200
1201 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1202                        struct ib_udata *udata);
1203 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1204 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1205 {
1206         return 0;
1207 }
1208
1209 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1210 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1211
1212 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1213 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1214                                    u64 virt_addr, int access_flags,
1215                                    struct ib_udata *udata);
1216 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1217                                      u64 length, u64 virt_addr,
1218                                      int mr_access_flags, struct ib_pd *pd,
1219                                      struct ib_udata *udata);
1220 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1221                                 u32 max_num_sg);
1222 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1223                        unsigned int *sg_offset);
1224 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1225 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1226                             struct hns_roce_cmd_mailbox *mailbox,
1227                             unsigned long mpt_index);
1228 unsigned long key_to_hw_index(u32 key);
1229
1230 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1231 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1232
1233 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1234 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1235                                         u32 page_shift, u32 flags);
1236
1237 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1238                            int buf_cnt, int start, struct hns_roce_buf *buf);
1239 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1240                            int buf_cnt, int start, struct ib_umem *umem,
1241                            unsigned int page_shift);
1242
1243 int hns_roce_create_srq(struct ib_srq *srq,
1244                         struct ib_srq_init_attr *srq_init_attr,
1245                         struct ib_udata *udata);
1246 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1247                         enum ib_srq_attr_mask srq_attr_mask,
1248                         struct ib_udata *udata);
1249 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1250
1251 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1252                                  struct ib_qp_init_attr *init_attr,
1253                                  struct ib_udata *udata);
1254 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1255                        int attr_mask, struct ib_udata *udata);
1256 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1257 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1258 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1259 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1260 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1261                           struct ib_cq *ib_cq);
1262 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1263 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1264                        struct hns_roce_cq *recv_cq);
1265 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1266                          struct hns_roce_cq *recv_cq);
1267 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1268 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1269                          struct ib_udata *udata);
1270 __be32 send_ieth(const struct ib_send_wr *wr);
1271 int to_hr_qp_type(int qp_type);
1272
1273 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1274                        struct ib_udata *udata);
1275
1276 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1277 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1278                          struct ib_udata *udata, unsigned long virt,
1279                          struct hns_roce_db *db);
1280 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1281                             struct hns_roce_db *db);
1282 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1283                       int order);
1284 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1285
1286 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1287 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1288 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1289 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1290 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1291 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1292 int hns_roce_init(struct hns_roce_dev *hr_dev);
1293 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1294 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1295                                struct ib_cq *ib_cq);
1296 #endif /* _HNS_ROCE_DEVICE_H */