2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
39 #define DRV_NAME "hns_roce"
41 #define PCI_REVISION_ID_HIP08 0x21
42 #define PCI_REVISION_ID_HIP09 0x30
44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
50 #define HNS_ROCE_BA_SIZE (32 * 4096)
54 /* Hardware specification only for v1 engine */
55 #define HNS_ROCE_MIN_CQE_NUM 0x40
56 #define HNS_ROCE_MIN_WQE_NUM 0x20
57 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
59 /* Hardware specification only for v1 engine */
60 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
61 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
63 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
64 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
65 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
66 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
67 #define HNS_ROCE_MIN_CQE_CNT 16
69 #define HNS_ROCE_RESERVED_SGE 1
71 #define HNS_ROCE_MAX_IRQ_NUM 128
73 #define HNS_ROCE_SGE_IN_WQE 2
74 #define HNS_ROCE_SGE_SHIFT 4
79 #define HNS_ROCE_CEQ 0
80 #define HNS_ROCE_AEQ 1
82 #define HNS_ROCE_CEQE_SIZE 0x4
83 #define HNS_ROCE_AEQE_SIZE 0x10
85 #define HNS_ROCE_V3_EQE_SIZE 0x40
87 #define HNS_ROCE_V2_CQE_SIZE 32
88 #define HNS_ROCE_V3_CQE_SIZE 64
90 #define HNS_ROCE_V2_QPC_SZ 256
91 #define HNS_ROCE_V3_QPC_SZ 512
93 #define HNS_ROCE_MAX_PORTS 6
94 #define HNS_ROCE_GID_SIZE 16
95 #define HNS_ROCE_SGE_SIZE 16
96 #define HNS_ROCE_DWQE_SIZE 65536
98 #define HNS_ROCE_HOP_NUM_0 0xff
100 #define BITMAP_NO_RR 0
103 #define MR_TYPE_MR 0x00
104 #define MR_TYPE_FRMR 0x01
105 #define MR_TYPE_DMA 0x03
107 #define HNS_ROCE_FRMR_MAX_PA 512
109 #define PKEY_ID 0xffff
111 #define NODE_DESC_SIZE 64
112 #define DB_REG_OFFSET 0x1000
114 /* Configure to HW for PAGE_SIZE larger than 4KB */
115 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
117 #define PAGES_SHIFT_8 8
118 #define PAGES_SHIFT_16 16
119 #define PAGES_SHIFT_24 24
120 #define PAGES_SHIFT_32 32
122 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
123 #define SRQ_DB_REG 0x230
125 #define HNS_ROCE_QP_BANK_NUM 8
126 #define HNS_ROCE_CQ_BANK_NUM 4
128 #define CQ_BANKID_SHIFT 2
130 /* The chip implementation of the consumer index is calculated
131 * according to twice the actual EQ depth
133 #define EQ_DEPTH_COEFF 2
143 enum hns_roce_qp_state {
144 HNS_ROCE_QP_STATE_RST,
145 HNS_ROCE_QP_STATE_INIT,
146 HNS_ROCE_QP_STATE_RTR,
147 HNS_ROCE_QP_STATE_RTS,
148 HNS_ROCE_QP_STATE_SQD,
149 HNS_ROCE_QP_STATE_ERR,
150 HNS_ROCE_QP_NUM_STATE,
153 enum hns_roce_event {
154 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
155 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
156 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
157 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
158 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
159 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
160 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
161 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
162 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
163 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
164 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
165 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
166 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
167 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
168 /* 0x10 and 0x11 is unused in currently application case */
169 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
170 HNS_ROCE_EVENT_TYPE_MB = 0x13,
171 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
172 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
173 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
176 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
179 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
180 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
181 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
182 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
183 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
184 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
185 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
186 HNS_ROCE_CAP_FLAG_MW = BIT(7),
187 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
188 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
189 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
190 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
191 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
194 #define HNS_ROCE_DB_TYPE_COUNT 2
195 #define HNS_ROCE_DB_UNIT_SIZE 4
198 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
201 enum hns_roce_reset_stage {
202 HNS_ROCE_STATE_NON_RST,
203 HNS_ROCE_STATE_RST_BEF_DOWN,
204 HNS_ROCE_STATE_RST_DOWN,
205 HNS_ROCE_STATE_RST_UNINIT,
206 HNS_ROCE_STATE_RST_INIT,
207 HNS_ROCE_STATE_RST_INITED,
210 enum hns_roce_instance_state {
211 HNS_ROCE_STATE_NON_INIT,
213 HNS_ROCE_STATE_INITED,
214 HNS_ROCE_STATE_UNINIT,
218 HNS_ROCE_RST_DIRECT_RETURN = 0,
221 #define HNS_ROCE_CMD_SUCCESS 1
223 /* The minimum page size is 4K for hardware */
224 #define HNS_HW_PAGE_SHIFT 12
225 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
227 struct hns_roce_uar {
230 unsigned long logic_idx;
233 struct hns_roce_ucontext {
234 struct ib_ucontext ibucontext;
235 struct hns_roce_uar uar;
236 struct list_head page_list;
237 struct mutex page_mutex;
245 struct hns_roce_xrcd {
246 struct ib_xrcd ibxrcd;
250 struct hns_roce_bitmap {
251 /* Bitmap Traversal last a bit which is 1 */
255 unsigned long reserved_top;
258 unsigned long *table;
261 /* For Hardware Entry Memory */
262 struct hns_roce_hem_table {
263 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
265 /* HEM array elment num */
266 unsigned long num_hem;
267 /* HEM entry record obj total num */
268 unsigned long num_obj;
269 /* Single obj size */
270 unsigned long obj_size;
271 unsigned long table_chunk_size;
274 struct hns_roce_hem **hem;
276 dma_addr_t *bt_l1_dma_addr;
278 dma_addr_t *bt_l0_dma_addr;
281 struct hns_roce_buf_region {
282 u32 offset; /* page offset */
283 u32 count; /* page count */
284 int hopnum; /* addressing hop num */
287 #define HNS_ROCE_MAX_BT_REGION 3
288 #define HNS_ROCE_MAX_BT_LEVEL 3
289 struct hns_roce_hem_list {
290 struct list_head root_bt;
291 /* link all bt dma mem by hop config */
292 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
293 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
294 dma_addr_t root_ba; /* pointer to the root ba table */
297 struct hns_roce_buf_attr {
299 size_t size; /* region size */
300 int hopnum; /* multi-hop addressing hop num */
301 } region[HNS_ROCE_MAX_BT_REGION];
302 unsigned int region_count; /* valid region count */
303 unsigned int page_shift; /* buffer page shift */
304 unsigned int user_access; /* umem access flag */
305 bool mtt_only; /* only alloc buffer-required MTT memory */
308 struct hns_roce_hem_cfg {
309 dma_addr_t root_ba; /* root BA table's address */
310 bool is_direct; /* addressing without BA table */
311 unsigned int ba_pg_shift; /* BA table page shift */
312 unsigned int buf_pg_shift; /* buffer page shift */
313 unsigned int buf_pg_count; /* buffer page count */
314 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
315 unsigned int region_count;
318 /* memory translate region */
319 struct hns_roce_mtr {
320 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
321 struct ib_umem *umem; /* user space buffer */
322 struct hns_roce_buf *kmem; /* kernel space buffer */
323 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
330 int enabled; /* MW's active status */
336 /* Only support 4K page size for mr register */
341 u64 iova; /* MR's virtual orignal addr */
342 u64 size; /* Address range of MR */
343 u32 key; /* Key of MR */
344 u32 pd; /* PD num of MR */
345 u32 access; /* Access permission of MR */
346 int enabled; /* MR's active status */
347 int type; /* MR's register type */
348 u32 pbl_hop_num; /* multi-hop number */
349 struct hns_roce_mtr pbl_mtr;
351 dma_addr_t *page_list;
354 struct hns_roce_mr_table {
355 struct hns_roce_bitmap mtpt_bitmap;
356 struct hns_roce_hem_table mtpt_table;
360 u64 *wrid; /* Work request ID */
362 u32 wqe_cnt; /* WQE num */
366 int wqe_shift; /* WQE size */
369 void __iomem *db_reg;
372 struct hns_roce_sge {
373 unsigned int sge_cnt; /* SGE num */
375 int sge_shift; /* SGE size */
378 struct hns_roce_buf_list {
384 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
387 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
389 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
390 * the allocated size is smaller than the required size.
393 HNS_ROCE_BUF_DIRECT = BIT(0),
394 HNS_ROCE_BUF_NOSLEEP = BIT(1),
395 HNS_ROCE_BUF_NOFAIL = BIT(2),
398 struct hns_roce_buf {
399 struct hns_roce_buf_list *trunk_list;
402 unsigned int trunk_shift;
403 unsigned int page_shift;
406 struct hns_roce_db_pgdir {
407 struct list_head list;
408 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
409 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
410 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
415 struct hns_roce_user_db_page {
416 struct list_head list;
417 struct ib_umem *umem;
418 unsigned long user_virt;
425 struct hns_roce_db_pgdir *pgdir;
426 struct hns_roce_user_db_page *user_page;
436 struct hns_roce_mtr mtr;
437 struct hns_roce_db db;
443 void __iomem *db_reg;
450 struct completion free;
451 struct list_head sq_list; /* all qps on this send cq */
452 struct list_head rq_list; /* all qps on this recv cq */
453 int is_armed; /* cq is armed */
454 struct list_head node; /* all armed cqs are on a list */
457 struct hns_roce_idx_que {
458 struct hns_roce_mtr mtr;
460 unsigned long *bitmap;
465 struct hns_roce_srq {
474 void __iomem *db_reg;
477 struct completion free;
479 struct hns_roce_mtr buf_mtr;
482 struct hns_roce_idx_que idx_que;
485 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
488 struct hns_roce_uar_table {
489 struct hns_roce_bitmap bitmap;
492 struct hns_roce_bank {
494 u32 inuse; /* Number of IDs allocated */
495 u32 min; /* Lowest ID to allocate. */
496 u32 max; /* Highest ID to allocate. */
497 u32 next; /* Next ID to allocate. */
500 struct hns_roce_qp_table {
501 struct hns_roce_hem_table qp_table;
502 struct hns_roce_hem_table irrl_table;
503 struct hns_roce_hem_table trrl_table;
504 struct hns_roce_hem_table sccc_table;
505 struct mutex scc_mutex;
506 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
507 struct mutex bank_mutex;
510 struct hns_roce_cq_table {
512 struct hns_roce_hem_table table;
513 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
514 struct mutex bank_mutex;
517 struct hns_roce_srq_table {
518 struct hns_roce_bitmap bitmap;
520 struct hns_roce_hem_table table;
523 struct hns_roce_raq_table {
524 struct hns_roce_buf_list *e_raq_buf;
536 u8 dgid[HNS_ROCE_GID_SIZE];
544 struct hns_roce_av av;
547 struct hns_roce_cmd_context {
548 struct completion done;
556 struct hns_roce_cmdq {
557 struct dma_pool *pool;
558 struct mutex hcr_mutex;
559 struct semaphore poll_sem;
561 * Event mode: cmd register mutex protection,
562 * ensure to not exceed max_cmds and user use limit region
564 struct semaphore event_sem;
566 spinlock_t context_lock;
568 struct hns_roce_cmd_context *context;
570 * Process whether use event mode, init default non-zero
571 * After the event queue of cmd event ready,
572 * can switch into event mode
573 * close device, switch into poll mode(non event mode)
578 struct hns_roce_cmd_mailbox {
585 struct hns_roce_rinl_sge {
590 struct hns_roce_rinl_wqe {
591 struct hns_roce_rinl_sge *sg_list;
595 struct hns_roce_rinl_buf {
596 struct hns_roce_rinl_wqe *wqe_list;
601 HNS_ROCE_FLUSH_FLAG = 0,
604 struct hns_roce_work {
605 struct hns_roce_dev *hr_dev;
606 struct work_struct work;
613 HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5),
618 struct hns_roce_wq rq;
619 struct hns_roce_db rdb;
620 struct hns_roce_db sdb;
621 unsigned long en_flags;
623 enum ib_sig_type sq_signal_bits;
624 struct hns_roce_wq sq;
626 struct hns_roce_mtr mtr;
639 void (*event)(struct hns_roce_qp *qp,
640 enum hns_roce_event event_type);
646 struct completion free;
648 struct hns_roce_sge sge;
650 enum ib_mtu path_mtu;
653 /* 0: flush needed, 1: unneeded */
654 unsigned long flush_flag;
655 struct hns_roce_work flush_work;
656 struct hns_roce_rinl_buf rq_inl_buf;
657 struct list_head node; /* all qps are on a list */
658 struct list_head rq_node; /* all recv qps are on a list */
659 struct list_head sq_node; /* all send qps are on a list */
662 struct hns_roce_ib_iboe {
664 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
665 struct notifier_block nb;
666 u8 phy_port[HNS_ROCE_MAX_PORTS];
670 HNS_ROCE_EQ_STAT_INVALID = 0,
671 HNS_ROCE_EQ_STAT_VALID = 2,
674 struct hns_roce_ceqe {
679 struct hns_roce_aeqe {
699 struct hns_roce_dev *hr_dev;
700 void __iomem *db_reg;
702 int type_flag; /* Aeq:1 ceq:0 */
710 struct hns_roce_buf_list *buf_list;
715 struct hns_roce_mtr mtr;
723 struct hns_roce_eq_table {
724 struct hns_roce_eq *eq;
725 void __iomem **eqc_base; /* only for hw v1 */
735 struct hns_roce_caps {
738 int gid_table_len[HNS_ROCE_MAX_PORTS];
739 int pkey_table_len[HNS_ROCE_MAX_PORTS];
740 int local_ca_ack_delay;
758 int max_qp_init_rdma;
759 int max_qp_dest_rdma;
767 int num_comp_vectors;
768 int num_other_vectors;
789 int qpc_timer_entry_sz;
790 int cqc_timer_entry_sz;
802 u32 qpc_timer_bt_num;
805 u32 cqc_timer_bt_num;
833 u32 qpc_timer_ba_pg_sz;
834 u32 qpc_timer_buf_pg_sz;
835 u32 qpc_timer_hop_num;
836 u32 cqc_timer_ba_pg_sz;
837 u32 cqc_timer_buf_pg_sz;
838 u32 cqc_timer_hop_num;
839 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
843 u32 srqwqe_buf_pg_sz;
859 u32 chunk_sz; /* chunk size in non multihop mode */
861 u16 default_ceq_max_cnt;
862 u16 default_ceq_period;
863 u16 default_aeq_max_cnt;
864 u16 default_aeq_period;
865 u16 default_aeq_arm_st;
866 u16 default_ceq_arm_st;
867 enum cong_type cong_type;
870 struct hns_roce_dfx_hw {
871 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
875 enum hns_roce_device_state {
876 HNS_ROCE_DEVICE_STATE_INITED,
877 HNS_ROCE_DEVICE_STATE_RST_DOWN,
878 HNS_ROCE_DEVICE_STATE_UNINIT,
882 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
883 int (*cmq_init)(struct hns_roce_dev *hr_dev);
884 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
885 int (*hw_profile)(struct hns_roce_dev *hr_dev);
886 int (*hw_init)(struct hns_roce_dev *hr_dev);
887 void (*hw_exit)(struct hns_roce_dev *hr_dev);
888 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
889 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
890 u16 token, int event);
891 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev,
892 unsigned int timeout);
893 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
894 int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index,
895 const union ib_gid *gid, const struct ib_gid_attr *attr);
896 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
897 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
899 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
900 struct hns_roce_mr *mr, unsigned long mtpt_idx);
901 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
902 struct hns_roce_mr *mr, int flags,
904 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
905 struct hns_roce_mr *mr);
906 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
907 void (*write_cqc)(struct hns_roce_dev *hr_dev,
908 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
909 dma_addr_t dma_handle);
910 int (*set_hem)(struct hns_roce_dev *hr_dev,
911 struct hns_roce_hem_table *table, int obj, int step_idx);
912 int (*clear_hem)(struct hns_roce_dev *hr_dev,
913 struct hns_roce_hem_table *table, int obj,
915 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
916 int attr_mask, enum ib_qp_state cur_state,
917 enum ib_qp_state new_state);
918 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
919 struct hns_roce_qp *hr_qp);
920 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
921 struct ib_udata *udata);
922 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
923 int (*init_eq)(struct hns_roce_dev *hr_dev);
924 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
925 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
926 const struct ib_device_ops *hns_roce_dev_ops;
927 const struct ib_device_ops *hns_roce_dev_srq_ops;
930 struct hns_roce_dev {
931 struct ib_device ib_dev;
932 struct platform_device *pdev;
933 struct pci_dev *pci_dev;
935 struct hns_roce_uar priv_uar;
936 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
938 spinlock_t bt_cmd_lock;
942 unsigned long reset_cnt;
943 struct hns_roce_ib_iboe iboe;
944 enum hns_roce_device_state state;
945 struct list_head qp_list; /* list of all qps on this dev */
946 spinlock_t qp_list_lock; /* protect qp_list */
947 struct list_head dip_list; /* list of all dest ips on this dev */
948 spinlock_t dip_list_lock; /* protect dip_list */
950 struct list_head pgdir_list;
951 struct mutex pgdir_mutex;
952 int irq[HNS_ROCE_MAX_IRQ_NUM];
953 u8 __iomem *reg_base;
954 void __iomem *mem_base;
955 struct hns_roce_caps caps;
956 struct xarray qp_table_xa;
958 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
963 void __iomem *priv_addr;
965 struct hns_roce_cmdq cmd;
966 struct hns_roce_bitmap pd_bitmap;
967 struct hns_roce_bitmap xrcd_bitmap;
968 struct hns_roce_uar_table uar_table;
969 struct hns_roce_mr_table mr_table;
970 struct hns_roce_cq_table cq_table;
971 struct hns_roce_srq_table srq_table;
972 struct hns_roce_qp_table qp_table;
973 struct hns_roce_eq_table eq_table;
974 struct hns_roce_hem_table qpc_timer_table;
975 struct hns_roce_hem_table cqc_timer_table;
976 /* GMV is the memory area that the driver allocates for the hardware
977 * to store SGID, SMAC and VLAN information.
979 struct hns_roce_hem_table gmv_table;
985 dma_addr_t tptr_dma_addr; /* only for hw v1 */
986 u32 tptr_size; /* only for hw v1 */
987 const struct hns_roce_hw *hw;
989 struct workqueue_struct *irq_workq;
990 const struct hns_roce_dfx_hw *dfx;
993 u32 cong_algo_tmpl_id;
996 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
998 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1001 static inline struct hns_roce_ucontext
1002 *to_hr_ucontext(struct ib_ucontext *ibucontext)
1004 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1007 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1009 return container_of(ibpd, struct hns_roce_pd, ibpd);
1012 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
1014 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
1017 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1019 return container_of(ibah, struct hns_roce_ah, ibah);
1022 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1024 return container_of(ibmr, struct hns_roce_mr, ibmr);
1027 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1029 return container_of(ibmw, struct hns_roce_mw, ibmw);
1032 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1034 return container_of(ibqp, struct hns_roce_qp, ibqp);
1037 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1039 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1042 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1044 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1047 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1049 writeq(*(u64 *)val, dest);
1052 static inline struct hns_roce_qp
1053 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1055 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1058 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1059 unsigned int offset)
1061 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1062 (offset & ((1 << buf->trunk_shift) - 1));
1065 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1067 unsigned int offset = idx << buf->page_shift;
1069 return buf->trunk_list[offset >> buf->trunk_shift].map +
1070 (offset & ((1 << buf->trunk_shift) - 1));
1073 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1075 static inline u64 to_hr_hw_page_addr(u64 addr)
1077 return addr >> HNS_HW_PAGE_SHIFT;
1080 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1082 return page_shift - HNS_HW_PAGE_SHIFT;
1085 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1088 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1093 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1095 return hr_hw_page_align(count << buf_shift);
1098 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1100 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1103 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1108 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1111 #define DSCP_SHIFT 2
1113 static inline u8 get_tclass(const struct ib_global_route *grh)
1115 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1116 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1119 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1120 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1121 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1122 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1124 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1125 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1126 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1128 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1129 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1131 /* hns roce hw need current block and next block addr from mtt */
1132 #define MTT_MIN_COUNT 2
1133 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1134 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1135 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1136 struct hns_roce_buf_attr *buf_attr,
1137 unsigned int page_shift, struct ib_udata *udata,
1138 unsigned long user_addr);
1139 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1140 struct hns_roce_mtr *mtr);
1141 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1142 dma_addr_t *pages, unsigned int page_cnt);
1144 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1145 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1146 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1147 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1148 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1149 int hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1151 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1152 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1153 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1154 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1155 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1156 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1157 void hns_roce_cleanup_xrcd_table(struct hns_roce_dev *hr_dev);
1159 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1160 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1162 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1163 u32 reserved_bot, u32 resetrved_top);
1164 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1165 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1166 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1167 int align, unsigned long *obj);
1168 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1169 unsigned long obj, int cnt,
1172 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1173 struct ib_udata *udata);
1174 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1175 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1180 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1181 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1183 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1184 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1185 u64 virt_addr, int access_flags,
1186 struct ib_udata *udata);
1187 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1188 u64 length, u64 virt_addr,
1189 int mr_access_flags, struct ib_pd *pd,
1190 struct ib_udata *udata);
1191 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1193 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1194 unsigned int *sg_offset);
1195 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1196 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1197 struct hns_roce_cmd_mailbox *mailbox,
1198 unsigned long mpt_index);
1199 unsigned long key_to_hw_index(u32 key);
1201 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1202 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1204 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1205 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1206 u32 page_shift, u32 flags);
1208 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1209 int buf_cnt, int start, struct hns_roce_buf *buf);
1210 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1211 int buf_cnt, int start, struct ib_umem *umem,
1212 unsigned int page_shift);
1214 int hns_roce_create_srq(struct ib_srq *srq,
1215 struct ib_srq_init_attr *srq_init_attr,
1216 struct ib_udata *udata);
1217 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1218 enum ib_srq_attr_mask srq_attr_mask,
1219 struct ib_udata *udata);
1220 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1222 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1223 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1225 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1226 struct ib_qp_init_attr *init_attr,
1227 struct ib_udata *udata);
1228 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1229 int attr_mask, struct ib_udata *udata);
1230 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1231 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1232 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1233 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1234 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1235 struct ib_cq *ib_cq);
1236 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1237 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1238 struct hns_roce_cq *recv_cq);
1239 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1240 struct hns_roce_cq *recv_cq);
1241 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1242 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1243 struct ib_udata *udata);
1244 __be32 send_ieth(const struct ib_send_wr *wr);
1245 int to_hr_qp_type(int qp_type);
1247 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1248 struct ib_udata *udata);
1250 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1251 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1252 struct ib_udata *udata, unsigned long virt,
1253 struct hns_roce_db *db);
1254 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1255 struct hns_roce_db *db);
1256 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1258 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1260 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1261 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1262 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1263 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1264 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1265 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1266 int hns_roce_init(struct hns_roce_dev *hr_dev);
1267 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1268 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1269 struct ib_cq *ib_cq);
1270 #endif /* _HNS_ROCE_DEVICE_H */